CYPRESS CY7C1339F Manual
Contents
1. 22 23 24 P1 K2 L2 25 28 29 M2 N2 Vop J2 J4 R4 15 41 65 Power Supply Power supply inputs to the core of the device 91 Vss D3 E3 F3 17 40 67 Ground Ground for the core of the device K3 M3 N3 90 P3 D5 E5 F5 H5 K5 M5 N5 P5 Vppa A1 F1 J1 4 11 20 1 0 Power Power supply for the I O circuitry M1 U1 A7 27 54 61 Supply F7 J7 M7 70 77 U7 Vsso 5 10 21 I O Ground Ground for the I O circuitry 26 55 60 71 76 MODE R3 31 Input Selects Burst Order When tied to GND selects linear burst sequence Static When tied to Vpp or left floating selects interleaved burst sequence This is a strap pin and should remain static during device operation Mode Pin has an internal pull up Document 38 05217 Rev C Page 4 of 17 I P CYPRESS Pin Definitions continued CY7C1339F Name BGA TQFP yo Description NC B1 C1 R1 1 14 16 No Connects Not internally connected to the die T1 D2 P2 30 38 39 T2 U2 J3 42 43 51 U3 D4 L4 66 80 U4 J5 U5 B6 D6 P6 T6 U6 B7 C7 R5 R7 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output registers controlled by the rising edge of the clock Maximum access delay from the clock rise tco is 3 5 ns 166 MHz device The CY7C1339F supports secondary cache in systems utilizing either a l2. jc Thermal Resistance measuring thermal impedance per 9 99 11 71 C W Junction to Case EIA JESD51 Capacitance TQFP BGA Parameter Description Test Conditions Package Package Unit Cin Input Capacitance TA 25 C f 1 MHz 5 5 pF Cei k Clock Input Capacitance yoo Ee 5 5 pF Cio Input Output Capacitance eee 5 7 pF AC Test Loads and Waveforms 3 3V I O Test Load 3 3V R 3170 OUTPUT ALL INPUT PULSES OUTPUT R 500 5pF L INCLUDING ii E Mp my JIGAND LL SCOPE 7 E 6 c b R 16670 2 5V ALL INPUT PULSES OUTPUT R 500 5pF L R 215380 Vy 1 25V INCLUDING E JIG AND c e scope 5 Note 11 Tested initially and after any design or process change that may affect these parameters Document 38 05217 Rev C Page 9 of 17 ll V i 7 CYPRESS C CY7C1339F Switching haracteristics Over the Operating Rangel 171 250 MHz 225 MHz 200 MHz 166 MHz 133 MHz 100 MHz Parameter Description Min Max Min Max Min Max Min Max Min Max Min Max Unit tPOWER Vpp Typical to the first Accessi T7 4 1 1 1 1 1 ms Clock teve Clock Cycle Time 4 0 4 4 5 0 6 0 7 5 10 ns tcu Clock HIGH 1 7 2 0 2 0 2 5 3 0 3 5 ns teL Clock LOW 1 7 2 0 2 0 2 5 3 0 3 5 ns Output Times tco Data Output Valid After CLK Rise 2 6 2 6 2 8 3 5 4 0 4 5 ns tpou Data Output Hold After CLK Rise 1 0 1 0 1 0
3. 19 Full width write can be initiated by either GW LOW or by GW HIGH BWE LOW and BW p LOW Document 38 05217 Rev C Page 11 of 17 CY7C1339F ipe Z CYPRESS Switching Waveforms continued uie dictado hr hg a a TO O_O WW X Ww v U Pus UNE wow ZZ E mnc s XI 2777 VEA s m crx un i i MI y UL n A D Va y 7 Ur CUZ ud ur Vi www a7 wk ln TID Emm Tl ZI m 7 y uu Zu ML V A Lr Le Rise nds bur amm aa OE tps DH paa jaan Mes DAD NM D A2 yi DIAZ 1 yen 42 41 won VE 4243 WE DIA3 en D Xs 0342 X Data Out Q J Extended BURST WRITE M E BURST READ ex Single WRITE EN BURST WRITE DON T CARE RA UNDEFINED Document 38 05217 Rev C Page 12 of 17 CYPRESS Switching Waveforms continued Read Write Cycle Timing 20 21 tec 4 CY7C1339F sum t eg FA AS E taps DH lt gt 0D EE CO e Ne soa CU wk momo Lh Hii toes tceH fk Nn Wh HUN 7g 7 TT ADV i tco tos toH dl lt gt a lt gt tOELZ Data In D High Z D A3 N DAS j Dae ja taz osz a lt _ A A OTIIA aowa noz A n AQ oun REA ane JL onen onea ones lt Back to Bac
4. DQc Vss GW Vss DQg DQg J VDDQ Vpp NC Vpp NC VDD VDDQ K DQp DQp Vss CLK Vss DQA DQA L DQp DQp BWp NC BW DQ DQa M Vppa DQp Vss BWE Vss DQ Vooo N DQp DQp Vss A1 Vss DQA DQA P DQp NC Vss A0 Vss NC DQA R NC A MODE Vop NC A NC T NC NC A A A NC ZZ U VDDQ NC NC NC NC NC VDDQ Pin Definitions Name BGA TQFP y o Description Ao Ay A P4 N4 37 36 Input Address Inputs used to select one of the 128K address locations A2 C2 R2 32 33 34 Synchronous Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW A3 B3 C3 35 44 45 and CE4 CE3 and CE3 are sampled active A1 AO are fed to the two bit T3 T4 A5 46 47 48 counter B5 C5 T5 49 50 81 A6 C6 R6 82 99 100 BWABWg L5 65 63 93 94 95 Input Byte Write Select Inputs active LOW Qualified with BWE to conduct Wy IA L3 96 Synchronous byte writes to the SRAM Sampled on the rising edge of CLK BWc BWp GW H4 88 Input Global Write Enable Input active LOW When asserted LOW on the Synchronous rising edge of CLK a global write is conducted ALL bytes are written regardless of the values on BWa p and BWE BWE M4 87 Input Byte Write Enable Input active LOW Sampled on the rising edge of Synchronous CLK This signal must be asserted LOW to conduct a byte write CLK K4 89 Input Clock Input Used to capture all synchronous inputs to the device Also Clock used to increment the burst counter when ADV is asserted LOW during a burst operation CE E4 98 Input Chip Enable
5. Isp2 Automatic CE Vpp Max Device Deselected All speeds 40 mA Power down Vin lt 0 3V or Vin Vopa 0 3V Current CMOS Inputs f 0 Shaded area contains advanced information Notes 9 Overshoot V y AC lt Vpp 1 5V Pulse width less than tcyc 2 undershoot Vi AC gt 2V Pulse width less than tcy 2 10 TPower up Assumes a linear ramp from Ov to Vpp min within 200ms During this time Vi lt Vpp and Vppq lt Vpp Document 38 05217 Rev C Page 8 of 17 Electrical Characteristics Over the Operating Range continued 19 CY7C1339F Parameter Description Test Conditions Min Max Unit Isp3 Automatic CE Vpp Max Device Deselected or 4 ns cycle 250 MHz 105 mA Power down Vin lt 0 3V or Vin gt Vopa 0 3V 7 Current CMOS Inputs f fyax eve ENS 109 mA 5 ns cycle 200 MHz 95 mA 6 ns cycle 166 MHz 85 mA 7 5 ns cycle 133 MHz 75 mA 10 ns cycle 100 MHz 65 mA Isp4 Automatic CE Vpp Max Device Deselected All Speeds 45 mA Power down Vin gt Vin or Vin lt Vi f 20 Current TTL Inputs Shaded areas contain advance information Thermal Resistance TQFP BGA Parameter Description Test Conditions Package Package Unit Oj Thermal Resistance Test conditions follow standard test 41 83 47 63 C W Junction to Ambient methods and procedures for
6. i BW 4 BYTE 2 i y D TIH waerea WRITE DRIVER DQ gt are Bwa BYTE H Z BWE ID D jJ WRITE REGISTER ED t WHITE DRIVER NN A INPUT Gw REGISTERS CE ENABLE PIPELINED CE2 Romie ENABLE s cu CES OE zz SLEEP CONTROL Note 1 For best practices recommendations please refer to the Cypress application note System Design Guidelines on www cypress com Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408 943 2600 Document 38 05217 Rev C Revised April 09 2004 Zz CYPRESS CY7C1339F Selection Guide 250 MHz 225 MHz 200 MHz 166 MHz 133 MHz 100 MHz Unit Maximum Access Time 2 6 2 6 2 8 3 5 4 0 4 5 ns Maximum Operating Current 325 290 265 240 225 205 mA Maximum CMOS Standby Current 40 40 40 40 40 40 mA Shaded areas contain advanced information Please contact your local Cypress sales representative for availability of these parts Pin Configurations O a n aoma Lu iu dEEEE S25 E w Bg ClO Olmimimimio gt OonOimioi li i lt lt 3 Oo oo r O sr CO CN Q O O00 r Qo 0 st CN EN Tr
7. 00 0 O00 Oo O cO cO c cO cO cO NC 1 80 NC 77 DQc 2 79 DQg DQc 3 78 DQg VDDQ 4 77 Vppa Vssa 5 76 ssQ DQc 6 75 DQg BYTE C DQc 7 74 DQg BYTEB DQc 8 73 DQg DQc 9 72 DQg Vssa 10 71 Vssa Vppa 11 70 Vppa DQc 12 69 DQg L Mns 13 68 DQg 14 67 V El 15 100 pin TQFP 66 No NC 16 CY7C1339F 65 Vop Vss 17 64 ZZ DQp 18 63 DQa DQp 19 62 DQa VDDQ 20 61 VDDQ Vssa 21 60 ssa DQp 22 59 DQa DQp 23 58 DQa BYTE D DQp 24 57 DQA BYTEA DQp 25 56 DQa Vssa 26 55 Vssa Vppa 27 54 VDDQ DQp 28 53 DQa DQp 29 52 DQ NC 30 51 NC TN CO sb orm 00 O N cO sf 10 CO F OQO co cO c0 c mmo cO SEO SE SB SB SB SB SB vb Te lt lt lt w lt lt lt lt goo 22 lt lt lt lt O Document 38 05217 Rev C Page 2 of 17 i a CY7C1339F CYPRESS Pin Configurations continued 119 ball BGA CY7C1339F 128K x 32 2 3 4 5 6 7 B NC CE gt A ADSC A NC NC Cc NC A A Vpp A A NC D DQc NC Vss NC Vss NC DQg E DQc DQc Vss CE Vss DQg DQg F VDDQ DQc Vss OE Vss DQg VDDQ G DQc DQc BW ADV BWg DQg DQg H DQc
8. 1 Input active LOW Sampled on the rising edge of CLK 1 Synchronous Used in conjunction with CE and CE to select deselect the device ADSP is ignored if CE is HIGH CE2 B2 97 Input Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Synchronous Used in conjunction with CE and CE3 to select deselect the device Document 38 05217 Rev C Page 3 of 17 I P CYPRESS Pin Definitions continued CY7C1339F Name BGA TQFP y o Description CEz 92 Input Chip Enable 3 Input active LOW Sampled on the rising edge of CLK Synchronous Used in conjunction with CE and CE to select deselectthe device Not connected for BGA Where referenced CEz is assumed active throughout this document for BGA OE F4 86 Input Output Enable asynchronous input active LOW Controls the Asynchronous direction of the I O pins When LOW the I O pins behave as outputs When deasserted HIGH I O pins are three stated and act as input data pins OE is masked during the first clock of a read cycle when emerging from a deselected state ADV G4 83 Input Advance Input signal sampled on the rising edge of CLK active Synchronous LOW When asserted it automatically increments the address in a burst cycle ADSP A4 84 Input Address Strobe from Processor sampled on the rising edge of Synchronous CLK active LO
9. 2 0 2 0 2 0 ns terz Clock to Low Z119 gt 14 15 0 0 0 0 0 0 ns tcuz Clock to High Z113 14 15 2 6 2 6 2 8 3 5 4 0 4 5 ns toev OE LOW to Output Valid 2 6 2 6 2 8 3 5 45 45 ns toeLz OE LOW to Output Low Z 13 14 15 0 0 0 0 0 ns toEuz OE HIGH to Output High ZL T9 2 6 2 6 2 8 3 5 4 0 4 5 ns Set up Times tas Address Set up Before CLK Rise 0 8 1 2 1 2 1 5 1 5 1 5 ns taps ADSC ADSP Set up Before CLK 0 8 1 2 1 2 1 5 1 5 1 5 ns Rise tapvs ADV Set up Before CLK Rise 0 8 1 2 1 2 1 5 1 5 1 5 ns twes GW BWE BW D Set up Before 0 8 1 2 1 2 1 5 1 5 1 5 ns CLK Rise tos Data Input Set up Before CLK Rise 0 8 1 2 1 2 1 5 1 5 1 5 ns tces Chip Enable Set Up Before CLK 0 8 1 2 1 2 1 5 1 5 1 5 ns Rise Hold Times tan Address Hold After CLK Rise 0 4 0 5 0 5 0 5 0 5 0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 4 0 5 0 5 0 5 0 5 0 5 ns taDVH ADV Hold After CLK Rise 0 4 0 5 0 5 0 5 0 5 0 5 ns twEH GW BWE BWia D Hold After CLK 0 4 0 5 0 5 0 5 0 5 0 5 ns Rise toH Data Input Hold After CLK Rise 0 4 0 5 0 5 0 5 0 5 0 5 ns tcEH Chip Enable Hold After CLK Rise 0 4 0 5 0 5 0 5 0 5 0 5 ns Shaded areas contain advance information Notes 12 This part has a voltage regulator internally tpoyygg is the time that the power needs to be supplied above Vpp minimum initially before a read or write operation can be initiated 13 toyz teLztoeLz and togpz are specified with AC test conditions shown in pa
10. 2538 CY 7C 1339F 100A CEM R nn _ AS y CY7C1339F 4 Mbit 128K x 32 Pipelined Sync SRAM Features Functional Description Registered inputs and outputs for pipelined operation The CY7C1339F SRAM integrates 131 072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two bit counter for internal burst operation All synchronous inputs are 3 3V core power supply gated by registers controlled by a positive edge triggered 2 5V 3 3V I O operation Clock Input CLK The synchronous inputs include all addresses all data inputs address pipelining Chip Enable 128K x 32 common I O architecture Fast clock to output times CE depth expansion Chip Enables CE and CE Burst 2 6 ns for 250 MHz device Control inputs ADSC ADSP and ADV Write Enables T BW and BWE and Global Write GW Asynchronous 2 0 ns for 225 MHZ device inpuls clude the Output Enable OE and the ZZ pin eens for ticas device Addresses and chip enables are registered at rising edge of 3 5 ns for 166 MHz device clock when either Address Strobe Processor ADSP or 4 0 ns for 133 MHz device lig cede lia ADS are Md parando 4 5 ns for 100 MHz device urst addresses can be internally generated as controlled by the Advance pin ADV Provide high performance 3 1 1 1 access rate Address data inputs and write controls are registered on chip User selectable burst counter sup
11. L H three state Deselect Cycle Power down None L X H L L X X X X L H three state Deselect Cycle Power down None L L X L H L X X X L H three state Deselect Cycle Power down None L X H L H L X X X L H three state Snooze Mode Power down None X X X H X X X X X X three state READ Cycle Begin Burst External L H L L L X X X L L H Q READ Cycle Begin Burst External L H L L L X X X H L H three state WRITE Cycle Begin Burst External L H L L H L X L X L H D READ Cycle Begin Burst External L H L L H L X H L L H Q READ Cycle Begin Burst External L H L L H L X H H L H three state READ Cycle Continue Burst Next X X X L H H L H L L H Q Notes 2 X Don t Care H Logic HIGH L Logic LOW 3 WRITE L when any one or more Byte Write enable signals BWA BWg BWc BWp and BWE L or GW L WRITE H when all Byte write enable signals BW BW BWc BWp BWE GW H OUA The DQ pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock CE CE and CE3 are available only in the TQFP package BGA package has only 2 chip selects CE and CE The SRAM always initiates a read cycle when ADSP is asserted regardless of the state of GW BWE or BWia a pj Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC As a result OE must be driven HIGH prior to the start of the
12. W When asserted LOW addresses presented to the device are captured in the address registers A1 AO are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ASDP is ignored when CE is deasserted HIGH ADSC B4 85 Input Address Strobe from Controller sampled on the rising edge of Synchronous CLK active LOW When asserted LOW addresses presented to the device are captured in the address registers A1 AO are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ZZ T7 64 Input ZZ sleep Input active HIGH When asserted HIGH places the device Asynchronous in a non time critical sleep condition with data integrity preserved For normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down DQs K6 L6 M6 52 53 56 I O Bidirectional Data I O lines As inputs they feed into an on chip data N6 K7 L7 57 58 59 Synchronous register that is triggered by the rising edge of CLK As outputs they N7 P7 E6 62 63 68 deliver the data contained in the memory location specified by the F6 G6 H6 69 72 73 addresses presented during the previous clock rise of the read cycle D7 E7 G7 74 75 78 The direction of the pins is controlled by OE When OE is asserted LOW H7 D1 E1 79 2 3 6 the pins behave as outputs When HIGH DQs are placed in a three state G1 H1 E2 7 8 9 12 condition F2 G2 H2 13 18 19 K1 L1 N1
13. Write Function GW BWE BWp BWc BWg BWA Read H H X X X X Read H L H H H H Write Byte A DQA H L H H H L Write Byte B DQg H L H H L H Write Bytes B A H L H H L L Write Byte C DQc H L H L H H Write Bytes C A H L H L H L Write Bytes C B H L H L L H Write Bytes C B A H L H L L L Write Byte D DQp H L L H H H Write Bytes D A H L L H H L Write Bytes D B H L L H L H Write Bytes D B A H L L H L L Write Bytes D C H L L L H H Write Bytes D C A H L L L H L Write Bytes D C B H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Notes TN 8 Table only lists a partial listing of the byte write combinations Any combination of BW pjis valid Appropriate write will be done based on which byte write is active Document 38 05217 Rev C Page 7 of 17 Z CYPRESS CY7C1339F Maximum Ratings Current into Outputs LOW sss 20 mA Above which the useful life may be impaired For user guide eM Toca MOL UIS LPR ee fg SL Tee SEO V lines not tested attend _65C to 150 C Latch up Current 2200 mA Ambient Temperature with Operating Range Power Applied esses 55 C to 125 C Ambient Supply Voltage on Vpp Relative to GND 0 5V to 4 6V Range Temperature Vop VDDQ DC Voltage Applied to Outputs Co
14. e memory array If GW is HIGH then the Write operation is controlled by BWE and BWa pj signals The CY7C1339F provides Byte Write capability that is described in the Write Cycle Descriptions table Asserting the Byte Write Enable input BWE with the selected Byte Write BWiA pj input will selectively write to only the desired bytes Bytes not selected during a Byte Write operation will remain unaltered A synchronous self timed Write mechanism has been provided to simplify the Write operations Because the CY7C1339F is a common I O device the Output Enable OE must be deserted HIGH before presenting data to the DQs inputs Doing so will three state the output drivers As a safety precaution DQs are automatically three stated whenever a Write cycle is detected regardless of the state of OE Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following condi tions are satisfied 1 ADSC is asserted LOW 2 ADSP is deserted HIGH 3 CE4 CE CE are all asserted active and 4 the appropriate combination of the Write inputs GW BWE and BWra pj are asserted active to conduct a Write to the desired byte s ADSC triggered Write accesses require a single clock cycle to complete The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array The ADV input is ignored during this cycle If a global Write is conducted the data pr
15. ent logic and the Address Register while being presented to the memory array The corresponding data is allowed to propagate to the input of the Output Registers At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 3 5 ns 166 MHz device if OE is active LOW The only exception occurs when the SRAM is emerging from a deselected state to a selected state its outputs are always three stated during the first cycle of the access After the first cycle of the access the outputs are controlled by the OE signal Consecutive single Read cycles are supported Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals its output will three state immediately Document 38 05217 Rev C Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise 1 ADSP is asserted LOW and 2 CE CE2 CEz are all asserted active The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array The Write signals GW BWE and BWryA pj and ADV inputs are ignored during this first cycle ADSP triggered Write accesses require two clock cycles to complete If GW is asserted LOW on the second clock rise the data presented to the DQs inputs is written into the corre sponding address location in th
16. esented to the DQs is written into the corresponding address location in the memory core If a Byte Write is conducted only the selected bytes are written Bytes not selected during a Byte Write operation will remain unaltered A synchronous self timed Write mechanism has been provided to simplify the Write operations Because the CY7C1339F is a common I O device the Output Enable OE must be deserted HIGH before presenting data to the DQs inputs Doing so will three state the output drivers As a safety precaution DQs are automatically three stated whenever a Write cycle is detected regardless of the state of OE Page 5 of 17 Y SP CYPRESS Burst rales The CY7C1339F provides a two bit wraparound counter fed by A1 AO that implements either an interleaved or linear burst CY7C1339F Interleaved Burst Address Table MODE Floating or Vpp sequence The interleaved burst sequence is designed specif AE Rae mus ONE ically to support Intel Pentium applications The linear burst ress ress ress ress sequence is designed to support processors that follow a A1 AO A1 AO A1 A0 A1 A0 linear burst sequence The burst sequence is user selectable 00 01 10 11 through the MODE input 01 00 11 10 Asserting ADV LOW at clock rise will automatically increment 10 11 00 01 the burst counter
17. ial CY7C1339F 200BGI BG119 119 ball BGA 14 x 22 x 2 4mm 166 CY7C1339F 166AC A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm Commercial CY7C1339F 166BGC BG119 119 ball BGA 14 x 22 x 2 4mm CY7C1339F 166Al A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm Industrial CY7C1339F 166BGI BG119 119 ball BGA 14 x 22 x 2 4mm 133 CY7C1339F 133AC A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm Commercial CY7C1339F 133BGC BG119 119 ball BGA 14 x 22 x 2 4mm CY7C1339F 133Al A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm Industrial CY7C1339F 133BGI BG119 119 ball BGA 14 x 22 x 2 4mm Notes 22 Device must be deselected when entering ZZ mode 23 DGs are in high Z when exiting ZZ sleep mode Document 38 05217 Rev C See Cycle Descriptions table for all possible signal conditions to deselect the device Page 14 of 17 CYPRE ss CY7C1339F Ordering Information continued Speed Package Operating MHz Ordering Code Name Package Type Range 100 CY7C1339F 100AC A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm Commercial CY7C1339F 100BGC BG119 119 ball BGA 14 x 22 x 2 4mm CY7C1339F 100AI A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm Industrial CY7C1339F 100BGI BG119 119 ball BGA 14 x 22 x 2 4mm Shaded areas contain advanced information Please contact your local Cypress sales representative for availability of these parts Package Diagrams 100
18. ife support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges pie 3 7j CYPRESS Document History Page CY7C1339F Document Title CY7C1339F 4 Mbit 128K x 32 Pipelined Sync SRAM Document Number 38 05217 Orig of REV ECN NO Issue Date Change Description of Change 119284 01 06 03 HGK New Data Sheet A 123850 01 18 03 AJH Added power up requirements to AC test loads and waveforms information B 200660 See ECN REF Final Data Sheet C 213342 See ECN VBL Update Ordering Info section unshade active parts 133Al amp BGI Document 38 05217 Rev C Page 17 of 17
19. inear or interleaved burst sequence The interleaved burst order supports Pentium and i486 processors The linear burst sequence is suited for processors that utilize a linear burst sequence The burst order is user selectable and is determined by sampling the MODE input Accesses can be initiated with either the Processor Address Strobe ADSP or the Controller Address Strobe ADSC Address advancement through the burst sequence is controlled by the ADV input A two bit on chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access Byte Write operations are qualified with the Byte Write Enable BWE and Byte Write Select BWia D inputs A Global Write Enable GW overrides all Byte Write inputs and writes data to all four bytes All writes are simplified with on chip synchronous self timed Write circuitry Three synchronous Chip Selects CE4 CE2 CE3 and an asynchronous Output Enable OE provide for easy bank selection and output three state control ADSP is ignored if CE is HIGH Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise 1 ADSP or ADSC is asserted LOW 2 CE CE CE3 are all asserted active and 3 the Write signals GW BWE are all deserted HIGH ADSP is ignored if CE4 is HIGH The address presented to the address inputs A is stored into the address advancem
20. k READs all Single WRITE lt BURST READ gt Back to Back WRITES W DON T CARE M UNDEFINED Note 20 The data bus Q remains in high Z following a WRITE cycle unless a new read access is initiated by ADSP or ADSC 21 GW is HIGH Document 38 05217 Rev C Page 13 of 17 d Y J CYPRESS Switching Waveforms continued ZZ Mode Timing 22 231 CY7C1339F AAA Pe Re a f ra ALL INPUTS except ZZ A DESELECT or READ Only DON T CARE Ordering Information Speed Package Operating MHz Ordering Code Name Package Type Range 250 CY7C1339F 250AC A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm Commercial CY7C1339F 250BGC BG119 119 ball BGA 14 x 22 x 2 4mm CY7C1339F 250Al A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm Industrial CY7C1339F 250BGI BG119 119 ball BGA 14 x 22 x 2 4mm 225 CY7C1339F 225AC A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm Commercial CY7C1339F 225BGC BG119 119 ball BGA 14 x 22 x 2 4mm CY7C1339F 225AI A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm Industrial CY7C1339F 225BGI BG119 119 ball BGA 14 x 22 x 2 4mm 200 CY7C1339F 200AC A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm Commercial CY7C1339F 200BGC BG119 119 ball BGA 14 x 22 x 2 4mm CY7C1339F 200Al A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm Industr
21. mmercial 0 C to 70 C 3 3V 5 10 2 5V 5 inthree state oan esareti 0 5V to Vppo 0 5V Industrial 40 C to 85 C to Vop DC Input Voltage coooocccnoccnnoccccnnoncccnnno 0 5V to Vpp 0 5V Electrical Characteristics Over the Operating Range 10 Parameter Description Test Conditions Min Max Unit Vop Power Supply Voltage 3 135 3 6 V Vppa 1 O Supply Voltage 2 375 Vpp V Vou Output HIGH Voltage Vppo 3 3V Vpp Min lop 4 0 mA 2 4 V Vppo 2 5V Vpp Min lop 1 0 mA 2 0 V VoL Output LOW Voltage Vppo 33V Vpp Min ly 8 0 mA 0 4 V Vppo 2 5V Vpp Min lp 1 0 mA 0 4 V Vin Input HIGH Voltage Vppo 3 3V 2 0 Vpp 0 3V V Vppo 2 5V 1 7 Vpp 0 3V V Vi Input LOW Voltage Vppo 3 3V 0 3 0 8 V Vppo 2 5V 0 3 0 7 V Ix Input Load Current GND lt Vi lt VDDQ 5 5 LA except ZZ and MODE Input Current of MODE Input Vss 30 LA Input Vpp 5 pA Input Current of ZZ Input Vss 5 uA Input Vpp 30 LA loz Output Leakage Current GND lt V lt Vppa Output Disabled 5 5 LA loo Vpp Operating Supply Vpp Max loyr 0 mA 4 ns cycle 250 MHz 325 mA Current f fmax Mteye 4 4 ns cycle 225 MHz 290 mA 5 ns cycle 200 MHz 265 mA 6 ns cycle 166 MHz 240 mA 7 5 ns cycle 133 MHz 225 mA 10 ns cycle 100 MHz 205 mA Isp4 Automatic CE Vpp Max Device Deselected 4 ns cycle 250 MHz 120 mA 5 ns cycle 200 MHz 110 mA 6 ns cycle 166 MHz 100 mA 7 5 ns cycle 133 MHz 90 mA 10 ns cycle 100 MHz 80 mA
22. pin Thin Plastic Quad Flatpack 14 x 20 x 1 4 mm A101 22 0010 20 20 0040 10 R 0 08 MIN 0 20 MAX GAUGE PLANE 0 WE 7 0 6020 15 1 00 REF Document 38 05217 Rev C 16 0020 20 14 00 0 10 R 0 08 MIN 0 20 MAX 0 20 MIN DETAIL DIMENSIONS ARE IN MILLIMETERS 1 4020 05 SEE DETAIL A 0 20 MAX 160 MAx SEATING PLANE 51 85050 A Page 15 of 17 CY7C1339F CYPRESS Package Diagrams continued 51 85115 B i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation PowerPC is a registered trademark of IBM Corporation All product and company names mentioned in this document may be trademarks of their respective holders Page 16 of 17 Cypress Semiconductor Corporation 2004 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use i Document 38 05217 Rev C of any circuitry other than circuitry embodied in a Cypress Semiconductor product Nor does it convey or imply any license under patent or other rights Cypress Semiconductor does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress i Semiconductor products in l
23. porting Intel to initiate a self timed Write cycle This part supports Byte Write Pentium interleaved or linear burst sequences operations see Pin Descriptions and Truth Table for further details Write cycles can be one to four bytes wide as controlled by the byte write control inputs Gy when active Separate processor and controller address strobes Synchronous self timed writes LOW causes all bytes to be written Asynchronous output enable The CY7C1339F operates from a 3 3V core power supply Offered in JEDEC standard 100 pin TQFP and 119 ball while all outputs may operate with either a 2 5 or 3 3V BGA packages supply All inputs and outputs are JEDEC standard JESD8 5 compatible ZZ Sleep Mode Option AQ Al A ADDRESS REGISTER x Irae MODE ADV Y ak BURST COUNTER R AND Q LOGIC ADSC ADSP DOs Dor aw BYTE Ley BYTE ap D Fd WRITE REGISTER WAITE DRIVER Dd DO BWc BYTE i BYTE y d WRITE REGISTER gt WRITE DRIVER MEMORY T OUTPUT OUTPUT da Tr ARRAY SS REGISTERS BUFFERS D s DQs 4 DOs t BWe BYTE
24. rt b of AC Test Loads Transition is measured 200 mV from steady state voltage 14 At any given voltage and temperature togpz is less than tog 7 and tcyz is less than tc z to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 15 This parameter is sampled and not 100 tested 16 Timing reference level is 1 5V when Vppq 3 3V and is 1 25V when Vppq 2 5V 17 Test conditions shown in a of AC Test Loads unless otherwise noted Document 38 05217 Rev C Page 10 of 17 F CYPRESS CY7C1339F Switching Waveforms Read Cycle Timing l PEEP APPR PAP TWh Y OT TWN E I Ins We CL zm MIL Zi a MLL comes wow WWW WW TU ILLU Wh e LLL lil ovs ADVH C UT TD A D STITT iv WL l Bones on jn ee OE l l T l T l T l l l l l l l l l l l toyz l l taz T rud DE mPp A Q2 Q A2 X Q A2 3 XX Q A2 XX Q A2 1 Data Out Q BURST READ V DON T CARE Ra UNDEFINED Notes 18 On this diagram nanen Pa LOW CE is LOW CE is HIGH and CE is s LOW When CE is HIGH CE is HIGH or CE is LOW or CE is HIGH
25. to the next address in the burst sequence Both Read and Write burst operations are supported 11 10 01 00 Sleep Mode Linear Burst Address Table MODE GND The ZZ input pin is an asynchronous input Asserting ZZ First Second Third Fourth places the SRAM in a power conservation sleep mode Two Address Address Address Address clock cycles are required to enter into or exit from this sleep A1 A0 A1 A0 A1 A0 A1 A0 mode While in this mode data integrity is guaranteed a 00 01 10 11 Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation 01 10 11 00 guaranteed The device must be deselected prior to entering 10 11 00 01 the sleep mode CE4 CE CE3 ADSP and ADSC must 11 00 01 10 remain inactive for the duration of tzzggc after the ZZ input returns LOW ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Snooze mode standby current ZZ gt Vpp 0 2V 40 mA tzzs Device operation to ZZ ZZ gt Vpp 0 2V 2tcvc ns tzzREC ZZ recovery time ZZ lt 0 2V 2tcyc ns tzzi ZZ active to snooze current This parameter is sampled 2tcvc ns trzzI ZZ Inactive to exit snooze current This parameter is sampled 0 ns Truth Table 2 3 4 5 6 7 Operation Add Used CE CE CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle Power down None H X X L X L X X X L H three state Deselect Cycle Power down None L L X L L X X X X
26. write cycle to allow the outputs to three state OE is a don t care for the remainder of the write cycle 7 OE is asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle all data bits are three state when OE IS inactive or when the device is deselected and all data bits behave as output when OE is active LOW Document 38 05217 Rev C Page 6 of 17 p Z CYPRESS CY7C1339F Truth Table 3 4 5 6 7 Operation Add Used CE CE CE3 ZZ ADSP ADSC ADV WRITE o CLK DQ READ Cycle Continue Burst Next X X X L H H L H H L H three state READ Cycle Continue Burst Next H X X L X H L H L L H Q READ Cycle Continue Burst Next H X X L X H L H H L H three state WRITE Cycle Continue Burst Next X X X L H H L L X L H D WRITE Cycle Continue Burst Next H X X L X H L L X L H D READ Cycle Suspend Burst Current X X X L H H H H L L H Q READ Cycle Suspend Burst Current X X X L H H H H H L H three state READ Cycle Suspend Burst Current H X X L X H H H L L H Q READ Cycle Suspend Burst Current H X X L X H H H H L H three state WRITE Cycle Suspend Burst Current X X X L H H H L X L H D WRITE Cycle Suspend Burst Current H X X L X H H L X L H D Partial Truth Table for Read
Download Pdf Manuals
Related Search
CYPRESS CY7C1339F Manual