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Intel StrataFlash Embedded Memory (P30) handbook

1. Order Number 306666 Revision 001 1 Gbit P30 Family Figure 23 Asynchronous Read to Write Timing R1 gt R2 gt W5 W8 gt Address A SEK X le R3 gt K R8 CE E TN R4 4 R9 OE G N Work w3 W6 WE M K R15 RIT WAIT T R7 gt W7 R6 gt R10 Ie n gt Data D Q D Q aD D k R5 gt RST P Note WAIT deasserted during asynchronous read and during write WAIT High Z during write per OE deasserted Figure 24 Write to Asynchronous Read Timing k WS ole W8 R1 gt Address A IK J zk ADVE V w2 y W6 gt R10 CE amp E i W3 me W18 WE M W14 OE G usa ENA WAIT T ie R2 R8 K WA k NT le R3 Pn Data D Q Q a W1 RST P Datasheet Intel StrataFlash Embedded Memory P30 April 2005 43 1 Gbit P30 Family l n Figure 25 Synchronous Read to Write Timing l l Latency Count i CLK C gt W5 gt i gt W18 le Address A e gt R104 fe ADV V i f N N 1 l R303 le 1 RU ke R3 gt As R13 gt ewe CE E f i R R4 4 gt l l gt R8 OE G w
2. R1 R2 A Max 2 A 1 0 TEE R101 les R105 R106 ADVE N R gt R8 CE E N I RA gt R10 OE G eue eme WAIT T V m R108 R9 DATA D Q LA am A am a Note WAIT shown deasserted during asynchronous read mode RCR 10 0 Wait asserted low Figure 19 Synchronous Single Word Array or Non array Read Timing i CLK C CE E R9 OE G f R307 HR312 R17 gt WAIT T gt R304 R305 l Data D Q I 1 WAIT is driven per OE assertion during synchronous array or non array read and can be configured to assert either during or one data cycle before valid data 2 This diagram illustrates the case in which an n word burst is initiated to the flash memory array and it is terminated by CE deassertion after the first word in the burst Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 39 1 Gbit P30 Family Figure 20 Continuous Burst Read showing an Output Delay Timing R301 l M R302 1 f f f f i i i gt R306 l i le R304 leR304 gt 1 gt R304 ke cK c xe we xu b R2 gt l R101 1 Address A E Sa SRI Kx R105 de MEN n EE EE ET AE EN EE R303 l R102 i R3 CE E jj 1 OE G i jy po d D i RISk R307 gt R312 WA
3. l n o 1 Gbit P30 Family 7 5 Program and Erase Characteristics V V Num Symbol Parameter iie di Units Notes Min Typ Max Min Typ Max Conventional Word Programming Program Single word 90 200 85 190 W200 t h 1 PROGW Time Single cell gt 30 60 30 60 Buffered Programming W200 tprocw Program Single word 90 200 85 190 1 W251 tgucr Time 32 word buffer 440 880 340 680 d Buffered Enhanced Factory Programming W451 tgerppw Single word n a n a n a 10 1 2 was2 serp Program fee Setup na nia na 5 Joa Setup Erasing and Suspending W500 t f ERSIPB rase Time 32 KByte cae 0 4 2 5 0 4 2 5 s W501 teERs MB 128 KByte Main 1 2 4 0 1 0 4 0 1 W600 tsuspyp Suspend Program suspend 20 25 20 25 W601 tsusp yg Latency Erase suspend 20 25 20 25 H Notes 1 Typical values measured at Tc 25 C and nominal voltages Performance numbers are valid for all speed versions Excludes system overhead Sampled but not 10096 tested 2 Averaged over entire device Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 45 1 Gbit P30 Family I n 3 0 Power and Reset Specifications 8 1 8 2 April 2005 46 Power Up and Down Power supply sequencing is not required if VCC VCCQ and VPP are connected together If VCCQ and or VPP are not connected to the VCC supply then
4. PrVendor ID 4 ID The Query command causes the flash component to display the Common Flash Interface CFT Query structure or database The structure sub sections and address locations are summarized below Query Structure Offset Sub Section Name 00001 Fh Reserved for vendor specific information 00010h CFI query identification string Command set ID and vendor data offset OOO1Bh System interface information Device timing amp voltage information 00027h Device geometry definition p5 Pira Notes 1 2 3 Flash device layout Intel specific Extended Query Table Vendor defined additional information specific Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode BA Block Address beginning location i e 08000h is block 1 s beginning location when the block size is 16 KWord Offset 15 defines P which points to the Primary Intel specific Extended Query Table Intel StrataFlash Embedded Memory P30 Order Number 306666 Revision 001 Datasheet Table 34 Table 35 Datasheet CFI Query Identification String 1 Gbit P30 Family The Identification String provides verification that the component supports the Common Flash Interface specification It also indicates the specification version and supported vendor specified command set s CFI Identification COCO Query unique
5. Full Erase Status Check if desired 0 Block Erase Successful BLOCK ERASE PROCEDURE Bus Block Data 0x20 Frase Addr Block to be erased BA Setup Block Erase Writ Erase Data OxDO Te Confirm Addr Block to be erased BA Erase Confirm Status Register data Suspend Check SR 7 None 1 WSM ready 0 WSM busy Repeat for subsequent block erasures Full Status register check can be done after each block erase or after a sequence of block erasures Write OxFF after the last operation to enter read array mode FULL ERASE STATUS CHECK PROCEDURE Operation None Check SR 3 1 Vpp Range Error None Check SR 4 5 Both 1 Command Sequence Error Sequence Erro one Ja Block Erase Error Block Erase Error Block Locked Error Check SR 1 None 1 Attempted erase of locked block erase aborted Only the Clear Status Register command clears SR 1 3 4 5 If an error is detected clear the Status register before attempting an erase retry or other error recovery Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 89 1 Gbit P30 Family Figure 45 Erase Suspend Resume Flowchart ERASE SUSPEND RESUME PROCEDURE Data 0x70 Read Status Addr Any partition address Fras Data OxBO Erase Suspend Suspend cue Same partition address as Status Register data Addr Same partition Check SR 7 1
6. Execute in Place XIP is defined as the ability to execute code directly from the flash memory XIP applications must partition the memory such that code and data are in separate programming regions see Table 26 Programming Regions per Device on page 61 Each Programming Region should contain only code or data and not both The following terms define the difference between code and data System designs must use these definitions when partitioning their code and data for the P30 device Code Execution code ran out of the flash device on a continuous basis in the system Data Information periodically programmed into the flash device and read back e g execution code shadowed and executed in RAM pictures log files etc Word Programming Word programming operations are initiated by writing the Word Program Setup command to the device see Section 9 0 Device Operations on page 48 This is followed by a second write to the device with the address and data to be programmed The device outputs Status Register data when read See Figure 40 Word Program Flowchart on page 85 Vpp must be above Vpp x and within the specified Vppr min max values nominally 1 8 V Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 61 1 Gbit P30 Family ntel amp 11 1 1 Note 11 2 April 2005 62 During programming the Write State Machine WSM executes a sequence of internally timed events
7. 1 Gbit P30 Family Table 29 Device Identifier Information Item Address Data Manufacturer Code 0x00 0089h Device ID Code 0x01 ID see Table 30 Block Lock Configuration Lock Bit e Block Is Unlocked DQg ObO e Block Is Locked BBA 0x02 DO 0b1 e Block Is not Locked Down DQ ObO e Block Is Locked Down DQ 0b1 Configuration Register 0x05 Configuration Register Data Lock Register O 0x80 PR LKO 64 bit Factory Programmed Protection Register 0x81 0x84 Factory Protection Register Data 64 bit User Programmable Protection Register 0x85 0x88 User Protection Register Data Lock Register 1 0x89 Protection Register Data 128 bit User Programmable Protection Registers Ox8A 0x109 PR LK1 Notes 1 BBA Block Base Address Table 30 Device ID codes Device Identifier Codes ID Code Type Device Density x B Top Parameter Bottom Parameter 64 Mbit 8817 881A Device Code 128 Mbit 8818 881B 256 Mbit 8919 891C 14 3 CFI Query The CFI Query command instructs the device to output Common Flash Interface CFI data when read See Section 9 2 Device Commands on page 50 for details on issuing the CFI Query command Appendix C Common Flash Interface on page 93 shows CFI information and address offsets within the CFI database Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 77 1 Gbit P30 Family Intel Appendix A
8. April 2005 91 1 Gbit P30 Family Figure 47 April 2005 92 Protection Register Programming Flowchart Write OxCO PR Address Write PR Address amp Data Read Status Register m 1 Full Status Check if desired Program Complete Read Status Register Data 0 Program Successful PROTECTION REGISTER PROGRAMMING PROCEDURE Program Setup Confirm Data Bus Write Program Data OxCO PR Setup Addr First Location to Program Write Protection Data Data to Program Program Addr Location to Program Check SR 7 None 1 WSM Ready 0 WSM Busy Program Protection Register operation addresses must be within the Protection Register address space Addresses outside this space will return an error Repeat for subsequent programming operations Full Status Register check can be done after each program or after a sequence of program operations Write OxFF after the last operation to set Read Array state EULL STATUS CHECK PROCEDURE Vpp Range Error Program Error Register Locked Program Aborted Operation Nana Check SR 3 1 Vpp Range Error Check SR 4 REM 1 Programming Error N Check SR 1 one 1 Block locked operation aborted Only the Clear Staus Register command clears SR 1 3 4 If an error is detected clear the Status register before attempting a program retry or other error recovery Intel StrataFlash Embedde
9. VCC WE I VPP CLK K VCCQ ADV gt I4 VSS us Flash Die 2 256 Mbit A MAX 0 3 I DQ 15 0 t WAIT Figure 12 1 Gbit QUAD SCSP Device Block Diagram QUAD 4 Die 1 Gbit Device Configuration F1 CE I 9 i i F2 CE Flash Die 1 Flash Die 3 WP 256 Mbit 256 Mbit RST OE I4 VCC WE I VPP CLK I VCCQ ADV gt F8 VSS Flash Die 2 Flash Die 4 256 Mbit 256 Mbit A MAX 0 a gt DQ 15 0 m WAIT Datasheet Intel StrataFlash Embedded Memory P30 Order Number 306666 Revision 001 April 2005 1 Gbit P30 Family 4 4 Memory Maps Intel Table 7 through Table 10 show the P30 memory maps See Section 11 0 Programming Operations on page 61 for Programming Region information Table 7 Discrete Top Parameter Memory Maps all packages Ferd Bik 2s6 Mbi f Bi 12 amp Mbit N 32 258 FFC000 FFFFFF 130 7FC000 7FFFFF 3FC000 3FFFFF 32 255 FF0000 FF3FFF 127 7F0000 FF3FFF 3F0000 3F3FFF i 128 254 FE0000 FEFFFF f 126 7E0000 7EFFFF 3E0000 3EFFFF 128 240 F00000 FOF
10. When the device is deselected while CE is deasserted during a program or erase operation it continues to consume active power until the program or erase operation is completed 9 15 Reset As with any automated device it is important to assert RST when the system is reset When the system comes out of reset the system processor attempts to read from the flash memory if it is the system boot device If a CPU reset occurs with no flash memory reset improper CPU initialization may occur because the flash memory may be providing status information rather than array data Flash memory devices from Intel allow proper CPU initialization following a system reset through the use of the RST input RST should be controlled by the same low true reset signal that resets the system CPU After initial power up or reset the device defaults to asynchronous Read Array and the Status Register is set to 0x80 Asserting RST de energizes all internal circuits and places the output drivers in High Z When RST is asserted the device shuts down the operation in progress a process which takes a minimum amount of time to complete When RST has been deasserted the device is reset to asynchronous Read Array state Note If RST is asserted during a program or erase operation the operation is terminated and the memory contents at the aborted location for a program or block for an erase are no longer valid because the data may have been only partially wri
11. ettet ens etx ete tari ER darle RARE d rcg Re ERE be EES aude EE ek 35 7 4 AC Write Specifications cece ee ee aana aaa ia NE a aaa AA Naa a ee ee 41 7 5 Program and Erase CharacteristicS iii sis see see ee ee ee ee nennen 45 8 0 Power and Reset Specifications ie ee ee ee esses 46 81 Power Up arid eo RE RE EE EE EE 46 8 2 Reset Specifications certet net rk ars ae GE GEK AR RE AREA Rd ke b NERA EAR EUER e adaa 46 8 3 Power Supply Decoupling sesesseessssssssseseenee eene enne nennen ed nnne snnt nen nennen 47 90 i sedenriniuplcd E 48 91 Bus OperallOnS uu 48 EN OR EE OR EA EE a 48 QTD Vcr LEE 49 9 1 3 Output Disable RE Rr EE eR ede E RR OE EE EE 49 EE SE oa OR N 49 9 1 5 aa EE N RE N 49 92 Device Commands ase hn reete ei N RES ERG ER dex IR ER ER Ee e RAE X Gee ee EE 50 9 3 Command Nel ee AR EE EE RR aaa aiaa A Ri 51 Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 3 1 Gbit P30 Family ntel amp 10 0 Read Operations ose EE teo ba P p e o eae busto 53 10 1 Asynchronous Page Mode Read iii ee RR Re Re GR ee AR Re ee ee nne EEEE EEEE 53 10 2 Synchronous Burst Mode Read ee RA Ge ee ee ee Re Re Re ee ee ee nnne nnns 53 10 3 Read Configuration Register iese ee RR Re AR Ge ee ee ek ke Re ee ee nnne nnns 54 10 3 1 Read Mode
12. 306666 Revision 001 l n 1 Gbit P30 Family Figure 5 512 Mbit 88 ball 80 active QUAD SCSP Specifications 8x11x1 2 mm A1 Index r S1 a Mark 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 Y Vee oot B s OOOOOOOO c c OOOOOOOO D OOOOOOOO E E OOOOOOOO V F p OOOOOOOOQO G c OOOOOOOO 4 H oooooooo J 3 OOOOOOOO K K OOOOOOOO L t OOOOOOOO M M OO OO Y a bu Top View Ball Down Bottom View Ball Up i Al i I dd rcs M rae Y Drawing not to scale Dimensions O s 12 o20 0007 i 080 0 0339 i 0425 10 Package Body Thickness Ball Lead Width 0 425 Package Body Length o Corner to Ball A1 Distance Along D om 10 a ze 8 as 88 PT EER IE owof 1200 1300 0 0433 om 860 000 800 88 x 5 10 1 200 0 0472 10 ae GEE EE 0 0079 00339 n 9 x 1 3 Symbol 0 b 0325 D 10 900 e 0 0 Datasheet Intel StrataFlash Embedded Memory P30 Order Number 306666 Revision 001 April 2005 15 1 Gbit P30 Family Figure 6 1 Gbit 88 ball 80 active QUAD SCSP Specifications 11x11x1 4 mm A1 Index S1 m Mark P 1 2 8 7 6 5 4 3 24 Y x S2 A OO O Oo B s OOOOOOOO c c OOOO
13. 4 Sampled but not 10096 tested 5 If RST is tied to the Vcc supply device will not be ready until tccpu after Vcc Vecmin 6 If RST is tied to any supply signal with Vcco voltage levels the RST input voltage must not exceed Vcc until Vcc 2 VCCMIN Reset completes within tp py if RST is asserted while no erase or program operation is executing N Intel StrataFlash Embedded Memory P30 Datasheet Order Number 306666 Revision 001 j ntel o 1 Gbit P30 Family Figure 27 Reset Operation Waveforms A Reset during V RST P read mode P Complete B Reset during v program or block erase RST P P1 lt P2 C Reset during v program or block erase RST P P1 gt P2 D VCC Power up to RST high nid ov 8 3 Power Supply Decoupling Flash memory devices require careful power supply de coupling Three basic power supply current considerations are 1 standby current levels 2 active current levels and 3 transient peaks produced when CE and OE are asserted and deasserted When the device is accessed many internal conditions change Circuits within the device enable charge pumps and internal logic states change at high speed All of these internal activities produce transient signals Transient current magnitudes depend on the device outputs capacitive and inductive loading Two line control and correct de coupling capacitor selection suppress transient voltage peaks Because
14. AD V Low on page 38 Figure 17 Asynchronous Single Word Read ADV Latch on page 38 Figure 19 Synchronous Single Word Array or Non array Read Timing on page 39 Read Status Register To read the Status Register issue the Read Status Register command at any address Status Register information is available to which the Read Status Register Word Program or Block Erase command was issued Status Register data is automatically made available following a Word Program Block Erase or Block Lock command sequence Reads from the device after any of these command sequences outputs the device s status until another valid command is written e g Read Array command The Status Register is read using single asynchronous mode or synchronous burst mode reads Status Register data is output on DQ 7 0 while 0x00 is output on DQ 15 8 In asynchronous mode the falling edge of OE or CE whichever occurs first updates and latches the Status Register contents However reading the Status Register in synchronous burst mode CE or ADV must be toggled to update status data The Device Write Status bit SR 7 provides overall status of the device Status register bits SR 6 1 present status and error information about the program erase suspend Vpp and block locked operations Status Register Description Sheet 1 of 2 Status Register SR Default Value 0x80 Erase Program Block
15. Lead Tip Angle 2 0 3 5 0 3 5 Seating Plane Coplanarity Y 0 100 0 004 Lead to Package Offset Z 0 150 0 250 0 350 0 006 0 010 0 014 Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 11 1 Gbit P30 Family I n e 3 2 64 Ball Easy BGA Package Figure 2 Easy BGA Mechanical Specifications Ball A1 Ball A1 Corner Corner xl 8 7 6 5 4 3 OOOOOO B0 00000 cOOOOOO ve OOOOOO e OOOOOO EODOODOD cs OOOOOO OQOOOOO Top View Ball side down Bottom View Ball Side Up Note Drawing not to scale Table 2 Easy BGA Package Dimensions Millimeters Inches Product Information Symbol Notes Min Nom Max Min Nom Max Package Height 64 128 256 Mbit A 1 200 0 0472 Package Height 512 Mbit A 1 300 0 0512 Ball Height 64 128 256 Mbit A1 0 250 0 0098 Ball Height 512 Mbit A1 0 240 0 0094 Package Body Thickness 64 128 256 Mbit A2 0 780 0 0307 Package Body Thickness 512 Mbit A2 0 910 0 0358 Ball Lead Width b 0 330 0 430 0 530 0 0130 0 0169 0 0209 Package Body Width D 9 900 10 000 10 100 0 3898 0 3937 0 3976 1 Package Body Length E 12 900 13 000 13 100 0 5079 0 5118 0 5157 1 Pitch e 1 000 0 0394 Ball Lead Count N 64 64 E Seating Plane Coplanarity b 0 100 0 0039 Corner to Ball A1 Distance Al
16. absolute hardware erase protection is provided for all device blocks If Vpp is below Vppjy y erase operations halt and SR 3 is set indicating a Vpp level error Intel StrataFlash Embedded Memory P30 Datasheet Order Number 306666 Revision 001 Intel 13 0 1 Gbit P30 Family Security Modes 13 1 13 1 1 13 1 2 13 1 3 Datasheet The device features security modes used to protect the information stored in the flash memory array The following sections describe each security mode in detail Block Locking Individual instant block locking is used to protect user code and or data within the flash memory array All blocks power up in a locked state to protect array data from being altered during power transitions Any block can be locked or unlocked with no latency Locked blocks cannot be programmed or erased they can only be read Software controlled security is implemented using the Block Lock and Block Unlock commands Hardware controlled security can be implemented using the Block Lock Down command along with asserting WP Also V pp data security can be used to inhibit program and erase operations see Section 11 6 Program Protection on page 66 and Section 12 4 Erase Protection on page 68 The P30 device also offers four pre defined areas in the main array that can be configured as One Time Programmable OTP for the highest level of security These include the four 32 KB parameter blocks together as
17. loaded into the buffer BEFP Program Verify Phase After the BEFP Setup Phase has completed the host programming system must check SR 7 0 to determine the availability of the write buffer for data streaming SR 7 cleared indicates the device is busy and the BEFP program verify phase is activated SR 0 indicates the write buffer is available Intel StrataFlash Embedded Memory P30 Datasheet Order Number 306666 Revision 001 intel Caution Note 11 3 4 11 4 Datasheet 1 Gbit P30 Family Two basic sequences repeat in this phase loading of the write buffer followed by buffer data programming to the array For BEFP the count value for buffer loading is always the maximum buffer size of 32 words During the buffer loading sequence data is stored to sequential buffer locations starting at address 0x00 Programming of the buffer contents to the flash memory array starts as soon as the buffer is full If the number of words is less than 32 the remaining buffer locations must be filled with OxFFFF The buffer must be completely filled for programming to occur Supplying an address outside of the current block s range during a buffer fill sequence causes the algorithm to exit immediately Any data previously loaded into the buffer during the fill cycle is not programmed into the array The starting address for data entry must be buffer size aligned if not the BEFP algorithm will be aborted and the program fails and SR 4
18. ns gt One CLK Period ns data hold setting of 2 clock periods must be used Data Hold Timing 1CLK Data sd DISC oma ome IE oma Y 2 CLK l Data E D 15 0 Q CLK C April 2005 58 Intel StrataFlash Embedded Memory P30 Datasheet Order Number 306666 Revision 001 intel 10 3 5 10 3 6 Table 25 10 3 7 10 3 8 Datasheet 1 Gbit P30 Family WAIT Delay The WAIT Delay WD bit controls the WAIT assertion delay behavior during synchronous burst reads WAIT can be asserted either during or one data cycle before valid data is output on DQ 15 0 When WD is set WAIT is deasserted one data cycle before valid data default When WD is cleared WAIT is deasserted during valid data Burst Sequence The Burst Sequence BS bit selects linear burst sequence default Only linear burst sequence is supported Table 25 shows the synchronous burst sequence for all burst lengths as well as the effect of the Burst Wrap BW setting Burst Sequence Word Ordering Start Burst Addressing Sequence DEC Addr Burst Wrap DEC RCR 3 4 Word Burst 8 Word Burst 16 Word Burst Continuous Burst BL 2 0 0b001 BL 2 0 0b010 BL 2 0 0b011 BL 2 0 0b111 0 0 0 1 2 3 0 1 2 3 4 5 6 7 0 1 2 3 4 14 15 0 1 2 3 4 5 6 1 0 1 2 3 0 1 2 3 4 5 6 7 0 1 2 3 4 5 15 0 1 2 3 4 5 6 7 2
19. ns R102 tELVH CE low to ADV high 10 ns R103 tyov ADV low to output valid 85 ns 1 R104 tVLVH ADV pulse width low 10 ns R105 tyav ADV pulse width high 10 ns R106 tvHax Address hold from ADV high 9 ns 1 4 R108 tAPA Page address access 25 ns R111 tohvh RST high to ADV high 30 ns Clock Specifications R200 fork CLK frequency 40 MHz R201 teik CLK period 25 ns 1 3 6 R202 tone CLK high low time 5 ns R203 rci kiRCLK CLK fall rise time 3 ns Synchronous Specifications R301 TAVCHIL Address setup to CLK 9 ns R302 TVLCHIL ADV low setup to CLK 9 ns R303 te cu CE low setup to CLK 9 ns R304 touov torev CLK to output valid 20 ns Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 35 1 Gbit P30 Family Table 16 AC Read Specifications for 64 128 Mbit Densities Sheet 2 of 2 Num Symbol Parameter Min Max Unit Notes R305 tCHOX Output hold from CLK 3 ns 1 5 R306 TCHAX Address hold from CLK 10 ns 1 4 5 R307 toa CLK to WAIT valid 20 ns 1 5 R311 tonve CLK Valid to ADV Setup 3 ns 1 R312 teurx WAIT Hold from CLK 3 ns 1 5 NOTES 1 See Figure 13 AC Input Output Reference Waveform on page 33 for timing measurements and max allowable input slew rate 2 OE may be delayed by up to tg oy ta oy after CEZ s falling edge without impact to tg oy 3 Sampled not 100 tested 4 Address hold in synchrono
20. oc Erase Main Blocks Vpp VppH 1000 Cycles Cycles Parameter Blocks Vpp VpPH 2500 NOTES 1 Tc Case Temperature 2 Temperature for 1 Gbit SCSP is 30 C to 85 C 3 In typical operation the VPP program voltage is Vpp VPP can be connected to 8 5 V 9 5 V for 80 hours April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 30 Order Number 306666 Revision 001 l n 1 Gbit P30 Family 6 0 Electrical Specifications 6 1 DC Current Characteristics Table 12 DC Current Characteristics Sheet 1 of 2 CMOS Inputs TTL Inputs A Veco Sym Parameter 17V 26 v 2 4 V 3 6 V Unit Test Conditions Notes Typ Max Typ Max Vcc VccMax lii Input Load Current 1 2 HA Veco VccoMax Vin Veco or Vss i Output Vcc VccMax lo Leakage DQ 15 0 WAIT 1 10 HA Veco VccoMax Current Vin Veco or Vss 64 Mbit 20 35 20 35 Vcc VccMax 128 Mbit 30 75 30 75 Veco VccoMax lecs Vcc Standby CER M ceS 256 Mbit 55 115 55 200 pa CCQ 1 2 lccp Power Down RST ar for lccs 512 Mbit 110 230 110 400 RST Vss for lccp WP Vj 1 Gbit 220 460 220 800 Asynchronous Single 1 Word Wordf 5MHz 1cLk 14 16 14 16 MA Read Page Mode Read 4 Word _ Average f 13 MHz 5 CLK 9 10 3 10 lee Vcc VccMax l Vcc 13 17 ni A BL 4W PUMA 1 CCR R
21. 0 2 3 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 15 0 1 2 3 4 5 6 7 8 3 0 3 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 15 0 1 2 3 4 5 6 7 8 9 4 0 4 5 6 7 0 1 2 3 4 5 6 7 8 15 0 1 2 3 4 5 6 7 8 9 10 5 0 5 6 7 0 1 2 3 4 5 6 7 8 9 15 0 1 2 3 4 5 6 7 8 9 10 11 6 0 6 7 0 1 2 3 4 5 6 7 8 9 10 15 0 1 2 3 4 5 6 7 8 9 10 11 12 7 0 7 0 1 2 3 4 5 6 7 8 9 10 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 14 15 0 1 2 12 13 14 15 16 17 18 19 20 15 0 15 0 1 2 3 13 14 15 16 17 18 19 20 21 0 1 0 1 2 3 0 1 2 3 4 5 6 7 0 1 2 3 4 14 15 0 1 2 3 4 5 6 1 1 1 2 3 4 1 2 3 4 5 6 7 8 1 2 3 4 5 15 16 1 2 3 4 5 6 7 2 1 2 3 4 5 2 3 4 5 6 7 8 9 2 3 4 5 6 16 17 2 3 4 5 6 7 8 3 1 3 4 5 6 3 4 5 6 7 8 9 10 3 4 5 6 7 17 18 3 4 5 6 7 8 9 4 1 4 5 6 7 8 9 10 11 4 5 6 7 8 18 19 4 5 6 7 8 9 10 5 1 5 6 7 8 9 10 11 12 5 6 7 8 9 19 20 5 6 7 8 9 10 11 6 1 6 7 8 9 10 11 12 13 6 7 8 9 10 20 21 6 7 8 9 10 11 12 7 1 7 8 9 10 11 12 13 14 7 8 9 10 11 21 22 7 8 9 10 11 12 13 14 1 14 15 16 17 18 28 29 14 15 16 17 18 19 20 15 1 15 16 17 18 19 29 30 15 16 17 18 19 20 21 Clock Edge The Clock Edge CE bit selects either a rising default or falling clock edge for CLK This clock edge is used at the start of a burst cycle to output synchronous data and to assert deassert WAIT Burst Wrap The Burst Wrap BW bit determines whether 4 word 8 word or 16 word burst length accesses wrap within the selected word length boundaries
22. 1 Gbit RD48F2000P0ZBQO RD48F3000P0ZBQO RD48F4000P0ZBQO RD48F4400POVBQO RD48F4444PPVBQO RD48F2000P0ZTQO RD48F3000P0ZTQO RD48F4000P0ZTQO RD48F4400P0VTQO RD48F4444PPVTQO PF48F2000P0ZBQO PF48F3000POZBQO PF48F4000P0ZBQO PF48F4400POVBQO PF48F4444PPVBQO PF48F2000P0ZTQO PF48F3000P0ZTQO PF48F4000POZTQO PF48F4400POVTQO PF48F4444PPVTQO RC48F4400P0VB00 RC48F4400P0VTOO PC48F4400P0VB00 PC48F4400POVTOO April 2005 Intel StrataFlash Embedded Memory P30 Datasheet
23. 12 1 12 2 Datasheet Flash erasing is performed on a block basis An entire block is erased each time an erase command sequence is issued and only one block is erased at a time When a block is erased all bits within that block read as logical ones The following sections describe block erase operations in detail Block Erase Block erase operations are initiated by writing the Block Erase Setup command to the address of the block to be erased see Section 9 2 Device Commands on page 50 Next the Block Erase Confirm command is written to the address of the block to be erased If the device is placed in standby CE deasserted during an erase operation the device completes the erase operation before entering standby V pp must be above V pp x and the block must be unlocked see Figure 44 Block Erase Flowchart on page 89 During a block erase the Write State Machine WSM executes a sequence of internally timed events that conditions erases and verifies all bits within the block Erasing the flash memory array changes zeros to ones Memory array bits that are ones can be changed to zeros only by programming the block see Section 11 0 Programming Operations on page 61 The Status Register can be examined for block erase progress and errors by reading any address The device remains in the Read Status Register state until another command is written SR 0 indicates whether the addressed block is erasing Status Register bit
24. 2 0 Functional Overview cniin ederent Ett Sean kein ig ee t Da t laa GEAG ee GE 9 3 0 Package Information ER EE re b teil Estes tes ie EE 10 3 1 56 Lead TSOP Package ertt ride in ERR IRR ERE ETE ee og ee GE CIN SEER IA bee nE 10 3 2 64 Ball Easy BGA Package eene nennen a Re a EE Ge GE Ee nhan ninth ane Reb an 12 3 3 QUAD SCSP Packages retener en AG RR SE RAGE RR EX RR ERE aaa Oe ges E EE SEG NER eis 13 4 0 Ballout and Signal Descriptions sss 17 41 Signal RE OR OE EE E prre re ei CREER TUR ER EPOR ERE OE EG 17 42 Signal Descriptions sssrinin nannan KA ERGE Ee tnnt Ge n nn ee ee soa eta Ee ri 20 43 SCSP Configurations s reu ER aes 22 4 4 IMGIMORY MET m 24 5 0 Maximum Ratings and Operating Conditions sss 29 5 1 Absolute Maximum Ratings uses ee de Re AA AA AA ee nennen intr ed de ee ek ee ns 29 5 2 Operating Conditions ee ee ee AR RR RA ee ee ee ee ee ee ee ke ee ee ee ee ee nnne eke ee ee 30 6 0 Electrical Speciliations ss AE PEER ed und dignas ag GE aa 31 6 1 DC Current Characteristics 3 err renti EERS ER ek aA SEE BES RE EER Ee EE MAE AERE ERGE EN EG ER 31 62 DC Voltage Characteristics esten EES Ee ERGE REEN EE REGEER Ke Ge SEE e GED NR EE Ke GENE RS EEN Wee EEN 32 7 0 AC CharacferisliC S ema Bed ses bre Re sees ee sa es ER bee 33 mL AC Test Conditions EE N a a a E Adaa aada OTa Aaaa aaia 33 72 Cap cit nte e S 34 7 3 AC Read Specifications
25. ASCII string QRY 13h 2 Primary vendor command set and control interface ID code 13 01 16 bit ID code for vendor specified algorithms 14 00 15h 2 Extended Query Table primary algorithm address 15 0A el ee E 17h 2 Alternate vendor command set and control interface ID code 17 00 ENE EE EIE IN 0000h means none exists 1A 00 System Interface Information Vcc logic supply minimum program erase voltage bits 0 3 BCD 100 mV bits 4 7 BCD volts Vec logic supply maximum program erase voltage bits 0 3 BCD 100 mV bits 4 7 BCD volts Vpp programming supply minimum program erase voltage bits 0 3 BCD 100 mV bits 4 7 HEX volts Vpp programming supply maximum program erase voltage bits 0 3 BCD 100 mV bits 4 7 HEX volts m Ta a N g z N e gt Intel StrataFlash Embedded Memory P30 Order Number 306666 Revision 001 April 2005 95 1 Gbit P30 Family l n C 4 Device Geometry Definition Table 36 Device Geometry Definition Offset 27h 1 n such that device size 2 in number of bytes 27 See table below Flash device interface code assignment n such that n 1 specifies the bit field that represents the flash device width eue as iib in the table TTT et ee a pipes n TERM that maximum _ of um in E Number of erase block regions x within device 1 x 0 means no erase blocking the devic
26. Address setup to WE high 50 ns WE twoen CE hold from WE high 0 ns 1 2 W7 twuox Data hold from WE high 0 ns W8 twuax Address hold from WE high 0 ns W9 twowe WE pulse width high 20 ns 1 2 5 W10 typwu Vpp setup to WEZ high 200 ns W11 tow Vpp hold from Status read 0 ns x2 W12 tovar WP hold from Status read 0 ns 225 W13 teuwa WP5 setup to WE high 200 ns Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 41 1 Gbit P30 Family Table 18 Figure 22 AC Write Specifications Sheet 2 of 2 Num Symbol Parameter Min Max Units Notes W14 toue WE high to OE low 0 ns 1 2 9 W16 twuov WEZ high to read valid tavov 35 ns ES ds Write to Asynchronous Read Specifications W18 twnav WEZ high to Address valid 0 ns 1 2 3 6 8 Write to Synchronous Read Specifications W19 twucun WEZ high to Clock valid 19 ns 12361 W20 tyiv WE high to ADV high 19 a ns 0 Write Specifications with Clock Active W21 twe ADV high to WE low 20 ns 1 2 3 11 W22 tcuw Clock high to WE low 20 ns Notes 1 Write timing characteristics during erase suspend are the same as write only operations 2 A write operation can be terminated with either CE or WE 3 Sampled not 100 tested 4 Write pulse width low ty wg Or tg gj is defined from CE or WE low whichever occurs last to CE or WE high whiche
27. Device Erase Program BEFP Write Status Suspend Status Status MERS use rd rockeg Status Status Status Status DWS ESS ES PS VPPS PSS BLS BWS 7 6 5 4 3 2 1 0 Bit Name Description 1 Device Write Status 0 Device is busy program or erase cycle in progress SR O valid DWS 1 Device is ready SR 6 1 are valid 6 Erase Suspend Status 0 Erase suspend not in effect ESS 1 Erase suspend in effect Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 75 1 Gbit P30 Family I n e Table 28 Status Register Description Sheet 2 of 2 Status Register SR Default Value 0x80 0 Erase successful i Erase Status ES 1 Erase fail or program sequence error when set with SR A 7 0 Program successful 4 Program Status PS 1 Program fail or program sequence error when set with SR 5 7 0 VPP within acceptable limits during program or erase operation E Vpp Status VPPS 1 VPP lt VPPLK during program or erase operation 2 Program Suspend Status 0 Program suspend not in effect PSS 1 Program suspend in effect 1 Block Locked Status 0 Block not locked during program or erase BLS 1 Block locked during program or erase operation aborted DWS BWS 0 0 WSM is busy and buffer is available for loading 0 BEFP Status BWS 0 1 WSMis busy and buffer is not available for loading 1 0 WSM is not busy and buffer is available for loading 1 1 R
28. Intel Multi Level Cell MLC flash memory devices draw their power from VCC VPP and VCCQ each power connection should have a 0 1 pF ceramic capacitor to ground High frequency inherently low inductance capacitors should be placed as close as possible to package leads Additionally for every eight devices used in the system a 4 7 pF electrolytic capacitor should be placed between power and ground close to the devices The bulk capacitor is meant to overcome voltage droop caused by PCB trace inductance Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 47 1 Gbit P30 Family ntel amp 9 0 Device Operations This section provides an overview of device operations The system CPU provides control of all in system read write and erase operations of the device via the system bus The on chip Write State Machine WSM manages all block erase and word program algorithms Device commands are written to the Command User Interface CUT to control all flash memory device operations The CUI does not occupy an addressable memory location it is the mechanism through which the flash device is controlled 9 1 Bus Operations CE low and RST high enable device read operations The device internally decodes upper address inputs to determine the accessed block ADV low opens the internal address latches OE low activates the outputs and
29. Laas ds Y PGM SUS WMF Intel StrataFlash Embedded Memory P30 Datasheet Order Number 306666 Revision 001 l n 1 Gbit P30 Family Figure 42 Buffer Program Flowchart Buffer Programming Procedure Bus Doerati n Command Comments Device Use Single Word Buffer Prog Data OXE8 ren E Programming valle Setup Addr Word Address SR 7 Valid Read None Addr Word Address Set Timeout or Loop Counter Check SR 7 Idle None 1 Write Buffer available Y 0 No Write Buffer available Get Next Target Address Write mE N 1 Word Count 7 Notes 1 2 None N O corresponds to count 1 Y Addr Word Address Issue Buffer Prog Cmd OxE8 Write Data Write Buffer Data None Word Address Notes 3 4 Addr Start Word Address m gt Y Write None Data Write Buffer Data S Read Status Register Note 3 Addr Word Address E 2 at Word Address Write Buffer Prog Data OXDO E Notes 5 6 Conf Addr Original Word Address no oo Status register Dat lt gister Data Read None Addr Note 7 ce a8 Check SR 7 ds Idle None 1 WSMReady 5 F 0 WSM Busy os F gt E Write Word Count 1 Word count value on DI7 0 is loaded into the word count 2c Word Address register Count ranges for this device ar
30. N N IN CE ADV A MAX 0 l Address D 15 0 Code 3 10 3 3 10 3 3 1 Datasheet WAIT Polarity The WAIT Polarity bit WP RCR 10 determines the asserted level Voy or VoL of WAIT When WP is set WAIT is asserted high default When WP is cleared WAIT is asserted low WAIT changes state on valid clock edges during active bus cycles CE asserted OE asserted RST deasserted WAIT Signal Function The WAIT signal indicates data valid when the device is operating in synchronous mode RCR 15 0 The WAIT signal is only deasserted when data is valid on the bus When the device is operating in synchronous non array read mode such as read status read ID or read query The WAIT signal is also deasserted when data is valid on the bus WAIT behavior during synchronous non array reads at the end of word line works correctly only on the first data access When the device is operating in asynchronous page mode asynchronous single word read mode and all write operations WAIT is set to a deasserted state as determined by RCR 10 See Figure 17 Asynchronous Single Word Read ADV Latch on page 38 and Figure 18 Asynchronous Page Mode Read Timing on page 39 Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 57 1 Gbit P30 Family ntel amp 10 3 4 Figure 30 Table 24 WAIT Functionality Table Condition WAIT Notes CE 1 O
31. Next State m Lack Down Write RCR Block Address Illegal Cmds or Block Block WSM Current Chi irm 2 9 w p Confirm Confirm Confirm pone BEFP Dale Operation State Completes 01H 2FH XXXXH all other codes Word Program Busy in Erase Suspend Word Busy Word Program Busy in Erase Suspend Busy Erase Suspend Program in Erase Suspend Suspend Word Program Suspend in Erase Suspend N A BP Load 1 BP Load 2 Ready BP Load 2 BP Load 2 N A BP Confirm if BP Confirm if Data load into Program Buffer is Ee oie BP Load 2 N Ready Program Buffer is complete Else BP Load 2 complete Else BP Load 2 BP in Erase Ready Error Suspend BP r Proceed if Ready E E Si d Guil eady Error in Erase Suspend Er AE Ready Error error BP Busy BP Busy in Erase Suspend Erase Suspend B BP Suspend in Erase Suspend Suspend Erase Erase Erase Erase Lock CR Setup in Erase Suspend Suspend Suspend Suspend Erase Suspend Lock Error Suspend Lock Lock Lock Down Set CR N A Error Block Block Buffered Ready Error avi Gee Ready Error Loading Data Enhanced Factory Program BEFP Program and Verify Busy if Block Address Mode given matches address given on BEFP Setup BEFP Busy Ready command Commands treated as data 7 Datasheet Intel StrataFlash Embedded Memory P30 Order Number 306666 Revision 001 April 2005 81 1 Gbit P30 Family I n Figure 38 Write State Machine Next State Table Sheet
32. SR 7 is set upon erase completion Status Register bit SR 7 indicates block erase status while the sequence executes When the erase operation has finished Status Register bit SR 5 indicates an erase failure if set SR 3 set would indicate that the WSM could not perform the erase operation because Vpp was outside of its acceptable limits SR 1 set indicates that the erase operation attempted to erase a locked block causing the operation to abort Before issuing a new command the Status Register contents should be examined and then cleared using the Clear Status Register command Any valid command can follow once the block erase operation has completed Erase Suspend Issuing the Erase Suspend command while erasing suspends the block erase operation This allows data to be accessed from memory locations other than the one being erased The Erase Suspend command can be issued to any device address A block erase operation can be suspended to perform a word or buffer program operation or a read operation within any block except the block that is erase suspended see Figure 41 Program Suspend Resume Flowchart on page 86 When a block erase operation is executing issuing the Erase Suspend command requests the WSM to suspend the erase algorithm at predetermined points The device continues to output Status Register data after the Erase Suspend command is issued Block erase is suspended when Status Register bits SR 7 6 are set Suspen
33. Standby Write i Bus Bus n Operation Comments State Operation Comments State Operation Comments Unlock Status Data Status Register Data Status Data Status Register Data Block Vern applied to VPP Read Register Address 1 Word Addr mE Register Address 1 Word Addr Write BEFP Data 0x80 1 Word Data Si Check SR 0 Check SR 7 Note 1 Setup Address Standby P8la Stream 9 Ready for Data Standby 0 Exit Not Completed Ready 1 Not Ready for Dat 1 Exit Completed Wie BEFP Data 0x80 1 Word Not Ready tor Data Fit Complete 1 m onfirm Address Standby Initialize y _ 9 Repeat for subsequent blocks Reid Status Data Status Register Data Count Register Address 1 Word Addr After BEFP exit a full Status Register check can determine if any program error occurred See full Status Register check procedure in the Word Program flowchart Write OxFF to enter Read Array state 1 First word address to be programmed within the target block must be aligned on a write buffer boundary 2 Write buffer contents are programmed sequentially to the flash array starting at the first word address WSM internally increments addressing April 2005 88 Intel StrataFlash Embedded Memory P30 Order Number 306666 Revision 001 Datasheet Figure 44 Datasheet 1 Gbit P30 Family Block Erase Flowchart Write Ox20 Block Address Write OxDO Block Address
34. Status Read Word Pgm Setup Word Pgm Setup in Erase Susp BP Setup Load1 Load 2 Confirm in Erase Suspend Lock CR Setup Lock CR Setup in Status Read Status Read Erase Susp Output does not change Ready Erase Suspend BP Suspend Erase Busy Status Guides notohange Anay Read Output does not BP Busy Read change BP Busy in Erase Word Pgm Busy in Erase Suspend Pgm Suspend In 1 Illegal commands include commands outside of the allowed command set allowed commands 40H pgm 20H erase etc 2 If a Read Array is attempted from a busy partition the result will be invalid data The ID and Query data are located at different locations in the address map 3 1st and 2nd cycles of 2 cycles write commands must be given to the same partition address or unexpected results will occur 4 To protect memory contents against erroneous command sequences there are specific instances in a multi cycle command sequence in which the second cycle will be ignored For example when the device is program suspended and an erase setup command 0x20 is given followed by a confirm resume command 0xDO the second command will be ignored because it is unclear whether the user intends to erase the block or resume the program operation Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 83 1 Gbit P30 Family ntel amp 5 The Clear Status command only clears the error b
35. Vcc should attain V ccm n before applying Vcco and Vpp Device inputs should not be driven before supply voltage equals VCCMIN Power supply transitions should only occur when RST is low This protects the device from accidental programming or erasure during power transitions Reset Specifications Asserting RST during a system reset is important with automated program erase devices because systems typically expect to read from flash memory when coming out of reset If a CPU reset occurs without a flash memory reset proper CPU initialization may not occur This is because the flash memory may be providing status information instead of array data as expected Connect RST to the same active low reset signal used for CPU initialization Also because the device is disabled when RST is asserted it ignores its control inputs during power up down Invalid bus conditions are masked providing a level of memory protection Num Symbol Parameter Min Max Unit Notes P1 tpi pu RST pulse width low 100 ns 1 2 3 4 po k RST low to device reset during erase 25 1 3 4 7 FERH RST low to device reset during program 25 us 1 3 4 7 P3 tyccpH Vcc Power valid to RST de assertion high 60 1 4 5 6 Notes 1 These specifications are valid for all device versions packages and speeds 2 The device may reset if tp py is lt tpj py MIN but this is not guaranteed 3 Not applicable if RST is tied to Vcc
36. Write State Machine Figure 34 through Figure 39 show the command state transitions Next State Table based on incoming commands Only one partition can be actively programming or erasing at a time Each partition stays in its last read state Read Array Read Device ID CFI Query or Read Status Register until a new command changes it The next WSM state does not depend on the partition s output state Figure 34 Write State Machine Next State Table Sheet 1 of 6 Command Input to Chip and resulting Chip Next State BE Confirm Buffered i current Chip me NR Emand gee OPI EN M rk roer urren l 2 3 4 3 4 Factory P d p Array Program BP Setup md ULB Suspend Status Register 5 ID Query CR setup 4 State Sup Confirm 9 FFH 10H 40H E8H 80H DOH BOH 50H 90H 98H 60H Program Erase Lock CR Read Read Lock CR Setup Ready Lock Error Ready Lock Error EN pii dd Busy Setup Word Program Busy Word Word Busy Program Busy Program Word Program Busy Suspend Program Word Suspend Word Program Suspend Program Word Program Suspend Busy setup BP Load 1 BP Load 2 BP Confirm if Data load into Program Buffer is complete Else BP Load 2 BE Ready Error BP Bus Ready Error Confirm y y y BP BP Busy NT N NT N BP EP suspend BP Busy BF BP Suspend BP Bus BP Suspend Suspend y Ready Error Erase Busy Ready Error EA eu Erase Busy EA d Erase Busy Erase Word Er
37. data output width OOh indicates no P 1E h un Er n Syahroni mode read configuration fields that 04 4 follow OOh indicates no burst capabili i P 20 h 1 JS ohronbus mod read capabilit configuration 2 12A 02 8 P 21 h 1 Synchronous mode read capability configuration 3 12B 03 16 P 22 h Synchronous mode read capability configuration 4 12C 07 Cont Synchronous mode read capability configuration 1 Bits 3 7 Reserved bits 0 2 n such that 2 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device s burstable address space This field s 3 bit value can be written directly to the Read Configuration Register bits 0 2 if the device is Ce ne for its maximum word width See offset 28h for Intel StrataFlash Embedded Memory P30 Order Number 306666 Revision 001 Datasheet i ntel e 1 Gbit P30 Family Table 40 Partition and Erase block Region Information Offset P 10Ah Description Hex Optional flash features and commands Code Value P 23 h P 23 h Number of device hardw are partition regions within the device 12D x 0 a single hardware partition device no fields follow x specifies the number of device partition regions containing one
38. flag will be set Data words from the write buffer are directed to sequential memory locations in the flash memory array programming continues from where the previous buffer sequence ended The host programming system must poll SR 0 to determine when the buffer program sequence completes SR 0 cleared indicates that all buffer data has been transferred to the flash array SR 0 set indicates that the buffer is not available yet for the next fill cycle The host system may check full status for errors at any time but it is only necessary on a block basis after BEFP exit After the buffer fill cycle no write cycles should be issued to the device until SR 0 0 and the device is ready for the next buffer fill Any spurious writes are ignored after a buffer fill operation and when internal program is proceeding The host programming system continues the BEFP algorithm by providing the next group of data words to be written to the buffer Alternatively it can terminate this phase by changing the block address to one outside of the current block s range The Program Verify phase concludes when the programmer writes to a different block address data supplied must be OxFFFF Upon Program Verify phase completion the device enters the BEFP Exit phase BEFP Exit Phase When SR 7 is set the device has returned to normal operating conditions A full status check should be performed at this time to ensure the entire block programmed successfully W
39. gates selected data onto the I O bus In asynchronous mode the address is latched when ADV goes high or continuously flows through if ADV is held low In synchronous mode the address is latched by the first of either the rising ADV edge or the next valid CLK edge with ADV low WE and RST must be Vig CE must be Vi Bus cycles to from the P30 device conform to standard microprocessor bus operations Table 19 summarizes the bus operations and the logic levels that must be applied to the device control signal inputs Table 19 Bus Operations Summary Bus Operation RST CLK ADV CE OE WE WAIT DQ 15 0 Notes ET Asynchronous Vin X L L L H Deasserted Output eat Synchronous Vin Running L L L H Driven Output Write Viu L L H L High Z Input 1 Output Disable Vin X X L H H High Z High Z 2 Standby Vin x x H X X High Z High Z 2 Reset ViL X X X X X High Z High Z 2 3 Notes 1 Refer to the Table 20 Command Bus Cycles on page 50 for valid DQ 15 0 during a write operation 2 X Don t Care H or L 3 RST must be at Vss 0 2 V to meet the maximum specified power down current 9 1 1 Reads To perform a read operation RST and WE must be deasserted while CE and OE are asserted CE is the device select control When asserted it enables the flash memory device OE is the data output control When asserted the addressed flash memory data is driven onto the I O bus See Section 10 0 Read Operations on page 53 for details on the available
40. one and the three adjacent 128 KB main blocks This is available for top or bottom parameter devices Lock Block To lock a block issue the Lock Block Setup command The next command must be the Lock Block command issued to the desired block s address see Section 9 2 Device Commands on page 50 and Figure 46 Block Lock Operations Flowchart on page 91 If the Set Read Configuration Register command is issued after the Block Lock Setup command the device configures the RCR instead Block lock and unlock operations are not affected by the voltage level on Vpp The block lock bits may be modified and or read even if Vpp is at or below Vppy x Unlock Block The Unlock Block command is used to unlock blocks see Section 9 2 Device Commands on page 50 Unlocked blocks can be read programmed and erased Unlocked blocks return to a locked state when the device is reset or powered down If a block is in a lock down state WP must be deasserted before it can be unlocked see Figure 32 Block Locking State Diagram on page 70 Lock Down Block A locked or unlocked block can be locked down by writing the Lock Down Block command sequence see Section 9 2 Device Commands on page 50 Blocks in a lock down state cannot be programmed or erased they can only be read However unlike locked blocks their locked state cannot be changed by software commands alone A locked down block can only be unlocked by issuing the Unlock Block command w
41. or cross word length boundaries When BW is set burst wrapping does not occur default When BW is cleared burst wrapping occurs When performing synchronous burst reads with BW set no wrap an output delay may occur when the burst sequence crosses its first device row 16 word boundary If the burst sequence s start address is 4 word aligned then no delay occurs If the start address is at the end of a 4 word Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 59 1 Gbit P30 Family ntel amp boundary the worst case output delay is one clock cycle less than the first access Latency Count This delay can take place only once and doesn t occur if the burst sequence does not cross a device row boundary WAIT informs the system of this delay when it occurs 10 3 9 Burst Length The Burst Length bit BL 2 0 selects the linear burst length for all synchronous burst reads of the flash memory array The burst lengths are 4 word 8 word 16 word and continuous word Continuous burst accesses are linear only and do not wrap within any word length boundaries see Table 25 Burst Sequence Word Ordering on page 59 When a burst cycle begins the device outputs synchronous burst data until it reaches the end of the burstable address space April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 60 Order Number 306666 Revision 001 In 11 0 1 Gbit P30 Family Programming Opera
42. or more contiguous erase block regions Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 99 1 Gbit P30 Family Appendix D Additional Information April 2005 100 Order Document Number Document Tool 290667 Intel StrataFlash Memory J3 Datasheet 290737 Intel StrataFlash Synchronous Memory K3 K18 Datasheet 290701 Intel Wireless Flash Memory W18 Datasheet 290702 Intel wireless Flash Memory W30 Datasheet 252802 Intel Flash Memory Design for a Stacked Chip Scale Package SCSP 298161 Intel Flash Memory Chip Scale Package User s Guide 253418 Intel Wireless Communications and Computing Package User s Guide 296514 Intel Small Outline Package Guide 297833 Intel Flash Data Integrator FDI User s Guide 298136 Intel Persistent Storage Manager User Guide 300783 Using Intel amp Flash Memory Asynchronous Page Mode and Synchronous Burst Mode 306667 Migration Guide for Intel StrataFlash Memory J3 to Intel StrataFlash Embedded Memory P30 Application Note 812 306668 Migration Guide for Spansion S29GLxxxN to Intel StrataFlash Embedded Memory P30 Application Note 813 306669 Migration Guide for Intel StrataFlash Synchronous Memory K3 K18 to Intel StrataFlash Embedded Memory P30 Application Note 825 Notes 1 Please call the Intel Literature Center at 800 548 4725 to request Intel documentation International customers sho
43. outputs data during DQ 15 0 outa memory Status Register Protection Register and Read Configuration Register reads Data balls float when the CE or OE are deasserted Data is internally latched during writes ADDRESS VALID Active low input During synchronous read operations addresses are latched on the rising edge of ADV or on the next valid CLK edge with ADV low whichever occurs first ADV Input In asynchronous mode the address is latched when ADV going high or continuously flows through if ADV is held low WARNING Designs not using ADV must tie it to VSS to allow addresses to flow through FLASH CHIP ENABLE Active low input CE low selects the associated flash memory die When asserted flash internal control logic input buffers decoders and sense amplifiers are active When F1 CE deasserted the associated flash die is deselected power is reduced to standby levels data and Input WAIT outputs are placed in high Z state F2 CE See Table 6 on page 22 for CE assignment definitions WARNING All chip enables must be high when device is not in use CLOCK Synchronizes the device with the system s bus frequency in synchronous read mode During synchronous read operations addresses are latched on the rising edge of ADV or on the CLK Input next valid CLK edge with ADV low whichever occurs first WARNING Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS F1 OEZ OUTPUT ENAB
44. read modes and see Section 14 0 Special Read States on page 75 for details regarding the available read states April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 48 Order Number 306666 Revision 001 I n e 1 Gbit P30 Family 9 1 2 Writes To perform a write operation both CE and WE are asserted while RST and OE are deasserted During a write operation address and data are latched on the rising edge of WE or CE whichever occurs first Table 20 Command Bus Cycles on page 50 shows the bus cycle sequence for each of the supported device commands while Table 21 Command Codes and Definitions on page 51 describes each command See Section 7 0 AC Characteristics on page 33 for signal timing details Note Write operations with invalid Vcc and or Vpp voltages can produce spurious results and should not be attempted 9 1 3 Output Disable When OE is deasserted device outputs DQ 15 0 are disabled and placed in a high impedance High Z state WAIT is also placed in High Z 9 1 4 Standby When CE is deasserted the device is deselected and placed in standby substantially reducing power consumption In standby the data outputs are placed in High Z independent of the level placed on OE Standby current Iccs is the average current measured over any 5 ms time interval 5 us after CE is deasserted During standby average current is measured over the same time interval 5 us after CE is deasserted
45. 0 28FFFF 4F0000 4FFFFF 270000 27FFFF 400000 40FFFF 200000 20FFFF 3F0000 3FFFFF 1F0000 1FFFFF 300000 30FFFF 180000 18FFFF 2F0000 2FFFFF 170000 17FFFF 200000 20FFFF 100000 10FFFF 1F0000 1FFFFF OF0000 OFFFFF 100000 10FFFF 080000 08FFFF Table 8 OF0000 OFFFFF 070000 07FFFF 000000 00FFFF 000000 OOFFFF Programming Region Discrete Bottom Parameter Memory Maps all packages 1 Gbit P30 Family 64 Mbit 256 Mbit Blk 128 Mbit E a 64 Mbit 128 258 FF0000 FFFFFF 130 7F0000 7FFFFF 128 62 3F0000 3FFFFF 15 7 128 243 F00000 FOFFFF 123 780000 78FFFF 128 56 380000 38FFFF 128 242 EF0000 EFFFFF 122 770000 77FFFF 128 55 370000 37FFFF 14 6 128 227 E00000 EoFFFF 115 700000 70FFFF 128 48 300000 30FFFF 128 226 DF0000 DFFFFF 114 6F0000 GFFFFF 128 47 2F0000 2FFFFF 13 5 128 211 D00000 DOFFFF 107 680000 68FFFF 128 40 280000 28FFFF Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 25 1 Gbit P30 Family Table 8 Discrete Bottom Parameter Me
46. 005 8 Reserved for Future Use Status Register Write State Machine Signal or voltage connection Signal or voltage level Hexadecimal number prefix Binary number prefix Denotes an individual register bit Denotes a group of similarly named signals such as address or data bus Denotes one element of a signal group membership such as an individual address bit Binary unit Fight bits Two bytes or sixteen bits 1024 bits 1024 bytes 1024 words 1 048 576 bits 1 048 576 bytes 1 048 576 words Intel StrataFlash Embedded Memory P30 Datasheet Order Number 306666 Revision 001 1 Gbit P30 Family Functional Overview Datasheet This section provides an overview of the features and capabilities of the 1 Gbit P30 Family device The P30 family provides density upgrades from 64 Mbit through 1 Gbit This family of devices provides high performance at low voltage on a 16 bit data bus Individually erasable memory blocks are sized for optimum code and data storage Upon initial power up or return from reset the device defaults to asynchronous page mode read Configuring the Read Configuration Register enables synchronous burst mode reads In synchronous burst mode output data is synchronized with a user supplied clock signal A WAIT signal provides an easy CPU to flash memory synchronization In addition to the enhanced architecture and interface the device incorporates technology that enables fast factory program and
47. 1 Write DBA 0x50 Word Program 2 Write WA nd Write WA WD Program Buffered Program gt 2 Write WA OxE8 Write WA N 1 Buffered Enhanced Factory Program BEFP 22 Write WA 0x80 Write WA OxDO Erase Block Erase 2 Write BA 0x20 Write BA OxDO Program Erase Suspend 1 Write DBA OxBO Suspend Program Erase Resume 1 Write DBA OxDO Lock Block 2 Write BA 0x60 Write BA 0x01 Block Locking Unlock Block 2 Write BA 0x60 Write BA OxDO Unlocking Lock down Block 2 Write BA 0x60 Write BA Ox2F April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 50 Order Number 306666 Revision 001 intel 1 Gbit P30 Family Table 20 Command Bus Cycles Sheet 2 of 2 First Bus Cycle Second Bus Cycle Bus Mode Command Posie y Oper Addr Data Oper Addr Data Program Protection Register 2 Write PRA OxCO Write PRA PD Protection Program Lock Register 2 Write LRA OxCO Write LRA LRD Configuration P 99ram Read Configuration 2 write RCD 0x60 Write RCD 0x03 Register Notes 1 First command cycle address should be the same as the operation s target address DBA Device Base Address NOTE needed for 2 or more die stacks IA Identification code address offset QA CFI Query address offset WA Word address of memory location to be written BA Address within the block PRA Protection Register address LRA Lock Register address RCD Read Configuration Register data o
48. 128P30T85 RC28F256P30T85 PC28F640P30B85 PC28F128P30B85 PC28F256P30B85 PC28F640P30T85 PC28F128P30T85 PC28F256P30T85 Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 101 1 Gbit P30 Family Intel Appendix F Ordering Information for SCSP Products Figure 49 Decoder for SCSP Intel StrataFlash Embedded Memory P30 Flash Family 1 2 Flash Family 3 4 4 Flash 1 Flash 2 Flash 3 Flash 4 U o RID A 8 F z B Qo Device Details 0 Original version of the product refer to the latest version of the datasheet for details Package Designator RD Intel SCSP leaded PF Intel SCSP lead free RC 64 Ball Easy BGA leaded PC 64 Ball Easy BGA lead free Ballout Designator Q QUAD ballout 0 Discrete ballout Group Designator 48F Flash Memory only Flash Density 0 No die Parameter Mux Configuration 2 64 Mbit B Bottom Parameter Non Mux 3 128 Mbit Toss ee NUM 4 256 Mbit Top Parameter Non ux I O Voltage CE Configuration Product Family Z 3 0 V Individual Chip Enable s P Intel StrataFlash Embedded Memory 102 Order Number 306666 Revision 001 0 No die V 3 0 V Virtual Chip Enable s Table 42 Valid Combinations for Stacked Products 64 Mbit 128 Mbit 256 Mbit 512 Mbit
49. 21 i l w21 w22 i i gt W22 We 15 i i w2 W3 sie W9 gt WE f d i p R16 je gt R307 je R312 WAIT T 1 i R304 be i V RT 9 R305 WIL Data D Q C Q _ D D Note WAIT shown deasserted and High Z per OE deassertion during write operation RCR 10 0 Wait asserted low Clock is ignored during write operation Figure 26 Write to Synchronous Read Timing gt R302 be l I K 9 R301 I I I l 1 R2 t 1 CLK l Li N N X N X X i j W5 ie W8 ig je R306 l Address A NEED fru epp ppm ET M R106 1 gt R104 be ADVE N le W6 om R303 be l j w2 R11 be 17 N CE E i e W18 I M W 19 I I imd W3 Pet W20 gt I eZ 8 1 i Re OE G I XI i i M R15 e gt R307 I WAIT T i X w7 i l gt R304 le l R305 I pwi le 1 R3 T gt gt R304 le Data D Q D sy Q T S wi 1 L L L RST P I 1 Note WAIT shown deasserted and High Z per OE deassertion during write operation RCR 10 0 Wait asserted low April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 44 Order Number 306666 Revision 001
50. 5 F2 OE VCCQ 2 s 2 2 DQ15 IN Gy VCCQ DQ14 DQ12 x npn Bo DOE BH BERO EEE ZZ MI o o EJ Yi i BEEF EDE MUN cL BOR NS a a ad a 7 1 a nm N 3 8 o o Q S 8 Bm o gt WG NS b VCCQ VCC Depop Depop Depop LEE B ig F1 CE o o EJ vss VSS DU Depop DU 19 Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 Datasheet 1 Gbit P30 Family 4 2 Table 3 Signal Descriptions This section has signal descriptions for the various P30 packages TSOP and Easy BGA Signal Descriptions Sheet 1 of 2 Symbol Type Name and Function A MAX 1 Input ADDRESS INPUTS Device address inputs 64 Mbit A 22 1 128 Mbit A 23 1 256 Mbit A 24 1 512 Mbit A 25 1 See Table 5 on page 22 and Figure 10 on page 23 for 512 Mbit addressing DQ 15 0 Input Output DATA INPUT OUTPUTS Inputs data and commands during write cycles outputs data during memory Status Register Protection Register and Read Configuration Register reads Data balls float when the CE or OE are deasserted Data is internally latched during writes ADV Input ADDRESS VALID Active low input During synchronous read operations addresses are latched on the rising edge of ADV or on the next valid CLK edge with ADV low whichever occurs first In asy
51. 5 of 6 Output Next State Table Command Input to Chip and resulting Output Mux Next State Buffered BE Confirm Word P E Program Clear Lock Unlock Program BP Setup Eu Resume Erase Read Status Read Lock down ID Query I J Status Current chip state Setup 3 4 emp ULB Confirm Suspend Register CR setup 10H 40H 30H DOH 50H 90H 98H 60H BEFP Setup BEFP Pgm amp Verify Busy Erase Setup OTP Setup BP Setup Load 1 Load 2 Confirm Status Read Word Pgm Setup Word Pgm Setup in Erase Susp BP Setup Load1 Load 2 Confirm in Erase Suspend Lock CR Setup Lock CR Setup in Status Read Erase Susp Ready Erase Suspend BP Suspend Output mux Read Array Status Read Output does not change Status Read does not Status Read change ID Read Word Pgm Busy in Erase Suspend Pgm Suspend In Erase Suspend April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 82 Order Number 306666 Revision 001 l n 1 Gbit P30 Family Figure 39 Write State Machine Next State Table Sheet 6 of 6 Output Next State Table Lock Lock Down Block Block Current chip state Confirm 9 Confirm 9 Write CR Block Address Illegal Cmds or WSM Confirm 9 2WAO BEFP Data Operation Completes 01H 2FH FFFFH all other codes BEFP Setup BEFP Pgm amp Verify Busy Erase Setup OTP Setup BP Setup Load 1 Load 2 Confirm
52. 54 FE0000 FEFFFF 128 0 000000 OOFFFF 128 258 FF0000 FFFFFF Flash Die 3 128 5 020000 02FFFF Bottom Parameter 32 3 00C000 OOFFFF 32 0 000000 003FFF 32 258 FFCO00 FFFFFF r Flash Die 2 32 255 FF0000 FF3FFF Top Parameter 128 254 FE0000 FEFFFF 128 0 000000 OOFFFF 128 258 FF0000 FFFFFF i Flash Die 1 128 4 010000 01FFFF Bottom Parameter 32 3 00C000 OOFFFF 32 0 000000 003FFF Note Refer to 256 Mbit Memory Map Table 7 and Table 8 for Programming Region Information April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 28 Order Number 306666 Revision 001 1 Gbit P30 Family Maximum Ratings and Operating Conditions 5 1 Warning Datasheet Absolute Maximum Ratings Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage These are stress ratings only Parameter Maximum Rating Notes Temperature under bias 40 C to 85 C 1 Storage temperature 65 C to 125 C Voltage on any signal except VCC VPP 0 5 V to 4 1 V 2 VPP voltage 0 2 V to 10 V 2 3 4 VCC voltage 0 2 V to 12 5 V 2 VCCQ voltage 0 2 V to 4 1 V 2 Output short circuit current 100 mA 5 Notes 1 Temperature for 1 Gbit SCSP is 30 C to 85 C 2 Voltages shown are specified with respect to Vss Minimum DC voltage is 0 5 V on input output signals and 0 2 V on Vcc Vcco and Vpp During transitions this level may un
53. BEFP Flowchart Setup Phase l Start Vpp applied Block Unlocked Write 80h 1 Word Address Write DOh 1 Word Address BEFP Setup delay Read Status Reg BEFP Setup Yes SRI7IEO Done No SR 7 1 Check Vpp Lock errors SR 3 1 BEFP Setup Program amp Verify Phase l Read Data Stream Ready Yes SR 0 0 In e Count X 0 Write Data 1 Word Address Increment Coun X X 1 Y Read Status Reg No SR 0 1 Program Done Yes SR 0 0 Write OxFFFF Address Not within Current Block BEFP Program amp Verify BEFP BUFFERED ENHANCED FACTORY PROGRAMMING BEFP PROCEDURE Exit Phase l Read Exited Yes SR 7 1 Full Status Check Procedure Program Complete BEFP Exit BEFP Check SR 7 Standby Setup 0 BEFP Ready Done 1 BEFP Not Ready Write Load Data Data to Program note 2 Buffer Address 1 Word Addr Increment Count AU Standby Error If SR 7 is set check Standby Condition SR 3 set Vpp Error Check SR 1 set Locked Block NOTES X 32 Yes Read SR 0 No Load Next Data Word Read Status Data Status Reg Data Register Address 1 Word Addr Progam Check SR 0 Standby bacs Buffer Standby Full 1 Program in Progress No Fill buffer again Yes Exit Exit Prog amp Data OxFFFF address Verify Phase not in current block 0 Program Done
54. E X or CEH 0 OE 1 High Z CE 0 OE 0 Active Synchronous Array Reads Active Synchronous Non Array Reads Active Pl RP Pl RiP All Asynchronous Reads Deasserted All Writes High Z 1 2 Notes 1 Active WAIT is asserted until data becomes valid then deasserts 2 When OE Vj during writes WAIT High Z Data Hold For burst read operations the Data Hold DH bit determines whether the data output remains valid on DQ 15 0 for one or two clock cycles This period of time is called the data cycle When DH is set output data is held for two clocks default When DH is cleared output data is held for one clock see Figure 30 The processor s data setup time and the flash memory s clock to data output delay should be considered when determining whether to hold output data for one or two clocks A method for determining the Data Hold configuration is shown below To set the device at one clock data hold for subsequent reads the following condition must be satisfied tcHQV ns tpaTa ns lt One CLK Period ns tpATA Data set up to Clock defined by CPU For example with a clock frequency of 40 MHz the clock period is 25 ns Assuming tcov 20 ns and tpara 4 ns Applying these values to the formula above 20 ns 4 ns lt 25 ns The eguation is satisfied and data will be available at every clock period with data hold setting at one clock If tcov ns DATA
55. EE EES EE DE cate ER ER GR ntt EG Se inu 55 10 3 2 Eatency Gount EI EE EE OE EE din adn 55 10 3 3 WAIT BoOl arity otro ee e etate Sih ace e 1o qe ah ee See Io t 57 10 3 4 Data Hold notet neta erect rte Ee aee RE er eee bee e eke gee Pe ek 58 Roes ER AE ER EE OO EE EE COP RE Ede ve e Hed totu 59 10 3 6 Burst Sequere ende tum eer ut DEus 59 10 3 7 Glock Edge rper E ero eme iz nite acted xo RR ERU 59 10 3 9 Burst Wraps ict een tried iet b GE aa ee Dr ee E Ee Ee ie 59 10 3 9 B rst Lengtli a ac RE Rede eA AE EN 60 11 0 Programming Operations 7 sse nennen 61 11 1 Word Programming esssssssssssesee eene enne ek ee ee ee ee nnn nennt nennen Re ee ee ee ee ee nnns 61 11 1 1 Factory Word ProgrammiNg iese sesse ee ee ee ek Re ke ee ee ee ee ee ee ee ee ee ee ee ee ee ee 62 11 2 Buffered ProgrammIiNg ie ee ek ee ee ee ee ee ee Ee ke AA ee ee ee ee nennen Re Re Re ee ee ee ee ee ee ee nnns 62 11 3 Buffered Enhanced Factory Programming sesse ee eed ee ee ee ee ee ee ke ee ee ee ee eek ek ke eke ee 63 11 3 1 BEFP Requirements and Considerations iese sesse ee ee ee ee ee ek eke ee ee ee ee ee ee ee 64 11 3 2 BEFP Setup Phase EE Sa ss eet dein Ec eh ANS fet Htec eoe o 64 11 3 3 BEFP Programy Verify Phase eie ees ese ees ee ee ee ee dee ee ee ee ee ee ee rn nnne nnn nenne 64 11 3 4 BEFP Exit Phase sie ese See nee ee tetto En ou des Gee raa e Ee G
56. Edge CE 0 Falling edge 1 Rising edge default 5 4 Reserved R Reserved bits should be cleared 0 April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 54 Order Number 306666 Revision 001 intel Table 22 1 Gbit P30 Family Read Configuration Register Description Sheet 2 of 2 Burst Wrap BW 0 Wrap Burst accesses wrap within burst length set by BL 2 0 1 No Wrap Burst accesses do not wrap within burst length default Burst Length BL 2 0 001 4 word burst 010 8 word burst 011 16 word burst 111 Continuous word burst default Other bit settings are reserved Note 10 3 1 10 3 2 Datasheet Latency Code 2 Data Hold for a 2 clock data cycle DH 1 WAIT must be deasserted with valid data WD 0 Latency Code 2 Data Hold for a 2 cock data cycle DH 1 WAIT deasserted one data cycle before valid data WD 1 combination is not supported Read Mode The Read Mode RM bit selects synchronous burst mode or asynchronous page mode operation for the device When the RM bit is set asynchronous page mode is selected default When RM is cleared synchronous burst mode is selected Latency Count The Latency Count bits LC 2 0 tell the device how many clock cycles must elapse from the rising edge of ADV or from the first valid clock edge after AD V is asserted until the first data word is to be driven onto DQ 15 0 The input clock frequency is used to determine thi
57. Enhanced Factory 0x80 BEFP Setu Program mode BEFP The CUI then waits for the BEFP Confirm command P OxDO that initiates the BEFP algorithm All other commands are ignored when BEFP mode begins gt If the previous command was BEFP Setup 0x80 the CUI latches the address 0XDO BEEF Confirm and data and prepares the device for BEFP mode First cycle of a 2 cycle command prepares the CUI for a block erase operation The WSM performs the erase algorithm on the block addressed by 0x20 Block Erase Setup the Erase Confirm command If the next command is not the Erase Confirm OxDO command the CUI sets Status Register bits SR 4 and SR 5 and places the device in read status register mode Erase If the first command was Block Erase Setup 0x20 the CUI latches the address and data and the WSM erases the addressed block During block OxDO Block Erase Confirm 258 operations the device responds only to Read Status Register and Erase Suspend commands CE or OE must be toggled to update the Status Register in asynchronous read CE or ADV must be toggled to update the Status Register Data for synchronous Non array reads This command issued to any device address initiates a suspend of the currently executing program or block erase operation The Status Register OxBO Program or Erase indicates successful suspend operation by setting either SR 2 program s d Suspend suspended or SR 6 erase suspended along with SR 7 ready The Write uspe
58. FF 11 080000 O8FFFF April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 26 Order Number 306666 Revision 001 intel Table 8 Programming Region 256 Mbit OF0000 OFFFFF Blk 128 Mbit 070000 07FFFF 010000 0O1FFFF 010000 O1FFFF 00C000 00FFFF 00C000 00FFFF 000000 03FFFF 000000 OOFFFF 1 Gbit P30 Family Discrete Bottom Parameter Memory Maps all packages Programming Region 64 Mbit Table 9 512 Mbit Memory Map Easy BGA and QUAD SCSP 512 Mbit Flash 2x256 Mbit w 1CE Flash Die Die Stack Config Size KB Bik Address Range FFCOOO FFFFFF Flash Die 2 FF0000 FF3FFF Top Parameter FE0000 FEFFFF 000000 OOFFFF FF0000 FFFFFF Flash Die 1 Bottom 010000 01FFFF Parameter 00C000 00FFFF 000000 003FFF Note Refer to 256 Mbit Memory Map Table 7 and Table 8 for Programming Region Information Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 27 1 Gbit P30 Family I n Table 10 1 Gbit Memory Map QUAD SCSP only 1 Gbit Flash 4x256 Mbit w 2CE Flash Die Die Stack Config Size KB BIk Address Range 32 258 FFCO00 FFFFFF i Flash Die 4 32 255 FF0000 FF3FFF Top Parameter 128 2
59. FFF 120 780000 78FFFF 380000 38FFFF 128 239 EF0000 EFFFFF 119 770000 77FFFF 370000 37FFFF 14 128 f 224 E00000 EOFFFF 112 700000 70FFFF 300000 30FFFF 128 223 DF0000 DFFFFF f 111 6F0000 6FFFFF 2F0000 2FFFFF 13 128 208 D00000 DOFFFF 104 680000 68FFFF 280000 28FFFF 128 207 CF0000 CFFFFF 103 670000 67FFFF 270000 27FFFF 12 128 192 C00000 COFFFF 96 600000 60FFFF 200000 20FFFF 128 f 191 BF0000 BFFFFF 95 5F0000 5FFFFF 1F0000 1FFFFF 11 128 f 176 B00000 BOFFFF 88 580000 S8FFFF 180000 18FFFF 128 175 AF0000 AFFFFF J 87 570000 57FFFF 170000 17FFFF 10 128 160 A0000 AOFFFF 80 500000 50FFFF 100000 10FFFF 128 159 9F0000 9FFFFF 79 4F0000 4FFFFF OF0000 OFFFFF 9 128 144 900000 90FFFF 72 480000 48FFFF 080000 08FFFF 128 143 8F0000 8FFFFF 71 470000 47FFFF 070000 07FFFF 8 128 128 800000 80FFFF 64 400000 40FFFF 000000 OOFFFF 128 127 7F0000 7FFFFF f 63 3F0000 3FFFFF 7 128 f 112 700000 70FFFF 56 380000 38FFFF April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 24 Order Number 306666 Revision 001 intel Table 7 Programming Region Discrete Top Parameter Memory Maps all packages 256 Mbit 6F0000 6FFFFF 128 Mbit 370000 37FFFF 600000 60FFFF 300000 30FFFF 5F0000 SFFFFF 2F0000 2FFFFF 500000 SOFFFF 28000
60. FI compliant device outputs 00h data on upper bytes The device outputs ASCII Q in the low byte DQ 9 and 00h in the high byte DQ 5 g At Query addresses containing two or more bytes of information the least significant data byte is presented at the lower address and the most significant data byte is presented at the higher address In all of the following tables addresses and data are represented in hexadecimal notation so the h suffix has been dropped In addition since the upper byte of word wide devices is always OOh the leading 00 has been dropped from the table notation and only the lower byte value is shown Any x16 device outputs can be assumed to have 00h on the upper byte in this mode Summary of Query Structure Output as a Function of Device and Mode Device Hex Hex ASCII Offset Code Value 00010 51 O Device Addresses 00011 52 R 00012 59 y Example of Query Structure Output of x16 Devices Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 93 1 Gbit P30 Family C 2 Table 33 April 2005 94 Word Addressing Offset Hex Code Ax Ao Dis Do 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h Query Structure Overview PrVendor ID PrVendor TblAdr AltVendor ID 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h Byte Addressing Hex Code D Do
61. IT T i ik gt R304 ke L R4 l gt R7 i lt gt R305 R305 R305 e R305 Data Dg 34 KOEK Notes 1 WAIT is driven per OE assertion during synchronous array or non array read and can be configured to assert either during or one data cycle before valid data 2 At the end of Word Line the delay incurred when a burst access crosses a 16 word boundary and the starting address is not 4 word boundary aligned April 2005 40 Intel StrataFlash Embedded Memory P30 Order Number 306666 Revision 001 Datasheet Figure 21 Synchronous Burst Mode Four Word Read Timing 1 Gbit P30 Family R302 4 CLK Address ADV CE E OE G WAIT T Data D Q 3 C Q0 Note WAIT is driven per OE assertion during synchronous array or non array read WAIT asserted during initial latency and deasserted during valid data RCR 10 0 Wait asserted low 7 4 AC Write Specifications Table 18 AC Write Specifications Sheet 1 of 2 Num Symbol Parameter Min Max Units Notes W1 teow RST high recovery to WE low 150 ns 1 2 3 W2 tewe CE setup to WE low 0 ns 1 2 3 W3 twwu WE write pulse width low 50 ns 1 2 4 WA tpywn Data setup to WEZ high 50 ns W5 tawny
62. In es Intel StrataFlash Embedded Memory P30 1 Gbit P30 Family Datasheet Product Features W High performance W Security 85 88 ns initial access One Time Programmable Registers 40 MHz with zero wait states 20 ns clock to 64 unique factory device identifier bits data output synchronous burst read mode 64 user programmable OTP bits 25 ns asynchronous page read mode Additional 2048 user programmable OTP bits 4 8 16 and continuous word burst mode Selectable OTP Space in Main Array Buffered Enhanced Factory Programming 4x32KB parameter blocks 3x128KB main BEFP at 5 pis byte Typ blocks top or bottom configuration 1 8 V buffered programming at 7 ps byte Typ Absolute write protection Vpp Vss Power transition erase program lockout Individual zero latency block locking Individual block lock down W Architecture Multi Level Cell Technology Highest Density at Lowest Cost Asymmetrically blocked architecture W Software Four 32 KByte parameter blocks top or 20 ys Typ program suspend bottom configuration 20 us Typ erase suspend 128 KByte main blocks Intel Flash Data Integrator optimized W Voltage and Power Basic Command Set and Extended Command Vcc core voltage 1 7 V 2 0 V Set compatible Vccq I O voltage 1 7 V 3 6 V Common Flash Interface capable Standby current 55 pA Typ for 256 Mbit W Density and Pac
63. Intel StrataFlash Embedded Memory P30 Datasheet 32 Order Number 306666 Revision 001 1 Gbit P30 Family AC Characteristics 7 1 Figure 13 Figure 14 Table 14 Figure 15 Datasheet AC Test Conditions AC Input Output Reference Waveform Veco Input Vecol2 Test Points Vecol2 Output NV Note AC test inputs are driven at Vcco for Logic 1 and 0 0 V for Logic 0 Input output timing begins ends at Vcco 2 Input rise and fall times 10 to 9096 lt 5 ns Worst case speed occurs at Vec VccMin Transient Equivalent Testing Load Circuit Device Under Test NOTES 1 See the following table for component values 2 Test configuration component value for worst case speed conditions 3 C includes jig capacitance Test configuration component value for worst case speed conditions Test Configuration C pF VccoMin Standard Test 30 Clock Input AC Waveform CLK C Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 33 1 Gbit P30 Family I n 7 2 Capacitance Table 15 Capacitance Symbol Parameter Signals Min Typ Max Unit Condition Note Address Data Typ temp 25 C Cin Input Capacitance t 2 6 7 pF Max temp 85 C 123 AOV Wi DereeSiondie Cour Output Capacitance Data WAIT 2 4 5 pF NOTES 1 Capacitance values are for
64. LE Active low input OE low enables the device s output data buffers during read Input cycles OE high places the data outputs and WAIT in High Z F2 OE F1 OE and F2 OE should be tied together for all densities RESET Active low input RST resets internal automation and inhibits write operations This RST Input provides data protection during power transitions RST high enables normal operation Exit from reset places the device in asynchronous read array mode WAIT Indicates data valid in synchronous array or non array burst reads Read Configuration Register bit 10 RCR 10 WT determines its polarity when asserted WAIT s active output is Vo or Vou when CE and OE are Vi WAIT is high Z if CE or OE is Vin WAT Output In synchronous array or non array read modes WAIT indicates invalid data when asserted and valid data when deasserted n asynchronous page mode and all write modes WAIT is deasserted WRITE ENABLE Active low input WE controls writes to the device Address and data are latched WEZ Input Ss on the rising edge of WEZ Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 21 1 Gbit P30 Famil y I n e Table 4 QUAD SCSP Signal Descriptions Sheet 2 of 2 Symbol Type Name and Function WRITE PROTECT Active low input WP low enables the lock down mechanism Blocks in lock WP Input down cannot be unlocked with the Unlock co
65. OOOO D gt OOOOOOOO E E OOOOOOOO F gt COOOOOOG4 G s OOOOOOOGQO u 66060000 J 1 OOOOOOOO K OOOOOOOO L L OOOOOOOO M M p OO a gt al a Top View Ball Down Bottom View Ball Up A2 Y N p cce EEN ZN TY Drawing not to scale 0 0 0 Milimetes Max 1 0 200 0 0079 10 0 0167 Package Body Length 11 000 0 4370 Package Body Width 11000 11 100 0 4291 0 4370 80 Ball tead Count 1 N 8 Seating Plane Coplanarity 0 0039 Comer to Ball A1 Distance Along E 2 700 2 800 0 1024 0 1102 Comer to Ball A1 Distance Along D S2 1 000 1 100 1 200 0 0394 0 0433 0 0472 April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 16 Order Number 306666 Revision 001 l n e 1 Gbit P30 Family 4 0 Ballout and Signal Descriptions 4 1 Signal Ballout Figure 7 56 Lead TSOP Pinout 64 128 256 Mbit WAIT A17 DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Intel StrataFlash ADV Embedded Memory P 30 AR i VPP 56 Lead TSOP Pinout DQ11 14 mm x 20 mm DQ3 DQ10 Top View DQ2 VCCQ DQ9 DQ1 DQ8 DQO VCC OE VSS CE A1 ODNDUNBRWNER 1 A1 is the least significant address bit 2 A23 is valid for 128 Mbit densities and above otherwise it is a no connect NC 3 A24 is valid for 256 Mbit densities and above otherwise it is a no connect NC Datasheet Intel StrataFlash Embedded Memory P30 Apr
66. Revision 001 intel 1 Gbit P30 Family Table 17 AC Read Specifications for 256 512 Mbit and 1 Gbit Densities Sheet 2 of 2 Num Symbol Parameter Speed Min Max Unit Notes R101 TAVVH Address setup to ADV high 10 ns R102 tervH CE low to ADV high 10 ns Vcc 1 8V 2 0V 85 R103 ty ovy ADV low to output valid ns 1 Vcc 1 7V 2 0V 88 R104 tyi vn ADV pulse width low 10 ns R105 tyuv ADV pulse width high 10 ns R106 tvHax Address hold from ADV high 9 ns 1 4 R108 TAPA Page address access 25 ns 1 R111 tphvh RST high to ADV high 30 ns Clock Specifications R200 fork CLK frequency 40 MHz R201 terk CLK period 25 ns 1 3 6 R202 tone CLK high low time 5 ns R203 TECLKIRCLK CLK fall rise time 3 ns Synchronous Specifications R301 TAVCHIL Address setup to CLK 9 ns R302 tcu ADV low setup to CLK 9 ns 1 R303 te cu CE low setup to CLK 9 ns R304 tengv terov CLK to output valid 20 ns R305 tchox Output hold from CLK 3 ns 1 5 R306 TCHAX Address hold from CLK 10 ns 1 4 5 R307 touty CLK to WAIT valid 20 ns 1 5 R311 TCHVL CLK Valid to ADV Setup 3 ns 1 R312 tcurx WAIT Hold from CLK 3 ns 1 5 NOTES T See Figure 13 AC Input Output Reference Waveform on page 33 for timing measurements and max allowable input slew rate 2 OE may be delayed by up to tg oy tai ovy after CEZ s falling edge without impac
67. SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice This document contains information on products in the design phase of development The information here is subject to change without notice Do not finalize a design with this information StrataFlash Embedded Memory P30 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Copyright 2005 Intel Corporation Other names and brands may be claimed as the property of others April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 2 Order Number 306666 Revision 001 j ntel o 1 Gbit P30 Family Contents 1 0 MENU LD eaa EE EN 7 L1 erue 7 MED unge 7 L3 ec LI mE 8
68. WSM ready 0 WSM busy Check SR 6 1 Erase suspended 0 Erase completed If the suspended partition was placed in Read Array mode or a Program Loop T mem Preturnparition seus mods Erase Resume ciel l Write Status fData 0x70 y Register Addr Same partition Les s H Erase Write OxFF r Write 0x70 1 Read Array ed zs Same Partition April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 90 Order Number 306666 Revision 001 intel Figure 46 Datasheet Block Lock Operations Flowchart 1 Gbit P30 Family Optional LOCKING OPERATIONS PROCEDURE Write Ox60 Block Address Lock Setup Write either 0x01 0xD0 0x2F Block Address Lock Confirm Write 0x90 Read Block Lock Status Read Device ID Write OxFF Partition Address Read ra Lock Change Complete Write Lock Data 0x60 Setup Addr Block to lock unlock lock down Lock Data 0x01 Block Lock Write Unlock or OxDO Block Unlock Lock Down Ox2F Lock Down Block Confirm Addr Block to lock unlock lock down Operation Write Read Data 0x90 Optional Device ID Addr Block address offset 2 Read Block Lock Block Lock status data Optional Status Addr Block address offset 2 oe ee Confirm locking change on D 1 0 Write Read Data OxFF Array Addr Block address Intel StrataFlash Embedded Memory P30 Order Number 306666 Revision 001
69. a single die for 2 die and 4 die stacks multiple the above values by the number of die in the stack 2 Sampled not 100 tested 3 Silicon die capacitance only add 1 pF for discrete packages April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 34 Order Number 306666 Revision 001 l n 1 Gbit P30 Family 7 3 AC Read Specifications Table 16 AC Read Specifications for 64 128 Mbit Densities Sheet 1 of 2 Num Symbol Parameter Min Max Unit Notes Asynchronous Specifications R1 tavav Read cycle time 85 ns R2 tavev Address to output valid 85 ns R3 tergov CE low to output valid 85 ns R4 tergov OE low to output valid 25 ns 1 2 R5 tenov RST high to output valid 150 ns 1 R6 teLox CE low to output in low Z 0 ns 1 3 R7 teLox OE low to output in low Z 0 ns 1 2 3 R8 tenoz CE high to output in high Z 24 ns R9 cuoz OE high to output in high Z 24 ns 1 3 R10 tou Output hold from first occurring address CE or OE change 0 ns R11 tener CE pulse width high 20 ns R12 terry CE low to WAIT valid 17 ns R13 ikir CE high to WAIT high Z z 20 ns 13 R15 teu OE low to WAIT valid 17 ns 1 R16 tGLTX OE low to WAIT in low Z 0 ns R17 tGHTZ OE high to WAIT in high Z 20 ns ue Latching Specifications R101 TAVVH Address setup to ADV high 10
70. ase Program BP Setup in ei Suspend Setup in Erase Erase Suspend Erase Busy Erase Suspend p Suspend Erase Erase Suspend Suspend Suspend P April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 78 Order Number 306666 Revision 001 l n 1 Gbit P30 Family Figure 35 Write State Machine Next State Table Sheet 2 of 6 NEED Command Input to Chip and resulting Chip Next State Buffered BE Confirm Buffered Enhanced P E BP Prg Read Clear Read Lock Unlock Current Chi j Program FAON Pom Resume Erase Satis Status inoue Lock down P Eg ULB Suspend Register Query oR setup State SENI Confirm 9 80H DOH BOH 50H 90H 98H 60H Word Program Busy in Erase Suspend Word Program w Busy Word Program Busy in Erase Suspend Suspend in Word Program Busy in Erase Suspend Busy ord Erase Program in Suspend Erase Suspend Word Program Suspend Word Program Suspend in Erase Suspend Busy in Word Program Suspend in Erase Suspend Erase Suspend BP Load 2 BP Confirm if Data load into Program Buffer is complete Else BP Load 2 BP in Erase BP BP Busy in Suspend Confirm Erase Suspend Error iras Ready Error in Erase Suspend BP Suspend BP Busy BP Busy in Erase Suspend in Erase BP Busy in Erase Suspend Suspend BP BP Busy in BP Suspend in Erase Suspend Erase BP Suspend in Erase Suspend Suspend Suspend Erase Suspend Unlock Block BEFP Buffered Ready Error Loading Ready Error Enha
71. be left floating NC No Connect No internal connection can be driven or floated 4 3 SCSP Configurations Table 5 Stacked Easy BGA Chip Select Logic TNR Selected Flash Selected Flash Stack Combination Die 1 Die 2 1 die F1 CE 2 die F1 CE A25 Vi F1 CE A25 Vi Table 6 QUAD SCSP Chip Select Logic Stack Selected Flash Selected Flash Selected Flash Selected Flash Combination Die 1 Die 2 Die 3 Die 4 1 die F1 CE 2 die F1 CE A24 Vj F1 CE A24 Vi 4 die F1 CE A24 Vj F1 CE A24 Vy F2 CE A24 Vi F2 CE A24 Vip April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 22 Order Number 306666 Revision 001 1 Gbit P30 Family Figure 10 512 Mbit Easy BGA Device Block Diagram Easy BGA 2 Die 512 Mbit Device Configuration F1 CE I e 5 Flash Die 1 WP 256 Mbit ii Reale OE a VCC WE i VEP CLK 4 VCCQ ADV ms IK4 VSS Flash Die 2 256 Mbit A MAX 1 r POLES m WAIT Figure 11 512 Mbit QUAD SCSP Device Block Diagram QUAD 2 Die 512 Mbit Device Configuration F1 CE e Flash Die 1 WP4 256 Mbit I RST OE 3 IF4
72. d deasserting CE places the device in standby reducing active current Vpp must remain at its programming level and WP must remain unchanged while in program suspend If RST is asserted the device is reset Program Resume The Resume command instructs the device to continue programming and automatically clears Status Register bits SR 7 2 This command can be written to any address If error bits are set the Status Register should be cleared before issuing the next instruction RST must remain deasserted see Figure 41 Program Suspend Resume Flowchart on page 86 Program Protection When Vpp V absolute hardware write protection is provided for all device blocks If Vpp is at or below Vpp g programming operations halt and SR 3 is set indicating a V pp level error Block lock registers are not affected by the voltage level on Vpp they may still be programmed and read even if Vpp is less than Vpp x Example VPP Supply Connections Veo VCC Vec VCC Vig VPP PROT VPP e Low voltage Programming only e Factory Programming with Vpp Vopu Logic Control of Device Protection e Complete write Erase Protection when V Vec VCC Vec VCC Vpp VppH VPP VPP e Low Voltage Programming Only Low Voltage and Factory Programming e Full Device Protection Unavailable Intel StrataFlash Embedded Memory P30 Datasheet Order Number 306666 Revision 001 Intel 12 0 1 Gbit P30 Family Erase Operations
73. d Memory P30 Datasheet Order Number 306666 Revision 001 intel 1 Gbit P30 Family Appendix C Common Flash Interface C 1 Table 31 Table 32 Datasheet The Common Flash Interface CFT is part of an overall specification for multiple command set and control interface descriptions This appendix describes the database structure containing the data returned by a read operation after issuing the CFI Query command see Section 9 2 Device Commands on page 50 System software can parse this database structure to obtain information about the flash device such as block size density bus width and electrical specifications The system software will then know which command set s to use to properly perform flash writes block erases reads and otherwise control the flash device Query Structure Output The Query database allows system software to obtain information for controlling the flash device This section describes the device s CFI compliant interface that allows access to Query data Query data are presented on the lowest order data outputs DQ 9 only The numerical offset value is the address relative to the maximum bus width supported by the device On this family of devices the Query table device starting address is a 10h which is a word address for x16 devices For a word wide x16 device the first two Query structure bytes ASCII Q and R appear on the low byte at word addresses 10h and 11h This C
74. d latency is specified in Section 7 5 Program and Erase Characteristics on page 45 Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 67 1 Gbit P30 Family ntel amp 12 3 12 4 April 2005 68 To read data from the device other than an erase suspended block the Read Array command must be issued During Erase Suspend a Program command can be issued to any block other than the erase suspended block Block erase cannot resume until program operations initiated during erase suspend complete Read Array Read Status Register Read Device Identifier CFI Query and Erase Resume are valid commands during Erase Suspend Additionally Clear Status Register Program Program Suspend Block Lock Block Unlock and Block Lock Down are valid commands during Erase Suspend During an erase suspend deasserting CE places the device in standby reducing active current Vpp must remain at a valid level and WP must remain unchanged while in erase suspend If RST is asserted the device is reset Erase Resume The Erase Resume command instructs the device to continue erasing and automatically clears status register bits SR 7 6 This command can be written to any address If status register error bits are set the Status Register should be cleared before issuing the next instruction RST must remain deasserted see Figure 41 Program Suspend Resume Flowchart on page 86 Erase Protection When Vpp Vi
75. dershoot to 2 0 V for periods lt 20 ns Maximum DC voltage on Vec is Vcc 0 5 V which during transitions may overshoot to Vcc 2 0 V for periods lt 20 ns Maximum DC voltage on input output signals and Veco is Vccg 0 5 V which during transitions may overshoot to Veco 2 0 V for periods lt 20 ns 3 Maximum DC voltage on Vpp may overshoot to 11 5 V for periods lt 20 ns 4 Program erase voltage is typically 1 7 V 2 0 V 9 0 V can be applied for 80 hours maximum total to any blocks for 1000 cycles maximum 9 0 V program erase voltage may reduce block cycling capability 5 Output shorted for no more than one second No more than one output shorted at a time Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 29 1 Gbit P30 Family I n e 5 2 Operating Conditions Note Operation beyond the Operating Conditions is not recommended and extended exposure beyond the Operating Conditions may affect device reliability Table 11 Operating Conditions Symbol Parameter Min Max Units Notes Te Operating Temperature 40 85 C 1 2 Vec VCC Supply Voltage 1 7 2 0 CMOS inputs 1 7 3 6 Vcco VO Supply Voltage TTL inputs 2 4 3 6 V Vpp Vpp Voltage Supply Logic Level 0 9 3 6 Vppu Factory word programming Vpp 8 5 9 5 tppy Maximum VPP Hours Vpp VppH 80 Hours 3 Block Main and Parameter Blocks Vpp Vec 100 000
76. e N 0x00 to Ox1F g Y 2 The device outputs the Status Register when read E Buffer Program Data mo id Buffer contents will be programmed at the issued word Do Start Word Address F less co 4 Align the start address on a Write Buffer boundary for 8 2 v 4 maximum programming performance i e A 4 0 of the Start 8 E Write Buffer Data Word Address 0x00 5Sa mee Word Address 5 The Buffered Programming Confirm command must be 9 amp issued to an address in the same block for example the eo original Start Word Address or the last address used during the se loop that loaded the buffer data so 6 The Status Register indicates an improper command 2 ii sequence if the Buffer Program command is aborted use the SO Clear Status Register command to clear error bits Zo 7 The Status Register can be read from any address within as T the programniing partition EU E 2 Write Confirm OxDO Full status check can be done after all erase and write 66 8 and Word Address Y sequences complete Write OxFF after the last operation to V Note 5 Issue Read lace the partition in the Read Array state 5 Status Register va Command g o Read Status Register la i o Note 7 2 3 22 as o eR 5 1 Yes ot v 2 o Full Status os Check if Desired Eg 8 SSS ua Program Complete EB on i Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 87 1 Gbit P30 Family Figure 43
77. e av EEN koe o ee d 65 11 4 Programi Suspend EE RE rte M Eer ER euer e UP yaa DINE ta NGK e ba eee EE 65 11 5 Program Res me Sie e RE Ee ICH Ee oe i e d ES ee He E s Eed SE n VEN Re Ne Be dee 66 11 6 Program Protection oet eed pene EE OE ken dag Rn ete 66 12 0 Erase Opefdli ns io ie albeit R ai a petia ahah whi ke GE Ge ee ae tiu 67 12 1 ee da OE RE p Eg ava Dal in Rolin Basse apo is 67 12 2 dIE od EA EE OE EE ONT E hana ORE RE AE vd N 67 12 3 di SUUR RE EE RE RE EE eq ea ERE OOK a gees 68 12 4 Erase ProteENOP iieri etes Ne SE EE Oe vee EE Ee Ne SR Ge eden SEG Ge EE DER ed Ee Ee De 68 13 0 Security Mode N PR OR pa RR ARN doa e AA a 69 13 1 Block bocklng 2 etit tet reli etta teet t qiero gu gee De rete cdd en eend 69 13 1 1 Bel ds eie SR in ot un EE ER RE ER e HE cde Yep bae ERE e o EXER ES 69 13 1 2 VI ee doele EE ee in RE N ee OE RS 69 13 1 3 bock Down BIOCK i e b te te EE EB Ee Ee pt 69 13 1 4 Block LOCK Status i s ott et ecce lee rnt eter eee t et beet petuo det as 70 13 1 5 Block Locking During Suspend esse eke RR Re ee ee ee ee ee enne 70 13 2 Selectable One Time Programmable BlOCKS ie ee ee ee RR ER AA Ak AA Re ee ee 71 13 3 Protection REJIS e S epe tr Vee EE tpe Me Pete ea LR Ee e een ER be ea en Ee ee ie 72 13 3 1 Reading the Protection Registers eene 73 13 3 2 Programming the Protection RegisterS iese ee ek AR Re ee ee ee ee ee 73 13 3 3 Locking the Protection Registers e
78. e eke eke ee ee ee ee Re nennen 74 14 0 Special Read States EE eae eae 75 14 1 Read Status Register eene deett atate enda aida nae ea enn don iran dis 75 14 1 1 Clear Status Register te eoe Dei ee A e pta eer pe d ce edes 76 14 2 Read Device Identifier Ese EDE cie eset dose er acr b Ce De e ta ie ie e aet Ego c 76 April 2005 4 Intel StrataFlash Embedded Memory P30 Datasheet Order Number 306666 Revision 001 i ntel F 1 Gbit P30 Family Pike died EE teer EE EE A A b naan 7T Appendix A Write State Machine ee ee seen 78 Appendix B Flowcharts ee ee ee ee ee ee ee Ge ee ee retener netta tete se terea es 85 Appendix C Common Flash Interface sess sse 93 Appendix D Additional Information sess 100 Appendix E Ordering Information for Discrete Products 101 Appendix F Ordering Information for SCSP Products 102 Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 5 1 Gbit P30 Family Revision History Revision Date Revision Description April 2005 001 Initial Release April 2005 6 Intel StrataFlash Embedded Memory P30 Order Number 306666 Revision 001 Datasheet 1 0 Introduction 1 Gbit P30 Family This document provides information about the Intel StrataFlash Embedded Memory P30 device and describes its features operation a
79. e erases in bulk 2 x specifies the number of device regions with one or See table below more contiguous same size erase blocks 3 Symmetrically blocked partitions have one blocking region Erase Block Region 1 Information bits 0 15 y y 1 number of identical size erase blocks bits 16 31 z region erase block s size are z x 256 bytes See table below Erase Block Region 2 Information bits 0 15 y y 1 number of identical size erase blocks bits 16 31 z region erase block s size are z x 256 bytes See table below Reserved for future erase block region information See table below April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 96 Order Number 306666 Revision 001 intel C 5 Table 37 Datasheet Intel Specific Extended Query Table Primary Vendor Specific Extended Query Offset Length Description Hex P 10Ah Optional flash features and commands Code Value Primary extended query table Unique ASCII string PRI Optional feature and comand support 1 yes 0 no bits 10 31 are reserved undefined bits are 0 If bit 31 is 1 then another 31 bit field of Optional features follows at the end of the bit 30 field bit O Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock unlock supported bit 4 Queued erase supported bit 5 Instant individual block locking supported bit 6 Protection bits supported bit 7 Pagemode r
80. ead ma j ma nnm 7 OE Vin Current Synchronous Burst 15 19 na na mA BL 8W Inputs Vi or Vin f 40 MHz 17 21 ma na mA BL 16W 21 26 n a n a mA BL Cont lccw Vcc Program Current 36 51 36 51 S Vpp VppL pgny ers in progress 1 3 4 7 lcce Vcc Erase Current 26 33 26 33 Vpp Vppy pgm ers in progress 1 3 5 7 64 Mbit 20 35 20 35 Vec Program 128 Mbit 30 75 30 75 l Suspend Current c i cows SUSP 256 Mbit 55 115 55 200 pa CE Vcco suspend in 136 lCCES Vcc Erase progress Suspend Current 512 Mbit 110 230 110 400 1 Gbit 220 460 220 800 Ipps Vpp Standby Current Ippws Vpp Program Suspend Current 0 2 5 0 2 5 HA Vpp Vpp_ Suspend in progress 1 3 Ippes Vpp Erase Suspend Current IppR Vpp Read 2 15 2 15 HA Vpp lt Vec 1 3 Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 31 1 Gbit P30 Family I n e Table 12 DC Current Characteristics Sheet 2 of 2 TTL Inputs Inputs E Veco Veco Sym Parameter 17 ves 6 V 2 4 V 3 6 V Unit Test Conditions Notes Typ Max Typ Max 0 05 0 10 0 05 0 10 Vpp VppL program in progress Ippw Vpp Program Current mA 8 22 8 22 Vpp Vppy program in progress 0 05 0 10 0 05 0 10 Vpp Vpp_ erase in progress Ippe Vpp Erase Current mA 8 22 8 22 Vpp Vppu erase in progress 1 All currents are RMS unless noted Typical values at typica
81. ead supported bit 8 Synchronous read supported bit 9 Simultaneous operations supported bit 10 Extended Flash Array Blocks supported bit 30 CFI Link s to follow bit 31 Another Optional Features field to follow Supported functions after suspend read Array Status Query Other supported operations are bits 1 7 reserved undefined bits are 0 bit O Program supported after erase suspend Block status register mask bits 2 15 are Reserved undefined bits are 0 bit O Block Lock Bit Status register active bit 1 Block Lock Dow n Bit Status active bit 4 EFA Block Lock Bit Status register active bit 5 EFA Block Lock Down Bit Status active Vec logic supply highest performance programverase voltage bits 0 3 BCD value in 100 mV bits 4 7 BCD value in volts pp Optimum program erase supply voltage bits 0 3 BCD value in 100 mV bits 4 7 HEX value in volts Intel StrataFlash Embedded Memory P30 Order Number 306666 Revision 001 1 Gbit P30 Family e9n 1 Mworversonmumber ASK top ER AM BOE ES EE NRI Mid April 2005 97 1 Gbit P30 Family Table 38 Table 39 April 2005 98 Protection Register Information Offset Length Description P 10Ah Optional flash features and commands Add P F h P 10 h P 11 h P 12 h P 13 h P 14 h P 15 h P 16 h P 17 h P 18 h P 19 h P 1A h P 1B h P 1C h Number of Protection register fields in JEDEC ID space 00h indicates tha
82. ed down Hardware Software locked 011 states should be tracked by system software to determine difference between Hardware Locked and Locked Down states as Block Locking During Suspend Block lock and unlock changes can be performed during an erase suspend To change block locking during an erase operation first issue the Erase Suspend command Monitor the Status Register until SR 7 and SR 6 are set indicating the device is suspended and ready to accept another command Next write the desired lock command sequence to a block which changes the lock state of that block After completing block lock or unlock operations resume the erase operation using the Erase Resume command A Lock Block Setup command followed by any command other than Lock Block Unlock Block or Lock Down Block produces a command sequence error and set Status Register bits SR 4 and Intel StrataFlash Embedded Memory P30 Datasheet Order Number 306666 Revision 001 13 2 Table 27 Datasheet 1 Gbit P30 Family SR 5 If a command sequence error occurs during an erase suspend SR 4 and SR 5 remains set even after the erase operation is resumed Unless the Status Register is cleared using the Clear Status Register command before resuming the erase operation possible erase errors may be masked by the command sequence error If a block is locked or locked down during an erase suspend of the same block the lock status bits change immed
83. erase operations Designed for low voltage systems the 1 Gbit P30 Family supports read operations with Vcc at 1 8 V and erase and program operations with V pp at 1 8 V or 9 0 V Buffered Enhanced Factory Programming BEFP provides the fastest flash array programming performance with Vpp at 9 0 V which increases factory throughput With Vpp at 1 8 V VCC and VPP can be tied together for a simple ultra low power design In addition to voltage flexibility a dedicated VPP connection provides complete data protection when Vpp lt VPPLK A Command User Interface CUT is the interface between the system processor and all internal operations of the device An internal Write State Machine WSM automatically executes the algorithms and timings necessary for block erase and program A Status Register indicates erase or program completion and any errors that may have occurred An industry standard command sequence invokes program and erase automation Each erase operation erases one block The Erase Suspend feature allows system software to pause an erase cycle to read or program data in another block Program Suspend allows system software to pause programming to read other locations Data is programmed in word increments 16 bits The 1 Gbit P30 Family s protection register allows unique flash device identification that can be used to increase system security The individual Block Lock feature provides zero latency block locking and unlocking In add
84. erations Full Status Register check can be done after each program or after a sequence of program operations Write OxFF after the last operation to set to the Read Array state FULL STATUS CHECK PROCEDURE Operation Check SR 3 jae me PEER O Non If an error is detected clear the Status Register before continuing operations only the Clear Staus Register command clears the Status Register error bits Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 85 1 Gbit P30 Family Figure 41 April 2005 86 Program Suspend Resume Flowchart PROGRAM SUSPEND RESUME PROCEDURE Program Completed Write FFh Pgm d Partition Read Array Data Read Status write 70h l Same Partition Bus Write Program Data BOh Suspend Addr Block to suspend BA n Read Data 70h id s partition Read Status register data Addr Suspended block BA Check SR 7 Standby 1 WSM ready 0 WSM busy Check SR 2 Standby 1 Program suspended 0 Program completed Data FFh Write Rean Addr Any address within the Array suspended partition Read array data from block other than the one being programmed Read Program Data DOh Write Resume Addr Suspended block BA If the suspended partition was placed in Read Array mode M EA SE Reid Return partition to Status mode I I Write Status Data 70h Addr Same partition l
85. eserved for Future Use RFU Note Always clear the Status Register prior to resuming erase operations It avoids Status Register ambiguity when issuing commands during Erase Suspend If a command sequence error occurs during an erase suspend state the Status Register contains the command sequence error status SR 7 5 4 set When the erase operation resumes and finishes possible errors during the erase operation cannot be detected via the Status Register because it contains the previous error status 14 1 1 Clear Status Register The Clear Status Register command clears the status register It functions independent of Vpp The Write State Machine WSM sets and clears SR 7 6 2 but it sets bits SR 5 3 1 without clearing them The Status Register should be cleared before starting a command sequence to avoid any ambiguity A device reset also clears the Status Register 14 2 Read Device Identifier The Read Device Identifier command instructs the device to output manufacturer code device identifier code block lock status protection register data or configuration register data see Section 9 2 Device Commands on page 50 for details on issuing the Read Device Identifier command Table 29 Device Identifier Information on page 77 and Table 30 Device ID codes on page 77 show the address offsets and data values for this device April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 76 Order Number 306666 Revision 001 In
86. for a cumulative total not to exceed 80 hours Extended use of this pin at 9 V may reduce block cycling capability VCC Power Device Core Power Supply Core logic source voltage Writes to the flash array are inhibited when Vcc lt Vi ko Operations at invalid Vcc voltages should not be attempted April 2005 20 Intel StrataFlash Embedded Memory P30 Datasheet Order Number 306666 Revision 001 l n o 1 Gbit P30 Family Table 3 TSOP and Easy BGA Signal Descriptions Sheet 2 of 2 Symbol Type Name and Function VCCQ Power Output Power Supply Output driver source voltage VSS Power Ground Connect to system ground Do not float any VSS connection REU E Reserved for Future Use Reserved by Intel for future device functionality and enhancement These should be treated in the same way as a Do Not Use DU signal DU Do Not Use Do not connect to any other signal or power supply must be left floating NC No Connect No internal connection can be driven or floated Table 4 QUAD SCSP Signal Descriptions Sheet 1 of 2 Symbol Type Name and Function ADDRESS INPUTS Device address inputs 64 Mbit A 21 0 128 Mbit A 22 0 256 Mbit A 23 0 512 Mbit A 24 0 A MAX 0 Input z See Table 6 on page 22 Figure 11 on page 23 and Figure 12 on page 23 for 512 Mbit and 1 Gbit addressing Input DATA INPUT OUTPUTS Inputs data and commands during write cycles
87. gure 42 Buffer Program Flowchart on page 87 On the next write a word count is written to the device at the buffer address This tells the device how many data words will be written to the buffer up to the maximum size of the buffer Intel StrataFlash Embedded Memory P30 Datasheet Order Number 306666 Revision 001 11 3 Datasheet 1 Gbit P30 Family On the next write a device start address is given along with the first data to be written to the flash memory array Subsequent writes provide additional device addresses and data All data addresses must lie within the start address plus the word count Optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 32 word boundary A 4 0 0x00 Crossing a 32 word boundary during programming will double the total programming time After the last data is written to the buffer the Buffered Programming Confirm command must be issued to the original block address The WSM begins to program buffer contents to the flash memory array If a command other than the Buffered Programming Confirm command is written to the device a command sequence error occurs and Status Register bits SR 7 5 4 are set If an error occurs while writing to the array the device stops programming and Status Register bits SR 7 4 are set indicating a programming failure When Buffered Programming has completed additional buffer writes can be initia
88. hen exiting the BEFP algorithm with a block address change the read mode will not change After BEFP exit any valid command can be issued to the device Program Suspend Issuing the Program Suspend command while programming suspends the programming operation This allows data to be accessed from the device other than the one being programmed The Program Suspend command can be issued to any device address A program operation can be suspended to perform reads only Additionally a program operation that is running during an erase suspend can be suspended to perform a read operation see Figure 41 Program Suspend Resume Flowchart on page 86 Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 65 1 Gbit P30 Family ntel amp 11 5 11 6 Figure 31 April 2005 66 When a programming operation is executing issuing the Program Suspend command requests the WSM to suspend the programming algorithm at predetermined points The device continues to output Status Register data after the Program Suspend command is issued Programming is suspended when Status Register bits SR 7 2 are set Suspend latency is specified in Section 7 5 Program and Erase Characteristics on page 45 To read data from the device the Read Array command must be issued Read Array Read Status Register Read Device Identifier CFI Query and Program Resume are valid commands during a program suspend During a program suspen
89. iately However the erase operation completes when it is resumed Block lock operations cannot occur during a program suspend See Appendix A Write State Machine on page 78 which shows valid commands during an erase suspend Selectable One Time Programmable Blocks Any of four pre defined areas from the main array the four 32 KB parameter blocks together as one and the three adjacent 128 KB main blocks can be configured as One Time Programmable OTP so further program and erase operations are not allowed This option is available for top or bottom parameter devices Selectable OTP Block Mapping Density Top Parameter Configuration Bottom Parameter Configuration blocks 258 255 parameters blocks 3 0 parameters block 254 main block 4 main 256 Mbit block 253 main block 5 main block 252 main block 6 main blocks 130 127 parameters blocks 3 0 parameters block 126 main block 4 main 128 Mbit block 125 main block 5 main block 124 main block 6 main blocks 66 63 parameters blocks 3 0 parameters block 62 main block 4 main 64 Mbit block 61 main block 5 main block 60 main block 6 main Note The 512 Mbit and 1 Gbit devices will have multiple Selectable OTP Areas depending on the number of 256 Mbit dies in the stack and the placement of the parameter blocks Please see your local Intel representative for details about the Selectable OTP i
90. il 2005 Order Number 306666 Revision 001 17 1 Gbit P30 Family Figure 8 April 2005 18 64 Ball Easy BGA Ballout 64 128 256 512 Mbit PP d BR seer set Sa Mees weet suo VSS AQ CE A14 A25 A19 All RST VCCO Veco Als em NM e PEN EN n n Nos dd t 1 enn ust c Seal wane DQ9 DQ3 DO4 CLK DQ15 Y Mey oe DQ10 Doll DOT ADV WAIT DO VCCQ DOS bos DO14 WER sy ons rd e e f Nr H Pd Pad i re 4 H t rd Meu Su SLE vec VSS DO13 VSS DQ7 A24 Easy BGA Top View Ball side down 90000000 A22 A18 VCC A13 VPP A8 OOOOOOOO RFU A19 A25 A14 CE AQ VSS QOOOCOCCO A21 A20 WP A15 A12 A10 OOOOOOO A17 A16 VCCQ VCCQRST A11 OOOOOOO RFU DO15 CLK DQ4 DQ3 DQ9 DOL se esEAE OE WAIT ADV DO12 DQ11 DQ10 DQO OOO CO WE DO14 DQ6 DQ5 VCCO DQ2 RFU OOOOOOO A24 DQ7 VSS DO13 VSS VCC VSS RFU Easy BGA Bottom View Ball side u Notes A1 is the least significant address bit POND Intel StrataFlash Embedded Memory P30 A23 is valid for 128 Mbit densities and above otherwise it is a no connect NC A24 is valid for 256 Mbit densities and above otherwise it is a no connect NC A25 is valid for 512 Mbit densities otherwise it is a no connect NC Datasheet Order Number 306666 Revision 001 1 Gbit P30 Family intel Figure 9 88 Ball 80 Active Ball QUAD SCSP Ballout Pin 1 O a LU LL o I
91. ite the desired Protection Register data to the same Protection Register address see Figure 33 Protection Register Map on page 73 Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 73 1 Gbit P30 Family ntel amp 13 3 3 Caution April 2005 74 The device programs the 64 bit and 128 bit user programmable Protection Register data 16 bits at a time see Figure 47 Protection Register Programming Flowchart on page 92 Issuing the Program Protection Register command outside of the Protection Register s address space causes a program error SR 4 set Attempting to program a locked Protection Register causes a program error SR 4 set and a lock error SR 1 set Locking the Protection Registers Each Protection Register can be locked by programming its respective lock bit in the Lock Register To lock a Protection Register program the corresponding bit in the Lock Register by issuing the Program Lock Register command followed by the desired Lock Register data see Section 9 2 Device Commands on page 50 The physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1 These addresses are used when programming the lock registers see Table 29 Device Identifier Information on page 77 Bit 0 of Lock Register 0 is already programmed at the factory locking the lower pre programmed 64 bit region of the first 128 bit Protection Register containing the uni
92. ith WP deasserted To return an unlocked block to locked Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 69 1 Gbit P30 Family ntel amp 13 1 4 Figure 32 13 1 5 Note April 2005 70 down state a Lock Down command must be issued prior to changing WP to Vr Locked down blocks revert to the locked state upon reset or power up the device see Figure 32 Block Locking State Diagram on page 70 Block Lock Status The Read Device Identifier command is used to determine a block s lock status see Section 14 2 Read Device Identifier on page 76 Data bits DQ 1 0 display the addressed block s lock status DQO is the addressed block s lock bit while DQ1 is the addressed block s lock down bit Block Locking State Diagram Hardware Locked 011 Locked X01 Power Up Reset WP Hardware Control Software Locked Unlocked 111 110 Unlocked x00 p Software Block Lock 0x60 0x01 or Software Block Unlock 0x60 0xDO Software Block Lock Down 0x60 0x2F Qum WP hardware control Notes 1 a b c represents WPZ DQ1 DQO X Don t Care 2 DQ1 indicates Block Lock Down status DQ1 0 Lock Down has not been issued to this block DQ1 1 Lock Down has been issued to this block 3 DQO indicates block lock status DQO 0 block is unlocked DQO T block is locked Lock
93. ition the P30 device also has four pre defined spaces in the main array that can be configured as One Time Programmable OTP Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 9 1 Gbit P30 Family 3 0 Package Information 3 1 56 Lead TSOP Package Figure 1 TSOP Mechanical Specifications Z See Notes 1 and 3 See Note 2 d Plane Detail A Detail B 3 7 b 2l le L Table 1 TSOP Package Dimensions Sheet 1 of 2 Millimeters Inches Product Information Sym Min Nom Max Min Nom Max Package Height A 1 200 0 047 Standoff Ai 0 050 0 002 Package Body Thickness Ao 0 965 0 995 1 025 0 038 0 039 0 040 Lead Width b 0 100 0 150 0 200 0 004 0 006 0 008 Lead Thickness c 0 100 0 150 0 200 0 004 0 006 0 008 Package Body Length D4 18 200 18 400 18 600 0 717 0 724 0 732 Package Body Width E 13 800 14 000 14 200 0 543 0 551 0 559 Lead Pitch e 0 500 0 0197 April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 10 Order Number 306666 Revision 001 j ntel o 1 Gbit P30 Family Table 1 TSOP Package Dimensions Sheet 2 of 2 Millimeters Inches Product Information Sym Min Nom Max Min Nom Max Terminal Dimension D 19 800 20 00 20 200 0 780 0 787 0 795 Lead Tip Length L 0 500 0 600 0 700 0 020 0 024 0 028 Lead Count N 56 56
94. its in the status register if the device is not in the following modes WSM running Pgm Busy Erase Busy Pgm Busy In Erase Suspend OTP Busy BEFP modes 6 BEFP writes are only allowed when the status register bit 0 O or else the data is ignored T The current state is that of the chip and not of the partition Each partition remembers which output Array ID CFI or Status it was last pointed to on the last instruction to the chip but the next state of the chip does not depend on where the partition s output mux is presently pointing to 8 Confirm commands Lock Block Unlock Block Lock Down Block Configuration Register perform the operation and then move to the Ready State 9 WAO refers to the block address latched during the first write cycle of the current operation April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 84 Order Number 306666 Revision 001 intel 1 Gbit P30 Family Appendix B Flowcharts Figure 40 Datasheet Word Program Flowchart Write 0x40 Word Address Write Data Word Address Full Status Check if desired Program Complete Read Status Register 0 Program Successful WORD PROGRAM PROCEDURE Bus Write Program Data 0x40 Setup Setup Addr Location to program Data Data to program Addr Location to program Confirm Program Suspend Loop Check SR 7 1 WSM Ready 0 WSM Busy Repeat for subsequent Word Program op
95. kaging 4 Word synchronous read current 64 128 256 Mbit densities in 56 Lead TSOP 13 mA Typ at 40 MHz package W Quality and Reliability 64 128 256 512 Mbit densities in 64 Ball Operating temperature 40 C to 85 C Intel amp Easy BGA package 1 Gbit in SCSP is 30 C to 85 C 64 128 256 512 Mbit and 1 Gbit densities in Minimum 100 000 erase cycles per block Intel QUAD SCSP ETOXTM VIII process technology 130 nm 16 bit wide data bus The Intel StrataFlash Embedded Memory P30 product is the latest generation of Intel StrataFlash memory devices Offered in 64 Mbit up through 1 Gbit densities the P30 device brings reliable two bit per cell storage technology to the embedded flash market segment Benefits include more density in less space high speed interface lowest cost per bit NOR device and support for code and data storage Features include high performance synchronous burst read mode fast asynchronous access times low power flexible security options and three industry standard package choices The P30 product family is manufactured using Intel 130 nm ETOX VIII process technology Order Number 306666 Revision 001 April 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF
96. l Vcc Tc 25 C 2 lccs is the average current measured over any 5 ms time interval 5 us after CE is deasserted 3 Sampled not 100 tested 4 Vcc read program current is the sum of Vcc read and Vcc program currents 5 Vcc read erase current is the sum of Vcc read and Vcc erase currents 6 lccEs is specified with the device deselected If device is read while in erase suspend current is lcces plus Icer 7 lccw lcce Measured over typical or max times specified in Section 7 5 Program and Erase Characteristics on page 45 6 2 DC Voltage Characteristics Table 13 DC Voltage Characteristics CMOS Inputs TTL Inputs Sym Parameter Weeg 714 V 38 VI Vcco 724 V 3 6V unit Test Condition Notes Min Max Min Max Vi Input Low Voltage 0 0 4 0 0 6 2 Vin Input High Voltage Veco 0 4 Veco 2 0 Veco Vcc VecMin VoL Output Low Voltage 0 1 0 1 V Veco VccoMin lot 100 HA Vcc VccMin Vou Output High Voltage Vcco 0 1 Vcco 0 1 V Vcco VccoMin lou 100 HA Vppik Vpp Lock Out Voltage 0 4 0 4 V 3 Viko Vcc Lock Voltage 1 0 1 0 V Vikog Vcco Lock Voltage 0 9 0 9 NOTES A Synchronous read mode is not supported with TTL inputs 2 Vi can undershoot to 0 4 V and V can overshoot to Vecgt 0 4 V for durations of 20 ns or less 3 Vpp Vpp x inhibits erase and program operations Do not use Vpp and Vppy outside their valid ranges April 2005
97. lgorithms However factory word programming enhances the programming performance with Vpp Vppy This can enable faster programming times during OEM manufacturing processes Factory word programming is not intended for extended use See Section 5 2 Operating Conditions on page 30 for limitations when Vpp Vppg When Vpp VppL the device draws programming current from the Vcc supply If Vpp is driven by a logic signal Vppr must remain above Vpp MIN to program the device When Vpp Vppg the device draws programming current from the V pp supply Figure 31 Example VPP Supply Connections on page 66 shows examples of device power supply configurations Buffered Programming The device features a 32 word buffer to enable optimum programming performance For Buffered Programming data is first written to an on chip write buffer Then the buffer data is programmed into the flash memory array in buffer size increments This can improve system programming performance significantly over non buffered programming When the Buffered Programming Setup command is issued see Section 9 2 Device Commands on page 50 Status Register information is updated and reflects the availability of the buffer SR 7 indicates buffer availability if set the buffer is available if cleared the buffer is not available To retry issue the Buffered Programming Setup command again and re check SR 7 When SR 7 is set the buffer is ready for loading see Fi
98. mands and the word count for each set of 32 data words Host programmer bus cycles fill the device s write buffer followed by a status check SR 0 indicates when data from the buffer has been programmed into sequential flash memory array locations Following the buffer to flash array programming sequence the Write State Machine WSM increments internal addressing to automatically select the next 32 word array boundary This aspect of BEFP saves host programming equipment the address bus setup overhead With adequate continuity testing programming equipment can rely on the WSM s internal verification to ensure that the device has programmed properly This eliminates the external post program verification and its associated overhead Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 63 1 Gbit P30 Family ntel amp 11 3 1 11 3 2 Note 11 3 3 April 2005 64 BEFP Requirements and Considerations BEFP requirements Case temperature Tc 25 C 45 C e Vcc within specified operating range VPP driven to Vppy Target block unlocked before issuing the BEFP Setup and Confirm commands The first word address WAO for the block to be programmed must be held constant from the setup phase through all data streaming into the target block until transition to the exit phase is desired e WAO must align with the start of an array buffer boundary BEFP considerations For optimum pe
99. mmand WP5 high overrides the lock down function enabling blocks to be erased or programmed using software commands Erase and Program Power A valid voltage on this pin allows erasing or programming Memory contents cannot be altered when Vpp lt Vpp x Block erase and program at invalid Vpp voltages should not be attempted P Set Vpp Vcc for in system program and erase operations To accommodate resistor or diode drops ower VPP from the system supply the Viu level of Vpp can be as low as Vpp min Vpp must remain above Vpp Input min to perform in system flash modification VPP may be 0 V during read operations Vppy can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles VPP can be connected to 9 V for a cumulative total not to exceed 80 hours Extended use of this pin at 9 V may reduce block cycling capability VCC Power Device Core Power Supply Core logic source voltage Writes to the flash array are inhibited when Vcc Vi ko Operations at invalid Vcc voltages should not be attempted VCCQ Power Output Power Supply Output driver source voltage VSS Power Ground Connect to system ground Do not float any VSS connection REU m Reserved for Future Use Reserved by Intel for future device functionality and enhancement These should be treated in the same way as a Do Not Use DU signal DU Do Not Use Do not connect to any other signal or power supply must
100. mory Maps all packages Programming Size I au 256 Mbit Bik 128 Mbit Sigg 64 Mbit Region KB Region 128 210 CF0000 CFFFFF f 106 670000 67FFFF 270000 27FFFF 12 28 195 CO0000 COFFFF 99 600000 60FFFF 200000 20FFFF 128 194 BF0000 BFFFFF 98 5F0000 SFFFFF 1F0000 1FFFFF 1 28 f 179 B00000 BoFFFF 91 580000 58FFFF 180000 18FFFF 128 178 AF0000 AFFFFF 90 570000 57FFFF 170000 17FFFF 10 128 163 A0000 AOFFFF 83 500000 50FFFF 100000 10FFFF 128 f 162 9F0000 9FFFFF 82 4F0000 4FFFFF 0F0000 OFFFFF 9 128 147 900000 90FFFF 75 480000 48FFFF 080000 08FFFF 128 146 8F0000 8FFFFF 74 470000 47FFFF 070000 07FFFF 8 128 131 800000 80FFFF f 67 400000 40FFFF 010000 01FFFF 28 130 7F0000 7FFFFF 66 3F0000 3FFFFF 00C000 00FFFF 7 128 115 700000 70FFFF 59 380000 38FFFF 000000 003FFF 28 f 114 6F0000 6FFFFF 58 370000 37FFFF 6 128 99 600000 60FFFF 51 300000 30FFFF 128 98 5F0000 5FFFFF f 50 2F0000 2FFFFF 5 128 83 500000 50FFFF 43 280000 28FFFF 128 82 4F0000 4FFFFF 42 270000 27FFFF 4 128 67 400000 40FFFF 35 200000 20FFFF 128 66 3F0000 3FFFFF f 34 1F0000 1FFFFF 3 28 51 300000 30FFFF 27 180000 18FFFF 128 50 2F0000 2FFFFF 26 170000 17FFFF 2 128 35 200000 20FFFF 19 100000 10FFFF 128 34 1F0000 1FFFFF 18 OF0000 OFFFFF 1 128 19 100000 10FF
101. mplementation Intel StrataFlash Embedded Memory P30 Order Number 306666 Revision 001 April 2005 71 1 Gbit P30 Family ntel amp 13 3 April 2005 72 Protection Registers The device contains 17 Protection Registers PRs that can be used to implement system security measures and or device identification Each Protection Register can be individually locked The first 128 bit Protection Register is comprised of two 64 bit 8 word segments The lower 64 bit segment is pre programmed at the Intel factory with a unique 64 bit number The other 64 bit segment as well as the other sixteen 128 bit Protection Registers are blank Users can program these registers as needed When programmed users can then lock the Protection Register s to prevent additional bit programming see Figure 33 Protection Register Map on page 73 The user programmable Protection Registers contain one time programmable OTP bits when programmed register bits cannot be erased Each Protection Register can be accessed multiple times to program individual bits as long as the register remains unlocked Each Protection Register has an associated Lock Register bit When a Lock Register bit is programmed the associated Protection Register can only be read it can no longer be programmed Additionally because the Lock Register bits themselves are OTP when programmed Lock Register bits cannot be erased Therefore when a Protection Register is locked i
102. n A 15 0 2 ID Identifier data QD Query data on DQ 15 0 SRD Status Register data WD Word data N Word count of data to be loaded into the write buffer PD Protection Register data LRD Lock Register data 3 The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer This is followed by up to 32 words of data Then the confirm command 0xDO is issued triggering the array programming operation 4 The confirm command 0xD0 is followed by the buffer data 9 3 Command Definitions Valid device command codes and descriptions are shown in Table 21 Table 21 Command Codes and Definitions Sheet 1 of 2 Mode Code Device Mode Description OXFF Read Array Places the device in Read Array mode Array data is output on DQ 15 0 Places the device in Read Status Register mode The device enters this mode 0x70 Read Status Register after a program or erase command is issued Status Register data is output on DQ 7 0 Read Device ID Places device in Read Device Identifier mode Subsequent reads output Read 0x90 jor Configuration manufacturer device codes Configuration Register data Block Lock status or Register Protection Register data on DQ 15 0 Places the device in Read Query mode Subsequent reads output Common 0x98 Read Query Flash Interface information on DQ 7 0 0x50 Clear Status Register The WSM can only set Status Regi
103. n State Machine remains in the suspend mode regardless of control signal states except for RST asserted OxDO Suspend Resume This command issued to any device address resumes the suspended program or block erase operation First cycle of a 2 cycle command prepares the CUI for block lock configuration Ox60 Lock Block Setu changes If the next command is not Block Lock 0x01 Block Unlock OxDO p or Block Lock Down 0x2F the CUI sets Status Register bits SR 4 and SR 5 indicating a command sequence error If the previous command was Block Lock Setup 0x60 the addressed block is Block Locking 0x01 Lock Block Mese p Unlockin 9 If the previous command was Block Lock Setup 0x60 the addressed block is OxDO Unlock Block unlocked If the addressed block is in a lock down state the operation has no effect OX2F Lock Down Block If the previous command was Block Lock Setup 0x60 the addressed block is locked down Programi Protection First cycle of a 2 cycle command prepares the device for a Protection Register Protection OxCO R g or Lock Register program operation The second cycle latches the register egister Setup address and data and starts the programming algorithm First cycle of a 2 cycle command prepares the CUI for device read 0x60 Read Configuration configuration If the Set Read Configuration Register command 0x03 is not Register Setup the next command the CUI sets Status Register bits SR 4 and SR 5 Gontla
104. nced Data X 32 Factory Program Mode BEFP Program and Verify Busy if Block Address given matches address given on BEFP Setup command Commands treated as data 7 Lock CR Setup in Erase Suspend Erase Suspend Lock Error Erase Suspend Lock Error Botch Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 79 1 Gbit P30 Family l n Figure 36 Write State Machine Next State Table Sheet 3 of 6 Command Input to Chip and resulting Chip Next State OTP oa SP n Write RCR Block Address Illegal Cmds or WEM 1 4 s 8 9 1 Current Chip setup Confirm Confirm Confirm WAO BEFP Data Operation State Completes COH 01H 2FH XXXXH all other codes Ready Ready Ready Read Lock CR Setup Lock Lock Lock Down Set E Ready Lock Error Error Block Blk Word Program Busy Program Word Program Suspend BP Load 1 BP Confirm if S r Data load into BP Confirm if Data load into Program Buffer is Ready Program Buffer is complete ELSE BP load 2 complete ELSE BP Load 2 Ready Error Ready Error ie de Ready Error y unlocked or lock y error BP Busy BP Suspend Ready Error Erase Busy Erase Suspend April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 80 Order Number 306666 Revision 001 Figure 37 Write State Machine Next State Table Sheet 4 of 6 1 Gbit P30 Family Command Input to Chip and resulting Chip
105. nchronous mode the address is latched when ADV going high or continuously flows through if ADV is held low WARNING Designs not using ADV must tie it to VSS to allow addresses to flow through CE Input FLASH CHIP ENABLE Active low input CE low selects the associated flash memory die When asserted flash internal control logic input buffers decoders and sense amplifiers are active When deasserted the associated flash die is deselected power is reduced to standby levels data and WAIT outputs are placed in high Z state WARNING All chip enables must be high when device is not in use CLK Input CLOCK Synchronizes the device with the system s bus frequency in synchronous read mode During synchronous read operations addresses are latched on the rising edge of ADV or on the next valid CLK edge with ADV low whichever occurs first WARNING Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS OE Input OUTPUT ENABLE Active low input OE low enables the device s output data buffers during read cycles OE high places the data outputs and WAIT in High Z RST Input RESET Active low input RST resets internal automation and inhibits write operations This provides data protection during power transitions RST high enables normal operation Exit from reset places the device in asynchronous read array mode WAIT Output WAIT Indicates data valid in synchronou
106. nchronous or asynchronous and it defines the synchronous burst characteristics of the device To modify RCR settings use the Configure Read Configuration Register command see Section 9 2 Device Commands on page 50 RCR contents can be examined using the Read Device Identifier command and then reading from offset 0x05 see Section 14 2 Read Device Identifier on page 76 The RCR is shown in Table 22 The following sections describe each RCR bit Table 22 Read Configuration Register Description Sheet 1 of 2 Read Configuration Register RCR Read WAIT Data WAIT Burst CLK Burst Mode RES Latency Count Polarity Hold Delay Seq Edge RES RES Wrap Burst Length RM R LC 2 0 WP DH WD BS CE R R BW BL 2 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Description 15 Read Mode RM 0 Synchronous burst mode read 1 Asynchronous page mode read default 14 Reserved R Reserved bits should be cleared 0 13 11 Latency Count LC 2 0 010 Code 2 011 Code 3 100 Code 4 101 Code 5 110 Code 6 111 Code 7 default Other bit settings are reserved 10 Wait Polarity WP 0 WAIT signal is active low 1 WAIT signal is active high default 9 Data Hold DH 0 Data held for a 1 clock data cycle 1 Data held for a 2 clock data cycle default 8 Wait Delay WD 0 WAIT deasserted with valid data 1 WAIT deasserted one data cycle before valid data default 7 Burst Sequence BS 0 Reserved 1 Linear default 6 Clock
107. nchronous page mode is the default read mode and the device is set to Read Array However to perform array reads after any other device operation e g write operation the Read Array command must be issued in order to read from the flash memory array Asynchronous page mode reads can only be performed when Read Configuration Register bit RCR 15 is set see Section 10 3 Read Configuration Register on page 54 To perform an asynchronous page mode read an address is driven onto the Address bus and CE and ADV are asserted WE and RST must already have been deasserted WAIT is deasserted during asynchronous page mode ADV can be driven high to latch the address or it must be held low throughout the read cycle CLK is not used for asynchronous page mode reads and is ignored If only asynchronous reads are to be performed CLK should be tied to a valid Vry level WAIT signal can be floated and ADV must be tied to ground Array data is driven onto DQ 15 0 after an initial access time taygv delay see Section 7 0 AC Characteristics on page 33 In asynchronous page mode four data words are sensed simultaneously from the flash memory array and loaded into an internal page buffer The buffer word corresponding to the initial address on the Address bus is driven onto DQ 15 0 after the initial access delay The lowest two address bits determine which word of the 4 word page is output from the data buffer at any given time Synchrono
108. nd specifications 1 1 Nomenclature 1 8V 3 0 V 9 0 V Block Main block Parameter block Top parameter device Bottom parameter device Vc core voltage range of 1 7 V 2 0 V Vecg VO voltage range of 1 7 V 3 6 V Vpp voltage range of 8 5 V 9 5 V A group of bits bytes 1 Gbit P30 Family or words within the flash memory array that erase simultaneously when the Erase command is issued to the device The 1 Gbit P30 Family has two block sizes 32 KByte and 128 K Byte An array block that is usually used to store code and or data Main blocks are larger than parameter blocks An array block that is usually used to store frequently changing data or small system parameters that traditionally would be stored in EEPROM A device with its parameter blocks located at the highest physical address of its memory map A device with its parameter blocks located at the lowest physical address of its memory map 1 2 Acronyms BEFP Buffer Enhanced Factory Programming CUI Command User Interface MLC Multi Level Cell OTP One Time Programmable PLR Protection Lock Register PR Protection Register RCR Read Configuration Register Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 7 1 Gbit P30 Family 1 3 Conventions VCC Vcc 0x 0b SRI4 A 15 0 A5 Bit Byte Word Kbit KByte KWord Mbit MByte MWord April 2
109. ong D S1 1 400 1 500 1 600 0 0551 0 0591 0 0630 1 Corner to Ball A1 Distance Along E S2 2 900 3 000 3 100 0 1142 0 1181 0 1220 1 Note Daisy Chain Evaluation Unit information is at Intel Flash Memory Packaging Technology http developer intel com design flash packtech April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 12 Order Number 306666 Revision 001 I n e 1 Gbit P30 Family 3 3 QUAD SCSP Packages Figure 3 64 128 Mbit 88 ball 80 active QUAD SCSP Specifications 8x10x1 2 mm A1 Index S Mark 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 Y 8855699 t B s OOOOOOOO c c OOOOOOOO D gt OOOOOOOO E E OOOOOOOO y F po F OOOOOOOO G 6 OOOOOOOO 660006000 J J OOOOOOOO K k OOOOOOOO L t OOOOOOOO M M OO OO y gt me s x Bottom View Ball Up Y i_ Ss WP WP WP Ww up wp uP EE Oo OO A Pad Y Drawing not to scale Millimeters Inches Dimensions N Symbol Min Nom Max Min Nom Max Package Height TA ff 00 os AA eta Er NEE a sz oor ae N _ _ _ sso EEN Package Body Width 9 900 Package Body Width ES n 900 Pitch o O EERS NAE Ee Ball Ball Lead Count O Count Seating Plane Coplanarity fe Corner to Ball A1 Distance Along E 1 100 1 200 1 300 0 0433 0 0472 Corner to Ball A1 Distance Along D 0 500 0 600 0 700 0 0197 0 0236 0 0276 Datasheet Intel Stra
110. que identification number of the device Bit 1 of Lock Register 0 can be programmed by the user to lock the user programmable 64 bit region of the first 128 bit Protection Register When programming Bit 1 of Lock Register 0 all other bits need to be left as 1 such that the data programmed is OxFFFD Lock Register 1 controls the locking of the upper sixteen 128 bit Protection Registers Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128 bit Protection Registers Programming a bit in Lock Register 1 locks the corresponding 128 bit Protection Register After being locked the Protection Registers cannot be unlocked Intel StrataFlash Embedded Memory P30 Datasheet Order Number 306666 Revision 001 In 14 0 1 Gbit P30 Family Special Read States 14 1 Table 28 Datasheet The following sections describe non array read states Non array reads can be performed in asynchronous read or synchronous burst mode A non array read operation occurs as asynchronous single word mode When non array reads are performed in asynchronous page mode only the first data is valid and all subsequent data are undefined When a non array read operation occurs as synchronous burst mode the same word of data requested will be output on successive clock edges until the burst length requirements are satisfied Refer to the following waveforms for more detailed information e Figure 16 Asynchronous Single Word Read
111. rformance cycling must be limited below 100 erase cycles per block BEFP programs one block at a time all buffer data must fall within a single block BEFP cannot be suspended Programming to the flash memory array can occur only when the buffer is full NOTES 1 Word buffer boundaries in the array are determined by A 4 0 0x00 through Ox1F The alignment start point is A 4 0 0x00 2 Some degradation in performance may occur if this limit is exceeded but the internal algorithm continues to work properly 3 If the internal address counter increments beyond the block s maximum address addressing wraps around to the beginning of the block 4 If the number of words is less than 32 remaining locations must be filled with OXFFFF BEFP Setup Phase After receiving the BEFP Setup and Confirm command sequence Status Register bit SR 7 Ready is cleared indicating that the WSM is busy with BEFP algorithm startup A delay before checking SR 7 is required to allow the WSM enough time to perform all of its setups and checks Block Lock status Vpp level etc If an error is detected SR 4 is set and BEFP operation terminates If the block was found to be locked SR 1 is also set SR 3 is set if the error occurred due to an incorrect V pp level Reading from the device after the BEFP Setup and Confirm command sequence outputs Status Register data Do not issue the Read Status Register command it will be interpreted as data to be
112. s array or non array burst reads Read Configuration Register bit 10 RCR 10 WT determines its polarity when asserted WAIT s active output is Vo or Vou when CE and OE are Vi WAIT is high Z if CE or OE is Viu n synchronous array or non array read modes WAIT indicates invalid data when asserted and valid data when deasserted n asynchronous page mode and all write modes WAIT is deasserted WE Input WRITE ENABLE Active low input WE controls writes to the device Address and data are latched on the rising edge of WE WP Input WRITE PROTECT Active low input WP low enables the lock down mechanism Blocks in lock down cannot be unlocked with the Unlock command WP high overrides the lock down function enabling blocks to be erased or programmed using software commands VPP Power Input Erase and Program Power A valid voltage on this pin allows erasing or programming Memory contents cannot be altered when Vpp lt Vpp x Block erase and program at invalid Vpp voltages should not be attempted Set Vpp Vcc for in system program and erase operations To accommodate resistor or diode drops from the system supply the Viu level of Vpp can be as low as Vpp min Vpp must remain above VppL min to perform in system flash modification VPP may be 0 V during read operations Vppy can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles VPP can be connected to 9 V
113. s value Figure 28 shows the data output latency for the different settings of LC 2 0 Synchronous burst with a Latency Count setting of Code 4 will result in zero WAIT state however a Latency Count setting of Code 5 will cause 1 WAIT state Code 6 will cause 2 WAIT states and Code 7 will cause 3 WAIT states after every four words regardless of whether a 16 word boundary is crossed If RCR 9 Data Hold bit is set data hold of two clocks this WAIT condition will not occur because enough clocks elapse during each burst cycle to eliminate subsequent WAIT states Refer to Table 23 LC and Frequency Support on page 56 for Latency Code Settings Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 55 1 Gbit P30 Family Figure 28 First Access Latency Count endo ADEM DO Dg DO Dg DO DQ DO Dg DO DQ DO DIQ DO Dg DO D Mies Kl Code feed md CE VEVEVEVEVEYE Code 2 amp ZIZIZIZIZIz 9x83 Cocke gt Code6 Table 23 LC and Frequency Support Latency Count Settings Frequency Support MHz 2 lt 27 3 lt 40 See Figure 29 Example Latency Count Setting using Code 3 April 2005 56 Intel StrataFlash Embedded Memory P30 Datasheet Order Number 306666 Revision 001 intel Figure 29 1 Gbit P30 Family Example Latency Count Setting using Code 3 ak
114. ster error bits The Clear Status Register command is used to clear the SR error bits First cycle of a 2 cycle programming command prepares the CUI for a write operation On the next write cycle the address and data are latched and the WSM executes the programming algorithm at the addressed location During program operations the device responds only to Read Status Register and NS 0x40 Word Program Setup Program Suspend commands CE or OE must be toggled to update the Status Register in asynchronous read CE or ADV must be toggled to update the Status Register Data for synchronous Non array reads The Read Array command must be issued to read array data after programming has finished Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 51 1 Gbit P30 Family Table 21 Command Codes and Definitions Sheet 2 of 2 Mode Code Device Mode Description 0x10 Altemate Word Equivalent to the Word Program Setup command 0x40 Program Setup oxEs Buffered Program This command loads a variable number of words up to the buffer size of 32 9 words onto the program buffer The confirm command is Issued after the data streaming for writing into the OxDO E Program buffer is done This instructs the WSM to perform the Buffered Program Write algorithm writing the data from the buffer to the flash memory array First cycle of a 2 cycle command initiates Buffered
115. t 256 protection fields are available Protection Field 1 Protection Description This field describes user available One Time Programmable OTP Protection register bytes Some are pre programmed with device unique serial numbers Others are user programmable Bits 0 15 point to the Protection register Lock byte the section s first byte The following bytes are factory pre programmed and user programmable bits 0 7 Lock bytes Jedec plane physical low address bits 8 15 Lock bytes Jedec plane physical high address bits 16 23 n such that 2 factory pre programmed bytes bits 24 31 n such that 2 user programmable bytes Protection Field 2 Protection Description Bits 0 31 point to the Protection register physical Lock word address in the Jedec plane Following bytes are factory or user programmable bits 32 39 n n factory pgm d groups low byte bits 40 47 n n factory pgm d groups high byte bits 48 55 n 2n factory programmable bytes group bits 56 63 n n user pgm d groups low byte bits 64 71 n n user pgm d groups high byte bits 72 79 n 2 user programmable bytes group Burst Read Information Offset Length Description P 10Ah Optional flash features and commands Add a Page Mode Read capability bits 0 7 n such that 2 HEX value represents the number of read page bytes See offset 28h for device word width to determine 3
116. t cannot be unlocked Intel StrataFlash Embedded Memory P30 Datasheet Order Number 306666 Revision 001 intel Figure 33 13 3 1 13 3 2 Datasheet 1 Gbit P30 Family Protection Register Map 0x109 128 bit Protection Register 16 User Programmable 0x102 0x91 128 bit Protection Register 1 User Programmable Ox8A Lock Register 1 Ox89 25 14 13 12 11 10 e e v e 4 iTe 0x88 64 bit Segment User Programmable 0x85 0x84 128 Bit Protection Register O 64 bit Segment Factory Programmed 0x81 Lock Register 0 BE EEE DP Te 7 PEEP Ebr 0x80 Reading the Protection Registers The Protection Registers can be read from any address To read the Protection Register first issue the Read Device Identifier command at any address to place the device in the Read Device Identifier state see Section 9 2 Device Commands on page 50 Next perform a read operation using the address offset corresponding to the register to be read Table 29 Device Identifier Information on page 77 shows the address offsets of the Protection Registers and Lock Registers Register data is read 16 bits at a time Programming the Protection Registers To program any of the Protection Registers first issue the Program Protection Register command at the parameter s base address plus the offset to the desired Protection Register see Section 9 2 Device Commands on page 50 Next wr
117. t to tg oy 3 Sampled not 100 tested 4 Address hold in synchronous burst mode is tcyax or tyyax whichever timing specification is satisfied first 5 Applies only to subsequent synchronous reads 6 See your local Intel representative for designs requiring higher than 40 MHz synchronous operation Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 37 1 Gbit P30 Family ntel amp Figure 16 Asynchronous Single Word Read ADV Low R1 R2 Address A ADV le R3 gt R8 CE E Y le R4 pet OE G R15 i R17 M WAIT T R7 R6 Data DIQ eo ae gt n R5 gt RST P Note WAIT shown deasserted during asynchronous read mode RCR 10 0 Wait asserted low Figure 17 Asynchronous Single Word Read ADV Latch R1 R2 Address A A 1 0 A R101 R105 n ADV y lt R3 R8 CE E N AA ha R4 OE G WAIT T R7 e R6 R10 Data D Q D Note WAIT shown deasserted during asynchronous read mode RCR 10 0 Wait asserted low April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 38 Order Number 306666 Revision 001 I n e 1 Gbit P30 Family Figure 18 Asynchronous Page Mode Read Timing
118. taFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 13 1 Gbit P30 Family l n Figure 4 256 Mbit 88 ball 80 active QUAD SCSP Specifications 8x11x1 0 mm A1 Index Mark m N Go A a o Co o a A Go N m A OOOOOOOOOO OOOOOOOOOO OOOOOOOOOO OOOOOOOOOO OOOOOOOOOOOO plo ja zr AS IT OT MUOU P zr ART OT MUOD P 000000000000 000000000000 y 000000000000 Y 4 Top View Ball Down Bottom View Ball Up A2 Y p v p ccc tc o A Drawing not to scale Note Dimensions A1 A2 and b are preliminary Millimeters Inches Dimensions Symbe Min Nom Max Min Nom Max Package Height o o o A P j 100 0034 BallHeight A ou7 oo Package Body Thickness J A2 omw J oon pBal Lead Width b o300 0350 o400 0 0118 0 0138 0 0157 Package Body Length p 10900 1100 11100 0 4201 0 4331 0 4370 package Body Width Ge N EN fa ES N em aa N EEN Bek es amm s oes si Bld N AR EER M Seating Plane Coplanarity 0 100 Corner to Ball A1 Distance Along E 1 100 1 200 1 300 0 0433 0 0472 Comer to Ball A1 Distance Along D mcum 1000 1 100 1 200 0 0394 0 0433 0 0472 April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 14 Order Number
119. ted by issuing another Buffered Programming Setup command and repeating the buffered program sequence Buffered programming may be performed with Vpp Vppj or Vppg see Section 5 2 Operating Conditions on page 30 for limitations when operating the device with Vpp Vppy If an attempt is made to program past an erase block boundary using the Buffered Program command the device aborts the operation This generates a command sequence error and Status Register bits SR 5 4 are set If Buffered programming is attempted while Vpp is below Vpp y Status Register bits SR 4 3 are set If any errors are detected that have set Status Register bits the Status Register should be cleared using the Clear Status Register command Buffered Enhanced Factory Programming Buffered Enhanced Factory Programing BEFP speeds up Multi Level Cell MLC flash programming The enhanced programming algorithm used in BEFP eliminates traditional programming elements that drive up overhead in device programmer systems BEFP consists of three phases Setup Program Verify and Exit see Figure 43 BEFP Flowchart on page 88 It uses a write buffer to spread MLC program performance across 32 data words Verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state A single two cycle command sequence programs the entire block of data This enhancement eliminates three write cycles per buffer two com
120. that program the desired data bits at the addressed location and verifies that the bits are sufficiently programmed Programming the flash memory array changes ones to zeros Memory array bits that are zeros can be changed to ones only by erasing the block see Section 12 0 Erase Operations on page 67 The Status Register can be examined for programming progress and errors by reading at any address The device remains in the Read Status Register state until another command is written to the device Status Register bit SR 7 indicates the programming status while the sequence executes Commands that can be issued to the device during programming are Program Suspend Read Status Register Read Device Identifier CFI Query and Read Array this returns unknown data When programming has finished Status Register bit SR 4 when set indicates a programming failure If SR 3 is set the WSM could not perform the word programming operation because Vpp was outside of its acceptable limits If SR 1 is set the word programming operation attempted to program a locked block causing the operation to abort Before issuing a new command the Status Register contents should be examined and then cleared using the Clear Status Register command Any valid command can follow when word programming has completed Factory Word Programming Factory word programming is similar to word programming in that it uses the same commands and programming a
121. tions Table 26 11 1 Datasheet The device supports three programming methods Word Programming 40h 10h Buffered Programming E8h DOh and Buffered Enhanced Factory Programming 80h DOh See Section 9 0 Device Operations on page 48 for details on the various programming commands issued to the device The following sections describe device programming in detail Successful programming requires the addressed block to be unlocked If the block is locked down WP must be deasserted and the block must be unlocked before attempting to program the block Attempting to program a locked block causes a program error SR 4 and SR 1 set and termination of the operation See Section 13 0 Security Modes on page 69 for details on locking and unlocking blocks The Intel StrataFlash Embedded Memory P30 is segmented into multiple Programming Regions Programming Regions are made up of 8 or 16 blocks depending on the density The 64 and 128 Mbit devices have 8 blocks per Programming Region while the 256 Mbit has 16 blocks in each Programming Region see Table 26 See Section 4 4 Memory Maps on page 24 for address ranges of each Programming Region per density Programming Regions per Device Device Density isi of blocks per Number of Programming rogramming Region Regions per Device 64 Mbit 8 blocks 8 128 Mbit 8 blocks 16 256 Mbit 16 blocks 16 512 Mbit 16 blocks 32 1 Gbit 16 blocks 64
122. tten or erased When returning from a reset RST deasserted a minimum wait is required before the initial read access outputs valid data Also a minimum delay is required after a reset before a write cycle can be initiated After this wake up interval passes normal operation is restored See Section 7 0 AC Characteristics on page 33 for details about signal timing Datasheet Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 49 1 Gbit P30 Family Intel 9 2 Device Commands Device operations are initiated by writing specific device commands to the Command User Interface CUI See Table 20 Command Bus Cycles on page 50 Several commands are used to modify array data including Word Program and Block Erase commands Writing either command to the CUI initiates a sequence of internally timed functions that culminate in the completion of the requested task However the operation can be aborted by either asserting RST or by issuing an appropriate suspend command Table 20 Command Bus Cycles Sheet 1 of 2 First Bus Cycle Second Bus Cycle Bus Mode Command Gales y Oper Addr Data Oper Addr Data Read Array 1 Write DBA OxFF Read Device Identifier 22 Write DBA 0x90 Read DBA IA ID Read CFI Query 22 Write DBA 0x98 Read DBA QA QD Read Status Register 2 Write DBA 0x70 Read DBA SRD Clear Status Register
123. uld contact their local Intel or distribution sales office 2 Visit Intel s World Wide Web home page at http www intel com for technical documentation and tools 3 For the most current information on Intel Flash Memory visit our website at http developer intel com design flash Intel StrataFlash Embedded Memory P30 Datasheet Order Number 306666 Revision 001 1 Gbit P30 Family intel Appendix E Ordering Information for Discrete Products Figure 48 Decoder for Discrete Intel StrataFlash Embedded Memory P30 T EI 2 I8 F 6 4 0 P 3 0 B 8 5 l MI MI Il JL JI J Package Designator Access Speed TE 56 Lead TSOP leaded 85 ns JS 56 Lead TSOP lead free RC 64 Ball Easy BGA leaded Parameter Location PC 64 Ball Easy BGA lead free B Bottom Parameter T Top Parameter Product Line Designator 28F Intel Flash Memory Product Family P30 Intel StrataFlash Embedded Memory Device Density Vcc 1 7 2 0 V 640 64 Mbit Vcco 1 7 8 6 V 128 128 Mbit 256 256 Mbit Table 41 Valid Combinations for Discrete Products 64 Mbit 128 Mbit 256 Mbit TE28F640P30B85 TE28F128P30B85 TE28F256P30B85 TE28F640P30T85 TE28F128P30T85 TE28F256P30T85 JS28F640P30B85 JS28F128P30B85 JS28F256P30B85 JS28F640P30T85 JS28F128P30T85 JS28F256P30T85 RC28F640P30B85 RC28F128P30B85 RC28F256P30B85 RC28F640P30T85 RC28F
124. uration indicating a command sequence error 9 If the previous command was Read Configuration Register Setup 0x60 the 0x03 Read Configuration CUI latches the address and writes A 15 0 to the Read Configuration Register Register Following a Configure Read Configuration Register command subsequent read operations access array data April 2005 52 Intel StrataFlash Embedded Memory P30 Datasheet Order Number 306666 Revision 001 Intel 10 0 1 Gbit P30 Family Read Operations 10 1 Note 10 2 Datasheet The device supports two read modes asynchronous page mode and synchronous burst mode Asynchronous page mode is the default read mode after device power up or a reset The Read Configuration Register must be configured to enable synchronous burst reads of the flash memory array see Section 10 3 Read Configuration Register on page 54 The device can be in any of four read states Read Array Read Identifier Read Status or Read Query Upon power up or after a reset the device defaults to Read Array To change the read state the appropriate read command must be written to the device see Section 9 2 Device Commands on page 50 See Section 14 0 Special Read States on page 75 for details regarding Read Status Read ID and CFI Query modes The following sections describe read mode operations in detail Asynchronous Page Mode Read Following a device power up or reset asy
125. us Burst Mode Read To perform a synchronous burst read an initial address is driven onto the Address bus and CE and ADV are asserted WE and RST must already have been deasserted ADV is asserted and then deasserted to latch the address Alternately ADV can remain asserted throughout the burst access in which case the address is latched on the next valid CLK edge while ADV is asserted During synchronous array and non array read modes the first word is output from the data buffer on the next valid CLK edge after the initial access latency delay see Section 10 3 2 Latency Count on page 55 Subsequent data is output on valid CLK edges following a minimum delay Intel StrataFlash Embedded Memory P30 April 2005 Order Number 306666 Revision 001 53 1 Gbit P30 Family l n However for a synchronous non array read the same word of data will be output on successive clock edges until the burst length requirements are satisfied Refer to the following waveforms for more detailed information Figure 19 Synchronous Single Word Array or Non array Read Timing on page 39 Figure 20 Continuous Burst Read showing an Output Delay Timing on page 40 Figure 21 Synchronous Burst Mode Four Word Read Timing on page 41 10 3 Read Configuration Register The Read Configuration Register RCR is used to select the read mode sy
126. us burst mode is tepax or tyyax whichever timing specification is satisfied first 5 Applies only to subsequent synchronous reads 6 See your local Intel representative for designs requiring higher than 40 MHz synchronous operation Table 17 AC Read Specifications for 256 512 Mbit and 1 Gbit Densities Sheet 1 of 2 Num Symbol Parameter Speed Min Max Unit Notes Asynchronous Specifications vcc 1 8 V 2 0 V 85 R1 tavav Read cycle time eas ET 3 ns Vcc 1 8 V 2 0 V 85 R2 tavev Address to output valid ns Vec 1 7V 2 0V 88 Vcc 1 8 V 2 0 V 85 R3 teLov CE low to output valid ns Vec 1 7V 2 0V 88 R4 tergov OE low to output valid 25 ns 1 2 R5 tpHov RST high to output valid 150 ns 1 R6 teLox CE low to output in low Z 0 ns 1 3 R7 teLox OE low to output in low Z 0 ns 1 2 3 R8 tEHOZ CE high to output in high Z 24 ns R9 cuoz OE high to output in high Z 24 ns 1 3 R10 tou Output hold from first occurring address CEZ or OE change 0 ns R11 tener CE pulse width high 20 ns R12 tei CE low to WAIT valid 17 ns 1 R13 tentz CE high to WAIT high Z 20 ns 1 3 R15 tery OE low to WAIT valid 17 ns 1 R16 tettx OE low to WAIT in low Z 0 ns R17 tentz OE high to WAIT in high Z 20 ns a Latching Specifications April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 36 Order Number 306666
127. ver occurs first Hence tyi wg tg gun twi EH tet wH 5 Write pulse width high twuwL Or tgug is defined from CE or WE high whichever occurs first to CE or WE low whichever occurs last Hence twhw tener twugL teuwi 6 twavi OF twucuu must be met when transitioning from a write cycle to a synchronous burst read T Vpp and WP should be at a valid level until erase or program success is determined 8 This specification is only applicable when transitioning from a write cycle to an asynchronous read See spec W19 and W20 for synchronous read 9 When doing a Read Status operation following any command that alters the Status Register W14 is 20 ns 10 Add 10 ns if the write operations results in a RCR or block lock status change for the subsequent read operation to reflect this change 11 These specs are required only when the device is in a synchronous mode and clock is active during address setup phase Write to Write Timing f Address A IB W5 W8 w5 gt W2 W6 W2 W6 CE IE Wa gt a W9 W3 gt WE W OE G SWA REWI I WA4 WI Data D Q m Wi RST amp P April 2005 Intel StrataFlash Embedded Memory P30 Datasheet 42 Order Number 306666 Revision 001 In

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