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motorola M68HC11 Microcontrollers handbook

1. MAIN PROGRAM INTERRUPT ROUTINE 7 STACK ___5 0 58 PC 3B RTI SP DIRECT lt dd SP 1 CCR RTN NEXT MAIN INSTR SP42 ACCB SP43 ACCA MAIN PROGRAM MEN iX PC JSR SP45 X INDEXED X 4 ff STACK 4 6 NEXT MAININSTR 5 7 IY MAINPROGRAM SP 1 RTN4 SP 8 RTNH Pe 18 SP gt SP49 RIN INDEXED Y SAD JSR SWI SOFTWARE INTERRUPT ff MAIN PROGRAM _ 7 NEXT MAIN INSTR BE ee am T MAIN PROGRAM SP 8 CCR PC BD PRE SP 7 ACCB RIPE SP 6 ACCA INDEXED Y SP 5 IX RTN WAI WAIT FOR INTERRUPT gt H NEXT MAIN INSTR SPA IX 2 MAIN PROGRAM SP 3 3E WAI SP 2 BSR BRANCH TO SUBROUTINE y L MAIN PROGRAM 7 STACK 0 PC 8D BSR c SP 2 LEGEND 5 1 RTNH RTN ADDRESS OF NEXT INSTRUCTION IN MAIN PROGRAM TO SP EXECUTED UPON RETURN FROM SUBROUTINE RTNy MOST SIGNIFICANT BYTE OF RETURN ADDRESS RTN LEAST SIGNIFICANT BYTE OF RETURN ADDRESS RTS RETURN FROM STACK POINTER POSITION AFTER OPERATION IS COMPLETE SUBROUTINE 6 dd 8 BIT DIRECT ADDRESS 0000 00FF HIGH BYTE ASSUMED STACK TO BE 00 MAIN PROGRAM 7 0 ff 8 BIT POSITIVE OFFSET 00 0 TO FF 255 IS ADDED TO INDEX PC 39 RTS SP hh HIGH ORDER BYTE OF 16 BIT EXTENDED ADDRESS SP 1 LOW ORDER BYTE 16
2. Memory Map 0000 0000 512 BYTES RAM EXT EXT Y 1000 m A n 64 BYTE REGISTER BLOCK EXT EXT 103 B600 512 EEPROM B600 B7FF A 00 BOOT SPECIAL MODES EXT EXT ROM INTERRUPT BFFF VECTORS D000 000 12 KBYTES ROM EPROM NORMAL MODES INTERRUPT FFFF FFFF FFFF VECTORS SINGLE EXPANDED BOOTSTRAP SPECIAL CHIP TEST Figure 2 4 Memory Map for MC68HC 7 11E9 0000 0000 768 BYTES RAM EXT EXT 02FF y y 1000 1000 A A 64 BYTE REGISTER BLOCK EXT EXT 103F Y Y 9000 8 ROM EPROM Ed d B600 512 BYTES EEPROM B600 B7FF 18007 BFCO SPECIAL MODES EXT ROM INTERRUPT BFEF 7 VECTORS D000 2000 12 KBYTES ROM EPROM NORMAL MODES INTERRUPT FFFF FFFF FFFF VECTORS SINGLE EXPANDED BOOTSTRAP SPECIAL CHIP TEST 20 Kbytes ROM EPROM are contained in two segments of 8 Kbytes and 12 Kbytes each Figure 2 5 Memory Map for MC68HC 7 11E20 M68HC11E Family Rev 5 Data Sheet MOTOROLA Operating Modes and On Chip Memory For More Information On This Product Go to www freescale com 37 Freescale Semiconductor Inc Operating Modes and On Chip Memory
3. 0000 0000 256 BYTES RAM E EXT OOFF 1000 S 1000 GI BYTE REGISTER BLOCK 103F EXT EXT Broo 8007 BFCO SPECIAL MODES ROM INTERRUPT BEEF grrr VECTORS Y dn 2048 BYTES EEPROM F800 F800 NORMAL MODES IL 1 INTERRUPT SSS FFFF VECTORS SINGLE EXPANDED BOOTSTRAP SPECIAL CHIP TEST Figure 2 6 Memory Map for MC68HC811E2 Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read Port A Data Register 7 PA7 PA6 PA5 PM PA3 PA2 PA1 PAO 1000 PORTA Write 110 peser 0 0 0 1001 Reserved R R R R R R R R Read Parallel Contro Register STAF CWOM HNDS OIN PLS EGA INVB 1002 Write 115 Reset 0 0 0 0 0 U 1 1 Read Port C Data Register PC7 PC6 PC5 PC4 PC3 PC2 1 1003 PORTC Write See page 111 peser Indeterminate after reset Read Port Data Register PB5 4 PB3 2 PBI PBO 1004 PORTB Write 111 Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved U Unaffected Indeterminate after reset Figure 2 7 Register and Control Bit Assignments Sheet 1 of 6 Data Sheet M68HC11E Family Rev 5 38 Operating Modes and On Chip Memory MOTOROLA Go to www freescale com For More Information On This Product Freescale Semiconductor Inc Operatin
4. SCI SPI PULSE ACCUM INPUT EDGE PULSE ACCUM OVERFLOW TIMER OVERFLOW TIMER OUTPUT COMPARE 5 TIMER OUTPUT COMPARE 4 TIMER OUTPUT COMPARE 3 TIMER OUTPUT COMPARE 2 TIMER OUTPUT COMPARE 1 TIMER INPUT CAPTURE 3 TIMER INPUT CAPTURE 2 TIMER INPUT CAPTURE 1 REAL TIME INT IRQ SWI ILLEGAL OP CODE COP FAIL CLOCK MONITOR RESET BFAA STAR EQU BFAA CE1068 LDX PROGDEL BFAD 18 000 LDY EPRMSTR BFB1 7E0000 JMP RAMSTR Block fill unused bytes with zeros BFB4 000000000000 BSZ SBFD1 000000000000 000000000000 000000000000 0000000000 Boot ROM revision level in ASCII ORG SBFD1 BFD1 41 FCC Mask set I D 0000 FOR ORG SBFD2 BFD2 0000 FDB 0000 Ckckckck ck ck k kk T D ORG SBFD4 BFD4 71E9 FDB 571 9 BFD6 00 4 FDB 100 60 BFD8 00 7 FDB 100 57 BFDA 00CA FDB 100 54 BFDC 00 FDB 100 51 00100 FDB 100 48 BFEO 00D3 FDB 100 45 BFE2 0006 FDB 100 42 4 0009 FDB 100 39 BFE6 00 FDB 100 36 BFE8 OODF FDB 100 33 BFEA 00 2 FDB 100 30 BFEC 00 5 FDB 100 27 00 8 FDB 100 24 BFFO OOEB FDB 100 21 BFF2 00 FDB 100 18 BFF4 00 1 FDB 100 15 BFF6 4 FDB 100 12 BFF8 00F7 FDB 100 9 BFFA OOFA FDB 100 6 BFFC OOFD FDB 100 3 BFFE 54 FDB BEGIN C000 END AN1060 Rev 1 0 EPROM start addr EXIT to start of RAM MOTOROLA
5. e 3x VIEW Y zd F BASE METAL Uu V1 PLATING EN nnn j 5 ER PE Y T EN A1 D 0 13 0 005 T L MO N O 51 zl SECTION AB AB ROTATED 90 CLOCKWISE 5 NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 2 CONTROLLING DIMENSION MILLIMETER 3 DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD 0 10 0 004 T WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE DATUMS L M AND N BE DETERMINED AT DATUM PLANE DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION IS 0 25 0 010 PER SIDE DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0 46 0 018 MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR T G SEATING 2 PLANE ES lt m gt
6. Freescale Semiconductor Inc Application Note YTECOUNT 16 X ADJUST FOR HIGH NIBBLE OSUB 6000 OSUB 7000 YTECOUNT BYTECOUNT X ADD LOW NIBBLE YTECOUNT BYTECOUNT 3 ADJUST FOR ADDRESS CHECKSUM EM NEXT 4 HEX DIGITS BECOME THE STARTING ADDRESS FOR THE DATA OSUB 6000 GET FIRST NIBBLE OF ADDRESS OSUB 7000 CONVERT TO DECIMAL DDRESS 4096 X OSUB 6000 GET NEXT NIBBLE OSUB 7000 DDRESS ADDRESS 256 X OSUB 6000 OSUB 7000 DDRESS ADDRESS 16 X OSUB 6000 OSUB 7000 DDRESS ADDRESS X RRAYCNT ADDRESS ADRSTART INDEX INTO ARRAY EM CONVERT THE DATA DIGITS TO BINARY AND SAVE IN THE ARRAY OR 1 TO BYTECOUNT OSUB 6000 OSUB 7000 SAVE UPPER NIBBLE OF BYTE OSUB 6000 OSUB 7000 Y X ADD LOWER NIBBLE ODE ARRAYCNT Y SAVE BYTE IN ARRAY RRAYCNT ARRAYCNT 1 INCREMENT ARRAY INDEX EXT I OTO 1000 LOSE 1 EM DUMP BOOTLOAD CODE TO PART OPEN R 2 COM1 1200 N 8 1 Macintosh COM statement PEN COM1 1200 N 8 1 CD0 CSO DSO RS FOR RANDOM AS 42 DOS COM statement NPUT Comm port open 05 HILE LOC 2 gt 0 FLUSH INPUT BUFFER OSUB 8020 END RINT PRINT Sending bootload code to target part
7. 141 ui si qf duinf e dej1s100q ui 19591 Jaye 195 151 41 se eoJq e 10 00 Buipues Ag 34 0800 1 6 0800 342 0000 SOA 331 0000 4 0000 341 0000 341 0000 4 0000 34 0000 33 0000 34 0v00 34 0v00 34 0000 34 0000 33 0000 33 0000 uone2o1 pue og VH5OHd 0810 89 0 arrZ 0000 9 27 VMLLZOHS9OIN 0810 89 0 9770 0 02 YA LLOH89ON 0034 201 0 1315 0000 27 LHLLOHS9OIN 0098 219 0 ES 6314 63LL20H890N so 6451 LOAS89OWN 6451 LOH890W 0098 992 9625 2311803S890IN 0098 992 2323 231 180 89900 INOHd3 0004 261 0 1 0000 dLLLOHS9OIN INOH 0003 261 0 1 aLLOHS9OIN S9 S9 952 LOH89OIN 952 19 8VLILO3S890IN 19 xSE N 8Y L LOH899IN 19S IVLLOH89OIN 19 YSE OV LLOHSS9OIN 03LL0H892N 952 s vasas e zasaso 204892 p eoumog 21995 ued NOW pean edi now 195 996 LOOd so1njeoJ poejejeg IWNOH 100g z AN1060 Rev 1 0 245 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Note Original M68HC11 Versions Required Exactly 256 Byte
8. 2 5 1 4 EEPROM Row Erase This example shows how to perform a fast erase of large sections of EEPROM ROWE DAB 50 ROW 1 ERASE 1 1 STAB 103B Set to ROW erase mode STAB 0 Write any data to any address ROW LDAB S0F ROW 1 ERASE 1 EELAT 1 EPGM 1 STAB 103B Turn on high voltage JSR DLY10 Delay 10 ms CLR 103B Turn off high voltage and set to READ mode Data Sheet M68HC11E Family Rev 5 60 Operating Modes and On Chip Memory MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes and On Chip Memory 2 5 1 5 EEPROM Byte Erase EEPROM This is an example of how to erase a single byte of EEPROM BYTEE 516 BYTE 1 ERASE 1 EELAT 1 STAB 103B Set to BYTE erase mode STAB 0 Write any data to address to be erased LDAB 517 BYTE 1 ERASE 1 EELAT 1 EPGM 1 STAB 103B Turn on high voltage JSR DLY10 Delay 10 ms CLR 103B Turn off high voltage and set to READ mode 2 5 1 6 CONFIG Register Programming Because the CONFIG register is implemented with EEPROM cells use EEPROM procedures to erase and program this register The procedure for programming is the same as for programming a byte in the EEPROM array except that the CONFIG register addres
9. 121 SCI Eror Detection 2 121 122 Serial Communications Data Register 122 Serial Communications Control Register 1 123 Serial Communications Control Register 2 124 Serial Communication Status 125 Baud Rate i ACE 126 Flags and 129 130 M68HC11E Family Rev 5 10 Table of Contents MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Section 8 Serial Peripheral Interface SPI 8 1 PPTT P 133 8 2 Funcional PERN o3 4 405 seen ee CR CORR GRE e FO a 133 8 3 SPI Transfer 134 8 4 Clock Phase and Polarity 135 8 5 SPEA E 14 d Ree RR 135 8 5 1 Master Ir Slave EA Ro OR e d 136 8 5 2 Linn 957 dj MEME 136 8 5 3 c p srl EM IT 136 8 5 4 RM sm 136 8 6 SPI System bee 137 8 7 SPI Regist rs owes 138 8 7 1 Serial Peripheral Control Register 138 8 7 2 Serial Peripheral Status Register 139 8 7 3 Serial Peripheral Data I O Regi
10. Address 1021 Bit 7 6 5 4 3 2 1 Bit 0 Read aia EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A rite Reset 0 0 0 0 0 0 0 0 Figure 9 3 Timer Control Register 2 TCTL2 EDGxB and EDGxA Input Capture Edge Control Bits There are four pairs of these bits Each pair is cleared to 0 by reset and must be encoded to configure the corresponding input capture edge detector circuit 4 functions only if the 14 O5 bit in the PACTL register is set Refer to Table 9 2 for timer control configuration Table 9 2 Timer Control Configuration EDGxB EDGxA Configuration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge 9 3 2 Timer Input Capture Registers Data Sheet When an edge has been detected and synchronized the 16 bit free running counter value is transferred into the input capture register pair as a single 16 bit parallel transfer Timer counter value captures and timer counter incrementing occur on opposite half cycles of the phase 2 clock so that the count value is stable whenever a capture occurs The timer input capture registers are not affected by reset Input capture values can be read from a pair of 8 bit read only registers A read of the high order byte of an input capture register pair inhibits a new capture transfer for one bus cycle If a double byte read instruction such as load double accumulator D
11. 1 3 0 to 5 5 0 T4 to Ty all timing is shown with respect to 20 Vpp and 70 Vpp unless otherwise noted 2 Ports C and D timing is valid for active drive CWOM and DWOM bits are not set in PIOC and SPCR registers respectively 3 If this setup time is met STRB acknowledges in the next cycle If itis not met the response may be delayed one more cycle MCU READ OF PORT For nondatched operation of port C Figure 10 7 Port Read Timing Diagram M68HC11E Family Rev 5 Data Sheet MOTOROLA Electrical Characteristics 179 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Characteristics pee MCU WRITE TO PORT l B C D PREVIOUS PORT DATA NEW DATA VALID PORT A PREVIOUS PORT DATA NEW DATA VALID Figure 10 8 Port Write Timing Diagram STRA IN PORT C IN Figure 10 9 Simple Input Strobe Timing Diagram MCU WRITE TO PORT B 7 E PORT B PREVIOUS PORT DATA NEW DATA VALID STRB OUT Figure 10 10 Simple Output Strobe Timing Diagram e READ FORTE E STRB OUT laES STRA IN tis PORT C IN Notes 1 After reading PIOC with STAF set 2 Figure shows rising edge STRA 1 and high true STRB INVB 1 Figure 10 11 Port C Input Handshake Timing Diagram Data Sheet M68HC11E Family Rev 5 180 Electrical Characteristics MOTOROLA For More Info
12. 7F103D 8604 9728 8680 9704 132E20FC 86FF 972F CEB675 8D53 8CB67D 26F9 AN1060 Rev 1 0 ckck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck kk kk kk 68HC7111 E9 Duplicator Program for AN1060 ck ckck ck ckck ck ckck ck ckck ck ck ck ck ck ck ck ck ck ck ck ck ck ck kk kk KkKKKK Equates All reg addrs except INIT are 2 digit for direct addressing KkKKKK INIT EQU 103D RAM Reg mapping SPCR EQU 28 DWOM in bit 5 PORTB EQU 04 Red LED bit 1 Grn bit 0 Reset of prog socket bit 7 RESET EQU 10000000 RED EQU 00000010 GREEN EQU 00000001 PORTE EQU 0A Vpp Sense in bit 7 1 SCSR EQU 2 SCI status register TDRE TC RDRF IDLE OR NF FE TDRE EQU 10000000 EQU 00100000 SCDR EQU 2 data register PROGRAM EQU 5 EPROM prog utility in boot ROM EPSTRT EQU D000 Starting address of EPROM ORG 58600 Start of EEPROM KKKKKKKKK BEGIN WTABRK BLLOOP Delay for about 4 c ck ckckckckck ck ckck kock ck ckockck ck ck ck ck ck ck ck ck ck ck k ck k ck kk kk kk CLR INIT Moves Registers to 0000 3F LDAA 504 Pattern for DWOM off no SPI STAA SPCR Turns off DWOM in EVBU MCU LDAA RESET STAA PORT
13. enn 89 9 8 1 Power On Reset POR 89 5 2 2 External Reset 5 90 5 23 Computer Operating Properly COP 90 5 2 4 E 91 5 2 5 System Configuration Options 92 5 2 6 Configuration Control 93 5 3 cea wed do a doe ER Re ean 93 5 3 1 Central Processor Unt CPU ince ccd bens RO CERE RAE ERE 94 B d e dE keh PC ee 94 5 3 3 yip prr cT 94 5 3 4 Real Time Interrupt 1 94 5 3 5 Pulse ASCUIUIBIBE sous s Shere eer ve ERE 94 5 3 B Computer Operating Properly 95 Serial Communications Interface SCI 95 5 3 8 Serial Peripheral Interface 95 5 2 9 Analog to Digital A D 95 5 3 10 5555558 95 5 4 Reset and Interrupt Priory o ie DP RC EE REPE a m 96 5 4 1 Highest Priority Interrupt and Miscellaneous Register 97 M68HC11E Family Rev 5 Data Sheet MOTOROLA Table of Contents 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 25 5 5 1 552 5 5 3 5 5 4
14. ADCTL A D CONTROL Y YYYYY RESULT REGISTER INTERFACE ADR A D RESULT 1 ADR2 A D RESULT 2 ADR3 A D RESULT 3 ADR4 A D RESULT 4 Figure 3 1 A D Converter Block Diagram DIFFUSION POLY COUPLER ANPUT 6 20V 42V 64kO 2pF 0 7V 0 7 20 pF PES 7X d Y 400 nA DAC DUMMY N CHANNEL JUNCTION CAPACITANCE OUTPUT DEVICE LEAKAGE INPUT PROTECTION DEVICE ce Vn THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12 CYCLE SAMPLE TIME Figure 3 2 Electrical Model of an A D Input Pin Sample Mode Data Sheet M68HC11E Family Rev 5 64 Analog to Digital A D Converter MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital A D Converter Overview 3 2 2 Analog Converter 3 2 3 Digital Control Conversion of an analog input selected by the multiplexer occurs in this block It contains a digital to analog capacitor DAC array a comparator and a successive approximation register SAR Each conversion is a sequence of eight comparison operations beginning with the most significant bit MSB Each comparison determines the value of a bit in the successive approximation register The DAC array performs two functions It acts as a sample and hold circuit during the entire conversion sequence and provides comparison voltage to the comparator during each successive comparison The result of each successive co
15. B INS Increment 1 55 INH 31 e 3 Stack Pointer INX Increment IX 1 IX INH 08 3 Index Register X INY Increment IY 1 gt lY INH 18 08 4 Index Register Y JMP opr Jump See Figure 3 2 EXT hh 11 3 IND X 6E ff 3 IND Y 18 6E 4 JSR opr Jump to See Figure 3 2 DIR 9D 5 Subroutine EXT BD hh 11 6 IND X AD ff 6 IND Y 18 AD ff 7 LDAA opr Load gt 86 jii 2 0 Accumulator A DIR 96 3 A A EXT B6 hh 11 4 A IND X 4 A IND Y 18 Jff 5 LDAB Load gt B IMM C6 11 2 0 Accumulator B DIR D6 ad 3 B B EXT F6 hh 4 B IND X E6 Iff 4 B IND Y 18 5 LDD opr Load Double gt 1 33 3 0 Accumulator DIR DC ad 4 D EXT FC hh 5 IND X ff 5 IND Y 18 EC 6 LDS opr Load Stack 1 IMM 8bE 133 3 0 Pointer DIR 9E 4 EXT BE hh 5 IND X AE ff 5 IND Y 18 AE ff 6 LDX opr Load Index M M 1 gt 1X IMM CE 133 3 0 Register DIR DE ad 4 X EXT FE hh 5 IND X EE ff 5 IND Y CD ff 6 LDY opr Load Index 15 IMM 18 133 4 0 Register DIR 18 DE 5 Y EXT 18 FE hh 6 IND X 1A EE ff 6 IND Y 18 ff 6 LSL opr Logical Shi EXT 78 hh 6 E Left Xa IND X 68 6 0 INDY 18 68 7 LSLA Logical Shi A INH 48
16. 3504 4 SCI CHARACTER TIMES BAUDOK POINT TO START OF RAM 50000 6 7 INITIALIZE TIMEOUT COUNT 8 WTLOOP 9 lt RECEIVE DATA READY YES NO LOOP 19 DECREMENT TIMEOUT COUNT CYCLES NO TMEDOUTYET gt 0 WYES STORE RECEIVED DATA TO 11 TRANSMIT ECHO FOR VERIFY 12 POINT AT NEXT RAM LOCATION 13 14 PAST END OF RAM NO YES 15 STAR SET UP FOR PROGRAM UTILITY X PROGRAMMING TIME CONSTANT 16 Y START OF EPROM JUMP TO START OF RAM 0000 17 Figure 3 MC68HC711E9 Bootloader Flowchart AN1060 Rev 1 0 220 MOTOROLA For More Information On This Product Go to www freescale com UPLOAD Utility NOTE Freescale Semiconductor Inc Application Note The UPLOAD utility subroutine transfers data from the MCU to a host computer system over the SCI serial data link Only EPROM versions of the M68HC 1 1 include this utility Verification of EPROM contents is one example of how the UPLOAD utility could be used Before calling this program the Y index register is loaded by user firmware with the address of the first data byte to be uploaded If a baud rate other than the current SCI baud rate is to be used for the upload process the user s firmware must also write to the baud register The UPLOAD program sends successive bytes of data out the SCI transmitter until a reset is issued the upload loop i
17. 9 en 99 gt Lu EVBU Schematic For More Information On This Product Go to www freescale com Data Sheet 208 Freescale Semiconductor Inc Order this document by AN1060 D Rev 1 0 Motorola Semiconductor Application Note AN1060 M68HC11 Bootstrap Mode By Jim Sibigtroth Mike Rhoades and John Langan Austin Texas Introduction The M68HC11 Family of MCUs microcontroller units has a bootstrap mode that allows a user defined program to be loaded into the internal random access memory RAM by way of the serial communications interface SCI the M68HC11 then executes this loaded program The loaded program can do anything a normal user program can do as well as anything a factory test program can do because protected control bits are accessible in bootstrap mode Although the bootstrap mode is a single chip mode of operation expanded mode resources are accessible because the mode control bits can be changed while operating in the bootstrap mode This application note explains the operation and application of the M68HC1 1 bootstrap mode Although basic concepts associated with this mode are quite simple the more subtle implications of these functions require careful consideration Useful applications of this mode are overlooked due to an incomplete understanding of bootstrap mode Also common problems associated with bootstrap mode could be avoided by a more complete underst
18. NEGB Two s 0 B INH 50 2 B NOP No operation No Operation INH 01 2 ORAA OR A M gt A A IMM jii 2 0 Accumulator A DIR 9A 3 A Inclusive A EXT BA hh 11 4 A IND X 4 A IND Y 18 AA 5 ORAB opr OR B M gt B B IMM CA jii 2 0 Accumulator B DIR DA ad 3 B Inclusive B EXT FA hh 11 4 B IND X ff 4 B IND Y 18 EA ff 5 PSHA Push A onto SIKSP SP 1 A INH 36 3 Stack PSHB Push Bonto SIKSP SP 1 INH 37 3 Stack PSHX Push X onto IX gt Stk SP SP 2 INH 3C 4 Stack Lo First PSHY Push Y onto IY Stk SP SP 2 INH 18 3C 5 Stack Lo First PULA Pull A from SP 1 A Stk A INH 32 4 Stack PULB Pull B from SP 1 Stk B INH 33 4 Stack PULX Pull X From SP SP 2 IX Stk INH 38 5 Stack Hi First PULY Pull Y SP SP 2 IY Stk INH 18 38 6 Stack Hi First ROL opr Rotate Left EXT 79 hh 11 6 A IND X 69 Iff 6 ars e INDY 18 69 lff 7 ROLA Rotate Left A A INH 49 2 67 50 ROLB Rotate Left B B INH 59 2 Ow Rotate Right EXT 76 hh 11 6 LE CERTE REED IND X 66 6 b7 b0 IND Y 18 66 7 M68HC11E Family Rev 5 Data Sheet MOTOROLA Central Processor Unit CPU 85 For More Information On This Product
19. 1909015 0 309 eAnisues 72 1 309 eAnsues eDp3 S9JoN SS3uaav 401 eui uoruw YM uaav uaav uaav 390940 4015 4015 4015 Pn Ge eS a AVISO gt OulX 10 d gt AA Data Sheet M68HC11E Family Rev 5 Electrical Characteristics 175 For More Information On This Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Electrical Characteristics 19A028H LIVM 6 01 LIVM osje 3S3H lt 593151999 MOVLS g Y HX IX TA SsS3udav S1d HH31N VNH3LNI HO OUIX M68HC11E Family Rev 5 Data Sheet MOTOROLA Electrical Characteristics For More Information On This Product 176 Go to www freescale com Freescale Semiconductor Inc Electrical Characteristics MC68L11E9 E20 Control Timing 91 9 01 0 4q eAnrsues one 72 308 eAnrsues 7 S JON Ss3uaav VNH3 NI HO z OHI Data Sheet M68HC11E Family Rev 5 Electrical Character
20. y yL zm otg 2 L 31ON VINH d ke Jd 2 14 2 95 9 92 A 1 90 o 13539 HALSWW Lor zd 8 Od HO VNIAH3LL S H3Sn OX ORE of ke TOT NJ63LLOH89ON E 9 0 97 X SS rer a Bod 4 WD 15 _ 16 NOW 990 HOLO3NNOO 310N 4 NOW ECON m O O 1 urvaon 05 OW T now e 93d SE POM eu o o gr Gad er 2 89 9y NOW SINON 61 353 vv NON 12839 uA 2 z 9n AON EH SVIVHIS a ON E 5 iy 9 6 7 SNOW S 0345 EL waon SInom 204 09 SznoN SIMON SI cqwisod ENN Osiwiead 84 2 Ot xd 6LNOW 2 50 a odi zqyizod Eze OH LOO LL 2 HAIN LH 20 gt aaa 590 64 TENON 290 9 z enon ge 917 84 2 NON 96 0E NON 3 SENON soorevd te _ _ BENON 8 2 NOW 66 Wd d ro ET i OW eee NON c OMON OF yn ge COUN ve NOW 80 19 S
21. 255 BOOTCODES ADD HEX FF TO SET BAUD RATE ON TARGET 11 OSUB 6500 RINT OR 1 TO BOOTCOUNT OF BYTES IN BOOT CODE BEING ECHOED OSUB 8000 5 B GOSUB 8500 RINT Character I received HX EXT I RINT Programming is ready to begin INPUT Are you ready 05 LS HILE LOC 2 gt 0 FLUSH INPUT BUFFER AN1060 Rev 1 0 MOTOROLA 241 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Note 1598 GOSUB 8020 1599 WEND 1600 XMT 0 RCV 0 POINTERS TO XMIT AND RECEIVE BYTES 1610 A CODE XMT 1620 GOSUB 6500 SEND FIRST BYTE 1625 FOR 1 TO CODESIZE 1 ZERO BASED ARRAY 0 gt CODESIZE 1 1630 AS CODE I SEND SECOND BYTE TO GET ONE IN QUEUE 1635 GOSUB 6500 SEND IT 1640 GOSUB 8000 GET BYTE FOR VERIFICATION 1650 RCV 1 1660 LOCATE 10 1 PRINT Verifying byte 4 I 1664 IF CHRS CODE RCV BS THEN 1670 1665 K CODE GOSUB 8500 1666 LOCATE 1 1 PRINT Byte 4 I Sent HX 1668 K ASC B GOSUB 8500 1669 PRINT Received HX 1670 NEXT I 1680 GOSUB 8000 GET BYTE FOR VERIFICATION 1690 CODESIZES 1 1700 LOCATE 10 1 PRINT Verifying byte CODESIZE 1
22. 14 Bit13 Bit12 Bit 11 10 Bit9 Bit8 See page 147 Reset Indeterminate after reset inis bn Bit7 Bite Bits Bit4 Bit 3 Bit2 Bito See page 147 Reset Indeterminate after reset TT ier Bit15 14 Bit13 Bit12 Bit10 Bit9 Bits See 149 Rese 1 1 1 1 1 1 1 1 1017 dun Bit7 Bit6 Bit 5 Bit 4 Bit 3 Bit2 Bit 1 Bit 0 Seepage Rect 1 1 1 1 1 1 1 1 racc n Bit15 14 Bit13 Bit12 Bit10 Bit9 Bits See page 150 Reset 1 1 1 1 1 1 1 1 a Bit7 Bite Bits Bit 3 Bit2 Bit Bito See page 150 Reset 7 1 1 1 1 1 1 1 1 101 15 Bit14 Bit13 Bit12 Bit 11 Bit9 Bits See 150 Reset 1 1 1 1 1 1 1 1 101B audien in Bit7 Bit6 Bit 5 Bit 4 Bit 3 Bit2 Bit 1 Bit 0 See page 150 Reset 1 1 1 1 1 1 1 1 nie 15 14 Bit13 Bit12 Bit10 Bit9 Bits Seepage 150 Reset 1 1 1 1 1 1 1 1 101D ic Bit7 Bit6 Bit 5 Bit 4 Bit 3 Bit2 Bit 1 Bit 0 Seepage 150 Reset 1 1 1 1 1 1 1 1 Unimplemented R Reserved U Unaffected Indeterminate after reset Figure 2 7 Register and Control Bit Assignments Sheet 3 of 6 Data Sheet M68HC11E Family Rev 5 40 Operating Modes and On Chip Memory MOTOROLA For More Information On This Product Go to www freescale com Addr 101E 101F 1020 1021 1022 1023 1024 1025 1026 1027
23. 10 Vss 0 T4 T to Ty unless otherwise noted 2 specification for RESET and MODA is not applicable because they are open drain pins specification not applicable to ports C and D in wired OR mode 3 Refer to 10 13 Analog to Digital Converter Characteristics and 10 14 MC68L11E9 E20 Analog to Digital Converter Characteristics for leakage current for port E M68HC11E Family Rev 5 Data Sheet MOTOROLA Electrical Characteristics 167 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Characteristics 10 6 Supply Currents and Power Dissipation Characteristics Symbol Min Max Unit Run maximum total supply current Single chip mode2 MHz 15 3 MHz Ipp 27 mA Expanded multiplexed mode2 MHz mE 27 3 MHz 35 Wait maximum total supply current all peripheral functions shut down _ 6 Single chip mode2 MHz Wipp ES 15 mA 3 MHz M 10 Expanded multiplexed mode2 MHz 20 3 MHz Stop maximum total supply current Single chip mode no clocks 40 C to 85 C Sip 25 gt 85 C to 105 C 50 gt 4105 C to 125 C 100 Maximum power dissipation Single chip mode2 MHz 85 3 MHz Pp 150 mW Expanded multiplexed mode2 MHz 150 3 MHz 195 1 Vpp 5 0 10 Vss 0 TA T to Ty unless otherwise noted 2 EXTAL is driven with a square wave and tcyc 500 ns for 2 MHz rating
24. Ey a Y Y FETCH VECTOR N N Y Y FETCH VECTOR lt gt SFFE4 SFFES N N Y FLAG Y FETCH VECTOR OC4F 1 FFE2 FFE3 Y FLAG Y FETCH VECTOR lt gt I4 O5IF 1 FFEO FFE1 T N N Y Y FETCH VECTOR lt gt SFFDF Y FLAG Y FETCH VECTOR PAOVF 1 FFDC FFDD Y FLAG FETCH VECTOR PAIF 1 FFDA FFDB x N N FLAGS d SPIF 17 OR SY FETCHVECTOR MODF 1 SFFD8 FFD9 N N SCI INTERRUPT FETCH VECTOR SEE FIGURE SFFD6 FFD7 i 5 3 N FETCH VECTOR SFFF2 FFF3 END Figure 5 6 Interrupt Priority Resolution Sheet 2 of 2 M68HC11E Family Rev 5 MOTOROLA Resets and Interrupts For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resets and Interrupts BEGIN FLAG 1 VALID SCI REQUEST VALID SCI REQUEST Figure 5 7 Interrupt Source Resolution Within SCI Data Sheet M68HC11E Family Rev 5 106 Resets and Interrupts MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resets and Interrupts Low Power Operation 5 6 Low Power Operation 5 6 1 Wait Mode 5 6 2 Stop Mode Both stop mode and wait mode suspend CPU operation until a reset or interrupt occurs Wait mode suspends processing and reduces power consumption to an intermediate level Stop mode turns off al
25. Retrieve the file pcbug342 exe a self extracting archive from the MCU11 directory Some Motorola evaluation board products also are shipped with PCbug11 For specific information about any of the PCbug11 commands see the appropriate sections in the PCbug11 User s Manual part number M68PCBUG11 D2 which is available from the Motorola Literature Distribution Center as well as the Worldwide Web at http www motorola com semiconductors The file is also on the software download system and is called pcbug11 pdf Mj 296 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Engineering Bulletin Programming Procedure Once you have obtained PCbug11 use this step by step procedure to program your MC68HC71 1E9 part Step 1 Before applying power to the EVBU remove the jumper from J7 and place it across J3 to ground the MODB pin Place a jumper across J4 to ground the MODA pin This will force the EVBU into special bootstrap mode on power up Remove the resident MC68HC11E9 MCU from the EVBU Place your MC68HC711E9 in the open socket with the notched corner of the part aligned with the notch on the PLCC socket e Connect the EVBU to one of your PC COM ports Apply 5 volts to Vpp and ground to GND on the power connector of your EVBU Also take note of P4 connector pin 18 In step 5 you will connect a 12 volt at most 12 5 volts programming vol
26. 30 1 4 10 3 FOIT I iud wapa 30 1 4 10 4 31 1 4 10 5 FILE enna d 31 Section 2 Operating Modes and On Chip Memory 2 1 ree EROR ere d 33 2 2 Operating Modes 33 2 2 1 fen 33 LA cpi doo fec 33 2 2 3 34 2 2 4 tees eeeeecs ceed cepheds 35 2 3 Memory BEBE cess eaten se had ACRI SPERO 35 2 3 1 RAM and Input Output 44 2 2 2 Mode 45 M68HC11E Family Rev 5 Data Sheet MOTOROLA Table of Contents 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 2 453 System iu saca go cede CR ES 47 2 3 3 1 System Configuration Register 48 2 3 3 2 RAM and I O Mapping Register 50 228 23 System Configuration Options Register 51 2 4 EPROWOTPROM pda ed air oisi d owned 52 2 4 1 Programming an Individual EPROM 53 2 4 2 Programming the EPROM with Downloaded Data 54 2 4 3 EPROM and EEPROM Programming Control Register 54 28 ic rr 57 25 EEPROM and CONFIG Programming and 57 2 5 1 1 Bl
27. Go to www freescale com Freescale Semiconductor Inc Central Processor Unit CPU Table 4 2 Instruction Set Sheet 6 of 7 Maemonic Operation Description Addressing Instruction Condition Codes Mode Opcode Operand Cycles H 1 2 Rotate Right A A INH 46 2 A b7 bo C RORB Rotate Right B B INH 56 2 b7 bo C RTI Return from See Figure 3 2 INH 3B 12 Interrupt RTS Return from See Figure 3 2 INH 39 5 Subroutine SBA Subtract B from INH 10 2 A SBCA opr Subtract with A M C gt A A IMM 82 2 Carry from A A DIR 92 3 A EXT B2 hh 11 4 A IND X A2 4 A IND Y 18 A2 5 SBCB opr Subtract with B IMM C2 fii 2 Carry from B B DIR D2 ad 3 B EXT F2 hh 11 4 B IND X E2 4 B IND Y 18 E2 ff 5 SEC Set Carry 1 gt C INH 00 2 SEI Set Interrupt Tl INH 2 1 Mask SEV Set Overflow 12V INH 0B 2 Flag STAA opr Store A gt M A DIR 97 da 3 B7 hb 11 4 A A IND X ff 4 A IND Y 18 ff 5 STAB opr Store BM B DIR D7 3 A Accumulator B EXT hh 11 4 B B IND X 7 4 B IND Y 18 E7 ff 5 STD opr Store A gt M B gt M 1 DIR DD 4
28. I I I I Kk Kk Kk RII IIR 7000 X INSTR H 5 7010 IF X 0 THEN FLAG 1 7020 X X 1 7030 RETURN I AN1060 Rev 1 0 242 MOTOROLA For More Information On This Product Go to www freescale com 7990 7992 7994 7996 7998 7999 8000 8005 8010 8020 8030 8490 8491 8492 8493 8494 8500 8510 8520 8530 9499 9500 9510 9520 9530 9540 9550 9560 9570 9580 9590 Freescale Semiconductor Inc Application Note SUBROUTINE TO READ IN ONE BYTE THROUGH THE COMM PORT OPENED AS FILE 2 WAITS INDEFINITELY FOR THE BYTE TO BE RECEIVED SUBROUTINE WILL BE ABORTED BY ANY KEYBOARD INPUT RETURNS BYTE IN B USES 5 W 0 WEND B R ETURN HILE LOC 2 0 EYS IF 05 lt gt THEN 4900 ANY KEY PRESSED THEN ABORT UTS 1 WAIT FOR COMM PORT INPUT 2 UKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK
29. to 125 C 2 MHz MC68HC1 1E0MB2 M68HC11E Family Rev 5 Data Sheet MOTOROLA Ordering Information and Mechanical Specifications 195 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Ordering Information and Mechanical Specifications 11 3 Custom ROM Device Ordering Information Description Temperature Frequency MC Order Number 52 pin plastic leaded chip carrier PLCC 0 to 70 3 MHz MC68HC11E9FN3 2 MHz MC68HC11E9CFN2 40 to 85 C Custom ROM 3 MHz MC68HC11E9CFN3 40 to 105 C 2 MHz MC68HC11E9VFN2 40 to 125 C 2 MHz MC68HC11E9MFN2 0 C to 70 C 3 MHz MC68HC11E20FN3 2 MHz MC68HC11E20CFN2 40 to 85 C 20 Kbytes custom ROM 3 MHz MC68HC11E20CFN3 40 to 105 C 2 MHz MC68HC11E20VFN2 40 to 125 C 2 MHz MC68HC11E20MFN2 64 pin quad flat pack QFP 0 C to 70 C 3 MHz MC68HC11E9FU3 2 MHz MC68HC11E9CFU2 40 to 85 C Custom ROM 3 MHz MC68HC11E9CFU3 40 to 105 C 2 MHz MC68HC11E9VFU2 40 to 125 C 2 MHz MC68HC11E9MFU2 64 pin quad flat pack continued 0 C to 70 C 3 MHz MC68HC11E20FU3 2 MHz MC68HC11E20CFU2 40 to 85 C 20 Kbytes Custom ROM 3 MHz MC68HC11E20CFU3 40 to 105 C 2 MHz MC68HC11E20VFU2 40 to 125 C 2 MHz MC68HC1 1E20MFU2 52 pin thin quad
30. 0 Break generator off 1 Break codes generated M68HC11E Family Rev 5 124 Serial Communications Interface SCI MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Communications Interface SCI SCI Registers 7 7 4 Serial Communication Status Register The SCSR provides inputs to the interrupt logic circuits for generation of the SCI system interrupt Address 102 Bit 7 6 5 4 3 2 1 Bit 0 Read TDRE TC RDRF IDLE OR NF FE Write Reset 1 1 0 0 0 0 0 0 Unimplemented Figure 7 6 Serial Communications Status Register SCSR TDRE Transmit Data Register Empty Flag This flag is set when SCDR is empty Clear the TDRE flag by reading SCSR with TDRE set and then writing to SCDR 0 SCDR busy 0 SCDR empty TC Transmit Complete Flag This flag is set when the transmitter is idle no data preamble or break transmission in progress Clear the TC flag by reading SCSR with TC set and then writing to SCDR 0 Transmitter busy 1 Transmitter idle RDRF Receive Data Register Full Flag This flag is set if a received character is ready to be read from SCDR Clear the RDRF flag by reading SCSR with set and then reading SCDR 0 SCDR empty 1 SCDR full IDLE Idle Line Detected Flag This flag is set if the RxD line is idle Once cleared IDLE is not set again until the RxD line has been acti
31. 333 ns for 3 MHz rating Vy lt 0 2 V gt 0 2 V dc loads Data Sheet M68HC11E Family Rev 5 168 Electrical Characteristics MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Characteristics MC68L11E9 E20 DC Electrical Characteristics 10 7 MC68L11E9 E20 DC Electrical Characteristics Characteristics Symbol Min Max Unit Output voltage 2 10 Load 10 0 uA V OL 0 1 V All outputs except XTAL Vpp 0 1 All outputs except XTAL RESET and MODA Output high voltage lLoad 0 5 mA 3 0V 0 8 MA Vpp 4 5 V All outputs except XTAL RESET and MODA Output low voltage 1 6 MA Vpp 5 0 V