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MAXIM MAX98089 Low-Power Stereo Audio Codec with FlexSound Technology handbook

1. Line to ADC TOTAL HARMONIC DISTORTION PLUS TOTAL HARMONIC DISTORTION PLUS TOTAL HARMONIC DISTORTION PLUS NOISE NOISE vs FREQUENCY LINE TO ADC NOISE vs FREQUENCY LINE TO ADC vs FREQUENCY LINE TO ADC 0 5 8 0 8 40 MCLK 12 288MHz 5 10 MCLK 12 288MHz E aa LRCLK 48kHz LRCLK 48kHz E 20 MODE 2 I MODE 12 20 viae 24430 Vin 1 4Vp p L3 Vin 1Vp p m d z AVPGAIN_ 6dB AVpGaIn_ 098 ei e 40 40 Cin Cin IN 7 2 amp 50 amp 50 40 E 60 2 60 50 70 70 60 80 8 90 9 70 100 10 80 10 0 1 10k 100k 10 100 k 10k 100k 10 0 1k 10k 100k FREQUENCY FREQUENCY FREQUENCY TOTAL HARMONIC DISTORTION PLUS NOISE POWER SUPPLY REJECTION RATIO vs FREQUENCY LINE IN TO ADC vs FREQUENCY LINE TO ADC 12 x MCLK 12 288MHz 8 E 200mVp p 10 LRCLK 48kHz THE RIPPLE 20 Vin 3 EXTERNAL
2. TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY DAC TO HEADPHONE vs OUTPUT POWER DAC TO HEADPHONE 0 0 MCLK 12 288MHz 8 LRCLK 48kHz 8 8 5 LRCLK 8kHz z gg MODE 3 20 FREQ MODE 3 LOW POWER MODE ncc 30 amp 30 308 40 E 40 e 50 50 Ea 60 60 70 70 80 80 90 90 0 0 01 002 0 03 0 04 0 05 0 06 0 07 10k OUTPUT POWER W FREQUENCY Hz TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY DAC TO HEADPHONE vs FREQUENCY DAC TO HEADPHONE vs FREQUENCY DAC TO HEADPHONE 0 5 8 8 MCLK 13 2 CLK 12 288MHz CLK 12 288MHz 5 10 5 LRCLK 48kHz E RCLK 96kHz E 20 20 NI MODE 3 MODE 3 P RHP 320 HP 320 30 8 3 39 S 308 o E 50 5 60 60 70
3. TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER DAC TO HEADPHONE vs OUTPUT POWER DAC TO HEADPHONE vs OUTPUT POWER DAC TO HEADPHONE 0 8 0 8 0 1 MCLK 12 288MHz 10 MCLK 12 288MHz 2 12 288MHz LRCLK 48kHz 5 LRCLK 96kHz 5 10 96kHz 3 20 NI MODE 5 20 NI MODE E 20 LN E 3 Rup 320 23 RHP 320 Ry 318 amp 308 amp 9 amp 40 WLP PACKAGE 5 40 TOFN PACKAGE 40 WLP PACKAGE amp 5 amp 5 amp 50 60009 gt 6000Hz 2 60 60 6000Hz 7 f 1000Hz 7 f 1000Hz 70 80 80 80 90 f 100Hz 90 Sf 0 0 100 100 100 0 0 010 0 020 0 030 0040 0 050 0 0 010 0 020 0 030 0 040 0 050 0 0 010 0 020 0 030 0040 0 050 0 005 0 015 0 025 0 035 0 045 0 005 0 015 0 025 0 035 0 045 0 005 0 015 0 025 0 035 0 045 OUTPUT POWER W OUTPUT POWER W OUTPUT POWER TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER DAC TO HEADPHONE vs OUTPUT POWER DAC TO HEADPHONE vs FREQUENCY DAC TO HEADPHONE 0 0 0 x MCLK
4. NOISE vs OUTPUT LEVEL TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE LINE IN TO LINE OUT vs FREQUENCY LINE IN TO LINE OUT vs FREQUENCY LINE IN TO LINE OUT 0 0 g 0 8 RLOAD 5 Vin 2 E m 5 10 10ko 5 E E 20 EXTERNAL GA 5 20 20 Rext 56kQ 30 amp 30 30 amp 40 40 E 40 50 50 t 50 5 60 60 10 70 40 80 80 90 90 90 100 0 02 04 06 08 10 12 14 10 100 1k 10k 100k 10 100 1k 10k 100k OUTPUT LEVEL Vrms FREQUENCY Hz FREQUENCY Hz MAXIM Maxim Integrated Products 38 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 21 CMICBIAS CREG CC1N C1P CHPVDD CHPvss AVMICPRE_ 20d0B AVMICPGA_ AVDACATTN AVDACGAIN
5. TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION OUTPUT POWER vs SUPPLY VOLTAGE vs OUTPUT POWER DAC TO RECEIVER vs FREQUENCY DAC TO RECEIVER DAC TO RECEIVER 8 200 5 MCLK 13MHz MCLK 13 8 2 8 LRCLK 8kHz 5 LRCLK 8kH 3 2 180 5 FREQ MODE FREQ MODE 5 THD N 10 E 25 RREC 320 2 320 85 160 E 4808 S 8 MCLK 13MHz c 140 LRCLK 8kHz 1000Hz 3000Hz 2 FREQ MODE ES ES 120 320 N 808 100 2 S 80 60 0 002 004 006 0 08 010 012 10k 25 30 35 40 45 50 55 OUTPUT POWER W FREQUENCY Hz SUPPLY VOLTAGE V GAIN vs FREQUENCY POWER CONSUMPTION vs OUTPUT POWER SUPPLY REJECTION RATIO DAC TO RECEIVER POWER DAC TO RECEIVER vs FREQUENCY DAC TO RECEIVER 8 8 12 E MCLK 13MHz 5 PPLE 200mVp p 5 E LRCLK 8kHz E ii E FREQ MODE E RIPPLE 0 4848 5 320 8 5 Fd e 6 a lt 2 5 5 1 2 10k 0 2 40 60 80 100 120 140 00k FREQUENCY Hz OUTPUT POWER PER CHANNEL mW FREQUENCY Maxim Integrated Products 35 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPK
6. REGISTER B7 B6 B5 B4 B3 B2 B1 ADDRESS DEFAULT R W LEVEL CONTROL Sidetone DSTS 0 DVST Ox2E oxoo R W 78 Playback DV1M 0 DV1G DV1 Ox2F RW 95 DAI Playback 0 0 0 1 DVEQ1 0x30 oxoo R W 94 Leve DAI2 Playback DV2M 0 0 0 0x31 R W 95 Leve DAI Playback 0 0 0 EQCLP2 DVEQ2 0x32 oxoo R W 94 Leve 27 0 0 AVL 0x33 R W 77 ne 0 0 AVRG AVR 0x34 R W 77 icrophone Ti PA1EN PGAM1 0x35 R W 70 Input Level lcrophone 2 g PA2EN PGAM2 0x36 0x00 R W 70 Input Level ddl o INAEXT 0 0 0 PGAINA 0x37 R W 72 ponia o INBEXT 0 0 0 PGAINB 0x38 R W 72 Left Headphone Amplifier HPLM 0 0 HPVOLL 0x39 111 Volume Control Righ Headphone Amplifier HPRM 0 0 HPVOLR 111 Volume Control Left Receiver Amplimer RECLM 0 0 RECVOLL Ox3B R W 99 Volume Control Right Receiver Amplifier RECRM RECVOLR Ox3C oxoo R W 99 Volume Control MAKIL Maxim Integrated Products 63 Table 1 Register Map continued MAX98089 Low Power Stereo Audio Codec with FlexSound Technology
7. Note 6 PARAMETER SYMBOL CONDITIONS MIN UNITS LINE INPUT PREAMP AVPGAIN OdB 1 Full Scale Input VIN AVPGAIN 6dB 14 Vp p PGAINA PGAINB 0x0 19 20 21 PGAINA PGAINB 1 1 14 15 PGAINA PGAINB 0x2 2 3 4 Level Adjust Gain _ PGAINA PGAINB 0x3 0 dB PGAINA PGAINB 0x4 4 3 2 PGAINA PGAINB 0x5 Ox6 Ox7 k 5 AVPGAIN_ 20dB 14 5 21 28 AVPGAIN_ 14dB 20 AVPGAIN_ 20 Input Resistance RIN 00B 75 10 14 AVPGAIN_ 20 AVPGAIN_ 20 Feedback Resistance INAEXT INBEXT 1 i kQ TA TMIN to TMAX 16 24 ADC LEVEL CONTROL ADC Level Adjust Range AVADCLVL AVL AVR OxF to 0x0 Note 5 12 3 dB ADC Level Step Size 1 ADC Gain Adjust Range AVADCGAIN AVLG AVRG 00 to 11 Note 5 0 18 ADC Gain Adjust Step Size 6 dB ADC DIGITAL FILTERS VOICE MODE IIR LOWPASS FILTER 0 Ripple limit cutoff 0 441 x fs Passband Cutoff cutoff fe Hz Passband Ripple f lt 0 1 0 1 dB Stopband Cutoff 0 47 x fs Hz Stopband Attenuation posi 74 dB MAXIM Maxim Integrated Products 9 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker
8. AVHP PARAMETER SYMBOL CONDITIONS MIN UNITS DAC TO HEADPHONE AMPLIFIER PATH Master or slave mode 101 Slave mode 97 Dynamic Range Note 4 DR fs 48kHz E dB Low power mode 95 97 25 C RHP 160 84 64 Total Harmonic Distortion THD N f 1kHz Pour 20mW 6 dB Noise RHP 320 85 HPL to HPR and HPR to HPL Pout 5mW Crosstalk f 1kHz Rup 320 92 dB VAVDD VPVDD 1 65V to 2 0V 46 54 f 217Hz VRIPPLE 200mVp p 72 AVHP_ Power Supply Rejection Ratio PSRR f 1kHz VRIPPLE 200mVp p dB 63 AVHP_ f 10kHz VRIPPLE 200mVp p 43 AVHP_ ODE 0 voice 8 2 2 2 1kHz OdB input highpass MODE 0 voice 14 16 2 DAC Path Phase Delay bd Measured ms from digital input to analog 1 music output 8kHz 4 5 ODE 1 music 48kHz He Gain Error 1 5 Channel Gain Mismatch 1 Peak voltage A weighted Into shutdown 62 Click and Pop Level 32 samples per second dBV AVHP_ Out of shutdown 63 LINE INPUT TO HEADPHONE AMPLIFIER PATH Total Harmonic Distortion THD N 1Vep f 1kHz Rup 320 81 dB Noise Dynamic Range Note 4 92 5 dB Peak voltage A weighted Into shutdown 62 Click and Pop Level 32 samples per second dBV Out of shutdown 63 MAALM Maxim Integrated Products 17
9. MAXIM MAX98089 s E JE E zo D 2 MAXIM Maxim Integrated Products 5 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology ABSOLUTE MAXIMUM RATINGS Voltages with respect to AGND DVDD AVDD PVDD HPVDD SPKLVDD SPKRVDD DVDDS1 DVDDS2 DGND HPGND SPKLGND SPKRGND FIPVSS ied etos VHPGND 2 2V CIN sr dete VHPVSS 0 3V t t EMT 0 3V to 2 2V 0 3V to 6 0V 0 1V to 0 1V VHPGND 0 3V VHPGND 0 3V CAP attendue VHPGND 0 3V t
10. TOTAL HARMONIC DISTORTION PLUS TOTAL HARMONIC DISTORTION PLUS TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY MIC TO ADC NOISE vs FREQUENCY MIC TO ADC NOISE vs FREQUENCY MIC TO ADC 0 0 8 MCLK 13MHz MCLK 13MHz E MCLK 12 288MHz 5 LRCLK 44 1kHz 5 RCLK 48kHz 5 E 20 LPLL MODE E 20 MO E Vin 1Vp p L3 N S amp 30 008 5 VMICPRE_ 048 o 40 40 amp 50 E 50 2 60 E 60 40 70 80 80 90 90 100 10k 10 00 1k 10k 100k 10 100 1k 10k 100k FREQUENCY Hz FREQUENCY Hz FREQUENCY Hz TOTAL HARMONIC DISTORTION PLUS TOTAL HARMONIC DISTORTION PLUS TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY MIC TO ADC NOISE vs FREQUENCY MIC TO ADC NOISE vs FREQUENCY MIC TO ADC 0 0 E CLK 12 288MHz 5 MCLK 13MHz MCLK 13MHz LRCLK 96kH 5 LRCLK 8kHz 5 LRCLK 8kHz 5 MO 20 ODE 5 20 FREQ MODE 2 1 L3 Vp p L3 Vin 0 032Vp p _ 200 309 40 40 amp 50 50 6 2 4 70 70 80 80 90 90 100 100 10 100 1k 10k 100k 10 100 1k 10k 10 100 1k 10k FREQUENCY FREQUENCY Hz FREQUENCY Hz MAXIM Maxim Integrated Products 28 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD
11. REGISTER BIT NAME DESCRIPTION AGC Attack Time 3 Defined as the time required to reduce gain by 63 of the total gain reduction one time constant of the exponential response Attack times are longer for low AGC threshold AGCATK levels See Figure 12 for details 00 2ms 2 01 7 2ms 10 2 31ms 11 123ms AGC Hold Time 1 The delay before the AGC release begins The hold time counter starts whenever the sig nal drops below the AGC threshold and is reset by any signal that exceeds the threshold AGCHLD Set AGCHLD to enable the AGC circuit See Figure 12 for details 00 AGC disabled 0 01 50ms 10 2 100ms 11 2 400ms Noise Gate Threshold 7 Gain is reduced for signals below the threshold to quiet noise The thresholds are relative to the ADC s full scale output voltage THRESHOLD THRESHOLD VALUE dBFS VALUE dBFS 9 0 0 Noise gate disabled Ox8 45 ANTH Ox1 Reserved Ox9 41 0x2 Reserved OxA 38 5 Ox3 64 OxB 34 0 4 62 OxC 30 0 5 58 OxD 27 4 0x6 53 OxE 22 Ox7 50 OxF 16 Ox40 AGC Threshold 3 Gain is reduced when signals exceed the threshold to prevent clipping The thresholds are relative to the ADC s full scale voltage THRESHOLD THRESHOLD VALUE dBFS VALUE dBFS 3 0 8 11 AGCTH Ox1 4 9 12 0x2 5 OxA 13 1 Ox3 6 OxB 14 Ox4 7 OxC 15 0x5 8 OxD 16 0 0x6 9 OxE 17 Ox7 10 OxF 18 Maxim Integrated Products 75 MAX98089 L
12. 10 0 1 10k 100k Ok FREQUENCY Hz FREQUENCY Hz GAIN vs FREQUENCY DAC TO HEADPHONE 98089 10102 NORMALIZED GAIN dB Ok FREQUENCY Hz Maxim Integrated Products 48 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL or LOUTR to SPKLGND CREF 2 2uF CMICBIAS CREG 1UF CC1N C1P CHPVDD CHPvss AVMICPRE_ 209 AVMICPGA_ AVDACATTN AVDACGAIN AVADCLVL OGB AVADCGAIN AVPGAIN_ AVHP_ OdB AVREC AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted POWER CONSUMPTION vs OUTPUT CURRENT CONSUMPTION vs OUTPUT POWER SUPPLY REJECTION RATIO POWER DAC TO HEADPHONE POWER DAC TO HEADPHONE vs FREQUENCY DAC TO HEADPHONE MCLK 12 288MHz LRCLK 48kHz MCLK 12 288MHz LRCLK 48kHz LOW POWER MODE _ 308 LE ON SPKL SP
13. 12 288MHz LRCLK 48kHz MAS 0 TA TMIN to Tmax unless otherwise noted Typical values are at 25 C Note 1 PARAMETER SYMBOL CONDITIONS MIN UNITS Peak voltage A weighted 32 Into shutdown 68 Click and Pop Level samples per second AVREC dBV OdB Out of shutdown 72 LINE INPUT TO RECEIVER AMPLIFIER PATH Dynamic Range Note 4 DR Referenced to full scale output level 94 dB ee Distortion THD N 64 dB Peak voltage A weighted 32 Into shutdown 51 Click and Pop Level samples per second AVREC dBV OdB Out of shutdown 49 RECEIVER AMPLIFIER Output Power POUT RREC 32Q f 1kHz THD 1 92 mW Full Scale Output Note 7 1 VRMS RECVOL 0x00 62 Volume Control Note 5 AVREC RECVOL 3 dB 8dB to 6dB 0 5 to 0dB 1 Volume Control Step Size OGB to 14dB 2 dB 14dB to 38dB 3 38dB to 62dB 4 Mute Attenuation f 1kHz 88 dB T RREC 320 500 Capacitive Drive Capability No sustained oscillations pF REC 100 DAC TO LINE OUT AMPLIFIER PATH Dynamic Range Note 4 DR fs 48kHz f 1kHz 83 96 dB Harmonie Distortion THD N f 1kHz R 72 dB LINE INPUT TO LINE OUT AMPLIFIER PATH Dynamic Range Note 4 DR Referenced to full scale output level 92 dB Distortion THD N f kHz RL 10kQ 76 Full Scale Output Note 7 2 ute Attenuation f 1kHz 85 dB Output Offset Voltage Vos AVREC_
14. 65 C to 150 C Lead Temperature TQFN only soldering 105 300 C Soldering Temperature reflow 260 C VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out loads RLOUT connected from LOUTL or LOUTR to SPKLGND RLOAD RHP ee ZSPK CREF 2 2UF CMICBIAS CREG CC1N C1P CHPVDD CHPvsS 1uF AVMICPRE_ 200 AVMICPGA_ 088 AVDACATTN OdB AVDACGAIN OdB AVADCLVL AVADCGAIN OdB AVPGAIN_ OdB AVREC OdB AVspK_ 12 288MHz LRCLK 48kHz MAS TA TMIN to TMAx unless otherwise noted Typical values are at TA 25 C Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY VSPKLVDD VSPKRVDD 2 8 5 5 Supply Voltage Range Guaranteed by PSRR VDVDD VAVDD VPVDD 1 65 1 8 2 V VDVDDS1 VDVDDS2 1 65 3 6 Analog 4 5 8 Full duplex z mono receiver output MAS 1 Speaker 18 a Digita 1 3 2 DAC playback 48kHz Analog 1 9 3 Total Supply lvDD stereo headphone Speaker 0 001 0 0058 mA Notes 2 and 3 outputs MAS 1 Digita 247 3 5 DAC playback 48kHz
15. MAX 3277 3 0 70 0 75 0 80 0 75 0 80 0 75 0 80 0 75 0 80 0 80 14477 2 0 0 02 0 05 0 02 0 05 0 02 0 05 0 02 0 05 0 05 4477 3 0 20 REF 0 20 REF 0 20 REF 0 20 REF 4877 3 0 25 0 30 0 35 0 20 0 25 0 30 0 25 0 30 0 20 0 25 0 30 0 25 1487774 6 90 7 00 7 10 6 90 6 90 7 00 7 10 4877 6 6 90 7 00 7 10 6 90 6 90 7 00 7 10 TROIS 0 65 BSC 0 50 856 4877 1 ozs 221211 4877 6 4877MN 8 0 45 0 55 0 65 0 45 0 55 0 65 4877N 8 32 44 5677 1 8 10 5677 1 8 12 5677 2 DIMENSIONING amp TOLERANCING CONFORM TO ASME Y14 5M 1994 ALL DIMENSIONS ARE IN MILLIMETERS ANGLES ARE IN DEGREES IS THE TOTAL NUMBER OF TERMINALS HE TERMINAL 1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95 1 PP 012 DETAILS OF TERMINAL 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN HE ZONE INDICATED THE TERMINAL 1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 5 DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0 25 mm AND 0 30 mm FROM TERMINAL TIP N ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND SIDE RESPECTIVELY DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL A
16. 114 Accessory Button Detection cekat iik rs 114 Jack Removal duree dp ee ee x OO d e en ate deo 114 Battery Meas rertient arsi GR ROG Ren ka e Re dob A Xd aO ee ee 116 Device Status s cu deb EC RE ___ BA eee ee dd 117 DEVICE REVISION STETERIT Rc 118 PO Serial Interface s c etes qe apetece EE oe ea ea OY te A GNO ud n e Po eod 118 Bit ata Sk CR d ui oec ES dU eG 118 START and STOP GoriditloOhns 23 ote Rd ER emendet rem RR dog nad 4 118 Early STOP Cofidillons 4 3o WO bo 118 olavesAdcdtess x anu V do ang tr got x do Sq eod Ro Rd 119 A knowledge i Pond Gb Or PONE UU Yeh ended a PUT UA RU RC 119 Wiite Data Fotmat eng oS Be HR EM Se ee eee ee 119 HeadiDate FOLial aur dc Mates ete Guns dox 120 Applications Information 22 04 ________________ 121 Typical Operating 018055 2 o ua terrm ole d teu ho ee ee Sor Bee eh Ra 121 Class eet edes
17. AVspK_ OdB MCLK 12 288MHz LRCLK 48kHz MAS 0 TA TMIN to Tmax unless otherwise noted Typical values are at TA 25 C Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STEREO AUDIO MODE DC BLOCKING HIGHPASS FILTER MODE1 1 fauPPB 000 ud Hz DC Attenuation DCatten AVFLT 000 90 dB MICROPHONE AUTOMATIC GAIN CONTROL AGC Hold Duration arcu AGCHLD 11 400 AGCATK 00 2 AGC Attack Time ms AGCATK 11 123 AGC Release Time 5 AGCRLS 111 10 AGC Threshold Level AGCTH to OxF 3 18 dB AGC Threshold Step Size 1 dB AGC Gain Note 5 0 20 dB ADC NOISE GATE NG Threshold Level ANTH 0x3 to OxF referred to OdBFS 64 16 dB NG Attenuation Note 5 0 12 dB ADC TO DAC DIGITAL SIDETONE MODE 0 Gain Rae Range Ave dB DVST Ox1F 60 5 Gain Adjust Step 2 dB Sidetone Path Phase Delay ae OdB input highpass filter 2 ms disabled 16kHz 121 ADC TO DAC DIGITAL LOOP THROUGH PATH fs 48kHz MCLK 12 288MHz MODE 1 Mange MMOL DR FIR to HP sai pios ue Total Harmonic Distortion f 1kHz fs 48kHz MCLK 12 288MHz MODE Noise CHEAN 1 FIR MIC ni 9 88 DAC LEVEL CONTROL DAC Attenuation Range AVDACATIN DV_ OxF to OxO Note 5 15 0 dB DAC Attenu
18. 0 0 010 0 000 0 0 005 0 015 0 025 OUTPUT POWE MAALM R 0 040 0 050 035 0 045 10 12 14 16 18 20 FREQUENCY kHz FFT 60dBFS DAC TO HEADPHONE MCLK 12 288MHz LROLK 48kHz LOW POWER MODE Rup 320 98089 toc119 AMPLITUDE dBV FREQUENCY kHz TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY LINE TO HEADPHONE gt 20 lt x 0 e MAX98089 0121 m d THD N RATIO dB UT 0 02W 10 k 10k 100k FREQUE Maxim Integrated Products 52 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads Rpp connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL or LOUTR to SPKLGND CREF 2 2uF CMICBIAS CREG 1UF CC1N C1P CHPVDD CHPvss AVMICPRE_ 209 AVMICPGA_ AVDACATTN AVDACGAIN AVADCLVL OGB AVADCGAIN AVPGAIN_ AVHP_ OdB AVspK_ MCLK 12 288MHz LRCLK
19. 93 DAH DAI2 K2_5 7 0 Ox7F OxB1 RW 93 c1 5 15 8 Ox80 0xB2 R w 93 c1 5 7 0 0 81 0 3 93 c2_5 15 8 0 82 0 4 R W 93 c2_5 7 0 Ox83 0XB5 R w 93 1 15 8 OxB6 OXCO 93 1 7 0 0xB7 0xC1 93 2 15 8 OxB8 OxC2 93 Eveursian a2 7 0 OxB9 OxC3 93 Limiter 00 15 8 OxBA OxC4 93 Biquad bO 7 0 OxBB OXC5 RW 93 DAI1 DAI2 b1 15 8 OxBC OxC6 RW 93 b1 7 0 OxBD OxC7 RW 93 b2 15 8 OxBE OXC8 93 b2 7 0 OxBF OXC9 93 REVISION ID Rev ID REV OxFF 0x40 R 118 Maxim Integrated Products 66 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Power Management The IC includes comprehensive power management to allow the disabling of all unused circuits minimizing supply current Table 2 Power Management Registers REGISTER BIT NAME DESCRIPTION Global Shutdown Disables everything except the headset detection circuitry which is 2 controlled separately 7 SED 0 Device Shutdown 1 Device Enabled 6 VBATEN See the Battery Measurement section Performance Mode Selects DAC to headphone playback performance mode 3 PERFMODE 0 High performance playback mode 1 2 Low power playback mode Headphone Only Playback Mode Configures System Bias Control register bits for low
20. MIC2 1 MIC 1 xxx1xxxx INB2 INBDIFF 0 or INB2 INB1 INADIFF 1 1 INB1 1 INA2 INADIFF 0 or INA2 INA1 INADIFF 1 1 INA1 1 Left DAC 0x29 5 101 1 MIXRECR LINE_MODE Right Receiver Output Mixer 1 Left DAC x1xxxxxx MIC2 1 MIC1 xxx1xxxx INB2 INBDIFF 0 or INB2 INB1 INBDIFF 1 XXxx1xxx INA1 INA2 INADIFF 0 or INA2 INA1 INADIFF 1 XXxxxx1lx INA1 Xxxxxxx1 Right DAC Receiver Output Mode Configures receive path output mode between BTL and stereo line output 0 1 Stereo line output Ox2A MIXRECR _GAIN Right Receiver Mixer Gain Select 00 01 10 9dB 11 12dB MIXRECL GAIN Left Receiver Mixer Gain Select 00 OdB 01 6dB 10 9dB 11 12dB MAALM Maxim Integrated Products 98 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Receiver Output Volume Table 21 Receiver Output Level Register REGISTER BIT NAME DESCRIPTION 1 Enabled 4 Receiver Output Volume Level VALUE VOLUME dB VALUE VOLUME dB 0x00 62 0x10 10 3 0x01 58 0x11 8 0x02 54 0x12 6 0x03 50 0x13 4 0x04 46 0x14 2 0x3B
21. Figure 40 Typical Application Circuit Using Analog Microphone Inputs and the Bypass Switch MAKILA Maxim Integrated Products 121 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology 2 8V 5 5V 0uF 1 8V TO 3 6V 1 8V TO 3 6V 0 1uF 10pF uF O 1uF 010051 DVDD AVDD SPKLVDD SPKRVDD 00052 10kQ TO MICROCONTROLLER lt BCLKS2 10MHz TO 60MHz CLOCK INPU MCLK LRCLKS2 Ke v BCLKS1 SDINS2 AUDIO lt gt LRCLKS1 SDOUTS2 PORT 1 SDINS1 JACKSNS G SDOUTS1 RECP RXI SDA RECN RXI 12C CONTROL PORT DIGITAL SPKL MIC 1 P DIGMICDATA MAXIM SPK MAX98089 DIGMICCLK DIGITAL MIC 2 AS JACKSNS HEADSET MICROPHONE A1 EXTMICP LINE INPUT A2 EXTMICN B1 LINE INPUT B2 DGND AGND HPGND SPKRGND SPKLGND HPVDD HPVSS CIN Figure 41 Typical Application Circuit Using the Digital Microphone Input and Receiver Amplifier Maxim Integrated Products 122 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Filterless Class D Operation Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier s output The filters add cost increase the solution size of the amplif
22. N 5 s N re ip SNM DVDDS1 5 SDINST 5 5 HarL f DGND BCLKS2 180182 1 1 MICBIAS DIGMICCLK 1500752 DVDDS2 SDINS2 1 1 AGND MIC2N MIC2P AVLA2CLAVI Maxim Integrated Products 55 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Pin Configuration TOP VIEW IC1N DIGMICCLK 1C1P DIGMICDATA A1 EXTMICP A2 EXTMICN D P LOUTL RXINP LOUTR RXINN MAXIM MAX98089 PKRVDD PKRGND PKRN SDOUTS2 7mm x 7mm x 0 75mm EXPOSED PAD CONNECT TO GROUND PLANE IVI Maxim Integrated Products 56 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Bump Pin Description BUMP PIN WLP FUNCTION A1 B1 15 SPKRN Negative Right Channel Class D Speaker Output A2 B2 16 SPKRGND jRight Speaker Ground B3 19 SPKLVDD Left Speaker REF Receiver Amp Power Supply Bypass to SPKLGND with a 1uF and a 10pF capacitor A4 B4 20 SPKLP Positive Left Channel Class D Speaker Output A5 B5 22 SPKLN Negative Left Channel Class D Speaker Output RECP LOUTL Positive Receiver Amplifier Output or Left Line Output Can be positive bypass
23. 2 4 6 8 FREQUENCY kHz Maxim Integrated Products 51 MAX98089 106116 10 12 14 16 18 20 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads Rpp connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2 CMICBIAS CREG CC1N C1P CHPvss AVMICPRE_ 42088 AVMICPGA_ AVDACATTN AVDACGAIN AVADCLVL AVADCGAIN 088 AVPGAIN_ OdB AVHP_ AVsPK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 Ta 25 C unless otherwise noted FFT 60dBFS DAC TO HEADPHONE MCLK 12 288MHz 2 LRCLK 96kHz NI MODE Rup 320 MAX98089 10 117 FFT OdBFS DAC HEADPHONE MCLK 12 288MHz LRCLK 48kHz LOW POWER MODE RHP 320 MAX98089 toc118 AMPLITUDE dBV do FREQUENCY kHz AMPLITUDE 6 8 Line to Headphone TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER LINE TO HEADPHONE MAX98089 toc120 THD N RATIO dB
24. Rapid Lock Mode Program NI1 NI2 to the nearest valid ratio and set NI1 O NI2 0 when PLL1 PLL2 1 0 NIHTOJ NI2 O to enable rapid lock mode Normally the PLL automatically calculates and dynamically adjusts NI1 NI2 When rapid lock mode is properly configured the PLL starting point is much closer to the correct value thus speeding up lock time Wait one LRCLK period after programming NI1 NI2 before setting PLL1 PLL2 1 MAKII Maxim Integrated Products 86 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 11 Clock Control Registers continued REGISTER BIT NAME DESCRIPTION DAI_ DAC Low Power Select 7 These bits setup the clocks to be generated from fixed counters that bypass the PLL for DAC low power mode FILTER FILTER VALUE SETTING SELECT VALUE SETTING SELECT DAI2_DAC_LP PLL derived PCLK 2304 OxO clock 0 8 x LRCLK Voice p 5 Ox1 128 Audio 96kHz 0x9 Reserved x LRCLK p 4 0x2 192 Audio 96kHz OxA Reserved Ox4F x LRCLK p Ox3 Audio 48kHz OxB Reserved x LRCLK p 0x4 CERA 984 Audio 48kHz OxC Reserved x LRCLK p 2 DAI1_DAC_LP 0x5 Voice OxD Reserved x LRCLK PCLK 1152 1 Ox6 x LRCLK Voice Reserved PCLK 1536 0 0 7 x LRCLK Voice OxF Reserved DAI2 DAC Input Dither Enable 3 DAC2DITHEN DAC2DITHEN is recommended to b
25. REGISTER B7 B6 B5 B4 B3 B2 B1 ADDRESS DEFAULT R W Left Speaker CONDE SPLM 0 0 SPVOLL Ox3D R W 102 Volume Control Right Speaker Amplifier SPRM 0 0 SPVOLR Ox3E 0x00 R W 102 Volume Control MICROPHONE AGC Configuration AGCSRC AGCRLS AGCATK AGCHLD Ox3F 74 75 Threshold ANTH 0 40 R W 75 SPEAKER SIGNAL PROCESSING Excursion 0 DHPUCF 0 0 DHPLCF 41 oxoo R W 104 Limiter Filter Excursion Limiter 0 0 0 0 0 DHPTH 0x42 R W 104 Threshold ALC ALCEN ALCRLS ALCMB ALCTH 0x43 R W 03 104 Power Limiter PWRTH 0 PWRK 0x44 0x00 105 Power Limiter PWRT2 1 0 45 0 00 R W 106 THDCLP 0 0 0 THDT1 0x46 R W 107 Limiter CONFIGURATION Audio Input INADIFF INBDIFF 0 0 0 0 0 0 47 R W 72 Microphone MICCLK DIGMICL DIGMICR 0 EXTMIC 0x48 0x00 R W 70 Level Control VS2EN VSEN ZDEN 0 0 0 0x49 R W 94 113 Bypass INABYP 0 MIC2BYP 5 Rw 7 Switches 112 Jack JDETEN 0 0 0 0 JDEB 4 R W 115 Detection POWER MANAGEMENT Input Enable INAEN INBEN MBEN ADLEN ADREN 0x4C R W 67 us HPLEN HPREN SPLEN SPREN RECLEN RECREN DALEN DAREN 0 40 R W 68 Rope oue BGEN SPREGEN VCMEN BIASEN JDWK Ox4E OxFO R W 68 Bias Control 2 DAC LP DA
26. ex Us qeu E enor eek Weds Reales Game UE ei d ard ion ade 101 Speaker Amplifier Signal Processing hh e s 102 EXGUFSIOTT iod Meee educere Oe P se spei 102 Speaker Output s uscite stes 102 Power zucca RR peed I UN D SAE he EAE ods 105 Distortion Limiter sa negn adaa gah Mw RR RI oe Ae eR a ios Sx aa de ug ar SD p den sad 106 Headphone RM EIE ER 107 DirectDrive Headphone Amplie ub ae LE 107 Charge PUMP AAA s Rage AA a dod 107 Class H Operation a er ducet _______ 108 Headphone Ground Sense 5 00 eee ee 108 Headphone Output Mixers 0 ete 110 Headphone Output ek hen deed ee eee Ra Re RUE 111 Output BY PaSS SWICHESs 3 223 dtt utt ES abr A Aa 112 GlicksandsPopiheductiOPihs 113 Maxim Integrated Products 3 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology TABLE OF CONTENTS continued JACK DELCCHON kh ange Ae 114 ACK ION
27. REGISTER ADDRESS A SLAVE ADDRESS DATABYTE L 1 1 1 1 1 REPEATED START 4 R W 4 Figure 39 Reading n Bytes of Data from the ICs AVLAX LA 1BYTE A CREMENT INTERNAL REGISTER ADDRESS POINTER UTOI Maxim Integrated Products 120 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Applications Information Typical Operating Circuits Figures 40 and 41 provide example operating circuits for the ICs The external components shown are the minimum required for the ICs to operate Additional components may be required by the application 2 8V 5 5V 1 8V TO 3 6V 1 8V TO 3 6V 0 1uF 10uF 0 1yF Eon DVDDS1 PVDD DVDD AVDD SPKLVDD SPKRVDD 010052 10kQ TO MICROCONTROLLER lt BCLKS2 10MHz TO 60MHz CLOCK INPUT CLK LRCLKS2 lt gt BCLKS1 SDINS2 lt gt LRCLKS1 SDOUTS2 DIGITAL AUDIO PORT 1 80151 JACKSNS SDOUTS1 RECP RXINP 12C CONTROL RECN RXINN PORT SPKL MICROPHONE C1P DIGMICDATA MAXIM SPKL OUTPUT TO MAX98089 BASEBAND C1N DIGMICCLK SPK e CBIAS JACKSNS lt lt 2 2kQ e C2P HEADSET MICROPHONE C2N HANDSET MICROPHONE IA2 EXTMICN NB1 LINE INPUT NB2 AGND HPGND SPKRGND SPKLGND HPVDD HPVSS CIN
28. AVADCLVL OGB AVADCGAIN AVPGAIN_ AVHP_ OdB AVREC AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted DAC to Speaker TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER DAC TO SPEAKER vs OUTPUT POWER DAC TO SPEAKER 0 i vpp 4 2V VSPK_VDD 3 7V E 10 MCLK 12 288MHz 8 10 MCLK 12 288MHz 8 20 LRCLK 48kHz 20 LRCLK 48kHz NI MODE 7 NI MODE amp 30 ZspK_ 8Q 68H amp 3 Zsp_ 8Q 68H o ii _ 808 5 AVspk_ 808 f 6000H f 600092 50 5 60 f 1000Hz 4 70 7 80 f 100Hz 8 90 9 0 02 04 06 08 10 12 14 0 0 2 0 4 06 08 10 OUTPUT POWER W OUTPUT POWER W TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER DAC TO SPEAKER vs OUTPUT POWER DAC TO SPEAKER vs OUTPUT POWER DAC TO SPEAKER 8 0 0 VsPk vpp 3 0V VSPK_VDD 5 0V 8 VsPk vpD 5 0V MCLK 12 288 10 FMCLK 12 288MHz 8 10 MCLK 12 288 2 8 LRCLK 48kHz 20 LRCLK 48kHz 20 LRCLK 48kHz E NI MODE NI MODE NI MODE Zspk 80 a 30 LZsPK 40
29. MCLK 12 288MHz LRCLK 48kHz MAS 1 Ta 25 C unless otherwise noted ADC ENABLE DISABLE RESPONSE FFT 60dBFS MIC TO ADC MIC TO ADC 98089 toc18 MCLK 12 288MHz LRCLK 96kHz NI MODE AVMICPRE_ 098 1 1 98089 toc17 AMPLITUDE dBFS 1 ADC oureur 0 5V div 20 10ms div FREQUENCY kHz SOFTWARE TURN ON OFF RESPONSE MIC TO ADC MAX98089 toc19 1 1V div J ADC OUTPUT 05V div 10ms div MAXIIAVI Maxim Integrated Products 31 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2yF CREG CC1N C1P CHPVDD CHPvss AVMICPRE_ 20d0B AVMICPGA_ AVDACATTN AVDACGAIN AVADCLVL OGB AVADCGAIN AVPGAIN_ AVHP_ OdB AVREC AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted
30. a rt zour e C i 5 X X X soro X m X X ISETUP tHOLD 1 ISETUP HOLD a c e i i 158 SDIN LB X X X MASTER MODE SLAVE MODE Figure 2 TDM Audio Interface Timing Diagram 1 FSW_ 0 i 4 Bear IBCLKH IBCLKL tose s gt i HZQUT Mel SNK SN X 158 X HI Z X X i tSeTUP HOLD tSeTUP 5 i gt lt gt X ws Y X X MASTER MODE SLAVE MODE Figure 3 TDM Audio Interface Timing Diagram TDM_ 1 FSW_ 1 DIGITAL MICROPHONE TIMING CHARACTERSTICS VAVDD VHPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V TA 25 C unless otherwise noted Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MICCLK 00 PCLK 8 MICCLK 01 PCLK 6 DIGMICCLK Frequency fMICCLK OP 120 51580 MICCLK 10 fLRCLK DIGMICDATA to DIGMICCLK E Setup Time tSU MIC Either clock edge 20 ns DIGMICDATA to DIGMICCLK Either clock ed 0 Hold Time MAKIL Maxim Integrated Products 23 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology 1 ficcLk gt ISUMIC
31. Xn rs At NNN WCI_ 0 BCI 1 DLY_ 0 TDM_ 1 FSW_ 0 WS_ 0 HIZOFF_ 1 SLOTL_ 0 SLOTR_ 1 ca 0185 84 85 82811 80 at ROK NS NY X ARAR AR AR AR AR AG AG A A A A A ARAR ARANAN ARAR NN ES m 5 65 9 89 0 t3 X o 85 84 5 2 00 0 CO ROK NS NY X 0 1 DLY_ 0 TDM_ 1 FSW_ 0 WS_ 0 HIZOFF_ 0 SLOTL_ 2 SLOTR_ 3 LRCLK SDOUT 9 ua us Kus Kua 81214 Y Lo fisso en Ro 85 Y Ra BCLK ABER AR ALAR AR ARAL ALAR ARAL ALAR ARAL ALAR AR ARAL ALAR ARAL ALAR ALAR ARAL AR SDIN or 5 e Y Co co 5 84 5 82811 re NNN 1 WCI_ 0 1 DLY_ 0 TDM_ 1 FSW_ 0 WS_ 0 HIZOFF_ 0 SLOTL_ 0 SLOTR_ 1
32. 0x18 0x20 Digital Passband Filters 0x25 to Ox2D Analog Mixers 0x52 to OxC9 Digital Signal Processing Coefficients MAXIMA SPKP 98089 spk N Figure 42 Optional Class D Ferrite Bead Filter AVLAZCLA Maxim Integrated Products 124 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Charge Pump Flying Capacitor The value of the flying capacitor connected between C1N and affects the output resistance of the charge pump A value that is too small degrades the device s ability to provide sufficient current drive which leads to a loss of output voltage Increasing the value of the flying capacitor reduces the charge pump output resistance to an extent Above 1uF the on resistance of the internal switches and the ESR of external charge pump capaci tors dominate Table 40 Unused Pins Charge Pump Holding Capacitors The holding capacitors bypassing HPVSS to HPGND and HPVDD to HPGND value and ESR directly affect the ripple at HPVSS and HPVDD Increasing the capacitor s value reduces output ripple Likewise decreasing the ESR reduces both ripple and output resistance Lower capacitance values can be used in systems with low maximum output power levels Unused Pins Table 40 shows how to connect the IC s pins when circuit blocks are unused NAM
33. 75 dB VOICE MODE IIR HIGHPASS FILTER MODE1 0 DVFLT 0x1 Elliptical tuned for fs 16kHz 0 0161 217Hz notch X TS DVFLT 0x2 500Hz Butterworth tuned for fs 0 0312 16kHz x fs Passband Cutoff DVFLT 0x3 Elliptical tuned for fs 8kHz 217Hz 0 0321 Hz from Peak DIETE notch x fs DVFLT 0x4 500Hz Butterworth tuned for fs 0 0625 8kHz XTS DVFLT 0x5 fs 240 Butterworth DVFLT 1 Elliptical tuned for fs 16 2 217Hz notch 0 0139 x fS DVFLT 0x2 500Hz Butterworth tuned for fs 16kHz 0 0156 x fs Stopband Cutoff MT 30dB from Peak fpHPSB DVFLT 0x3 Elliptical tuned for fs 8kHz 217Hz 0 0279 x fs Hz notch DVFLT 0x4 500Hz Butterworth tuned for fs 0 0312 x fs 8kHz DVFLT 0x5 fs 240 Butterworth 0 0021 x fs DC Attenuation DCATTEN DVFLT 000 85 dB STEREO AUDIO MODE FIR LOWPASS FILTER MODE1 1 DHF1 DHF2 0 LRCLK lt 50 2 Ripple limit cutoff 0 43 x fs Passband Cutoff fPLP cutoff 0 47 x fs Hz 6 02dB cutoff 0 5 x fs Passband Ripple f fpLP 0 1 0 1 dB Stopband Cutoff 0 58 x fs Hz Stopband Attenuation Note 6 f gt SLP 60 dB MAKILA Maxim Integrated Products 12 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and
34. AVDACGAIN AVADCLVL AVADCGAIN AVPGAIN_ AVHP_ AVREC AVspK_ OdB MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted Speaker Bypass Switch TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER ON RESISTANCE vs SPEAKER BYPASS SWITCH SPEAKER BYPASS SWITCH 4 5 RECEIVER AMPLIFIER 5 20 Vspk vpp 3 0V 1 DRIVING LOUDSPEAKER 8 35 E Zspk 80 2 5 20 3 0 3 2 25 f 1000kHz 5 50 1 5 60 1 7 05 80 0 0 005 00 015 0 20 0 25 0 1 2 3 4 5 6 OUTPUT POWER W V OFF ISOLATION vs FREQUENCY SPEAKER BYPASS SWITCH PEAKER AMP DRIVING LOUDSPEAKER PEAKER BYPASS SWITCH OPE EASURED AT RX nn 98089 toc128 LOAD ON RX OFF ISOLATION dB o RECEIVER AMP DRIVING 10 100 1k 10k 100k FREQUENCY Hz MAAKLM Maxim Integrated Products 54 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Bump Configuration TOP VIEW BUMP SIDE DOWN SPKRN ISPKRGND SPKLVDD SPKRN SPKRGND SPKLVDD SPKRP SPKRP 8 SPKLGND 8 MAXIM MAX98089 BCLKSt 15001181 SPKRVDD LROLKSI
35. LRCLK LEFT RIGHT SDOUT Y or 0 014011012 1 pio 08 TUTURUELELELELELELELELELELELELELELLTL T LL 01 01000 os os 05 s 02 oe ps o7 vs 05 o os 02 NN Figure 16 Non TDM Data Format Examples Maxim Integrated Products 83 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology 0 BCI 1 DLY_ 0 TDM_ 1 FSW_ 0 WS_ 0 HIZOFF_ 0 SLOTL_ 0 SLOTR_ 1 LRCLK SDOUT 82 15 4 211 0618 fue X ts Y La Y L3 Y Jmm mis mon Joy no Y Re 86 y BCLK vivivivivivivivivivivivivivivivivivivivivivivivvvviviviviviv SDIN to ce ur we X Y e oen Rs S NY 1 0 BCI 1 DLY_ 0 TDM_ 1 FSW_ 1 WS_ 0 HIZOFF_ 0 SLOTL_ 0 SLOTR_ 1 LRCLK SDOUT 87 15 04 3 fos e a ffi fio ro Ra Jv ne e eo YO RAR AR AR ARAB AR AR AR ARAL ALAR ARAL ARAL ARAL AL AD AL AL VV 05014 foe fe noe Lo 54 fo
36. MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Device Status either by poling register 0x00 or configuring the IRQ to The IC uses register 0x00 and IRQ to report the status of pull low when specific events occur IRQ is an open drain various device functions The status register bits are set output that requires a pullup resistor for proper operation when their respective events occur and cleared upon Register OxOF determines which bits in the status register reading the register Device status can be determined trigger IRQ to pull low Table 36 Status and Interrupt Registers REGISTER BIT NAME DESCRIPTION Full Scale 0 All digital signals are less than full scale 1 The DAC or ADC signal path has reached or exceeded full scale This typically indicates clipping 7 CLD Volume Slew Complete SLD reports that any of the programmable gain arrays or volume controllers has com pleted slewing from a previous setting to a new programmed setting If multiple gain arrays or volume controllers are changed at the same time the SLD flag is set after the 6 SLD last volume slew completes SLD also reports when the digital audio interface soft start or soft stop process has completed MCLK is required for proper SLD operation 0 No volume slewing sequences have completed since the status register was last 0x00 read Read Only 1 Volume slewing complete Digital Audio Interface Unlocked 5 ULK 0 B
37. Right Headphone Enable 0 Disabled 1 Enabled Left Speaker Enable 0 Disabled 1 Enabled SPREN Right Speaker Enable 0 Disabled 1 Enabled RECLEN Receiver Left Line Output Enable Use this bit to enable the differential receiver output or left line output 0 Disabled 1 Enabled RECREN Right Line Output Enable Use this bit to enable the right line output 0 Disabled 1 Enabled DALEN Left DAC Enable 0 Disabled 1 Enabled DAREN Right DAC Enable 0 Disabled 1 Enabled Ox4E BGEN Bandgap Enable Must be enabled for proper operation of the 2 5V regulator and as sociated circuitry 0 Disabled 1 Enabled SPREGEN 2 5V Regulator Enable SPREGEN enables a 2 5V internal regulator required for the ADC speaker and receiver line out amplifier The 2 5V regulator is powered by SP KLVDD 0 Disabled 1 Enabled VCMEN Common Mode Voltage Resistor String Enable VCMEN enables the common mode voltage for the input and output amplifiers in the codec 0 Disabled 1 Enabled BIASEN Chip Bias Enable BIASEN needs to be set for the codec amplifiers to be enabled 0 Disabled 1 2 Enabled JDWK See the Jack Detection section Maxim Integrated Products 68 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Microphone Inputs The device includes three di
38. 0 OxOB 28 Ox1B 1 OxOC 25 Ox1C 41 5 22 Ox1D 2 19 Ox1E 42 5 OxOF 17 Ox1F 3 MAALM Maxim Integrated Products 111 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Output Bypass Switches The IC s includes two output bypass switches that solve common applications problems When a single trans ducer is used for the loudspeaker and receiver the need exists for two amplifiers to power the same transducer Bypass switches connect the IC s receiver amplifier output to the speaker amplifier s output allowing either amplifier to power the same transducer In systems where an external receiver amplifier is used route its output to the left speaker through RECP RXINP and RECN RXINN bypassing the Class D amplifier In systems where an external amplifier drives both the receiver and the IC s line input one of the differential signals can be discon nected from the receiver when not needed by passing it through the analog switch that connects RECP RXINP to RECN RXINN RECP RXINP 048 EXTERNAL RECEIVER RECN RXINN RECBYP RECLEN RECREN SPKBYP OPTIONAL 100 RESISTORS IMPROVE DISTORTION THROUGH THE ANALOG SWITCH Y gt 008 RECBYP SPKBYP RECP RXINP RECN RXINN RECBYP SPKBYP SPKLP e SPKLN Ya
39. 2 2 15 8 0 64 0 96 R W 93 c2 2 7 0 Ox65 0x97 RW 93 K 3 15 8 0x66 0x98 RW 93 K 3 7 0 0 67 0 99 RW 93 K1_3 15 8 0 68 0 9 R w 93 K1_3 7 0 0 69 0 9 RW 93 EQ Band 3 K2 3 15 8 Ox6A Ox9C 93 DAI DAI2 K2_3 7 0 Ox6B Ox9D _Oxxx Rw 93 c1 3 15 8 Ox6C OX9E RW 93 c1 3 7 0 Ox6D Ox9F 93 2 3 15 8 Ox6E OXAE 93 c2 3 7 0 Ox6F OxA1 93 K_4 15 8 Ox70 0xA2 93 K_4 7 0 0 71 0 IRW 93 K1_4 15 8 72 4 IRW 93 K1_4 7 0 0 73 0 5 IRW 93 EQ Band 4 K2_4 15 8 0 74 0 6 IRW 93 DAI1 DAI2 K2_4 7 0 0 75 0 7 93 c1 4 15 8 Ox76 0xA8 IRW 93 1 A 7 0 0 77 0 9 IRW 93 2 4 15 8 0 78 R W 93 c2_4 7 0 0 79 93 Maxim Integrated Products 65 Table 1 Register Map continued MAX98089 Low Power Stereo Audio Codec with FlexSound Technology REGISTER B7 B6 B5 B4 B3 B2 B1 ADDRESS DEFAULT R W PAGE K 5 15 8 RW 93 K 5 7 0 Ox7B OxAD RW 93 K1_5 15 8 Ox7C OXAE 93 K1_5 7 0 Ox7D OxAF RW 93 Band 5 K2_5 15 8 Ox7E OxBO
40. An evaluation kit EV kit is available to provide an exam ple layout for the IC The EV kit allows quick setup of the IC and includes easy to use software allowing all internal registers to be controlled WLP Applications Information For the latest application details on WLP construction dimensions tape carrier information PCB techniques bump pad layout and recommended reflow temperature profile as well as the latest information on reliability test ing results refer to the Application Note 1891 Wafer Level Packaging WLP and Its Applications Figure 44 shows the dimensions of the WLP balls used on the MAX98089EWY MAXIM 0 21mm Figure 44 MAX98089EWY WLP Ball Dimensions Ordering Information PART TEMP RANGE PIN PACKAGE MAX98089EWY T 40 C to 85 C 68 WLP MAX98089ETN T 40 C to 85 C 56 TQFN EP T Tape and reel Denotes lead Pb free ROHS compliant package EP Exposed pad Maxim Integrated Products 127 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Package Information For the latest package outline information and land patterns footprints go to www maxim ic com packages Note that a or in the package code indicates RoHS status only Package drawings may show a different suffix character but the drawing pertains to the package regardless of RoHS status PACKAGE TYPE PACKAGE CODE OUTLINE NO LAND PATTER
41. REGISTER 0x01 BIT NAME NG DESCRIPTION Noise Gate Attenuation Reports the current noise gate attenuation 000 001 188 010 288 011 to 598 100 to 788 101 8dB to 9dB 110 1088 to 11dB 111 1298 AGC AGC Gain Reports the current AGC gain setting VALUE GAIN dB 0x00 20 0x01 1 VALUE OxOB 0 0 8 GAIN dB 0 02 7 OxOE 6 0 04 OxOF 5 ii 0x03 1 0x05 0 10 4 1 0 06 0 11 3 i 0x07 0x12 2 1 0 08 0x13 1 0 09 0x14 to Ox1F 0 1 n Ox3F AGCSRC AGC Noise Gate Signal Source Determines which ADC channel the AGC and noise gates analyze Gain is adjusted on both channels regardless of the AGCSRC setting 0 ADC output 1 Maximum of either the left or right ADC output AGCRLS AGC Release Time Defined as the duration from start to finish of gain 12 000 78ms 001 156ms 010 312ms 011 625ms 100 1 25s 101 2 55 110 55 111 105 increase in the region shown in Figure MAALM Maxim Integrated Products 74 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 6 Record Path Signal Processing Registers continued
42. S 30 25 40 AVspk 48dB 5 AVspk_voL 808 AVspk voL 8dB 40 PACKAGE 40 WLPPACKAGE 600 az 50 50 60 f 6000Hz 60 70 70 go L f 100 f 1000Hz 80 90 90 0 01 02 03 04 05 06 07 08 0 05 10 15 20 25 30 35 0 05 10 15 20 25 30 35 OUTPUT POWER W OUTPUT POWER W OUTPUT POWER W Maxim Integrated Products 39 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2yF CREG CC1N C1P CHPVDD AVMICPRE_ 209 AVDACGAIN AVADCLVL OGB AVADCGAIN AVPGAIN_ AVHP_ AVREC AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER DAC TO SPEAKER TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER DAC TO SPEAKER TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT PO
43. The capacitor value varies based on the ferrite bead chosen and the actual speaker lead length Select a capacitor less than 1nF based on EMI performance Input Capacitor An input capacitor CIN in conjunction with the input impedance of the IC line inputs forms a highpass filter that removes the DC bias from an incoming analog signal The AC coupling capacitor allows the amplifier to automatically bias the signal to an optimum DC level Assuming zero source impedance the 3dB point of the highpass filter is given by 4 Choose CIN so that f 3dB is well below the lowest fre quency of interest For best audio quality use capacitors whose dielectrics have low voltage coefficients such as tantalum or aluminum electrolytic Capacitors with high voltage coefficients such as ceramics may result in increased distortion at low frequencies Charge Pump Capacitor Selection Use capacitors with an ESR less than 100mQ for optimum performance Low ESR ceramic capacitors minimize the output resistance of the charge pump Most surface mount ceramic capacitors satisfy the ESR requirement For best performance over the extended temperature range select capacitors with an X7R dielectric Table 39 Registers That Are Sensitive to Changes During Operation REGISTER DESCRIPTION 0x10 to 0x13 0x19 to Ox1B Clock Control Registers 0x14 to 0x17 Ox1C to Ox1F Digital Audio Interface Configuration
44. 0x3 0 09 OxB 0 72 0 4 0 11 OxC 1 00 0 5 0 13 OxD 1 43 0x44 4 0x6 0 18 OxE 1 57 0x7 0 22 1 80 Power Limiter Weighting Factor 2 Determines the balance between time constant 1 and 2 to match the dominance of each time constant in the loudspeaker VALUE T1 T2 000 50 50 1 001 62 5 37 5 010 75 25 011 87 5 12 5 100 100 0 101 12 5 87 5 110 25 75 114 37 5 62 5 MIAXKLAVI Maxim Integrated Products 105 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 25 Power Limiter Registers continued REGISTER BIT NAME DESCRIPTION 7 Power Limiter Time Constant 2 Select a value that matches the thermal time constant of the loudspeaker s magnet VALUE TIME ae VALUE TIME oa 9 0x0 Disabled 0x8 3 75 PWRT2 Ox1 0 50 Ox9 5 00 0x2 0 67 OxA 6 66 5 0x3 0 89 OxB 8 88 Ox4 1 19 OxC Reserved 0x5 1 58 OxD Reserved 4 Ox6 2 11 OxE Reserved 0x45 0x7 2 81 Reserved 3 Power Limiter Time Constant 1 Select a value that matches the thermal time constant of the loudspeaker s voice coil VALUE TIME CONSTANT VALUE TIME CONSTANT 5 5 5 0x0 Disabled 0x8 3 75 PWRT4 Ox1 0 50 Ox9 5 00 0x2 0 67 OxA 6 66 1 0x3 0 89 OxB 8 88 Ox4 1 19 OxC Reserved 0x5 1 58 OxD Reserved 0 Ox6 2 11 Reserved Ox7 2 81 OxF Reserved Distortion Limiter The IC s distortion limiter ensures that the speaker amplifier s output does
45. 12288MHz E MLK 12 288MHz E MCLK 12 288 E 5 77 LRCLK 4kHz 5 5 20 NI MODE 5 20 MODE 5 E n Rup 160 Rup 160 OWER MODE _ 30 amp 99 _ 308 amp 30 160 amp 40 5 WLP PACKAGE 5 308 40 PACKAGE 5 50 a 6000Hz 50 60 60 amp E 60 f 1000H 70 70 6000Hz 80 80 70 90 90 80 10 100 90 0 0 01 0 02 0 03 0 04 0 05 0 06 0 07 0 0 01 002 003 0 04 005 006 007 0 0 01 002 003 004 005 006 0 07 OUTPUT POWER W OUTPUT POWER W OUTPUT POWER W Maxim Integrated Products 46 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2yF CREG CC1N C1P CHPVDD AVMICPRE_ 209 AVDACGAIN AVADCLVL OGB AVADCGAIN AVPGAIN_ AVHP_ AVREC AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted
46. 3127 4380 49BA 16 9344 1000 116A 1738 2000 2204 2 71 4000 4549 2E71 4000 4549 18 432 OAAB OEB3 1000 1555 1D66 2000 2AAB 3ACD 4000 2AAB 3ACD 4000 20 0905 1349 1818 107 2752 3631 2752 3631 Note Values in bold are exact integers that provide maximum full scale performance Sample Rate Converter audio can be output through DAI1 to either SDOUTS1 or The sample rate conversion circuit allows for both sam SDOUTS2 The sample rate converter can be enabled on ple rate conversion and mixing of asynchronous audio a per channel basis allowing for one channel of DAI to data from SDIN1 and DAI2 SDIN2 The resulting output microphone data while the other channel is outputting sample rate converted data SAMPLE RATE CONVERTER Figure 18 Sample Rate Converter Maxim Integrated Products 88 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 13 Sample Rate Converter Register REGISTER BIT NAME DESCRIPTION Sample Rate Mix Mode Sets mixing configuration applied to the sample rate converted channel s 4 SRMIX_MODE 0 DAI 1 DAI DAI2 2 Sample Rate Mix Enable If enabled mixes data on DAI1 and DAI2 If cleared SCR 3 SRMIX_ENL 21 data source is DAI2 only 0
47. 48kHz MAS 1 TA 25 C unless otherwise noted GAIN vs FREQUENCY POWER SUPPLY REJECTION RATIO LINE TO HEADPHONE vs FREQUENCY LINE TO HEADPHONE PPLE 200mVp MAX98089 10 122 MAX98089 10 123 ED GAIN dB PSRR dB ORMALIZ 10 100 1 10k 100k 10 00 1 10k 100k FREQUENCY Hz FREQUENCY Hz CROSSTALK vs FREQUENCY LINE TO HEADPHONE Rup 320 5 Cin 8 CROSSTALK dB TQFN RIGHT TO LEFT TQFN LEFT TO RIGH 10 0 1k 10k 100k Maxim Integrated Products 53 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2 CMICBIAS CREG CC1N C1P CHPvss AVMICPRE_ 420848 AVMICPGA_ AVDACATTN
48. AMPLITUDE dBFS 0 5 10 15 20 FREQUENCY kHz FFT 60dBFS MIC TO ADC MCLK 12 288MHz 20 LRCLK 48kHz NI MODE 40 AVMICPRE_ 048 98089 toc15 AMPLITUDE dBFS 100 120 140 0 5 10 15 20 FREQUENCY kHz MAALM FFT OdBFS MIC TO ADC MCLK 12 288MH LRCLK 48 MAX98089 10614 AVM 5 AMPLITUDE dBFS 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY kHz FFT OdBFS MIC TO ADC MCLK 12 288MHz LRCLK 96kHz ODE 98089 toc16 AVM AMPLITUDE dBFS 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY kHz Maxim Integrated Products 30 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2yF CREG CC1N C1P CHPvss AVMICPRE_ 42088 AVMICPGA_ AVDACATTN AVDACGAIN AVADCLVL AVADCGAIN 088 AVPGAIN_ AVHP_ OdB AVsPK_
49. CHPVDD CHPVSS 1HF AVMICPRE_ 2088 AVMICPGA_ AVDACATTN OdB AVDACGAIN OdB AVADCLVL AVADCGAIN OdB AVPGAIN_ AVHP_ AVspK_ OdB MCLK 12 288MHz LRCLK 48kHz MAS TA TMIN to TMAx unless otherwise noted Typical values are at 25 C Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RECEIVER BYPASS SWITCH On Resistance RON IRECP 100mA RECBYP 1 VRECN OV VSPKL 5 VDD Total Harmonic Distortion THD N VIN 2VP P VCM VSPKLVDD 2 ZSPK 80 60 2 Noise 68uH f 1kHz RECBYP 1 Rs 00 VIN 2 VCM VSPKLVDD 2 ZSPK 80 Off Isolation 68uH f 1kHz 84 dB VRECP VSPKLVDD VRECN Off Leakage Current 15 15 A 5 VSPKLVDD OV JACK DETECTION 092x 095x 098x MICBIAS enabled VMICBIAS VMICBIAS VMICBIAS JACKSNS High Threshold VTH1 V MICBIAS disabled 092 095 0 98x VSPKLVDD VSPKLVDD VSPKLVDD 0 06 010 0 17 VMICBIAS VMICBIAS VMICBIAS MICBIAS enabled JACKSNS Low Threshold VTH2 V MICBIAS disabled 0 06x 0 0 0 17x VSPKLVDD VSPKLVDD VSPKLVDD JACKSNS Sense Voltage MICBIAS disabled JDWK 1 3 65 3 7 JACKSNS Sense Resistance RsENSE MICBIAS disabled JDWK 0 1 6 2 4 2 9 JACKSNS Weak Pullup Current IWPU MICBIAS disabled JDWK 1 2 5 9 5 JACKSNS Deglitch Period tGLITCH en e S ms JDEB 1
50. D SPKRVI MAX98089 0609 PSRR dB VniPPLE 200mVp p 10 100 1k 10k 100k FREQUENCY Hz FFT OdBFS MIC TO ADC MCLK 13MHz LRCLK 44 1kHz PLL MODE 098 Cy 1uF 98089 toc12 AMPLITUDE dBFS 0 500 1k 15k 2 FREQUE 25k 3k 35k 4k CY Hz AMPLITUDE dBFS FREQUENCY kHz Maxim Integrated Products 29 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2yF CREG CC1N C1P CHPvss AVMICPRE_ 42088 AVMICPGA_ AVDACATTN AVDACGAIN AVADCLVL AVADCGAIN 088 AVPGAIN_ AVHP_ OdB AVREC AVsPK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 Ta 25 C unless otherwise noted FFT 60dBFS MIC TO ADC MCLK 13MHz 20 LRCLK 44 1kHz PLL MODE 40 048 MAX98089 013
51. INB1 1 INA2 INADIFF 0 or INA2 INA1 INADIFF 1 XXxxxx1lx INA1 Right Headphone Mixer Path Select 0x25 MIXHPL 0x26 MIXHPR 0 101 0 41 41 e 5 0 Directly connect to the right DAC bypass right headphone output mixer SEL 1 Right headphone output mixer Left Headphone Mixer Path Select 4 MIXERE RATEI 0 Directly connect to the left DAC bypass left headphone output mixer SEL 1 Left headphone output mixer Right Headphone Mixer Gain Select 3 0x27 00 098 GAIN 01 6dB 2 10 9dB 11 12dB Left Headphone Mixer Gain Select MIXHPL e GAIN 01 6dB 0 T 10 9dB 11 12dB MAKII Maxim Integrated Products 110 Headphone Output Volume Table 28 Headphone Output Level Register REGISTER BIT 39 HPLM HPRM HPVOLL HPVOLR MAX98089 Low Power Stereo Audio Codec with FlexSound Technology DESCRIPTION Headphone Output Mute 0 Disabled 1 Enabled Left Right Headphone Output Volume Level VALUE VOLUME dB VALUE VOLUME dB 0x00 67 0x10 15 0x01 63 0x11 13 0x02 59 0x12 11 0x03 55 0x13 9 0x04 51 0x14 7 0x05 47 0x15 5 0x06 43 0x16 4 0x07 40 0 17 3 0 08 37 0 18 2 0x09 34 0x19 1 31
52. In systems where an external amplifier drives both the receiver and the MAX98089 s line input one of the dif ferential signals can be disconnected from the receiver when not needed by passing it through the analog switch that connects RECP RXINP to RECN RXINN The stereo Class D amplifier provides efficient amplifica tion for two speakers The amplifier includes active emis sions limiting to minimize the radiated emissions EMI traditionally associated with Class D In most systems no output filtering is required to meet standard EMI limits To optimize speaker sound quality the IC includes an excursion limiter a distortion limiter and a power limiter The excursion limiter is a dynamic highpass filter with variable corner frequency that increases in response to high signal levels Low frequency energy typically causes more distortion than useful sound at high sig nal levels so attenuating low frequencies allows the speaker to play louder without distortion or damage At lower signal levels the filter corner frequency reduces to pass more low frequency energy when the speaker can handle it The distortion limiter reduces the volume when the output signal exceeds a preset distortion level This ensures that regardless of input signal and battery voltage excessive distortion is never heard by the user The power limiter monitors the continuous power into the loudspeaker and lowers the signal level if the speaker is at risk of
53. LRCLK 16 CYCLES 16 CYCLES 16 CYCLES 16 CYCLE a gt gt BCLK Wy vvv venen sow 00008861 98588508 Figure 17 TDM Mode Data Format Examples Maxim Integrated Products 84 Th MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Clock Control e digital signal paths in the IC require a master clock MCLK between 10MHz and 60MHz to function The MAX98089 requires an internal clock between 10MHz an d 20MHz A prescaler divides MCLK by 1 2 or 4 to create the internal clock PCLK PCLK is used to clock all Th portions of the IC e MAX98089 includes two digital audio signal paths both capable of supporting any sample rate from 8kHz to dif of su 96kHz Each path is independently configured to allow ferent sample rates To accommodate a wide range system architectures four main clocking modes are pported PLL Mode When operating in slave mode enable the PLL to lock onto any LRCLK input This mode requires the least configuration but provides the lowest per formance Use this mode to simplify initial setup or when normal mode and exact integer mode cannot be used Table 11 Clock Control Registers Normal Mode This mode uses a 15 bit
54. Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2 CMICBIAS CREG CC1N C1P CHPVDD CHPvss AVMICPRE_ 20dB AVMICPGA_ AVDACATTN AVDACGAIN OdB AVADCLVL AVADCGAIN OdB AVPGAIN_ AVHP_ AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted SOFTWARE TURN ON OFF RESPONSE SOFTWARE TURN ON OFF RESPONSE DAC TO HEADPHONE VSEN 0 DAC TO HEADPHONE VSEN 1 B nnd 1 1 1V div qv div el m 4 OUTPUT 1 OUTPUT 1Vidiv 1 10ms div 10ms div FFT OdBFS DAC TO HEADPHONE FFT 60dBFS DAC TO HEADPHONE 20 20 z MCLK 13MHz MCLK 13MHz 8 LRCLK 8kHz 3 0 LRCLK 8kHz 8 FREQ MODE 2 FREQ MODE 2 2 320 20 Rup 320 5 40 amp 40 p 6 a a 4 100 100 120 120 14 140 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY kHz FREQUENCY kHz Maxim Integrated Products 50 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VPVDD VD
55. SPEAKER AMPLIFIER BYPASS USING EXTERNAL RECEIVER AMPLIFIER Figure 32 Output Bypass Switch Block Diagrams Table 29 Output Bypass Switches Register SPEAKER AMPLIFIER BYPASS USING THE INTERNAL RECEIVER AMPLIFIER CONTROLLING AN EXTERNAL RECEIVE AMPLIFIER AND SPEAKER REGISTER BIT NAME DESCRIPTION 7 INABYP 4 MIC2BYP See the Microphone Inputs section 1 RECBYP 0 Disabled Ox4A 1 Enabled RXINP to RXINN Bypass Switch Shorts RXINP to RXINN allowing a signal to pass through the ICs Disable the receiver amplifier when RECBYP 1 9 SPKBYP 1 0 Disabled 1 Enabled RXIN to SPKL Bypass Switch Shorts RXINP RXINN to SPKLP SPKLN allowing either the internal or an external receiver amplifier to power the left speaker Disable the left speaker amplifier when MAXIM Maxim Integrated Products 112 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Click and Pop Reduction The IC includes extensive click and pop reduction cir cuitry The circuitry minimizes clicks and pops at turn on turn off and during volume changes Zero crossing detection is implemented on all analog PGAs and volume controls to prevent large glitches when volume changes are made Instead of making a volume change immediately the change is made when the audio signal crosses the midpoint If no zero crossing occurs within the timeout window the change is forced Volume s
56. SRC mix disable SRMPCENR 1 SRC mix enable 1 an Rate Converter Enable Select if the SRC is enabled on a per channel 0 SRC 0 Sample rate converter disable 1 Sample rate converter enable Passband Filtering Use music mode when processing high fidelity audio Each digital signal path in the IC includes options for content The music FIR filters reduce power consump defining the path bandwidth Figure 19 The playback tion and are linear phase to maintain stereo imaging and record paths connected to DAI1 support both voice An optional DC blocking filter is available to eliminate and music filtering while the playback path connected to unwanted DC offset DAI2 supports music filtering only In music mode a second set of FIR filters are available to The voice IIR filters provide greater than 70dB stopband support sample rates greater than 5OkHz The filters can attenuation at frequencies above fs 2 to reduce aliasing be independently selected for and DAI2 and sup Three selectable highpass filters eliminate unwanted low port both the playback and record audio paths frequency signals AUDIO VOICE FILTERS AUDIO FILTERS DCB2 AUDIO VOICE FILTERS MODE DVFLT Figure 19 Digital Passband Filtering Block Diagram Maxim Integrated Products 89 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 14 Passband Fil
57. ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL or LOUTR to SPKLGND CREF 2 21 CMICBIAS CREG CC1N C1P CHPVDD CHPVSS AVMICPRE_ 208B AVMICPGA_ AVDACATTN AVDACGAIN AVADCLVL OGB AVADCGAIN AVPGAIN_ AVHP_ OdB AVREC AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted Line to Receiver TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER PLUS NOISE vs FREQUENCY LINE TO RECEIVER LINE TO RECEIVER 320 EC 320 E 4 AVpec 8dB 5 REC 808 E On tur Cin 3 gm ms 5 24 2 E xl 30 f 1000Hz F LN 0 002 004 0 008 0 10 OUTPUT POWER W FREQUENCY GAIN vs FREQUENCY POWER SUPPLY REJECTION RATIO LINE TO RECEIVER vs FREQUENCY LINE TO RECEIVER 120 g E VRIPPLE 200 E 3 100 3
58. 200Hz 00 11 Programmable us ing biquad 600Hz 300 2 010 11 Programmable us ing biquad 800Hz 400 2 011 11 Programmable us ing biquad 1kHz 500Hz 100 11 ALC and Excursion Limiter Release Time Sets the release time for both the ALC and Excursion Limiter See the Automatic Level 6 Control section for ALC release times Excursion limiter release time is defined as the time required to slide from the high corner frequency to the low corner frequency VALUE EXCURSION LIMITER RELEASE TIME s 000 4 0x43 5 ALCRLS 091 E 010 1 011 0 5 100 0 25 4 101 0 25 110 Reserved 114 Reserved Excursion Limiter Threshold 3 Measured at the Class D speaker amplifier outputs Signals above the threshold use the upper corner frequency Signals below the threshold use the lower corner frequency VBAT must correctly reflect the voltage of SPKLVDD to achieve accurate thresh 2 olds 000 0 34Vp 0x42 DHPTH 001 0 71VP 1 010 1 30VpP 011 1 77Vp 100 2 33 101 3 25Vp 0 110 2 4 25Vp 111 2 4 95Vp MAXIM Maxim Integrated Products 104 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Power Limiter The IC s power limiter tracks the continuous power deliv ered to the loudspeaker and briefly mutes the speaker amplifier output if the speaker is at risk of sustaining permanent damage Loudspeakers are typically damaged when the voice coil overheats due to extended operation above the rated power During normal operation heat generat
59. 30 HPSNS configurations Maxim Integrated Products 108 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology MIXHPL_ PATH SEL PVOLL TO 67dB MIXHPR PATH SEL 3dB TO 67dB Figure 31 Headphone Amplifier Block Diagram MAKILA Maxim Integrated Products 109 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Headphone Output Mixers The headphone amplifier mixer accepts input from the stereo DAC the line inputs single ended or differential and the MIC inputs Configure the mixer to mix any com bination of the available sources When more than one signal is selected the mixer can be configured to attenu ate the signal by 6dB 9dB or 12dB The stereo DAC can bypass the headphone mixers and be connected directly to the headphone amplifiers to provide lower power consumption Table 27 Headphone Output Mixer Register REGISTER w DESCRIPTION Left Headphone Output Mixer 1 Right DAC x1xxxxxx MIC2 1 MIC1 XXX INB2 INBDIFF 0 or INB2 INB1 INADIFF 1 1 INB1 1 INA2 INADIFF 0 or INA2 INA1 INADIFF 1 1 INA1 1 Left DAC Right Headphone Output Mixer 1 Left DAC x1xxxxxx MIC2 1 MIC1 xxx1xxxx INB2 INBDIFF 0 or INB2 INB1 INBDIFF 1 1
60. 48kHz MAS 1 TA 25 C unless otherwise noted Analog Loopback TOTAL HARMONIC DISTORTION PLUS TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY NOISE vs FREQUENCY FFT OdBFS LINE TO ADC TO DAC TO HEADPHONE LINE TO ADC TO DAC TO HEADPHONE LINE TO ADC TO DAC TO HEADPHONE 0 0 20 5 10 CLK 13MHz 1 CLK 12 288MHz E MCLK 13MHz LROLK 44 1kHz 8 LRCLK 48kHz 8 LRCLK 44 1kHz 42 20 MODE 20 MODE RHP 320 RHP 320 2 Rup 320 8 30 F Cin 10pF 8 30 10 2 Cin e 40 40 4 5 50 4 5 4 60 Pour 0 02W E Pout 0 02W 8 70 7 Pour 0 01W 80 80 D Pour 0 01W 90 90 12 10 0 1 10k 100k 10 100 1k k Ok 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY Hz FREQUENCY Hz FREQUENCY kHz FFT 604 5 LINE ADC TO DAC FFT OdBFS LINE TO ADC TO DAC FFT 60dBFS LINE TO ADC TO DAC TO HEADPHONE TO HEADPHONE TO HEADPHONE 0 8 2 g 5 MCLK 13MHz 2 MCLK 12 288MHz MCLK 12 288 20 LRCLK 44 1kHz 42 LRCLK 48kHz 115 2 LRCLK
61. 70 Pout 0 02W 80 8 Pout 0 01 90 9 10 100 1k 10k 100k 10 100 k 0k 00k 100k FREQUENCY Hz FREQUENCY Hz MAAKLM Maxim Integrated Products 47 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2yF CREG CC1N C1P CHPVDD AVMICPRE_ 209 AVDACGAIN AVADCLVL OGB AVADCGAIN AVPGAIN_ AVHP_ OdB AVREC AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY DAC TO HEADPHONE vs FREQUENCY DAC TO HEADPHONE CLK 12 288M RCLK 48kHz CLK 12 288MHz LRCLK 48kHz 20 MODE Rup 160 30 43dB MAX98089 10 101 0 MAX98089 toc100 HD N RATIO dB THD N RATIO dB
62. 8kHz to 48 2 E 3 lt 4 5 LRCLK 48kHz 6 0 200 400 600 800 1000 FREQUENCY Hz 110 111 N A Reserved MAXIM Maxim Integrated Products 91 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Playback Path Signal Processing The IC playback signal path includes automatic level control ALC and a 5 band parametric equalizer EQ Figure 20 The DAI1 and DAI2 playback paths include separate ALCs controlled by a single set of registers Two completely separate parametric EQs are included for the DAI1 and DAI2 playback paths Automatic Level Control The automatic level control ALC circuit ensures maxi mum signal amplitude without producing audible clip ping This is accomplished by a variable gain stage that works on a sample by sample basis to increase the gain up to 12dB A look ahead circuit determines if the next sample exceeds full scale and reduces the gain so that the sample is exactly full scale A programmable low signal threshold determines the minimum signal amplitude that is amplified Select a threshold that prevents the amplification of background noise When the signal level drops below the low signal threshold the ALC reduces the gain to OdB until the sig nal increases above the threshold Figure 21 shows an example of ALC input vs output Curves MULTI BAI DVEQ1 DVEQ2 BTO B TO 15dB Figure 20 Playback Path Signal Proces
63. 93 Maxim Integrated Products 27 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL or LOUTR to SPKLGND CREF 2 2 CMICBIAS CREG CC1N C1P CHPVDD 95 AVMICPRE_ 208B AVMICPGA_ AVDACATTN AVDACGAIN AVADCLVL OGB AVADCGAIN AVPGAIN_ AVHP_ OdB AVREC AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted Microphone to ADC
64. Audio Left Right Clock Input Output LRCLKS1 is the audio sample rate D4 10 LRCLKS1 clock and determines whether S1 audio data is routed to the left or right channel In TDM mode LRCLKS1 is a frame sync pulse LRCLKS1 is an input when the IC is in Slave mode and an output when in master mode D8 36 INB2 Single Ended Line Input B2 Also positive differential line input B D9 35 HPR Right Channel Headphone Output MAXIM Maxim Integrated Products 57 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Bump Pin Description continued BUMP PIN WLP FUNCTION 1 6 DVDDS1 51 Digital Audio Interface Power Supply Input Bypass to with ca pacitor 2 5 MCLK Master Clock Input Acceptable input frequency range is 10MHz to 60MHz EA 9 SDINS1 1 Digital Audio Serial Data DAC Input The input output voltage is referenced to DVDDS1 Hardware Interrupt Output IRQ can be programmed to pull low when bits in E5 56 TRO status register 0x00 change state Read status register 0x00 to clear IRQ once set Repeat faults have no effect on IRQ until it is cleared by reading the 12C status register 0x00 Connect a 10kQ pullup resistor to DVDD for full output swing 6 45 JACKSNS Jack Sense Detects the insertion and removal of a jack In typical applications connect JACKSNS to the MIC pole of the jack See the Jack Dete
65. CONDITION REPEATED START CONDITION STOP START CONDITION CONDITION Figure 5 Interface Timing Diagram Note 1 The IC is 100 production tested at TA 25 C Specifications over temperature limits are guaranteed by design Note 2 Analog supply current lAvpp IHPVDD Speaker supply current ISPKLVDD IsPKRVDD Digital supply current IDvDD IDVDDS1 IDVDDS2 Note 3 Clocking all zeros into the DAC Note 4 Dynamic range measured using EIAJ method 60dBFS 1kHz output signal A weighted and normalized to OdBFS f 20Hz to 20kHz Note 5 Gain measured relative to the OdB setting Note 6 The filter specification is accurate only for synchronous clocking modes where NI is a multiple of 0 1000 Note 7 OdBFS for DAC input for INA INB inputs Note 8 LRCLK may be any rate in the indicated range Asynchronous or noninteger MCLK LRCLK ratios may exhibit some full scale performance degradation compared to synchronous integer related MCLK LRCLK ratios Note 9 In master mode operation the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate Note 10 CB is in pF Power Consumption VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V MAS 0 MODE IAVDD IPVDD IDVDD puse POWER DYNAMIC mA mA mA mA mA mW RANGE dB Playback to Headphone Only DAC Playback 48kHz Stereo HP DAC gt HP low power modei 24bit m
66. Figure 4 Digital Microphone Timing Diagram 12C TIMING CHARACTERISTICS DS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V TA 25 C unless otherwise noted VAVDD VPVDD VDVDD VDVD Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Serial Clook Frequenoy Set by SCL pulse width low and 0 400 kHz Bus Free Time Between STOP and t 13 START Conditions BUF H Hold Time Repeated START Condition 0 6 us SCL Pulse Width Low tLOW 1 3 Us SCL Pulse Width High tHIGH 0 6 us Setup Time for a Repeated START Condition SU STA 0 6 us Data Hold Time tHD DAT RPU 4750 CB 100pF 400pF 0 900 ns Data Setup Time tSU DAT 100 ns SDA and SCL Receiving Rise Time iR Note 10 d 300 ns SDA and SCL Receiving Fall Time Note 10 300 ns SDA Transmitting Fall Time tF RPU 4750 100pF 400pF Note 10 250 ns Setup Time for STOP Condition tSU STO 0 6 us Bus Capacitance Guaranteed by SDA transmitting fall time 400 pF Pulse Width of Suppressed Spike tsp 0 50 ns MAALM Maxim Integrated Products 24 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology 12C TIMING CHARACTERISTICS continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V TA 25 C unless otherwise noted Note 1 tH pat tUSTAM MEP HD STA tsp tHD STA START
67. POWER W 10 0 020 0 030 0 040 0 045 n 0 Nn Cc c c c 0 0 01 0 02 0 03 OUTPUT POWER W 0 0 TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER DAC TO HEADPHONE 10 MCLK 12 288MHz E LRCLK 48kHz 20 ODE 320 HP 308 PACKAGE 98089 toc88 30 Az a D e 1 e e 100 0 0 010 0 020 0 030 0 040 0 050 0 005 0 015 0 025 0 035 0 045 OUTPUT POWER W Maxim Integrated Products 45 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2 CMICBIAS CREG CC1N C1P CHPVDD CHPvss AVMICPRE_ 20dB AVMICPGA_ AVDACATTN AVDACGAIN OdB AVADCLVL AVADCGAIN AVPGAIN_ AVHP_ OdB AVREC AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted
68. RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out loads RLOUT connected from LOUTL or LOUTR to SPKLGND RLOAD RHP ee ee ZSPK ee CREF 2 2 CMICBIAS CREG CC1N C1P CHPVDD 1HF AVMICPRE_ 2088 AVMICPGA_ AVDACGAIN OdB AVADCLVL AVADCGAIN OdB AVPGAIN_ OdB AVHP_ AVspK_ OdB MCLK 12 288MHz LRCLK 48kHz MAS TA TMIN to Tmax unless otherwise noted Typical values are at 25 C Note 1 PARAMETER SYMBOL CONDITIONS MIN MAX UNITS STEREO AUDIO MODE FIR LOWPASS FILTER MODE1 1 DHF1 DHF2 1 for LRCLK gt 50kHz Ripple limit cutoff 0 24 x fs Passband Cutoff f H 3aB cutoff 0 31 x fs Passband Ripple f lt 0 1 0 1 dB Stopband Cutoff 0 477 xfs Hz Stopband Attenuation Note 6 f lt SLP 60 dB STEREO AUDIO MODE DC BLOCKING HIGHPASS FILTER Passband Cutoff 0 000104 from Peak fpHPPB DVFLT 000 DAI1 DCB2 1 DAI2 xis Hz DC Attenuation DCATTEN DVFLT 000 DAI 1 DCB2 1 DAI2 90 dB AUTOMATIC LEVEL CONTROL Dual Band Lowpass Corner ALCMB 1 5 kHz Frequency Dual Band Highpass Corner ALCMB 1 5 kHz Frequency Gain Range 0 12 dB Low Signal Threshold ALCTH 111 to 001 48 12 dBFS ALCRLS 101 0 25
69. VPVDD VDVDDS1 2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL or LOUTR to SPKLGND CREF 2 2 CMICBIAS CREG CC1N C1P CHPVDD CHPvss AVMICPRE_ 20d0B AVMICPGA_ AVDACATTN AVDACGAIN AVADCLVL OGB AVADCGAIN 088 AVPGAIN_ AVHP_ AVsPK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 Ta 25 C unless otherwise noted GAIN vs FREQUENCY MIC TO ADC NORMALIZED GAIN dB FREQUENCY Hz MCLK 13MHz LRCLK 8kHz FREQ MODE _ 098 98089 toc07 10k 98089 1010 COMMON MODE REJECTION RATIO vs FREQUENCY MIC TO ADC 2048 CMRR dB AMPLITUDE dBFS FREQUENCY kHz MAALM FREQUE FFT 60dBFS MIC TO ADC MCLK 13MHz LRC FRI AVMICP LK 8kHz EQ MODE 098 98089 10 08 Ok 98089 toc11 POWER SUPPLY REJECTION RATIO vs FREQUENCY MIC TO ADC
70. be issued after any number of read data bytes If a STOP condition is issued followed by another read operation the first data byte to be read is from register OxOO The adaress pointer can be preset to a specific register before a read command is issued The master presets the address pointer by first sending the IC s slave address with the R W bit set to O followed by the register address A REPEATED START condition is then sent followed by the slave address with the R W bit set to 1 The IC then trans mits the contents of the specified register The address pointer autoincrements after transmitting the first byte The master acknowledges receipt of each read byte during the acknowledge clock pulse The master must acknowledge all correctly received bytes except the last byte The final byte must be followed by a not acknowl edge from the master and then a STOP condition Figure 38 illustrates the frame format for reading one byte from the IC Figure 39 illustrates the frame format for reading multiple bytes from the ICs ACKNOWLEDGE FROM MAX98089 3 SLAVE ADDRESS 0 A REGISTER ADDRESS A 3r SAVEADDRESS ___1 DATA BYTE L 1 1 1 1 L 1 1 m3 Figure 38 Reading One Byte of Data from the ICs ACKNOWLEDGE FROM MAX98089 ACKNOWLEDGE FROM MAX98089 4 4 REPEATED START 4 1 BYTE ENT INTERNAL REGISTER ADDRESS ACKNOWLEDGE FROM MAX98089 SLAVE ADDRESS 0
71. dem ae battle Rosen den cel a 123 RE SusceptibillBy rues m obe EE S ei deed Reda qe 123 Startup Shutdowrn SEQuenGING y RUE Ed quoc RO PUN a pi doe OS T ER deoa e dr ERR Ed 123 Component SElECION sa Bawa ue rA ka RR Y E OR eR SER AUPA Ra race dor gon 124 Optional Femte Bead Filter 2 ie et Ive be PRUNUS pe ES MEE 124 RETO MT IT 124 Charge Pump Capacitor Selection s 124 Charg Pump Flying Capacitor RE ab od har Rab ed ra o aes dea 125 Charge Pump Holding Capacitors imss o cakar teei m s 125 deb er RERUMS HR REST oe bie Ged es hoes 125 Recommended PCB ROUNO x s Creda iat ee eee Gi Re Pe es Rod bee Sea 126 Supply Bypassing Layout and Grounding rier 126 WLP Applications Information 0 0 00 00 RR RR e s 127 Ordering IMOrmatioi e acte Grads ode hk HEURE an elu eg de ors Ne notes 127 Package ___ ______ __ _____________ _____ 128 REVISION cata dieses a tine 131 Maxim Integrated Products 4 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Functional Diagram
72. eee 38 to SPEAKS trade Madi bec hie MMe che Molde 39 gonad eee ger PAPA eRe err pacem Pau Bee RSS 44 DAG to e p NE o Y qe SIS 45 headphone M RE ECRIRE TET T T TT UP 52 Speaker Bypass SWITCH eg ee eet oe debba Pa eae bese ed is 54 P v 55 Pin DescriptloDi 4004 57 Detailed 60 12 Slave Address iliis a a a see 61 __________ _______ _ ___ __ 61 dn o S ecu DAR Oe we Goenka FS Eo 67 Microphone 5 228 69 ake 1 AVLAZCL VI Maxim Integrated Products 2 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology TABLE OF CONTENTS continued ADG Input MIXERS x x ux dr coh Atcha dard Ra Sen SA 72 Record Path Signal Processing oesi 0 eee 73 Microphone AGC os os eed se XT Pee Se ee ee Ee eee ES 73 Noise Gales bes en rate a
73. loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out loads RLOUT connected from LOUTL or LOUTR to SPKLGND RLOAD RHP ee ee ZSPK ee CREF 2 2 CMICBIAS CREG CC1N C1P CHPVDD CHPVSS 1HF AVMICPRE_ 2088 AVMICPGA_ AVDACGAIN OdB AVADCLVL AVADCGAIN OdB AVPGAIN_ OdB AVHP_ AVspK_ OdB MCLK 12 288MHz LRCLK 48kHz MAS 0 TA TMIN to Tmax unless otherwise noted Typical values are at 25 C Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP UNITS 8 to 6dB 0 5 to 0dB 1 Volume Control Step Size OGB to 14dB 2 dB 4 to 38dB 3 3848 to 64dB 4 Mute Attenuation f 1kHz 86 dB Output Offset Voltage Vos AVSPK_ 610B TA 25 C 0 5 3 mV EXCURSION LIMITER Upper ENS quen DHPUCF 001 to 100 400 1000 Hz Range Lower Corner Frequency DHPLCF 01 to 10 400 Hz DHPUCF 000 fixed mode 100 DHPUCF 001 200 iqua inimum Corner DHPUCF 010 300 Frequency DHPUCF 011 400 DHPUCF 100 500 ZSPK 80 68H VSP DHPTH 000 0 34 Threshold Voltage KLVDD VSPKRVDD 5 5 AVspk 8dB DHPTH 111 0 95 ALCRLS 101 0 25 Release Ti
74. lt 8 8 2 S 6 4 2 00k 10 100 1k 10k 100k FREQUENCY Hz FREQUENCY Hz MAKILA Maxim Integrated Products 37 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL or LOUTR to SPKLGND CREF 2 2 CMICBIAS CREG CC1N C1P CHPVDD CHPvss AVMICPRE_ 42088 AVMICPGA_ AVDACATTN AVDACGAIN AVADCLVL OGB AVADCGAIN AVPGAIN_ AVHP_ AVREC AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted DAC to Line Output INBAND OUTPUT SPECTRUM INBAND OUTPUT SPECTRUM OdBFS DAC TO LINE 60dBFS DAC TO LINE MCLK 13MHz LRCLK 8kHz FREQ MODE 10kQ MCLK 13MHz LK 8kHz EQ MODE 10kQ MAX98089 toc49 98089 10650 AMPLITUDE dBV AMPLITUDE dBV 20 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY kHz FREQUENCY kHz Line to Line Output TOTAL HARMONIC DISTORTION PLUS
75. overheating The stereo Class H headphone amplifier uses a dual mode charge pump to maximize efficiency while out putting a ground referenced signal This eliminates the need for DC blocking capacitors or a midrail bias for the headphone jack ground return Ground sense reduces output noise caused by ground return current The IC integrates jack detection allowing the detection of insertion and removal of accessories as well as button presses Maxim Integrated Products 60 Table 1 Register Map MAX98089 Low Power Stereo Audio Codec with FlexSound Technology I C Slave Address Configure the MAX98089 using the 12C control bus The IC uses a slave address of 0x20 or 00100000 for write operations and 0x21 or 00100001 for read operations See the Serial Interface section for a complete inter face description Registers Table 1 lists all of the registers their addresses and power on reset states Registers 0x00 to 0x03 and OxFF are read only while all of the other registers are read write Write zeros to all unused bits in the register table when updating the register unless otherwise noted REGISTER B7 B6 B5 B4 B3 B2 B1 ADDRESS DEFAULT R W STATUS Status CLD SLD ULK JDET 0x00 R 117 Micr
76. path to Maxim Integrated Products 78 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology the playback path in the digital audio interface to allow faces must be configured for the same sample rate but the IC s full complement of digital signal processing to the interface format need not be the same This allows be used Loopback allows digital data input to either the IC to route audio data from one device to another SDINS1 or SDINS2 to be routed from one interface to the converting the data format as needed Figure 15 shows other for output on SDOUTS2 or SDOUTS1 Both inter the available digital signal routing options SS BCLKS1 LRCLKS1 SDOUTS1 SDINS1 DVDDS1 BCLKS2 1301 52 50010152 SDINS2 DVDDS2 0 4 tat HIZOFF2 Nase SDOE Z SDIEN2 DATA DATA OUTPUT INPUT Z c c DAI DAI DAI2 RECORD PATH PLAYBACK PATH PLAYBACK PATH Figure 15 Digital Audio Signal Routing Table 9 Common Digital Audio Formats MODE WCH WCI2 BCH BCI2 DLY1 DLY2 TDM1 TDM2 SLOTL1 SLOTL2 SLOTR1 SLOTR2 Left Justified 1 0 0 0 X X 125 0 0 1 0 X PCM X 1 X 1 0 0 TDM X 1 X 1 Set as
77. power playback when using DAC to headphone playback path only When enabled this bit overrides the System Bias Control register settings When disabled the System Bias 2 HPPLYBCK Control register is used to enable system bias blocks Set both HPPLYBCK and PER 0x51 FMODE for lowest power consumption when using DAC to headphone playback path only 0 Disabled 1 Enabled 8kHz Power Save Mode PWRSV8K configures the ADC for reduced power consump tion when fs 8kHz PWRSV8K can be used in conjunction with PWRSV when fs 8kHz 1 PWRSV8K for more power savings 0 Normal high performance mode 1 2 Low power mode Power Save Mode PWRSV configures the ADC for reduced power consumption for all sample rates PWRSV can be used in conjunction with PWRSV8K for more power sav 0 PWRSV ings 0 Normal high performance mode 1 Low power mode Line Input A Enable 7 INAEN 0 Disabled 1 Enabled Line Input B Enable 6 INBEN 0 Disabled 1 Enabled Microphone Bias Enable Ox4C 3 BE 0 Disabled 1 Enabled Left ADC Enable 1 ADLEN 0 Disabled 1 Enabled Right ADC Enable 0 ADREN 0 Disabled 1 Enabled Maxim Integrated Products 67 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 2 Power Management Registers continued REGISTER BIT NAME DESCRIPTION Ox4D HPLEN Left Headphone Enable 0 Disabled 1 Enabled HPREN
78. serial clock line SCL SDA and SCL facilitate com munication between the IC and the master at clock rates up to 400kHz Figure 5 shows the 2 wire interface timing diagram The master generates SCL and initiates data transfer on the bus The master device writes data to the IC by transmitting the proper slave address followed by the register address and then the data word Each trans mit sequence is framed by a START S or REPEATED START Sr condition and a STOP P condition Each word transmitted to the IC is 8 bits long and is followed by an acknowledge clock pulse A master reading data from the IC transmits the proper slave address followed by a series of nine SCL pulses The IC transmits data on SDA in sync with the master generated SCL pulses The master acknowledges receipt of each byte of data Each read sequence is framed by a START or REPEATED START condition a not acknowledge and a STOP condi tion SDA operates as both an input and an open drain output A pullup resistor typically greater than 5000 is required on SDA SCL operates only as an input A pullup resistor typically greater than 5000 is required on SCL if there are multiple masters on the bus or if the single master has an open drain SCL output Series resistors in line with SDA and SCL are optional Series resistors pro tect the digital inputs of the IC from high voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals Bit T
79. signal path allows attenuation only and DAI2 playback audio paths The DAI1 signal path DVIG 0 6 12 18dB 0 2 2 048 TO 15dB ye 048 TO 15dB Figure 23 Playback Level Control Block Diagram Table 18 DAC Playback Level Control Register REGISTER BIT NAME DESCRIPTION DAI1 DAI2 Mute 7 DV1M DV2M 0 Disabled 1 Enabled Voice Mode Gain 5 DV1G only applies when MODE1 0 00 01 648 4 10 12dB 11 18dB Ox2F 0x31 3 DAI1 DAI2 Attenuation VALUE GAIN dB VALUE GAIN dB OxO 0 Ox8 8 2 Ox1 1 Ox9 9 DV1 DV2 Ox2 2 OxA 10 Ox3 3 OxB 11 1 Ox4 4 OxC 12 0 5 5 OxD 13 Ox6 6 14 i 0x7 7 15 MAKII Maxim Integrated Products 95 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology DAC Input Mixers The IC s stereo DAC accepts input from two digital audio paths The DAC mixer routes any audio path to the left and right DACs Figure 24 MIX MIXDAL Figure 24 DAC Input Mixer Block Diagram Table 19 DAC Input Mixer Register REGISTER BIT NAME DESCRIPTION 7 Left DAC Input Mixer 6 1xxx DAI left channel MIXDAL x1xx DAI right channel 5 1 DAI2 left channel 4 xxx1 DAI2 right channel 3 2 0x22 Right DAC Input Mixer 1xxx DAI left channel MIXDAR 1 DAI right channel 1 xx1x DAI2 left channel 0 1 DAI2 right cha
80. uses a charge pump to create an internal negative sup ply voltage This allows the headphone outputs of the ICs to be biased at GND while operating from a single supply Figure 1 Without a DC component there is no need for the large DC blocking capacitors Instead of two large 220uF typ capacitors the IC s charge pump requires 3 small ceramic capacitors conserving board space reducing cost and improving the frequency response of the headphone amplifier Charge Pump The dual mode charge pump generates both the positive and negative power supply for the headphone amplifier To maximize efficiency both the charge pump s switching fre quency and output voltage change based on signal level AVLAZCLA the switching frequency is reduced to a low rate This minimizes switching losses in the charge pump When the input signal exceeds 1096 of PVDD the switching fre quency increases to support the load current For input signals below 25 of PVDD the charge pump generates PVDD 2 to minimize the voltage drop across the amplifiers power stage and thus improve efficiency Input signals that exceed 25 of PVDD cause the charge pump to output PVDD The higher output voltage allows for full output power from the headphone amplifier To prevent audible gliches when transitioning from the PVDD 2 output mode to the xPVDD output mode the charge pump transitions very quickly This quick change draws significant current from PVDD for the
81. 0x3C 2 0x05 42 0x15 0 RECVOLL 0 06 38 0 16 1 RECVOLR 0x07 35 0x17 2 0x08 32 0x18 3 0x09 29 0x19 4 26 Ox1A 5 OxOB 23 Ox1B 6 0 0 20 Ox1C 46 5 17 Ox1D 7 14 Ox1E 7 5 OxOF 12 Ox1F 8 MAXIM Maxim Integrated Products 99 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Speaker Amplifiers The IC integrates a stereo filterless Class D amplifier that offers much higher efficiency than Class AB without the typical disadvantages The high efficiency of a Class D amplifier is due to the switching operation of the output stage transistors In a Class D amplifier the output transistors act as current steering switches and consume negligible additional power Any power loss associated with the Class D out put stage is mostly due to the 28 loss of the MOSFET on resistance and quiescent current overhead SPVOLL 4808 624 SPVOLR p 808 TO 6208 Figure 26 Speaker Amplifier Path Block Diagram MAXIM The theoretical best efficiency of a linear amplifier is 78 however that efficiency is only exhibited at peak output power Under normal operating levels typical music reproduction levels efficiency falls below 30 whereas the IC s Class D amplifier still exhibits 80 efficiency under the same conditions Traditional Class D amplifiers require the use of exter nal LC filters or shielding to meet
82. 1 200 BATTERY ADC Input Voltage Range 2 6 5 6 V LSB Size 0 1 V DIGITAL INPUT OUTPUT CHARACTERISTICS VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V TA 25 C unless otherwise noted Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MCLK Input High Voltage VIH 1 2 V Input Low Voltage VIL 0 6 V Input Leakage Current IL I VDVDD 2 0V VIN OV 5 5V TA 25 C 1 Input Capacitance 10 pF Maxim Integrated Products 19 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology DIGITAL INPUT OUTPUT CHARACTERISTICS continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V TA 25 C unless otherwise noted Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SDINS1 BCLKS1 LRCLKS1 INPUT 0 7 High Voltage DVDDS1 0 29 x nput Low Voltage VIL DVDDS1 y nput Hysteresis 200 mV nput Leakage Current IIH VDVDDS1 3 6V VIN OV 3 6V TA 25 C 41 1 nput Capacitance 10 pF BCLKS1 LRCLKS1 SDOUTS1 OUTPUT Output Low Voltage VOL 51 1 65V loi 0 4 V Output High Voltage VOH VDVDDS1 1 65V 3mA 207 V nput Leakage Current HL VDVDD 2 0V VIN 5 5 TA 252 1 1 uA high impedance state SDINS2 BCLK
83. 12 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
84. 48kHz 4 PLL MODE 2 MODE _ 40 Rup 32Q 217 RHP 320 _ 4 RHP 320 amp Cin 1pF amp 4 Cin 1pF amp Cin 1pF a 60 D w 6 x E ea 6 az 80 8 z g lt lt 100 40 10 120 120 12 140 140 140 20 20 0 20 FREQUENCY kHz FREQUENCY kHz FREQUENCY kHz MAXIM Maxim Integrated Products 34 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2yF CREG CC1N C1P CHPVDD AVMICPRE_ 209 AVDACGAIN AVADCLVL OGB AVADCGAIN AVPGAIN_ AVHP_ OdB AVREC AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted DAC to Receiver
85. 62dB TQFN package only 0 5 4 mV Capacitive Drive Capability No sustained oscillations RL 1kQ 500 pF Maxim Integrated Products 14 12 288MHz LRCLK 48kHz MAS TA TMIN to TMAx unless otherwise noted Typical MAX98089 Low Power Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out loads RLOUT connected from LOUTL or LOUTR to SPKLGND RLOAD RHP ee ee ZSPK ee CREF 2 2 CMICBIAS CREG CC1N C1P CHPVDD CHPVSS 1HF AVMICPRE_ 2088 AVMICPGA_ OdB AVDACGAIN OdB AVADCLVL AVADCGAIN OdB AVPGAIN_ AVHP_ AVspK_ OdB MCLK ues are at TA 25 C Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC TO SPEAKER AMPLIFIER PATH oo Distortion f 1kHz POUT 200m Zeek 8 68uH 68 dB SPKL to SPKR and SPKR to SPKL Crosstalk Pout 640mW f 1kHz 88 dB Output Noise 53 UVRMS Peak voltage A weighted Into shutdown 65 Click an
86. 8 INA1 EXTMICP INA2 EXTMICN Figure 6 Microphone Input Block Diagram MAXIM PGAM1 20dB 048 AGC CONTROL 5 PGAM1 20dB 048 Maxim Integrated Products 69 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 3 Microphone Input Registers REGISTER BIT NAME DESCRIPTION MIC1 MIC2 Preamplifier Gain 6 Course microphone gain adjustment 00 Preamplifier disabled L PA1EN PA2EN 01 OdB 5 10 2048 11 30dB MIC1 MIC2 PGA Fine microphone gain adjustment VALUE GAIN dB VALUE GAIN dB 3 0 00 20 Ox0B 9 0 35 0 36 0 01 1 OxOC 48 0x02 7 2 0x03 OxOE 6 PGAM1 PGAM2 0 04 1 OxOF 5 0 05 0 10 4 1 0 06 0 11 3 Ox07 0x12 2 0x08 1 0x13 1 0 0x09 11 0x14 to Ox1F 0 OxOA 10 Digital Microphone Clock Frequency 7 Select a frequency that is within the digital microphone s clock frequency range Set OSR1 1 when using a digital microphone MICCLK 00 PCLK 8 01 PCLK 6 6 10 64 x LRCLK 11 Reserved n 01 Left Digital Microphone Enable Set PA1EN 00 for proper operation 0 Disabled 1 Enabled 5 DIGMICL 0x48 Right Digital Microphone Enable Set PA1EN 00 for proper operation 0 Disabled 1 Enabled External Microphone Connection 1 Routes INA_ EXT
87. A6 24 um RXINP Switch input when receiver amp is shut down AT 25 PVDD Headphone Power Supply Bypass to HPGND with a 1uF and 10uF capacitor A8 31 HPVSS Inverting Charge Pump Output Bypass to HPGND with a ceramic capacitor A9 30 HPGND Headphone Ground RECN LOUTR Negative Receiver Amplifier Output or Right Line Output Can be negative bypass B6 23 RXINN switch input when receiver amp is shut down B7 26 1 Charge Pump Flying Capacitor Positive Terminal Connect a 1uF ceramic capacitor between C1N and C1P 27 CIN Charge Pump Flying Capacitor Negative Terminal Connect a 1uF ceramic capacitor between C1N and B9 32 HPVDD ae Charge Pump Output Bypass to HPGND with a 1uF ceramic capaci C1 C2 17 SPKRP Positive Right Channel Class D Speaker Output C3 18 SPKRVDD Right Speaker Power Supply Bypass to SPKRGND with a 1uF capacitor C4 C5 21 SPKLGND Left Speaker Ground C6 55 11 14 D6 D7 E3 28 29 46 No Connection Headphone Amplifier Ground Sense Connect to the headphone jack ground C8 34 HPSNS terminal for optimal performance or connect to PCB ground C9 33 HPL Left Channel Headphone Output 1 Digital Audio Bit Clock Input Output BCLKS1 is an input when the IC is in slave D1 8 BCLKS1 mode and an output when in master mode The input output voltage is referenced to DVDDS1 02 7 SDOUTS1 1 Digital Audio Serial Data ADC Output The output voltage is referenced to DVDDS1 51 Digital
88. ASEN See the Power Management section JACKSNS Pullup When JDWK 1 JACKSNS is slow to increase in voltage Set JDWK 0 before setting 0 JDWK JDETEN 1 to prevent false detection Valid when MBIAS 0 0 2 4kQ to SPKLVDD allows microphone detection 1 5pA to SPKLVDD minimizes supply current Battery Measurement The IC measures the voltage applied to SPKLVDD typically the battery voltage and reports the value in register This value is also used by the speaker limiter circuitry to set accurate thresholds When the battery measurement func tion is disabled the battery voltage is user programmable Table 35 Battery Measurement Registers REGISTER BIT NAME DESCRIPTION Battery Voltage 3 Read VBAT when VBATEN 1 to determine VsPKLVDD Program when 0x03 2 VBAT 0 to allow proper speaker amplifier signal processing Calculate program the battery 1 voltage using the following formula 0 VBATTERY 2 55V VBAT 10 7 SHDN See the Power Management section Battery Measurement Enable Enables an internal ADC to measure VSPKLVDD 6 VBATEN 0 Disabled register 0x03 readable and writeable 1 Enabled register 0x03 read only 0x51 5 3 PERFMODE See the Power Management section 2 HPPLYBCK See the Power Management section 1 PWRSV8K See the Power Management section 0 PWRSV See the Power Management section MAKII Maxim Integrated Products 116
89. AVsek 808 Cin 1 E CN 1pF 3 3 20 1 2 4 S 2 2 30 o o amp 1 4 a a Pour 0 5W 0 50 50 E 60 60 7 3 70 8 Pout 0 25W 4 80 90 5 0 02 04 06 08 10 10 100 1k 10k 100k 10 00 1 10k 100k OUTPUT POWER W FREQUENCY Hz FREQUENCY Hz POWER SUPPLY REJECTION RATIO CROSSTALK vs FREQUENCY vs FREQUENCY LINE TO SPEAKER LINE TO SPEAKER 90 0 g 5 ZFN 80 68 80 8 2 Cin 8 70 i 60 RIPPLE ON SPKLVDD mod 50 RIPPLE ON AVDD SPKRVDD x DVDD HPVDD M 5 40 2 RIGHT TO LEF 30 8 20 10 PUTS AC GROUNDED i LEFT TO RIGHT VRIPPLE 200mVp p 0 120 10 100 k k Ok 10 0 1k 10k 100k FREQUENCY Hz FREQUENCY Hz MAAKLM Maxim Integrated Products 44 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL or LOUTR to SPKLGND CREF 2 2uF CMICBIAS CREG 1UF CC1N C1P CHPVDD CHPvss AVMICPRE_ 209 AVMICPGA_ AVDACGAIN OdB AVADCLVL OGB AVADCGAIN AVPGAIN_ AVHP_ OdB AV
90. Analog 3 6 6 5 stereo speaker outputs Speaker 6 41 8 5 AS 1 Digita 249 35 Shutd S Analog 0 2 2 utdown Supply Curren _ Note 2 TA 25 C speaker 0 01 1 Digita 1 5 REF Voltage 2 5 V REG Voltage 0 79 V VSEN 30 Shutdown to Full Operation VSEN S0 ms VSEN 1 17 MAXIM Maxim Integrated Products 6 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out loads RLOUT connected from LOUTL or LOUTR to SPKLGND RLOAD RHP ee ee ZSPK ee CREF 2 2 CMICBIAS CREG CC1N C1P CHPVDD CHPVSS 1HF AVMICPRE_ 2088 AVMICPGA_ OdB AVDACGAIN OdB AVADCLVL AVADCGAIN OdB AVPGAIN_ OdB AVHP_ AVspK_ OdB MCLK 12 288MHz LRCLK 48kHz MAS TA TMIN to TMAx unless otherwise noted Typical values are at 25 C Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP UNITS MICROPHONE TO ADC PATH Dynamic Range DR ee MODE 0 IIR voice AVMICPRE_ 088 88 dB 897 VIN O 1VP P fs 8kHz f 1kH
91. C LP Ox4F oxoo R W 87 Power Mode 1 DAC Low DAC2 IP CGM2_ CGM1 Power Mode 2 EN DITH EN EN EN OXOR 218 System 67 SHDN VBATEN PERFMODEIHPPLYBACKIPWRSV8K PWRSV 0x51 R W Shutdown 116 Maxim Integrated Products 64 Table 1 Register Map continued MAX98089 Low Power Stereo Audio Codec with FlexSound Technology REGISTER B7 B6 B5 B4 B3 B2 B1 BO ADDRESS DEFAULT R W PAGE DSP COEFFICIENTS K 1 15 8 0 52 0 84 R W 93 1 7 0 0 53 0 85 R W 93 K1_1 15 8 0x54 0x86 93 K1_1 7 0 Ox55 0x87 93 EQ Band 1 K2 1 15 8 0 56 0 88 RW 93 DAI1 DAI2 K2_1 7 0 0 57 0 89 RW 93 c1 1 15 8 93 c1_1 7 0 0x59 0x8B R W 93 c2_1 15 8 Ox5A Ox8C RW 93 c2_1 7 0 Ox5B OX8D RW 93 K_2 15 8 93 K 2 7 0 0 50 0 8 RW 98 K1_2 15 8 Ox5E 0x90 93 K1_2 7 0 0 5 0 91 93 2 K2_2 15 8 0 60 0 92 R W 93 DAI DAI2 K2 2 7 0 0 61 0 93 R W 93 c1 2 15 8 Ox62 0x94 RW 93 c1 2 7 0 0 63 0 95 93
92. Codec with FlexSound Technology Detailed Description The 98089 is a fully integrated stereo audio codec with FLEXSOUND technology and integrated amplifiers Two differential microphone amplifiers can accept signals from three analog inputs One input can be retasked to support two digital microphones Any combination of two microphones analog or digital can be recorded simul taneously The analog signals are amplified up to 5098 and recorded by the stereo ADC The digital record path supports voice filtering with selectable preset highpass filters and high stopband attenuation at fs 2 An automat ic gain control AGC circuit monitors the digitized signal and automatically adjusts the analog microphone gain to make best use of the ADC s dynamic range A noise gate attenuates signals below the user defined threshold to minimize the noise output by the ADC The IC includes two analog line inputs One of the line inputs can be optionally retasked as a third analog micro phone input Both line inputs support either stereo single ended input signals or mono differential signals The line inputs are preamplified and then routed to the ADC for recording and or to the output amplifiers for playback The single ended line inputs signals from INA1 and INA2 can bypass the PGAs and be connected directly to the ADC input to provide the best dynamic range Integrated analog switches allow two differential micro phone signals to b
93. E CONNECTION NAME CONNECTION SPKRP Unconnected INB1 Unconnected SPKRVDD Always connect INA2 MICEXTN Unconnected SPKLVDD Always connect LRCLKS2 Unconnected SPKLP Unconnected MCLK Always connect RECN RXINN Unconnected SDINS2 AGND HPVDD Unconnected Unconnected C1P Unconnected MIC1P DIGMICDATA Unconnected HPGND AGND INA1 MICEXTP Unconnected SPKRN Unconnected DGND Always connect SPKRGND Always connect BCLKS2 Unconnected SPKLGND Always connect SDA Always connect SPKLN Unconnected SCL Always connect RECP RXINP Unconnected REG Always connect Unconnected REF Always connect HPL Unconnected MIC1N DIGMICCLK Unconnected HPVSS Unconnected MIC2P Unconnected SDINS1 AGND SDOUTS2 Unconnected LRCLKS1 Unconnected DVDDS2 DVDD HPSNS AGND DVDD Always connect INB2 Unconnected AVDD Always connect HPR Unconnected PVDD Always connect DVDDS1 DVDD AGND Always connect SDOUTS1 Unconnected MICBIAS Unconnected BCLKS1 Unconnected MIC2N Unconnected JACKSNS Unconnected IVI Maxim Integrated Products 125 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Recommended PCB Routing The MAX98089EWY uses a 63 bump WLP package Figure 43 provides an example of how to connect to all active bumps using 3 layers of the PCB To ensure terrupted ground returns use layer 2 as a connecting layer between layer 1 and layer 3 and flood the remaining area with ground LAYER 2 LAYER 3 Figure 43 Suggested Routing for the MAX98089
94. EN55022B and FCC electromagnetic interference EMI regulation standards Maxim s patented active emissions limiting edge rate control circuitry reduces EMI emissions allowing opera tion without any output filtering in typical applications RVD PKR SPKR SPKRGN Maxim Integrated Products 100 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Speaker Output Mixers The IC s speaker amplifiers accept input from the stereo DAC the line inputs single ended ore differential and the MIC inputs Configure the mixer to mix any combination of the available sources When more than one signal is selected the mixer can be configured to attenuate the signal by 9dB 1 Table 22 Speaker Output Mixer Register REGISTER BIT NAME DESCRIPTION 7 Speaker Output Mixer 6 1 Right DAC 5 1 MIC2 4 1 MIC1 Ox2B MIXSPL xxx1xxxx INB2 INBDIFF 0 or INB2 INB1 INBDIFF 1 3 Xxxx1xxx INB1 2 1 INA2 INBDIFF 0 or INA2 INA1 INADIFF 1 1 XXXXXX1X INA T 0 XXXxxxx1 Left DAC 7 Right Speaker Output Mixer 6 1 Left DAC 5 x1xxxxxx 2 MIC2 4 1 MIC1 Ox2C MIXSPR xxx1xxxx INB2 INBDIFF 0 or INB2 INB1 INBDIFF 1 3 Xxxx1xxx INB1 2 xxxx1xx INA2 INADIFF 0 or INA2 INA1 INADIFF 1 1 XXxxxx1lx INA1 0 Xxxxxxx1
95. EWY MAXIM Supply Bypassing Layout and Grounding Proper layout and grounding are essential for optimum performance When designing a PCB for the ICs parti tion the circuitry so that the analog sections of the IC are separated from the digital sections This ensures that the analog audio traces are not routed near digital traces Use a large continuous ground plane on a dedicated layer of the PCB to minimize loop areas Connect AGND DGND HPGND SPKLGND and SPKRGND directly to the ground plane using the shortest trace length possible Proper grounding improves audio performance minimizes crosstalk between channels and prevents any digital noise from coupling into the analog audio signals Ground the bypass capacitors on MICBIAS REG and REF directly to the ground plane with minimum trace length Also be sure to minimize the path length to AGND Bypass AVDD directly to AGND Connect all digital I O termination to the ground plane with minimum path length to DGND Bypass DVDD DVDDS1 and DVDDS2 directly to DGND Place the capacitor between and C1N as close as possible to the ICs to minimize trace length from C1P to Inductance and resistance added between and reduce the output power of the headphone ampli fier Bypass HPVDD and HPVSS with a capacitor located close to HPVSS with a short trace length to HPGND Close decoupling of HPVSS minimizes supply ripple and maxi mizes output power from the headph
96. GAIN MODE RexT 56kQ 8 RIPPLE ON SPKLVDD SPKRVDD 4 g n 6 TRI RIPPLE ON AVDD DVDD HPVDD 40 7 mn 20 90 100 0 10 100 1k 10k 100k 10 100 k Ok 00k FREQUENCY Hz FREQUENCY MAXIM Maxim Integrated Products 32 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2yF CREG CC1N C1P CHPVDD AVMICPRE_ 209 AVDACGAIN AVADCLVL OdB AVADCGAIN AVPGAIN_ AVHP_ OdB AVREC AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted Line In Pin Direct to ADC TOTAL HARMONIC DISTORTION PLUS NOISE POWER SU
97. IGMICCLK OUTPUT Output Low Voltage VOL VDVDD 1 65V lo 1mA 0 4 V Output High Voltage VOH VDVDD 1 65V 1 2 Y INPUT CLOCK CHARACTERISTICS VAVDD VPVDD VDVDD VDVDDS1 VDVD Note 1 DS2 1 8V VSPKLVDD VSPKRVDD 3 7V TA 25 C unless otherwise noted PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CLK Input Frequency MCLK 10 60 MHz CLK Input Duty Cycle _____ PSCLK 10 or 11 30 70 aximum MCLK Input Jitter 100 PSRMS LRCLK Sample Rate Note 8 5 kHz 1 48 96 DAI1 LRCLK Average Frequency FREQ1 0 to OxF 0 0 Error Note 9 FREQ1 0 0 0 025 0 025 a Frequency 0 025 40 025 PLL Lock Time Rapid Ock mode 2 T Nonrapid lock mode 12 25 aximum LRCLK Jitter to Maintain 400 PLL Lock Soft Start Stop Time 10 ms MAXIM Maxim Integrated Products 21 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology AUDIO INTERFACE TIMING CHARACTERISTICS VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V TA 25 C unless otherwise noted Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS BCLK Cycle Time Slave mode 90 ns BCLK High Time tBCLKH Slave mode 20 ns BCLK Low Time tBCLKL Slave mode 20 ns BCLK or LRCLK Rise and Fall Time tR Master mode CL 15pF 5 ns SDIN to BCLK
98. ITAL CONTROL AUDIO AUDIO INTERFACE INTERFACE DIGITAL MICROPHONE INPUT FLEXSOUND TECHNOLOGY 5 44 5 BAND PARAMETRIC EQ AUTOMATIC LEVEL CONTROL SPEAKER AMP LOUDSPEAKER PROCESSING 0 EXCURSION LIMITER THD LIMITER POWER LIMITER MICROPHONE PROCESSING SPEAKER AMP AUTOMATIC GAIN CONTROL C NOISE GATE ASYNCHRONOUS DIGITAL MIXING MUP HEADPHONE AMP MAXIM MAX98089 T Ps HEADPHONE AMP MAKII Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com MAX98089 Low Power Stereo Audio Codec with FlexSound Technology TABLE OF CONTENTS General Description s iuda d eom Oe tad ee oe oe acr Ge Gee ead eR Edda eA SEER 1 i r TE 1 SIMPE e pio 1 1 stara s ot P euch V Ea etek ed 5 Absolute Maximum e a OR DX ded Ade 6 Ele
99. Input AC couple a microphone with a series DIGMICCLK 1uF capacitor Can be retasked as a digital microphone clock output F9 39 INA1 Single Ended Line Input A1 Also negative differential line input A or positive dif EXTMICP ferential external microphone input Maxim Integrated Products 58 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Bump Pin Description continued BUMP PIN WLP FUNCTION G1 1 SDOUTS2 52 Digital Audio Serial Data ADC Output The output voltage is referenced to DVDDS2 G2 55 DVDDS2 52 Digital Audio Interface Power Supply Input Bypass to with ca pacitor 52 Digital Audio Serial Data DAC Input The input voltage is referenced to G3 54 SDINS2 DVDDS2 Digital Power Supply Supply for the digital core and 12C interface Bypass to G4 ae DVDD DGND with 1pF capacitor G5 50 AVDD Analog Power Supply Bypass to AGND with a 11 capacitor G6 48 REF Converter Reference Bypass to AGND with a 2 21 capacitor G7 47 AGND Analog Ground 43 MIC2N Negative Differential Microphone 2 Input AC couple a microphone with a series 1 capacitor G9 42 MIC2P Positive Differential Microphone 2 Input AC couple a microphone with a series 1uF capacitor EP Exposed Pad TQFN Only Connect the exposed pad to the PCB ground plane MAKILA Maxim Integrated Products 59 MAX98089 Low Power Stereo Audio
100. KRVDD MAX98089 toc103 MAX98089 toc104 MAX98089 toc105 POWER CONSUMPTION mW CURRENT CONSUMPTION 0 1 1 10 100 100 Ok OUTPUT POWER PER CHANNEL mW OUTPUT POWER PER CHANNEL mW FREQUENCY Hz POWER SUPPLY REJECTION RATIO CROSSTALK vs FREQUENCY vs FREQUENCY DAC TO HEADPHONE DAC TO HEADPHONE 120 g 5 RIPPLE ON SPKLVDD 8 CLK 12 288MHz SPKRVDD 3 LRCLK 48kHz 100 E 7 NI MODE RHP 320 80 amp 2 6 RIPPLE ON AVDD 2 a PVDD DVDD 2 4 2 VniPPLE 200mVp p 100 k k 100k Ok FREQUENCY Hz FREQUENCY kHz MAXIM Maxim Integrated Products 49 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N
101. LELELELELRLELEL LLL TLITLTPO SDIN 015101410131012101110101 D9 D8 D7 061051 D4 A D2 D1 A DO D154D144D134D124D114D10A 09 D7 A D6 DS D4 D3 D2 A D1 DO WCI_ 1 CL 0 DLY_ 0 TOM_ 0 FSW_ 0 WS_ 0 HIZOFF_ 1 SLOTL_ 0 SLOTR_ 0 LEFT RIGHT mm SDOUT oo or os Kos o9 9 SN 0 0908 or osos 0302 ASN 1 BCLK AL A A ATA A A son 2 09 08X07 032 oo NN 00 42 201109 oos Kos WCI_ 0 BCI_ 1 DLY_ 0 TDM_ 0 FSW_ 0 WS_ 0 HIZOFF_ 1 SLOTL_ 0 SLOTR_ 0 LRCLK LEFT RIGHT SDOUT N A 01401011 K NN 0 50 4013012012 AR AR AR An AR ARAL AGAR AR ARAL ARAB ARAL ARAL L 0 0440140721 01101009 06 05 bo 2 500140 3 12011010 807 05 01X oo NNI WCI_ 0 BCI_ 0 DLY_ 1 TDM_ 0 FSW_ 0 WS_ 0 HIZOFF_ 1 SLOTL_ 0 SLOTR_ 0
102. LK 48kHz NI MODE NI MO 2 NI S 30 Zsp_ 80 68 ZSPK_ 68uH ZSPK_ 33H o 1 AVspk_ 4848 5 5 30 _ 89 amp 4 Pour 0 55W 2 50 Pour 0 25W 2 8 5 60 E 70 6 80 Pout 0 55W 7 90 8 100 k 10k 100k 0 Ok Ok FREQUENCY Hz FREQUENCY Hz FREQUENCY Hz Maxim Integrated Products 40 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2yF CREG CC1N C1P CHPVDD CHPvss AVMICPRE_ 209 AVMICPGA_ AVDACGAIN AVADCLVL OGB AVADCGAIN 088 AVPGAIN_ AVHP_ 5 _ MCLK 12 288MHz LRCLK 48kHz MAS 1 Ta 25 C unless otherwise noted TOTAL HARMONIC DISTORTION PLUS NOISE OUTPUT POWER
103. LVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2yF CREG CC1N C1P CHPVDD CHPvss AVMICPRE_ 209 AVMICPGA_ AVDACGAIN AVADCLVL OGB AVADCGAIN 088 AVPGAIN_ OdB AVHP_ OdB 5 _ MCLK 12 288MHz LRCLK 48kHz MAS 1 Ta 25 C unless otherwise noted SOFTWARE TURN ON OFF RESPONSE SOFTWARE TURN ON OFF RESPONSE DAC TO RECEIVER VSEN 0 DAC TO RECEIVER VSEN 1 98089 toc41 98089 toc42 SCL 2V div SCL 1V div RECEIVER OUTPUT 0 5V div RECEIVER OUTPUT 1V div 10ms div 10ms div FFT OdBFS DAC TO RECEIVER FFT 60dBFS DAC TO RECEIVER MCLK 13MHz LRCLK 8kHz FREQ MODE 320 MCLK 13MHz LRCLK 8kHz FREQ MODE 320 MAX98089 toc43 98089 10044 AMPLITUDE dBV AMPLITUDE dBV FREQUENCY kHz FREQUENCY kHz MAXIIAVI Maxim Integrated Products 36 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads
104. MAKILA gt INNOVATION DELIVERED MAX98089 Low Power Stereo Audio Codec with FlexSound Technology General Description Features The 98089 is a full featured audio codec whose high 5 6mW Power Comsumption DAC to HP at 97dB DR performance and low power consumption make it ideal 101dB DR Stereo DAC 8kHz lt fs lt 96kHz for portable applications 93dB DR Stereo ADC 8kHz fs 96kHz Class D speaker amplifiers provide efficient amplification Stereo Low EMI Class D Amplifiers for two speakers Low radiated emissions enable com 1 7W Channel 80 VSPK VDD 5 0V pletely filterless operation Integrated bypass switches 2 9W Channel 40 VSPK VDD 5 0V optionally connect an external amplifier to the transducer when the Class D amplifiers are disabled Efficient Class H Headphone Amplifier Differential Receiver Amplifier Stereo Line Outputs The IC features a stereo Class H headphone amplifier 2 Stereo Single Ended Mono Differential Line that utilizes a dual mode charge pump to maximize effi Inputs ciency while outputting a ground referenced signal that 3 Differential Microphone Inputs does not require output coupling capacitors 9 FlexSound Technology The IC also features a mono differential amplifier that can 5 Band Parametric EQ also be configured as a stereo line output Automatic Level Control ALC 1 Excursion Limiter Two differential analog microphone inputs are availabl
105. MAX98089 Low Power Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out loads RLOUT connected from LOUTL or LOUTR to SPKLGND RLOAD RHP ZSPK CREF 2 2UF CMICBIAS CREG CC1N C1P CHPVDD 55 1HF AVMICPRE_ 200 AVMICPGA_ AVDACATTN OdB AVDACGAIN OdB AVADCLVL AVADCGAIN OdB AVPGAIN_ AVHP_ AVspK_ OdB MCLK 12 288MHz LRCLK 48kHz MAS TA TMIN to TMAx unless otherwise noted Typical values are at TA 25 C Note 1 VsPKL_ VSPKLVDD OV PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS HEADPHONE AMPLIFIER RHP 320 30 Output Power Pour 1kHz THD 1 mW 160 38 Positive Charge Pump Output HPVDD VOUT lt VPVDD x 02V RHP PVDD 2 V Voltage VOUT gt VPVDD X 0 2V RHP ee PVDD Negative Charge Pump Out HPVSS VOUT lt VPVDD x 02V RHP PVDD 2 V put Voltage VOUT gt VPVDD x 0 2V RHP PVDD Output Voltage Threshold Output Voltage at which the Charge Pump Switch
106. MIC_ to the microphone preamplifiers Set INAEN 0 when using INA_ EXTMIC_ as a microphone input EXTMIC 00 Disabled 01 MIC1 input 0 10 MIC2 input 11 Reserved 4 DIGMICR MAKII Maxim Integrated Products 70 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 3 Microphone Input Registers continued REGISTER BIT NAME 7 INABYP 0 Disabled 1 Enabled 4 MIC2BYP 0 Disabled 1 Enabled 0 4 1 0 SPKBYP Line Inputs The device includes two sets of line inputs Figure 7 Each set can be configured as a stereo single ended input or as a mono differential inout Each input includes adjustable gain to match a wide range of input signal levels If a custom gain is needed the external gain mode provides a trimmed feedback resistor Set the gain PGAINA 420dB 6dB INA1 EXTMICP PGAINA 420dB TO 6dB INA2 EXTMICN gt lt PGAINB 42048 TO 6dB Oo INBDIFF PGAINB 420dB TO 6dB Figure 7 Line Input Block Diagram MAXIM DESCRIPTION INA_ EXTMIC_ to MIC1_ Bypass Switch MIC1_ to MIC2_ Bypass Switch See the Output Bypass Switches section by choosing the appropriate input resistor and using the following formula AVPGAIN 20 log 2 The external gain mode also allows summing multiple signals into a single input by connecting multiple in
107. N NO 56 TQFN 15677 1 21 0144 90 0042 63 WLP W633A3 1 21 0462 DETAIL A MARKING PHA BOTTOM VIEW R IS OPTIONAL DETAIL ilil Na i 9 TERMINAL TIP 2 EVEN TERMINAL ODD TERMINAL AVIAXIL VI TITLE PACKAGE OUTLINE 32 44 48 S6L THIN QFN 7x7x0 75m APPROVAL DOCUMENT CONTROL NO NG NOT SCALE 21 0144 SIDE VIEW MAXIM Maxim Integrated Products 128 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Package Information continued For the latest package outline information and land patterns footprints go to www maxim ic com packages Note that or in the package code indicates RoHS status only Package drawings may show a different suffix character but the drawing pertains to the package regardless of RoHS status COMMON DIMENSIONS EXPOSED PAD VARIATIONS CUSTOM PKG PKG DEPOPULATED 02 14877 1 CODES LEADS PKG 321 7x7 44 7x7 481 7x7 48L 7x7 56L 7x7 ara SYMBOL
108. PPLY REJECTION RATIO vs FREQUENCY LINE TO ADC PIN DIRECT vs FREQUENCY LINE TO ADC PIN DIRECT 0 E 120 8 4 MCLK 12 288MHz PLE 200mVp p LRCLK 48kHz 100 M 4 1 20 NI MODE P Vin 1Vp p 3 AVPGAIN_ 048 ERE 2 4 Cin 60 50 Ed 60 40 7 20 8 90 0 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY Hz FREQUENCY Hz Digital Loopback FFT OdBFS SDINS1 TO SDINS2 FFT 604 5 SDINS1 TO SDINS2 DIGITAL LOOPBACK DIGITAL LOOPBACK MCLK 12 288MHz 13 3 2 LRCLK 48kHz 2 NI MODE 4 NI MODE 60 e gt gt Eon z 40 140 160 18 20 20 FREQUENCY kHz FREQUENCY kHz Maxim Integrated Products 33 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2yF CREG CC1N C1P CHPVDD AVMICPRE_ 209 AVDACGAIN AVADCLVL OGB AVADCGAIN AVPGAIN_ AVHP_ AVREC AVspK_ MCLK 12 288MHz LRCLK
109. R W PAGE 82 Filters 0 DHF2 0 0 DCB2 0x20 0x00 R W 96 SRC Sample Rate Converter SRMIX_ SRMIX SRC SRC ENL ENR ENL ENR 0x21 0x00 R W 89 MIXERS DAC Mixer MIXDAL MIXDAR 0x22 0x00 R W 96 Left ADC ixer MIXADL 0x23 0x00 R W 73 Right ADC ixer MIXADR 0x24 0x00 R W 73 Left Headphone Amplifier ixer MIXHPL 0x25 0x00 R W 110 Righ Headphone Amplifier Mixer MIXHPR 0x26 0x00 R W 110 Headphone Amplifier Mixer Control MIXHPR_ PATHSEL MIXHPL_ PATHSEL MIXHPR MIXHPL GAIN 0 27 0x00 R W 110 Left Receiver Amplifier Mixer MIXRECL 0 28 0x00 R W 98 Righ Receiver Amplifier Mixer MIXRECR 0x29 0x00 R W 98 Receiver Amplifier Mixer Control LINE_ MODE MIXRECR_GAIN MIXRECL_GAIN Ox2A 0x00 R W 98 Left Speaker Amplifier Mixer MIXSPL Ox2B 0x00 R W 101 Righ Speaker Amplifier Mixer MIXSPR Ox2C 0x00 R W 101 Speaker Amplifier Mixer Control MIXSPR_GAIN MIXSPL_GAIN Ox2D 0x00 R W 101 Maxim Integrated Products 62 Table 1 Register Map continued MAX98089 Low Power Stereo Audio Codec with FlexSound Technology
110. REC AVspK_ OdB MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted TOTAL HARMONIC DISTORTION PLUS NOISE DAC to Headphone vs OUTPUT POWER DAC TO HEADPHONE MCLK 13MHz LRCLK 8kHz FREQ MODE 98089 toc84 En Rup 320 _ 3dB PACKAGE 1 TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER DAC TO HEADPHONE MCLK 13MHz LRCLK 8kHz FREQ MODE 98089 toc85 Rup 320 308 WLP PACKAGE Az THD N RATIO dB THD N RATIO dB a TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER DAC TO HEADPHONE MCLK 13MHz 10 F LRCLK 44 1kH PLL MODE MAX98089 toc86 32Q 30 F AVHP_ 308 TQFN PACKAGE 3 f 100 THD N RATIO dB 1 600 i o f 300 f 1000Hz 0 0 01 0 0 100Hz 2 0 03 0 04 0 05 OUTPUT POWER W TOTAL HARMONIC DISTORTION PLUS NOISE MCLK 13MHz vs OUTPUT POWER DAC TO HEADPHONE 0 LRCLK 44 1kHz PLL MODE 98089 10287 WLP PACKAGE f 6000H Hz HD N RATIO dB HD N RATIO dB 60 0 0 0 005 MAALM 0 015 OUTPU f 100Hz 0 025 0 035
111. ROL AVLG 0 6 AVRG 0 6 PGAM2 12 1808 12 1808 2008 008 AVL OdB AVR OdB TO 15dB TO 15dB Figure 10 Record Path Signal Processing Block Diagram AVLAZCLA Noise Gate Since the AGC increases the levels of all signals below a user defined threshold the noise floor is effectively increased by 20dB To counteract this the noise gate reduces the gain at low signal levels Unlike typical noise gates that completely silence the output below a defined level the noise gate in the IC applies downward expan sion The noise gate attenuates the output at a rate of 1dB for each 288 the signal is below the threshold with a maximum attenuation of 12dB The noise gate can be used in conjunction with the AGC or on its own When the AGC is enabled the noise gate reduces the output level only when the AGC has set the gain to the maximum setting Figure 11 shows the gain response resulting from using the AGC and noise gate AGC AND NOISE GATE AMPLITUDE RESPONSE 2 2 O _ AGC AND NOISE 7743 AGC AND NOISE GATE y GATE DISABLED 1 OUTPUT AMPLITUDE dBFS NOISE GATE ONLY an e an 80 60 40 INPUT AMPLITUDE dBFS Figure 11 AGC and Noise Gate Input vs Output Gain Maxim Integrated Products 73 MAX98089 Low Power Stereo Audio Codec with FlexSo Table 6 Record Path Signal Processing Registers und Technology
112. ROSSTALK vs FREQUENCY DAC TO SPEAKER CLK 12 288MHz LRCLK 48kHz MAX98089 toc73 20 MODE Zspk 80 CROSSTALK dB 100 RIGHT 10 100 1k 10k FREQUENCY Hz 120 FFT 60dBFS DAC TO SPEAKER MCLK 12 2888MHz LRCLK 48kHz NI MODE 29 80 68uH 100k 98089 toc76 AMPLITUDE dBV 0 5 1 15 FREQUENCY kHz MAALM 20 SOFTWARE TURN ON OFF RESPONSE DAC TO SPEAKER VSEN 0 98089 toc74 SCL SPEAKER OUTPUT 1 1V div 10ms div FFT 60dBFS DAC TO SPEAKER 0 MCLK 13MHz 5 20 LRCLK 44 1kHz2 E PLL MODE 20 2044 Zspk lt 80 68H Z 6 a c 2 20 10 80 12 14 100 20 SOFTWARE TURN ON OFF RESPONSE DAC TO SPEAKER VSEN 1 98089 toc75 cal SCL 1 1V div 4 SPEAKER OUTPUT 1 1V div 10ms div WIDEBAND FFT DAC TO SPEAKER MCLK 13MHz LRCLK 44 1kHz PLL MODE 98089 toc78 Zspk 80 68 Maxim Integrated Products 43 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD
113. Release Time 5 ALCRLS 000 8 PARAMETRIC EQUALIZER umber of Bands 5 Bands Per Band Gain Range 12 12 dB Preattenuator Gain Range Note 5 15 0 Preattenuator Step Size 1 dB DAC TO RECEIVER AMPLIFIER PATH Dynamic Range DR fs 48kHz f 1kHz Note 4 96 dB Output Offset Voltage Vos AVREC 628B TA 25 C WLP package only 0 5 4 mV A PE Distortion THD N f 1kHz Pour 15mW RREC 320 63 dB VSPKLVDD 2 8V to 5 5V TA 25 C 64 75 f 217Hz V 200mVp 80 Power Supply Rejection Ratio PSRR f 1kHz VRIPPLE 200mVp p 80 f 10kHz VRIPPLE 200mVp p TT MAALM Maxim Integrated Products 13 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out loads RLOUT connected from LOUTL or LOUTR to SPKLGND RLOAD RHP ee ee ZSPK ee CREF 2 2 CMICBIAS CREG CC1N C1P CHPVDD 5 1HF AVMICPRE_ 2088 AVMICPGA_ AVDACGAIN OdB AVADCLVL AVADCGAIN OdB AVPGAIN_ OdB AVHP_ AVspK_ MCLK
114. Right DAC 8 Right Speaker Mixer Gain Select MIXSPR 06 01 6dB 2 10 11 Ox2D 1 Left Speaker Mixer Gain Select MIXSPL imi GAIN 01 0 7 10 11 Maxim Integrated Products 101 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Speaker Output Volume Table 23 Speaker Output Level Register REGISTER BIT NAME DESCRIPTION Left Right Speaker Output Mute 4 SPLM SPRM 0 Disabled 1 Enabled Left Right Speaker Output Volume Level VALUE VOLUME dB VALUE VOLUME dB 0x00 62 0x10 10 0x01 58 0x11 8 0x02 54 0x12 6 0x03 50 0x13 4 0x04 46 0x14 2 3 0 05 42 0 15 0 SPVOLL SPVOLR 2 ual 0 07 35 0x17 2 0x08 32 0x18 3 0x09 29 0x19 4 26 5 OxOB 23 Ox1B 6 OxOC 20 Ox1C 6 5 17 Ox1D 7 14 Ox1E 7 5 12 Ox1F 8 Speaker Amplifier Signal Processing The IC includes signal processing to improve the sound quality of the speaker output and protect transducers from damage An excursion limiter dynamically adjusts the highpass corner frequency while a power limiter and distortion limiter prevent the amplifier from outputting too much distortion or power The excursion limiter is located in the DSP while the distortion limiter and power limiter control the analog
115. S THE TERMINALS DRAWING CONFORMS TO JEDEC MO220 EXCEPT THE EXPOSED PAD DIMENSIONS OF 4877 3 4 6 amp 15677 1 10 WARPAGE SHALL NOT EXCEED 0 10 mm IMAX N MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY TITLE 12 NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY 13 ALL DIMENSIONS APPLY TO BOTH LEADED AND PbFREE PKG CODES 4 QFN 7x7x0 75m APPROVAL DOCUMENT CONTROL NO DRAWING NOT TO SCALE 21 0144 Maxim Integrated Products 129 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Package Information continued For the latest package outline information and land patterns footprints go to www maxim ic com packages Note that a Or in the package code indicates RoHS status only Package drawings may show a different suffix character but the drawing pertains to the package regardless of RoHS status PIN 1 INDICATOR X 1 COMMON DIMENSIONS 0 64 0 05 0 19 0 03 0 45 REF 0 025 BASIC 20 27 0 03 2 40 BASIC VIEW TOP E1 SE e TE 50006 COO Pi O O O O Q O O O H 1 2 53 4 5 6 7 8 9 1 T VIEW TOM DRAWING NOT SCALE MAXIM SEE SIDE
116. S2 LRCLKS2 INPUT 0 7 x nput High Voltage VIH DVDDS2 V 0 29 x nput Low Voltage VIL DVDDS2 V nput Hysteresis 200 mV nput Leakage Current VbVDDS2 3 6V VIN OV 3 6V TA 25 C 1 1 nput Capacitance 10 pF BCLKS2 LRCLKS2 SDOUTS2 OUTPUT Output Low Voltage VOL VDVDDS2 1 65V loi 3mA 0 4 V Output High Voltage VOH VDVDDS2 1 65V 3mA s V VDVDD 2 0V VIN OV 5 5V TA 25 C Input Leakage Current liL high impedance state 1 1 SDA SCL INPUT 0 7 x nput High Voltage VIH DVDD V 0 3 x nput Low Voltage VIL DVDD V nput Hysteresis 210 mV nput Leakage Current lL VDVDD 2 0V VIN OV 5 5V TA 25 C 1 1 Capacitance 10 pF SDA IRQ OUTPUT Output High Current Vout 5 5V 25 C 1 mA 0 2 x Output Low Voltage VOL VDVDD 1 65V IOL 3mA DVDD V AVLAX LAW Maxim Integrated Products 20 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology DIGITAL INPUT OUTPUT CHARACTERISTICS continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V TA 25 C unless otherwise noted Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGMICDATA INPUT nput High Voltage VIH V 0 35 x nput Low Voltage VIL DVDD V nput Hysteresis 125 mV nput Leakage Current IIH liL 2 0V VIN OV 2 0V TA 25 25 25 nput Capacitance 10 pF D
117. Setup Time tSETUP 20 ns LRCLK to BCLK Setup Time tSYNCSET mode 20 ns SDIN to BCLK Hold Time tHOLD 20 ns LRCLK to BCLK Hold Time tSYNCHOLD Slave mode 20 ns inimum Delay Time from LSB BCLK Falling Edge to tHIZOUT Master mode TDM_ 1 42 ns High Impedance State LRCLK Rising Edge to SDOUT SB Delay tSYNCTX CL 1 FSW_ 1 50 ns 1 BCLK rising edge 50 BCLK to SDOUT Del t F CLK to SDOUT Delay CLKTX CL 30p 0 50 ns 1 15 15 Delay Time from BCLK toLRCLK t Master 08 ns y CLKSYNC 0 8x tBCLKL Delay Time from LRCLK to BCLK Master After LSB tENDSYNC moda 1 FSW_ 1 20 ns BCLK tBCLKL ISYNCSET et tou ICLKSYNC HT io 9e T HI Z x LSB HI Z tSETUP HOLD 1 tSETUP HOLD X cus MASTER MODE SLAVE MODE Figure 1 Non TDM Audio Interface Timing Diagrams 0 Maxim Integrated Products 22 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology tBCLK 0 ee IBCLKH lt gt lt gt Ko 2 gt 4 SYNCSET lt gt a tsYNCHOLD LRCLK j NE
118. TH INA pin direct fs 48kHz MODE 1 Dynamic Range Note 4 DR FIR audio 93 dB Total Harmonic Distortion THD N Viu Vbi f 82 74 Noise Gain Error DC accuracy 1 VAVDD 1 65V to 1 95V input referred line inputs unconnected TA 25 C f 217Hz VRIPPLE 200mVp p m AVADC input referred Power Supply Rejection Ratio PSRR dB f 1kHz VRIPPLE 200mVp p 2 AVApC 088 input referred f 10kHz VRIPPLE 200mVp p 088 input referred 57 68 57 Maxim Integrated Products 8 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out loads RLOUT connected from LOUTL or LOUTR to SPKLGND RLOAD RHP ZSPK CREF 2 2UF CMICBIAS CREG CC1N C1P CHPVDD CHPvsS 1HF AVMICPRE_ 200 AVMICPGA_ AVDACATTN AVDACGAIN OdB AVADCLVL AVADCGAIN OdB AVPGAIN_ OdB AVHP_ AVspk OdB MCLK 12 288MHz LRCLK 48kHz MAS TA TMIN to TMAx unless otherwise noted Typical values are at 25 C Note 1
119. TO SPEAKER 100 10 8 120 R 80 68uH z 90 2 80 68uH E 200mVp p E 8 3 80 3 100 RIPPLE ON SPKLVDD 3 SPKRVDD g 80 gt 6 Zspk 40 gt 60 Zspk 40 33uH amp 5 50 60 40 7 m E 40 RIPPLE ON AVDD SPK_VDD 4 40 DVDD HPVDD 30 MCLK 12 288MHz 30 MCLK 12 288MHz 20 LRCLK 48kHz 2 LRCLK 48kHz NI MODE NI MODE 20 10 AVskp 808 10 AVskp 80B 0 0 0 400 800 1200 1600 2000 0 200 400 600 800 1000 1200 1400 1600 10 100 1k 10k 100k 200 600 1000 1400 1800 OUTPUT POWER PER CHANNEL mW FREQUENCY OUTPUT POWER PER CHANNEL mW Maxim Integrated Products 42 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2yF CREG CC1N C1P CHPVDD AVMICPRE_ 209 AVDACGAIN AVADCLVL OGB AVADCGAIN AVPGAIN_ AVHP_ OdB AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted C
120. V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 2yF CREG CC1N C1P CHPVDD CHPvss AVMICPRE_ 208B AVMICPGA_ AVDACATTN AVDACGAIN AVADCLVL OGB AVADCGAIN AVPGAIN_ AVHP_ OdB AVREC AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted GAIN vs FREQUENCY EFFICIENCY vs OUTPUT DAC TO SPEAKER POWER DAC TO SPEAKER 9 ZSPK 80 68 MAX98089 10 68 MAX98089 10669 S _ 70 6 5 8 50 5 40 vbD 4 2V 3 MCLK 12 288MHz 2 LRCLK 48kHz NI MODE 1 AVskp_ 808 00k 0 05 1 0 15 2 0 FREQUENCY OUTPUT POWER PER CHANNEL W EFFICIENCY vs OUTPUT EFFICIENCY vs OUTPUT POWER POWER SUPPLY REJECTION RATIO POWER DAC TO SPEAKER DAC TO SPEAKER vs FREQUENCY DAC
121. VDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL or LOUTR to SPKLGND CREF 2 2uF CMICBIAS CREG 1UF CC1N C1P CHPvss AVMICPRE_ 42088 AVMICPGA_ AVDACATTN AVDACGAIN AVADCLVL AVADCGAIN AVPGAIN_ AVHP_ OdB AVREC AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted INBAND FREQUENCY SPECTRUM OdBFS DAC TO HEADPHONE FFT 60dBFS DAC TO HEADPHONE MCLK 13MHz LRCLK 44 1kHz PLL MODE Rup 320 MAX98089 toc112 AMPLITUDE dBV FREQUE FFT OdBFS DAC TO HEADPHONE MCLK 12 288MHz LRCLK 48kHz MODE Rup 320 MAX98089 toc 114 MCLK 13MHz LRCLK 44 1kHz PLL MODE 320 MAX98089 10113 AMPLITUDE dBV MAX98089 toc1 15 FFT OdBFS DAC HEADPHONE MCLK 12 288 LRCLK 96k Rup 32 Hz Hz MODE Q AMPLITUDE dBV MAALM 8 FREQUENCY kHz 10 12 14 16 18 20 AMPLITUDE AMPLITUDE dBV
122. VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out RLOUT connected from LOUTL LOUTR to SPKLGND CREF 2 21 CMICBIAS CREG CC1N C1P CHPVDD CHPvss AVMICPRE_ 20dB AVMICPGA_ AVDACATTN 098 AVDACGAIN AVADCLVL OGB AVADCGAIN AVPGAIN_ AVHP_ AVREC AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 1 TA 25 C unless otherwise noted Line to Speaker TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE GAIN vs FREQUENCY vs OUTPUT POWER LINE TO SPEAKER vs FREQUENCY LINE TO SPEAKER LINE TO SPEAKER 0 g 5 5 Zspk 80 68H 8 ZspK_ 80 68H 2 25 80 8 40 AVgpK_ 80B E 10
123. VIEW NOTE 7 3 20 BASIC 0 40 BASIC 0 00 BASIC 0 00 BASIC DEPOPULATED PKG CODE BUMPS 6 1 5 1 NONE NOTES Terminal pitch is defined by terminal center to center value Outer dimension is defined by center lines between scribe lines All dimensions in millimeters Marking shown is for package orientation reference only Tolerance is 0 02mm unless specified otherwise All dimensions apply to PbFree package codes only Front side finish can be either Black or Clear TITLE PACKAGE OUTLINE 63 BUMPS WLP PKG 0 4mm PITCH APPROVAL DOCUMENT CONTROL NO 21 0462 Maxim Integrated Products 130 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Revision History REVISION REVISION PAGES NUMBER DATE DESCRIPTION CHANGED 0 6 11 Initial release 4 3 12 Added output offset voltage row to the DAC to Receiver Amplifier Path section in the 13 14 77 Electrical Characteristics table updated the sidetone functions 78 114 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 131 20
124. WER DAC TO SPEAKER 8 0 g g Vspk_vpp 4 2V Vsek 3 7V 5 3 0V 3 MCLK 12 288MHz 10 MCLK 12 288MHz E 10 MCLK 12 288MHz E 2 LRCLK 48kHz E 20 LRCLK 48kHz 20 LRCLK 48kHz NI MODE ODE _ NI MODE 8 30 Zspx_ 4Q amp 30 Zsek 40 amp 30 75 _ 40 AVspK voL 8dB SPK VOL 89 _ 808 40 E 40 E 40 ce a a f 6000Hz 6 f 600092 60 60 70 70 70 0 f 1000Hz E f 100Hz 5 8 80 f 100092 80 80 10092 9 90 9 0 0 5 1 0 15 20 25 0 0 2 04 06 08 10 12 14 16 18 20 0 02 04 06 08 10 12 OUTPUT POWER W OUTPUT POWER OUTPUT POWER W TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY DAC TO SPEAKER vs FREQUENCY DAC TO SPEAKER vs FREQUENCY DAC TO SPEAKER 0 5 8 Vspk_voD 4 2V 3 7V 2 VSPK_VDD 4 2V 2 10 F MCLK 12 288MHz 5 MCLK 12 288MHz 3 1 MCLK 12 288MHz 5 20 LRCLK 48kHz LRCLK 48kHz LRC
125. abled 001 64 x LRCLK 010 48 x LRCLK 011 128 x LRCLK invalid for DHF1 DHF2 1 100 PCLK 2 101 PCLK 4 110 PCLK 8 114 PCLK 16 SEL1 SEL2 DAI1 DAI2 Audio Port Selector Selects which port is used by DAI1 DAI2 00 None 01 Port 51 10 Port 52 11 Reserved Digital Loopthrough Connects the output of the record signal path to the input of the playback path Data input to from an external device is mixed with the recorded audio signal 0 Disabled 1 Enabled 0 16 1 LBEN1 LBEN2 DAI1 DAI2 Digital Audio Interface Loopback LBEN1 routes the digital audio input to back out on DAI2 LBEN2 routes the digital audio input to DAI2 back out on DAI1 Selecting LBEN2 disables the ADC output data 0 Disabled 1 Enabled DMONO1 DMONO2 DAI1 DAI2 DAC Mono Mix Mixes the left and right digital input to mono and routes the combined signal to the left and right playback paths The left and right input data is attenuated by 6dB prior to the mono mix 0 Disabled 1 Enabled MAALM Maxim Integrated Products 81 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 10 Digital Audio Interface Registers continued REGISTER 0x16 0x1E Ox17 0x1F BIT NAME HIZOFF1 HIZOFF2 SDOEN1 SDOEN2 SDIEN 1 SDIEN2 SLOTL1 SLOTL2 DESCRIPTION Disable DAI1 DAI2 Output High Impedance M
126. ak notch fs AVFLT 0x4 500Hz Butterworth tuned for 15 0 0312 8kHz x fs AVFLT 5 fs 240 Butterworth 2 DC Attenuation DCATTEN AVFLT 000 90 dB STEREO AUDIO MODE FIR LOWPASS FILTER MODE1 1 DHF1 0 LRCLK lt 50 2 Ripple limit cutoff 0 43 x fs Passband Cutoff fPLP cutoff 0 48 x fs Hz 6 02 cutoff 0 5 x fs Passband Ripple f fpLP 0 1 40 1 dB Stopband Cutoff 0 58 x fs Hz Attenuation pes 60 dB ADC STEREO AUDIO MODE FIR LOWPASS FILTER MODE1 1 DHF1 1 LRCLK gt 50kHz Ripple limit cutoff 0 208 x fs Passband Cutoff fPLP 3dB cutoff 0 28 x fg Hz Passband Ripple f fpLP 0 1 0 1 dB Stopband Cutoff 0 417 x fs Hz Stopband Attenuation f lt SLP 60 dB Maxim Integrated Products 10 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out loads RLOUT connected from LOUTL or LOUTR to SPKLGND RLOAD RHP ee ee ZSPK ee CREF 2 2 CMICBIAS CREG CC1N C1P CHPVDD CHPVSS 1HF AVMICPRE_ 2088 AVMICPGA_ AVDACATTN OdB AVDACGAIN OdB AVADCLVL AVADCGAIN OdB AVPGAIN_ AVHP_
127. an ade eg ad Det ton ee 73 ADC Record Level Control eee EUREN UY P Cee eRe ACH EH oe oe eres 76 sep c 77 Digital Audio Interfaces 6 hh eee 78 Glock ea oe aah bP Rad add 85 Sample Rate Converter 5 koe beue dox ee ee oe ew ei dote Pew d eed 88 Passband Filtering mssi neg coh says 89 Playback Signal ProCESSING Foes eee he eed baad ds 92 Automatic Level e d en ecu ne or heehee Eod eS 92 Parametric EQUAIIZER v Ree SEA 93 Playback Level Control rereset tereseta rire De REX baled esee eee ee ee ii 95 DAG MIXOES gel tial date MEA aus 96 Receiver AMONG eee boa Gp Ea Oe saa e eee daba ee 97 Receiver Output de ee ede toe hee ed dee M ede feos d RC UR 98 Receiver Output VOlUTTi i i comete wie Patre n aita ics 99 Speaker Amplifiers ewes ____ erue deu err 100 MIXGIS
128. ation Step Size 1 dB DAC Gain Adjust Range AVDACGAIN DV1G 00 to 11 Note 5 0 18 dB DAC Gain Adjust Step Size 6 dB Maxim Integrated Products 11 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out loads RLOUT connected from LOUTL or LOUTR to SPKLGND RLOAD RHP ZSPK CREF 2 2UF CMICBIAS CREG CC1N C1P CHPVDD CHPvsS 1HF AVMICPRE_ 200 AVMICPGA_ AVDACATTN OdB AVDACGAIN OdB AVADCLVL AVADCGAIN OdB AVPGAIN_ AVHP_ OGB AVspK_ OdB MCLK 12 288MHz LRCLK 48kHz MAS 0 TA TMIN to Tmax unless otherwise noted Typical values are at 25 C Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC DIGITAL FILTERS VOICE MODE IIR LOWPASS FILTER 0 Ripple limit cutoff 0 448 x fs Passband Cutoff f H PLP cutoff 0 451 x fs Passband Ripple f lt 0 1 0 1 dB Stopband Cutoff 0 476 x fs Hz Stopband Attenuation Note 6 f gt
129. attenuation or dynamic attenuation based on signal level If the dynamic EQ clip detection is enabled the signal level from the EQ is fed back to the attenuator circuit to determine the amount of gain reduction necessary to avoid clipping Table 17 EQ Registers face for generating the EQ coef are sample rate dependent and through OxB5 ficients The coefficients stored in registers 0x52 REGISTER BIT NAME DESCRIPTION DAH DAI2 EQ Clip Detection A EQCLP1 Automatically controls the EQ attenuator to prevent clipping in the EQ EQCLP2 0 Enabled 1 Disabled DAI1 DAI2 EQ Attenuator 3 Provides attenuation to prevent clipping in the EQ when full scale signals are boosted DVEQ1 DVEQ2 operates only when EQ1EN EQ2EN 1 and EQCLP1 EQ CLP2 1 0x30 0x32 VALUE GAIN dB VALUE GAIN dB 2 0x0 0 0 8 8 DVEQ1 DVEQ2 0x1 1 9 9 0x2 2 OxA 10 1 0x3 3 11 0 4 4 OxC 12 0 5 5 OxD 13 0 0 6 6 14 Ox7 7 OxF 15 7 VS2EN VSEN See the Click and Pop Reduction section 5 ZDEN DAI2 EQ Enable 0x49 1 EQ2EN 0 Disabled 1 Enabled DAH EQ Enable 0 EQ1EN 0 Disabled 1 Enabled Maxim Integrated Products 94 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Playback Level Control allows boost when MODE1 0 and attenuation in any The IC includes separate digital level control for the DAI mode The DAI2
130. clock divider to set the sample rate relative to PCLK This allows high flexibility in both the PCLK and LRCLK frequen cies and can be used in either master or slave mode Exact Integer Mode only In both master and slave modes common MCLK frequencies 12MHz 13MHz 16MHz and 19 2MHz can be programmed to operate in exact integer mode for both 8kHz and 16kHz sample rates In these modes the MCLK and LRCLK rates are selected by using the FREQ bits instead of the NI and PLL control bits DAC Low Power Mode This mode bypasses the PLL for reduce power consumptions and uses fixed counters to generate the clocks The DAC LP bits override the other clock settings REGISTER BIT NAME DESCRIPTION MCLK Prescaler 5 Generates PCLK which is used by all internal circuitry 00 PCLK disabled 0x10 01 10MHz lt MCLK lt 20 MCLK 4 10 20MHz lt MCLK lt 40MHz MCLK 2 11 40MHz lt MCLK lt 60MHz PCLK MCLK 4 DAI1 DAI2 Sample Rate 7 Used by the ALC to correctly set the dual band crossover frequency and the excursion limiter to set the predefined corner frequencies SAMPLE RATE SAMPLE RATE 6 VALUE kHz VALUE kHz 0 0 Reserved 0 8 48 0 11 0 19 SR1 SR2 1 8 Ox9 88 2 0x2 11 025 OxA 96 Ox3 16 OxB Reserved Ox4 22 05 OxC Reserved 0x5 24 OxD Reserved 4 Ox6 32 OxE Reserved Ox7 44 1 OxF Reserved AVLAZCL VI Ma
131. ction section E7 37 INB1 Single Ended Line Input B1 Also negative differential line input B 40 MIC1P Positive Differential Microphone 1 Input AC couple a microphone with a series DIGMICDATA capacitor Can be retasked as a digital microphone data input E9 38 INA2 Single Ended Line Input A2 Also positive differential line input A or negative dif EXTMICN ferential external microphone input F1 3 DGND Digital Ground S2 Digital Audio Bit Clock Input Output BCLKS2 is an input when the IC is in slave F2 2 BCLKS2 mode and an output when in master mode The input output voltage is referenced to DVDDS2 S2 Digital Audio Left Right Clock Input Output LRCLKS2 is the audio sample rate clock and determines whether audio data on S2 is routed to the left or right chan F3 4 LRCLKS2 nel In TDM mode LRCLKS2 is a frame sync pulse LRCLKS2 is an input when the IC is in slave mode and an output when in master mode The input output voltage is referenced to DVDDS2 1 m F4 52 SDA Serial Data Input Output Connect a pullup resistor to DVDD for full output swing F5 51 SCL Serial Clock Input Connect a pullup resistor to DVDD for full output swing F6 49 REG Common Mode Voltage Reference Bypass to AGND with a 1uF capacitor F7 44 MICBIAS Low Noise Bias Voltage Outputs a 2 2V microphone bias An external 2 2kQ resis tor should be placed between MICBIAS and the microphone output 41 MIC1N Negative Differential Microphone 1
132. ctrical Characteristics 104 ev mee be eGo PAG ee Y QE A Reed bre de E dde 6 Digital Input Output Characteristics 0 tees 19 Clock Characteristics Blass tos pem o epe do atate due dac d 21 Audio Interface Timing Characteristics 22 Digital Microphone Timing gat eee 23 1 12015 22 71 22 see ERI Pos eee aos he ede eee es 24 Power Consumption o oe be ee o ge ey 25 Typical Operating Characteristics kam e ieee ere quse ave EO E oed nde 4 28 MicropnonetO ADC 94 aq deu d xd cadet 28 Blur o 32 Ling In Pin Directto ADG Gr db _ ____ _ A 33 Digital LOO DDaCKu ta aun DAL Gar eee Be 33 Analog Lace he d dedos acl Ut eee RL Ae dood 34 DAC TO RECEIVER oon RS Gude te ed the EH bg eed Te 35 LINGO dive dete nanan Ghd Sob o iol ok ae d dt Ed 37 QUEDUE is ax oen e ee eared _____________________ _ 38 ineto Line Outputs hei he eee ee E RR UG HUS ue bw
133. d Pop Level 32 samples per second dBV AVsPK Out of shutdown 66 MIC INPUT TO SPEAKER AMPLIFIER PATH Dynamic Range Note 4 DR Referenced to full scale output level AVSPK_ 098 82 dB oe Distortion THD N f 1kHz Pour 200 RL 82 68uH 71 dB Peak voltage A weighted 32 Into shutdown 55 Click and Pop Level samples per second AVSPK_ dBV OdB Out of shutdown 52 SPEAKER AMPLIFIER f 1kHz VSPKLVDD VSPKRVDD 5 0V 2950 THD 10 VSPKLVDD VSPKRVDD 4 2V 2060 ZSPK 40 VSPKLVDD VSPKRVDD 3 7V 1570 33H VSPKLVDD VSPKRVDD 3 0V 1000 f 1kHz VSPKLVDD VSPKRVDD 5 0V 2320 THD 1 VSPKLVDD VSPKRVDD 4 2V 1620 ZSPK 40 VSPKLVDD VSPKRVDD 3 7V 1240 33H V V 3 0V 785 Output Power POUT 882000 SPKRVDD 2 mW f 1kHz VSPKLVDD VSPKRVDD 5 0V 730 THD 10 VSPKLVDD VSPKRVDD 4 2V 1210 ZSPK 80 VSPKLVDD VSPKRVDD 3 7V 930 VSPKLVDD VSPKRVDD 3 0V 600 f 1kHz VSPKLVDD VSPKRVDD 5 0V 1365 THD 1 VSPKLVDD VSPKRVDD 4 2V 955 ZSPK 80 VSPKLVDD VSPKRVDD 3 7V 735 68H VSPKLVDD VSPKRVDD 3 0V 475 Full Scale Output Note 7 2 VRMS SPVOLL SPVOLR 0x00 62 Volume Control AV Note 5 dB 3 SPK SPVOLL SPVOLR Ox1F MAXIM Maxim Integrated Products 15 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker
134. desired X Maxim Integrated Products 79 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 10 Digital Audio Interface Registers REGISTER BIT NAME DESCRIPTION MAS1 MAS2 DAI1 DAI2 Master Mode In master mode DAI1 DAI2 outputs LRCLK and BCLK In slave mode DAI1 DAI2 accept LRCLK and BCLK as inputs 0 Slave mode 1 Master mode 0x14 0x1C MAALM WCI1 WCl2 BCI1 BCI2 DLY1 DLY2 TDM1 TDM2 FSW1 FSW2 WS1 WS2 DAI1 DAI2 Word Clock Invert TDM1 TDM2 0 O Left channel data is transmitted while LRCLK is low 1 Right channel data is transmitted while LRCLK is low TDM1 TDM2 1 Always 0 DAI1 DAI2 Bit Clock Invert BCI1 BCI2 must be set to 1 when TDM1 TDM2 1 0 SDIN is accepted on the rising edge of BCLK SDOUT is valid on the rising edge of BCLK 1 SDIN is accepted on the falling edge of BCLK SDOUT is valid on the falling edge of BCLK Master Mode O LRCLK transitions on the falling edge of BCLK 1 2 LRCLK transitions on the rising edge of BCLK DAI1 DAI2 Data Delay DLY1 DLY2 has no effect when TDM1 TDM2 1 0 The most significant data bit is clocked on the first active BCLK edge after an LRCLK transition 1 The most significant data bit is clocked on the second active BCLK edge after an LRCLK transition DAI1 DAI2 Time Division Multiplex Mode TDM Mode Set TDM1 TDM2 w
135. duration of the transition The bypass capacitor on PVDD supplies the required current and prevents droop on PVDD The charge pump s dynamic switching mode can be turned off through the 12C interface The charge pump can then be forced to output either x PVDD 2 or xPVDD regardless of input signal level Maxim Integrated Products 107 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology CONVENTIONAL AMPLIFIER BIASING SCHEME DirectDrive AMPLIFIER BIASING SCHEME Figure 28 Traditional Amplifier Output vs DirectDrive Output OUTPUT VOLTAGE Figure 29 Class H Operation MAXIM Class H Operation A Class H amplifier uses a Class AB output stage with power supplies that are modulated by the output signal In the case of the ICs two nominal power supply differ entials of 1 8V 0 9V to 0 9V and 3 6V 1 8V to 1 8V are available from the charge pump Figure 29 shows the operation of the output voltage dependent power supply Headphone Ground Sense HPSNS HPSNS senses the ground return for the headphone load For optimal performance connect HPSNS to the ground pole of the jack through an isolated trace as shown in Figure 30 If HPSNS is not used connect to the analog ground plane CONFIGURATION FOR OPTIMAL PERFORMANCE HEADPHONE JACK HEADPHONE JACK Figure
136. during the master generated 9th SCL pulse The second byte transmitted from the master configures the IC s internal register address pointer The pointer tells the IC where to write the next byte of data An acknowl edge pulse is sent by the ICs upon receipt of the address pointer data The third byte sent to the ICs contains the data that is writ ten to the chosen register An acknowledge pulse from the ICs signals receipt of the data byte The address pointer autoincrements to the next register address after each received data byte This autoincrement feature allows a master to write to sequential registers within one continu ous frame The master signals the end of transmission by issuing a STOP condition Register addresses greater than OxC7 are reserved Do not write to these addresses Read Data Format Send the slave address with the R W bit set to 1 to initi ate a read operation The IC acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse A START command followed by a read com mand resets the address pointer to register OxOO ACKNOWLEDGE FROM MAX98089 E ACKNOWLEDGE FROM MAX98089 1 The first byte transmitted from the ICs is the content of register 0 00 Transmitted data is valid on the rising edge of SCL The address pointer autoincrements after each read data byte This autoincrement feature allows all registers to be read sequentially within one continuous frame A STOP condition can
137. e as Speaker Power Limiter well as support for two PDM digital microphones Integrated Speaker Distortion Limiter switches allow for an additional microphone input as well Microphone Automatic Gain Control as microphone signals to be routed out to external devices and Noise Gate Two flexible single ended or differential line inputs may be Dual I2S PCM TDM Digital Audio Interfaces connected to an FM radio or other sources Asynchronous Digital Mixing Integrated FlexSound technology improves loudspeak 9 Supports Master Clock Frequencies from 10MHz er performance by optimizing the signal level and fre to 60MHz quency response while limiting the maximum distortion RF Immune Analog Inputs and Outputs and power at the output to prevent speaker damage Extensive Click and Pop Reduction Circuitry Automatic gain control AGC and a noise gate optimize Available in 63 Bump WLP Package 3 80mm x the signal level of microphone input signals to make best 3 30mm 0 4mm Pitch and 56 Pin TQFN Package use of the ADC dynamic range 7mm x 7mm x 0 75mm The device is fully specified over the 40 C to 85 C Ordering Information appears at end of data sheet extended temperature range For related parts and recommended products to use with this part FlexSound is a trademark of Maxim Integrated Products Inc refer to www maxim ic com MAX98089 related Simplified Block Diagram 25 VS PCM DS RECEIVER LINEOUT AMPS DIGITAL DIG
138. e from minimum to the programmed value at turn on and back to minimum at 6 VSEN turn off 0 Enabled oxar 1 Disabled Applies to volume changes in HPVOLL HPVOLR RECVOL SPVOLL and SPVOLR Zero Crossing Detection Holds volume changes until there is a zero crossing in the audio signal This reduces click and pop during volume changes zipper noise If no zero crossing is detected 5 ZDEN within 100ms the volume change is forced 0 Enabled 1 Disabled Applies to volume changes in PGAM1 PGAM2 PGAOUTA PGAOUTB PGAOUTC HPVOLL HPVOLR RECVOL SPVOLL and SPVOLR See the 5 Band tric EQ secti 0 EQ1EN ee the 5 Band Parametric EQ section MAAXLAVI Maxim Integrated Products 113 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Jack Detection The IC features jack detection that can detect the insertion and removal of a jack as well as the load type When a jack is detected an interrupt on IRQ can be triggered by set ting to alert the microcontroller of the event Figure 33 shows the typical configuration for jack detection Jack Insertion To detect a jack insertion the IC must have a power sup ply Set JDETEN to enable jack detection circuitry and apply a pullup current to JACKSNS Set JDWK to mini mize supply current Jack insertion can be performed in shutdown or out of shutdown Clear JDWK to differentiate between headsets with a microphone and headphones without a microphone The vo
139. e routed out the third microphone input to an external device This eliminates the need for an external analog switch in systems that have two devices recording signals from the same microphone Through two digital audio interfaces the device can transmit one stereo audio signal and receive two stereo audio signals in wide range of formats including 125 PCM and up to four mono slots in TDM Each interface can be connected to either of two audio ports 51 and 52 for communication with external devices Both audio interfaces support 8kHz to 96kHz sample rates Each input signal is independently equalized using 5 band parametric equalizers A multiband automatic level con trol ALC boosts signals by up to 12dB One signal path additionally supports the same voiceband filtering as the ADC path The IC includes a stereo Class D speaker amplifier a high efficiency Class H stereo headphone amplifier and a differential receiver amplifier that can be configured as a single ended stereo line output When the receiver amplifier is disabled analog switches allow RECP RXINP and RECN RXINN to be reused for signal routing In systems where a single transducer is used for both the loudspeaker and receiver an exter nal receiver amplifier can be routed to the left speaker through RECP RXINP and RECN RXINN bypassing the Class D amplifier If the internal receiver amplifier is used then leave RECP RXINP and RECN RXINN unconnected
140. e set when 12 DAC LP 0000 0 Disabled 1 Enabled DAI1 DAC Input Dither 1 Enable 2 DACHDITHEN DACTDITHEN is recommended to be set when LP 0000 0 Disabled 1 Enabled 0x50 DAI2 Clock Gen Module Enable CGM1_EN has to be set along with CGM2 EN to enable the clock generation for the 1 CGM2 EN DAI2 DAC playback path 0 Disabled 1 2 Enabled DAI1 Device Clock Gen Module Enable CGM1_EN enables the device clock generation and needs to be set for DAC playback 0 CGM1_EN or ADC record 0 Disabled 1 Enabled Maxim Integrated Products 87 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 12 Common NI1 NI2 Values LRCLK kHz PCLK MHz DHF1 2 0 DHF1 2 1 8 11025 12 16 2205 24 32 44 1 48 64 88 2 96 10 1349 1818 107 2752 3631 4 5 6C61 75F7 6061 75 7 11 11 0 18A2 1ACF 2 3144 59 477E 6287 6 477E 6287 6 11 2896 116A 1800 1 1 2204 3000 343F 4549 6000 6870 4549 6000 6870 12 1062 1694 1893 20C5 2029 3127 4189 5451 624E 4189 5A51 624E 12 288 1000 1600 1800 2000 2CiA 3000 4000 5833 6000 4000 5833 6000 13 20 1408 16 29 2052 7 5352 3C7F 5352 16 4 10EF 126F 1893 21DE 2400 3127 4380 49BA
141. ed in the voice coil is transferred to the speaker s magnet which transfers heat to the surrounding air For the voice coil to overheat both the voice coil and the magnet must overheat The result is that a loudspeaker can operate above its rated power for a significant time before it heats sufficiently to cause damage Table 25 Power Limiter Registers The IC s power limiter includes user programmable time constants and power thresholds to match a wide range of loudspeakers Program the power limiter s threshold to match the loudspeaker s rated power handling This can be determined through measurement or the loudspeak er s specification Program time constant 1 to match the voice coil s thermal time constant Program time constant 2 to match the magnet s thermal time constant The time constants can be determined by plotting the voice coil s resistance vs time as power is applied to the speaker REGISTER BIT NAME DESCRIPTION Power Limiter Threshold If the continuous output power from the speaker amplifiers exceeds this threshold 7 the output is briefly muted to protect the speaker The threshold is measured in watts assuming an 8Q load VBAT must correctly reflect the voltage of SPKLVDD SP KRVDD to achieve accurate thresholds VALUE THRESHOLD VALUE THRESHOLD W W 0x8 0 27 Ox1 0 05 Ox9 0 35 5 0x2 0 06 OxA 0 48
142. es VTH RL ee pios V Modes VOUT Rising Transi tion from Split to Invert Mode Full Scale Output Note 7 1 VRMS Volume Control AV Note 5 HPVOL_ 3 3dB to 1dB 0 5 1dB to 5d0B 1 Volume Control Step Size 588 to 19dB 2 19dB to 43dB 3 43dB to 67dB 4 Mute Attenuation f 1kHz 100 dB TA 25 C 0 1 1 Output Offset Voltage Vos AVHP_ 67dB mV TA TMIN to TMAX 3 a RHP 320 500 Capacitive Drive Capability No sustained oscillations pF SPEAKER BYPASS SWITCH ISPKL_ 100 SPKBYP 1 On Resistance R 2 8 ON Vrxin_ OV VSPKLVDD m VIN 2VP P VSPKLVDD 2 100 60 oo Distortion THD N ZspK 80 68uH f 1kHz dB SPKBYP 1 Rs 0Q 60 VIN 2VP P VCM VSPKLVDD 2 Off Isolation ZepK 6 f TkHz 96 dB Off Leakage Current VRXIN_ VsPKLVDD 20 20 MAXIM Maxim Integrated Products 18 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out loads RLOUT connected from LOUTL or LOUTR to SPKLGND RLOAD RHP ee ee ZSPK ee CREF 2 2 CMICBIAS CREG CC1N C1P
143. fferential microphone inputs and a low noise microphone bias for powering the micro phones Figure 6 One microphone input can also be con figured as a digital microphone input accepting signals from up to two digital microphones Any two microphones analog or digital can be recorded simultaneously In the typical application one microphone input is used for the handset microphone and the other is used as an accessory microphone In systems using a background noise microphone INA can be retasked as another microphone input In systems where the codec is not the only device recording microphone signals connect microphones to MIC2P MIC2N and EXTMICP EXTMICN MIC1P MIC1N then become outputs that route the microphone signals to an external device as needed Two devices can then record microphone signals without needing external analog switches Analog microphone signals are amplified by two stages of gain and then routed to the ADCs The first stage offers selectable OdB 20dB or 30dB settings The second stage is a programmable gain amplifier PGA adjustable from to 2088 in 1dB steps To maximize the signal to noise ratio use the gain in the first stage whenever possible Zero crossing detection is included on the PGA to minimize zipper noise while making gain changes MICBIAS MICTP DIGMICDATA MICTN DIGMICCLK EXTMIC PATEN 0 20 3008 EXTMIC PA2EN 0 20 304
144. gram MAKILA Maxim Integrated Products 72 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 5 ADC Input Mixer Register REGISTER BIT NAME DESCRIPTION T Left Right ADC Input Mixer 6 Selects which analog inputs are recorded by the left right ADC 1 MIC 1 1 MIC2 2 MIXADL MIXADR 1999 INST pin direct 3 1 INA2 pin direct 2 1 INA1 1 INA2 INADIFF 0 or INA2 INADIFF 1 1 1 INB 1 0 1 INB2 INBDIFF 0 or INB2 INB1 INBDIFF 1 Record Path Signal Processing The device s record signal path includes both automatic gain control AGC for the microphone inputs and a digi tal noise gate at the output of the ADC Figure 10 Microphone AGC The IC s AGC monitors the signal level at the output of the ADC and then adjusts the MIC1 and MIC2 analog PGA settings automatically When the signal level is below the predefined threshold the gain is increased up to its maximum 20dB If the signal exceeds the threshold the gain is reduced to prevent the output signal level exceeding the threshold When AGC is enabled the microphone PGA is not user programmable The AGC provides a more constant signal level and improves the available ADC dynamic range PGAM1 420dB 69 AUTOMATIC GAIN CONT
145. hen communicating with devices that use a frame synchronization pulse on LRCLK instead of a square wave 0 Disabled 1 Enabled 1 12 must be set 1 DAI1 DAI2 Wide Frame Sync Pulse Increases the width of the frame sync pulse to the full data width when TDM1 TDM2 1 FSW1 FSW2 has no effect when TDM1 TDM2 0 0 Disabled 1 Enabled DAH DAI2 Audio Data Bit Depth Determines the maximum bit depth of audio being transmitted and received Data is always 16 bit when TDM1 TMD2 0 0 16 bits 1 24 bits Maxim Integrated Products 80 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 10 Digital Audio Interface Registers continued REGISTER BIT NAME DESCRIPTION OSR1 ADC Oversampling Ratio Use the higher setting for maximum performance Use the lower setting for reduced power consumption at the expense of performance 00 96x 01 64x 10 Reserved 11 Reserved DAC_OSR1 DAC_OSR2 DAC Oversample Clock Select PCLK 2 for higher performance Select PCLK 4 for lower power consumption 1 DAC input clock PCLK 2 0 DAC input clock PCLK 4 0x15 0x1D BSEL1 BSEL2 DAI1 DAI2 BCLK Output Frequency When operating in master mode BSEL1 BSEL2 set the frequency of BCLK When operating in slave mode BSEL1 BSEL2 have no effect Select the lowest BCLK frequency that clocks all data input to the DAC and output by the ADC 000 BCLK dis
146. ier and can decrease efficiency and THD N performance The traditional PWM scheme uses large differential output swings 2 x VDD peak to peak and causes large ripple currents Any parasitic resistance in the filter components results in a loss of power lowering the efficiency The IC does not require an output filter The device relies on the inherent inductance of the speaker coil and the natural filtering of both the speaker and the human ear to recover the audio component of the square wave out put Eliminating the output filter results in a smaller less costly more efficient solution Because the frequency of the IC s output is well beyond the bandwidth of most speakers voice coil movement due to the square wave frequency is very small Although this movement is small a speaker not designed to handle the additional power can be damaged For optimum results use a speaker with a series inductance gt 10pH Typical 8Q speakers exhibit series inductances in the 20yH to 100pH range RF Susceptibility GSM radios transmit using time division multiple access TDMA with 217Hz intervals The result is an RF signal with strong amplitude modulation at 217Hz and its har monics that is easily demodulated by audio amplifiers The IC is designed specifically to reject RF signals how ever PCB layout has a large impact on the susceptibility of the end product Table 38 Example Startup Sequence In RF applications improveme
147. ieve the correct center frequency for each playback path 0 Single band ALC 1 Dual band ALC Low Signal Threshold 2 Selects the minimum signal level to be boosted by the ALC 000 low signal threshold disabled 001 12dB 010 18dB ACGIH 011 24dB 100 30dB 101 0 110 42dB 111 48dB Parametric Equalizer The parametric EQ contains five independent biquad filters with programmable gain center frequency and bandwidth Each biquad filter has a gain range of 12dB and a center frequency range from 20Hz to 20kHz Use a filter Q less than that shown in Figure 22 to achieve ideal frequency responses Setting a higher Q results in non ideal frequency response The biquad filters are series connected allowing a total gain of 60dB ui a a wo gt gt lt 00 10 000 00 000 ER FREQUENCY Hz Figure 22 Maximum Recommended Filter vs Frequency IVI Maxim Integrated Products 93 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology The MAX98089 EV kit software includes a graphical inter Use the attenuator at the EQ s input to avoid clipping the signal The attenuator can be programmed for fixed
148. ingle ended inputs DAC Playback to Class D Speaker DAC Playback 48kHz Stereo SPK DAC gt 2 31 0 00 6 33 2 14 0 01 31 44 92 24 bit music filters Maxim Integrated Products 26 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Power Consumption continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V MAS 0 MODE lAVDD IPVDD ee IDVDD puru POWER DYNAMIC mA mA mA mA mA mW RANGE dB DAC Playback 48kHz Mono SPK DAC 1 35 0 00 3 23 1 84 0 01 17 69 92 24 bit music filters Line Playback Mono SPK NA gt SPKL 1 01 0 00 3 24 0 03 0 00 13 83 93 Differential inputs Full Duplex Full Duplex 8kHz Mono RCV IC1 ADC Record 93 DAC REC 6 32 0 00 1 54 1 24 0 01 19 33 Playback 94 16 bit voice filters Full Duplex 8kHz Stereo HP IC1 2 gt ADC DAC gt HP 16 bit mixer voice filters Record 93 11 19 1 27 0 48 1 28 Playback 96 0 01 26 43 Full Duplex 8kHz Stereo HP MIC1 2 ADC DAC HP 16 bit low power mode voice filters Record 93 7 12 0 47 0 48 1 10 Playback 96 0 02 17 44 Line Record Line Stereo Record 48kHz INA gt ADC 6 19 0 00 0 20 1 31 24 bit low power music filters Line Stereo Record 48kHz INA gt ADC Direct pin input 24bit low power music filters 0 15 14 47 91 5 69 0 00 0 20 1 31 0 12 13 53
149. itive numbers Store a1 and a2 as negated two s complement numbers Separate filters can be stored for the DAI1 and DAI2 playback paths ff EXCURSION LIMITER Figure 27 Speaker Amplifier Signal Processing Block Diagram MAALM The MAX98089 EV kit software includes a graphic interface for generating the user programmable biquad coefficients Note Only change the excursion limiter settings when the signal path is disabled to prevent undesired artifacts SPVOLL 484 TO 62dB 4648 SPLEN Y POWER DISTORTION LIMITER SPVOLR 8dB TO 62dB Maxim Integrated Products 103 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 24 Excursion Limiter Registers REGISTER BIT NAME DESCRIPTION Excursion Limiter Corner Frequency 6 The excursion limiter has limited sliding range and minimum corner frequencies Listed below are all the valid filter combinations LOWER CORNER UPPER CORNER MINIMUM BIQUAD COR 5 FREQUENCY FREQUENCY NER FREQUENCY DHPLCF DHPUCF Excursion limiter disabled 000 00 400Hz 001 00 600Hz 010 00 4 800Hz 011 00 1kHz 100 00 41 Programmable using biquad 100Hz 000 11 1 200Hz 400Hz 001 01 400Hz 600Hz 010 10 400Hz 800Hz 011 10 Programmable us DHPLCF ing biquad 400Hz
150. lewing breaks up large volume changes into the smallest available step size and the steps through each step between the initial and final volume setting When Table 30 Click and Pop Reduction Register enabled volume slewing also occurs at device turn on and turn off During turn on the volume is set to mute before the output is enabled Once the output is on the volume ramps to the desired level At turn off the volume is ramped to mute before the outputs are disabled When there is no audio signal zero crossing detection can prevent volume slewing from occurring Enable enhanced volume slewing to prevent the volume control ler from requesting another volume level until the previ ous one has been set Each step in the volume ramp then occurs after a zero crossing has occurred in the audio signal or the timeout window has expired During turn off enhance volume slewing is always disabled REGISTER BIT NAME DESCRIPTION Enhanced Volume Smoothing During volume slewing the controller waits for each step in the ramp to be applied be fore sending the next step When zero crossing detection is enabled this prevents large T VS2EN steps in the output volume when no zero crossings are detected 0 Enabled 1 Disabled Applies to volume changes in HPVOLL HPVOLR RECVOL SPVOLL and SPVOLR Volume Adjustment Smoothing Volume changes are smoothed by stepping through intermediate steps Also ramps the volum
151. loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out loads RLOUT connected from LOUTL or LOUTR to SPKLGND RLOAD RHP ZSPK CREF 2 2UF CMICBIAS CREG CC1N C1P CHPVDD 55 1HF AVMICPRE_ 200 AVMICPGA_ AVDACATTN OdB AVDACGAIN OdB AVADCLVL AVADCGAIN OdB AVPGAIN_ AVHP_ AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS TA TMIN to TMAx unless otherwise noted Typical values are at TA 25 C Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VOICE MODE IIR HIGHPASS FILTER MODE1 0 AVFLT 0 1 Elliptical tuned for fs 16kHz 0 0161 217Hz notch X TS AVFLT 0x2 500Hz Butterworth tuned for fs 0 0319 16kHz x fs Passband Cutoff AVFLT 0x3 Elliptical tuned for fs 8kHz 217Hz 0 0321 Hz 3dB from Peak notch x fs AVFLT 0 4 500Hz Butterworth tuned for fs 0 0632 8kHz xfs AVFLT 0x5 fs 240 Butterworth po AVFLT 0 1 Elliptical tuned for fs 16kHz 0 0139 217Hz notch x fs AVFLT Ox2 500Hz Butterworth tuned for fs 0 0156 16 2 x fs Stopband Cutoff AVFLT 0x3 Elliptical tuned for fs 8kHz 217Hz 0 0279 Hz 0 from Pe
152. ltage on JACKSNS is equal to SPKLVDD as long as no load is applied to JACKSNS and MICBIAS is disabled Table 31 shows the change in JKSNS that occurs when a jack is inserted Accessory Button Detection After jack insertion the MAX98089 can detect button presses on accessories that include a microphone and a switch that shorts the microphone signal to ground Set JDETEN to enable jack detection circuitry Button presses can be detected both when MICBIAS is enabled and disabled Table 32 shows the change in JKSNS that occurs when the accessory button is pressed Jack Removal The IC detects jack removal by monitoring JACKSNS for transitions to the 11 state Set JDETEN to enable jack detection circuitry Set JDWK to minimize supply current if button detection is not required Table 33 shows the change in JKSNS that occurs when a jack is removed Jack removal can be done in shutdown or out of shutdown JACKSENSE MICBIAS 22 L MiC2P 11 HPL HPR Figure 33 Typical Configuration for Jack Detection Table 31 Change in JKSNS Upon Jack Insertion JACK TYPE JDWK 1 JDWK 0 5 JKSNS 11 gt 00 JKSNS 11 gt 00 JKSNS 11 gt 00 JKSNS 11 gt 01 Table 32 Change in JKSNS Upon Button Press JACK TYPE MICBIAS ENABLED OR DISABLED GND HPR HPL JKSNS 01 00 AVLAZCLAW Ma
153. me S ALCRLS 000 4 POWER LIMITER Attenuation 64 dB ZSPK 80 VSP PWRTH 1 0 08 Threshold KLVDD VSPKRVDD 5 5V W AVSPK_ 8dB PWRTH OxF 1 23 Time Constant 1 t PM 23 5 i PWR 8 7 PWRT2 1 to OxF 0 5 me i i PWR2 PWRT2 8 7 Weighting Factor PWRK 000 to 111 12 5 100 DISTORTION LIMITER THDCLP 1 lt 1 Distortion Limit THDCLP OxF 24 THDT1 000 0 76 Release Time Constant 5 THDT1 111 6 2 MAXIM Maxim Integrated Products 16 12 288MHz LRCLK 48kHz MAS TA TMIN to TMAx unless otherwise noted Typical va MAX98089 Low Power Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected from HPL or HPR to HPGND Line out loads RLOUT connected from LOUTL or LOUTR to SPKLGND RLOAD RHP ee ee ZSPK ee CREF 2 2 CMICBIAS CREG CC1N C1P CHPVDD CHPVSS 1HF AVMICPRE_ 2088 AVMICPGA_ OdB AVDACGAIN OdB AVADCLVL AVADCGAIN OdB AVPGAIN_ OdB AVHP_ AVREC AVspK_ OdB MCLK ues are at TA 25 C Note 1
154. nnel Maxim Integrated Products 96 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Receiver Amplifier The IC includes a single differential receiver amplifier The receiver amplifier is designed to drive a 320 earpiece speaker In cases where a single transducer is used for the loudspeaker and receiver use the SPKBYP switch to route the receiver amplifier output to the left soeaker outputs The receiver amplifier can also be configured as stereo single ended line outputs using the 12C interface RECVOLL 8dB TO 6208 IX gt RECLEN XRECL RECVOLR 8dB TO 6208 gt gt EMODE RECREN o Figure 25 Receiver Amplifier Block Diagram MAKILA Maxim Integrated Products 97 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Receiver Output Mixer The IC s receiver amplifier accepts input from the stereo DAC the line inputs single ended or differential and the MIC inputs Configure the mixer to mix any combination of the available sources When more than one signal is selected the mixed signal can be configured to attenuate 9dB or 12dB Table 20 Receiver Output Mixer Register REGISTER m NAME DESCRIPTION 0x28 MIXRECL Left Receiver Output Mixer 1xxxxxxx Right DAC 1
155. not exceed the programmed THD N limit The distortion limiter analyzes the Class D output duty cycle to determine the percentage of the waveform that is clipped If the distortion exceeds the programmed threshold the output gain is reduced Maxim Integrated Products 106 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 26 Distortion Limiter Registers REGISTER BIT NAME DESCRIPTION 7 Distortion Limit Measured in THD N 6 VALUE THD N LIMIT VALUE THD N LIMIT 0x0 Limiter disabled 0x8 12 Ox1 lt 1 0 9 14 5 THDCLP Ox2 1 OxA 16 Ox3 2 OxB 18 0x46 Ox4 4 OxC 20 4 0x5 6 OxD 21 0x6 8 OxE 22 Ox7 10 OxF 24 Distortion Limiter Release Time Constant Duration of time required for the speaker amplifier s output gain to adjust back to the 0 THDT1 nominal level after a large signal has passed 1 45 1 2 85 Headphone When the input signal level is less than 10 of PVDD DirectDrive Headphone Amplifier Traditional single supply headphone amplifiers have outputs biased at a nominal DC voltage typically half the supply Large coupling capacitors are needed to block this DC bias from the headphone Without these capacitors a significant amount of DC current flows to the headphone resulting in unnecessary power dis sipation and possible damage to both headphone and headphone amplifier Maxim s second generation DirectDrive architecture
156. nts to both layout and com ponent selection decrease the IC s susceptibility to RF noise and prevent RF signals from being demodulated into audible noise Trace lengths should be kept below 1 4 of the wavelength of the RF frequency of interest Minimizing the trace lengths prevents them from functioning as anten nas and coupling RF signals into the IC The wavelength in meters is given by c f where c x 108 m s and f the RF frequency of interest Route audio signals on middle layers of the PCB to allow ground planes above and below to shield them from RF interference Ideally the top and bottom layers of the PCB should primarily be ground planes to create effec tive shielding Additional RF immunity can also be obtained by rely ing on the self resonant frequency of capacitors as it exhibits a frequency response similar to a notch filter Depending on the manufacturer 10pF to 20pF capaci tors typically exhibit self resonance at the RF frequencies of interest These capacitors when placed at the input pins can effectively shunt the RF noise to ground For these capacitors to be effective they must have a low impedance low inductance path to the ground plane Avoid using microvias to connect to the ground plane whenever possible as these vias do not conduct well at RF frequencies Startup Shutdown Sequencing To ensure proper device initialization and minimal click and pop program the IC s SHDN 1 after c
157. o VHPVDD 0 REF MIGBIAS oie MCLK SDINS1 SDINS2 JACKSNS SDA SCL IRO 0 3V to 6 0V LRCLKS1 BCLKS1 SDOUTS1 LRCLKS2 BCLKS2 SDOUTS2 0 3V to VSPKLVDD 0 3V 0 3V to VbVDDS1 0 3V 0 3V to 0 3V REG INA1 EXTMICP INA2 EXTMICN INB1 INB2 MIC1P DIGMICDATA MIC1N DIGMICCLK 2 2 oer ences 0 3V to 2 2V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional opera tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS FIRGNS VHPGND 0 3V to VHPGND 0 3V APL HPR VHPVSS 0 3V to VHPVDD 0 3V RECP LOUTL RXINP RECP LOUTR RXINN 2 VSPKLGND 0 3V to VSPKLVDD 0 3V SPKLP SPKLN VSPKLGND 0 3V to VSPKLVDD 0 3V SPKRP SPKRN VSPKRGND 0 to VSPKRVDD 0 3V Continuous Power Dissipation TA 70 C 63 WLP derate 25 6mW C above 70 2 05W 56 TQFN derate 40mW C above 70 3 2W Operating Temperature 40 C to 85 C Storage Temperature
158. ode Normally SDOUT is set high impedance between data words Set HIZOFF1 HIZOFF2 to force a level on SDOUT at all times 0 Disabled 1 Enabled DAI1 DAI2 Record Path Output Enable DAI2 outputs data only if LBEN1 1 0 Disabled 1 Enabled DAI1 DAI2 Playback Path Input Enable 0 Disabled 1 Enabled TDM Left Time Slot Selects which of the four slots is used for left data on DAI1 DAI2 If the same slot is selected for left and right audio left audio is placed in the slot 00 Slot 1 01 Slot 2 10 Slot 3 11 Slot 4 SLOTR1 SLOTR2 TDM Right Time Slot Selects which of the four slots is used for right data on DAI1 DAI2 If the same slot is selected for left and right audio left audio is placed in the slot 00 Slot 1 01 Slot 2 10 Slot 3 11 Slot 4 SLOTDLY1 SLOTDLY2 TDM Slot Delay Adds 1 BCLK cycle delay to the data in the specified TDM slot 1xxx Slot 4 delayed 1 Slot 3 delayed xx1x Slot 2 delayed xxx1 Slot 1 delayed Maxim Integrated Products 82 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology WCI_ 0 BCI_ 0 DLY_ 0 TDM_ 0 FSW_ 0 WS lt 0 HIZOFF_ 1 SLOTL_ 0 SLOTR_ 0 LRCLK LEFT RIGHT SDOUT NA 050044 4 11 oe o7 oo lt lt 2550 4 0 010 08 oe FATAL KLELELELELELELELELELELRLELELEL LT LEE ELELE
159. one amplifier HPSNS senses ground noise on the headphone jack and adds the same noise to the output audio signal thereby making the output headphone output minus ground noise free Connect HPSNS to the headphone jack shield to ensure accurate pickup of headphone ground noise Bypass SPKLVDD and SPKRVDD to SPKLGND and SPKRGND respectively with as little trace length as possible Connect SPKLP SPKLN SPKRP and SPKRN to the stereo speakers using the shortest traces pos sible Reducing trace length minimizes radiated EMI Route SPKLP SPKLN and SPKRP SPKRN as differential pairs on the PCB to minimize loop area thereby the inductance of the circuit If filter components are used on the speaker outputs be sure to locate them as close as possible to the IC to ensure maximum effectiveness Minimize the trace length from any ground connected passive components to SPKLGND and SPKRGND to further minimize radiated EMI Maxim Integrated Products 126 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Route microphone signals from the microphone to the ICs as a differential pair ensuring that the positive and nega tive signals follow the same path as closely as possible with equal trace length When using single ended micro phones or other single ended audio sources ground the negative microphone input as close as possible to the audio source and then treat the positive and negative traces as differential pairs
160. onfiguring all registers Table 38 lists an example startup sequence for the device To shut down the IC simply set SHDN O SEQUENCE DESCRIPTION REGISTERS 1 Ensure SHDN 0 Ox51 2 Configure clocks 0x10 to 0x13 0x19 to Ox1B 3 Configure digital audio interface 0x14 to 0x17 Ox1C to Ox1F 4 Configure digital signal processing 0x18 0x20 Ox3F to 0x46 5 Load coefficients 0x52 to OxC9 6 Configure mixers 0x22 to Ox2D 7 Configure gain and volume controls Ox2E to 8 Configure miscellaneous functions 0x47 to 4 9 Enable desired functions 0 4 0x50 10 Set SHDN 1 0x51 AVLAZCL VI Maxim Integrated Products 123 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Many configuration options in the ICs can be made while the devices are operating however some regis ters should only be adjusted when the corresponding audio path is disabled Table 39 lists the registers that are sensitive during operation Either disable the cor responding audio path or set SHDN 0 while changing these registers Component Selection Optional Ferrite Bead Filter In applications where speaker leads exceed 20mm additional EMI suppression can be achieved by using a filter constructed from a ferrite bead and a capacitor to ground Figure 42 Use a ferrite bead with low DC resis tance high frequency gt 600MHz impedance between 1000 and 6000 and rated for at least 1
161. ophone AGC NG NG AGC 0 01 R 74 Jack Status JKSNS 0 02 R 115 Battery VBAT 0x03 Rw 116 Voltage Interrupt IULK 0 0 0 IJDET 0 117 Enable MASTER CLOCK CONTROL Master Clock 0 0 PSCLK 0 0 0 0 0 10 0x00 R W 85 DAI1 CLOCK CONTROL Clock Mode SR1 FREQ1 0x11 0x00 R W 85 86 Any Clock PLL1 NH 14 8 0x12 R W 86 Control NHI 1 0x13 R W 86 DAI1 CONFIGURATION Format MAS1 WCI1 BCI1 DLY1 0 TDM1 FSW1 WS1 Ox14 0x00 80 Clock ADC OSR1 DAC ORS1 0 0 BSEL1 0x15 0x00 81 SEL1 LTEN1 LBEN1 DMONO 1 HIZOFF1 SDOEN1 SDIEN1 Ox16 0x00 R W 81 82 Configuration Division SLOTL1 SLOTR1 SLOTDLY1 0x17 RW 82 Multiplex Filters MODE1 AVFLT1 DHF1 DVFLT1 0x18 0 00 90 DAI2 CLOCK CONTROL Clock Mode SR2 0 0 0 0 0x19 0x00 R W 85 Any Clock PLL2 NI2 14 8 0 00 RAV 86 Control NI2 7 1 1 R W 86 DAI2 CONFIGURATION Format MAS2 WCI2 BCI2 DLY2 0 TDM2 FSW2 WS2 0 1 0x00 80 DAC_ Clock 0 0 ORS 0 0 BSEL2 Ox1D 0x00 R W 81 Je SEL2 0 LBEN2 DMONO 2 HIZOFF2 SDOEN2 SDIEN2 Ox1E 0 00 R W 81 82 Configuration Maxim Integrated Products 61 Table 1 Register Map continued MAX98089 Low Power Stereo Audio Codec with FlexSound Technology REGISTER Time Division Multiplex B7 B6 5 4 B1 BO ADDRESS Ox1F DEFAULT 0x00 R W
162. oth digital audio interfaces are operating normally 1 Either digital audio interface is configured incorrectly or receiving invalid clocks Jack Configuration Change JDET reports changes to any bit in the Jack Status register 0x02 Changes to the Jack Status bits are debounced before setting JDET The debounce period is programmable using the JDEB bits JDET is always set the first time JDETEN or SHDN is set the first time power is applied to IC Read the status register following such an event to clear JDET and allow for proper jack detection 0 No change in jack configuration 1 Jack configuration has changed Full Scale Interrupt Enable CLD 0 Disabled 1 Enabled Volume Slew Complete Interrupt Enable 6 SLD 0 Disabled 1 Enabled OxOF P Digital Audio Interface Unlocked Interrupt Enable 5 ULK 0 Disabled 1 Enabled Jack Configuration Change Interrupt Enable 1 IJDET 0 Disabled 1 Enabled MAXIN Maxim Integrated Products 117 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Device Revision Table 37 Device Revision Register REGISTER BIT NAME DESCRIPTION 7 6 5 OxFF 4 REV Device Revision Code Read Only 3 REV is always set to 0x40 2 1 0 I C Serial Interface The IC features an I C SMBus compatible 2 wire serial interface comprising a serial data line SDA and a
163. oviding a more DVST 048 TO 60dB SIDETONE DSTS Figure 14 Sidetone Block Diagram AMVI Maxim Integrated Products 77 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 8 Sidetone Register REGISTER BIT NAME DESCRIPTION Sidetone Source 7 Selects which ADC output is fed back as sidetone When mixing the left and right ADC outputs each is attenuated by to prevent full scale signals from clipping DSTS 00 Sidetone disabled 01 Left ADC 6 10 Right ADC 11 Left Right ADC Sidetone Level 4 Adjusts the sidetone signal level All levels are referenced to the ADC s full scale output VALUE LEVEL dB VALUE LEVEL dB 0x00 Sidetone disabled 0x10 30 5 0x01 0 5 0x11 32 5 3 0x02 2 5 0x12 34 5 0x2E 0x03 4 5 0x13 36 5 0x04 6 5 0x14 38 5 0x05 8 5 0x15 40 5 7 DVST 0 06 10 5 0 16 42 5 0 07 12 5 0 17 44 5 0x08 14 5 0x18 46 5 0x09 16 5 0x19 48 5 OxOA 18 5 Ox1A 50 5 OxOB 20 5 Ox1B 52 5 OxOC 22 5 Ox1C 54 5 24 5 Ox1D 56 6 2 26 5 58 5 OxOF 28 5 Ox1F 60 5 natural user experience The IC implements sidetone dig Each audio interface can be configured in a variety of for itally Doing so helps prevent unwanted feedback into the mats including left justified 125 PCM and time division playback signal path and better ma
164. ow Power Stereo Audio Codec with FlexSound Technology gt ATTACK TIME HOLD TIME RELEASE TIME Figure 12 AGC Timing ADC Record Level Control The IC includes separate digital level control for the left and right ADC outputs Figure 13 To optimize dynamic range use analog gain to adjust the signal level and set AVLG 0 6 AVRG 0 6 12 18dB 12 18dB AVL 0dB AVR 0dB TO 15dB 15dB Figure 13 ADC Record Level Control Block Diagram MAKII Maxim Integrated Products 76 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 7 ADC Record Level Control Register REGISTER BIT NAME DESCRIPTION Left Right ADC Gain 5 00 0dB AVLG AVRG 01 4 10 12dB 11 1898 3 Left Right ADC Level VALUE GAIN dB VALUE GAIN dB 0x33 0x34 2 0 0 3 Ox8 5 Ox1 2 Ox9 6 AVLIAVR 0 2 1 OxA 7 1 Ox3 0 OxB 8 Ox4 1 OxC 9 Ox5 2 OxD 10 0 Ox6 3 OxE 11 Ox7 4 OxF 12 the digital level control to OdB whenever possible Digital Enable sidetone during full duplex operation to add a evel control is primarily used when adjusting the record low level copy of the recorded audio signal to the play evel for digital microphones back audio signal Figure 14 through DAI1 playback path Sidetone is commonly used in telephony to allow Sidetone the speaker to hear himself speak pr
165. put resistors as show in Figure 8 and or inputting signals larger than 1VP P by adjusting the ration of the 20kQ Rjj less than 1 VA INAT EXTMICP 1Vp p max gt INA2 EXTMICN 1Vp p max Figure 8 Summing Multiple Input Signals into INA INB Maxim Integrated Products 71 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 4 Line Input Registers REGISTER BIT NAME DESCRIPTION Line Input A B External Gain Switches out the internal input resistor and selects a trimmed 20kQ feedback resistor 6 INAEXT INBEXT Use an external input resistor to set the gain of the line input 0 Disabled 1 Enabled Line Input A B Internal Gain Settings 0 37 38 o nic 001 14dB 010 3dB 1 PGAINA PGAINB 011 048 100 101 6dB 0 110 6dB 111 6dB Line Input A Differential Enable 7 INADIFF 0 Stereo single ended input 1 Mono differential input Ox47 Line Input B Differential Enable 6 INBDIFF 0 Stereo single ended input 1 Mono differential input ADC Input Mixers The IC s stereo ADC accepts input from the microphone amplifiers line inputs amplifiers and directly from the INA1 and INA2 The ADC mixer routes any combina tion of the eight audio inputs to the left and right ADCs Figure 9 MIXADL MIXADR Figure 9 ADC Input Mixer Block Dia
166. ransfer One data bit is transferred during each SCL cycle The data on SDA must remain stable during the high period of the SCL pulse Changes in SDA while SCL is high are con trol signals see the START and STOP Conditions section START and STOP Conditions SDA and SCL idle high when the bus is not in use A mas ter initiates communication by issuing a START condition A START condition is a high to low transition on SDA with SCL high A STOP condition is a low to high transition on SDA while SCL is high Figure 33 A START condition from the master signals the beginning of a transmission to the IC The master terminates transmission and frees the bus by issuing a STOP condition The bus remains active if a REPEATED START condition is generated instead of a STOP condition Early STOP Conditions The IC recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition For proper operation do not send a STOP condition during the same SCL high pulse as the START condition Figure 34 START STOP and REPEATED START Conditions SMBus is a trademark of Intel Corp AVLAZCLA Maxim Integrated Products 118 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Slave Address The slave address is defined as the seven most signifi cant bits MSBs followed by the read wri
167. rom HPL or HPR to HPGND Line out loads RLOUT connected from LOUTL or LOUTR to SPKLGND RLOAD RHP ZSPK CREF 2 2 CMICBIAS CREG CC1N C1P CHPVDD CHPVSS 1HF AVMICPRE_ 2088 AVMICPGA_ AVDACATTN OdB AVDACGAIN OdB AVADCLVL AVADCGAIN OdB AVPGAIN_ AVHP_ AVspK_ MCLK 12 288MHz LRCLK 48kHz MAS 0 TA TMIN to Tmax unless otherwise noted Typical values are at TA 25 C Note 1 PARAMETER SYMBOL CONDITIONS MIN MAX UNITS MICROPHONE BIAS MICBIAS Output Voltage 5 1mA 2 15 2 2 2 25 V Load Regulation ILOAD 1mA to 2mA 0 5 4 5 mV Line Regulation VSPKLVDD 2 8V to 5 5V 110 uV f 217Hz V 100mVp 92 Ripple Rejection 2 VRIPPLE SPKLVDD P P dB f 10kHz VRIPPLE SPKLVDD 100mVp p 83 A weighted f 20Hz to 20kHz 3 9 V Noise Voltage P weighted f 20Hz to 4kHz 24 ee f 1kHz 50 nV Hz MICROPHONE BYPASS SWITCH IMIC1_ 100mA INABYP MIC2BYP 1 On Resistance RON VMIC2_ OV AVDD 25 C 5 30 Q Total Harmonic Distortion VIN 2 0 9V RL 10kQ Noise f 1kHz INABYP MIC2BYP 1 dB Off Isolation VIN 2VP P Vom 0 9V RL 10kQ f 1kHz 60 dB AVDD VMIC2 _ _ Off Leakage Current AVDD OV 1 1 LINE INPUT TO ADC PA
168. sing Block Diagram AVLAX LA The ALC can optionally be configured in multiband mode In this mode the input signal is filtered into two bands with a 5kHz center frequency Each band is routed through independent ALCs and then summed together In multiband mode both bands use the same parameters OUTPUT SIGNAL dBFS INPUT SIGNAL LOW LEVEL 12 dBFS THRESHOLD ALC WITH ALCTH 000 OUTPUT SIGNAL dBFS INPUT SIGNAL LOW LEVEL 12 dBFS THRESHOLD ALC WITH ALCTH 000 OUTPUT SIGNAL dBFS INPUT SIGNAL LOW LEVEL 12 dBFS THRESHOLD ALC DISABLED Figure 21 ALC Input vs Output Examples Maxim Integrated Products 92 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 16 Automatic Level Control Registers REGISTER BIT NAME DESCRIPTION ALC Enable 7 ALCEN Enables ALC on both the DAI1 and DAI2 playback paths 0 Disabled 1 Enabled ALC and Excursion Limiter Release Time Sets the release time for both the ALC and Excursion Limiter See the Excursion Limiter 6 section for Excursion Limiter release times ALC release time is defined as the time required to adjust the gain from 12dB to VALUE ALC RELEASE TIME s 000 8 5 ALCRLS 001 4 010 2 011 1 100 0 5 101 0 25 0x43 4 110 Reserved 111 Reserved Multiband Enable Enables dual band processing with a 5kHz center frequency SR1 and SR2 must be 3 ALCMB configured properly to ach
169. tches the playback audio signal Sidestone is available in voice mode only Digital Audio Interfaces The IC includes two separate playback signal paths and one record signal path Digital audio interface 1 DAI1 is used to transmit the recorded stereo audio signal and receive a stereo audio signal for playback Digital audio interface 2 DAI2 is used to receive a second stereo audio signal Use for full duplex operations and for all voice signals Use DAI2 for music and to mix two playback audio signals The digital audio interfaces are separate from the audio ports to enable either interface to communicate with any external device connected to either audio port AVLAZCLA multiplexed TDM TDM mode supports up to 4 mono audio slots in each frame The IC can use up to 2 mono slots per interface leaving the remaining two slots avail able for another device Table 9 shows how to configure the device for common digital audio formats Figures 16 and 17 show examples of common audio formats By default SDOUTS1 and SDOUTS are set high imped ance when the IC is not outputting data to facilitate shar ing the bus Configure the interface in TDM mode using only slot 1 to transmit and receive mono PCM voice data The IC s digital audio interfaces support both ADC to DAC loop through and digital loopback Loop through allows the signal converted by the ADC to be routed to the DAC for playback The signal is routed from the record
170. te bit For the IC the seven most significant bits are 0010000 Setting the read write bit to 1 slave address 0x21 configures the IC for read mode Setting the read write bit to slave address 0x20 configures the ICs for write mode The address is the first byte of information sent to the IC after the START condition Acknowledge The acknowledge bit ACK is a clocked 9th bit that the IC uses to handshake receipt each byte of data when in write mode Figure 35 The IC pulls down SDA dur ing the entire master generated 9th clock pulse if the previous byte is successfully received Monitoring ACK allows for detection of unsuccessful data transfers An unsuccessful data transfer occurs if a receiving device START CONDITION is busy or if a system fault has occurred In the event of an unsuccessful data transfer the bus master retries communication The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the IC is in read mode An acknowledge is sent by the master after each read byte to allow data transfer to continue A not acknowledge is sent when the master reads the final byte of data from the IC followed by a STOP condition Write Data Format A write to the IC includes transmission of a START condi tion the slave address with the R W bit set to 0 one byte of data to configure the internal register address pointer one or more bytes of data and a STOP condition Figure 36 illustrates
171. tering Registers REGISTER BIT NAME DESCRIPTION DAI1 Passband Filtering Mode 7 1 0 Voice filters 1 Music filters recommended for fs gt 24 2 6 ADC Highpass Filter Mode 5 MODE1 AVFLT1 AVFLT1 0 See Table 15 4 1 Select a nonzero value to enable the DC blocking filter 0x18 DAI High Sample Rate Mode Selects the sample rate range 8kHz lt LRCLK x 48kHz 1 48kHz lt LRCLK lt 96kHz 2 DAI1 DAC Highpass Filter Mode 1 MODE1 DVFLT1 DVFLT1 0 See Table 15 Select a nonzero value to enable the DC 0 1 NA blocking filter DAI2 High Sample Rate Mode Selects the sample rate range Bhika 8kHz lt LRCLK lt 48kHz 1 48kHz lt LRCLK lt 96kHz 0x20 DAI2 DC Blocking Filter Enables a DC blocking filter on the DAI2 playback audio path 0 DCB2 0 Disabled 1 Enabled Maxim Integrated Products 90 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 15 Voice Highpass Filters AVFTL DVFLT VALUE INTENDED SAMPLE RATE FILTER RESPONSE 000 N A Disabled 1 22 1 22 001 011 16kHz 8kHz E 3 lt 4 5 6 200 400 600 800 1000 FREQUENCY Hz NEL 010 100 16kHz 8kHz 3 lt 4 5 6 0 200 400 600 800 1000 FREQUENCY Hz PES 101
172. the proper frame format for writing one byte of data to the IC Figure 37 illustrates the frame format for writing n bytes of data to the IC CLOCK PULSE FOR ACKNOWLEDGMENT x PX FO DX AA NOT ACKNOWLEDGE Figure 35 Acknowledge ACKNOWLEDGE FROM MAX98089 E ACKNOWLEDGE FROM MAX98089 E ACKNOWLEDGE ACKNOWLEDGE FROM MAX98089 SLAVE ADDRESS A REGISTER ADDRESS A Figure 36 Writing One Byte of Data to the ICs A 1 BYTE 1 TERNAL REGISTER ADDRESS POINTER AUTOINCREMENT ACKNOWLEDGE FROM MAX98089 OWLEDGE FROM MAX98089 B7 86 B5 B4 B2 B1 B5 B2 TT T 1 REGISTER ADDRESS DATABYIET DATA BYTEn 2 R W 4 L AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER ACKNOWLEDGE FROM MAX98089 E ACKNOWLEDGE FROM MAX98089 E S SLAVE ADDRESS 0 1 1 1 BYTE Figure 37 Writing n Bytes of Data to the ICs AVLAZCL VI Maxim Integrated Products 119 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology The slave address with the R W bit set to O indicates that the master intends to write data to the ICs The ICs acknowledge receipt of the address byte
173. usie 1 25 0 47 0 00 1 35 0 01 5 55 97 filters 256Fs DAC Playback 48kHz Stereo HP DAC gt HP Low power mode 24 bit music 1 25 1 81 0 00 1 56 0 01 8 32 97 filters 256Fs 0 1mW channel RHP 320 MAKII Maxim Integrated Products 25 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Power Consumption continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V MAS 0 MODE lAVDD IPVDD IDVDD puru POWER DYNAMIC mA mA mA mA mA mW RANGE dB DAC Playback to Headphone DAC Playback 48kHz Stereo HP DAC HP 2 04 1 27 0 00 1 53 0 01 8 72 101 24 bit music filters 256Fs DAC Playback 48kHz Stereo HP DAC gt HP 24 bit music filters 256Fs O 1mW channel 32Q DAC Playback 44 1kHz Stereo HP DAC HP 2 03 1 27 0 00 1 41 0 01 8 46 101 24 bit music filters DAC Playback 44 1kHz Stereo HP 2 04 2 11 0 00 1 74 0 01 10 63 101 DAGS HP 1 25 0 47 0 00 1 25 0 01 5 34 98 Low power mode 24 bit music filters DAC Playback 8kHz Stereo HP DAC gt HP 2 04 1 27 0 00 1 07 0 00 7 89 96 16 bit voice filters DAC Playback 8kHz Stereo HP DAC HP 1 26 0 47 0 00 0 90 0 00 4 72 96 16 bit low power mode voice filters DAC Playback 8kHz Mono HP DAC gt HP 0 77 0 29 0 00 0 79 0 00 3 33 98 16 bit low power mode voice filters Line Playback Stereo HP INA gt HP 2 40 1 27 0 00 0 02 0 00 6 67 95 S
174. volume control Figure 28 All three limiters analyze the speaker amplifier s output signal to determine when to take action Excursion Limiter The excursion limiter is a dynamic highpass filter that monitors the speaker outputs and increases the highpass corner frequency when the speaker amplifiers output exceeds a predefined threshold The filter smoothly transitions between the high and low corner frequency to prevent unwanted artifacts The filter can operate in four different modes e Fixed Frequency Preset Mode The highpass corner frequency is fixed at the upper corner frequency and does not change with signal level e Fixed Frequency Programmable Mode The high pass corner frequency is fixed to that specified by the programmable biquad filter e Preset Dynamic Mode The highpass filter automati cally slides between a preset upper and lower corner frequency based on output signal level e User Programmable Dynamic Mode The highpass filter slides between a user programmed biquad filter on the low side to a predefined corner frequency on the high side Maxim Integrated Products 102 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology The transfer function for the user programmable biquad is _ 6971 boz H z 1 2 22 The coefficients bo 61 02 a1 and are sample rate dependent and stored in registers OxB4 through OxC7 Store bo b1 and b2 as pos
175. vs SUPPLY VOLTAGE vs FREQUENCY DAC TO SPEAKER DAC TO SPEAKER 2500 MCLK 12 288MHz MCLK 12 288MHz 2 i LRCLK 48kHz 5 LRCLK 48kHz 8 NI MODE E 2000 Ni MODE 3 Zspk 40 33pH a Zspk 80 68 30 AVspK_ 8dB AVspK_ 8dB 1500 TOFN PACKAGE 40 THD N 10 5 1000 6 5 7 E 500 HD N 1 8 9 0 Ok 25 30 35 40 45 50 55 FREQUENCY Hz SUPPLY VOLTAGE V OUTPUT POWER vs SUPPLY VOLTAGE OUTPUT POWER vs SUPPLY VOLTAGE OUTPUT POWER vs SUPPLY VOLTAGE DAC TO SPEAKER DAC TO SPEAKER DAC TO SPEAKER 2500 8 4000 g 4000 5 MCLK 12 288MHz 8 MCLK 12 288MHz MCLK 12 288MHz LRCLK 48kHz 8 3500 LRCLK 46kHz z350 LLRCLK 48kHz 8 2000 DE 2 NI MODE E NI MODE THD N 10 5 80 68H 3000 f 25 40 41 3000 25 40 _ 80 AVspk_ 8dB AVSPK_ 808 d 15 WLP PACKAGE 85 2500 p TOFN PACKAGE 2500 F WLP PACKAGE 1 THD N 10 5 2000 2000 6 5 5 1500 8 1500 1000 1000 5 500 5 5 THD N 1 500 500 0 0 2 5 3 0 3 5 40 45 5 0 5 5 25 3 0 35 4 0 45 5 0 55 25 3 0 35 40 45 5 0 55 SUPPLY VOLTAGE V SUPPLY VOLTAGE SUPPLY VOLTAGE V Maxim Integrated Products 41 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7
176. xim Integrated Products 114 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 33 Change in JKSNS Upon Jack Removal JACK TYPE JDWK 1 AND MICBIAS DISABLED JDWK 0 OR MICBIAS ENABLED l JKSNS 00 gt 11 JKSNS 00 gt 11 EL JKSNS 00 gt 11 JKSNS 01 11 Table 34 Jack Detection Registers REGISTER BIT NAME DESCRIPTION JACKSNS State Reports the status of JACKSNS when JDETEN 1 VALUE MODE DESCRIPTION 7 00 BEN 1 VJACKSNS 0 1V x VMICBIAS BEN 0 VJACKSNS lt 0 1V x VSPKLVDD 0 1V x VMICBIAS lt VJACKSNS lt Ox02 BEN 1 0 95V x V Read Only 01 VMICBIAS BEN 0 0 1V x VSPKLVDD lt VJACKSNS lt 0 95V x VSPKLVDD BEN 1 Reserved 6 10 BEN 0 Reserved ii BEN 1 0 95V x VMICBIAS lt VJACKSNS BEN 0 0 95V x VSPKLVDD lt VJACKSNS Jack Detection Enable 7 JDETEN 0 Disabled 1 Enabled Jack Detection Debounce Ox4B 1 Configures the debounce time for setting JDET 00 25ms JIDER 01 50ms 0 10 100ms 11 200ms MAXIM Maxim Integrated Products 115 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 34 Jack Detection Registers continued REGISTER Ox4E BIT NAME DESCRIPTION 14 BGEN See the Power Management section 6 SPREGEN See the Power Management section 5 VCMEN See the Power Management section 4 BI
177. xim Integrated Products 85 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology Table 11 Clock Control Registers continued REGISTER BIT NAME DESCRIPTION Exact Integer Mode Overrides PLL1 and and configures a specific PCLK to LRCLK ratio 3 VALUE SAMPLE RATE VALUE SAMPLE RATE PCLK 12MHz OxO Disabled 0x8 LRCLK 8kHz PCLK 12MHz Ox1 Reserved 0x9 LRCLK 16kHz PCLK 13MHz 0x2 Reserved OxA LRCLK 8kHz 0 11 FREQ1 PCLK 13MHz Ox3 Reserved OxB LRCLK 16kHz PCLK 16MHz 0 4 Reserved OxC LRCLK PCLK 16MHz Ox5 Reserved OxD LRCLK 16kHz PCLK 19 2MHz 1 Ox6 Reserved OxE LRCLK 8kHz PCLK 19 2MHz Ox7 Reserved LRCLK 16kHz PLL Mode Enable Slave Mode Only PLL1 PLL2 enables a digital PLL that locks on to the externally supplied LRCLK frequen 7 PLL1 PLL2 cy and automatically sets the LRCLK divider 1 2 0 Disabled 1 Enabled 6 Normal Mode LRCLK Divider Ox12 0x1A 5 When PLL1 PLL2 0 the frequency of LRCLK is determined by NI1 NI2 See Table 12 4 for common NI values 3 A SAMPLE RATE DHF1 DHF2 NI1 NI2 FORMULA 1 65 536 96 f 0 NI1 8kHz LRCLK lt 48kHz 0 NI P LRCLK 7 NI2 PCLK 6 65 536 x 48 x f 5 48kHz LRCLK lt 96kHz 1 NI 2 PCLK 3 2 fLRCLK LRCLK frequency 0x13 0x1B fPCLK Prescaled MCLK frequency
178. z 78 armonic Distortion VIN 1Vp p f 1kHz 85 dB AVMICPRE_ 0 VIN 32mVp p f 1kHz 71 CMRR Vin 100mVp p f 217Hz 74 dB Ratio VAVDD 1 65V to 1 95V input referred 50 62 MIC inputs unconnected Power Supply Rejection Ratio PSRR f 217Hz VRIPPLE 200mVp p input referred 62 dB f 1kHz VRIPPLE 200mVp p input referred 62 f 10kHz VRIPPLE 200mVp p input referred 55 MODE 0 IIR voice 22 8kHz 1kHz OdB input MODE 0 IIR voice 11 i i 16kHz Path Phase Delay highpass filter disabled ims measured from analog MODE 1 FIR audio input to digital output 8kHz 4 5 MODE 1 FIR audio 48kHz 9 76 MICROPHONE PREAMP Full Scale Input AVMICPRE_ 1 05 VP P PA1EN PA2EN 01 0 Preamplifier Gain AVMICPRE_ Note 5 PA1EN PA2EN 10 19 5 20 20 5 dB PA1EN PA2EN 11 29 5 30 30 5 PGAM1 PGAM2 0x00 19 20 21 PGA Gain AV Note 5 dB Motes PGAM1 PGAM2 0x14 0 All gain settings measured at MIC1P IC Input Resistance RIN_MIC MIC1N MIC2P MIC2N 50 kQ IVI Maxim Integrated Products 7 MAX98089 Low Power Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS continued VAVDD VPVDD VDVDD VDVDDS1 VDVDDS2 1 8V VSPKLVDD VSPKRVDD 3 7V Speaker loads ZsPK connected between SPK_P and SPK_N Receiver load RREC connected between RECP and RECN Headphone loads RHP connected f

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