TEXAS INSTRUMENTS CD54/74HC123 CD54/74HCT123 CD74HC423 CD74HCT423 High Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets handbook
Contents
1. C D54 74H C123 4 TEXAS INSTRUMENTS Data sheet acquired from Harris Semiconductor SCHS142A September 1997 Revised May 2000 Features Overriding Reset Terminates Output Pulse Triggering From the Leading or Trailing Edge Q and Q Buffered Outputs Separate Resets Wide Range of Output Pulse Widths Schmitt Trigger on Both A and B Inputs Fanout Over Temperature Range Standard Outputs Bus Driver Outputs Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types 2V to 6V Operation High Noise Immunity 30 30 0f Vcc at Vcc 5V HCT Types 4 5V to 5 5V Operation Direct LSTTL Input Logic Compatibility 0 8V Max 2V Min CMOS Input Compatibility lt 14A at Pinout CD54HC123 CD54HCT123 CERDIP CD74HC123 CD74HCT123 CD74HC423 CD74HCT423 PDIP SOIC TOP VIEW 10 LSTTL Loads 15 LSTTL Loads Wide Operating Temperature Range 55 C to 125 C CD54 74HC123 CD54 74HCT 123 CD74HC423 CD74HCT423 High Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets Description The HC123 HCT123 CD74HC423 and CD74HCT423 are dual monostable multivibrators with resets They are all retriggerable and differ only in that the 123 types can be triggered by a negative to positive reset pulse whereas the 423 types do not have this feature An external resistor Rx and an external2. 74HC 123 CD54 74HCT123 CD74HC423 CD74HCT423 DC Electrical Specifications Continued TEST PARAMETER SYMBOL V UNITS V lo ma MIN TYP MAX MIN MAX MIN MAX HCT TYPES High Level Input 4 5 to 2 2 2 V Voltage 5 5 Low Level Input 4 5 to Voltage 5 5 High Level Output VoH Vig Or Vi 0 02 4 5 Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output VoL 0 02 4 5 0 1 0 1 0 1 V Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Voc and 0 1 Current GND Quiescent Device or Current Additional Quiescent Voc zd 5 to d Device Current Per 2 1 5 5 Input Pin 1 Unit Load NOTE For dual supply systems theoretical worst case V 2 4V Voc 5 5V specification is 1 8mA HCT Input Loading Table INPUT UNIT LOADS NOTE Unit Load is Alcc limit specified in DC Electrical Table e g 360uA max at 25 C Prerequisite for Switching Specifications 40 85 559 1259 5 Minimum Input Pulse Width A CD54 74HC 123 CD54 74HCT123 CD74HC423 CD74HCT423 Prerequisite for Switching Specifications Continued 40 85 559 1259 Hold Time Reset Removal Time Retrigger Time Number Rx 10KQ Cx 0 Output Pulse Width QorQ Rx 10KQ Cy 10nF HCT TYPES Minimum Inpu
3. WIDTH AS A FUNCTION FIGURE 5 TYPICAL K FACTOR AS A FUNCTION OF Vcc Cy FOR Ry 10kQ AND 100 IMPORTANT NOTICE Texas Instruments its subsidiaries reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using TI components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied
4. capacitor Cx control the timing and the accuracy for the circuit Adjustment of Rx and Cy provides a wide range of output pulse widths from the Q and Q terminals Pulse triggering on the A and B inputs occur at a particular voltage level and is not related to the rise and fall times of the trigger pulses Once triggered the output pulse width may be extended by retriggering inputs A and B The output pulse can be terminated by a LOW level on the Reset R pin Trailing edge triggering A and leading edge triggering B inputs are provided for triggering from either edge of the input pulse If either Mono is not used each input on the unused device A B and R must be terminated high or low The minimum value of external resistance Rx is typically 5kQ The minimum value external capacitance Cx is OpF The calculation for the pulse width is tw 0 45 RxC x at Vcc 5V Ordering Information NOTES 1 When ordering use the entire part number Add the suffix 96 to obtain the variant in the tape and reel 2 Wafer or die for this part number is available which meets all electrical specifications Please contact your local TI sales office or customer service for ordering information CAUTION These devices are sensitive to electrostatic discharge Users should follow proper IC Handling Procedures Copyright 2000 Texas Instruments Incorporated CD54 74HC 123 CD54 74HCT123 CD74HC423 CD74HCT423 Functional Diagram TRUTH TA
5. is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 2000 Texas Instruments Incorporated
6. BLE INPUTS OUTPUTS CD74HC HCT123 NOTE H High Voltage Level L Low Voltage Level X Don t Care CD54 74HC 123 CD54 74HCT123 CD74HC423 CD74HCT423 Absolute Maximum Ratings Thermal Information DC Supply Voltage 0 5V to 7V Thermal Resistance Typical Note 3 DC Input Diode Current lik PDIP Package For Vj lt 0 5V or Vj gt Voc 0 5 i20mA SOIC Package DC Output Diode Current lox Maximum Junction Temperature For lt 0 5 gt 05 20mA Maximum Storage Temperature Range 65 C to 150 C DC Output Source or Sink Current per Output Pin lo Maximum Lead Temperature Soldering 10s For Vo gt 0 5V lt 0 5 25 SOIC Lead Tips Only DC Vec or Ground Current 50 Operating Conditions Temperature Range Ta 55 C to 125 C Supply Voltage Range Vcc HC Types 2V to 6V HET Types uet expe e seve 4 5V to 5 5V DC Input or Output Voltage Vi Vo Input Rise and Fall Time 1000ns Max 500ns Max 400ns Max CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE 3 is measured with the component mounted o
7. n an evaluation PC board in free air DC Electrical Specifications TEST CONDITIONS Vec 40 C 85 C 55 C TO 125 C PARAMETER SYMBOL V UNITS AN iTVP ec 5 lt Voltage lt Pn Ea PALAESSA NONE Voltage ERUNT RC RR MET GMOS Loads ve posae crees nes Figh Level RESET TTL Loads RES E HIS sec ete oie lt 0 70 50 00 High Level Input 1 18 15 1 15 VIL lt lt lt lt lt lt lt lt lt lt lt CMOS Loads MIN Input Leakage Voc or 0 1 1 1 Current GND Quiescent Device loc Voc or 160 Current GND lt Low Level Output Voltage TTL Loads lt lt CD54
8. t Pulse Width am e reae 5 Retrigger Time Number Note 4 Ry 10KQ Cy 0 tT 5 50 63 76 ns Output Pulse Width Q or Q tw 5 40 50 38 7 51 3 38 2 51 8 us Ry 10KQ Cx 10nF NOTE 4 Time to trigger depends on the values of Rx and Cx The output pulse width can only be extended when the time between the active going edges of the trigger input pulses meet the minimum retrigger time requirement CD54 74HC 123 CD54 74HCT123 CD74HC423 CD74HCT423 Switching Specifications C 50pF Input tp t 6ns Rx 10KQ Cy 0 55 C TO 25 C 85 C 125 C TEST PARAMETER SYMBOL CONDITIONS Vcc V MIN TYP MAX MAX UNITS HC TYPES Uni Trigger Propagation Delay tPHL 50pF 55 pe fol fol ole eae aes IEEE EE eSI el Reset Propagation Delay 50pF 2 ae ao se Output Transition Time tTHL trLH 50pF 2 Output Pulse Width 5 Rx 10KQ Cy 10pF Pulse Width Match Between Circuits In the Same Package R
9. x 10KQ Cy 10pF Power Dissipation Capacitance 15pF Notes 5 6 IE LE 5 Cpp is used to determine the dynamic power consumption per multivibrator 6 Pp Cpp Oy Vec fi CL Vee fo where f input frequency fo Output Frequency C Output Load Capacitance Cx External Capacitance Vcc Supply Voltage assuming fj t Ww CD54 74HC 123 CD54 74HCT123 CD74HC423 CD74HCT423 Test Circuits and Waveforms tw I tw FIGURE 1 OUTPUT PULSE CONTROL USING RESET INPUT FIGURE 2 OUTPUT PULSE CONTROL USING RESET INPUT R PULSE FOR 123 R FOR 423 R HIGH NOTE Output pulse control using retrigger pulse for 123 and 423 FIGURE 3 TRIGGERING OF ONE SHOT BY INPUT A OR INPUT B FOR A PERIOD tw 0 9 EXTERNAL CAPACITANCE Cy 10nF 0 8 EXTERNAL RESISTANCE Ry 10kQ TO 100k AMBIENT TEMPERATURE Ta 25 C 1 wo o 0 7 Cr gt ok 0 6 0 5 SS 7 FACTOR 0 4 E o SUPPLY VOLTAGE Vcc 5V BIENT TEMPERATURE Ta 25 M d Qo du Rud 3 4 5 6 7 8 9 10 EXTERNAL CAPACITANCE Cy pF DC SUPPLY VOLTAGE Vcc VOLTS OUTPUT PULSE WIDTH us 5 N ROC N ROC M POCO N LMC FIGURE 4 TYPICAL OUTPUT PULSE
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