MAXIM MAX2120 Complete Direct-Conversion Tuner for DVB-S Free-to-Air Applications handbook
Contents
1. AI A ld Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com OcCLOCXVIWN MAX2120 Complete Direct Conversion Tuner for DVB S and Free to Air Applications ABSOLUTE MAXIMUM RATINGS Vecto GND saree D javlja pa 0 3V to 3 9V Continuous Power Dissipation TA 70 C All Other Pins to GND 0 3V to Vcc 0 3V 28 Pin Thin QFN derated 34 5mW C above 70 C 2 75W RF Input Power REIN 10dBm Operating Temperature Range 0 C to 70 C VCOBYP CPOUT REFOUT XTAL IOUT_ QOUT_ IDC_ and Junction Temperature AAA 150 C ODC Short Circuit Protecton nn 10s Storage Temperature Range 65 C to 160 C Lead Temperature soldering 1Oei 300 C Soldering Temperature reflow 260 C CAUTION ESD SENSITIVE DEVICE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the oper absolute maximum rating conditions for extended periods may affect device reliability DC ELECTRICAL CHARACTERISTICS MAX2120 Evaluation Kit Vec 3 13V to 3 47V Vaci 0 5V max gain I Os are open circuited and LO2. 100 z Divide by 4 101 through 110 All divide values from 5 101 to 7 110 111 Divide by 8 Sets the PLL reference divider R number 00001 Divide by 1 00010 z Divide by 2 00011 Divide by 3 00100 z Divide by 4 default 00101 through 11110 All divide values from 3 00101 to 29 11110 11111 2 Divide by 31 Table 6 PLL Register BIT NAME BIT LOCATION 0 LSB DEFAULT FUNCTION VCO divider setting D24 0 Divide by 2 Use for LO frequencies gt 1125MHz 1 Divide by 4 Use for LO frequencies lt 1125MHz Charge pump current mode CPS ICP X 0 Charge pump current controlled by ICP bit 1 Charge pump current controlled by VCO autoselect VAS Charge pump current 5 O 600pA typical 1 1200pA typical a dl d Slab 11 OcLOCXVIN MAX2120 Complete Direct Conversion Tuner for DVB S and Free to Air Applications Table 7 VCO Register BITNAME BITLOCATION 0 1B DEFAULT Controls which VCO is activated when using manual VCO VCO 4 0 programming mode This also serves as the starting point for the VCO autoselect mode VCO Autoselection VAS Circuit 0 Disable VCO selection must be program through PE 1 Enable VCO selection controlled by autoselection circuit Enables or disables the VCO tuning voltage ADC latch when he VCO autoselect mode VAS is disabled 0 Disables the ADC latch 1 Latches the ADC value Enables or disables VCO tuning voltage AD
3. 0 5V lt Vac1 lt 2 7V Baseband Gain Control Range Bits GC2 1111 to 0000 In Band Input IP3 Note 3 of Band Input IP3 Note 4 ut IP2 Note 5 jacent Channel Protection Note 6 Vaci is set to 0 5V maximum RF gain and BBG 3 0 is adjusted to give a 1Vp p baseband output level for a ise Figure 75dBm CW input tone at 1500MHz Starting with the same BBG 3 0 setting as above Vac1 is adjusted to back off RF gain by 10dB Note 7 inimum RF Input Return Loss 925MHz lt fRE lt 2175MHz in 750 system dB BASEBAND OUTPUT CHARACTERISTICS Nominal Output Voltage Swing RLOAD 2kQ 10pF f Vp p Q Amplitude Imbalance Measured at 500kHz filter set to 22 27MHz dB Q Quadrature Phase Imbalance Measured at 500kHz filter set to 22 27MHz j Degrees Single Ended UO Output mpedance Real Zo from 1MHz to 40MHz Output 1dB Compression Voltage Differential Baseband Highpass 3dB Frequency Corner BASEBAND LOWPASS FILTERS Filter Bandwidth Range Rejection Ratio At 2 x adB Group Delay Up to 1dB bandwidth Ratio of In Filter Band to Out of fINBAND 100Hz to 22 5MHz foUTBAND 87 5MHz to Filter Band Noise 112 5MHz FREQUENCY SYNTHESIZER RF Divider Frequency Range RF Divider Range N Reference Divider Frequency Range 47nF capacitors at IDC QDC Reference Divider Range R Phase Detector Comparison Frequency MM d Slab 3 OcCLOCXVIN MAX2120
4. an on MAX2120CTI 0 C to 70 C 28 Thin QEN EP chip crystal oscillator is provided along with a buffered output for driving additional tuners and demodulators EP Exposed padale Synthesizer programming and device configuration are Denotes a lead Pb free HoHS compliant package accomplished with a 2 wire serial interface The IC fea tures a VCO autoselect VAS function that automatically selects the proper VCO For multituner applications the Pin Configuration device can be configured to have one of two 2 wire Functional Diagram interface addresses A low power standby mode is available whereupon the signal path is shut down while leaving the reference oscillator digital interface and buffer circuits active providing a method to reduce power in single and multituner applications mm 271 mi 1251 j m m The MAX2120 is the most advanced DBS tuner available vec 2 15 E MAXIM DC oFFseT KH today The low noise figure eliminates the need for an EL a eius CORRECTION external LNA A small number of passive components are vec nei 23 CONTROL needed to form a complete DVB DBS or VSAT RF front U end solution The tuner is available in a very small 28 pin thin QFN package GND 3 Applications DirecTV and Dish Network DBS FREQUENCY DVB S p SYNTHESIZER Two Way Satellite Systems ih VSATS Free to Air
5. enable 0 Normal operation 1 Shuts down the RF VGA Value not tested RF front end enable O lt Normal operation 1 lt Shuts down the RF front end Value not tested Table 11 Test Register BIT NAME BIT LOCATION 0 LSB DEFAULT FUNCTION Charge pump test modes 000 z Normal operation default 001 Crystal translator ECL to CMOS path CPTST 2 0 100 Both source and sink currents enabled 101 2 Source current enabled 110 2 Sink current enabled 111 High impedance both source and sink current disabled Don t care Charge pump fast lock Users must program to 1 upon powering up the device REFOUT output SERGE 000 z Normal operation other values are not tested dl d Slab 13 OcCLOCXVIN MAX2120 Complete Direct Conversion Tuner for DVB S and Free to Air Applications Table 12 Status Byte 1 Register BIT NAME BIT LOCATION 0 LSB FUNCTION Power on reset status 0 Chip status register has been read with a stop condition since last power on 1 Power on reset power cycle has occurred default values have been loaded registers dicates whether VCO autoselection was successful Indicates the autoselect function is disabled or unsuccessful VCO selection Indicates successful VCO autoselection atus indicator for the autoselect function Indicates the autoselect function is active Indicates the autoselect process is inactive PLL lock detector TURBO bit must be
6. frequency 2150MHz Default register settin at Vcc 3 3V TA 25 C unless otherwise noted Note 1 PARAMETER CONDITIONS SUPPLY ational sections of the specifications is not implied Exposure to Ta 0 C to 70 C No input signals at RF baseband gs except BBG 3 0 1011 Typical values measured Supply Voltage Receive mode bit STBY 0 Supply Current Standby mode bit STBY 1 ADDRESS SELECT INPUT ADDR Digital Input Voltage High ViH Digital Input Voltage Low VIL Digital Input Current High liH Digital Input Current Low li ANALOG GAIN CONTROL INPUT GC1 nput Voltage Range Maximum gain 0 5V nput Bias Current VCO TUNING VOLTAGE INPUT VTUNE nput Voltage Range 2 WIRE SERIAL INPUTS SCL SDA Clock Frequency Input Logic Level High Input Logic Level Low Input Leakage Current 2 WIRE SERIAL OUTPUT SDA Digital inputs GND or Vcc Output Logic Level Low ISINK gt 1mA MAXIM Complete Direct Conversion Tuner for DVB S and Free to Air Applications AC ELECTRICAL CHARACTERISTICS MAX2120 Evaluation Kit Vcc 3 13V to 3 47V Vac1 0 5V max gain TA 0 C to 70 C Default register settings except BBG 3 0 1011 Typical values measured at Vcc 3 3V TA 25 C unless otherwise noted Note 1 PARAMETER CONDITIONS MAIN SIGNAL PATH PERFORMANCE Input Frequency Range Note 2 RF Gain Control Range GC1
7. programmed to 1 for valid LD reading 0 Unlocked 1 2 Locked Don t care Table 13 Status Byte 2 Register BIT NAME BIT LOCATION 0 LSB FUNCTION VCOSBR 4 0 7 3 VCO band readback VAS ADC output readback 000 Out of lock 001 Locked 010 z VAS locked 101 2 VAS locked 110 2 Locked 111 2 Out of lock 14 MAXKLM Complete Direct Conversion Tuner for DVB S and Free to Air Applications 2 Wire Serial Interface The MAX2120 uses a 2 wire I2C compatible serial interface consisting of a serial data line SDA and a serial clock line SCL SDA and SCL facilitate bidirec tional communication between the MAX2120 and the master at clock frequencies up to 400kHz The master initiates a data transfer on the bus and generates the SCL signal to permit data transfer The MAX2120 behaves as a slave device that transfers and receives data to and from the master SDA and SCL must be pulled high with external pullup resistors 1kQ or greater for proper bus operation One bit is transferred during each SCL clock cycle A minimum of nine clock cycles is required to transfer a byte in or out of the MAX2120 8 bits and an ACK NACK The data on SDA must remain stable during the high period of the SCL clock pulse Changes in SDA while SCL is high and stable are considered control signals see the START and STOP Conditions section Both SDA and SCL remain high when the bus is not busy Pullup resistors should be referen
8. the RF input Note 4 Out of band IIP3 test conditions GC1 set to provide nominal baseband output drive when mixing down a 23dBm tone at 2175MHz to 5MHz baseband fi o 2170MHz Baseband gain is set to its default value BBG 3 0 lt 1011 Two tones at 20dBm each are applied at 2070MHz and 1975MHz The IM3 tone at 5MHz is measured at baseband but is referred to the RF input Note 5 Input IP2 test conditions GC1 set to provide nominal baseband output drive when mixing down a 23dBm tone at 2175MHz to SMHz baseband fi o 2170MHz Baseband gain is set to its default value BBG 3 0 1011 Two tones at 20dBm each are applied at 925MHz and 1250MHz The IM2 tone at 5MHz is measured at baseband but is referred to the RF input Note 6 Adjacent channel protection test conditions GC1 is set to provide the nominal baseband output drive with a 2110MHz 27 5Mbaud signal at 55dBm GC2 set for mid scale The test signal will be set for PR lt 7 8 and SNR of 8 5dB An adjacent channel at 40MHz is added at 25dBm DVB S BER performance of 2E 4 will be maintained for the desired signal GC2 may be adjusted for best performance Note 7 Guaranteed by design and characterization at TA 25 C Note 8 See Table 14 for crystal ESR requirements 4 MAXIM Complete Direct Conversion Tuner for DVB S and Free to Air Applications Typical Operating Characteristics MAX2120 Evaluation Kit Vcc 3 3V baseband output frequency 5M
9. 19 0832 Rev 2 5 10 Lu ATION KIT NN NN MLABL MAKII Complete Direct Conversion Tuner for DVB S and Free to Air Applications General Description Features The MAX2120 low cost direct conversion tuner IC is 925MHz to 2175MHz Frequency Range designed for satellite set top and VSAT applications Monolithic VCO No Calibration Required The IC is intended for QPSK Digital Video Broadcast 75dBm to 0dBm High Dynamic Range DVB S DSS and free to air applications Predne ted Variable BW L Fii The MAX2120 directly converts the satellite signals i g S MER did Single 3 3V 5 Supply from the LNB to baseband using a broadband 1 Q downconverter The operating frequency range extends Low Power Standby Mode from 925MHz to 2175MHz Address Pin for Multituner Applications The device includes an LNA and an RF variable gain Differential UO Interface amplifier and Q downconverting mixers and baseband 20 5 Wi lowpass filters with programmable cutoff frequency IC 2 Wire sental Interface control and digitally controlled baseband variable gain Very Small 28 Pin Thin QFN Package amplifiers Together the RF and baseband variable gain amplifiers provide more than 80dB of gain control range 9 99 9 gt The IC is compatible with virtually all QPSK demodulators Orderin Information The MAX2120 includes fully monolithic VCOs as well as PART TEMP RANGE PIN PACKAGE a complete frequency synthesizer Additionally
10. BBG 2 Status Byte 1 VASA VASE LD Status Byte 2 0 Set to 0 for factory tested operation 1 Set to 1 for factory tested operation X Don t care VCOSBRI4 Table 2 N Divider MSB Register BIT NAME BIT LOCATION 0 LSB DEFAULT VCOSBR 3 VCOSBR 2 VCOSBR 1 FUNCTION VCOSBR 0 ADC 2 X 7 X 000001 1 Table 3 N Divider LSB Register BIT NAME BIT LOCATION 0 lt LSB DEFAULT Don t care Sets the most significant bits of the PLL integer divide number N Default value is N 2 950 decimal N can range from 16 to 2175 FUNCTION N 7 0 7 0 10 10110110 Sets the least significant bits of the PLL integer divide number N Default value is N 2 950 decimal N can range from 16 to 2175 MAKILA Complete Direct Conversion Tuner for DVB S and Free to Air Applications Table 4 Charge Pump Register BIT NAME BIT LOCATION 0 LSB DEFAULT FUNCTION Charge pump minimum pulse width Users must program to 00 upon powering up the device CPMP 1 0 Controls charge pump linearity CPLIN 1 0 d 00 lt Typically balanced charge and sink currents Other values are not tested X Don t care Table 5 XTAL Buffer and Reference Divider Register BIT NAME BIT LOCATION 0 LSB DEFAULT FUNCTION Sets the crystal divider setting 000 Divide by 1 default 001 Divide by 2 011 Divide by 3
11. C read when the VCO autoselect mode VAS is disabled 0 Disables ADC read 1 Enables ADC read Table 8 Lowpass Filter Register BIT NAME BIT LOCATION 0 LSB DEFAULT FUNCTION Sets the baseband lowpass filter 3dB corner frequency 3dB corner frequency 4MHz LPF 7 0 12 x 290kHz LPF 7 0 7 0 01001011 Table 9 Control Register BIT NAME BIT LOCATION 0 lt LSB DEFAULT FUNCTION Software standby control O lt Normal operation STBY 1 lt Disables the signal path and freguency synthesizer leaving only the 2 wire bus crystal oscillator XTALOUT buffer and XTALOUT buffer divider active X Don t care Factory use only O lt Normal operation other value is not tested Don t care X Baseband gain setting 1dB typical per step BBG 3 0 0000 Minimum gain OdB 1111 Maximum gain 15dB typical 12 MAXIM Complete Direct Conversion Tuner for DVB S and Free to Air Applications Table 10 Shutdown Register BIT LOCATION 0 LSB Don t care PLL enable 0 Normal operation 1 Shuts down the PLL Value not tested Divider enable O Normal operation 1 Shuts down the divider Value not tested VCO enable 0 Normal operation 1 Shuts down the VCO Value not tested Baseband enable O lt Normal operation 1 Shuts down the baseband Value not tested RF mixer enable 0 Normal operation 1 Shuts down the RF mixer Value not tested RF VGA
12. Complete Direct Conversion Tuner for DVB S and Free to Air Applications AC ELECTRICAL CHARACTERISTICS continued MAX2120 Evaluation Kit Vec 3 13V to 3 47V Vac1 0 5V max gain TA 0 C to 70 C Default register settings except BBG 3 0 1011 Typical values measured at Vcc 3 3V TA 25 C unless otherwise noted Note 1 PARAMETER CONDITIONS MIN TYP MAX UNITS VOLTAGE CONTROLLED OSCILLATOR AND LO GENERATION Guaranteed LO Frequency Range TA 0 C to 70 C MHz OFFSET 10kHz LO Phase Noise foFFSET 100kHz dBc Hz OFFSET 1MHz XTAL REFERENCE OSCILLATOR INPUT AND OUTPUT BUFFER XTAL Oscillator Frequency Range Parallel resonance mode crystal Note 8 Input Overdrive Level AC coupled sine wave input XTAL Output Buffer Divider Range TAL Output Voltage Swing 4MHz to 30MHz CLOAD 10pF XTAL Output Duty Cycle Note 1 Min max values are production tested at TA 70 C Min max limits at TA 0 C and TA 25 C are guaranteed by design and characterization Note 2 Gain control range specifications met over this band Note 3 In band IIP3 test conditions GC1 set to provide the nominal baseband output drive when mixing down a 23dBm tone at 2175MHz to 5MHz baseband fi o 2170MHz Baseband gain is set to its default value BBG 3 0 lt 1011 Two tones at 26dBm each are applied at 2174MHz and 2175MHz The IM3 tone at 3MHz is measured at baseband but is referred to
13. Hz Vac1 1 2V TA 25 C Default register settings except BBG 3 0 1011 STANDBY MODE SUPPLY CURRENT SUPPLY CURRENT SUPPLY CURRENT vs SUPPLY VOLTAGE vs SUPPLY VOLTAGE vs BASEBAND FILTER CUTOFF FREQUENCY 98 A 2 900 E 104 A 9 Ta 470 C S S 102 S Ge SE 2 100 z a z E 95 E z gu Ta 242570 Seil nec a S ps E S 29 5 2 600 5 4 zZ o z z a a 92 Es 85 2 500 a o 91 e a 90 90 Ta 07 Sen Ta 0 C 25 C 88 89 86 88 2 300 84 30 31 32 33 34 35 36 30 31 32 33 34 35 36 4 8 12 16 20 24 28 32 36 40 SUPPLY VOLTAGE V SUPPLY VOLTAGE V BASEBAND FILTER CUTOFF FREQUENCY MHz QUADRATURE MAGNITUDE MATCHING HD3 vs OUTPUT VOLTAGE QUADRATURE PHASE vs LO FREQUENCY vs LO FREQUENCY 10 z 93 5 B 10 3 zs E BASEBAND 10MHz 8 m BASEBAND 10MHz 8 a 15 S s amp 08 s a 92 5 2 E z 20 E 25 C Z 0 6 E S 5 uj 915 z 04 E 2 mu T 30 T a 02 amp a 905 3 2 35 x 0 C d 4 89 5 S je S 4 S S 3 88 5 04 55 pr amp 50 S 06 Gi a Hs 3 48 60 86 5 1 0 10 15 20 25 3 0 35 900 1200 1500 1800 2100 2400 900 1200 1500 1800 2100 2400 Vout Vp p LO FREQUENCY MHz LO FREQUENCY MHz QUADRATURE PHASE
14. QUADRATURE MAGNITUDE MATCHING vs BASEBAND FREQUENCY vs BASEBAND FREQUENCY 93 5 8 0 8 fio 925MHz E fLo 925MHz 925 E S E Ta 70 C 2 915 S Lu 2 E ES Lu a 905 a a LE E 425 C 89 5 A Ta 0 C 2 ST LI S 885 5 z 87 5 2 a CH 86 5 0 0 4 8 12 16 20 0 4 8 12 16 20 BASEBAND FREQUENCY MHz BASEBAND FREQUENCY MHz MAXIM 5 OcCLOCXVIWN MAX2120 Complete Direct Conversion Tuner for DVB S and Free to Air Applications Typical Operating Characteristics continued MAX2120 Evaluation Kit Vcc 3 3V baseband output frequency 5MHz Vac1 1 2V TA 25 C Default register settings except BBG 3 0 1011 BASEBAND FILTER BASEBAND FILTER HIGHPASS FREQUENCY RESPONSE FREQUENCY RESPONSE 5 2 8 1 s 0 S g J SC 3 T Es 30 A 2 5 o a 5 4 5 6 CX Les za 2 s ea ca 2 E g 3 2 10 7 12 80 14 0 20 40 60 80 100 1000 0 000 BASEBAND FREQUENCY MHz BASEBAND FREQUENCY MHz PROGRAMMED f 3qp FREQUENCY BASEBAND FILTER 3dB FREQUENCY vs MEASURED Lo FREQUENCY vs TEMPERATURE 7 0 12 Lg AMHz 290kH E NORMALIZED TO Ta 25 C B B g 2 E 5 3 s Ke CO lt bes tr E lt 3 LL cc Es amp e 8 Ed
15. acitor connected as close as possible to the pin Do not share capacitor ground vias with other ground connections VCC_RF1 DC Power Supply for LNA Connect to a 3 3V low noise supply Bypass to GND with a 1nF capacitor connected as close as possible to the pin Do not share capacitor ground vias with other ground connections GND Ground Connect to the board s ground plane for proper operation Wideband 75Q RF Input Connect to an RF source through a DC blocking capacitor RF Gain Control Input High impedance analog input with a 0 5V to 2 7V operating range Vac1 0 5V corresponds to the maximum gain setting DC Power Supply for LO Generation Circuits Connect to a 3 3V low noise supply Bypass to GND with a 1nF capacitor connected as close as possible to the pin Do not share capacitor ground vias with other ground connections VCC_VCO DC Power Supply for VCO Circuits Connect to a 3 3V low noise supply Bypass to GND with a 1nF capacitor connected as close as possible to the pin Do not share capacitor ground vias with other ground connections VCOBYP Internal VCO Bias Bypass Bypass to GND with a 100nF capacitor connected as close as possible to the pin Do not share capacitor ground vias with other ground connections VTUNE High Impedance VCO Tune Input Connect the PLL loop filter output directly to this pin with as short of a connection as possible GNDTUNE GNDSYN Ground for VTUNE Conn
16. ation Use controlled impedance on all high frequency traces For proper operation the exposed paddle must be soldered evenly to the board s ground plane Use abundant vias beneath the exposed paddle for maximum heat dissipation Use abundant ground vias between HF traces to minimize undesired coupling Bypass each Vcc pin to ground with a 1nF capacitor placed as close as possible to the pin MAXIM Complete Direct Conversion Tuner for DVB S and Free to Air Applications LLL Typical Operating Circuit SERIAL DATA INPUT OUTPUT SERIAL CLOCK U INPUT 126 qe dM oe ael IDC MAXIN DC OFFSET E S INTERFACE LOGIC MAX2120 Gel Eyee ari AND CONTROL SS tour CONTROL at H gt IOUT voc n2 BASEBAND RF INPUT i mm IN ch OUTPUTS H gt QOUT 6C1 jase FREQUENCY 1 VCC DIG VCC_LO SYNTHESIZER ses Vec vec vco REFOUT dl d Slab 19 Oz iIZXVIN MAX2120 Complete Direct Conversion Tuner for DVB S and Free to Air Applications PROCESS BICMOS 20 Chip Information Package Information For the latest package outline information and land patterns go to www maxim ic com packages Note that a or in the package code indicates RoHS status only Package draw ings may show a different suffix character but the drawing per tains to the package regardless o
17. can be used for checking the lock status of the VCOs Table 15 summarizes the ADC trip points and the VCO lock indication The VCO autoselect routine will only select a VCO in the VAS locked range This allows room for a VCO to drift over temperature and remain in a valid locked range The ADC must first be enabled by setting the ADE bit in the VCO register The ADC reading is latched by a sub sequent programming of the ADC latch bit ADL lt 1 The ADC value is reported in the Status Byte 2 register see Table 13 Table 15 ADC Trip Points and Lock Status ADC 2 0 LOCK STATUS Out of Lock Locked VAS Locked VAS Locked Locked Out of Lock 18 Standby Mode The MAX2120 features normal operating mode and standby mode using the 12C interface Setting a logic high to the PWDN bit in the Control register enables power down In this mode all circuitries except for the 2 wire compatible bus are disabled allowing for program ming of the MAX2120 registers while in power down In all cases register settings loaded prior to entering shutdown are saved upon transition back to active mode Default register values are provided for the user s convenience only It s the user s responsibility to load all the registers no sooner than 100ys after the device is powered up Layout Considerations The MAX2120 EV kit serves as a guide for PCB layout Keep HF signal lines as short as possible to mini mize losses and radi
18. ced to the MAX2120 s Vcc START and STOP Conditions The master initiates a transmission with a START condi tion S which is a high to low transition on SDA while SCL is high The master terminates a transmission with a STOP condition P which is a low to high transition on SDA while SCL is high Acknowledge and Not Acknowledge Conditions Data transfers are framed with an acknowledge bit ACK or a not acknowledge bit NACK Both the mas ter and the MAX2120 slave generate acknowledge bits To generate an acknowledge the receiving device must pull SDA low before the rising edge of the acknowledge related clock pulse ninth pulse and keep it low during the high period of the clock pulse To generate a not acknowledge condition the receiver allows SDA to be pulled high before the rising edge of the acknowledge related clock pulse and leaves SDA high during the high period of the clock pulse Monitoring the acknowledge bits allows for detection of unsuccessful data transfers An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred In the event of an unsuc cessful data transfer the bus master must reattempt communication at a later time MAXIM Slave Address The MAX2120 has a 7 bit slave address that must be sent to the device following a START condition to initi ate communication The slave address is internally pro grammed to 1100000 The eighth bit R W following the 7 bit a
19. dBm IN BAND IIP3 vs INPUT POWER IIP2 vs INPUT POWER OTE 3 ON PAGE 4 FOR CONDITIONS E OTE 5 ON PAGE 4 FOR CONDITIONS 3 CO p S a Li z ge 80 70 60 50 40 30 20 10 0 80 70 60 50 40 30 20 10 0 INPUT POWER dBm INPUT POWER dBm PHASE NOISE AT 10kHz OFFSET INPUT RETURN LOSS vs FREQUENCY vs CHANNEL FREQUENCY 0 S 70 z s S 2 8 5 B S 4 S D 6 2 uc S 40 su S z 5 80 45 e P E GO z S A4 LLI 20 2 86 E 88 25 90 900 1125 1350 1575 1800 2005 2250 925 1115 1305 1495 1685 1875 2065 2255 FREQUENCY MHZ CHANNEL FREQUENCY MHz MAXIM 7 OcCLOCXVIW MAX2120 Complete Direct Conversion Tuner for DVB S and Free to Air Applications Typical Operating Characteristics continued MAX2120 Evaluation Kit Vcc 3 3V baseband output frequency 5MHz Vac1 1 2V TA 25 C Default register settings except BBG 3 0 1011 PHASE NOISE vs OFFSET FREQUENCY LO LEAKAGE vs LO FREQUENCY 70 VCC_RF2 flo 1800MHz E MEASURED AT RF INPUT 3 z z PE 75 F 80 g k z uu 90 Lu 2 80 m 100 S z 3 110 ge 120 130 90 04 10 100 1000 925 1175 1425 1675 1925 2175 OFFSET FREQUENCY kHz LO FREQUENCY MHz Pin Description FUNCTION DC Power Supply for LNA Connect to a 3 3V low noise supply Bypass to GND with a 1nF cap
20. ddress determines whether a read or write operation will occur The MAX2120 continuously awaits a START condition followed by its slave address When the device recog nizes its slave address it acknowledges by pulling the SDA line low for one clock period it is ready to accept or send data depending on the R W bit Figure 1 The write read address is CO C1 if the ADDR pin is con nected to ground The write read address is C2 C3 if the ADDR pin is connected to Vcc SLAVE ADDRESS Figure 1 MAX2120 Slave Address Byte with ADDR Pin Connected to Ground Write Cycle When addressed with a write command the MAX2120 allows the master to write to a single register or to multi ple successive registers A write cycle begins with the bus master issuing a START condition followed by the seven slave address bits and a write bit R W 0 The MAX2120 issues an ACK if the slave address byte is successfully received The bus master must then send to the slave the address of the first register it wishes to write to see Table 1 for register addresses If the slave acknowl edges the address the master can then write one byte to the register at the specified address Data is written beginning with the most significant bit The MAX2120 again issues an ACK if the data is successfully written to the register The master can continue to write data to the successive i
21. ect to the PCB ground plane Ground for Synthesizer Connect to the PCB ground plane CPOUT Charge Pump Output Connect this output to the PLL loop filter input with the shortest connection possible MAXIM Complete Direct Conversion Tuner for DVB S and Free to Air Applications Pin Description continued NAME FUNCTION DC Power Supply for Synthesizer Circuits Connect to a 3 3V low noise supply Bypass to GND with VCC SYN a 1nF capacitor connected as close as possible to the pin Do not share capacitor ground vias with other ground connections Crystal Oscillator Interface Use with an external parallel resonance mode crystal by a series 1nF capacitor See the Typical Operating Circuit Crystal Oscillator Buffer Output A DC blocking capacitor must be used when driving external circuitry DC Power Supply for Digital Logic Circuits Connect to a 3 3V low noise supply Bypass to GND VCC DIG with a 1nF capacitor connected as close to the pin as possible Do not share capacitor ground vias with other ground connections QOUT QOUT Quadrature Baseband Differential Output AC couple with a 47nF capacitor to the demodulator input In Phase Baseband Differential Output AC couple with a 47nF capacitor to the demodulator input Channel baseband DC Offset Correction Connect a 47nF ceramic chip capacitor from IDC to IDC QDC Q Channel Baseband DC Offset Correction Connect a 47nF cera
22. f RoHS status PACKAGE PACKAGE OUTLINE LAND TYPE CODE NO PATTERN NO 28 TQFN T285543 21 0140 90 0023 MAXIM Complete Direct Conversion Tuner for DVB S and Free to Air Applications Revision History REVISION REVISION PAGES NUMBER DATE DESCRIPTION CHANGED 0 Initial release Corrected errors in data sheet replaced Read Cycle section and Figure 3 added Table 14 ER Corrected D24 bit Function in Table 6 11 OcCLOCXVIN Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 21 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
23. igure 3 illustrates an example in which registers O through 2 are read back WRITE DEVICE ADDRESS WRITE REGISTER WRITE DATA TO REGISTER ADDRESS 0x00 WRITE DATA WRITE DATA TO REGISTER TO REGISTER 0x01 0x02 1100000 0x00 OxOE OxD8 OxOE1 DEVICE ADDRESS 1100000 REGISTER ADDRESS Figure 3 Example Receive data from read registers 16 MAXIM Complete Direct Conversion Tuner for DVB S and Free to Air Applications Applications Information The MAX2120 downconverts RF signals in the 925MHz to 2175MHz range directly to the baseband UO signals The devices are targeted for digital DBS tuner applications RF Input The RF input of the MAX2120 is internally matched to 750 Only a DC blocking capacitor is needed See the Typical Operating Circuit RF Gain Control The MAX2120 features a variable gain low noise amplifi er providing 73dB of RF gain range The voltage control VGC range is 0 5V minimum attenuation to 2 7V maximum attenuation Baseband Variable Gain Amplifier The receiver baseband variable gain amplifiers provide 15dB of gain control range programmable in 1dB steps The VGA gain can be serially programmed through the SPITM interface by setting bits BBG 3 0 in the Control register Baseband Lowpass Filter The MAX2120 includes a programmable on chip 7th order Butterworth filter The 3dB corner frequency of the baseband filter is pr
24. mic chip capacitor from QDC to QDC QDC DC Power Supply for Baseband Circuits Connect to a 3 3V low noise supply Bypass to GND with a VCC_BB 1nF capacitor connected as close as possible to the pin Do not share capacitor ground vias with other ground connections SDA 2 Wire Serial Data Interface Requires a 1kQ pullup resistor to Vcc SCL 2 Wire Serial Clock Interface Requires a gt 1kQ pullup resistor to Vec ADDR Address ADDR is at logic high if unconnected EP Exposed Paddle Solder evenly to the board s ground plane for proper operation MM d Slab 9 OcLOCXVIN Complete Direct Conversion Tuner for DVB S and Free to Air Applications figurations The register configuration of Table 1 shows each bit name and the bit usage information for all regis ters Note that all registers must be written after and no Detailed Description Register Description MAX2120 The MAX2120 includes 12 user programmable registers and 2 read only registers See Table 1 for register con Table 1 Register Configuration REG REGISTER NAME REG ADDRESS earlier than 100us after the device is powered up DATA BYTE D 4 N Divider MSB N Divider LSB 0x00 N 12 NI4 Charge Pump CPLIN O Not Used Not Used XTAL Divider R Divider VCO 2 VCO 1 VCO 0 LPF 5 LPF 4 LPF 3 LPF 2 Test CPTST 1 0 PWDN CPTSTI0 0 BBG 3
25. nternal registers with the MAX2120 acknowledging each successful transfer or it can ter minate transmission by issuing a STOP condition The write cycle will not terminate until the master issues a STOP condition 15 OcCLOCXVIN MAX2120 Complete Direct Conversion Tuner for DVB S and Free to Air Applications Figure 2 illustrates an example in which registers O through 2 are written with OxOE OxD8 and OxE1 respectively Read Cycle When addressed with a read command the MAX2120 allows the master to read back a single register or mul tiple successive registers A read cycle begins with the bus master issuing a START condition followed by the 7 slave address bits and a write bit R W 0 The MAX2120 issues an ACK if the slave address byte is successfully received The bus master must then send the adaress of the first register it wishes to read see Table 1 for register addresses The slave acknowledges the address Then a START condi tion is issued by the master followed by the 7 slave address bits and a read bit RW 1 The MAX2120 issues an ACK if the slave address byte is successfully received The MAX2120 starts sending data MSB first with each SCL clock cycle At the 9th clock cycle the master can issue an ACK and continue to read succes sive registers or the master can terminate the transmis sion by issuing a NACK The read cycle does not terminate until the master issues a STOP condition F
26. ogrammable by setting the bits LPF 7 0 in the Lowpass register The value of the LPF 7 0 is determined by the following equation LPF 7 0jdec 288 AMPH 45 0 29MHz where f agB is in units of MHz The filter can be adjusted from approximately 4MHz to 40MHz Total device supply current depends on the fil ter BW setting with increasing current commensurate with increasing 3dB BW DC Offset Cancellation The DC offset cancellation is required to maintain the I Q output dynamic range Connecting an external capacitor between IDC and IDC forms a highpass filter for the channel and an external capacitor between QDC and QDC forms a highpass filter for the Q channel Keep the value of the external capacitor less than 47nF to form a typical highpass corner of 400Hz SPI is a trademark of Motorola Inc MAXIM XTAL Oscillator The MAX2120 contains an internal reference oscillator reference output divider and output buffer All that is required is to connect a crystal through a series 1nF capacitor To minimize parasitics place the crystal and series capacitor as close as possible to pin 14 XTAL pin See Table 14 for crystal XTAL ESR equivalent series resistance requirements The typical input capacitance is 40pF VCO Autoselect VAS The MAX2120 includes 24 VCOs The local oscillator fre quency can be manually selected by programming the VCO 4 0 bits in the VCO register The selected VCO is reported in the Stat
27. us Byte 2 register see Table 13 Alternatively the MAX2120 can be set to autonomously choose a VCO by setting the VAS bit in the VCO regis ter to logic high The VAS routine is initiated once the N divider LSB register word REG 2 is loaded In the event that only the R divider register or N divider MSB register word is changed the N divider LSB word must also be loaded last to initiate the VCO autoselect function The VCO value pro grammed in the VCO 4 0 register serves as the start ing point for the automatic VCO selection process During the selection process the VASE bit in the Status Byte 1 register is cleared to indicate the autoselection function is active Upon successful completion bits VASE and VASA are set and the VCO selected is reported in the Status Byte 2 register see Table 13 If the search is unsuccessful VASA is cleared and VASE is set This indicates that searching has ended but no good VCO has been found and occurs when trying to tune to a frequency outside the VCO s specified frequency range Refer to the MAX2112 MAX2120 VAS application note for more information Table 14 Maximum Cystal ESR Requirements ESRMAX 9 XTAL FREQUENCY MHz 6 lt fxTAL lt 8 8 lt fxTaL s 13 5 17 OcCLOCXVIW MAX2120 Complete Direct Conversion Tuner for DVB S and Free to Air Applications 3 Bit ADC The MAX2120 has an internal 3 bit ADC connected to the VCO tune pin VTUNE This ADC
28. x O a a d amp a z a 0 5 10 15 20 25 30 35 40 45 0 10 20 30 40 50 60 70 PROGRAMMED f 3qg FREQUENCY MHz TEMPERATURE C INPUT POWER vs Vgci NOISE FIGURE vs FREQUENCY 10 10 0 S ADJUST BBG 3 0 FOR 1Vp p E ADJUST BBG 3 0 FOR 1Vp p E BASEBAND OUTPUT WITH E BASEBAND OUTPUT WITH E un LPivz 75dBm AND Vac1 05V 95 L n 75dBm AND Ve 0 5V s a s TA TC 470 Ta 0 3 Ti 425 C Ta 470 C g 90 z EA Te s M 2 85 gt ce 7 z 5 6 8 0 7 8 15 0 5 10 15 20 25 30 900 1100 1300 1500 1700 1900 2100 2300 Vect V FREQUENCY MHz 6 MAKLM Complete Direct Conversion Tuner for DVB S and Free to Air Applications Typical Operating Characteristics continued MAX2120 Evaluation Kit Vcc 3 3V baseband output frequency 5MHz Vac1 1 2V TA 25 C Default register settings except BBG 3 0 1011 NOISE FIGURE vs INPUT POWER OUT OF BAND IIP3 vs INPUT POWER 70 S s ADJUST BBGI3 0 FOR 1Vp p E SEE NOTE 4 ON PAGE 4 FOR CONDITIONS E go LBASEBAND OUTPUT WITH s 8 Pin 75dBm AND Ver 0 5V 3 fio 1500MHz s 50 5 m u a E 40 SS EC Es s 30 i e o 9 20 8 10 0 80 70 60 50 40 30 20 10 0 80 70 60 50 40 30 20 10 0 INPUT POWER dBm INPUT POWER
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MAXIM MAX2120 Complete Direct Conversion Tuner for DVB S Free to Air Applications handbook