MAXIM MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA handbook
Contents
1. LO PHASE NOISE CHANNEL SWITCHING FREQUENCY LO FREQUENCY vs VTUNE vs OFFSET FREQUENCY SETTLING FROM 2500 2400MHz 2600 5 50 2831 32 10055 2550 3 cm 8 250 S I amp 245 DB 10 10 2 8 2 div E 2400 2 amp amp 12 2350 13 14 230 45 50kHz 02 04 06 08 1 0 12 14 16 18 20 22 24 0 001 01 01 0 0 250 5 V OFFSET FREQUENCY MHz PLL SETTLING TIME FROM PLL SETTLING TIME Rx TO Tx TURNAROUND SHUTDOWN TO STANDBY MODE FROM STANDBY TO Tx PLL SETTLING TIME 50 2831 32 056 50 2831 32 10657 25kHz 2831 32 10058 i 10kHz dne 10kHz w n Wed div div i p f 50kHz 50kHz 25kHz 0 2ms 0 30us 0 50 5 CRYSTAL OSCILLATOR OFFSET FREQUENCY Tx Rx TURNAROUND PLL SETTLING TIME CLOCK OUTP2. 20 20 g 20 5 18 E 18 8 18 16 16 E 16 14 14 14 ET A 405 12 1 12 c ce c Lu E 10 10 10 8 08 amp 08 amp 08 ir 06 5 06 5 06 Ta AC 42520 04 04 04 02 02 02 0 0 0 0 2 4 6 8 10 12 14 16 18 20 22 0 2 4 6 8 10 12 14 16 18 20 22 0 2 4 6 8 10 12 14 16 18 20 22 OUTPUT POWER dBm OUTPUT POWER dBm Pout dBm PA OUTPUT POWER HISTORGRAM POWER DETECTOR OUTPUT PA OUTPUT ENVELOPE RESPONSE FOR 1 14 POWER DETECTOR OUTPUT ENVELOPE I MEAN 18 5dBm 8 10 8 TXIQINPUT 1 4 POWER DETECTOR I i 3 2 E 2 i 0 100ns div 1us div 0 1dB div PA OUTPUT RETURN LOSS vs RF FREQUENCY Tx OUTPUT SPURS 1 0 1 0 2831 32 toc52 RBW 1MHz 8 802 110 SIGNAL 45 10 2 E S 3 m 4 5 a S 25 5 7 8 30 90 2300 2350 2400 2450 2500 2550 2600 DC 26 5GHz RF FREQUENCY MHz 16 MAXI 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Typical Operating Characteristics continued MAX2831 EV kit Vcc_ 2 8V VCCPA VCCTXPA 3 3V TA 25 C fi o 2 437 2 fReF 40MHz SHDN CS high RXHP SCLK DIN low
3. NOISE FIGURE Rx VOLTAGE GAIN Rx Icc vs Vec vs BASEBAND GAIN SETTINGS vs BASEBAND GAIN SETTING 5 45 10 8 4 5 90 LNA HIGH GA LNA LOW GAIN E 8 8 z 35 E 7 3 zz 6 25 8 LNA MEDIUM GAIN 5 5 Es 2 15 3 LNA MEDIUM GAIN 1 LNA HIGH GAIN 2 5 1 LNA LOW GAI 21 28 29 30 31 32 33 34 35 36 0 2 4 6 8 101214 16 18 20 22 24 26 28 30 32 0 2 4 6 8 1012 14 16 18 20 22 24 26 28 30 32 Voc V BASEBAND GAIN SETTINGS BASEBAND GAIN SETTINGS Rx IN BAND OUTPUT 14 vs GAIN Rx EVM vs Pin Rx EVM vs Vout 0 22 8 30 3 5 HIGH GAIN LNA LOW GAIN 50dBm 5 8 5 3E GH GAIN B 18 LNA MEDIUM GAI 16 E 5 z 7 LNA MEDIUM HIGH i amp GAIN SWITCH POIN 14 3 ES gt LNA MEDIUM LOW a GAIN SWITCH POINT a 2 8 10 8 5 6 4 6 0 5 2 7 0 0 5 25 35 45 55 75 85 5 80 70 60 50 40 30 20 40 0 29 27 25 23 21 19 17 15 13 11 9 GAIN dB dBm Vour OFDM EVM WITH OFDM JAMMER LNA INPUT RETURN LOSS vs OFFSET FREQUENCY Rx EMISSION SPECTRUM LNA INPUT vs RF FREQUENCY 15 4 2831 32 1008 5 14 FPiy 62dBm 4 RBW 300kH 13 foreser 20MHz 5 cz 5 LNA LOW GAIN 5 12 S14 2 10 z Slo z 11 2 10 8 18 o 9 forrser 25M 5 8 15 55 8 7 rT 5 2 6 20 5 5 4 3 25 2 1 0 30 65 55 45 35 25 DC 26 5GH
4. RX TX GAIN EFERENCE RX TX GAIN CONTROL CLOCKBUFFER CONTROL OUTPUT NOTE ALL GROUND PINS 2 26 AND 31 AND BYPASS CAPACITORS GROUND REQUIRE THEIR OWN VIAS TO GROUND DO NOT CONNECT THEM TO THE EXPOSED PADDLE GROUND 18 MAXIM 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Block Diagrams Typical Operating Circuits continued RX BASEBAND HPF CORNER FREQUENCY CONTROL RX OUTPUTS 1 o 0 VCCRXVGA MAXIM RXQ GNDRXLNA MAX2832 RXBBO OUTPUTS RX TX B4 RX TX GAIN GAIN CONTROL CONTROL RX INPUT gt BYPASS GNDVCO RX GAIN CONTROL IMUX QMUX x GAIN TX OUTPU CONTROL DETECTO CRYSTAL lt H OSCILLATOR BUFFER JE RXITX GAIN CONTROL EMP SENSOR MODE CONTROL RSS I RX TX GAIN EFERENCE GAIN CONTROL UFFER CONTROL UT NOTE ALL GROUN
5. 260 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability CAUTION ESD SENSITIVE DEVICE DC ELECTRICAL CHARACTERISTICS MAX2831 EV kit Vcc_ 2 7V to 3 6V VCCTXPA 2 7V to 4 2V TA 40 C to 85 C Rx set to the maximum gain CS high RXHP SCLK DIN low RSSI and clock output buffer are off no signal at RF inputs all RF inputs and outputs terminated into 500 receiver baseband outputs are open 100mVRws differential and Q signals 54Mbps 802 110 OFDM applied to 1 baseband inputs of transmitter in transmit mode fREF 40MHz and registers set to recommended settings and corresponding test mode unless otherwise noted Typical values are at Vcc 2 8V 3 3V and Ta 25 C LO frequency 2 437GHz unless otherwise noted RF inputs outputs and SMA connectors Note 1 PARAMETERS Supply Voltage Vcc_ CONDITIONS specifications are referenced to device pins and do not include 1dB loss from EV kit PCB balun VCCPA VCCTXPA Supply Current Shutdown mode B7 B1 0000000 reference osc
6. 78 27 28 23 30 31 32 33 34 35 36 Voc V HISTOGRAM Tx OUTPUT POWER VARIATION MEAN 18 5dBm GAIN ADJUSTED TO ACHIEVE 5 6 EVM 2831 32 1033 0 148 Tx OUTPUT POWER vs GAIN SETTING MAX2832 ONLY a MAX2831 32 toc36 0 4 8 12162024 28 32 36 40 44 48 52 56 60 64 GAIN SETTINGS MAKLM 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Typical Operating Characteristics continued MAX2831 EV kit Vcc_ 2 8V VCCPA VCCTXPA 3 3V TA 25 C fLo 2 437 2 fReF 40MHz SHDN CS high RXHP SCLK DIN low EVM vs Tx OUTPUT POWER 11g SPECTRAL MASK Tx OUTPUT SPURS MAX2832 ONLY MAX2832 ONLY MAX2832 ONLY 3 00 10 2831 32 10 38 275 5 20 250 2 s 40 2 2 25 50 2 00 60 1 75 70 1 50 80 90 1 25 100 1 00 110 30 24 18 42 6 0 2387 247 247 247 247 2487 DC 26 5GHz OUTPUT POWER dBm FREQUENCY MHz Tx GA
7. Transmitter Upconverter Supply Voltage 1 SCLK Serial Clock Logic Input of 3 Wire Serial Interface See Figure 2 4103 011 DIN Data Logic Input of 3 Wire Serial Interface See Figure 2 VCCPLL PLL and Registers Supply Voltage Connect to the supply voltage to retain the register settings CLOCKOUT Reference Clock Buffer Output Lock Detect Logic Output of Frequency Synthesizer Output high indicates that the frequency synthesizer is locked Output programmable as CMOS or open drain output See Tables 16 and 20 N Receiver and Transmitter Gain Control Logic Input Bit 1 Charge Pump Output Connect the frequency synthesizer s loop filter between CPOUT and TUNE see the Block Diagrams Typical Operating Circuits PLL Charge Pump Supply Voltage Charge Pump Circuit Ground Crystal Oscillator Supply Voltage XTAL Crystal or Reference Clock Input AC couple a crystal or a reference clock to this analog input Connection for Crystal Oscillator Off Chip Capacitors When using an external reference clock input CTUNE leave CTUNE unconnected VCCVCO VCO Supply Voltage GNDVCO VCO Ground TUNE VCO TUNE Input see the Block Diagrams Typical Operating Circuits On Chip VCO Regulator Output Bypass Bypass with a 0 1uF to 1uF capacitor to GND Do not BYPASS connect other circuitry to this point B4 Receiver and Transmitter Gain
8. MAKII 2 4GHz to 2 5GHz 802 11 g b RF Transceivers with Integrated PA General Description The MAX2831 MAX2832 direct conversion zero IF RF transceivers are designed specifically for 2 4GHz to 2 5GHz 802 11g b WLAN applications The MAX2831 completely integrates all circuitry required to implement the RF transceiver function providing an RF power amplifier PA RF to baseband receive path baseband to RF transmit path VCO frequency synthesizer crystal oscillator and baseband control interface The MAX2832 integrates the same functional blocks except for the PA Both devices include a fast settling sigma delta RF syn thesizer with smaller than 20Hz frequency steps and a digitally tuned crystal oscillator allowing use of a low cost crystal The devices also integrate on chip DC offset cancellation and I Q errors and carrier leakage detection circuits Only an RF bandpass filter BPF crystal RF switch and a small number of passive components are needed to form a complete 802 110 0 WLAN RF front end solution The MAX2831 MAX2832 completely eliminate the need for an external SAW filter by implementing on chip mono lithic filters for both the receiver and transmitter The baseband filters are optimized to meet the IEEE 802 119 standard and proprietary turbo modes up to 40MHz channel bandwidth These devices are suitable for the full range of 802 11g OFDM data rates 6Mbps to 54Mbps and 802 11b QPSK and CCK data rates 1Mbps t
9. C inimum gain B7 B1 0000000 Total Voltage Gain TA 25 C From high gain mode B7 B6 11 to medium gain mode B7 B6 10 RF Gain Steps Note 3 From high gain mode B7 B6 11 to low gain mode B7 B6 0X Gain change from high gain to medium gain high gain to RF Gain Change Settling Time low or medium gain to low gain gain settling to within 2dB of steady state RXHP 1 MAXL 3 CE8TXVYNW LE8SZXVIN MAX2831 MAX2832 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA AC ELECTRICAL CHARACTERISTICS Rx Mode continued 2831 EV kit Vcc_ 2 8V VCCPA 3 3V 25 C fnr 2 439GHz fLo 2 437GHZz receiver baseband I Q out puts at 112 mVams 19dBV fREF 40MHz SHDN CS high RXTX SCLK DIN low with power matching for the differential RF pins using the typical applications and registers set to default settings and corresponding test mode unless otherwise noted Unmodulated single tone RF input signal is used with specifications which normally apply over the entire operating conditions unless otherwise indicated RF inputs outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB balun and SMA connectors Note 1 PARAMETER CONDITIONS Baseband Gain Range From maximum baseband gain B5 B1 11111 to minimum baseband gain B5 B1 00000 DSB Noise Figure Voltage gain
10. Set to recommended value 000000 Transmitter VGA Gain Control Set D5 DO 000000 for minimum gain and set 05 00 111111 for maximum gain Table 28 Register 13 A3 A0 1101 D13 D10 RECOMMENDED 0011 DESCRIPTION Set to recommended value D9 D6 1010 Set to recommended value 30 D5 DO 010010 Set to recommended value MAXIM 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Table 29 Register 14 A3 A0 1110 BIT RECOMMENDED DESCRIPTION D13 D11 000 Set to recommended value Do 0 Reference Clock Output Divider Ratio Set 1 to divide by 2 or set 0 to divide by 1 1 Reference Clock Output Enable Set 1 to enable the reference clock output or set 0 to disable 10 Set to recommended value XXXXXXX Crystal Oscillator Fine Tune Tunes crystal oscillator over x20ppm to within x 1ppm X Dont care Table 30 Register 15 A3 A0 1111 BIT RECOMMENDED DESCRIPTION D13 D12 00 Set to recommended value Receiver I Q Output Common Mode Voltage Adjustment Set D11 D10 00 1 1V 01 1 2V 10 1 3V 11 1 45V D9 DO 0101000101 Set to recommended value D11 D10 00 Table 31 Operating Mode Table REGISTER LOGIC PINS SETTINGS CIRCUIT BLOCK STATES PLL VCO Rx PATH Tx PATH LO GEN AUTO TUNER D1 DO 0 0110 CALIBRATION SECTIONS ON Shutdown None Standby None None Cal tone RF phase shift Tx
11. maximum with B7 B6 11 Voltage gain 50dB with B7 B6 11 Voltage gain 45dB with B7 B6 10 Voltage gain 15dB with B7 B6 OX In Band Compression Point Based on EVM 19dBVRMs baseband B7 B6 11 output EVM degrades to B7 B6 10 9 B7 B6 OX dBm In Band Output P 1dB Voltage gain 90dB with B7 B6 11 VP P Out of Band Input IP3 Note 4 B7 B6 11 B7 B6 10 dBm B7 B6 0X 10 Phase Error 16 variation without calibration 10 Gain Imbalance 16 variation without calibration RX I Q Output Load Impedance RII C Minimum differential resistance Degrees Maximum differential capacitance Tx to Rx Conversion Gain for Rx 10 Calibration For receiver gain B7 B1 1101111 Note 5 Baseband VGA Settling Time I Q Output DC Step when RXHP Transitions from 1 to O in Presence of 802 119 Short Sequence I Q Output DC Droop Gain change from B5 B1 10111 to B5 B1 00111 gain settling to within 2dB of steady state After switching RXHP to logic 0 from initial logic 1 during ideal short sequence data at 55dBm input in AWGN channel for 19dBV output normalized to RMS signal on and Q outputs transition point varied from 0 8us in steps of O 1us After switching RXHP to 0 D13 D12 Register 7 A3 A0 0111 I Q Static DC Offset Spurious Signal Emissions from LNA input RXHP 1 B7 B1 1101110 16 variation RF 1GHz to 2
12. 00 for 100Hz X1 for 4kHz and 10 for 30kHz D11 D6 000000 Set to recommended value Transmitter Lowpass Filter Corner Frequency Fine Adjustment Relative to Coarse Setting See Table 8 Bits D1 D0 in A3 A0 1000 provide the lowpass filter corner coarse adjustment D13 D12 01 Receiver Lowpass Filter Corner Frequency Fine Adjustment Relative to Coarse Setting See Table 5 Bits D1 D0 in A3 A0 1000 provide the lowpass filter corner coarse adjustment Table 23 Register 8 A3 A0 1000 RECOMMENDED DESCRIPTION Set to recommended value Enable Receiver Gain Programming Through the Serial Interface Set to 1 to enable programming through the 3 wire serial interface 06 00 in Register A3 A0 1011 Set to 0 to enable programming in parallel through external digital pins 7 1 Set to recommended value RSSI Operating Mode Set to 1 to enable RSSI output independent of RXHP Set to 0 to disable RSSI output if RXHP 0 and enable the RSSI output if RXHP 1 RSSI Power Detector or Temperature Sensor Output Select Set to 00 to enable the RSSI output in receive mode Set to 01 to enable the temperature sensor output in receive and transmit modes Set to 10 to enable the power detector output in transmit mode See Table 7 001000 Set to recommended value Receiver and Transmitter Lowpass Filter Corner Frequency Coarse Adjustment See Tables 4 9 and 7 MAXIM 29 CESSCXVIN LESSCXVIN
13. 1 12 FREQUENCY MHz FREQUE MAXIM 13 MAX2831 MAX2832 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA MAX2831 SCLK DIN low FILTER RESPONSE dB o d X om amp m e 68 14 c HISTOGRAM Rx GAIN IMBALANCE MEAN 0dB STD 0 064dB SAMPLE SIZE 951 1o di HISTOGRAM Tx 10 LEAKAGE MEAN 33 45dBc STD 6 31dB SAMPLE SIZE 999 MAX2831 32 toc28 MAX2831 32 10631 Tx BASEBAND FREQUENCY RESPONSE MAX2831 32 toc34 0 1 1 10 BASEBAND FREQUENCY MHz 100 Pour dBm Typical Operating Characteristics continued HISTOGRAM Rx PHASE IMBALANCE MEAN 0 3 STD 0 314 SAMPLE SIZE 1013 1o di MAX2831 32 toc29 HISTOGRAM Tx SIDEBAND SUPPRESSION MEAN 42dBc STD 1 9dB SAMPLE SIZE 1000 MAX2831 32 toc32 1o div Tx OUTPUT POWER vs FREQUENCY B6 B1 111111 MAX2832 0NLY MAX2831 32 10635 244 FREQUENCY GHz 2 46 Icc mA Pour dBm EV kit Vcc_ 2 8V VCCPA VCCTXPA 3 3V TA 25 C fi o 2 437GHz fREF 40MHz SHDN CS high RXHP Tx Icc vs Vec 88 86 2831 32 1030 84 82 80
14. 9dBm Voltage Short sequence tr itter power 9d Maximum Power Detector Output Voltage Short sequence transmitter power 19dBm RF Power Detector Response Time TRANSMITTER LO LEAKAGE AND I Q CALIBRATION USING LO LEAKAGE AND SIDEBAND DETECTOR see the Calibration Mode section Tx BASEBAND I Q INPUTS TO RECEIVER OUTPUTS Output at 1 x fTONE for LO leakage 29dBc Calibration register fTONE 2MHz 100MVRMS and Sideband D12 D11 00 etector Output 0110 Output at 2 x fTONE for LO leakage 240dBc 2MHz 100mVRMs Amplifier Gain Range D12 D11 00 to D12 D11 11 A3 A0 0110 Lower 3dB Corner Frequency MAXIM 7 CESSCXVIN LESSCXVIN MAX2831 MAX2832 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA AC ELECTRICAL CHARACTERISTICS Frequency Synthesis MAX2831 EV kit Vcc_ 2 7V VCCPA VCCTXPA 3 3V Ta 25 C 2 437GHz fREF 40MHz SHDN CS high DIN low PLL loop bandwidth 150kHz and Ta 25 C unless otherwise noted Note 1 PARAMETER CONDITIONS FREQUENCY SYNTHESIZER RF Channel Center Frequency Channel Center Frequency Programming Minimum Step Size Charge Pump Comparison Frequency Reference Frequency Range Reference Frequency Input Levels AC coupled to XTAL pin Reference Frequency Input Resistance XTAL Impedance R II C Capacitance XTAL foFFSET 1 2
15. Control Logic Input Bit 4 20 AVLAZCLAM NAME 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Pin Description continued FUNCTION RXBBQ RXBBQ RXBBI RXBBI Receiver Baseband Q Channel Differential Outputs In TX calibration mode these pins are the LO leakage and sideband detector outputs Receiver Baseband Channel Differential Outputs In TX calibration mode these pins are the LO leakage and sideband detector outputs VCCRXVGA Receiver VGA Supply Voltage 40 RXHP Receiver Baseband AC Coupling High Pass Corner Frequency Control Logic Input VCCRXFL Receiver Baseband Filter Supply Voltage TXBBQ TXBBQ TXBBI Transmitter Baseband I Channel Differential Inputs Transmitter Baseband Q Channel Differential Inputs 1 2 13 14 TXBBI 5 6 VCCRXMX 7 Receiver Downconverters Supply Voltage RX TX Mode Control Logic Input See Table 31 for operating modes Exposed Paddle Connect to the ground plane with multiple vias for proper operation and heat dissipation Do not share with any other pin grounds and bypass capacitors ground Detailed Description The MAX2831 MAX2832 single chip low power direct conversion zero IF transceivers are designed to support 802 11g b applications operating in the 2 4GHz to 2 5GHz band The fully integrated transceivers include a receive path transmit path voltage controlled oscillator VCO sigma
16. ELECTRICAL CHARACTERISTICS Tx Mode MAX2831 EV kit 2 8V VCCPA VCCTXPA 3 3V TA 25 C fnr 2 439GHz fi o 2 437GHz fReF 40MHz SHDN RXTX CS high and SCLK DIN low with power matching for the differential RF pins using the typical applications circuit 100mVnws sine and cosine signal or 100mVRMs 54Mbps IEEE 802 110 1 signals wherever OFDM is mentioned applied to base band I Q inputs of transmitter differential DC coupled Registers set to recommend settings and corresponding test mode unless otherwise noted RF inputs outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB balun and SMA connectors Note 1 PARAMETER CONDITIONS TRANSMIT SECTION Tx BASEBAND I Q INPUTS TO RF OUTPUTS RF Output Frequency Range Output power adjusted to meet 5 6 EVM and spectral mask B6 B1 000000 54Mbps 802 11g OFDM signal MAX2831 2831 2832 Output Power 802 11b signal 141mVRMs IEEE802 11b I Q signals Output power adjusted to meet spectral mask 3dB VGA back off MAX2832 B6 B1 000000 Unwanted Sideband Suppression Carrier Leakage at Center Frequency of Channel Without I Q calibration B6 B1 100001 Without DC offset correction Transmitter Spurious Signal Emissions MAX2831 Transmitter Spurious Signal Emissions MAX2832 1 3 x fLO lt 1GHz gt 1GHz 2 3 x fLo B
17. MAX2831 MAX2832 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Table 24 Register 9 A3 A0 1001 RECOMMENDED BIT D13 D11 DESCRIPTION Set to recommended value D10 1110110101 Enable Transmitter Gain Programming Through the Serial or Parallel Interface Set to 1 to enable programming through the 3 wire serial interface 05 00 in Register 1011 Set to 0 to enable programming in parallel through external digital pins B6 B1 Set to recommended value Table 25 Register 10 A3 A0 1010 BIT D13 D10 RECOMMENDED DESCRIPTION Power Amplifier Enable Delay Sets a delay between RXTX low to high transition and internal PA enable Programmable in O 5us steps D13 D10 0001 0 2us and D13 D10 1111 7us D9 D7 Set to recommended value Second Stage Power Amplifier Bias Current Adjustment Set to XXXX for 802 110 0 First Stage Power Amplifier Bias Current Adjustment Set to XXX for 802 110 0 Table 26 Register 11 0 1011 RECOMMENDED DESCRIPTION 0000000 Set to recommended value 11 LNA Gain Control Set to 11 for high gain mode Set to 10 for medium gain mode reducing LNA gain by 16dB Set to OX for low gain mode reducing LNA gain by 33dB Receiver VGA Control Set D4 DO 00000 for minimum gain and D4 DO 11111 for maximum gain Table 27 Register 12 A3 A0 1100 RECOMMENDED DESCRIPTION 00000101
18. Pulse Width Low Last Rising Edge of SCLK to Rising Edge of CS or Clock to Load Enable Setup Time tcsH CS High Pulse Width tcsw Time Between the Rising Edge of CS and the Next Rising Edge of SCLK tcs1 Clock Frequency Rise Time tn Fall Time tF Note 1 Min and max limits are guaranteed by test at TA 25 C and 85 C and guaranteed by design and characterization at TA 40 C The power on register settings are not production tested Recommended register setting must be loaded after is supplied Note 2 Guaranteed by design and characterization Note 3 The nominal part to part variation of the RF gain step is 1dB Note 4 Two tones at 25MHz and 48MHz offset with 35dBm tone Measure IM3 at 2MHz Note 5 Tx I Q inputs 100mVnws 10 MAXIM 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Typical Operating Characteristics MAX2831 EV kit Voc 2 8V VCCPA VCCTXPA 3 3V TA 25 fL o 2 437GHz fReF 40MHz SHDN CS high RXHP SCLK DIN low
19. The Vcc traces branch out from this node each going to a separate Vcc node in the circuit Place a bypass capacitor as close as possible to each supply pin This arrangement provides local decoupling at each Vcc pin Use at least one via per bypass capacitor for a low inductance ground connection Do not share the capacitor ground vias with any other branch and the exposed paddle ground MAXIM N e lt 32 55 53 x Figure 3 Timing Diagram TOP VIEW Vocuna 11 GNDRXLNA 21 86 13 87 6 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA POWER SUPPLY ON 3 WIRE SERIAL INTERFACE AVAILABLE SHUTDOWN CS SELECT i SCLK CLOCK DIN DATA SPI tt 1 CHANNEL FREQUENCY PA BIAS TRANSMITTER LINEARITY i RECEIVER RSSI OPERATION CALIBRATION MODE ETC INTERNAL PA I ENABLED DRIVES POWER RAMP CONTROL 112 01075 PA ENABLE SHUTDOWN 5 E RECEIVE TRANSMIT MODE E MODE Pin Configuration PROCESS 5 lt MODE gt Chip Information Package Information For the latest package outline information and land patterns footprints go to www maxim ic com packages Note that a MAXIM 2831 2832 MAXI 48 TQFN EP T4877 4 21 0144 900130 I or in the package code indicates RoHS
20. enabled in this mode Set SHDN to logic high and RXTX to logic low to place the device in Rx mode Transmit Tx Mode The complete transmitter signal path is enabled in this mode Set SHDN RXTX to logic high to place the device in Tx mode Tx Rx Calibration Mode The MAX2831 MAX2832 feature Rx Tx calibration modes to detect 1 imbalances and transmit LO leakage In the Tx calibration mode all Tx circuit blocks except the PA driver and external PA are powered on and active The AM detector and receiver and Q channel buffers are also on along with multiplexers in the receiver side to route this AM detector s signal In this mode the LO leakage calibration is done only for the LO leakage sig nal that is present at the center frequency of the channel i e in the middle of the OFDM or QPSK spectrum The LO leakage calibration includes the effect of all DC off sets in the entire baseband paths of the I Q modulator and direct leakage of the LO to the I Q modulator output 32 The LO leakage and sideband detector output are taken at the receiver and Q channel outputs during this calibration phase During Tx LO leakage and I Q imbalance calibration a sine and cosine signal f frone is input to the base band I Q Tx pins from the baseband IC At the LO leak age and sideband detector output the LO leakage corresponds to the signal at ffoneg and the sideband suppression corresponds to the signal at 2 frone Th
21. filter On except PA AM detector driver and PA Rx buffers Rx Calibration Upconverters Tx Calibration X Don t care MAXIM 31 ct 8cXVW LESCXVM MAX2831 MAX2832 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Modes of Operation The modes of operation for the 2831 2832 are shutdown standby transmit receive transmitter calibra tion and receiver calibration See Table 31 for a summa ry of the modes of operation The logic input pins SHDN pin 12 and RXTX pin 48 control the various modes Shutdown Mode The 2831 2832 feature a low power shutdown mode that disables all circuit blocks except the serial interface and internal registers allowing the registers to be loaded and values maintained as long as Vcc is applied Set SHDN and logic low to place the device in shutdown mode After supply voltage ramp up supply current in shut down mode could be high Program the default value to register 0 to eliminate high shutdown current Standby Mode The standby mode is used to enable the frequency synthesizer block while the rest of the device is pow ered down In this mode the PLL VCO and LO gener ators are on so that Tx or Rx modes can be quickly enabled from this mode Set SHDN to a logic low and RXTX to a logic high to place the device in standby mode Receive Rx Mode The complete receive signal path is
22. status only Package drawings may show a different suffix character but the drawing pertains to the package regardless of ROHS status PACKAGE PACKAGE OUTLINE LAND oo TYPE CODE NO 900130 30 33 ct 8cXVMW LESCXVM MAX2831 MAX2832 2 4GHz to 2 5GHz 802 11 g b RF Transceivers with Integrated PA Revision History REVISION REVISION PAGES NUMBER DATE DESCRIPTION CHANGED 0 10 06 Initial release 1 3 10 Removed 2832 future product reference and made minor corrections 1 2 10 18 19 20 Corrected conditions for Rx I Q Output Common Mode Voltage Variation in the 2 3 11 DC Electrical Characteristics corrected Tables 14 17 and 27 added text to Shutdown Mode section Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 34 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
23. 6 5GHz RECEIVER BASEBAND FILTERS Gain Ripple in Passband Group Delay Ripple in Passband t0kHz to 8 5MHz at baseband 10kHz to 8 5MHz at baseband MAXIM 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA AC ELECTRICAL CHARACTERISTICS Rx Mode continued MAX2831 EV kit Vcc_ 2 8V VCCPA VCCTXPA 3 3V 25 C fnr 2 439GHz 10 2 437 2 receiver baseband I Q out puts at 112 mVams 19dBV fREF 40MHz SHDN CS high RXTX SCLK DIN low with power matching for the differential RF pins using the typical applications and registers set to default settings and corresponding test mode unless otherwise noted Unmodulated single tone RF input signal is used with specifications which normally apply over the entire operating conditions unless otherwise indicated RF inputs outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB balun and SMA connectors Note 1 PARAMETER CONDITIONS MIN TYP At 8 5MHz Baseband Filter Rejection At 15MHz A Nominal Mode 20MHz 50 At gt 40MHz 80 RSSI RSSI Minimum Output Voltage LOAD gt 10 ll 5 RSSI Maximum Output Voltage LOAD gt 10 Il 5pF RSSI Slope To within 3dB of steady 32dB signal step state 32dB signal step RSSI Output Settling Time MAXIM 5 CE8TXVYNW LE8ZXVIN 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA AC
24. 6 B1 111000 OFDM signal 4 3 x Lo 5 3 x fLo 8 3 x fLo 2x fLo 1 3 x fLo lt 1GHz gt 1GHz 2 3 x fLo B6 B1 111111 x fO OFDM signal 5 3 x fLo 8 3 x fLo 2x flo 3x fLo MAXIM 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA AC ELECTRICAL CHARACTERISTICS Tx Mode continued MAX2831 EV kit 2 8V VCCPA VCCTXPA 3 3V TA 25 C fnr 2 439GHz fi o 2 437GHz 40MHz SHDN RXTX CS high and SCLK DIN low with power matching for the differential RF pins using the typical applications circuit 100mVnws sine and cosine signal or 100mVRMs 54Mbps IEEE 802 110 1 signals wherever OFDM is mentioned applied to base band I Q inputs of transmitter differential DC coupled Registers set to recommend settings and corresponding test mode unless otherwise noted RF inputs outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB balun and SMA connectors Note 1 PARAMETER CONDITIONS Off chip balun match single MAX2831 ended 2832 RF Output Return Loss Tx I Q Input Load Impedance Minimum differential resistance R II C Maximum differential capacitance Baseband 3dB Corner D1 D0 01 Register 8 Frequency A3 A0 1000 Baseband Filter Rejection At 30MHz in nominal mode Nominal mode Minimum Power Detector Output hort nce transmitter er
25. CS transitions high the bit registers The 14 most significant bits MSBs are shift register is latched into the register selected by the used for register data The 4 least significant bits contents of the address bits See Figure 2 Only the last LSBs of each register contain the register address 18 bits shifted into the device are retained in the shift See Table 14 for a summary of the registers and rec register No check is made the number of clock ommended register settings pulses For programming data words less than 14 bits long only the required data bits and the address bits need to be shifted resulting in faster Rx and Tx gain control where only the LSBs need to be programmed Register data is loaded through the 3 wire SPI MICROWIRE compatible serial interface Data is MICROWIRE is a trademark of National Semiconductor Corp Table 14 Recommended Register Settings ADDRESS DO A3 A0 0000 REGISTER g D13 D12 The power on register settings are not production tested Recommended register settings must be loaded after Vcc is supplied fL fL n f nm nr lt lt pe 14 01 tps teso tess 1 i Figure 2 3 Wire SPI Serial Interface Timing Diagram MAXI 27 ct 8cXVMW LESCXVM MAX2831 MAX2832 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integra
26. D PINS 2 26 AND 31 AND BYPASS CAPACITORS GROUND REQUIRE THEIR OWN VIAS TO GROUND DO NOT CONNECT THEM TO THE EXPOSED PADDLE GROUND MAXIM 19 ct 8cXVW LESCXVM MAX2831 MAX2832 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Pin Description PIN NAME FUNCTION LNA Supply Voltage GNDRXLNA LNA Ground Receiver and Transmitter Gain Control Logic Input Bit 6 LNA Differential Input Input is internally AC coupled and matched to 1000 differential Connect RXRF directly to a 2 1 balun B7 Receiver Gain Control Logic Input Bit 7 VCCPA Supply Voltage for Second Stage of Power Amplifier B3 Receiver and Transmitter Gain Control Logic Input Bit 3 TXRF Power Amplifier Differential Output for the MAX2831 PA output must be AC coupled PA driver internally AC coupled differential outputs and matched to 100Q differential for the MAX2832 Connect TXRF directly to a 2 1 balun B2 Receiver and Transmitter Gain Control Logic Input Bit 2 SHDN Active Low Shutdown and Standby Logic Input See Table 31 for operating modes Supply Voltage for First Stage of PA and PA Driver 1 410 011 o k k 5 Receiver and Transmitter Gain Control Logic Input Bit 5 CS Active Low Chip Select Logic Input of 3 Wire Serial Interface See Figure 2 RSSI RSSI PA Power Detector MAX2831 Only or Temperature Sensor Multiplexed Analog Output
27. IN VARIATION vs FREQUENCY Tx EVM vs Pout PA SUPPLY CURRENT vs Pout B6 B1 101001 8 28 E Vecpa 4 2V 4 3 I V 33V 8 25 3 3 CCPA 9 6 2 VCCPA 3 0V 22 u se ac gt 2 V gt R 19 Ta 48590 4 x 3 16 2 7V 3 0V 3 3V 2 13 0 2 4 6 8 10 12 14 16 18 20 22 0 2 4 6 8 10 12 14 16 18 20 22 24 2 40 2 42 2 44 2 46 2 48 2 50 Pout dBm Pout dBm FREQUENCY GHz 802 119 Pout vs GAIN SETTING Tx OUTPUT POWER vs FREQUENCY 11g SPECTRAL MASK UPPER GAIN CONTROL RANGE 20 9 g 22 i GAIN ADJUSTED TO ACHIEVE 5 696 EV E 19 Pour 18 64dBm a 8 EVM 5 6 A 8 8 8 425 C ka 20 39 49 18 8 8 18 59 B 69 16 79 7 89 14 x 99 6 109 12 240 242 2 44 246 2 48 2 50 2387 2407 207 247 2467 2487 40 44 48 52 56 60 64 FREQUENCY GHz FREQUENCY MHz GAIN SETTINGS MAXIM 15 CE8TXVYNW LE8SZXVIN MAX2831 MAX2832 2 4GHz to 2 5GHz 802 11 g b RF Transceivers with Integrated PA 2831 POWER DETECTOR OVER FREQUENCY Typical Operating Characteristics continued EV kit Vcc_ 2 8V VCCPA VCCTXPA 3 3V TA 25 C fi o 2 437GHz fREF 40MHz SHDN CS high RXHP SCLK DIN low POWER DETECTOR OVER SUPPLY VOLTAGE POWER DETECTOR OVER TEMPERATURE
28. IONS SYSTEM TIMING See Figure 3 From SHDN rising edge to LO settled within 1kHz using Turn On Time external reference frequency input Crystal Oscillator Turn On Time 9096 of final output amplitude level Channel Switching Time Loop BW 150kHz fnr 2 5GHz to 2 4GHz Measured from Tx or Rx Rx to Tx enable rising edge signal settling to within x2dB of Rx Tx Turnaround Time steady state Tx to Rx RXHP 1 ime from Standby x enable active rising edge signal settling to 2dB of steady state Ime non x enable inactive rising edge ime from Standby From Rx enable active rising edge signal settling to within gt 20 of steady state me omi standby From Rx enable inactive rising edge MAXKLNI 9 CESSCXVIN FESSCXVIN MAX2831 MAX2832 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA AC ELECTRICAL CHARACTERISTICS Timing continued MAX2831 EV kit 2 8V VCCPA VCCTXPA 3 3V TA 25 10 2 437GHz fRaEF 40MHz SHDN CS high SCLK DIN low PLL loop bandwidth 150kHz and TA 25 C unless otherwise noted Note 1 PARAMETER CONDITIONS 3 WIRE SERIAL INTERFACE TIMING See Figure 2 SCLK Rising Edge to CS Falling Edge Wait Time tcso Falling Edge of CS to Rising Edge of First SCLK Time tcss DIN to SCLK Setup Time tps DIN to SCLK Hold Time SCLK Pulse Width High tcH SCLK
29. MHz Table 9 Transmitter LPF Fine 3dB Corner Frequency Adjustment in Register A3 A0 0111 ADJUSTMENT RELATIVE TO COARSE SETTING 000 90 95 100 105 110 11g 115 101 111 Not used BITS D5 D3 23 CESSXVIN LESSCXVIN MAX2831 MAX2832 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Transmitter Variable Gain Amplifier The variable gain amplifier of the transmitter provides 31dB of gain control range programmable in 0 5dB steps over the top 8dB of the gain control range and in steps below that The transmitter gain can be pro grammed serially through the SPI interface by setting bits D5 D0 in Register 12 A3 A0 1100 or in parallel through the digital logic gain control pins B6 B1 pins 3 6 8 11 14 23 and 34 respectively Set bit D10 0 in Register 9 A3 A0 1001 to enable parallel pro gramming and set bit D10 1 to enable programming through the 3 wire serial interface See Table 10 for the transmitter VGA gain control settings Table 10 Transmitter VGA Gain Control Settings D5 D0 Or B6 B1 63 111111 Max 111110 Max 0 5dB Max 1 0dB NUMBER OUTPUT SIGNAL POWER Max Max 7 54 8qB 8qB 9 29dB ax 29dB 30dB 30dB 31dB 0 000000 ax 31dB 000011 000010 000001 Power Amplifier Driver Output Matc
30. UT vs CRYSTAL OSCILLATOR TUNING BITS 25kHz 2831 32 toc59 Y 800 fcLock 40MHz 700 KYOCERA 3 Cloap 5pF gt _ 600 322558 D E 500 E peeieel z 400 2 300 2 10 5 2 z 3 2 4 5 2 7 8 10ns div 0 10 20 30 40 50 60 70 80 90 100110120130 DIGITAL BITS MAXIM 17 CESSCXVIN FESSCXVIN MAX2831 MAX2832 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Block Diagrams Typical Operating Circuits RX BASEBAND HPF MODE CORNER FREQUENCY CONTRO CONTROL RX OUTPUTS r 1 o 0 VCCRXVGA VCCLNA P i RXBBQ MAXIM RXQ GNDRXLNA MAX2831 RXBBQ OUTPUTS RX TX B4 RX TX GAIN GAIN CONTROL CONTROL RX INPUT gt BYPASS TUNE RX GAIN DVCO CONTROL X QMUX E AM RX TX GAIN ETECTOR TX OUTPU CONTROL CRYSTAL OSCILLATOR BUFFER TEMP SENSOR gt POWER DETECTOR GAIN SERIAL CONTROL NTERFACE MODE CONTROL
31. b free RoHS compliant package T Tape and reel Pin Configuration appears at end of data sheet Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Dallas Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com CESSCXVIN LESSCXVIN MAX2831 MAX2832 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA ABSOLUTE MAXIMUM RATINGS VCCTXPA VCCPA TXRF_ to GND 0 3V to 4 5V VCCLNA VCCPLL VCCXTAL VCCVCO VCCRXVGA VCCRXFL and to GND 0 3V to 3 9V B6 B7 B3 B2 SHDN B5 CS SCLK DIN B1 TUNE B4 TXBBI_ TXBBQ RXHP RXTX RXBBQ RSSI BYPASS CPOUT LD CLOCKOUT XTAL CTUNE RXRF to 0 3V to Operating Vcc 0 3 RXBBI_ RSSI BYPASS CPOUT LD CLOCKOUT Short Circuit Duration 2 112224 RF Input POW ST ate bae SNS Su da 10dBm Continuous Power Dissipation TA 70 C 48 Pin TQFN derates 27 8mW C above 70 C 2 22W Operating Temperature Range 40 C to 85 C Junction Temperature 150 Storage Temperature Range 65 C to 160 C Lead Temperature soldering 105 300 C Soldering Temperature
32. ble internal 30kQ pullup D9 resistor or set to O to disable the resistor Only available when lock detect open drain output is selected A3 A0 0010 D12 1 Set to recommended value Lock Detect Output Enable Set to 1 to enable the lock detect output or set to 0 to disable the output The output is high impedance when disabled D4 D3 Set to recommended value Reference Frequency Divider Ratio to PLL Set to 0 to divide by 1 Set to 1 to divide by 2 01 00 7 C NE 28 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Table 21 Register 6 A3 A0 0110 DATA BIT RECOMMENDED DESCRIPTION D13 0 Set to recommended value Tx I Q Calibration LO Leakage and Sideband Detector Gain Control Bits D12 D11 00 9 01 19dB 10 29dB 11 9 D10 D7 Set to recommended value D12 D11 Power Detector Enable in Tx Mode Set to 1 to enable the power detector or set to 0 to disable the detector Set to recommended value Tx Calibration Mode Set to 1 to place the device in Tx calibration mode or 0 to place the device in normal Tx mode when is set to 1 see Table 31 Rx Calibration Mode Set to 1 to place the device in Rx calibration mode or 0 to place the device in normal Rx mode when is set to 0 see Table 31 Table 22 Register 7 A3 A0 0111 BIT RECOMMENDED DESCRIPTION Receiver Highpass Corner Frequency Setting for RXHP 0 Set to
33. delta fractional N synthesizer crystal oscil lator RSSI PA power detector MAX2831 temperature sensor Rx and Tx I Q error detection circuitry baseband control interface and linear power amplifier MAX2831 The only additional components required to implement a complete radio front end solution are a crystal a pair of baluns a BPF a switch and a small number of passive components RCs no inductors required Receiver The fully integrated receiver achieves a noise figure of 2 6dB in high gain mode and an input compression point of 6dBm in low gain mode while consuming only 62mA of supply current The receiver integrates an LNA and VGA with a 95dB digitally programmable gain control range direct conversion downconverters 1 0 baseband lowpass filters with programmable LPF corner frequen cies analog RSSI and integrated DC offset correction cir cuitry A logic low on the RXTX input pin 48 and a logic high on the SHDN input pin 12 enable the receiver MAXIM LNA Input Matching The LNA features a differential input that is internally AC coupled and internally matched to 100Q Connect a 2 1 balun transformer directly to the RXRF pin 4 and RXRF pin 5 ports to convert the differential 100Q input impedance to a single ended 50Q input Provide electrically symmetrical input traces from the LNA input to the balun to maintain IP2 performance and RF com mon mode noise rejection LNA Gain Control The LNA has three
34. e output power of these signals vary for 1dB of varia tion in the LO leakage and sideband suppression To calibrate the Tx path first set the power detector gain to 9dB using D12 D11 in Register 5 see Table 21 Adjust the DC offset of the baseband inputs to minimize the signal at frone LO leakage Then adjust the base band input relative magnitude and phase offsets to reduce the signal at 2 x In Rx calibration mode the calibrated Tx RF signal is internally routed to the Rx inputs In this mode the VCO LO generator PLL blocks are powered on and active except for the low noise amplifier LNA Applications Information Layout Issues The MAX2831 EV kit can be used as a starting point for layout For best performance take into consideration grounding and RF baseband and power supply rout ing Make connections from vias to the ground plane as short as possible Do not connect the device ground pin to the exposed paddle ground Keep the buffered clock output trace as short as possible Do not share the trace with the RF input layer especially on or inter layer or back side of the board On the high impedance ports keep traces short to min imize shunt capacitance EV kit Gerber files can be requested at www maxim ic com Power Supply Layout To minimize coupling between different sections of the IC a star power supply routing configuration with a large decoupling capacitor at a central Vcc node is rec ommended
35. e 3 for baseband VGA gain control settings Receiver Baseband Lowpass Filter The receiver integrates lowpass filters that provide an upper 3dB corner frequency of 8 5MHz nominal mode with 50dB of attenuation at 20MHz and 45ns of group delay ripple in the passband 10kHz to 8 5MHz The upper 3dB corner frequency is tightly controlled on chip and does not require user adjustment However provi sions are made to allow fine tuning of the upper cor ner frequency In addition coarse frequency tuning allows the 3dB corner frequency to be set to 7 5MHz 11b mode 8 5MHz 11g mode 15MHz turbo 1 mode and 18MHz turbo 2 mode by programming bits D1 DO in Register 8 0 1000 See Table 4 The coarse corner frequency can be fine tuned approximately 10 in 596 steps by programming bits D2 DO in Register 7 0 0111 See Table 5 for receiver LPF fine 3dB corner frequency adjustment Table 2 Receiver Baseband VGA Gain Step Value Pins B5 B1 or Register D4 DO 0 1011 GAIN STEP aB Table 3 Baseband VGA Gain Control Settings in Receiver Gain Control Register Pin B5 B1 or Register D4 D0 A3 A0 1011 Baseband Highpass Filter and DC Offset Correction The receiver implements programmable AC and near DC coupling of I Q baseband signals Temporary AC coupling is used to quickly remove LO leakage and other DC offsets that could saturate the receiver out puts When DC offsets have s
36. eration a 40MHz reference oscillator is divided by 2 to generate a 20MHz compari Fractional Divider 0 85 x 220 1 891289 decimal son frequency fcomp The following method be 1101 1001 1001 1001 1001 used when calculating divider ratios supporting various See Table 13 for integer and fractional divider ratios for reference and comparison frequencies 802 11g b systems using a 20MHz comparison frequency Table 11 Integer Divider Register A3 A0 0011 RECOMMENDED DESCRIPTION 00000 6 LSBs of 20 Bit Fractional Portion of Main Divider 01111001 8 Bit Integer Portion of Main Divider Programmable from 64 to 255 Table 12 Fractional Divider Register A3 A0 0100 BIT D13 D0 RECOMMENDED 11011001100110 DESCRIPTION 14 MSBs of 20 Bit Fractional Portion of Main Divider Table 13 IEEE 802 11g b Divider Ratio Programming Words INTEGER DIVIDER FRACTIONAL DIVIDER A3 A0 0011 D7 D0 A3 A0 0100 D13 D0 A3 A0 0011 D13 D8 111 1000b 111 1000b 111 1001b 111 1001b 111 1001b 111 1010b fnr fcowP E ce 2484 124 2 111 11006 0CCCh 33h 0 MAXIM 25 CESSXVIN FESSCXVIN MAX2831 MAX2832 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Crystal Oscillator The crystal oscillator has been optimized to work with low cost crystals e g K
37. ettled near DC coupling is enabled to avoid attenuation of the received signal AC coupling is set highpass corner frequency of 600kHz when a logic high is applied to RXHP pin 40 Near DC coupling is set 3dB highpass corner fre quency of 100Hz nominal when a logic low is applied to RXHP Bits D13 D12 in Register 7 A3 A0 0111 allow the near DC coupling 3B highpass corner fre quency to be set to 100Hz D13 D12 00 4kHz D13 D12 X1 or 3OkHz D13 D12 10 See Table 6 Table 4 Receiver LPF Coarse 3dB Corner Frequency Settings in Register 0 1000 1 3dB CORNER srequencr ati YOPE Table 5 Receiver LPF Fine 3dB Corner Frequency Adjustment in Register A3 A0 0111 BITS D2 D0 ADJUSTMENT RELATIVE TO COARSE SETTING Table 6 Receiver Highpass Filter 3dB Corner Frequency Programming A3 A0 0111 3dB HIGHPASS CORNER D13 D12 FREQUENCY Hz 600k 100 recommended 22 4k 30k X Dont care MAXIM 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Receiver I Q Baseband Outputs The differential outputs RXBBI RXBBI RXBBQ RXBBQ of the baseband amplifiers have a differential output impedance of 300 and are capable of dri ving differential loads up to 10 Il 10pF The outputs are internally biased to a common mode voltage of 1 1V and are intended to be DC coupled to the in phase 1 and
38. foFFSET 10kHz Closed Loop Phase Noise foFFSET 100kHz dBc Hz foFFSET 1MHz foFFsET 10MHz Closed Loop Integrated Phase Noise RMS phase jitter integrate from 10kHz to 10MHz offset Degrees Charge Pump Output Current mA Reference Spurs 20MHz offset Measured from Tx Rx or Rx Tx to 9us transition gt 9us VOLTAGE CONTROLLED OSCILLATOR Pushing Referred to 2400MHz LO Vcc varies by 0 3V VCO Tuning Voltage Range VCO Frequency Error VTUNE 0 5V VTUNE 2 2V LO Tuning Gain 8 MAXIM 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA AC ELECTRICAL CHARACTERISTICS Miscellaneous Blocks 2831 EV kit Vcc_ 2 8V VCCPA 3 3V fLo 2 437GHZ fREF 40 2 SHDN CS high DIN low and TA 25 C unless otherwise noted Note 1 PARAMETER CONDITIONS CRYSTAL OSCILLATOR On Chip Tuning Capacitance Maximum capacitance A3 A0 1110 D6 D0 1111111 Range Minimum capacitance A3 A0 1110 D6 D0 0000000 On Chip Tuning Capacitance Step Size ON CHIP TEMPERATURE SENSOR Output Voltage 0 1000 D9 D8 01 AC ELECTRICAL CHARACTERISTICS Timing MAX2831 EV kit Vcc_ 2 8V VcCPA VCCTXPA 3 3V TA 25 10 2 437 2 fREF 40MHz SHDN CS high SCLK DIN low PLL loop bandwidth 150kHz and TA 25 C unless otherwise noted Note 1 PARAMETER CONDIT
39. gain modes max gain max gain 16dB and max gain 33dB The three LNA gain modes can be serially programmed through the SPI interface by programming bits D6 D5 in Register 11 0 1011 or programmed in parallel through the digital logic gain control pins 7 pin 6 6 3 Set bit D12 1 in Register 8 0 1000 to enable pro gramming through the SPI interface or set bit D12 0 to enable parallel programming See Table 1 for LNA gain control settings Table 1 LNA Gain Control Settings Pins B7 B6 or Register A3 A0 1011 D6 D5 B7 OR D6 B6 OR D5 NAME DESCRIPTION 1 High Max gain x Low 0 Max gain 33dB typ SPI is a trademark of Motorola Inc 21 CESSCXVIN FESSCXVIN MAX2831 MAX2832 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Baseband Variable Gain Amplifier The receiver baseband variable gain amplifiers provide 624 of gain control range programmable in 2dB steps The VGA gain can be serially programmed through the SPI interface by setting bits D4 DO in Register 11 A3 A0 1011 or programmed in parallel through the digital logic gain control pins B5 pin 14 B4 pin 34 B3 pin 8 B2 pin 11 and B1 pin 23 Set bit D12 1 in Register 8 A3 A0 1000 to enable serial programming through the serial interface or set bit D12 0 to enable parallel programming through the external logic pins See Table 2 for the gain step value and Tabl
40. hing MAX2832 PA driver of the 2832 has 1000 differential output with on chip AC coupling capacitors Provide electrically symmetrical traces to present a balanced load to the PA driver output to help maintain driver lin earity and RF common mode rejection 24 Power Amplifier Bias Enable Delay and Output Matching MAX2831 The MAX2831 integrates a 2 stage PA providing 18 5dBm of output power at 5 6 EVM 54Mbps OFDM signal in 802 11g mode while exceeding the 802 11g spectral mask requirements The first and sec ond stage PA bias currents are set through program ming bits D2 D0 and bits D6 D3 in Register 10 A3 A0 1010 respectively An adjustable PA enable delay rel ative to the transmitter enable RXTX low to high transi tion be set from 200ns to 758 through programming bits D13 D10 in Register 10 A3 A0 1010 of the MAX2831 has 1000 differential output that is internally matched The output has to be AC cou pled using two off chip 1 5pF capacitors to 1000 500 balun Provide electrically symmetrical traces from the PA output to the balun to present a balanced load and to reduce out of band spurs Power Detector MAX2831 The MAX2831 integrates a voltage peak detector at the PA output and provides an analog voltage proportional to PA output power See the Power Detector Over Frequency and Power Detector Over Supply Voltage graphs in the Typical Operating Characteristics Set bi
41. illator not applied TA 25 C Standby mode TA 25 C TA 40 C to 85 C Rx mode Tx mode TA 25 C Vcc 2 8V VCCPA 3 3V Note 2 TA 25 TA 40 C to 85 C MAX2831 transmit section MAX2831 PA Pour 18 2dBm MAX2832 Rx calibration mode Tx calibration mode TA 25 C TA 25 C Rx I Q Output Common Mode Voltage Rx I Q Output Common Mode Voltage Variation TA 25 C at default common mode setting TA 40 C relative to TA 25 C TA 85 C relative to TA 25 C Tx Baseband Input Common Mode Voltage Operating Range Tx Baseband Input Bias Current DC coupled Source current MAXIM 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA DC ELECTRICAL CHARACTERISTICS continued 2831 EV kit Vcc_ 2 7V to 3 6V VCCPA VCCTXPA 2 7V to 4 2V TA 40 to 85 C Rx set to the maximum gain CS high RXHP SCLK DIN low RSSI and clock output buffer are off no signal at RF inputs all RF inputs and outputs terminated into 500 receiver baseband outputs are open 100mVRMS differential and Q signals 54Mbps IEEE 802 119 OFDM applied to I Q baseband inputs of transmitter in transmit mode fREF 40MHz and registers set to recommended settings and corresponding test mode unless otherwise noted Typical values are at Vcc 2 8V VCCPA 3 3V and TA 25 C LO frequency 2 437GHz unless otherwi
42. o 11Mbps The ICs are available in a small 48 pin TQFN package measuring only 7mm x 7mm x 0 8mm Applications Wi Fi PDA VOIP and Cellular Handsets Wireless Speakers and Headphones General 2 4GHz ISM Radios MAXIM Features 9 2 4GHz to 2 5GHz ISM Band Operation 9 IEEE 802 11g b Compatible 54Mbps OFDM and 11Mbps CCK 9 Complete RF Transceiver PA and Crystal Oscillator MAX2831 Best in Class Transceiver Performance 62mA Receiver Current 2 6dB Rx Noise Figure 76dBm Rx Sensitivity 54Mbps OFDM No I Q Calibration Required 0 1dB 0 35 Rx I Q Gain Phase Imbalance 33dB RF and 62dB Baseband Gain Control Range 60dB Range Analog RSSI per RF Gain Setting Fast Rx l Q DC Offset Settling Programmable Baseband Lowpass Filter 20 Bit Sigma Delta Fractional N PLL with 20Hz Step Size Digitally Tuned Crystal Oscillator 18 5dBm Transmit Power 5 6 EVM with 54Mbps OFDM 31dB Tx Gain Control Range Integrated Power Detector MAX2831 Serial or Parallel Gain Control Interface gt 40dB Tx Sideband Suppression without Calibration Tx Rx Error Detection 9 Transceiver Operates from 2 7V to 3 6V PA Operates from 2 7V to 4 2V 2831 9 Low Power Shutdown Mode 9 Small 48 Pin TQFN Package 7mm x 7mm x 0 8mm Ordering Information TEMP RANGE 40 C to 85 C 40 C to 85 C PIN PACKAGE 48 TOFN EP 48 TQFN EP MAX2831ET MAX2832E Exposed Denotes a lead P
43. quadrature Q analog to digital data converter inputs of the accompanying baseband IC Additionally the common mode output voltage can be adjusted from 1 1V to 1 4V through programming bits D11 D10 in Register 15 A3 A0 1111 Received Signal Strength Indicator RSSI The RSSI output pin 16 can be programmed to multi plex an analog output voltage proportional to the received signal strength the PA output power 2831 or the die temperature Set bits D9 D8 00 in Register 8 A3 A0 1000 to enable the RSSI output in receive mode off in transmit mode Set bit D10 1 to enables the RSSI output when RXHP 1 and dis able the RSSI output when RXHP 0 Set bit D10 0 to enable the RSSI output independent of RXHP See Table 7 for a summary of the RSSI output versus regis ter programming and RXHP The received signal strength indicator provides an ana log voltage proportional to the log of the sum of the squares of the and Q channels measured after the receive baseband filters and before the variable gain amplifiers The RSSI analog output voltage is propor tional to the RF input signal level and LNA gain state over a 60dB range and is not dependent upon VGA gain See the graph RX RSSI Output vs Input Power in the Typical Operating Characteristics for further details Transmitter The transmitter integrates baseband lowpass filters direct upconversion mixers a VGA a PA driver and a lin ear RF PA with a power detec
44. se noted RF inputs outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB balun and SMA connectors Note 1 PARAMETERS CONDITIONS LOGIC INPUTS SHDN RXTX SCLK DIN CS B7 B1 RXHP Input Voltage High ViH Input Voltage Low VIL a ital Input Current High al Input Current Low liL OGIC OUTPUTS LD CLOCKOUT Digital Output Voltage High Sourcing 100 Digital Output Voltage Low VoL Sinking 100pA AC ELECTRICAL CHARACTERISTICS Rx Mode MAX2831 EV kit Vcc_ 2 8V VCCPA VCCTXPA 3 3V TA 25 C fnr 2 439GHz 10 2 437 GHz receiver baseband I Q out puts at 112 mVams 19dBV fREF 40MHz SHDN CS high RXTX SCLK DIN low with power matching for the differential RF pins using the typical applications and registers set to default settings and corresponding test mode unless otherwise noted Unmodulated single tone RF input signal is used with specifications which normally apply over the entire operating conditions unless otherwise indicated RF inputs outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB balun and SMA connectors Note 1 PARAMETER CONDITIONS RECEIVER SECTION LNA RF INPUT TO BASEBAND I Q OUTPUTS HF Input Frequency Range High RF gain RF Input Return Loss id RF gain Low RF gain aximum gain B7 B1 TA 25 1111111 TA 40 C to 85
45. ted PA Table 15 Register 0 A3 A0 0000 DATA BITS RECOMMENDED DESCRIPTION D13 D11 Set to recommended value 010 Fractional N PLL Mode Enable Set 1 to enable the fractional N PLL or set O to enable the integer N PLL D9 DO 1101000000 Set to recommended value Table 16 Register 1 0 0001 DATA BITS RECOMMENDED DESCRIPTION D13 0 Set to recommended value Lock Detector Output Select Set to 1 for CMOS Output Set to 0 for open drain output Bit D9 12 in register A3 A0 0101 enables or disables an internal pullup resistor in open drain output mode D11 D0 000110011010 Set to recommended value Table 17 Register 2 A3 A0 0010 DATA BITS RECOMMENDED DESCRIPTION D13 D0 01000000000011 Set to recommended value This register contains the 8 bit integer portion and 6 LSBs of the fractional portion of the divider ratio of the synthesizer Table 18 Register 3 A3 A0 0011 BIT RECOMMENDED DESCRIPTION D13 D8 00000 6 LSBs of 20 Bit Fractional Portion of Main Divider D7 DO 01111001 8 Bit Integer Portion of Main Divider Programmable from 64 to 255 Table 19 Register 4 0 0100 BIT RECOMMENDED DESCRIPTION D13 DO 11011001100110 14 MSBs of 20 Bit Fractional Portion of Main Divider Table 20 Register 5 0 0101 BIT RECOMMENDED DESCRIPTION D13 D10 0000 Set to recommended value Lock Detect Output Internal Pullup Resistor Enable Set to 1 to ena
46. third order lowpass RC loop filter which in turn connects to the voltage tuning input TUNE pin 32 of the VCO completing the PLL loop The charge pump output sink and source current is 1mA and the VCO tuning gain is 103 2 at 0 5V tune voltage and 86MHz N at 2 2V tune voltage The RC loop filter values have been optimized for a loop band width of 150kHz to achieve the desired Tx Rx turn around settling time while maintaining loop stability and good phase noise Refer to the MAX2831 EV kit schematic for the recommended loop filter component values Keep the line from this pinto the tune input as short as possible to prevent spurious pickup Lock Detector Output The PLL features a logic lock detect output A logic high indicates the PLL is locked and a logic low indicates the PLL is not locked Bit D5 in Register 5 A3 A0 0101 enables or disables the lock detect output Bit D12 in Register 1 A3 A0 0001 configures the lock detect output as a CMOS or open drain output In open drain output mode bit D9 in Register 5 0 0101 enables or disables an internal 30kQ pullup resistor from the open drain output MAXIM 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Programmable Registers and shifted in MSB first and is framed by CS When CS is 3 Wire SPI Interface low the clock is active and data is shifted with the ris The MAX2831 MAX2832 include 16 programmable 18 ing edge of the clock When
47. tor MAX2831 A logic high on the RXTX input pin 48 and a logic high on the SHDN input pin 12 enable the transmitter Transmitter I Q Baseband Inputs The differential analog inputs of the transmitter baseband amplifier I Q inputs TXBBI TXBBQ TXBBQ have a differential impedance of 20kQ Il 1pF The inputs require an input common mode voltage of 0 9V to 1 3V which is provided by the DC coupled and Q DAC out puts of the accompanying baseband IC Transmitter Baseband Lowpass Filtering The transmitter integrates lowpass filters that can be tuned to 3dB corner frequencies of 8MHz 11b 11MHz 119 16 5MHz turbo 1 mode and 22 5MHz turbo 2 mode through programming bits D1 DO in MAXI Register 8 A3 A0 1000 and bit D5 D3 in Register 7 0 0111 The 3dB corner frequency is tightly con trolled on chip and does not require user adjustment Additionally provisions are made to fine tune the cor ner frequency through bits D5 D3 in the Filter Programming register A3 A0 0111 See Tables 8 and 9 Table 7 RSSI Pin Truth Table INPUT CONDITIONS A3 A0 1000 A3 A0 1000 D9 D8 D10 RSSI OUTPUT No signal Temperature sensor Power detector MAX2831 RSSI Temperature sensor Power detector MAX2831 X Dont care Table 8 Transmitter LPF Coarse 3dB Corner Frequency Settings in Register A3 A0 1000 BITS 01 00 3dB CORNER FREQUENCY
48. ts 09 08 10 in Register 8 A3 A0 1000 to multiplex the power detector analog output voltage to the RSSI output pin 16 Synthesizer Programming The 2831 2832 integrate a 20 bit sigma delta fractional N synthesizer allowing the device to achieve excellent phase noise performance 0 9 RMS from 10kHz to 10 2 fast PLL settling times and an RF fre quency step size of 20Hz The synthesizer includes a divide by 1 or a divide by 2 reference frequency divider an 8 bit integer portion main divider with a divi sor range programmable from 64 to 255 and a 20 bit fractional portion main divider Bit D2 in Register 5 0 0101 sets the reference oscillator divider ratio to 1 or 2 Bits D7 DO in Register 3 A3 A0 0011 set the integer portion of the main divider The 20 bit frac tional portion of the main divider is split between two registers The 14 MSBs of the fractional portion are set in Register 4 0 0100 and the 6 LSBs of the frac tional portion of the main divider are set in Register 3 A3 A0 0011 See Tables 11 and 12 MAXIM 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Calculating Integer and Fractional Divider Ratios LO Frequency Divider fpg 2437 2 The desired integer and fractional divider ratios can be 20MHz 121 85 calculated by dividing the RF frequency fag by Integer Divider 121 d 0111 1001 binary For nominal 802 11g b op
49. v MAKLM 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA Typical Operating Characteristics continued MAX2831 EV kit Vcc_ 2 8V VCCPA VCCTXPA 3 3V TA 25 C fi o 2 437GHz fReF 40MHz SHDN CS high RXHP SCLK DIN low 3V 0v 500mV ov 500mV Rx BB VGA SETTLING RESPONSE 8 GAIN STEP 40ns div MAX2831 32 toc19 OV 500mV OV 500mV Rx BB VGA SETTLING RESPONSE 40ns div 2831 32 toc20 3V oV 500mV OV 500mV Rx BB VGA SETTLING RESPONSE 32 GAIN STEP 40ns div MAX2831 32 toc21 ct 8cXVMW LESCXVM Rx BB FREQUENCY RESPONSE vs FINE SETTING COARSE SETTING 8 5MHz RF LNA SETTLING RESPONSE HIGH TO LOW RF LNA SETTLING RESPONSE HIGH TO MEDIUM MAX2831 32 toc22 MAX2831 32 toc23 2 3V MAX2831 32 toc24 dB OV 500mV 6 OV E 8 500mV 40 100ns div 100ns div 1 10 00 FREQUENCY MHz Rx BB FREQUENCY RESPONSE vs RX BASEBAND FILTER COARSE SETTING FINE SETTING 010 GROUP DELAY HISTOGRAM Rx STATIC DC OFFSET 20 2831 32 toc26 MEAN OmV STD 0 977mV SAMPLE SIZE 1006 2831 32 10625 2831 32 0627 dB 20ns div 100
50. yocera CX 3225SB See Figure 1 The crystal oscillator frequency can be fine tuned through bits D6 DO in Register 14 A3 A0 1110 which control the value of from 0 5pF to 15 4pF in 0 12 steps See the Crystal Oscillator Offset Frequency vs Crystal Oscillator Tuning Bits graph in the Typical Operating Characteristics The crystal oscillator can be used as a buffer for an external reference fre quency source In this case the reference signal is AC coupled to the XTAL pin and capacitors C1 and C2 are not connected When used as a buffer the XTAL input pin has to be AC coupled The XTAL pin has an input impedance of 5kQ Il 4pF set D6 DO 0000000 Register 14 A3 A0 1110 MAXIM MAX2831 MAX2832 FOR EXTERNAL REFERENCE CLOCK SET C1 C2 OPEN Figure 1 Crystal Oscillator Schematic 26 Reference Clock Output Divider Buffer The reference oscillator of the MAX2831 MAX2832 has a divider and a buffered output for routing the refer ence clock to the accompanying baseband IC Bit D10 in Register 14 0 1110 sets the buffer divider to divide by 1 or 2 independent of the divide ratio for the reference frequency provided to the PLL Bit B9 in the same register enables or disables the reference buffer output See the Clock Output waveform in the Typical Operating Characteristics Loop Filter The PLL charge pump output CPOUT pin 24 con nects to an external
51. z 2300 2350 2400 2450 2500 2550 2600 P JAMMER dBm RF FREQUENCY MHz MAXIM 11 CESSCXVIN FESSCXVIN MAX2831 MAX2832 2 4GHz to 2 5GHz 802 11g b RF Transceivers with Integrated PA SCLK DIN low Rx RSSI OUTPUT vs INPUT POWER LNA HIGH GAIN 25 MAX2831 32 toc10 2 0 FLNA MEDIUM GAI RSSI OUTPUT V 0 5 LNA LOW GAIN 120 100 80 60 40 20 0 2 Pin dBm Rx 1 0 DC OFFSET SETTLING RESPONSE 8dB BB VGA GAIN STEP MAX2831 32 toc13 40ns div Rx 1 0 DC OFFSET SETTLING RESPONSE 32dB BB VGA GAIN STEP MAX2831 32 toc16 400ns div 12 Typical Operating Characteristics continued MAX2831 EV kit Vcc_ 2 8V VCCPA VCCTXPA 3 3V TA 25 C fi o 2 437GHz fReF 40MHz SHDN CS high RXHP Rx RSSI STEP RESPONSE 32dB LNA GAIN STEP MAX2831 32 toc11 200ns div Rx 1 0 DC OFFSET SETTLING RESPONSE 84 BB VGA GAIN STEP MAX2831 32 1014 2 5V OV 10mV 5mV OmV 40ns div 1 Q OUTPUT DC ERROR DR00P RxHP 1 0 100Hz MODE MAX2831 32 toc17 20ms div Rx RSSI STEP RESPONSE 32dB LNA GAIN STEP 2831 32 toc12 200ns div Rx 1 0 DC OFFSET SETTLING RESPONSE 16dB BB VGA GAIN STEP 2831 32 toc15 3V Vr 10mV 5mV 0v 400ns div Rx BB VGA SETTLING RESPONSE 8 GAIN STEP MAX2831 32 toc18 I I i I s OV 500mV OV 500 40ns di
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MAXIM MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA handbook