MAXIM MAX5182/MAX5185 handbook
Contents
1. E T a amp 5 ce e 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 25 30 35 40 45 50 55 NPUT CODE NPUT CODE SUPPLY VOLTAGE V ANALOG SUPPLY CURRENT DIGITAL SUPPLY CURRENT DIGITAL SUPPLY CURRENT vs TEMPERATURE vs SUPPLY VOLTAGE vs TEMPERATURE 3 00 10 4 00 g g b 8 8 z E 275 375 a a amp BE ec CE 6 s 2 gt 250 5182 lt 21 950 5 4 E 72 wn 72 en f a S 225 5 5 325 lt a 2 a 2 00 0 3 00 4 145 0 3 60 85 25 30 35 40 45 50 55 4 15 10 3 60 85 TEMPERATURE SUPPLY VOLTAGE V TEMPERATURE C STANDBY CURRENT MAX5182 MAX5185 SHUTDOWN CURRENT vs SUPPLY VOLTAGE STANDBY CURRENT vs TEMPERATURE vs SUPPLY VOLTAGE _ 590 3 3 07 5 580 B MAX5182 06 gt on amp MAX518 570 E 5 t5 05 560 550 04 25 30 35 40 45 50 55 40 15 10 35 60 85 25 30 35 40 45 50 55 SUPPLY VOLTAGE V TEMPERATURE SUPPLY VOLTAGE V AVLAZCLAVI Dual 10 Bit 40MHz Current Voltage Alternate Phase Output DACs Typical Operating Characteristics continued AVpp DVpp 3V AGND DGND 0 4000 differential output IFs 1m2. REFO pin must be buffered with an external amplifier if heavier loading is required The MAX5182 MAX5185 also employ a control amplifier designed to simultaneously regulate the full scale out put current IFS for both outputs of the ICs The output current is calculated as follows IFS 8 x IREF where IREF is the reference output current IREF VREFO RSET and IFs is the full scale output current RsET is the reference resistor that determines the amplifier s output current Figure 2 on the MAX5182 This current is mirrored into the current source array where it is equally distributed between matched current segments and summed to valid output current read ings for the DACs Inside the MAX5185 each output current DAC1 and DAC2 is converted to an output voltage VoUT1 VOUT2 with two internal ground referenced 4000 load resistors Using the internal 1 2V reference voltage the MAX51895 s integrated reference output current resistor RSET 9 6kQ sets IREF to 125 and IFs to 1mA MAXIM Dual 10 Bit 40MHz Current Voltage Alternate Phase Output DACs OPTIONAL EXTERNAL BUFF FOR HEAVIER LOADS REN MAXIM MAX4040 12N BANDGAP REFERENCE MAXIM MAX5182 MAX5185 CURRENT SOURCE ARRAY COMPENSATION CAPACITOR COMP 100nF 9 6kQ REFERENCE CURRENT SET RESISTOR INTERNAL TO MAX5185 ONLY USE EXTERNAL MAX5182 Figure 2 Setting IFs with the Internal
3. grounding and power supply decoupling guidelines for high speed high frequency applications should be closely followed First a multilayer PC board with separate ground and power supply planes is recommended High speed signals should run on controlled impedance lines directly above the ground plane Since the MAX5182 MAX5185 have separate analog and digital ground buses AGND and DGND respectively the PC board should also have separate analog and digital ground sections with only one point connecting the two Digital signals should run above the digital ground and plane and analog signals should run above the analog ground plane Both devices have two power supply inputs analog Vpp AVpp and digital DVpp Each AVpp input should be decoupled with parallel 10uF and 0 1uF ceramic chip capacitors as close to the pin as possi ble Their opposite ends should have the shortest pos sible connection to the ground plane The DVpp pins should also have separate 10yF and 0 1uF capacitors again adjacent to their respective pins Try to minimize the analog load capacitance for proper operation For best performance it is recommended to bypass CREF1 and CREF2 with low ESR 0 1uF capacitors to AVpp The power supply voltages should also be decoupled at the point they enter the PC board with large tantalum or electrolytic capacitors Ferrite beads with additional decoupling capacitors forming a pi network could also improve performan
4. offset point For a DAC the offset point is the step value when the digital input is zero This error affects all codes by the same amount and can usually be compensated by trimming DIFFERENTIAL LINEARITY ERROR 1 4 LSB 4 LSB i DIFFERENTIALS 0 7 LINEARITY ERROR 1 4 LSB ANALOG OUTPUT VALUE 3 010 01 100 101 DIGITAL INPUT CODE gt IDEAL FULL SCALE OUTPUT 7 p TOM GAIN ERROR 1 1 4 LSB D IDEAL DIAGRAM PM PL i ACTUAL FULL SCALE OUTPUT gt f gt a gt o ce e g z lt 000 100 101 110 DIGITAL INPUT CODE 3 Figure 5d Gain Error 11 MAKINI S8LGXVMW C8LSXVIMW 5182 5185 Dual 10 Bit 40MHz Current Voltage Alternate Phase Output DACs Gain Error Gain error Figure 5d is the difference between the ideal and the actual full scale output voltage on the transfer curve after nullifying the offset error This error alters the slope of the transfer function and corre sponds to the same percentage error in each step Settling Time Settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the converter s specified accuracy Digital Feedthrough Digital feedthrough is the noise generated on a DAC s output when any digital input transitions Proper board layout and grounding will significant
5. 00Q loads in parallel with a 5pF capacitive load The MAX5185 features integrated 400Q resistors that restore the array currents into pro portional differential voltages of 400mV These differ ential output voltages can then be used to drive a balun transformer or a low distortion high speed operational amplifier to convert the differential voltage into a single ended voltage Applications Information Static and Dynamic Performance Definitions Integral Nonlinearity Integral nonlinearity INL Figure 5a is the deviation of the values on an actual transfer function from either a best straight line fit closest approximation to the actual ANALOG OUTPUT VALUE gt 000 001 010 011 100 101 110 111 DIGITAL INPUT CODE 3 ACTUAL P DIAGRAM a ACTUAL OFFSET 1 67 POINT IDEAL OFFSET POINT 001 010 011 DIGITAL INPUT CODE OFFSET ERROR 1 1 4 LSB Figure 5c Offset Error transfer curve or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullified For a DAC the deviations are mea sured every single step Differential Nonlinearity Differential nonlinearity DNL Figure 5b is the differ ence between an actual step height and the ideal value of 1LSB A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function Offset Error Offset error Figure 5c is the difference between the ideal and the actual
6. 1 2 Reference and the Control Amplifier BANDGAP REFERENCE EXTERNAL 1 2V REFERENCE CURRENT MAXUM SOURCE ARRAY MAX6520 AGND MAXIM MAX5182 MAX5185 9 6kQ REFERENCE CURRENT SET RESISTOR INTERNAL TO MAX5185 ONLY USE EXTERNAL Rset FOR MAX5182 Figure 3 5 182 5 185 with External Reference MAKIM 9 S8LSXVIN CSELSXVIN 5182 5185 Dual 10 Bit 40MHz Current Voltage Alternate Phase Output DACs Figure 4 Timing Diagram Table 1 Power Down Mode Selection wo Ae XXX PD DACEN POWER DOWN SELECT DACENABLE POWER DOWN MODE OUTPUT STATE MAX5182 High Z 0 0 Standby MAX5185 AGND 0 1 Wake Up Last state prior to standby mode 1 5182 High Z pees MAX5185 AGND X Don t care External Reference To disable the MAX5182 MAX5185 s internal reference connect REN to DVpp A temperature stable external reference may now be applied to drive the REFO pin Figure 3 to set the full scale output Be sure to choose a reference capable of supplying at least 150pA to drive the bias circuit that generates the cascode cur rent for the current array For improved accuracy and drift performance chose a fixed output voltage refer ence such as the 1 2V 25ppm C MAX6520 bandgap reference Standby Mode To enter the lower power standby mode connect digital inputs PD and DACEN to DGND In standby both the referenc
7. 2MHz TA 25 57 70 Total Harmonic Distortion to THD OLK 40MHz OUT 550 2 70 dB Nyquist OUT 2 2MHz TA 25 68 63 Signal to Noise Ratio to SNR OLK 40MHz OUT 550kHz 61 dB Nyquist OUT 2 2MHz TA 25 C 56 59 DAC to DAC Ouput Isolation OUT 2 2MHz 60 dB Clock and Data Feedthrough All Os to all 1s 50 nVs Output Noise 10 pA NHz ed Betwesn fouT 2 2MHz TA 25 405 1 FSR ANALOG OUTPUT Full Scale Output Voltage VES 400 mV Voltage Compliance of Output 0 3 0 8 V Output Leakage Current DACEN 0 MAX5182 only 1 1 HA Full Scale Output Current IFS MAX5182 only 0 5 1 1 5 mA is External Output Resistor R MAX5182 only 400 Q 2 AVLAZCLAVI Dual 10 Bit 40MHz Current Voltage Alternate Phase Output DACs ELECTRICAL CHARACTERISTICS continued AVpp DVpp 3V 1096 AGND DGND 0 40MHz IFs 1 4000 differential output CL 5pF TA TMIN to TMAX unless otherwise noted Typical values are at TA 25 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE Output Voltage Range VREF 2 7 1 2 1 28 V Output Voltage Temperature Drift TCVREF 50 ppm C om Output Drive 10 UA Reference Supply Rejection 0 5 mvV V Current Gain IFs IREF 8 mA mA POWER REQUIREMENTS Analog Power Supply Volta
8. 80 9 98 jeslap OTES 5 0250 0300 0 635 0762 D amp E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS x evzi 2287 688 7 29 MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 006 PER SIDE N 1 e 3 pos BIER E Y APPLY ONLY 16 AND 28 4A X 4 5 PROPRIETARY INFORMATION CONTROLLING DIMENSIONS INCHES me MEETS JEDEC M0137 APPROVAL DOCUMENT CONTROL NO REV 1 L Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses implied Maxim reserves the right to change the circuitry and specifications without notice at any time 14 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2001 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products
9. A CL 5pF TA 25 C unless otherwise noted INTERNAL REFERENCE VOLTAGE vs SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE vs TEMPERATURE 1 28 i 28 127 27 e 126 126 e gt m 5182 m 3 amp 125 8 125 5 m Hi 5185 124 124 1 23 1 23 25 30 35 40 45 50 55 40 15 10 35 60 85 SUPPLY VOLTAGE V TEMPERATURE C DYNAMIC RESPONSE RISE TIME DYNAMIC RESPONSE FALL TIME OUT P OUT P 150mV 150mv div div OUT N OUT N 150mV 150mV div div 50ns div 50ns div FFT PLOT DAC1 FFT PLOT DAC2 0 0 E 40 four 22MHz 10 four 22MHz 8 40 fcuk 40MHz g 20 20 3 30 30 40 40 _ 50 _ 50 a c Rz S 60 S 60 70 70 5 80 L4 80 90 Mi 90 i 100 100 110 110 i i 120 120 LL L 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 OUTPUT FREQUENCY MHz OUTPUT FREQUENCY MHz MAKIM OUTPUT CURRENT vs REFERENCE CURRENT MAX5182 85 13 0 125 250 REFERENCE CURRENT uA SETTLING TIME 375 500 MAX5182 85 16 12 5ns div SPURIOUS FREE DYNAMIC RANGE vs CLOCK FREQUENCY MAX5182 85 19 10 15 20 25 30 3
10. AZCLAVI Dual 10 Bit 40MHz Current Voltage Alternate Phase Output DACs Pin Description PIN NAME FUNCTION 1 CREF1 Reference Bias Bypass DAC1 2 OUT1P Positive Analog Output DAC1 Current output for MAX5182 voltage output for MAX5185 3 OUT1N Negative Analog Output DAC1 Current output for MAX5182 voltage output for MAX5185 4 AGND Analog Ground 5 AVDD Analog Positive Supply 2 7V to 3 3V DAC Enable Digital Input q d X Enter shutdown mode with PD DVpp X don t care Power Down Select 7 PD 0 Enter DAC standby mode DACEN DGND or power up DAC DACEN DVpp 1 Enter shutdown mode 8 CS Active Low Chip Select 9 CLK Clock Input 10 N C No Connection Do not connect to this pin 11 REN Active Low Reference Enable Connect to DGND to activate the on chip 1 2V reference 12 21 D0 D9 Data Bit DO LSB to Data Bit D9 MSB 22 DVDD Digital Supply 2 7V to 3 3V 23 DGND Digital Ground 24 REFR Reference Input 25 REFO Reference Output 26 OUT2N Negative Analog Output DAC2 Current output for MAX5182 voltage output for MAX5185 27 OUT2P Positive Analog Output DAC2 Current output for MAX5182 voltage output for MAX5185 28 CREF2 Reference Bias Bypass DAC2 AVLAZCLAVI S8LGXVMW C8LSXVIMW 5182 5185 Dual 10 Bit 40MHz Current Voltage Alternate Phase Output DACs AVpp AGND CS DACEN PD CURRENT SOUR
11. CE ARRAY DAC 1 SWITCHES DAC 2 SWITCHES TPUT OUTPUT TCHES LATCHES MSB DECODE MSB MAXIM MAX5182 et MAX5 185 LATCHES INTERNAL 4000 AND 9 6kQ RESISTORS FOR MAX5185 ONLY Figure 1 Functional Diagram Detailed Description The MAX5182 MAX5185 are dual 10 bit digital to ana log converters DACs capable of operating with clock speeds up to 40MHz Each of these dual converters consists of separate input and DAC registers followed by a current source array capable of generating up to 1 5mA full scale output current Figure 1 An integrated 1 2V voltage reference and control amplifier determine the data converters full scale output currents voltages Careful reference design ensures close gain matching and excellent drift characteristics The MAX5185 with its voltage output operation features matched 4000 on chip resistors that convert the current from the current array into a voltage Internal Reference and Control Amplifier The MAX5182 MAX5185 provide an integrated 50ppm C 1 2V low noise bandgap reference which can be disabled and overridden by an external refer ence voltage REFO serves either as an input for an external reference or as an output for the integrated ref erence If REN is connected to DGND the internal ref erence is selected and REFO provides a 1 2V output Due to its limited 10A output drive capability the 8 DVpp DGND
12. CLOCK FREQ 5 40 4 UENCY 5 50 55 60 Hz S8LGXVMW C8LSXVIW 100mV 100mV 5182 5185 Dual 10 Bit 40MHz Current Voltage Alternate Phase Output DACs Typical Operating Characteristics continued AVpp DVpp 3V AGND 0 4000 differential output IFs 1mA CL 5pF TA 25 C unless otherwise noted SPURIOUS FREE DYNAMIC RANGE vs OUTPUT SPURIOUS FREE DYNAMIC RANGE vs OUTPUT SIGNAL TO NOISE PLUS DISTORTION FREQUENCY AND CLOCK FREQUENCY DAC1 FREQUENCY AND CLOCK FREQUENCY DAC2 vs OUTPUT FREQUENCY 78 78 625 8 50MHz 20 7 fcLk 40MHz 3 76 76 i 620 74 74 8 8 615 DAC2 B 72 Hi 72 2 610 DAC1 70 70 68 10 gt 2 60 5 30MHz 66 66 60 0 500 700 900 1100 1300 1500 1700 1900 2100 2300 500 700 900 1100 1300 1500 1700 1900 2100 2300 0 500 1000 1500 2000 2500 OUTPUT FREQUENCY kHz OUTPUT FREQUENCY kHz OUTPUT FREQUENCY kHz MULTITONE SPURIOUS FREE DYNAMIC RANGE SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY vs FULL SCALE OUTPUT CURRENT 8 74 g o az U 70 8 68 e I B c5 66 64 62 60 0 2 4 6 8 10 12 14 16 18 20 0 50 0 75 1 00 125 150 OUTPUT FREQUENCY MHz FULL SCALE OUTPUT CURRENT mA 6 AVL
13. ce MAXIM Dual 10 Bit 40MHz Current Voltage Alternate Phase Output DACs AVpp AVpp P o Jour DVpp CREF1 CREF2 JTUL OUTIP OUTPUT1 MAXIM MAX5182 MAX5185 OUTIN OUTPUT2 MAXIM MAX4108 DGND REN 400Q RESISTORS INTERNAL TO MAX5185 ONLY 5182 ONLY Figure 6 Differential to Single Ended Conversion Using a Low Distortion Amplifier Chip Information TRANSISTOR COUNT 9464 SUBSTRATE CONNECTED TO AGND AVLAZCLAVI 13 S8LGXVMW C8LGSXVIW 5182 5185 Dual 10 Bit 40MHz Current Voltage Alternate Phase Output DACs Package Information QSOP EPS S B INCHES MILLIMETERS r E 8 DIM MIN Max MIN MAX L 3 L 3 L 3 L 3 L 3 VARIATIDNS SEE VARIATIONS 2 209 A 1061 e8 155 173 i Al 004 o098 010 0 249 1 a2 055 os 140 155 lt B 008 020 031 C 0075 0098 0191 0 249 H 4 Y D SEE VARIATIUNS E 150 457 s8 399 e 025 BSC 0 635 BSC H 230 244 584 620 h oes 041 Jon U L ow 3 o4 089 N X Y a Ae 196 480 0070 0 05 X a23 272 342 D 337 344 ese 8 74 S o5o0 0550 1 270 1397 D 337 344 856 874 24 AC 5 0250 0300 0 635 0762 D 386 393 9
14. e 40 C to 85 C AGND IO DON Dursin 0 3V to 0 3V Storage Temperature Range 65 C to 150 C tO DVD 3 3V Lead Temperature soldering 105 300 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS AVpp DVpp 3V 10 AGND DGND 0 40MHZ IFs 1mA 400Q differential output CL 5pF TA TMIN to TMAX unless otherwise noted Typical values are at Ta 25 C PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N 10 Bits Integral Nonlinearity INL 2 0 5 2 LSB Differential Nonlinearity DNL Guaranteed monotonic 1 0 5 1 LSB it MAX5182 2 2 Zero Scale Error LSB MAX5185 8 8 Full Scale Error Note 1 40 15 40 LSB DYNAMIC PERFORMANCE Output Settling Time To 0 5LSB error band 25 ns Glitch Impulse 10 pVs Spurious Free Dynamic Range SFDR OLK 40MHz OUT 550kHz 72 dBc to Nyquist OUT 2
15. e and the control amplifier are active with the current array inactive To exit this condition DACEN must be pulled high with PD held at DGND The MAX5182 MAX5185 typically require 50us to wake up and let both outputs and reference settle 10 Shutdown Mode For lowest power consumption the MAX5182 MAX5185 provide a power down mode in which the reference control amplifier and current array are inactive and the DACs supply current is reduced to 1pA To enter this mode connect PD to DVpp To return to active mode connect PD to DGND and DACEN to DVpp About 50us are required for the devices to leave the shutdown mode and to settle their outputs to the values prior to shutdown Table 1 lists the power down mode selection Timing Information Both internal DAC cells write to their outputs in alternate phase Figure 4 The input latch of the first DAC DAC1 is loaded after the clock signal transitions high When the clock signal transitions low the input latch of the second DAC DAC2 is loaded The contents of the first input latch are shifted into the DAC1 register on the rising edge of the clock the contents of the second input latch are shifted into the input register of DAC2 on the falling edge of the clock Both outputs are updated on alternate phases of the clock MAXIM Dual 10 Bit 40MHz Current Voltage Alternate Phase Output DACs Outputs The MAX5182 outputs are designed to supply 1mA full scale output currents into 4
16. ge AVDD 2 7 3 3 V Analog Supply Current IAVDD D e lp digital inputs atg 2 7 5 0 mA Digital Power Supply Voltage DVpp 2 7 3 3 V Digital Supply Current IDVDD ere 1 digital inputs at 0 4 2 5 0 mA Standby Current ISTANDBY T 0 digital inputs at 0 1 0 1 5 mA Shutdown Current ISHDN UE RR NE 0 5 1 HA LOGIC INPUTS AND OUTPUTS Digital Input Voltage High 2 V Digital Input Voltage Low VIL 0 8 V Digital Input Current IIN VIN 0 or DVpp 1 UA Digital Input Capacitance Ci 10 pF TIMING CHARACTERISTICS DAC1 DATA to CLK Rise a 10 T Setup Time DAC2 DATA to CLK Fall 1582 10 Setup Time DAC1 CLK Rise to DATA iso 0 e old Time DAC2 CLK Fall to DATA biis 0 m old Time CS Fall to CLK Rise Time 5 ns CS Fall to CLK Fall Time 5 ns DACEN Rise Time to Vour 0 5 us PD Fall Time to VouT_ 50 us Clock Period tcLK 25 ns Clock High Time tcH 10 0 ns Clock Low Time tcL 10 ns Note 1 Excludes reference and reference resistor MAX5185 tolerance AVLAZCLAVI 3 S8LGXVMW C8LGSXVM 5182 5185 Dual 10 Bit 40MHz Current Voltage Alternate Phase Output DACs Typical Operating Characteristics AVpp DVpp 3V AGND DGND 0 4000 differential output IFs 1mA CL 5pF TA 25 C unless otherwise noted DIFFERENTIAL NONLINEARITY vs INPUT CODE ANALOG SUPPLY CURRENT vs SUPPLY VOLTAGE INTEGRAL NONLINEARITY vs INPUT CODE
17. ly reduce this noise but there will always be some feedthrough caused by the DAC itself Total Harmonic Distortion Total harmonic distortion THD is the ratio of the RMS sum of the input signal s first four harmonics to the fun damental itself This is expressed as We Va 7 Vc THD 20xlog V where V1 is the fundamental amplitude and V2 through V5 are the amplitudes of the 2nd through 5th order harmonics Spurious Free Dynamic Range Spurious free dynamic range SFDR is the ratio of RMS amplitude of the fundamental maximum signal compo nent to the RMS value of the next largest distortion component Differential to Single Ended Conversion The MAX4108 low distortion high input bandwidth amplifier may be used to generate a voltage from the MAX5182 s current array output The differential voltage across OUT1P or OUT2P and OUT1N or OUT2N is converted into a single ended voltage by designing an appropriate operational amplifier configuration as shown in Figure 6 12 Grounding and Power Supply Decoupling Grounding and power supply decoupling strongly influ ence the performance of the MAX5182 MAX5185 Unwanted digital crosstalk may couple through the input reference power supply and ground connec tions which may affect dynamic specifications like sig nal to noise ratio or SFDR In addition electromagnetic interference EMI can either couple into or be generat ed by the MAX5182 MAX5185 Therefore
18. o mE n full DAC operation allows for power conservation by MAXS1825EEI i eek 28 QSOP activating the DACs only when required MAX5185BEEI 40 to 85 C 28 QSOP The MAX5182 MAX5185 are available in a 28 pin QSOP package and are specified for the extended 40 C to 85 C temperature range For pin compatible 8 bit versions refer to the MAX5188 MAX5191 data sheet Internal 1 2V Low Noise Bandgap Reference Small 28 Pin QSOP Package 9 9 9 Pin Configuration Applications TOP VIEW Signal Reconstruction Digital Signal Processing Arbitrary Waveform Generators AWGs Imaging Applications MAXIM MAX5182 MAX5185 AVLAZCLAVI Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Dallas Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com S8LGXVMW C8LSXVIW 5182 5185 Dual 10 Bit 40MHz Current Voltage Alternate Phase Output DACs ABSOLUTE MAXIMUM RATINGS AVpp DVpp to AGND DGND 0 3V to 46V Maximum Current into Any Pin 50mA Digital Inputs to DGND sss 0 3V to 6V Continuous Power Dissipation Ta 70 C OUT1P OUT1N OUT2P OUT2N CREF1 28 Pin QSOP derate 9 00mW C above 70 725mW CBEE2 to AGND uuu se 0 3V to 6V Operating Temperature Ranges VREF lO AGNI 0 3V to 6V MAX518 BEEI ss
19. ss Ror 1201 Dual 10 Bit 40MHz Current Voltage Alternate Phase Output DACs General Description Features The MAX5182 is a dual 10 bit alternate phase update 2 7V to 3 3V Single Supply Operation current output digital to analog converter DAC designed for superior performance in systems requiring Wide Spurious Free Dynamic Range 70dB at analog signal reconstruction with low distortion and four 2 2MHz low power operation The MAX5185 provides equal Fully Differential Outputs for Each DAC specifications with on chip output resistors for voltage 0 5 FSR Gain Mismatch Between DAC Outputs output operation Both devices are designed for 10pV s glitch operation to reduce distortion and minimize Low Current Standby or Full Shutdown Modes unwanted spurious signal components at the output An on board 1 2 bandgap circuit provides a well regu lated low noise reference that can be disabled for external reference operation The MAX5182 MAX5185 are designed to provide a high level of signal integrity for the least amount of power dis sipation Both DACs operate from a 2 7V to 3 3V sin gle supply Additionally these DACs have three modes of operation normal low power standby and complete shutdown A full shutdown provides the lowest possible Ordering Information power dissipation with a maximum shutdown current of PART TEMP RANGE PIN PACKAGE 1 Fast wake up time 0 5us from standby mode t
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MAXIM MAX5182/MAX5185 handbook