MAXIM MAX1446 10-Bit 60Msps 3.0V Low-Power ADC with Internal Reference handbook
Contents
1. THD 20xlog y where V4 is the fundamental amplitude and V2 through V5 are the amplitudes of the 2nd through 5th order harmonics Spurious Free Dynamic Range SFDR SFDR is the ratio expressed in decibels of the rms amplitude of the fundamental maximum signal compo nent to the rms value of the next largest spurious com ponent excluding DC offset Intermodulation Distortion IMD The two tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd order or higher inter modulation products The individual input tone levels are at 6 58B full scale CLK TL wp ANALOG INPUT tap TH TRACK HOLD TRACK Figure 12 T H Aperture Timing MAXIM 10 Bit GOMsps 3 0V Low Power ADC with Internal Reference Pin Configurations continued TOP VIEW MAXIM MAX1446 Package Information For the latest package outline information and land patterns go to www maxim ic com packages PACKAGE TYPE PACKAGE CODE DOCUMENT NO MAXIM 19 MAX1446 10 Bit G0Msps 3 0V Low Power ADC with Internal Reference REVISION REVISION NUMBER DATE Revision History DESCRIPTION PAGES CHANGED 11 07 Various corrections updated to extended temperature range for automotive applications replaced TOCs 9 20 23 24 26 30 31 33 updated package outlines 1 9 15 18 20 21 11 08 Updates to the Electrical Characteristics table and notes se2. fci 62 5MHz 50 duty cycle TA TMIN to Tmax unless otherwise noted 2 gt 25 C guaranteed by production test lt 25 C guaranteed by design and characterization Typical values are at Ta 25 C PARAMETER SYMBOL CONDITIONS DC ACCURACY Resolution Integral Nonlinearity 7 492MHz TA gt 25 C Differential Nonlinearity No missing codes 7 492MHz Offset Error Gain Error Ta 25 C ANALOG INPUT Input Differential Range Differential or single ended inputs Common Mode Voltage Range Input Resistance Switched capacitor load Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS 7 492MHz Signal to Noise Ratio 19 943MHz 39 9MHz Note 1 7 492MHz 19 943MHz 39 9MHz Note 1 7 492MHz 19 943MHz 39 9MHz Note 1 Signal to Noise Distortion Up to 5th Harmonic Spurious Free Dynamic Range 2 10 Bit GOMsps 3 0V Low Power ADC with Internal Reference ELECTRICAL CHARACTERISTICS continued Vpp 3 0V OVpp 2 7V O 1yF and 1 0uF capacitors from REFP REFN and COM to GND VReFin 2 048V REFOUT connected to REFIN through a 10kQ resistor Vin 2Vp p differential with respect to COM 10pF at digital outputs fci 62 5MHz 50 duty cycle TA TMIN to Tmax unless otherwise noted 2 gt 25 C guaranteed by production test lt 25 C
3. SNR 60 1dB SNR 59 508 J R 59 6dB THD 71 5dBc THD 72 908 D 70 7dBc 1 SINAD 59 8dB SFDR 74 3dBc DR 72 2dBc ES 8 8 z 8 a fa c 3 35 5 10 4 20 25 30 35 35 ANALOG INPUT FREQUENCY MHz ANALOG INPUT FREQUENCY MHz ANALOG INPUT FREQUENCY MHz FFT PLOT FFT PLOT FFT PLOT fin 26 8MHz 8192 POINT FFT fin 50MHz 8192 POINT FFT fin 7 5MHz 8192 POINT FFT DIFFERENTIAL INPUT DIFFERENTIAL INPUT SINGLE ENDED INPUT SINAD 59 0 3 SFDR 70dBc 59 508 8 SNR 59 4dB 3 SNR 59 1dB 10 R 597dB 43 THD 70 5dBc THD 67 1dBc p D 73 0dBc 2 SFDR 72 9dBc SINAD 58 508 SFDR 73 6dBc 30 z wo Ex p 50 4 lt 70 8 90 8 iui i o B i TUIN nm 10 Ti bi ad o liui 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 ANALOG INPUT FREQUENCY MHz ANALOG INPUT FREQUENCY MHz ANALOG INPUT FREQUENCY MHz FFT PLOT TWO TONE INTERMODULATION SPURIOUS FREE DYNAMIC RANGE fin 20MHz 8192 POINT FFT 8192 POINT IMD vs ANALOG INPUT FREQUENCY SINGLE ENDED INPUT DIFFERENTIAL INPUT Ain 0 5dBFS SINAD 59 2cB O 65dBFS E E 10 SNR 595dB 2 10 15 21MHz AT 6 5dBFS E DIFFERE 20 3RD IMD 76dBc E 75 2 3 30 70 a 4 ws 40 E E 50 50 65 B 9 m 5 LE ENDED 70 70 a 80 m 80 55 90 b L bin TIT ERIT TERN 90 Pi p 100 MI ill i NN Lb ll 1 50 0 5
4. to be driven directly by a set of exter nal reference sources Followed by a 10Hz lowpass fil ter and precision voltage divider Figure 11 the MAX6066 generates a DC level of 2 500V The buffered outputs of this divider are set to 2 0V 1 5V and 1 0V with an accuracy that depends on the tolerance of the divider resistors The three voltages are buffered by the 16 COM REFIN MAXIM REFP MAX1446 N 1000 REFN COM MAX4252 which provides low noise and low DC offset The individual voltage followers are connected to 10Hz lowpass filters which filter both the reference voltage and amplifier noise to a level of 3nVHz The 2 0V and 1 0V reference voltages set the differential full scale range of the associated ADCs at 2Vp p The 2 0V and 1 0V buffers drive the ADC s internal ladder resistances between them Note that the common power supply for all active components removes any concern regarding power supply sequencing when powering up or down With the outputs of the MAX4252 matching better than 0 1 the buffers and subsequent lowpass filters can be replicated to support as many as 32 ADCs For applications that require more than 32 matched ADCs a voltage reference and divider string common to all converters is highly recommended MAXIM 10 Bit GOMsps 3 0V Low Power ADC with Internal Reference MAXIM 2 0V AT 8mA Nz1 MAX6066 MAXIMA REFOUT REFIN MAXIM MAX1446 REF
5. 0 15 20 25 30 35 0 5 10 15 20 25 30 35 0 10 20 30 40 50 60 70 80 90 ANALOG INPUT FREQUENCY MHz ANALOG INPUT FREQUENCY MHz ANALOG INPUT FREQUENCY MHz 6 MAKLM 10 Bit GOMsps 3 0V Low Power ADC with Internal Reference Typical Operating Characteristics continued Vpp 3 0V OVpp 2 7V internal reference differential input at 0 5dBFS fci 62 35MHz 10pF TA 25 C unless otherwise noted SIGNAL TO NOISE RATIO TOTAL HARMONIC DISTORTION SIGNAL TO NOISE AND DISTORTION vs ANALOG INPUT FREQUENCY vs ANALOG INPUT FREQUENCY vs ANALOG INPUT FREQUENCY Ain 0 5dBFS Ain 0 5dBFS Ain 0 5dBFS 60 2 50 60 DIFFERENT ENTIAL LJE H 59 59 55 58 _ 58 ns s7 a 65 2 56 i ss 70 INGLE ENDED T 54 B DIFFERENTIAL 53 55 80 52 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90 ANALOG INPUT FREQUENCY MHz ANALOG INPUT FREQUENCY MHz ANALOG INPUT FREQUENCY MHz SPURIOUS FREE DYNAMIC RANGE SIGNAL TO NOISE RATIO TOTAL HARMONIC DISTORTION vs ANALOG INPUT POWER vs ANALOG INPUT POWER vs ANALOG INPUT POWER fin 19 943MHz fin 19 943
6. 19 1729 Rev 4 11 08 LU ATION E AVAILABL General Description The MAX1446 10 bit 3V analog to digital converter ADC features a fully differential input a pipelined 10 stage ADC architecture with digital error correction and wideband track and hold T H incorporating a fully dif ferential signal path This ADC is optimized for low power high dynamic performance applications in imaging and digital communications The MAX1446 operates from a single 2 7V to 3 6V supply consuming only 90mW while delivering a 59 5dB signal to noise ratio SNR at a 20MHz input frequency The fully differ ential input stage has a 400MHz 3dB bandwidth and may be operated with single ended inputs In addition to low operating power the MAX1446 features a 5uA power down mode for idle periods An internal 2 048V precision bandgap reference is used to set the ADC full scale range A flexible reference structure allows the user to supply a buffered direct or externally derived reference for applications requiring increased accuracy or a different input voltage range Lower and higher speed pin compatible versions of the MAX1446 are also available Refer to the MAX1444 data sheet for a 40Msps version the MAX1448 data sheet for an 80Msps version and the MAX1449 data sheet for a 105Msps version The MAX1446 has parallel offset binary three state outputs that can be operated from 1 7V to 3 3V to allow flexible interfacing The device is ava
7. 3b SNR vs Clock Duty Cycle Differential Input Figure 4b SINAD vs Clock Duty Cycle Differential Input tENABLE DISABLE OUTPUT HIGH Z HIGH Z DATA 09 00 VALID DATA Figure 5 Output Enable Timing MAXUM 13 SPUD LXVIN MAX1446 10 Bit GOMsps 3 0V Low Power ADC with Internal Reference samples at the falling edge of the input clock Output data is valid on the rising edge of the input clock The output data has an internal latency of 5 5 clock cycles Figure 6 also shows the relationship between the input clock parameters and the valid output data Applications Information Figure 7 shows a typical application circuit containing a single ended to differential converter The internal refer ence provides a Vpp 2 output voltage for level shifting purposes The input is buffered and then split to a volt age follower and inverter A lowpass filter follows the op amps to suppress some of the wideband noise associ ated with high speed op amps The user may select the Riso and values to optimize the filter performance to suit a particular application For the application in Figure 7 an Riso of 50Q is placed before the capaci tive load to prevent ringing and oscillation The 22pF CIN capacitor acts as a small bypassing capacitor Using Transformer Coupling An RF transformer Figure 8 provides an excellent solution for converting a single ended source signal to a fully differential signal required by the MAX144
8. 6 for optimum performance Connecting the transformer s center tap to COM provides a Vpp 2 DC level shift to the input Although a 1 1 transformer is shown a step up transformer may be selected to reduce the drive requirements A reduced signal swing from the input driver such as an op amp may also improve the over all distortion In general the MAX1446 provides better SFDR and THD with fully differential input signals than single ended drive especially for very high input frequencies In differential input mode even order harmonics are lower since both inputs IN IN are balanced and each of the inputs only requires half the signal swing compared to single ended mode Single Ended AC Coupled Input Signal Figure 9 shows an AC coupled single ended applica tion The MAX4108 op amp provides high speed high bandwidth low noise and low distortion to maintain the integrity of the input signal Buffered External Reference Drives Multiple ADCs Multiple converter systems based on the MAX1446 are well suited for use with a common reference voltage The REFIN pin of those converters can be connected directly to an external reference source A precision bandgap reference like the MAX6062 generates an external DC level of 2 048V Figure 10 and exhibits a noise voltage density of 150nVHz Its output passes through a 1 pole lowpass filter with 10Hz cutoff fre quency to the MAX4250 which buffers the reference before its out
9. ATURE C OVpp V 8 MAXIM 10 Bit GOMsps 3 0V Low Power ADC with Internal Reference Typical Operating Characteristics continued Vpp 3 0V OVpp 2 7V internal reference differential input at 0 5dBFS fci 62 35MHz 10pF Ta 25 C unless otherwise noted DIGITAL SUPPLY CURRENT ANALOG POWER DOWN CURRENT DIGITAL POWER DOWN CURRENT vs TEMPERATURE vs ANALOG POWER SUPPLY vs DIGITAL POWER SUPPLY 20 8 9 g fin 7 5MHz 3 E E E E 16 105 z 12 EM 5 4 0 MEM IL 270 285 300 315 330 345 3 60 TEMPERATURE a 45 8 OVpp V Vpp V INTERNAL REFERENCE VOLTAGE INTERNAL REFERENCE VOLTAGE SNR SINAD THD SFDR vs CLOCK FREQUENCY vs ANALOG SUPPLY VOLTAGE vs TEMPERATURE 80 E 210 a 3 S 74 z 2 08 E 5 5 68 206 o ea o E m G8 204 gt Z 5 202 Hz A 0 5dBFS 50 2 00 j 5 62 86 270 285 300 315 330 345 360 40 15 10 35 60 85 110 CLOCK FREQUENCY MHz V TEMPERATURE C OUTPUT NOISE HISTOGRAM DC INPUT MAX1446 toc34 129421 COUNT N 2 NH N N N 2 DIGITAL OUTPUT CODE MAXI 9 10 Bit GOMsps 3 0V Low Power ADC with Internal Reference Pin Description REFN Lower Reference Conversion range is V
10. IC DISTORTION SIGNAL TO NOISE AND DISTORTION INTEGRAL NONLINEARITY vs DIGITAL vs TEMPERATURE vs TEMPERATURE OUTPUT CODE BEST STRAIGHT LINE 60 2 70 5 5 943MHz Ain 0 5dBFS E fin 19 943MHz 0 5dBFS 3 fin 7 5MHz g E 4 64 66 T 68 62 02 nn pz z a iF d Wiis 72 A 58 i m 0 TIT 105 0 1 bi Ta 105 Mi TW 80 50 0 3 110 40 5 10 35 60 85 10 0 200 400 600 800 1000 1200 TEMPERATURE C TEMPERATURE C DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY GAIN ERROR vs TEMPERATURE OFFSET ERROR vs TEMPERATURE vs DIGITAL OUTPUT CODE EXTERNAL REFERENCE Vperin 2 048V EXTERNAL REFERENCE Vperin 2 048V 0 3 3 10 8 10 fiy 7 5MHz 3 8 E 8 E 0 T ih lh MERIIN vl 6 6 1 Em _ lh 4 p 4 0 ult 2 55 28 2 2 EE 0 1 T il go amp 0 02 i T lii MAU 20 b 2 LP 5 PIN IE 4 5 4 0 3 6 6 0 4 8 8 0 5 10 10 0 200 400 600 800 1000 1200 40 5 10 35 60 85 10 40 45 1 35 6 85 110 DIGITAL OUTPUT CODE TEMPERATURE C TEMPERATURE C ANALOG SUPPLY CURRENT ANALOG SUPPLY CURRENT DIGITAL SUPPLY CURRENT vs ANALOG SUPPLY VOLTAGE vs TEMPERATURE vs DIGITAL SUPPLY VOLTAGE 35 s 50 g 8 E 46 fin 7 5MHz 33 3 42 7 3 38 6 z 3 34 2 30 8 5 29 26 22 27 18 3 14 25 10 2 270 285 300 315 330 345 3 60 40 45 10 3 60 85 10 12 18 24 30 36 Vpp V TEMPER
11. MHz fin 19 943MHz 80 2 66 50 75 60 E 55 70 54 60 65 48 S 60 42 70 55 36 75 50 30 80 20 46 12 8 4 0 20 46 12 8 4 0 20 46 12 8 4 0 ANALOG INPUT POWER dBFS ANALOG INPUT POWER dBFS ANALOG INPUT POWER dBFS SIGNAL TO NOISE AND DISTORTION vs ANALOG INPUT POWER SPURIOUS FREE DYNAMIC RANGE fin 19 943MHz vs TEMPERATURE SIGNAL TO NOISE RATIO vs TEMPERATURE 65 80 t 70 E fin 19 943MHz 0 5dBFS fin 19 943MHz Ain 0 5dBFS 60 E 2 76 66 E 55 amp 4 g n 5 5 5 68 sg 40 64 54 35 30 60 50 20 16 8 4 0 40 15 10 35 60 85 40 15 10 35 60 85 ANALOG INPUT POWER dBFS TEMPERATURE C TEMPERATURE C MAXI 7 MAX1446 10 Bit GOMsps 3 0V Low Power ADC with Internal Reference Typical Operating Characteristics continued Vpp 3 0V OVpp 2 7V internal reference differential input at 0 5dBFS fci 62 35MHz 10pF Ta 25 C unless otherwise noted THD dBc DNL LSB TOTAL HARMON
12. N 1 4 MAX4252 6V AAA gt 33V 47 MAXIM 1 4 4252 AAA e 1 5V AT OmA COM 10uF 6V MAX4254 POWER SUPPLY BYPASSING PLACE CAPACITOR AS CLOSE AS 14rkQ POSSIBLE TO THE OP AMP NOTE ONE FRONT END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 32 ADCs Figure 11 Unbuffered External Reference Drives Up to 32 ADCs Grounding Bypassing _ Board Layout The MAX1446 requires high speed board layout design techniques Locate all bypass capacitors as close to the device as possible preferably on the same side as the ADC using surface mount devices for minimum inductance Bypass Vpp REFP REFN and COM with two parallel 0 1uF ceramic capacitors and a 2 2uF bipolar capacitor to GND Follow the same rules to bypass the digital supply OVpp to OGND Multilayer boards with separated ground and power planes pro MAXI REFOUT REFIN MAXIM MAX1446 N 32 REFN COM duce the highest level of signal integrity Consider using a split ground plane arranged to match the physi cal location of the analog ground GND and the digital output driver ground OGND on the ADC s package The two ground planes should be joined at a single point so that the noisy digital ground currents do not interfere with the analog ground plane The ideal loca tion of this connection can be determined experimen tally at a poi
13. REFP VREFN Bypass to GND with a gt 0 1uF capacitor Common Mode Voltage Output Bypass to GND with a gt 0 1uF capacitor MAX1446 Analog Supply Voltage Bypass to GND with a capacitor combination of 2 2uF in parallel with O 1uF Analog Ground Positive Analog Input For single ended operation connect signal source to IN egative Analog Input For single ended operation connect IN to COM Conversion Clock Input Power Down Input High power down mode Low normal operation Output Enable Input High digital outputs disabled Low digital outputs enabled Three State Digital Outputs D9 D5 D9 is the MSB Output Driver Supply Voltage Bypass to GND with a capacitor combination of 2 2uF in parallel with O 1yF Test Point Do not connect Output Driver Ground Three State Digital Outputs D4 DO DO is the LSB Internal Reference Voltage Output May be connected to REFIN through a resistor or a resistor divider Reference Input VREFIN 2 x VngrP VREFN Bypass to GND with a gt 0 01uF capacitor Upper Reference Conversion range is VREFP VREFN Bypass to GND with a gt 0 1uF capacitor 10 MAXIM 10 Bit GOMsps 3 0V Low Power ADC with Internal Reference Detailed Description The MAX1446 uses a 10 stage fully differential pipelined architecture Figure 1 that allows for high speed conversion while minimizing power consump tion Each sample mo
14. al Reference ABSOLUTE MAXIMUM RATINGS Vp OVDDO QNI teet tete etta 0 3V to 3 6V Continuous Power Dissipation Ta 70 C to GND 0 3V to 0 3V 32 Pin TQFP derate 18 7mW C above 70 C 1495 3mW INF asas ce ete nce eter he dots 0 3V to Vpp Operating Temperature Ranges REFIN REFOUT REFP MAXTAAJOEH secte ctt terat tein 40 C to 85 C REFN and COM to 0 3V to Vpp 0 3V 14469 40 to 105 C OE PD CL TO GND 0 3V to Vpp 0 3V Storage Temperature Range 60 C to 150 C D9 DO to GND 0 3V to OVpp 0 3V Lead Temperature soldering 105 300 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS Vpp 3 0V OVpp 2 7V O 1yF and 1 0uF capacitors from REFP REFN and COM to GND VReFin 2 048V REFOUT connected to REFIN through a 10kQ resistor Vin 2Vp p differential with respect to COM 10pF at digital outputs
15. ction 5 14 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 20 2008 Maxim Integrated Products Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 Maxim is a registered trademark of Maxim Integrated Products Inc
16. d Vpp 3 0V OVpp 2 7V 0 1uF and 1 0uF capacitors from R EFP REFN and COM to GND VngriN 2 048V REFOUT connected to REFIN through a 10kQ resistor Vin 2Vp p differential wi th respect to COM C 10pF at digital outputs fci 62 5MHz 50 duty cycle TA TMIN to Tmax unless otherwise noted 2 gt 25 C guaranteed by production test lt 25 C guaranteed by design and characterization Typical values are at Ta 25 C PARAMETER SYMBOL CONDITIONS UNITS Maximum REFN Source Current ISOURCE Maximum REFN Sink Current ISINK UNBUFFERED EXTERNAL REFERENCE VngriN AGND reference voltage applied to REFP RE Measured between REFP and COM and REFN and COM REFP REFN Input Resistance REFP REFN COM Input Capacitance Differential Reference Input Voltage Range AVREF VREFP VREFN COM Input Voltage Range REFP Input Voltage Vcom AVREF 2 REFN Input Voltage VCOM AVREF 2 DIGITAL OUTPUTS CLK PD OE Input High Threshold Low Threshold Hysteresis Vp VDD Leakage Vi 20 DIGITAL OUTPUTS D9 DO Output Voltage Low ISINK 200 Output Voltage High ISOURCE 200 Three State Leakage Current Three State Output Capacitance MAXIM 10 Bit GOMsps 3 0V Low Power ADC with Internal Reference ELECTRICAL CHARACTERISTICS continued Vpp 3 0V OVpp 2 7V O 1
17. formance The use of buffers on the ADC s digital outputs can further isolate the digital outputs from heavy capacitive loads To further improve the dynamic performance of the MAX1446 small series resistors e g 1000 may be added to the digital output paths close to the ADC Figure 5 displays the timing relationship between out put enable and data output valid as well as power down wake up and data output valid System Timing Requirements Figure 6 shows the relationship between the clock input analog input and data output The MAX1446 STRAIGHT OFFSET BINARY 11 1111 1111 11 1111 1110 VREF x 1 512 1LSB 10 0000 0001 0 Bipolar Zero 10 0000 0000 VREF x 1 512 1LSB 01 1111 1111 Negative Full Scale 1LSB 00 0000 0001 VREF x 511 512 VREF x 512 512 VREFIN VREFP VREFN 12 Negative Full Scale 00 0000 0000 MAXIM 10 Bit GOMsps 3 0V Low Power ADC with Internal Reference fin 12 5MHz AT 0 5dBFS 5MHz AT 0 5dBFS 40 80 20 30 40 50 60 70 20 30 40 50 60 70 CLOCK DUTY CYCLE CLOCK DUTY CYCLE Figure 3a SFDR vs Clock Duty Cycle Differential Input Figure 4a THD vs Clock Duty Cycle Differential Input 5MHz AT 0 5dBFS fin 12 5MHz AT 0 5dBFS rp 20 30 40 50 60 70 20 30 40 50 60 70 CLOCK DUTY CYCLE CLOCK DUTY CYCLE Figure
18. guaranteed by design and characterization Typical values are at Ta 25 C PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IN 7 492MHz 74 Third Harmonic Distortion HD3 IN 19 943MHZ 73 dBc IN 39 9MHz Note 1 71 Distortion M9 oie at 650665 Note 2 75 de uae IN 7 492MHz 70 64 Bop ee THD fin 19 943MHz IN 39 9MHz Note 1 69 Small Signal Bandwidth Input at 20dBFS differential inputs 500 MHz Full Power Bandwidth FPBW Input at 0 5dBFS differential inputs 400 MHz Aperture Delay tAD 1 ns Aperture Jitter tAJ 2 psrms Overdrive Recovery Time For 1 5 x full scale input 2 ns Differential Gain 1 Differential Phase 0 25 Output Noise IN IN COM 0 2 LSBrms INTERNAL REFERENCE Reference Output Voltage REFOUT pras V d RE TREE 60 Load Regulation 1 25 mV mA BUFFERED EXTERNAL REFERENCE Veerin 2 048V REFIN Input Voltage VREFIN 2 048 Positive Reference Output Voltage VREFP 2 012 V bin Reference Output BEEN 0 988 V Common Mode Level VCOM Vpp 2 V Output AVREF AVREF VREFP VREFN TA 25 C 0 98 1 024 1 07 V REFIN Resistance RREFIN gt 50 MQ Maximum REFP COM Source je QuBGE 5 mA Current COM Sink 250 UA MAXI 3 MAX1446 10 Bit GOMsps 3 0V L ow Power ADC with Internal Reference ELECTRICAL CHARACTERISTICS continue
19. ilable in a 5mm x 5mm 32 pin TQFP package and is specified over the extended industrial 40 C to 85 C and automotive 40 C to 105 C temperature ranges ___ Applications Ultrasound Imaging CCD Imaging Baseband and IF Digitization Digital Set Top Boxes Video Digitizing Applications Pin Compatible Lower Higher Speed Versions SAMPLING SPEED Msps 40 80 MAXIM AVLAZCIL AVI 10 Bit GOMsps 3 0V Low Power ADC with Internal Reference Features Single 3 0V Operation Excellent Dynamic Performance 59 5dB SNR at fin 20MHz 73dB SFDR at fin 20MHz Low Power 30mA Normal Operation 5pA Shutdown Mode Fully Differential Analog Input Wide 2Vp p Differential Input Voltage Range 400MHz 3dB Input Bandwidth On Chip 2 048V Precision Bandgap Reference CMOS Compatible Three State Outputs 32 Pin TQFP Package Evaluation Kit Available MAX1448 EV Kit 9 9 9 9 9 9 Ordering Information PIN PACKAGE MAX1446EHJ 40 C to 85 C 32 TQFP MAX1446GHJ 40 C to 105 C 32 TQFP Denotes a lead Pb free ROHS compliant package PART TEMP RANGE Functional Diagram MAXIMA MAX1446 CONTROL REFOUT REFIN REFP COM REFN Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com SPUD LXVIN MAX1446 10 Bit GOMsps 3 0V Low Power ADC with Intern
20. lay Aperture delay tAp is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken Figure 12 Signal to Noise Ratio SNR For a waveform perfectly reconstructed from digital samples the theoretical maximum SNR is the ratio of the full scale analog input rms value to the rms quanti zation error residual error The ideal theoretical mini mum A D noise is caused by quantization error only and results directly from the ADC s resolution N bits SNR MAX 6 02 x N 1 76 In reality there are other noise sources besides quanti zation noise thermal noise reference noise clock jitter etc SNR is computed by taking the ratio of the rms sig nal to the rms noise which includes all spectral compo nents minus the fundamental the first five harmonics and the DC offset Signal to Noise Plus Distortion SINAD SINAD is computed by taking the ratio of the rms signal to all spectral components minus the fundamental and the DC offset 18 Effective Number of Bits ENOB ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate An ideal ADC s error consists of quantization noise only ENOB is computed from SINAD 1 76 6 02 ENOB Total Harmonic Distortion THD THD is typically the ratio of the rms sum of the input signal s first four harmonics to the fundamental itself This is expressed as V22 V32 V42 t Vg V1
21. nal reference mode the internal reference out put REFOUT can be tied to the REFIN pin through a resistor e g 10kQ or resistor divider if an application requires a reduced full scale range For stability pur poses it is recommended to bypass REFIN with a gt 10nF capacitor to GND In buffered external reference mode the reference volt age levels can be adjusted externally by applying a stable and accurate voltage at REFIN In this mode REFOUT may be left open or connected to REFIN through a gt 10kQ resistor In unbuffered external reference mode REFIN is con nected to GND thereby deactivating the on chip buffers of REFP COM and REFN With their buffers shut down these pins become high impedance and can be driven by external reference sources Clock Input CLK The MAX1446 CLK input accepts CMOS compatible clock signals Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock use a clock with low jitter and fast rise and fall times lt 2ns In particular sampling occurs on the falling edge of the clock signal mandating this edge to provide lowest possible jitter Any significant aperture jitter would limit the SNR per formance of the ADC as follows SNR 20x log 2xmnx fN XtAJ where fiN represents the analog input frequency and tAJ is the time of the aperture jitter Table 1 MAX1446 Output Code for Differential Inpu
22. nt along the gap between the two ground planes that produces optimum results Make this con nection with a low value surface mount resistor 1Q to 5Q a ferrite bead or a direct short Alternatively all 17 SPUD LXVIN MAX1446 10 Bit G0Msps 3 0V Low Power ADC with Internal Reference ground pins could share the same ground plane if the ground plane is sufficiently isolated from any noisy dig ital systems ground plane e g downstream output buffer or DSP ground plane Route high speed digital signal traces away from sensitive analog traces Keep all signal lines short and free of 90 turns Static Parameter Definitions Integral Nonlinearity Integral nonlinearity INL is the deviation of the values on an actual transfer function from a straight line This straight line can be either a best straight line fit or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullified The MAX1446 s static linearity parameters are measured using the best straight line fit method Differential Nonlinearity Differential nonlinearity DNL is the difference between an actual step width and the ideal value of 1LSB A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function Dynamic Parameter Definitions Aperture Jitter Figure 12 depicts the aperture jitter tAJ which is the sample to sample variation in the aperture delay Aperture De
23. put is applied to a second 10Hz lowpass gS 6L0CK CYCLE LATENCY gt ANALOG INPUT DATA OUTPUT Figure 6 System and Output Timing Diagram 14 MAXIM 10 Bit G0Msps 3 0V Low Power ADC with Internal Reference MAXIM MAX1446 LOWPASS FILTE NVV Riso Vin MAXIM MAX4108 i 1000 7 MAXIM MAX1446 MINI CIRCUITS ADTI 1WT Riso 500 Cin 22pF Figure 8 Using a Transformer for AC Coupling Figure 9 Single Ended AC Coupled Input MAXI 15 9bPv LXVIN MAX1446 10 Bit GOMsps 3 0V Low Power ADC with Internal Reference MAXIM MAX6062 REFOUT REFIN MAXIM REFP MAX1446 N 1 REFN 10Hz LOWPASS FILTER NOTE ONE FRONT END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs Figure 10 Buffered External Reference Drives Up to 1000 ADCs filter The MAX4250 provides a low offset voltage for high gain accuracy and a low noise level The passive 10Hz filter following the buffer attenuates noise pro duced in the voltage reference and buffer stages This filtered noise density which decreases for higher fre quencies meets the noise levels specified for precision ADC operation Unbuffered External Reference Drives Multiple ADCs Connecting each REFIN to analog ground disables the internal reference of each device allowing the internal reference ladders
24. re closed con necting capacitors C1a and C1b to the amplifier output S4c is closed This charges Cla and C1b to the same values originally held on C2a and C2b This value is then presented to the first stage quantizer and iso lates the pipeline from the fast changing input The wide input bandwidth T H amplifier allows the 1446 to track and sample hold analog inputs of high frequencies beyond Nyquist The analog inputs IN and IN can be driven either differentially or single ended It is recommended to match the impedance of IN and IN and set the common mode voltage to mid supply Vpp 2 for optimum performance Analog Input and Reference Configuration The MAX1446 full scale range is determined by the internally generated voltage difference between REFP VDD 2 VREFIN 4 and REFN Vpp 2 VREFIN 4 The ADC s full scale range is user adjustable through the REFIN pin which provides a high input impedance for this purpose REFOUT REFP COM Vpp 2 and REFN are internally buffered low impedance outputs INTERNAL BIAS INTERNAL BIAS CLK INTERNAL HOLD NONOVERLAPPING CLOCK SIGNALS Figure 2 Internal T H Circuit SPUD LXVIN MAX1446 10 Bit G0Msps 3 0V Low Power ADC with Internal Reference The MAX1446 provides three modes of reference oper ation e Internal reference mode e Buffered external reference mode e Unbuffered external reference mode In inter
25. ts DIFFERENTIAL INPUT Full Scale 1LSB Full Scale 2LSB DIFFERENTIAL INPUT VOLTAGE VREF x 511 512 Veer x 510 512 Clock jitter is especially critical for undersampling applications The clock input should always be consid ered as an analog input and routed away from any ana log input or other digital signal lines The MAX1446 clock input operates with a voltage threshold set to Vpp 2 Clock inputs with a duty cycle other than 50 must meet the specifications for high and low periods as stated in the Electrical Character istics See Figures 3a 3b 4a and 4b for the relation ship between spurious free dynamic range SFDR signal to noise ratio SNR total harmonic distortion THD or signal to noise plus distortion SINAD vs duty cycle Output Enable OE Power Down PD and Output Data DO D9 All data outputs DO LSB through D9 MSB are TTL CMOS logic compatible There is a 5 5 clock cycle latency between any particular sample and its valid output data The output coding is straight offset binary Table 1 With OE and PD power down high the digi tal output enters a high impedance state If OE is held low with PD high the outputs are latched at the last value prior to the power down The capacitive load on the digital outputs DO D9 should be kept as low as possible lt 15pF to avoid large digital currents that could feed back into the ana log portion of the MAX1446 degrading its dynamic per
26. uts settle to VIL Note 4 Wake up time is defined as the time from complete reference power down until the ADC performs within 0 3 ENOB of the 2 3yF Note 5 Dynamic characteristics guaranteed at fin 19 943MHz for the specified duty cycle range better if referenced to the two tone envelope Note 6 Guaranteed by design and engineering characterization MAXIM inal performance for fin 10MHz at 0 5dBFS input amplitude VREFIN 2 048V REFN and CML decoupled with MAX1446 10 Bit GOMsps 3 0V Low Power ADC with Internal Reference Typical Operating Characteristics Vpp 3 0V OVpp 2 7 internal reference differential input at 0 5dBFS fci 62 35MHz 10pF TA 25 C unless otherwise noted FFT PLOT FFT PLOT FFT PLOT fin 7 5MHz 8192 POINT FFT fin 13 3MHz 8192 POINT FFT fin 20MHz 8192 POINT FFT DIFFERENTIAL INPUT DIFFERENTIAL INPUT DIFFERENTIAL INPUT SFDR 72 2dBc SINAD 59 348 AD 59 308 8
27. ves through a pipeline stage every half clock cycle Counting the delay through the output latch the clock cycle latency is 5 5 A 1 5 bit 2 comparator flash ADC converts the held input voltage into a digital code The following digital to analog converter DAC converts the digitized result back into an analog voltage which is then subtracted from the original held input signal The resulting error signal is then multiplied by two and the product is passed along to the next pipeline stage where the process is repeated until the signal has been process ed by all 10 stages Each stage provides a 1 bit resolu tion Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes Input Track and Hold Circuit Figure 2 displays a simplified functional diagram of the input T H circuit in both track and hold mode In track mode switches S1 S2a S2b S4a S4b S5a and S5b are closed The fully differential circuit samples the input signal onto the two capacitors C2a and C2b S2a and S2b set the common mode for the amplifier 1 5 bits STAGE 1 m STAGE 2 DIGITAL CORRECTION LOGIC a 9 Vin INPUT VOLTAGE BETWEEN IN AND IN DIFFERENTIAL OR SINGLE ENDED Figure 1 Pipelined Architecture Stage Blocks MAALM input The resulting differential voltage is held on C2a and C2b S4a S4b S5a S5b S1 S2a and S2b are then opened before S3a S3b and S4c a
28. yF and 1 0uF capacitors from REFP REFN and COM to GND VReFin 2 048V REFOUT connected to REFIN through a 10kQ resistor Vin 2Vp p differential with respect to COM 10pF at digital outputs fci 62 5MHz 50 duty cycle TA Tmin to Tmax unless ot and characterization Typical values are at Ta 25 C PARAMETER POWER REQUIREMENTS Analog Supply Voltage SYMBOL CONDITIONS herwise noted gt 25 C guaranteed by production test lt 25 C guaranteed by design 3 0 3 6 Output Supply Voltage 10pF 3 0 3 6 Analog Supply Current Operating fin 19 943MHz at 0 5dBFS Shutdown clock idle PD OE OVpp 30 37 Output Supply Current Operating CL 15pF fin 19 943MHz at 0 5dBFS Shutdown clock idle PD OE OVpp Power Supply Rejection TIMING CHARACTERISTICS CLK Rise to Output Data Valid tDO Offset Gain Figure 5 Notes 3 6 E Fall to Output Enable tENABLE Figure 5 E Rise to Output Disable tDISABLE Figure 5 Clock Duty Cycle Figure 6 clock period 16ns Notes 5 6 45 55 Wake Up Time tWAKE Notes 4 6 366 520 us Note 1 SNR SINAD THD SFDR and HD3 are based on an analog input voltage of 0 5dBFS referenced to a 1 024V full scale input voltage range Note 2 Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier This number is Note 3 Digital outp
Download Pdf Manuals
Related Search
MAXIM MAX1446 10 Bit 60Msps 3.0V Low Power ADC with Internal Reference handbook