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MAXIM MAX1426 10-Bit 10Msps ADC handbook

1. REFN CML applied externally Input Resistance RIN REFIN Note 8 6 5 Input Capacitance CIN REFIN 10 pF Differential Reference VREFP VREFN 2 0 V Input Current li REFP CML REFN 325 325 HA Input Capacitance CIN REFP CML REFN 15 pF E 3 25 REFP Input Range 10 V 225 CML Input Range 10 V E 1 25 REFN Input Range 10 V REFERENCE OUTPUTS REFP CML REFN external 2 5V reference Positive Reference Voltage VREFP 3 25 V Common Mode Reference Voltage VCML 2 25 V Negative Reference Input Voltage VREFN yes u Differential Reference VREFP VREFN A 25 C 1 9 2 0 2 1 V Differential Reference S Temperature Coefficient 90 ppmc 3 9CDLXVIN MAX1426 10 Bit 10Msps ADC ELECTRICAL CHARACTERISTICS continued VAVpp VCMLP 5V Vpvpp 3 3V VCMLN VAGND VDGND OV internal reference digital output loading 35pF to Tmax unless otherwise noted Typical values are at Ta 25 C 10MHz 50 duty cycle TA TMI PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE OUTPUT REFP CML REFN internal 2 5V reference Positive Reference VREFP Note 1 3 25 V Common Mode Reference Voltage VCML Note 1 2 25 V Negative Reference VREFN Note 1 1 25 V Differential Reference VnErP VREFN TA 25 1 8 2 2 2 V Differential Reference Te
2. Figure 1 Pipelined A D Architecture Block the residue by two and the next stage in the pipeline performs a similar operation System Timing Requirements Figure 3 shows the relationship between the clock input analog input and data output The MAX1426 samples the falling edge of the input clock Output data is valid on the rising edge of the input clock The output data has an internal latency of 5 5 clock cycles as shown Figure 4 shows an output timing diagram that specifies the relationship between the input clock para meters and the valid output data Analog Input and Internal Reference The MAX1426 has an internal 2 5V reference used to generate three reference levels 3 25V 2 25V and 1 25V corresponding to VREFP VCML and VREEN These reference voltages enable a 2V input range Bypass all reference voltages with a 0 1uF capacitor The MAX1426 allows for three modes of reference operation an internal reference default mode an externally adjusted reference mode or a full external reference mode The internal reference mode occurs when no voltages are applied to REFIN REFP CML b HOLD MODE Figure 2 Internal Track and Hold Circuit n 2 ANALOG INPUT 5 5 CLOCK CYCLE LATENCY 10Msps ADC n 3 CLOCK INPUT DATA OUTPUT Figure 4 Output Timing Diagram and REFN In this mode the voltages at these pins are
3. per tains to the package regardless of RoHS status PACKAGE TYPE PACKAGE CODE OUTLINE NO LAND PATTERN NO 28 SSOP A28 1 21 0056 90 0095 MAXUM 15 9CULXVIN MAX1426 10 Bit 10Msps ADC Revision History REVISION REVISION DESCRIPTION PAGES CHANGED Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 16 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
4. 19 1598 Rev 1 7 11 General Description The MAX1426 10 bit monolithic analog to digital con verter ADC is capable of a 10Msps sampling rate This device features an internal track and hold T H amplifier for excellent dynamic performance at the same time it minimizes the number of external components Low input capacitance of only 8pF minimizes input drive requirements A wide input bandwidth up to 150MHz makes this device suitable for digital RF IF downconvert er applications employing undersampling techniques The MAX1426 employs a differential pipelined architec ture with a wideband T H amplifier to maximize through put while limiting power consumption to only 156mW The MAX1426 generates an internal 2 5V reference that supplies three additional reference voltages 3 25V 2 25V and 1 25V These reference volt ages provide a differential input range of 2V to 2V The analog inputs are biased internally to correct the DC level eliminating the need for external biasing on AC coupled applications A separate 3V digital logic supply input allows for separation of digital and analog circuitry The output data is in two s complement format The MAX1426 is available in the space saving 28 pin SSOP package For a pin compatible version at a higher data rate refer to the MAX1424 or MAX1425 Applications Medical Ultrasound Imaging CCD Pixel Processing IR Focal Plane Array Radar IF and Baseband Digitization Set Top
5. Boxes Functional Diagram MAXIM MAX1426 INTERFACE PIPELINE ADC REF SYSTEM BIAS REFIN CML REF MAKI 10 Bit 10Msps ADC Features Differential Inputs for High Common Mode Noise Rejection 61dB Signal to Noise Ratio at fin 2MHz Internal 2 5V Reference 150MHz Input Bandwidth Wide 2V Input Range Low Power Consumption 156mW 9 9 9 9 9 Separate Digital Supply Input for 3V Logic Compatibility Single 5V Operation Possible Ordering Information PART TEMP RANGE PIN PACKAGE MAX1426CAI 0 C to 70 C 28 SSOP MAX1426EAI 40 C to 85 C 28 SSOP Denotes a lead Pb free ROHS compliant package Devices are also available in a tape and reel package Specify tape and reel by adding T to the number when order ing Pin Configuration TOP VIEW MAXIMA MAX1426 Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com 9CULXVIN MAX1426 10 Bit 10Msps ADC ABSOLUTE MAXIMUM RATINGS AVpp to AGND esc 0 3V to 6V DVpp to DGND s 0 3V to 6V AVpp to DGND eh 0 3V to 6V DGND to tereti 0 3V REFP REFIN REFN CMLN CMLP CML INP INN aaa VAGND 0 3V to Vavpp 0 3V CLK OE PD D0 D9 VbGND 0 3V to Vpypp 0 3V Continuo
6. REE DYNAMIC RANGE vs POWER fin 9 942MHz TOTAL HARMONIC DISTORTION vs POWER fin 1 997MHz TOTAL HARMONIC DISTORTION vs POWER fiy 4 942MHz 8 0 z 0 6 20 20 4 2 40 24 wn 2 60 60 80 80 60 45 30 5 0 60 45 30 5 0 60 45 30 15 0 INPUT dB INPUT dB INPUT dB EFFECTIVE NUMBER OF BITS EFFECTIVE NUMBER OF BITS EFFECTIVE NUMBER OF BITS vs POWER fin 1 997MHz vs POWER fiy 4 942MHz vs INPUT FREQUENCY 10 2 10 z 10 0 8 n 8 T 6 2 6 B 92 a 4 Bid 2 2 84 0 0 80 60 45 30 15 0 60 45 30 15 0 2 3 1 5 INPUT dB INPUT dB INPUT FREQUENCY MHz SIGNAL TO NOISE RATIO TOTAL HARMONIC DISTORTION SIGNAL TO NOISE PLUS DISTORTION vs INPUT FREQUENCY vs INPUT FREQUENCY vs INPUT FREQUENCY 60 70 61 2 71 59 e 72 3 2 s 438 a 58 58 74 57 75 57 2 3 4 5 2 9 4 5 2 3 4 5 INPUT FREQUENCY MHz INPUT FREQUENCY MHz INPUT FREQUENCY MHz MAX1426 10 Bit 10Msps ADC Typical Operating Characteristics continued VAVpp VCMLP 5V VDVpp 3 3V VCMLN VAGND OV internal reference digital output load 35pF 10MHz 50 duty cycle for dynamic performance OGB is full scale Ta 25 C unless otherwise noted FFT PLOT
7. SR Internal reference Note 1 10 5 10 External reference REFIN Note 2 5 2 5 Gain Error GE FSR External reference REFP CML REFN 5 3 5 Note 3 Power Supply Rejection Ratio PSRR Note 4 5 2 5 mvV V DYNAMIC PERFORMANCE Ay 1 0dBFS Signal to Noise Ratio SNR f 2MHz 60 61 dB Spurious Free Dynamic Range SFDR f 2MHz 69 72 dB Total Harmonic Distortion THD f 2MHz 70 67 dB first five harmonics Signal to Noise and Distortion SINAD f 2MHz 58 60 dB MAXIM 10 Bit 10Msps ADC ELECTRICAL CHARACTERISTICS continued VAVpp VCMLP 5V Vpvpp 3 3V VCMLN VAGND VDGND OV internal reference digital output loading 35pF 10MHz 50 duty cycle TA to Tmax unless otherwise noted Typical values are at TA 25 C PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Effective Number of Bits ENOB f 2MHz 9 3 9 7 Bits f1 1 98MHz f2 2 00MHz Intermodulation Distortion IMD 7dB FS each tone Note 5 70 dBc ANALOG INPUT INP INN CML Input Resistance RI Either input to ground 3 5 Input Capacitance Ci Either input to ground 8 pF Input Common Mode Voltage 2 25 Range CML Note 6 10 V Differential Input Range DR VINP VINN 2 V Small Signal Bandwidth SSBW Note 7 400 MHz Large Signal Bandwidth LSBW Note 7 150 MHz REFERENCE VngriN
8. data outputs DO through D9 are TTL CMOS logic compatible There is a 5 5 clock cycle latency between the start convert signal and the valid output data The output coding for the MAX1426 is in binary two s com plement format which has the MSB inverted Table 1 The digital output goes into a high impedance state and the device into a low power mode when OE PD goes high For normal operation drive OE low The out puts are not designed to drive high capacitances or 11 9cVU LXVIN MAX1426 10 Bit 10Msps ADC heavy loads as they are specified to deliver only 200 for TTL compatibility If an application needs output buffering use 74LS74s 74ALS541s as required Applications Information Figure 5 shows a typical application circuit containing a single ended to differential converter The internal ref erence provides a 2 25V output for level shifting The input is buffered and then split to a voltage follower and inverter The op amps are followed by a lowpass filter to remove some of the wideband noise associated with MAXIM MAX4108 high speed op amps In this application the amplifier outputs are directly coupled to the inputs This configura tion can also be modified for AC coupled applications The MAX1426 includes a DC level shifting circuit internal to the part allowing for AC coupled applications The level shifting circuit is shown in Figure 6 The circuit in Figure 6 can accept a 1Vp p maximum inpu
9. eference digital output load 35pF 10MHz 50 ANALOG INPUT BANDWIDTH FULL POWER fine 2MHz i 4 2 ues 5 30 2 2 2 4 amp a 2 35 6 271 80 0 200 400 60 800 1000 0 200 40 600 800 1000 001 01 1 10 100 1000 10 000 CODE CODE BANDWIDTH MHz SIGNAL TO NOISE PLUS DISTORTION SIGNAL TO NOISE RATIO PLUS DISTORTION vs POWER fiy 1 997MHz vs POWER fin 4 942MHz 80 8 80 8 20 _ 40 60 60 8 s e x 80 D zm 100 5 120 14 0 0 0 05 10 15 20 25 30 35 40 45 50 60 45 30 15 0 60 45 30 15 0 SIGNAL TO NOISE RATIO SIGNAL TO NOISE RATIO SPURIOUS FREE DYNAMIC RANGE vs POWER fiy 1 997MHz vs POWER fin 4 942MHz vs POWER fiy 1 997MHz 7 5 70 80 2 60 60 70 60 5 50 50 amp 4 40 S 40 6 30 6 30 3 20 20 1 10 10 0 0 60 45 30 15 0 60 45 30 15 0 60 45 30 15 0 INPUT dB INPUT dB INPUT dB 6 MAK LAI 10 Bit 10Msps ADC Typical Operating Characteristics continued VAVpp VCMLP 5V Vpvpp 3 3V VCMLN VAGND OV internal reference digital output load 35pF 10MHz 50 duty cycle for dynamic performance OGB is full scale TA 25 C unless otherwise noted SPURIOUS F
10. ere YO MAXIM MAX1426 rern DD 1v Figure 7 Using an External Reference for REFP REFN and CML internal reference shut down 13 MAX1426 10 Bit 10Msps ADC INN MAXIMA MAX1426 MINICIRCUITS KKB1 Figure 8 Using a Transformer for AC Coupling Bypassing and Board Layout The MAX1426 requires high speed board layout design techniques Locate all bypass capacitors as close to the device as possible using surface mount devices for minimum inductance Bypass all analog voltages AVpp REFIN REFN and CML to AGND Bypass the digital supply DVpp to DGND Multilayer boards with separated ground and power planes pro duce the highest level of signal integrity Route high speed digital signal traces away from sensitive analog traces Matching impedance especially for the input clock generator may reduce reflections thus providing less jitter in the system For optimum results use low distortion complementary components such as the MAX4108 14 500 MAXIM MAX1426 Figure 9 Single Ended AC Coupled Input Signal 10 Bit 10Msps ADC LLL Package Information For the latest package outline information and land patterns footprints go to www maxim ic com packages Note that a or in the package code indicates RoHS status only Package drawings may show a different suffix character but the drawing
11. fiy 2MHz MAX1426 19 lt 60 E 8 ii 100 i l 120 Fy 140 0 05 10 15 20 25 30 35 40 45 50 FREQUENCY MHz TOTAL SUPPLY CURRENT vs TEMPERATURE MAX1426 21 44 40 dE oom EE gt 32 22 28 24 40 15 10 35 60 85 TEMPERATURE 0 85 0 80 0 75 0 70 0 65 0 60 SHUTDOWN CURRENT mA E dB FFT PLOT fiy 5MHz MAX1426 20 MAGNITUD ENCE V FREQUENCY MHz INTERNAL REFERENCE VOLTAGE vs TEMPERATURE 1426 22 n2 D m INTERNAL REFER ne 2 10 40 15 10 35 60 85 TEMPERATURE C MAXIM 10 Bit 10Msps ADC Pin Description PIN NAME FUNCTION 1 7 AGND Analog Ground Connect all return paths for analog signals to these pins 28 AV Analog Supply Voltage Input Bypass with a parallel combination of 2 2uF 0 1uF and 100pF capacitors DE to AGND Bypass each supply input to the closest AGND e g capacitors between pins 1 and 2 Positive Reference Output Bypass to AGND with a 0 1uF capacitor If the internal reference is 3 REFP uh disabled REFP can accept an external voltage External Reference Input Bypass to AGND with a O 1uF capacitor REFIN can be biased ex
12. mperature Coefficient nied POWER SUPPLY Analog Supply Voltage VAVDD 4 75 5 00 5 25 V Digital Supply Voltage VDVDD 24 3 3 5 5 V Analog Supply Current lAVDD 29 38 mA Analog Supply Current with REFIN AGND 25 35 mA Internal Reference in Shutdown Analog Shutdown Current OE PD DVpp 0 6 1 mA m Vpvpp 3 3V 3 3 6 Digital Supply Current mA iid DVDD vpvpp 5 0V 5 3 8 Digital Shutdown Current OE PD DVpp 40 150 pA Power Dissipation PD 156 210 mW DIGITAL INPUTS CLK OE PD Vpvpp gt 4 75V 2 4 Input Logic High V V p g 9 IH lt 4 75V 0 7 x VDVDD Vpvpp gt 4 75V 0 8 In Logic Lo V V put Log w IL VbVpp lt 4 75V 0 3 x VDVDD ICLK 10 10 uA In Current Leakage V 5 25V put Cu g DVDD IGE PD 20 20 pA Input Capacitance 10 pF DIGITAL OUTPUTS 00 09 T Output Logic High VoH loH 200 Vpvpp 2 7V On V Output Logic Low VoL loL 200HA Vpvpp 2 7V 0 5 V Three State Leakage Vpvpp 5 25V OE PD DVpp 10 10 pA Three State Capacitance OE PD DVpp 10 pF AVLAZCLAM 10 Bit 10Msps ADC ELECTRICAL CHARACTERISTICS continued VAVpp VCMLP 5V Vpvpp 3 3 VCMLN VAGND VDGND OV internal reference digital output loading 35pF 10MHz 50 duty cycle TA to Tmax unless otherwise noted Typical values are at TA 25 C PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS Con
13. s ADC Detailed Description The MAX1426 uses a 10 stage fully differential pipelined architecture Figure 1 that allows for high speed conver sion while minimizing power consumption Each sample moves through a pipeline stage every half clock cycle Counting the delay through the output latch there is a 5 5 clock cycle latency A 2 bit flash ADC converts the input voltage to digital code A DAC converts the ADC result back into an ana log voltage which is subtracted from the held input sig nal The resulting error signal is then multiplied by two and this product is passed along to the next pipeline stage where the process is repeated Digital error correc tion compensates for offsets and mismatches in each pipeline stage and ensures no missing codes Internal Track and Hold Circuit Figure 2 shows a simplified functional diagram of the internal track and hold T H circuit in both track mode and hold mode The fully differential circuit samples the input signal onto the four capacitors Cla C1b C2a and C2b Switches S2a and S2b set the common mode for the amplifier input and open before S1 When 51 opens the input is sampled Switches S3a and S3b then connect capacitors Cla and C1b to the output of the amplifier Capacitors C2a and C2b are connected either to REFN REFP or each other depending on the results of the flash ADC The amplifier then multiplies STAGE 1 STAGE 2 DIGITAL CORRECTION LOGIC
14. set to their nominal values see Electrical Characteristics The reference voltage levels can be adjusted externally by applying a voltage at REFIN This allows other input levels to be used as well The full external reference mode is entered when REFIN AGND External voltages can be applied to REFP CML and REFIN In this mode the internal voltage shuts down resulting in less overall power consump tion Clock Input CLK CLK is TTL CMOS compatible Since the interstage conversion of the device depends on the rising and falling edges of the external clock use a clock with low jitter and fast rise and fall times lt 2ns Low clock jitter improves SNR performance The MAX1426 operates with a 50 duty cycle If the clock has a duty cycle other than 50 the clock must meet the specifications for high and low periods as stated in the Electrical Characteristics Table 1 MAX1426 Output Code DIFFERENTIAL INPUT NOS COMPLEMENT Full Scale 913 1311411 Full Scale 1LSB 0111111110 Full Scale 2LSB 0111111101 3 4 Full Scale 0110000000 1 2 Full Scale 0100000000 1 4 Full Scale 0010000000 1 LSB 0000000001 Bipolar Zero 0000000000 1 LSB 3 T5053 T Vs Ts 1 4 Full Scale 1110000000 1 2 Full Scale 1100000000 3 4 Full Scale 1010000000 Full Scale 1LSB 1000000001 Full Scale 1000000000 Output Enable Power Down Function OE PD and Output Data All
15. t voltage With a maximum clock frequency of 1OMHz use 50Q termination to minimize reflections Buffer the digital outputs with a low cost high speed ALAXCLAI MAX1426 MAXIMA MAX473A S F Figure 5 Typical Application Circuit Using the Internal Reference 12 ANN 6000 MAXIM octal D latched flip flop 74ALS374 or use octal buffers such as the 74ALS541 Typical Application Using an External Reference Figure 7 shows an application circuit that shuts down the internal reference allowing an external reference to be used for selecting a different common mode volt age This added flexibility also allows for ratiometric conversions as well as for calibration 10 Bit 10Msps ADC Using Transformer Coupling A small transformer Figure 8 provides isolation and AC coupling to the ADC s input Connecting the trans former s center tap to CML provides a 2 25VDC level shift to the input Transformer coupling reduces the need for high speed op amps thereby reducing cost Although a 1 1 transformer is shown a step up trans former may be selected to reduce the drive require ments Single Ended DC Coupled Input Signal Figure 9 shows an AC coupled single ended applica tion The MAX4106 quad op amp provides high speed high bandwidth low noise and low distortion to main tain the integrity of the input signal MAXIM MAX4284 n
16. ternally 4 REFIN to adjust the reference level and calibrate full scale errors To disable the internal reference connect REFIN to AGND 5 REFN Negative Reference Output Bypass to AGND with 0 1uF capacitor REFN can accept an external voltage when the internal reference is disabled REFN AGND 6 CML Common Mode Level Input Bypass to AGND with a 0 1uF capacitor CML can accept an external voltage when the internal reference is disabled REFN AGND 9 INP Positive Analog Signal Input 10 INN Negative Analog Signal Input 41 CMLP Common Mode Level Positive Input For AC applications connect to AVpp to internally set the input DC bias level For DC coupled applications connect to AGND Common Mode Level Negative Input Connect AGND to internally set the input DC bias level for 2 CMLN both AC and DC coupled applications 13 CLK Clock Input Clock frequency range from 0 1MHz to 10MHz Active Low Output Enable and Power Down Input Digital outputs become high impedance 4 OE PD HM device enters low power mode when pin is high 15 D9 Digital Data Output MSB 16 19 D8 D5 Digital Data Outputs 8 5 Digital Supply Voltage Input Bypass with 2 2uF and O 1uF capacitors in parallel Digital supply can 20 22 DVDD i operate with voltages as low as 2 7V 21 23 DGND Digital Ground 24 27 D4 D1 Digital Data Outputs 4 1 28 DO Digital Data Output LSB MAXIM 9cVU LXVIN MAX1426 10 Bit 10Msp
17. us Power Dissipation TA 70 C 28 Pin SSOP derated 9 5mW C above 70 O 762mW Operating Temperature Ranges MAXT426CA u tico caedere ctt dn tat 0 C to 70 C MAX1426EAI ssssss ee 40 C to 85 C Maximum Junction Temperature 150 C Storage Temperature Range 65 C to 150 C Lead Temperature soldering 105 300 C Soldering Temperature reflow 260 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS VAVpp VCMLP 5V Vpvpp 3 3V VCMLN VAGND VDGND OV internal reference digital output loading 35pF 10MHz 50 duty cycle TA to Tmax unless otherwise noted Typical values are at TA 25 C PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ACCURACY Resolution RES 10 Bits Differential Nonlinearity DNL 1 1 LSB Integral Nonlinearity INL 1 5 0 3 1 5 LSB No Missing Codes Guaranteed monotonic Midscale Offset MSO Note 1 3 1 0 3 F
18. version Rate CONV 0 1 10 MHz Clock Frequency fcLK 10 MHz Clock High tCH Figure 4 40 50 60 ns Clock Low teL Figure 4 40 50 60 ns Pipeline Delay Latency 5 5 cycles Aperture Delay tAD 5 ns Aperture Jitter tAJ 7 ps Data Output Delay toD 5 20 25 ns Bus Enable 10 20 ns Bus Disable 10 20 ns Note 1 Internal reference REFIN bypassed to AGND with a 0 1uF capacitor Note 2 External 2 5V reference applied to REFIN Note 3 Internal reference disabled VREFIN VREFP 3 25V VcML 2 25V and VREFN 1 25V Note 4 Measured as the ratio of the change in midscale offset voltage for a 5 change in VAvpp using the internal reference Note 5 IMD is measured with respect to either of the fundamental tones Note 6 Specifies the common mode range of the differential input signal supplied to the MAX1426 Note 7 Defined as the input frequency at which the fundamental component of the output spectrum is attenuated by Note 8 VREFIN is internally biased to 2 5V through a 5kQ resistor MAXUM 5 9CULXVIN MAX1426 10 Bit 10Msps ADC Typical Operating Characteristics duty cycle for dynamic performance OGB is full scale TA 25 C unless otherwise noted INTEGRAL NONLINEARITY vs CODE DIFFERENTIAL NONLINEARITY vs CODE VAVpp VCMLP 5V VDVpp 3 3V VCMLN VAGND OV internal r

MAXIM MAX1426 10-Bit 10Msps ADC handbook

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