ANALOG DEVICES AD8275 English products handbook Rev A
Contents
1. One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 62008 2010 Analog Devices Inc All rights reserved AD8275 TABLE OF CONTENTS Features 6e LE V EE 1 Applications TEE 1 Pin ConfiguratiOD cete iit titi ttd e tH deer 1 Typical Application s c ccsssvsssssesessssnosessesssnesevosssenssssonvsshosevessisnbevsstaseres 1 General Description rn Eee SHY s 1 REVASION HISLOP Y S See eere R E 2 Specification seien be OR o be teblern 3 Absolute Maximum Ratings sentent 4 Maximum Power Dissipation sss 4 ESDGa tionizzsicecee m E NONE Ree 4 Pin Configuration and Function Descriptions esses 5 Typical Performance Characteristics sees 6 Theory of Operation ss wll Basic Connection wll PowerSuppliesztat i DEREN RES HYS 12 REVISION HISTORY 8 10 Rev 0 to Rev A Changes to Figure T eerie aiaiai 14 10 08 Revision 0 Initial Version Reference i ccs e Mtt LE D EE 12 Common Mode Input Voltage Range ss 12 Input Protection ccecesseseesessessseeneseeeseesseessseesseensseeeseeneseens 12 CONF SUrations EE EE REEE NEEESE 13 Applications Information eene 14 Driving a Single Ended ADC sss 14 Differential Outputs eto bd eben 14 Increasing Input Impedance see 15 AC Coupling 2 sued epp EE EEREEUTE 15 Using the AD822. Page 3 of 16 AD8275 ABSOLUTE MAXIMUM RATINGS Table 3 Parameter Rating Supply Voltage 18V Output Short Circuit Current Voltage at IN IN Pins Voltage at REFx Vs Vs SENSE and OUT Pins Current into REFx IN IN SENSE and OUT Pins Storage Temperature Range Specified Temperature Range Thermal Resistance 0 4 Package Glass Transition Temperature Tg ESD Human Body Model See derating curve Figure 3 Vs 40V Vs 40V Vs 0 5 V Vs 0 5 V 3mA 65 C to 130 C 40 C to 85 C 135 C W 140 C 2kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8275 package is limited by the associated rise in junction temperature Tj on the die The plastic encapsulating the die locally reaches the junction temperature At approximately 140 C which is the glass transition temperature the plastic changes its properties Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die permanently shifting the parametric perf
3. REFI connected to GND and REF2 connected to 5 V Ri 2 kQ connected to Vs 2 Ta 25 C unless otherwise noted S 3 U o G o p 9 I gt K U o u u s NORMALIZED AT 25 C REPRESENTATIVE SAMPLES s S 300 5 600 400 200 0 200 400 600 40 20 0 20 40 60 80 100 120 OFFSET VOLTAGE pV TEMPERATURE C Figure 5 Typical Distribution of System Offset Voltage Referred to Output Figure 8 Offset Voltage vs Temperature Normalized at 25 C Referred to Output 70 60 50 2 gt 3 40 xs p S I m tc 30 ui z lt o 20 10 2 LE S 60 40 20 0 20 40 60 45 30 15 0 15 30 45 60 75 90 105 120 CMRR V V TEMPERATURE C Figure 6 Typical Distribution of CMRR Referred to Output Figure 9 Gain Error vs Temperature Normalized at 25 C 60 40 T E 20 K gt 2 3 5 ac 9 o S ut 8 20 H 2 40 60 S 5 40 20 0 20 40 60 80 100 120 50 25 0 25 50 75 100 125 TEMPERATURE C TEMPERATURE C Figure 7 CMRR vs Temperature Normalized at 25 C Figure 10 Quiescent Current vs Temperature Rev A Pa
4. 90 100 dB Reference Divider Accuracy 0 024 0 024 Common Mode Rejection Veu 10 V referred to output 80 96 86 dB Ratio INPUT CHARACTERISTICS Input Voltage Range 12 3 12 12 3 12 V Impedance Differential Vem Vs 2 108 2 108 2 kQ pF Common Mode 27 5 2 27 5 2 kQ pF OUTPUT CHARACTERISTICS Output Swing Vrer2 4 096 V REF1 and Ri connected Vs Vs Vs 4 Vs V to GND Ri 2 kQ 0 048 0 1 0 048 0 1 Capacitive Load 100 100 pF Short Circuit Current Limit 30 30 mA POWER SUPPLY Specified Voltage Range 5 5 V Operating Voltage Range 3 3 15 3 3 15 V Supply Current lo 0 mA Vs 2 5 V reference and 1 9 2 3 1 9 2 3 mA input pins grounded Over Temperature lo 0 mA Vs 2 5 V reference and 2 1 2 7 2 1 2 7 mA input pins grounded 40 C to 85 C TEMPERATURE RANGE Specified Performance 40 85 40 85 C 1 Includes amplifier voltage and current noise as well as noise of internal resistors 2 Includes input bias and offset current errors 3 See Figure 7 for CMRR vs temperature 4 The input voltage range is a function of the voltage supplies reference voltage and ESD diodes When operating on other supply voltages see the Absolute Maximum Ratings section Figure 11 and Table 5 for more information 5 Internal resistors are trimmed to be ratio matched but have 20 absolute accuracy 6 See Figure 25 to Figure 28 in the Typical Performance Characteristics section for more information Rev A
5. to rail complementary transistor inputs The input range of the internal op amp is Vs 0 9 V to Vs 1 35 V 600 400 N e e OFFSET uV eo 200 400 07546 132 600 10 8 6 4 2 0 2 4 6 8 10 COMMON MODE VOLTAGE V Figure 32 AD8275 Does Not Have Crossover Distortion Typical of Rail to Rail Input Amplifiers AD8275 The AD8275 employs a balanced high gain linear output stage that adaptively generates current as required eliminating the dynamic errors found in other amplifiers This is useful when driving SAR ADCs which can deliver kickback current into the output of the amplifier The result is a design that achieves low distortion consistent bandwidth and high slew rate BASIC CONNECTION The basic configurations for the AD8275 are shown in Figure 33 and Figure 34 In Figure 33 REF1 and REF2 are tied together A voltage Vrer applied to the tied REF1 and REF2 pins sets the output voltage level to Vrer For example in Figure 33 if Vrer 2 V and the inputs are tied to ground the output remains at 2 V Vine Vinn Vour g VREF 07546 031 Figure 33 Basic Configuration 1 Shared Reference In contrast Figure 34 shows REFI tied to ground and REF2 tied to Varr In this example the two 20 kQ resistors serve as a resistor divider and Vw is divided by 2 For example if both inputs of the AD8275 are grounded and Vre 5 V the outpu
6. 75 as a Level Translator in a Data Acquisition SY SECT PAET eim ie ete redet tias 15 Outline DIMENSIONS eite ret teint tton 16 Ordering Guide Rar A eee EESE 16 Rev A Page 2 of 16 SPECIFICATIONS AD8275 Vs 5 V G 02 REFI connected to GND and REF2 connected to 5 V Ri 2 kQ connected to Vs 2 Ta 25 C unless otherwise noted Specifications referred to output unless otherwise noted Table 2 A Grade B Grade Parameter Test Conditions Comments Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE Small Signal Bandwidth 3 dB 10 15 10 15 MHz Slew Rate 4V step 20 25 20 25 V us Settling Time to 0 0196 4 V step on output C 100 pF 350 350 450 ns Settling Time to 0 00196 4 V step on output C 100 pF 450 450 550 ns Overload Recovery Time 5096 overdrive 300 300 ns NOISE DISTORTION THD N f 1 kHz Voy 4 V p p 22 kHz band 106 106 dB pass filter Voltage Noise f 0 1 Hz to 10 Hz referred to output 1 4 1 4 uV p p Spectral Noise Density f 1 kHz referred to output 40 40 nV VHz GAIN Vrer2 4 096 V REF1 and Ri connected 0 2 0 2 V V to GND Vin Vin 2 10 V to 10 V Gain Error 0 024 0 024 Gain Drift 40 C to 85 C 1 3 0 3 1 ppm C Gain Nonlinearity Vour 4 V p p Ri 600 O 2 KO 10 kQ 2 5 2 5 3 ppm OFFSET AND CMRR Offset Referred to output Vs 2 5 V 300 700 150 500 uV reference and input pins grounded vs Temperature 40 C to 85 C 2 5 2 5 7 uV C vs Power Supply Vs 3 3Vto5V
7. ANALOG DEVICES G 0 2 Level Translation 16 Bit ADC Driver AD8275 FEATURES Translates 10 V to 4V Drives 16 bit SAR ADCs Small MSOP package Input overvoltage 40 V to 35 V Vs 5 V Fast settling time 450 ns to 0 001 Rail to rail output Wide supply operation 3 3 V to 15 V High CMRR 80 dB Low gain drift 1 ppm C Low offset drift 2 5 pV C APPLICATIONS Level translator ADC driver Instrumentation amplifier building block Automated test equipment GENERAL DESCRIPTION The AD8275 isa G 0 2 difference amplifier that can be used to translate 10 V signals to a 4 V level It solves the problem typically encountered in industrial and instrumentation applic ations where 10 V signals must be interfaced to a single supply 4 V or 5 V ADC The AD8275 interfaces the two signal levels simplifying design The AD8275 has fast settling time of 450 ns and low distortion making it suitable for driving medium speed successive approx imation SAR ADCs Its wide input voltage range and rail to rail outputs make it an easy to use building block Single supply operation reduces the power consumption of the amplifier and helps to protect the ADC from overdrive conditions Internal matched precision laser trimmed resistors ensure low gain error low gain drift of 1 ppm C maximum and high common mode rejection of 80 dB Low offset and low offset drift combined with its fast settling time make the AD8275 suita
8. Cs such as the AD7685 yet still condition 10 V signals One important factor in selecting an ADC driver is its ability to settle within the acquisition window of the ADC The AD8275 is able to drive medium speed SAR ADCs In Figure 38 the 2 7 nF capacitor serves to store and deliver necessary charge to the switched capacitor input of the ADC The 33 Q series resistor reduces the burden of the 2 7 nF load from the amplifier and isolates it from the kickback current injected from the switched capacitor input of the AD7685 The output impedance of the amplifier can affect the THD of the ADC In this case the combined impedance of the 33 Q resistor and the output impedance of the AD8275 provides extremely low THD of 112 dB Figure 39 shows the ac response of the AD8275 driving the AD7685 Vs 10kO 50kO AD7685 EF ADR444 1 ADR445 07546 034 Figure 38 Driving a Single Ended ADC 5V 0 1pF y 50kKQ 100 2 AD8275 REF1 Vs ra a ae 8 moe ADC FULL SCALE dB iy NATAL NTA a if Phim 07546 139 FREQUENCY kHz Figure 39 FFT of AD8275 Directly Driving the AD7685 Using the 5 V Reference of the Evaluation Board Input 20 V p p 1 kHz THD 112 dB The AD8275 can condition signals for higher resolution ADCs such as 18 bit SAR converters provided that a narrower bandwidth is sampled to limit noise DIFFERENTIAL OUTPU
9. ENCY Hz OUTPUT VOLTAGE V Figure 13 Common Mode Rejection vs Frequency Referred to Input Figure 16 Gain Nonlinearity R 600 Q 2 kO 10 kQ Rev A Page 7 of 16 AD8275 60 50 40 5V SOURCE m 30 E Ei apices 3 3V SOURCE 2i A ae 10 0n ul E E o ga E 10 neo 5 _20 ds o 5 E 30 3 3V SINK S E ira 40 2u 5V SINK oc 50 60 3 70 s 50 25 0 25 50 75 100 125 14 TEMPERATURE C OUTPUT CURRENT mA Figure 17 Short Circuit Current vs Temperature Vs 3 3 V 5 V Figure 20 Output Voltage Swing vs Output Current Vs 5 V 1k 8 S EZ ES JI A LES 9 lt 2 Q 100 ae Q 2 0 o be a B Fu lt 2u LE om d gt 5 10 5 100k 1 10 100 1k 10k 100k Rioap FREQUENCY Hz Figure 18 Output Voltage Swing vs Rioap Vs 5 V Figure 21 Voltage Noise Density vs Frequency Referred to Output s3 gt q 92 5 z gt gt I amp wo LI Ww ae 9 20 ul ul o EC lt at E EH gt 24 e of TIME 1s DIV OUTPUT CURRENT mA Figure 19 Output Voltage Swi
10. TS In certain applications it is necessary to create a differential signal For example high resolution ADCs often require a differential input In other cases transmission over a long distance can require differential signals for better immunity to interference Figure 40 shows how to configure the AD8275 to output a differential signal The AD8655 op amp is used in an inverting topology to create a differential voltage VREF sets the output midpoint Errors from the op amp are common to both outputs and are thus common mode Likewise errors from using mismatched resistors cause a common mode dc offset error Such errors are rejected in differential signal processing by differential input ADCs or by instrumentation amplifiers When using this circuit to drive a differential ADC Vrer can be set using a resistor divider from the ADC reference to make the output ratiometric with the ADC AD8655 0 1pF 43 5V 42 5V Un Vour 415v 07546 035 Figure 40 AD8275 Configured for Differential Output for Driving a Differential ADC Rev A Page 14 of 16 INCREASING INPUT IMPEDANCE In applications where a high input impedance is needed low input bias current op amps can be used to buffer the AD8275 In Figure 41 an AD8620 is used to provide high input imped ance Input bias current is limited to 10 pA INVERTING INPUT Vs 50kO 10kQ SENSE SS NON INVERTING INPUT 07546 036 Figure 41 Adding Op Am
11. age is expected to exceed the maximum ratings of the AD8275 use external transorbs Adding series resistors to the inputs of the AD8275 is not recommended because the internal resistor ratios are matched to provide optimal CMRR and gain accuracy Adding external series resistors to the input degrades the performance of the AD8275 All other pins are protected by ESD diodes that clamp 0 5 V beyond either supply rail For example the voltage range of the REF1 and REF2 pins on a 5 V supply is 0 5 V to 45 5 V Rev A Page 12 of 16 CONFIGURATIONS Figure 36 and Figure 37 along with Table 6 and Table 7 provide examples of the possible input and output ranges for various supplies and reference voltages 5V USEFUL Vout HI LINEAR Viy j SWING RANGE HI ins SWING VINN MID VREF LO 07546 136 Figure 36 Split Reference Table 6 Input and Output Relationships for Split Reference Configuration in Figure 36 Note that Table 6 and Table 7 list the typical voltage range of the AD8275 AD8275 these values do not reflect variation over process or temperature LINEAR Viy RANGE HI MID LO 5V Figure 37 Shared Reference USEFUL Voyt HI l 4SWING Ay SWING 07546 137 Table 7 Input and Output Relationships for Shared Reference Configuration in Figure 37 Linear Linear Vout for Differential Useful Vour Vout for Differential Useful Vour Vs Vaer Vin OV VinRange R
12. anges Vs Vaer Vin OV VinRange Ranges 5V 5V 2 5V High 12V High 4 95 V SV 5V 5V High 0 1V High 4 98V Mid 0V Swing 2 45 V Mid 0V Swing 4 94 V Low 12 3V 2455V Low 24 7V Low 0 06 V Low 0 045 V 5V 4 096V 4 096V High 44V High 4 98 V 5V 25V 1 25V High 18 3V High 4 95 V Mid 0V Swing 0 884 V Mid 0V Swing 43 7 V Low 20 2V to 4 03V Low 6 V 1 205V Low 0 06 V Low 0 045 V SV 3V 3V High 9 5V High 4 95 V 5V 4 096V 2048V High 14 3V High 4 95 V Mid 0V Swing 1 9 V Mid 0 V Swing 2 902 V Low 148V 2 955V Low 10V 2 003 V Low 0 045 V Low 0 045 V 5V 25V 2 5V High 12V High 4 95 V 33V 33V 1 65 V High 8V High 3 24 V Mid 0V Swing 2 45 V Mid 0V Swing 1 59 V Low 12 3V 2455V Low 8V 1 605 V Low 0 045 V Low 0 045 V SV 2 048V 2 048V High 14 3V High 4 95 V 33V 25V 1 25V High 10V High 3 24V Mid 0V Swing 2 902 V Mid 0V Swing 1 99 V Low 10V 2 003 V Low 6 V 1 205V Low 0 045 V Low 0 045 V 5V 125V 125V 18 3V to High 4 95 V 6V Swing 3 7 V Vs 0V 1 205 V Low 0 045 V ov lov 0v 245Vto0 2V High 4 95 V Swing 4 95 V Low 0 045 V 1 Vsz0V Rev A Page 13 of 16 AD8275 APPLICATIONS INFORMATION DRIVING A SINGLE ENDED ADC The AD8275 provides the common mode rejection that SAR ADCs often lack In addition it enables designers to use cost effective precision 16 bit AD
13. ble for a variety of data acquisition applications where accurate and quick capture is required Rev A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners PIN CONFIGURATION REF1 Y e s REF2 TOP VIEW IN 5 Not to Scale OUT Vs 4 5 SENSE 07546 001 Figure 1 TYPICAL APPLICATION 5V 4 048V 2 048V Ny 0 048V Vs 10kQ 10V 50kQ 07546 002 Figure 2 Translating 10 V to 4 096 V ADC Full Scale The AD8275 can be used as an analog front end or it can follow buffers to level translate high voltages to a voltage range accepted by the ADC In addition the AD8275 can be configured for diff erential outputs if used with a differential ADC The AD8275 is available in a space saving 8 lead MSOP and is specified for performance over the 40 C to 85 C temperature range Table 1 Difference Amplifiers by Category Single Supply Low Distortion High Voltage Current Sense AD8270 AD628 AD8202 AD8273 AD629 AD8203 AD8274 AD8205 AD8275 AD8206 AMP03 AD8216
14. e AD8228 and the AD8253 have very low gain drift because all gain setting resistors are internal and laser trimmed AD8275 4 07546 143 Figure 43 Level Translation in a Data Acquisition System Rev A Page 15 of 16 AD8275 OUTLINE DIMENSIONS 0 95 15 MAX 0 85 1 10 MAX LAS am Db yf f A 015 T 0 80 m 0 40 e 4 1 0 23 055 0 05 cb 025 05 0 09 0 40 COPLANARITY 10 07 2009 B COMPLIANT TO JEDEC STANDARDS MO 187 AA Figure 44 8 Lead Mini Small Outline Package MSOP RM 8 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8275ARMZ 40 C to 85 C 8 Lead MSOP RM 8 Y13 AD8275ARMZ R7 40 C to 85 C 8 Lead MSOP 7 Tape and Reel RM 8 Y13 AD8275ARMZ RL 40 C to 85 C 8 Lead MSOP 13 Tape and Reel RM 8 Y13 AD8275BRMZ 40 C to 85 C 8 Lead MSOP RM 8 Y1V AD8275BRMZ R7 40 C to 85 C 8 Lead MSOP 7 Tape and Reel RM 8 Y1V AD8275BRMZ RL 40 C to 85 C 8 Lead MSOP 13 Tape and Reel RM 8 Y1V Z RoHS Compliant Part 2008 2010 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D07546 0 8 10 A ANALOG DEVICES Rev A Page 16 of 16 www analog com
15. ge 6 of 16 AD8275 35 120 30 E 25 Lo g G 20 X lt S 80 un s d 15 E gt ui 10 d 60 o 5 c Z gt 0 a 40 E a 20 o ui E 10 E 15 N a 0 20 A S i 25 S 20 5 05 0 05 1 0 15 20 25 3 0 35 40 45 5 0 5 5 100 1k 10k 100k 1M OUTPUT VOLTAGE V FREQUENCY Hz Figure 11 Input Common Mode Voltage vs Output Voltage No Load Figure 14 Power Supply Rejection vs Frequency Referred to Output 0 6 5 amp 5 gt 10 ul a _ 715 a a o kJ gt z 20 5 3 2 E 25 o 2 2a 30 z 2 35 x lt 40 0 5 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M FREQUENCY Hz FREQUENCY Hz Figure 12 Gain vs Frequency Figure 15 Maximum Output Voltage vs Frequency 100 20 15 g 9 z E 10 o 2 p 80 E 5 il E uj 70 Bo a a o z S 5 S z 3 10 o O 50 E Ed 5 Z 40 5 20 5 100 1k 10k 100k 1M 10M 0 1 2 3 4 FREQU
16. igure 29 Large Signal Pulse Response and Settling Time Ri 2 kQ 2us DIV 07546 027 THD N 1 0 0 1 eo e A 0 001 0 0001 Rev A Page 10 of 16 Vout 4V p p R 6000 R 2kQ R7 10kQ 10 100 1k 10k FREQUENCY Hz Figure 30 THD N vs Frequency Vour 4 V p p 07546 029 THEORY OF OPERATION The AD8275 level translates 10 V signals at its inputs to 4 V at its output It does this by attenuating the input signal by 5 A subtractor network performs the attenuation the level shifting and the differential to single ended conversion One benefit of the subtractor topology is that it can accept input signals beyond its supply voltage The subtractor is composed of tightly matched resistors By integrating the resistors and trimming the resistor ratios the AD8275 achieves 80 dB CMRR and 0 024 gain error 07546 030 Figure 31 AD8275 Simplified Schematic To achieve a wider input voltage range the AD8275 uses an internal 2 5 V voltage bias tied to Vs and two 7 KO resistors as shown in Figure 31 The resistors help to set the common mode of the internal amplifier The benefit of this circuit is that it extends the input range without causing crossover distortion typical of amplifiers that have rail
17. kQ AD8275 Ya Figure 35 REF1 and REF2 Pin Guidelines AD8275 s 07546 033 COMMON MODE INPUT VOLTAGE RANGE The common mode voltage range is a function of the input voltage range of the internal op amp the supply voltage and the reference voltage Equation 1 expresses the maximum positive common mode voltage range Vom pos 13 14 Vs 7 14 Vs 5 REF1 REF2 2 29 69 1 Equation 2 expresses the minimum common mode voltage range Vom_nec Z 6 Vs 5 REF1 REF2 2 0 11 2 The voltage range of the internal op amp varies depending on temperature The equations reflect a typical input voltage range of Vs 0 9 V and Vs 1 35 V over temperature Table 5 lists expected common mode ranges for typical configurations Table 5 Expected Common Mode Voltage Range for Typical Configurations Vs V Vaer V Vrer2 V Veut V Vem V 5 5 0 23 5 12 6 5 2 5 0 29 8 6 4 5 4 096 0 25 8 10 4 3 3 3 3 0 5 4 8 4 3 3 2 5 0 74 6 4 5 5 5 11 0 25 1 5 4 096 4 096 15 5 20 6 5 3 3 21 0 15 1 5 2 5 2 5 23 5 12 6 5 2 048 2 048 25 8 10 4 5 1 25 1 25 29 8 6 4 5 0 0 36 0 0 1 1 Vs 0V INPUT PROTECTION The inputs of the AD8275 IN and IN are protected by ESD diodes that clamp 40 V above Vs and 40 V below Vs When operating on a single 5 V supply the ESD diode conducts at input voltages less than 35 V and greater than 40 V If the input volt
18. ng vs Output Current Vs 3 3 V Figure 22 0 1 Hz to 10 Hz Voltage Noise Referred to Output Rev A Page 8 of 16 07546 119 AD8275 40 60 35 50 30 Z 25 3 ul o 2 o 0 S 30 tc 45 E o oO 20 e 10 10 5 amp a M S 0 s 0 5 40 20 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 160 TEMPERATURE C CAPACITANCE pF Figure 23 Slew Rate vs Temperature Figure 26 Small Signal Overshoot vs Capacitive Load No Resistive Load 60 C 47pF LOAD P ako NO LOAD 50 g gt LE a 6000 o s Q 30 E Dd 2 O 20 L gt 10kQ 10 o 0 o ius DIV 0 20 40 60 80 100 120 140 160 CAPACITANCE pF Figure 24 Small Signal Step Response for Various Resistive Loads Figure 27 Small Signal Overshoot vs Capacitive Load Step Responses Staggered for Clarity 600 Q in Parallel with Capacitive Load 60 NO RESISTIVE LOAD 50 g 40 gt LE a 9 3 3V gt I 30 E a amp amp 5V gt Q 20 10 5 0 S 1ps DIV 0 20 40 60 80 100 120 140 160 CAPACITANCE pF Figure 25 Small Signal Pulse Response for Various Capacitive Loads Figure 28 Small Signal Overshoot vs Capacitive Load Step Responses Staggered for Clarity 2 kQ in Parallel with Capacitive Load Rev A Page 9 of 16 AD8275 F10mV DIV F
19. ormance of the AD8275 Exceeding a junction temperature of 140 C for an extended period can result in changes in silicon devices potentially causing failure The still air thermal properties of the package and PCB Oya the ambient temperature Ta and the total power dissipated in the package Pp determine the junction temperature of the die The junction temperature is calculated as follows Ty Ta Pp x Oza The power dissipated in the package Pp is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs The quiescent power is the voltage between the supply pins Vs times the quiescent current Is Assuming the load Rz is referenced to midsupply the total drive power is Vs 2 x Iour some of which is dissipated in the package and some of which is dissipated in the load Vour x Tour The difference between the total drive power and the load power is the drive power dissipated in the package Pp Quiescent Power Total Drive Power Load Power V Vous P V xI U i ur OUT 2 m R In single supply operation with Ri referenced to V s the worst case is Vour Vs 2 Airflow increases heat dissipation effectively reducing Oya In addition more metal directly in contact with the package leads from metal traces through holes ground and power planes reduces 05 Figure 3 shows the maximum safe power dissipation in the package vs the ambien
20. p Buffers for High Input Impedance AC COUPLING An integrator can be tied to the AD8275 in feedback to create a high pass filter as shown in Figure 42 This circuit can be used to reject dc voltages and offsets At low frequencies the impedance of the capacitor C is high Thus the gain of the integrator is high DC voltage at the output of the AD8275 is inverted and gained by the integrator The inverted signal is injected back into the REFx pins nulling the output In contrast at high fre quencies the integrator has low gain because the impedance of C is low Voltage changes at high frequencies are inverted but at a low gain The signal is injected into the REFx pins but it is not enough to null the output High frequency signals are therefore allowed to pass When a signal exceeds foron nass the AD8275 outputs the conditioned input signal fHIGH PASS 345 RG Vout 07546 037 T 45V Figure 42 AC Coupled Level Translator AD8275 USING THE AD8275 AS A LEVEL TRANSLATOR IN A DATA ACQUISITION SYSTEM Signal size varies dramatically in some data acquisition applica tions Instrumentation amplifiers such as the AD8253 AD8228 or AD8221 are often used at the inputs to provide CMRR and high input impedance However the instrumentation amplifiers output 10 V signals and the ADC full scale is 5 V or 4 096 V In Figure 43 the AD8275 serves as a level translator between the in amp and the ADC The AD8275 along with th
21. t is 2 5 V 45V 7 50kKQ 100 VINN 07546 032 Vinp Vinn Vrer OV Vout 5 2 Figure 34 Basic Configuration 2 Split Reference Rev A Page 11 of 16 AD8275 POWER SUPPLIES Use a stable dc voltage to power the AD8275 Noise on the supply pins can adversely affect performance Place a bypass capacitor of 0 1 uF between each supply pin and ground as close to each pin as possible A tantalum capacitor of 10 uF should also be used between each supply and ground It can be farther away from the AD8275 and typically can be shared by other precision integrated circuits REFERENCE The reference terminals are used to provide a bias level for the output For example in a single supply 5 V operation the reference terminals can be set so that the output is biased at 2 5 V This ensures that the output can swing positive or negative around a 2 5 V level Figure 33 and Figure 34 illustrate two different ways to set the reference voltage See the Basic Connection section for the differences between the two settings The allowable reference voltage range is a function of the common mode input and supply voltages The REF1 and REF2 pins should not exceed either Vs or Vs by more than 0 5 V The REFx terminals should be driven by low source impedance because parasitic resistance in series with REF1 and REF2 can adversely affect CMRR and gain accuracy CORRECT INCORRECT Vs 50kQ VREF 50
22. t temperature on a 4 layer JEDEC standard board 2 00 1 75 1 50 1 25 MAXIMUM POWER DISSIPATION W S e 07546 003 40 20 0 20 40 60 80 100 AMBIENT TEMPERATURE C N Figure 3 Maximum Power Dissipation vs Ambient Temperature ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge A without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev A Page 4 of 16 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF1 7 e s REF2 anpa AD8275 F7 v TOP VIEW TN 3 Not to Scale 5 OUT Vg 4 5 SENSE 07546 001 Figure 4 Pin Configuration Table 4 Pin Function Descriptions AD8275 Pin No Mnemonic Description 1 REF1 Reference Pin Sets the output voltage level see the Reference section 2 IN Negative Input Pin 3 IN Positive Input Pin 4 Vs Negative Supply Pin 5 SENSE Sense Output Pin Tie this pin to the OUT pin 6 OUT Output Pin Force Output 7 TVs Positive Supply Pin 8 REF2 Reference Pin Sets the output voltage level see the Reference section Rev A Page 5 of 16 AD8275 TYPICAL PERFORMANCE CHARACTERISTICS Vs 5 V G 0 2
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ANALOG DEVICES AD8275 English products handbook Rev A