ANALOG DEVICES ADN2526 English products handbook Rev A
Contents
1. Vyss P VCCx ae Isc V pras X IBIAS where VCC is the power supply voltage Vmser is the voltage applied to the MSET pin Tsuppry is the sum of the currents that flow into VCC IMODP and IMODN which are sank by the ADN2526 when Veser Vuser 0 V expressed in amps see Table 1 Visas is the average voltage presented on the IBIAS pin IBIAS is the bias current sank by the ADN2526 Considering Vsser IBIAS 10 mV mA as the conversion factor from Vsser to IBIAS the dissipated power becomes Ve V P VCCx ee Bs Isc aa x V Bras To ensure long term reliable operation the junction tempera ture of the ADN2526 must not exceed 125 C as specified in Table 2 For improved heat dissipation the SFP module case can work as a heat sink as shown in Figure 32 A compact optical module is a complex thermal environment and calculations of device junction temperature using the package junction to ambient thermal resistance Oja do not yield accurate results THERMAL COMPOUND MODULE CASE THERMOCOUPLE PACKAGE PCB gt COPPER PLANE VIAS 07511 032 Figure 32 Typical Optical Module Structure The parameters in Table 6 can be used to estimate the IC junction temperature Table 6 Definitions Parameter Description Unit Trop Temperature at the top of the package C Trap Temperature at the package exposed paddle C T IC junction temperature2. C P Power dissipation WwW OTOP Thermal resistance from the IC junction to C W the package top OJ PaD Thermal resistance from the IC junction to C W the package exposed paddle Tror and Tran can be determined by measuring the temperature at points inside the module as shown in Figure 32 The thermo couples should be positioned to obtain an accurate measurement of the package top and paddle temperatures Using the model shown in Figure 33 the junction temperature can be calculated by Px Cae x 95 top T yop XO pap Tpap X0 J TOP T 9j_pap 9_ top where 0 rop and 6 rap are given in Table 2 P is the power dissipated by the ADN2526 Trop 8 top Trop 07511 033 Figure 33 Electrical Model for Thermal Calculations Rev A Page 13 of 16 APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT Figure 34 shows the typical application circuit for the ADN2526 The dc voltages applied to the BSET and MSET pins control the bias and modulation currents The bias current can be monitored as a voltage drop across the 1 KQ resistor connected between the IBMON pin and GND The ALS pin allows the user to turn on or turn off the bias and modulation currents depending on the logic level applied to the pin The data signal source must be connected to the DATAP and DATAN pins of the ADN2526 using 50 Q transmission lines The modulation current outputs IMODP and IMODN must be connected to the load TOSA using
3. Figure 8 Deterministic Jitter vs IMOD IMOD mA Figure 9 Total Supply Current vs IMOD o 3 4 5 Figure 10 Differential 67891 FREQUENCY GHz 0 1 1 12 13 14 15 S11 07511 036 07511 008 07511 009 DIFFERENTIAL S22 dB OCCURRENCE OCCURRENCE 012 3 4 5 6 7 8 9 10 14 12 13 14 15 FREQUENCY GHz Figure 11 Differential S22 23 24 25 26 27 28 29 30 RISE TIME ps Figure 12 Worst Case Rise Time Distribution VCC 3 07 V IBIAS 100 mA IMOD 80 mA Ta 85 C 25 26 27 28 29 30 FALL TIME ps 23 24 Figure 13 Worst Case Fall Time Distribution VCC 3 07 V IBIAS 100 mA IMOD 80 mA Ta 85 C 07511 035 07511 012 07511 013 Figure 15 Filtered SONET OC192 Optical Eye Diagram for Reference Rev A Page 9 of 16 Figure 14 Electrical Eye Diagram 11 3 Gbps PRBS31 IMOD 80 mA Acq Limit Test Waveforms 1000 Acq Limit Test yavetorns 1000 Figure 16 Filtered 10 Gb Ethernet Optical Eye 07511 014 07511 015 07511 016 THEORY OF OPERATION As shown in Figure 1 the ADN2526 consists of an input stage and two voltage controlled current sources for b
4. Rismon should be placed close to the ADC to minimize errors due to voltage drops on the ground plane The equivalent circuits of the BSET IBIAS and IBMON pins are shown in Figure 20 Figure 21 and Figure 22 VCC VCC BSET 8009 2000 07511 020 Figure 20 Equivalent Circuit of the BSET Pin Rev A Page 10 of 16 IBIAS VCC 1000 07511 021 Figure 21 Equivalent Circuit of the IBIAS Pin 1000 07511 022 IBMON Figure 22 Equivalent Circuit of the IBMON Pin The recommended configuration for BSET IBIAS and IBMON is shown in Figure 23 TO LASER CATHODE BSET IBMONC 07511 023 Figure 23 Recommended Configuration for the BSET IBIAS and IBMON Pins The circuit used to drive the BSET voltage must be able to drive the 1 KO input resistance of the BSET pin For proper operation of the bias current source the voltage at the IBIAS pin must be between the compliance voltage specifications for this pin over supply temperature and bias current range see Table 1 The maximum compliance voltage is specified for only two bias current levels 10 mA and 100 mA but it can be calculated for any bias current by Vcompuance_max V VCC V 0 75 4 4 x IBIAS 1 See the Applications Information section for examples of headroom calculations The function of the inductor L is to isolate the capacitance of the IBIAS output from the high frequency signal path For recommended components see Tabl
5. 50 Q differential 25 Q single ended transmission lines It is recommended that the components shown in Table 7 be used between the ADN2526 and the TOSA for an example ac coupling circuit For up to date component recommendations contact your local Analog Devices Inc sales representative Working with a TOSA laser sample the circuit in Figure 34 delivers optical performance shown in Figure 15 and Figure 16 For additional applications information and optical eye perfor mance of other laser samples contact your local Analog Devices sales representative Table 7 Recommended Components for AC Coupling LAYOUT GUIDELINES Due to the high frequencies at which the ADN2526 operates care should be taken when designing the PCB layout to obtain optimum performance Well controlled transmission line impedance must be used for the high speed signal paths The length of the transmission lines must be kept to a minimum to reduce losses and pattern dependent jitter The PCB layout must be symmetrical on both the DATAP and DATAN inputs and the IMODP and IMODN outputs to ensure a balance between the differential signals All VCC and VEE pins must be connected to solid copper planes by using low inductance connections When the connections are made through vias multiple vias should be used in parallel to reduce the parasitic inductance Each VEE pin must be locally decoupled with high quality capacitors If proper decoupling cannot be achieved usin
6. Supply 6 IMODN Al Modulation Current Sink Negative 7 IMODP Al Modulation Current Sink Positive 8 VCC P Positive Power Supply 9 VEE P Negative Power Supply Normally connected to system ground 10 IBIAS Al Bias Current Sink 11 IBMON AO Bias Current Monitoring Output 12 BSET Al Bias Current Control Input 13 VCC P Positive Power Supply 14 DATAP Al Data Signal Positive Input 15 DATAN Al Data Signal Negative Input 16 VCC P Positive Power Supply 17 EPAD Exposed Pad EPAD P The exposed pad on the bottom of the package must be connected to VCC or the GND plane 1 Al analog input DI digital input P power AO analog output Rev A Page 7 of 16 TYPICAL PERFORMANCE CHARACTERISTICS Ta 25 C VCC 3 3 V unless otherwise noted RISE TIME ps FALL TIME ps JITTER ps 27 0 26 5 26 0 25 5 25 0 24 5 24 0 23 5 23 0 27 0 26 5 0 7 0 3 0 2 0 1 o 20 40 60 IMOD mA Figure 5 Rise Time vs IMOD 20 40 60 IMOD mA Figure 6 Fall Time vs IMOD 100 100 o 20 40 60 IMOD mA Figure 7 Random Jitter vs IMOD 100 07511 005 07511 006 07511 007 TOTAL IVcc A JITTER ps DIFFERENTIAL S11 dB Rev A Page 8 of 16 0 35 0 30 0 25 0 20 0 15 0 10 20 40 60 IMOD mA 80 100
7. a TOSA resistance of 25 Q the typical value of K is equal to 120 mA V Assuming that IMOD 60 mA and using the preceding equation the MSET voltage is given by IMOD mA 60 V o 05V MSET 120 mA V 120 The MSET voltage range can be calculated using the required IMOD range and the minimum and maximum K values These can be obtained from the minimum and maximum curves in Figure 29 Rev A Page 15 of 16 OUTLINE DIMENSIONS 0 50 0 40 0 60 MAX 0 30 i PIN 1 BOTTOM ign INDICATOR 1 65 1 50 SQ PIN 1 4 1 35 INDICATOR 0 25 MIN 12 MAX 0 90 0 65 TYP FOR PROPER CONNECTION OF 0 85 THE EXPOSED PAD REFER TO j THE PIN CONFIGURATION AND 0 80 F 0 02 NOM FUNCTION DESCRIPTIONS SEATING A SECTION OF THIS DATA SHEET PLANE 0 20 REF COMPLIANT TO JEDEC STANDARDS MO 220 VEED 2 EXCEPT FOR EXPOSED PAD DIMENSION Figure 35 16 Lead Lead Frame Chip Scale Package LFCSP_VQ 3mm x 3 mm Body Very Thin Quad CP 16 3 Dimensions shown in millimeters 071708 A ORDERING GUIDE Model Temperature Range Package Description Package Option Branding ADN2526ACPZ 40 C to 85 C 16 Lead LFCSP_VQ CP 16 3 FOC ADN2526ACPZ R2 40 C to 85 C 16 Lead LFCSP_VQ 7 Tape amp Reel 250 Piece Reel CP 16 3 FOC ADN2526ACPZ R7 40 C to 85 C 16 Lead LFCSP_VQ 7 Tape amp Reel 1 500 Piece Reel CP 16 3 FOC Z RoHS Compliant Part 2009 Analog Devices Inc All rights reserved Trademarks a
8. count optical subassemblies The modulation and bias currents are programmable via the MSET and BSET control pins By driving these pins with control voltages the user has the flexibility to implement various average optical power and extinction ratio control schemes including closed loop or look up table control The automatic laser shutdown ALS feature allows the user to turn on off the bias and modulation currents by driving the ALS pin with a LVTTL logic source The product is available in a space saving 3 mm x 3 mm LFCSP specified from 40 C to 85 C FUNCTIONAL BLOCK DIAGRAM vcc CPA CROSS POINT ADJUST MSET VEE Rev A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners 07511 001 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2009 Analog Devices Inc All rights reserved TABLE OF CONTENTS USC 100 1 ot SO aS lea sO aS nO Ren naa OOS 1 Applications Ea 1 General Descriptions istsscssssscsssevedssevasevebivesscehig
9. ANALOG DEVICES FEATURES 3 3 V operation Up to 11 3 Gbps operation Typical 24 ps rise fall times Full back termination of output transmission lines Drives TOSAs with resistances ranging from 5 Q to 500 Bias current range 10 mA to 100 mA Differential modulation current range 10 mA to 80 mA Voltage input control for bias and modulation currents Data inputs sensitivity 150 mV p p diff Automatic laser shutdown ALS Cross point adjustment CPA XFP compliant bias current monitor SFP MSA compliant Optical evaluation board available Compact 3 mm x 3 mm LFCSP APPLICATIONS SONET OC 192 and SDH STM 64 optical transceivers 10 Gb Fibre Channel transceivers 10 Gb Ethernet optical transceivers SFP XFP X2 XENPAK XPAK MSA 300 optical modules 11 3 Gbps Active Back Termination Differential Laser Diode Driver ADN2526 GENERAL DESCRIPTION The ADN2526 laser diode driver is designed for direct modula tion of packaged laser diodes that have a differential resistance ranging from 5 Q to 50 Q The active back termination in the ADN2526 absorbs signal reflections from the TOSA end of the output transmission lines enabling excellent optical eye quality to be achieved even when the TOSA end of the output transmission lines is significantly misterminated ADN2526 is an SFP MSA compliant device and its small package and enhanced ESD protection provide the optimum solution for compact modules where laser diodes are packaged in low pin
10. ds to signal reflections back to the driver The excellent back termination in the ADN2526 absorbs these reflections preventing their reflection back to the load This enables excellent optical eye quality to be achieved even when the load end of the transmission lines is significantly mistermi nated The connection between the load and the ADN2526 must be made with 50 Q differential 25 Q single ended transmission lines so that the driver end of the transmission lines is properly terminated Rev A Page 12 of 16 CROSSPOINT ADJUSTMENT The optical eye cross point is adjustable between 35 and 65 using the cross point adjust CPA control input The equivalent circuit for the CPA pin is shown in Figure 31 In a default CPA setting leave CPA unconnected maintain pin to pin compatibil ity with the ADN2525 The internal bias circuit presents about 1 9 V at the CPA pin and the eye cross point is set to 50 To set the cross point at various points apply an external voltage to the CPA pin 07511 031 CPA Figure 31 Equivalent Circuit for CPA Pin POWER SEQUENCE To ensure reliable operation the recommended power up sequence is the supply rail to ADN2526 first then the BSET pin followed by the MSET pin and finally the CPA pin To turn off the ADN2526 the operation is reversed shut down CPA first then MSET followed by BSET and last the supply rail POWER CONSUMPTION The power dissipated by the ADN2526 is given by
11. e see the example in the Applications Information section The circuit used to drive the MSET voltage must be able to drive the 1 KQ resistance of the MSET pin To be able to drive 80 mA modulation currents through the differential load the output stage of the ADN2526 the IMODP and IMODN pins must be ac coupled to the load The voltages at these pins have a dc component equal to VCC and an ac component with single ended peak to peak amplitude of IMOD x 25 Q This is the case even if the load impedance is less than 50 Q differential because the transmission line characteristic impedance sets the peak to peak amplitude For proper operation of the output stage the voltages at the IMODP and IMODN pins must be between the compliance voltage specifications for these pins over supply temperature and modulation current range as shown in Figure 30 See the Applications Information section for examples of headroom calculations IMODP IMODN VCC 1 1V NORMAL OPERATION REGION VCC vcc 1 1V 07511 030 Figure 30 Allowable Range for the Voltage at IMODP and IMODN LOAD MISTERMINATION Due to its excellent S22 performance the ADN2526 can drive differential loads that range from 5 Q to 50 Q In practice many TOSAs have differential resistance less than 50 Q In this case with 50 Q differential transmission lines connecting the ADN2526 to the load the load end of the transmission lines are misterminated This mistermination lea
12. e 7 AUTOMATIC LASER SHUTDOWN ALS The ALS pin is a digital input that enables disables both the bias and modulation currents depending on the logic state applied as shown in Table 5 Table 5 ALS Functions ALS Logic State IBIAS and IMOD High Disabled Low Enabled Floating Enabled The ALS pin is compatible with 3 3 V CMOS and LVTTL logic levels Its equivalent circuit is shown in Figure 24 vec vec 1000 40k 2kQ 07511 024 Figure 24 Equivalent Circuit of the ALS Pin MODULATION CURRENT The modulation current can be controlled by applying a dc voltage to the MSET pin This voltage is converted into a dc current by using a voltage to current converter using an operational amplifier and a bipolar transistor as shown in Figure 25 FROM INPUT STAGE ADN2526 07511 025 Figure 25 Generation of Modulation Current on the ADN2526 This dc current is switched by the data signal applied to the input stage DATAP and DATAN pins and amplified by the output stage to generate the differential modulation current at the IMODP and IMODN pins The output stage also generates the active back termination which provides proper transmission line termination Active back termination uses feedback around an active circuit to synthesize a broadband termination resistance This provides excellent transmission line termination while dissipating less power than a traditional resistor passive back termination A small
13. e those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge A without detection Although this product features patented or proprietary protection circuitry damage NANS may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev A Page 6 of 16 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4 Pin Function Descriptions 15 DATAN 14 DATAP 13 VCC oO 9 gt o 4 PIN 1 oa INDICATOR ADN2526 TOP VIEW Not to Scale nor oZa20 oaoaago gt oos 22 NOTES 1 THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE MUST BE CONNECTED TO VCC OR THE GND PLANE 07511 004 Figure 4 Pin Configuration Pin No Mnemonic 1 O Description 1 MSET Al Modulation Current Control Input 2 CPA Al Adjustable Cross Point Defaults to not connected NC mode floating 3 ALS DI Automatic Laser Shutdown 4 VEE P Negative Power Supply Normally connected to system ground 5 VCC P Positive Power
14. enstsbevessebsvenodebotevenesy 1 Functional Block Diagram ssssssssssssssssssssssssssssttssssssssnsssrteeessssssss 1 REVISION History serey entin p ERRE ER 2 Spe fications ireira E EE E EE 3 Thermal Specifications cessessssssesseesessesseesessessessesseesseeseeaes 4 Absolute Maximum Ratings cssessesesseseeseeseesteseeseenseneeseees 6 ESD Caution dtd cenit 6 Pin Configuration and Function Descriptions 7 Typical Performance Characteristics cssssessesssessesesseessesseens 8 Theory Of Operation s csscessearsecssssionnscsasenessosiecnasssbenessestnecsssthonssenoe 10 Input Stage ssiri srira deh teh n S cab E S S EEs Bias Current REVISION HISTORY 8 09 Rev 0 to Rev A Changes to 0 pan Maximum Value Table 2 sssssssseseesesseseersssee 4 Changes to Figure 5 and Figure 6 cscsssssssssssssessesssesesseesesseenes 8 1 09 Revision 0 Initial Version Automatic Laser Shutdown ALS c cccscsesesesesesesesesesesesees 11 Modulation Current insonne ienn nuana 11 Load Mistermination ssssssssssssssssssssssssssettesessssssssrstttesssssssnsereet 12 Crosspoint Adjustment csceesessessessesssessesseesessessesesseese 13 Power SEQUENCE sic2e2 nonnen R R ected ue dat tees es 13 Power Consumption cssessssessseeseseeseseeeseeseseeeseeeseensneeneseens 13 Applications Information sssssssssssssssssssssssssstsssssssssssrssreeeessressssssss 14 Typical Application Circuit ecssessesseesessesseesse
15. ermination Resistance 100 Q Differential BIAS CONTROL INPUT BSET BSET Voltage to IBIAS Gain 90 mA V BSET Input Resistance 1000 Q MODULATION CONTROL INPUT MSET MSET Voltage to IMOD Gain 50 78 100 mA V See Figure 29 MSET Input Resistance 1000 Q BIAS MONITOR IBMON IBMON to IBIAS Ratio 10 pA mA Accuracy of IBIAS to IBMON Ratio 5 0 5 0 10 mA lt IBIAS lt 20 mA Rismon 1 KQ 4 0 4 0 20 mA lt IBIAS lt 40 mA Remon 1 kQ 2 5 2 5 40 mA lt IBIAS lt 70 mA Remon 1 kQ 2 2 70 mA lt IBIAS lt 100 mA Remon 1 KQ AUTOMATIC LASER SHUTDOWN ALS Vin 2 0 V Vit 0 8 V li 30 30 uA lH 0 200 uA ALS Assert Time 2 us Rising edge of ALS to falling edge of IBIAS and IMOD below 10 of nominal see Figure 2 ALS Negate Time 10 us Falling edge of ALS to rise of IBIAS and IMOD above 90 of nominal see Figure 2 Rev A Page 3 of 16 Parameter Min Typ Max Unit Test Conditions Comments POWER SUPPLY Vcc 3 0 3 3 3 6 V Icc6 46 55 mA Veset Vmser OV IsuppLy 74 95 mA Veser VmseT O V Isupery Icc IMODP IMODN CPA 1 88 V In NC mode refer to Table 4 Cross Point 50 From an optical eye in NC mode 1 IMOD is the total modulation current sink capability for a differential driver IMOD Imovp Imoon the dynamic current sank by the IMODP and IMODN pins Refers to the voltage between the pin for which the compliance voltage is specified and VEE 3 The pattern used is a repetitive seque
16. g a single capacitor the user can use multiple capacitors in parallel for each VEE pin A 20 uF tantalum capacitor must be used as a general decoupling capacitor for the entire module For guidelines on the surface mount assembly of the ADN2526 see the Amkor Technology Application Notes for Surface Mount Assembly of Amkor s MicroLeadFrame MLF Packages Component Value Description R1 R2 360 0603 size resistor R3 R4 200 Q 0603 size resistor C3 C4 100 nF 0603 size capacitor Phycomp 223878615649 L2 L3 20 nH 0402 size inductor Murata LQW15AN20NJO L6 L7 0402 size ferrite Murata BLM15HG102SN1 L1 L4 L5 L8 10 uH 0603 size inductor Murata LQM21FN100M70L vcc BSETO L4 R1 L8 R4 L7 Zo 509 Zo 250 DATAP C DATAP c1 c4 v DATAN DATAN c2 c3 Y 3 L6 L4 R2 L5 R3 vcc VCC Figure 34 Typical Application Circuit Rev A Page 14 of 16 TOSA 07511 034 DESIGN EXAMPLE This design example covers e Headroom calculations for the IBIAS IMODP and IMODN pins e Calculation of the typical voltage required at the BSET and MSET pins to produce the desired bias and modulation currents This design example assumes that the resistance of the TOSA is 25 Q the forward voltage of the laser at low current is Vr 1 V IBIAS 40 mA IMOD 60 mA and VCC 3 3 V Headroom Calculations To ensure proper device operation the voltages on the IBIAS IMODP and IMODN pins must meet the compliance vo
17. ias and modula tion The bias current which is available at the IBIAS pin is controlled by the voltage applied at the BSET pin and can be monitored at the IBMON pin The differential modulation current which is available at the IMODP and IMODN pins is controlled by the voltage applied to the MSET pin The output stage implements the active back match circuitry for proper transmission line matching and power consumption reduction The ADN2526 can drive a load having differential resistance ranging from 5 Q to 50 The excellent back termination in the ADN2526 absorbs the signal reflections from the TOSA end enabling excellent optical eye quality even though the TOSA is significantly misterminated INPUT STAGE The input stage of the ADN2526 converts the data signal applied to the DATAP and DATAN pins to a level that ensures proper operation of the high speed switch The equivalent circuit of the input stage is shown in Figure 17 VCC 07511 017 Figure 17 Equivalent Circuit of the Input Stage The DATAP and DATAN pins are terminated internally with a 100 Q differential termination resistor This minimizes signal reflections at the input which can otherwise lead to degradation in the output eye diagram It is not recommended to drive the ADN2526 with single ended data signal sources The ADN2526 input stage must be ac coupled to the signal source to eliminate the need for matching between the common mode voltages of the data
18. ltage specifications in Table 1 Considering the typical application circuit shown in Figure 34 the voltage at the IBIAS pin can be written as Visas VCC Vr IBIAS x Rrosa Via where VCC is the supply voltage Vr is the forward voltage across the laser at low current Rrosa is the resistance of the TOSA Via is the dc voltage drop across L5 L6 L7 and L8 For proper operation the minimum voltage at the IBIAS pin should be greater than 0 6 V as specified by the minimum IBIAS compliance specification in Table 1 Assuming that the voltage drop across the 25 Q transmission lines is negligible and that Via 0 V Vr 1 V and IBIAS 40 mA Vras 3 3 1 0 04 x 25 1 3 V Visas 1 3 V gt 0 6 V which satisfies the requirement The maximum voltage at the IBIAS pin must be less than the maximum IBIAS compliance specification as described by Vcomrrance max VCC 0 75 4 4 x IBIAS 2 For this example Veompuiance_Max VCC 0 75 4 4 x 0 04 2 53 V Visias 1 3 V lt 2 53 V which satisfies the requirement To calculate the headroom at the modulation current pins IMODP and IMODN the voltage has a dc component equal to VCC due to the ac coupled configuration and a swing equal to IMOD x 25 For proper operation of the ADN2526 the voltage at each modulation output pin should be within the normal operation region shown in Figure 30 Vis is the dc voltage drop across L1 L2 L3 and L4 Ass
19. nce of eight 1s followed by eight Os at 11 3 Gbps 4 Measured using the high speed characterization circuit shown in Figure 3 5 The pattern used is K28 5 00111110101100000101 at a 11 3 Gbps rate 6 Only includes current in the VCC pins 7 Without laser diode loaded THERMAL SPECIFICATIONS Table 2 Parameter Min Typ Max Unit Conditions Comments O pap 2 6 5 8 10 7 C W Thermal resistance from junction to bottom of exposed pad Os top 65 72 2 79 4 C W Thermal resistance from junction to top of package IC Junction Temperature 125 C ALS ALS NEGATE TIME IBIAS AND IMOD 07511 002 ASSERT TIME Figure 2 ALS Timing Diagram Rev A Page 4 of 16 2 0 nal Yeno BIAS TEE PICOSECOND PULSE LABS MODEL 5542 219 ADAPTER PASTERNACK PE 9436 2 92mm FEMALE TO FEMALE ADAPTER VEE ATTENUATOR PASTERNACK PE 7046 2 92mm 20dB ATTENUATOR 22uF GND GND GND Figure 3 High Speed Characterization Circuit Rev A Page 5 of 16 07511 003 ABSOLUTE MAXIMUM RATINGS VEE connected to supply ground Table 3 Parameter Rating Supply Voltage VCC to VEE 0 3 V to 4 2V IMODP IMODN to VEE 1 1 V to 4 75 V DATAP DATAN to VEE VCC 1 8 V to VCC 0 4 V All Other Pins 0 3 V to VCC 0 3 V HBM ESD on IMODP IMODN 200 V HBM ESD on All Other Pins 1kV Junction Temperature 150 C Storage Temperature Range 65 C to 150 C Soldering Temperature 300 C Less Than 10 sec Stresses abov
20. nd ANALOG registered trademarks are the property of their respective owners D07511 0 8 09 A DEVICES www analo g com Rev A Page 16 of 16
21. portion of the modulation current flows in the virtual 50 Q active back termination resistor All of the preset IMOD modulation current the range specified in Table 1 flows into the external load The equivalent circuits for MSET IMODP and IMODN are shown in Figure 26 and Figure 27 The two 25 Q resistors in Figure 27 are not actual resistors They represent the active back termination resistance Rev A Page 11 of 16 MSET 8000 2000 07511 026 Figure 26 Equivalent Circuit of the MSET Pin vcc IMODN IMODP vec 250 250 07511 027 Figure 27 Equivalent IMODP and IMODN Pins As Seen From Laser Side The recommended configuration of the MSET IMODP and IMODN pins is shown in Figure 28 See Table 7 for the recommended components ADN2526 7511 028 vcc VCC Figure 28 Recommended Configuration for the MSET IMODP and IMODN Pins The ratio between the voltage applied to the MSET pin and the differential modulation current available at the IMODP and IMODN pins is a function of the load resistance value as shown in Figure 29 220 210 Imon VmseT mA V m o 07511 029 DIFFERENTIAL LOAD RESISTANCE Q Figure 29 MSET Voltage to Modulation Current Ratio vs Differential Load Resistance Using the resistance of the TOSA the user can calculate the voltage range that should be applied to the MSET pin to generate the required modulation current rang
22. signal source and the input stage of the driver see Figure 18 The ac coupling capacitors should have an impedance much less than 50 Q over the required frequency range Generally this is achieved using 10 nF to 100 nF capacitors In SFP MSA applications the DATAP and DATAN pins need to be connected to the SFP connector directly This connection requires enhanced ESD protection to support the SFP module hot plug in application ADN2526 07511 018 i DATA SIGNAL SOURCE ee eee eee 4 Figure 18 AC Coupling the Data Source to the ADN2526 Data Inputs BIAS CURRENT The bias current is generated internally using a voltage to current converter consisting of an internal operational amplifier and a transistor as shown in Figure 19 07511 019 Figure 19 Voltage to Current Converter Used to Generate IBIAS The voltage to current conversion factor is set at 100 mA V by the internal resistors and the bias current is monitored using a current mirror with a gain equal to 1 100 By connecting a 1 kQ resistor between IBMON and VEE the bias current can be moni tored as a voltage across the resistor A low temperature coefficient precision resistor must be used for the IBMON resistor Revon Any error in the value of Rismon that is due to tolerances or to drift in its value over temperature contributes to the overall error budget for the IBIAS monitor voltage If the IBMON voltage is connected to an ADC for analog to digital conversion
23. sseesesseenes 14 Layout Guidelines a 14 Design Examplensavira r n a a E a aes 15 Outline Dimensions rei a a E EENET 16 Ordering GUE se scs ass cssseseensevesnestisstosedestanndasa hnacdsesiossssvatess onste 16 Rev A Page 2 of 16 SPECIFICATIONS VCC VCC to VCCmax Ta 40 C to 85 C 50 Q differential load resistance unless otherwise noted Typical values are specified at Ta 25 C IMOD 40 mA unless otherwise noted Table 1 Parameter Min Typ Max Unit Test Conditions Comments BIAS CURRENT IBIAS Bias Current Range 10 100 mA Bias Current While ALS Asserted 300 pA ALS high Compliance Voltage 0 6 VCC V IBIAS 100 mA 0 6 VCC V IBIAS 10 mA MODULATION CURRENT IMODP IMODN Modulation Current Range 10 80 mA diff Rioap 5 Q to 50 Q differential Modulation Current While ALS Asserted 0 5 mA diff ALS high Rise Time 20 to 80 4 24 32 5 ps Fall Time 20 to 80 4 24 32 5 ps Random Jitter 4 0 4 0 9 ps rms Deterministic Jitter 7 2 12 ps p p Includes pulse width distortion Pulse Width Distortion 4 2 5 ps PWD Tuich Trow 2 Differential S22 10 dB 5 GHz lt f lt 10 GHz Zo 50 Q differential 14 dB f lt 5 GHz Zo 50 Q differential Compliance Voltage VCC 1 1 VCC 1 1 V DATA INPUTS DATAP DATAN Input Data Rate 11 3 Gbps NRZ Differential Input Swing 0 15 1 6 V p p diff Differential ac coupled Differential S11 16 8 dB f lt 10 GHz Zo 100 Q differential Input T
24. uming that Vis 0 V and IMOD 60 mA the minimum voltage at the modulation output pins is equal to VCC IMOD x 25 2 VCC 0 75 VCC 0 75 gt VCC 1 1 V which satisfies the requirement The maximum voltage at the modulation pins is equal to VCC IMOD x 25 2 VCC 0 75 VCC 0 75 lt VCC 1 1 V which satisfies the requirement Headroom calculations must be repeated for the minimum and maximum values of the required IBIAS and IMOD ranges to ensure proper device operation over all operating conditions BSET and MSET Pin Voltage Calculation To set the desired bias and modulation currents the BSET and MSET pins of the ADN2526 must be driven with the appropriate dc voltage The voltage range required at the BSET pin to generate the required IBIAS range can be calculated using the BSET voltage to IBIAS gain specified in Table 1 Assuming that IBIAS 40 mA and the typical IBIAS Voser ratio of 100 mA V the BSET voltage is given by IBIAS mA _ 40 Vecer 04V BSET 100mA V 100 The BSET voltage range can be calculated using the required IBIAS range and the minimum and maximum BSET voltage to IBIAS gain values specified in Table 1 The voltage required at the MSET pin to produce the desired modulation current can be calculated using IMOD Vuser kK where K is the MSET voltage to IMOD ratio The value of K depends on the actual resistance of the TOSA It can be read using the plot shown in Figure 29 For
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ANALOG DEVICES ADN2526 English products handbook Rev A