ICS ICS9248- 195 Frequency Generator Integrated Buffers for PENTIUM II/III K6 Manual
Contents
1. d cs integrated ICS9248 195 Circuit Systems Inc Frequency Generator amp Integrated Buffers for PENTIUM II III M amp K6 Recommended Application Key Specifications 440BX MX VIA PM PL PLE 133 style chip set with CPU Output Jitter 2 5V lt 300ps Coppermine or Tualatin processor for note book CPU Output Jitter 3 3V lt 250ps applications id PCI Output Jitter 3 3V lt 250ps e CPU Output Skew 9 2 5V 175ps Output Features P k 3V 17 4 CPUs 2 5V 3 3V CPU Output Skew 9 3 3V 175ps PCI Output Skew 9 3 3V 500ps including 1 free running CPUCLK F PCI Early to PCI Skew 3 3V typ 3ns e 9 SDRAM Q 3 3V SDRAM Output Skew 9 3 3V 500ps 7 PCI 3 3V including 1 free running PCICLK F 1 PCI Early 3 3V Pin Configuration 1 48MHz 9 3 3V fixed UEBER 1 24 48MHz 3 3V SPREAD REFO 2 VDDLCPU GNDREF 3 CPUCLK_F 2 REF 3 3V 14 318MHz x1 4 CPUCLKO X2 5 GNDLCPU Features VDDPC 6 CPUCLK1 e Upto 137MHz frequency support EP EEK 7 p e 97MHz to support high end AMD processor GNDPC 9 9 GNDSDR SEL24_48 PCICLK1 SDRAM_F Support power management CLK PCI stop and SELPCIE BWP CLK2 T SDRAMO Power down Mode from I C programming PCICLK3 eo SDRAM1 PCICLK4 q2. Lead Free Optional Package Type G TSSOP Revision Designator will not correlate with datasheet revision Device Type Prefix ICS Standard Device 0375D 02 02 04 16
3. 100 00 1 20 133 33 0 45 o0 o o 6667 0 90 o 0 1 100 00 0 90 o 1 0 90 00 0 70 ERB EREe 0 90 1 0 0 70 00 0 70 1 0 14 105 00 0 70 1 1 0 133 33 1 2096 0 70 0 EN EN NI EN EN EN EN Notes 1 Default at Power up will be for latched logic inputs to define frequency Bit 2 6 4 are default to 0011 2 PWD Power Up Default 0375D 02 02 04 ICS9248 195 Byte 1 Active Inactive Register 1 enable 0 disable d z z Description Reserved CPUCLK F En Dis Reserved Reserved SDRAM_F En Dis CPUCLK2 En Dis CPUCLK1 En Dis CPUCLKO En Dis Rl Rel Rel Re O O eye Description 1 PCICLK_F En Dis 1 PCICLK6 En Dis PCICLK4 En Dis PCICLK3 En Dis PCICLK2 En Dis PCICLK1 En Dis PCICLKO En Dis Description Reserved Reserved Reserved Reserved SDRAM7 En Dis SDRAM6 En Dis SDRAMS En Dis SDRAM4 En Dis Notes 1 Inactive means outputs are held LOW and are disabled from switching 2 Latched register values will be inverted from pin values Default latch condition is for all latched inputs to be floating pulled up via internal resistor at power up 0375D 02 02 04 ICS9248 195 Ics Byte 4 Active Inactive Register 1 enable 0 dis
4. Vopr 3 3 V 5 unless otherwise stated input High Voltage Viu 2 0 3 ImutLowVolage Vi sg 3 d O08 f V OS Gun Iotaaoe From Vpp 3 3 V to 1 target Freq Guaranteed by design not 100 tested in production Electrical Characteristics Input Supply Common Output Parameters Ta 0 70 C Supply Voltage Vpp 3 3 V 5 Vpop 2 5 V 5 unless otherwise stated C 0 pF Select 66 8 MHz 15 Operating Sonic wes Bso Samo ane ft is mA Ci 0 pF Select 133 MHz J Powerdown Current CL 0 pF Input address VDDorGND 10 mA Vr 15V Vn 1 25 V rg p 4m Guaranteed by design not 100 tested in production 0375D 02 02 04 ICS9248 195 Ics Electrical Characteristics CPU Ta 0 70 C Vpp 3 3V 5 CL 20 pF Output High Vollage Vora low 20mA_ 24 V Output Low Voltage Voz lo 12mA 1 1111 O04 V Output High Current log Von 20V 1 zjm Output Low Current oz Vo 08V 22 Jm PiseTme m Vou 0 4V Voce 24V fas 2 ns Fame a Wors 24V Va zoav ru 2 ns Skew window ta Wetsv 7 5 es Der Oyceioeyde ges Vreis 1 160 2 Guaranteed by design not 100 tested in production Electrical Characteristics CPU Ta 0 70 C Vool 2 5 V 5 C 20 pF Output High Vo
5. such a manner that guarantees the high pulse width is a full pulse CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks INTERNAL CPUCLK PCICLK CLK_STOP PCI_STOP High SDRAM CPUCLK CPUCLK _F SDRAM F Notes 1 All timing is referenced to the internal CPU clock 2 CLK_STOP is an asynchronous input and metastable conditions may exist This signal is synchronized to the CPU clocks inside the ICS9248 195 3 SDRAM F output is controlled by Buffer in signal not affected by the ICS9248 195 CLK_STOP signal SDRAM are controlled as shown 4 All other clocks continue to run undisturbed 0375D 02 02 04 13 ICS9248 195 Ics PCI STOP Z Timing Diagram PCI STOP4 is an asynchronous input to the ICS9248 195 It is used to turn off the PCICLK clocks for low power operation PCI STOP Z is synchronized by the ICS9248 195 internally The minimum that the PCICLK clocks are enabled PCI STOP5 high pulse is atleast 10 PCICLK clocks PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed PCICLK clock on latency cycles are only three rising PCICLK clocks off latency is one PCICLK clock CPUCLK Internal PCICLK F d Internal PCICLK F X d Free running CLK_STOP ME RN PCI STOP PCICLK Notes 1 All timing is referenced t
6. 4 318 MHz reference clock FS2 Frequency select pin Latched Input 1 Internal Pull up Resistor of 120K to 3 3V on indicated inputs 2 Bidirectional input output pins input logic levels are latched at internal power on reset Use 10Kohm resistor to program logic Hi to VDD or GND for logic low 0375D 02 02 04 ICS9248 195 Ics General Description The ICS9248 195 is the single chip clock solution for Notebook designs using the 440BX MX VIA PM PL PLE 133 style chip set with Coppermine or Tualatin processor for Note book applications It provides all necessary clock signals for such a system Spread spectrum may be enabled through 12C programming Spread spectrum typically reduces system EMI by 8dB to 10dB This simplifies EMI qualification without resorting to board design iterations or costly shielding The ICS9248 195 employs a proprietary closed loop design which tightly controls the percentage of spreading over process and temperature variations Serial Configuration Command Bitmap Byte0 Functionality and Frequency Select Register default 0 Description EH Center Spread Spectrum Modulation 1 1 Down Spread Spectrum Modulation FS3 FS2 FS1 FSO Center Down abv Spread Spread o o o f 6667 3333 0 35 _ 0 70 o 0 1 100 00 0 70 o 1 0 6667 1 20 Po 1 1 0 70 1 0 0 6667 0 45 1 0 1 100 00 0 45 1 1 0
7. CSclock will acknowledge Controller host sends a dummy byte count CSclock will acknowledge Controller host starts sending first byte Byte 0 through byte 5 CSclock will acknowledge each byte one at a time Controller host sends a Stop bit How to Write ICS Slave Receiver How to Read Controller host will send start bit Controller host sends the read address D3 2 CSclock will acknowledge e ICS clock will send the byte count Controller host acknowledges CS clock sends first byte Byte 0 through byte 5 Controller host will need to acknowledge each byte Controller host will send a stop bit SetBt 1 7 How to Read Address D2 Start Bit 5 0 LACK Address a Dummy Command Code DSH D ACK y O OAK Dummy Byte Cout Byte Count po ACK Po ACK Pp y Bye0 0 Byte ACK ACK Byte Byte D ACK ACK Bytie y Byte 2 ACK po ACK po Byte po Byte D ACK po ACK Po Bye4 S Byte4 po ACK P ADE Jp Bye5 y S Byte 5 ACK ACK Stop Bit StoppBit Notes 1 The ICS clock generator is a slave receiver Fo component It can read back the data stored in the latches for verification Read Back will support Intel PII PIII Block Read protocol The input is operating at 3 3V logic levels The data byte format is 8 bit
8. VDDSDR Spread spectrum for EMI control VDDPC e SDRAM2 Uses external 14 318MHz crystal SEND d ONDE e j PCICLK5 lt SDRAM4 FS pns for frequency select PCICLK6 PCICLK_E SDRAM5 VDDCOR VDDSDR PCI_STOP SDRAM6 Vtt_PWRGD PD SDRAM7 GND48 VDD48 SDATA 48MHz FSO SCLK 24 48MHZ FS1 Block Diagram 48 Pin SSOP and TSSOP aba MEME CE nternal Pull up Resistor of 120K to VDD PLL2 gt L 4gmMHz i I mp 24MHz I I X1 L 23 XTAL gt Functionality ee koii Bit4 CPUCLK PCICLK BUFFER IN l REF 0 1 0 0 0 0 66 67 33 33 0 0 0 1 100 00 33 33 CPUCLK F 0 0 1 0 66 67 33 33 I Ficus I 0 0 1 1 133 33 33 33 Spectrum CROCE 0 1 0 0 66 67 33 33 0 1 0 1 100 00 33 33 4j Mti ee C LATCH eror 743 SDRAM 0 11 0 1 1 0 100 00 33 33 sb 0 1 1 1 133 33 33 33 TER i 1 0 0 0 66 67 33 33 i CPU_STOP s PCICLK 0 4 1 0 0 1 100 00 33 33 i Control p 1 0 1 0 90 00 30 00 PCI STOP PCICLKF 1 0 1 1 133 33 33 33 l Logic I x i SDATA TL Jl Cong 1 1 0 0 70 00 35 00 oat ur Ene i 1 1 0 1 105 00 35 00 ee E 1 1 1 1 0 133 33 33 33 0375D 02 02 04 1 1 1 1 140 00 35 00 ICS9248 195 Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION VDDREF Ref XTAL power supply nominal 3 3V SPREAD Active High Spread Spectrum enable input Power up default is High spreading is on REFO 14 318 Mhz reference clock This REF output is t
9. able Description Reserved Reserved SEL24_48 Latched FSO Latched FS1 Latched FS2 Latched FS3 Reserved Description SDRAM3 En Dis SDRAM2 En Dis SDRAM 1 En Dis SDRAMO En Dis 48MHz En Dis 24MHz En Dis REFI En Dis REFO En Dis Notes 1 Inactive means outputs are held LOW and are disabled from switching 2 Latched register values will be inverted from pin values Default latch condition is for all latched inputs to be floating pulled up via internal resistor at power up 0375D 02 02 04 ICS9248 195 Absolute Maximum Ratings Supply Voltage 0 000 0 eee 5 5 V Logic Inputs lt casi fate eed daha oes GND 0 5Vto Vpp 0 5 V Ambient Operating Temperature 0 C to 70 C Case Temperature 000 115 C Storage Temperature 65 C to 150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect product reliability Electrical Characteristics Input Supply Common Output Parameters Ta 0 70 C Supply Voltage Vpp
10. bytes or w o The data transfer rate supported by this clock generator is 100K bits sec or less standard mode To simplify the clock generator IC interface the protocol is set to use only Block Writes from the controller The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred The Command code and Byte count shown above must be sent but the data is ignored for those two bytes The data is loaded until a Stop sequence is issued 6 At power on all registers are setto a default condition as shown 0375D 02 02 04 Ics ICS9248 195 Shared Pin Operation Input Output Pins The I O pins designated by input output serve as dual signal functions to the device During initial power up they act as input pins The logic level voltage that is present on these pins atthis time is read and stored into a 5 bit internal data latch At the end of Power On reset see AC characteristics for timing values the device changes the mode of operations for these pins to an output function In this mode the pins produce the specified buffered clocks to external loads To program load the internal configuration register for these pins a resistor is connected to either the VDD logic 1 power supply or the GND logic 0 voltage potential A 10 Kilohm 10K resistor is used to provide both the solid CMOS prog
11. he STRONGER buffer for ISA BUS loads PCI_STOP Halts PCICLK clocks at logic 0 level when input low In mobile mode MODE 0 3 9 16 33 40 44 GND Ground X1 Crystal input has internal load cap 36pF and feedback resistor from X2 X2 Crystal output nominally 14 318MHz VDDPCI Supply for PCICLK F and PCICLK nominal 3 3V CPU2 5 8 94 Indicates whether VDDLCPU is 2 5 or 3 3V High 2 5V CPU LOW 3 3V CPU Latched Input PCICLK F Free running PCI clock not affected by PCI_STOP for power management FS3 Frequency select pin Latched Input PCICLKO PCI clock output Synchronous to CPU clocks with 1 4ns skew CPU early SEL24 48it Selects either 24 or 48MHz when Low 48 MHz PCICLK1 PCI clock output Synchronous to CPU clocks with 1 4ns skew CPU early SELPCIE 62 PCI Early or normal PCI select latch input for pin 18 power up default is High early PCICLK PCICLK2 PCICLK clock output 17 18 12 PCICLK 5 3 PCI clock outputs Synchronous to CPU clocks with 1 4ns skew CPU early 15 BUFFER IN Input to Fanout Buffers for SDRAM outputs 18 PCICLK6 PCICLK_ E PCI clock output or early PCI clock output selectable by SELPCIE_6 19 VDDCOR Power pin for the PLL core 3 3V Vtt PWRGND This pin acts as a dual function input pin for Vtt PWRGD and PD signal When Vtt PWRGD goes high the frequency select
12. ltage Vows lon 12ma o 1 2 V Output Low Voltage Vors lu 12mA 1 1 1 1 04 V Output High Current logs Vous 17V 1 21 ma Output Low Current los Va 07V Jz Jm Vo 0 4 V Vou 2 0 V 140 18 ms Fat Time ws Von 20V Va c 04V uo x8 s Vr 1 25 V lt 133 MHz Dum d e 125 V gt 138 MHZ Skew window ta vr 1 25vV CTS 60 175 ps Uer Cycefocyde ipee vs 128v tas 290 Tis Guaranteed by design not 100 tested in production 0375D 02 02 04 EES ICS9248 195 Electrical Characteristics PCI Ta 0 70 C Vpp 3 3 V 5 C 30 pF Output High Votage Vom lon 18mA_ eaf fv Output Low Voltage Vos _la 94mA_ o04 V Output High Current los Von 20V _ dajm Vr 1 5V Titer Absolute as Vreis Cd 50 1Guaranteed by design not 100 tested in production i Von 2 4 V Vo 0 4 V txt Electrical Characteristics SDRAM Ta 0 70 C Vpp 3 3 V 5 C 30 pF Output High Voltage Vors low 28mA 1 1 1 1 24 Jv Output Low Voltage Vos__flan 19mA 04 VV Output High Current los Von 20V _ o Rise Time Ta Va 04V Voz 24V E FalTime Te Vou 24V Va 04V 1 Duty Cycle Vr 15V Propagation Time 7 Buffer In to output taa bee Guaranteed by de
13. o the Internal CPUCLK defined as inside the ICS9248 device 2 PCI STOP Z is an asynchronous input and metastable conditions may exist This signal is required to be synchronized inside the ICS9248 3 All other clocks continue to run undisturbed 4 CLK_STOP is shown in a high true state 0375D 02 02 04 14 ICS9248 195 In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS A1 020 040 008 016 b 020 034 00 0135 eS D SEEVARATIONS SEEVARIATIONS 4l a INDEX AREA 10 03 10 68 0 635 BASIC 0 025 BASIC oe SEE VARIATIONS o 8 0 Epoo Reference Doc JEDEC Publication 95 MO 118 10 0034 300 mil SSOP Package Ordering Information ICS9248yF 195LF T Example ICS XXXX y FLF T Designation for tape and reel packaging T Lead Free Optional Package Type F SSOP Revision Designator will not correlate with datasheet revision Device Type Prefix ICS Standard Device 0375D 02 02 04 15 ICS9248 195 In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS SEE VARIATIONS E 8 10 BASIC Reference Doc JEDEC Publication 95 MO 153 10 0039 240 mil 0 020 mil 6 10 mm Body 0 50 mm pitch TSSOP Ordering Information ICS9248yG 195LF T Example ICS XXXX y GLF T L Designation for tape and reel packaging
14. ramming voltage needed during the power up programming period and to provide an insignificant load on the output clock during the subsequent operating period Programming Header Via to Gnd Figure 1 shows a means of implementing this function when a switch or 2 pin header is used With no jumper is installed the pin will be pulled high With the jumper in place the pin will be pulled low If programmability is not necessary than only a single resistor is necessary The programming resistors should be located close to the series termination resistor to minimize the current loop area Itis more importantto locate the series termination resistor close to the driver than the programming resistor Clock trace to load Series Term Res 0375D 02 02 04 Fig 1 11 ICS9248 195 Ics PD Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part PD is an asynchronous active low input This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer Internal clocks are not running after the device is put in power down When PD is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal The power up latency needs to be less than 4 mS The power down latency should be as short as possible but conforming to the sequence requi
15. rements shown below PCI STOP and CLK_STOP are considered to be don t cares during the power down operations The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible Due to the state of the internal logic stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete PD WW aM 9 7 CPUCLK ILIL a i tC LI LI LI uL PCICLK a a LT co ry 8 0 00 NUBE o VMAEEEENENENEENE NEN NNNSSSSSSSSSESNS Notes 1 All timing is referenced to the Internal CPUCLK defined as inside the ICS9248 device 2 As shown the outputs Stop Low on the next falling edge after PD goes low 3 PD is an asynchronous input and metastable conditions may exist This signal is synchronized inside this part 4 The shaded sections on the VCO and the Crystal signals indicate an active clock 5 Diagrams shown with respect to 133MHz Similar operation when CPU is 100MHz 0375D 02 02 04 ET 12 ICS9248 195 Ics CLK_STOP Timing Diagram CLK_STOP is an asychronous input to the clock synthesizer It is used to turn off the CPU clocks for low power operation CLK_STOP is synchronized by the ICS9248 195 The minimum that the CPU clock is enabled CLK_STOP high pulse is 100 CPU clocks All other clocks will continue to run while the CPU clocks are disabled The CPU clocks will always be stopped in a low state and start in
16. sign not 100 tested in production 0375D 02 02 04 ss ICS9248 195 Ics Electrical Characteristics 24 48MHz Ta 0 70 C Vpp 3 3 V 5 C 10 20 pF unless otherwise stated Output High Voltage Voms lon 14mA oea V Output Low Voltage Vos ln 6mA J m Titer Absolute touc w 15v Guaranteed by design not 100 tested in production Electrical Characteristics REF Ta 0 70 C Vpp 3 3 V 5 C 10 20 pF unless otherwise stated Output High Voltage Vows lou M4m 1 1 1 24 26 v Output Low Voltage Vos a 6mA JO02 04 VV Output High Current log Vou 20V 32 20 mA Output Low Current los Va 08V 1 16 22 m FaiTme t Vo24V Vas04v 2M 4 rs Titer cycle to cyce tas Vee 18V eoo se 1000 ps Guaranteed by design not 100 tested in production 0375D 02 02 04 ICS9248 195 General I C serial interface information The information in this section assumes familiarity with FG programming For more information contact ICS for an 1 C programming application note How to Write Controller host sends a start bit e Controller host sends the write address D2 p CSclock will acknowledge Controller host sends a dummy command code
17. will be latched at power on thereafter the pin is an asynchronous active low power down pin PD Asynchronous active low input pin used to power down the device into a low power state The internal clocks are disabled and the VCO and the crystal are stopped The latency of the power down will not be greater than 4ms 22 GND48 Ground pin for the 24 amp 48MHz output buffers amp fixed PLL core 28 29 31 32 34 35 37 38 SDRAM 7 0 SDRAM clock outputs Fanout Buffer outputs from BUFFER IN pin controlled by chipset 30 36 VDDSDR Supply for SDRAM and CPU PLL Core nominal 3 3V 23 SDATA Data input for IC serial input 5V tolerant input 24 SCLK Clock input of lC input 5V tolerant input 25 24 48MHz 24MHz or 48MHz output clock selectable by pin 10 FS1 Frequency select pin Latched Input 26 48MHz 48MHz output clock FSO Frequency select pin Latched Input 27 VDD48 Power for 24 amp 48MHz output buffers and fixed PLL core 39 SDRAM_F Free running SDRAM clock output Not affected by CPU_STOP 41 CLK_STOP This asynchronous input halts CPUCLK amp SDRAM at logic 0 level when driven low 42 43 45 CPUCLK 2 0 CPU clock outputs powered by VDDLCPU 46 CPUCLK_F Free running CPU clock Not affected by the CPU_STOP 47 VDDLCPU Supply for CPU clocks 2 5V 48 Notes REF1 1
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ICS ICS9248 195 Frequency Generator Integrated Buffers for PENTIUM II/III K6 Manual