ELPIDA 2G bits DDR2 SDRAM EDE2104ABSE (512M words × 4 bits) EDE2108ABSE (256M words × 8 bits)
Contents
1. TO T1 T2 T3 T4 15 T6 T7 T8 CK oci EO UM l7 77 74 l7 7 7 7 707 7M joe o j cl 1 D j M Y I j l y i i i CK i AE 1 ond WE 1 ANS L 1 i SENE 1 Command READ X NOP lt tDQSCK ZEE NN ii mM E M py E i i 1 r i i bas i T A T p cL 3 dnd ME RL 3 too M pape eene eser Burst Read Operation RL 3 BL 8 AL 0 and CL 3 ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 55 EDE2104ABSE EDE2108ABSE CK CK Command DOS DAS gen DQ a Burst Read Operation RL 5 BL 4 AL 2 CL 3 CK i l Posted Posted Command HEAD er no Y AAR NOP tRTW Read to Write 4 clocks DQS DQS S WL RL 1 4 t t Da ofr fo on l Burst Read Followed by Burst Write RL 5 WL RL 1 4 BL 4 The minimum time from the burst read command to the burst write command is defined by a read to write turn around time which is 4 clocks in the case of BL 4 operation 6 clocks in case of BL 8 operation Command DQS DQS DQ2. BH 68 0 45 0 05 6 40 15 4 S A B 14 4 OQOOOOQOOOOO OOO0O0O0O0OOO0O0Q0 ECA TS2 0234 01 ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 18 EDE2104ABSE EDE2108ABSE Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDE21XXABSE Type of Surface Mount Device EDE2104ABSE EDE2108ABSE 68 ball FBGA Lead free Sn Ag Cu gt ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 19 EDE2104ABSE EDE2108ABSE NOTES FOR CMOS DEVICES D PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when once it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity MOS devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap MOS devices must not be touched with bare hands Similar precautions need to
3. Read Followed by a Write to the Same Bank AL 0 and CL 3 RL AL CL 3 WL RL 1 2 ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 53 EDE2104ABSE EDE2108ABSE Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations write cycle or from memory locations read cycle The parameters that define how the burst mode will operate are burst sequence and burst length DDR2 SDRAM supports 4 bits burst and 8bits burst modes only For 8 bits burst mode full interleave address ordering is supported however sequential address ordering is nibble based for ease of implementation The burst type either sequential or interleaved is programmable and defined by the address bit 3 A3 of the MRS which is similar to the DDR I SDRAM operation Seamless burst read or write operations are supported Unlike DDR I devices interruption of a burst read or writes operation is limited to ready by Read or Write by Write at the boundary of Burst 4 Therefore the burst stop command is not supported on DDR2 SDRAM devices Burst Length and Sequence Burst length Starting address A2 A1 AO Sequential addressing decimal Interleave addressing decimal 000 0 1 2 3 0 1 2 3 Fi 001 1 2 3 0 1 0 3 2 010 2 3 0 1 2 3 0 1 011 3 0 1 2 3 2 1 0 000 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 001 1 2 3 0 5 6 7 4 1 0 3 2 5 4 7 6 010 2 3 0 1 6 7 4 5 2 3 0 1 6 7 4 5 011 3 0
4. s d 31 13 19 A 7 11 5 23 17 ps Vins 0 7 31 42 19 30 7 18 5 6 17 46 ps 06 43 59 31 47 19 35 7 5 11 ps 05 74 89 62 77 50 65 38 53 ps 04 4 55 s 3 SO 140 115 128 103 116 ps ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 23 EDE2104ABSE EDE2108ABSE Derating Values of tDS tDH with Differential DQS DDR2 667 800 DOS DQS differential slew rate 4 0 V ns 3 0 V ns 2 0 V ns 1 8 V ns 1 6 V ns 1 4 V ns 1 2 V ns 1 0 V ns 0 8 V ns AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH Unit 2 0 100 45 100 45 1100 145 ps 1 5 67 21 67 21 67 21 79 433 ps 100 0 12 412 24 24 ps DQ 09 5 14 5 14 7 2 19 10 131 422 ps 08 13 31 1 19 11 7 23 5 35 17 ps Vins 0 7 10 42 2 30 114 18 26 6 38 6 ps 06 10 2 47 414 35 26 23 138 11 ps 05 24 89 12 77 65 412 53 ps 4 v o c 523 1440 40 128 228 116 ps Derating Values of tDS1 tDH1 with Single Ended DQS DDR2 533 DOS DQS single ended slew rate 2 0
5. ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 56 EDE2104ABSE EDE2108ABSE Enabling a read command at every other clock supports the seamless burst read operation This operation is allowed regardless of same or different banks as long as the banks are activated Notes 1 LU E ur us Burst interrupt is only allowed at this timing Burst Read Interrupt by Read Read burst interrupt function is only allowed on burst of 8 burst interrupt of 4 is prohibited Read burst of 8 can only be interrupted by another read command Read burst interruption by write command or precharge command is prohibited Read burst interrupt must occur exactly two clocks after previous read command any other read burst interrupt timings are prohibited Read burst interruption is allowed to any bank inside DRAM Read burst with auto precharge enabled is not allowed to interrupt Read burst interruption is allowed by another read with auto precharge command All command timings are referenced to burst length set in the mode register They are not referenced to actual burst For example minimum read to precharge timing is AL BL 2 where BL is the burst length set in the mode register and not the actual burst which is shorter because of interrupt ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 57 EDE2104ABSE EDE2108ABSE Burst Write Command WRIT The Burst Write command is in
6. 450 0 45 0 45 Min tCL tCH 3750 3750 3750 5000 225 0 35 tAC min tHP tQHS 0 25 0 35 0 35 0 2 0 2 45 tRCD min max tAC max tAC max 300 Unit Notes tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ps ps 4 tCK tCK ns ns ELPIDA EDE2104ABSE EDE2108ABSE 5C Speed bin DDR2 533 4 4 4 Parameter Symbol min max Unit Notes Active bank A to active bank B command period tRRD 7 5 ns Four active window period tFAW 37 5 ns CAS to CAS command delay tCCD 2 tCK Write recovery time tWR 15 ns Auto precharge write recovery precharge time tDAL ns tCK 1 9 RU tRP tCK Internal write to read command delay tWTR 15 ns Internal read to precharge command delay tRTP 7 5 ns Exit self refresh to a non read command tXSNR tRFC 10 ns Exit self refresh to a read command tXSRD 200 tCK Exit precharge power down to any non read command 2 tCK Exit active power down to read command UXARD 2 tCK 3 A manos AL CKE minimum pulse width high and low pulse width tCKE 3 tCK Output impedance test driver delay tOIT 0 12 ns MRS command to ODT update delay tMOD 0 12 ns Auto refresh to active auto refresh command time tRFC 195 ns Average periodic refresh interval tREFI 78 jis 0 C lt TC lt 85 C 85 C lt TC lt 95 C tREFI 3 9 us iia Pu LE tDELAY tIS tCK tIH ns Notes 1 For each of the terms above i
7. eee VREF VIL DC max VIL AC max Se scat VSS VREF VIL AC max ATF AC Input Test Signal Wave forms Falling slew Measurement point VIH AC min VREF ATR Rising slew DQ O AN e VTT Preliminary Data Sheet E1196E10 Ver 1 0 20 RT 25 Q Output Load ELPIDA Clock Jitter DDR2 800 667 EDE2104ABSE EDE2108ABSE 8G 6E Frequency Mbps 800 667 Parameter Symbol min max min max Unit Notes Average clock period tCK avg 2500 8000 3000 8000 ps 1 Clock period jitter tJIT per 100 100 125 125 ps 5 Clock period jitter during tJIT DLL locking period per Ick i ps i Cycle to cycle period jitter tJIT cc 200 250 ps 6 Cycle to cycle clock period jitter during DLL locking period EIE ION dd m Ai Cumulative error across 2 cycles tERR 2per 150 150 175 175 5 7 Cumulative error across 3 cycles tERR 3per 175 175 225 225 ps 7 Cumulative error across 4 cycles tERR Aper 200 200 250 250 ps 7 Cumulative error across 5 cycles tERR 5per 200 200 250 250 ps 7 Cumulative error across tERR n 6 7 8 9 10 cycles 6 10per 00 M E aes d D Cumulative error across tERR n 11 12 49 50 cycles 11 50per 799 qun x Ten ps D Average high pulse width tCH avg 0 48 0 52 0 48 0 52 tCK avg 2 Average low pulse width tCL avg 0 48 0 52 0 48 0 52 tCK avg 3 Duty cycle jitter tJIT duty
8. EDE2104ABSE EDE2108ABSE CONTENTS PECE m ecde scour 1 FS cs saree alsa EA E E 1 Ordering 2 2 ipe Gre MIMO URI ONA a e aE E e 3 4 1 gf rs SDOSITCAODIS eee ee 5 Sies rro yz ius RR 29 PUM FE OU ON M E 30 command OPETAUON ese a i EE aaia 32 Simplified State IACI altus etoueseet sniadania enaa sinivseaicd asin atleunbreaied ri tid tenu uod Ei a pedcs inaia E 40 Operation ikari 41 ee 78 Recommended Soldering nnn nnn 79 ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 EDE2104ABSE EDE2108ABSE Electrical Specifications e All voltages are referenced to VSS GND e Execute power up and Initialization sequence before proper device operation is achieved Absolute Maximum Ratings Parameter Symbol Rating Unit Notes Power supply voltage VDD 1 0 to
9. MRS EMRS 1 2 DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS 1 2 Operation Note Nop gt Precharging after tWR Nop gt Precharging after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL 1 5 Enter idle after tRFC Nop gt Enter idle after tRFC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop gt Enter idle after tMRD Nop gt Enter idle after tMRD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ELPIDA EDE2104ABSE EDE2108ABSE Current state ICS RAS CAS WE Address Command Operation Note Extended Mode H x x x x DESL Nop gt Enter idle after tMRD register accessing L H H H x NOP Nop gt Enter idle after tMRD L H L H BA CA A10 READ READA ILLEGAL L H L L BA CA A10 AP WRIT WRITA ILLEGAL L L H H BA RA ACT ILLEGAL L L H L BA PRE ILLEGAL L L H L A10 AP PALL ILLEGAL L L L H x REF ILLEGAL L L L H x SELF ILLEGAL L L L L BA MRS OPCODE MRS ILLEGAL L L L L BA EMRS OPCODE EMRS 1 2 ILLEGAL Remark H VIH L VIL x VIH or VIL Notes 1 This command may be issued for other banks depending on the state of the banks 2 All banks must be in IDLE All AC timing specs must be met Only allowed at the boundary of 4 bits burst Burst interruptions at other timings are illegal Available in case tRCD is satisfied by AL se
10. Write recovery time tWR is defined by A9 to A11 Refer to the table for specific codes Address field 0j0 0 o jPD wR jDLL TM CASlatecy BT Burstlength Mode register 1 3 E 0 0 Nomai O Sequential oloo MS Write recovery for autoprecharge Lo o 1 EMRS 0 1 0 Emesa 0 1 1 EMRS Reserved I1 2 DDR2 400 DDR2 533 DDR2 667 DDR2 800 Active power down exit timing O0 Fast exit use tXARD timing Slow exit use tXARDS timing 3 6 o Reserved Notes 1 A13 and A14 are reserved for future use and must be programmed to 0 when setting the mode register 2 WR min Write Recovery for autoprecharge is determined by tCK max and WR max is determined by tCK min WR in clock cycles is calculated by dividing tWR in ns tCK in ns and rounding up to hte next integer WR cycles tWR ns tCK ns The mode register must be programmed to this value This is also used with tRP to determine tDAL Mode Register Set MRS ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 42 EDE2104ABSE EDE2108ABSE DDR2 SDRAM Extended Mode Registers Set EMRS EMRS 1 Programming The extended mode register 1 stores the data for enabling or disabling the DLL output driver strength additive latency ODT DQS disable OCD program RDQS enable The default value of the extended mode register 1 is not defined th
11. l l l l l l l l l l CKE can go to Jow one clock after an auto refresh command CKE Active Command to Power Down Entry Command ACT CKE can go to low one clock after an active command TT REN Precharge Precharge All Command to Power Down Entry Command CKE can go to low one clock afler a precharge or precharge all command CKE MRS EMRS Command to Power Down Entry Command EMRS i tMRD p p l l l ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 15 EDE2104ABSE EDE2108ABSE Asynchronous CKE Low Event DRAM requires CKE to be maintained high for all valid operations as defined in this data sheet If CKE asynchronously drops low during any valid operation DRAM is not guaranteed to preserve the contents of array If this event occurs memory controller must satisfy DRAM timing specification tDELAY before turning off the clocks Stable clocks must exist at the input of DRAM before CKE is raised high again DRAM must be fully re initialized steps 4 through 13 as described in initialization sequence DRAM is ready for normal operation after the initialization sequence See AC Characteristics table for tDELAY specific
12. tRC IDD 60 60 60 ns tRRD IDD 7 5 7 5 7 5 ns tFAW IDD 35 37 5 37 5 ns tCK IDD 2 5 3 3 75 ns tRAS min IDD 45 45 45 ns tRAS max IDD 70000 70000 70000 ns tRP IDD 15 15 15 ns tRFC IDD 195 195 195 ns IDD7 Timing Patterns for 8 Banks The detailed timings are shown in the IDD7 Timing Patterns for 8 Banks tables Speed bins Timing Patterns DDR2 533 AO RAO A1 RA1 A2 RA2 A3 3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 DD DDR2 667 AO RAO D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RAS D A6 RA6 D A7 RA7 DD DDR2 800 AO RAO D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RAS D A6 RAG D A7 RA7 DDD Remark A Active RA Read with auto precharge D Deselect Notes 1 All banks are being interleaved at minimum tRC IDD without violating tRRD IDD and tFAW IDD using a Burst length 4 2 Control and address bus inputs are STABLE during DESELECTs 3 IOUT OMA ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 10 DC Characteristics 2 TC 006 to 89506 VDD VDDQ 1 8V 0 1V Parameter Symbol Input leakage current 111 Output leakage current ILO Minimum required output pull up under AC VOH test load Maximum required output pull down under VOL AC test load Output timing measurement reference level VOTR Output minimum sink DC current IOL Output minimum source DC current EDE2104ABSE EDE2108ABSE Value 2 5 VTT 0 603 VTT 0 603 0 5 x VDDQ 13 4 13 4 Notes 1 The VDDQ of the device und
13. 100 100 125 125 ps 4 Notes 1 tCK avg is calculated as the average clock period across any consecutive 200cycle window tCK avg DE jy 54 N 200 tCH avg is defined as the average high pulse width as calculated across any consecutive 200 high pulses j l N 200 tCL avg is defined as the average low pulse width as calculated across any consecutive 200 low pulses tCH avg tCHj jw x tCK avg tCL avg tCLj x tCK avg N 200 tJIT duty is defined as the cumulative set of tCH jitter and tCL jitter tCH jitter is the largest deviation of any single tCH from tCH avg tCL jitter is the largest deviation of any single tCL from tCL avg tJIT duty is not subject to production test tJIT duty Min Max of tJIT CH tJIT CL where tJIT CH tCHj tCH avg where j 1 to 200 tJIT CL tCLj tCL avg where j 1 to 200 tJIT per is defined as the largest deviation of any single tCK from tCK avg tJIT per Min Max of tCK tCK avg where j 1 to 200 tJIT per defines the single period jitter when the DLL is already locked tJIT per Ick uses the same definition for single period jitter during the DLL locking period only tJIT per and tJIT per Ick are not subject to production test ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 21 EDE2104ABSE EDE2108ABSE 6 tJIT cc is defined as the absolute difference in clock period bet
14. AL 2 CL 3 tRTP lt 2tCK DQS DQS DQ Auto precharge begins Burst Read with Auto Precharge Followed by an Activation to the Same Bank RL 5 BL 8 AL 2 CL 3 tRTP lt 2tCK ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 67 EDE2104ABSE EDE2108ABSE Burst Write with Auto Precharge WRITA If A10 is high when a write command is issued the Write with auto precharge function is engaged The DDR2 SDRAM automatically begins precharge operation after the completion of the burst writes plus write recovery time tWR The bank undergoing auto precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied 1 The data in to bank activate delay time tWR tRP has been satisfied 2 The RAS cycle time tRC from the previous bank activation has been satisfied CK CK Command DQS DQS DQ Completion of the burst write Auto precharge begins Burst Write with Auto Precharge tRC Limit WL 2 tWR 2 CK CK A10 1 Posted Command Cum X l DOS 8 tWR min tRP min DQ Completion of the burst write Auto precharge begins Burst Write with Auto Precharge tWR tRP WL 4 tWR 2 tRP 3 ELPIDA Preliminary D
15. Immediately after the bank active command the DDR2 SDRAM can accept a read or write command on the following clock cycle If a RAW command is issued to a bank that has not satisfied the tRCD min specification then additive latency must be programmed into the device to delay when the RAW command is internally issued to the device The additive latency value must be chosen to assure tRCD min is satisfied Additive latencies of O 1 2 3 and 4 are supported Once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank The bank active and precharge times are defined as tRAS and tRP respectively The minimum time interval between successive bank activate commands to the same bank is determined by the RAS cycle time of the device tRC which is equal to tRAS tRP The minimum time interval between successive bank activate commands to the different bank is determined by tRRD In order to ensure that 8 bank devices do not exceed the instantaneous current supplying capability of 4 bank devices a restriction on the number of sequential ACT commands that can be issued must be observed The rule is as follows Note 8 bank device sequential bank activation restriction No more than 4 banks may be activated in a rolling tFAW window Converting to clocks is done by dividing tFAW ns by tCK ns and rounding up to next integer value As an example of the rolling window if tFAW tCK rounds up
16. The following tables show the operations that are performed when each command is issued in each state of the DDR SDRAM Current state ICS RAS CAS WE Address Command Operation Notes Idle H x x DESL Nop L H H H x NOP Nop L H L H BA CA A10 READ READA ILLEGAL 1 L H L L BA CA A10 AP WRIT WRITA ILLEGAL 1 L L H H BA RA ACT Row activating L L H L BA PRE Nop L L H L A10 AP PALL Nop L L L H x REF Auto refresh 2 L L L H x SELF Self refresh 2 L L L L BA MRS OPCODE MRS Mode register accessing 2 L L L L BA EMRS OPCODE EMRS 1 2 Extended mode register accessing 2 Bank s active H x x x x DESL Nop L H H H x NOP Nop L H L H BA CA A10 AP READ READA Begin Read L H L L BA CA A10 AP WRIT WRITA Begin Write L L H H BA RA ACT ILLEGAL 1 L L H L BA PRE Precharge L L H L A10 AP PALL Precharge all banks L L L H x REF ILLEGAL L L L H x SELF ILLEGAL L L L L BA MRS OPCODE MRS ILLEGAL L L L L BA EMRS OPCODE EMRS 1 2 ILLEGAL Bead H T 2 DESL Continue burst to end gt Row active L H H H NOP Me burst to end Row L H L H BA CA A10 AP READ READA Burst interrupt 1 4 L H L L BA CA A10 AP WRIT WRITA ILLEGAL 1 L L H H BA RA ACT ILLEGAL 1 L L H L BA PRE ILLEGAL 1 8 L L H L A10 AP PALL ILLEGAL 8 L L L H x REF ILLEGAL L L L H x SELF ILLEGAL L L L L BA MRS OPCODE MRS ILLEGAL L L L L BA EMRS OPCODE EMRS 1 2 ILLEGAL ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 34 EDE2104ABSE EDE2108ABSE Curr
17. V ns 1 5 V ns 1 0V ns 0 9V ns 0 8V ns 0 7 V ns 0 6 V ns 0 5 V ns 0 4 V ns A A A A A A A A A A A A A A A A A A DS1 tDH1 1551 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 1551 tDH1 1581 tDH1 1551 tDH1 2 0 188 1188 167 146 1125 463 ps 1 5 146 167 125 125 83 42 81 443 ps 1 0 63 125 42 83 0 2 11 7 13 ps DQ 09 31 69 11 14 13 13 18 27 29 45 ps sew 0 8 25 31 27 30 32 44 43 62 60 86 ps Vins 0 7 45 53 50 67 61 85 78 109 108 152 ps 06 74 96 85 114 102 138 132 181 183 246 ps 05 128 156 145 180 175 223 226 288 ps 04 210 243 240 286 291 351 ps ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 24 EDE2104ABSE EDE2108ABSE Derating Values of tlS tlH DDR2 533 CK CK Differential Slew Rate 2 0 V ns 1 5 V ns 1 0 V ns AUS AtlH AUS AtlH AUS AtlH Unit Notes 4 0 187 94 217 124 247 154 ps 3 5 179 89 209 119 239 149 ps 3 0 167 83 197 113 227 143 ps 2 5 150 75 180 105 210 135 ps 2 0 125 45 155 75 185 105 ps 1 5 83 21 113 51 143 81 ps 1 0 0 0 30 30 60 60 ps 0 9 11 14 19 16 49 46 ps Command address 0 8 25 31 5 1 35 29 ps sl
18. a b Precharge all AL BL 2 Max RTP 2 2 tCK a b Write Precharge to same bank as write WL BL 2 tWR tCK b Precharge all WL BL 2 tWR tCK b Write w AP Precharge to same bank as write w AP WL BL 2 WR tCK b Precharge all WL BL 2 WR tCK b Precharge Precharge to same bank as precharge 1 tCK b Precharge all 1 tCK b Precharge all Precharge 1 tCK b Precharge all 1 tCK b a RTP cycles RU tRTP ns tCK ns where RU stands for round up tCK avg should be used in place of tCK for DDR2 667 800 b For a given bank the precharge period should be counted from the latest precharge command either one bank precharge or precharge all issued to that bank The precharge period is satisfied after tRP depending on the latest precharge command issued to that bank ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 39 EDE2104ABSE EDE2108ABSE Simplified State Diagram INITALIZATION OCD SEQUENCE CKE L CALIBRATION E PRE ee a oE E MRS ALL BANKS Bee AUTO PRECHARGED REFRESH C ACT E CKE L CKE L ACTIVE POWER DOWN BANK ACTIVE n WRIT Ses 45 ZN PRE PALL READA PRE PALL PRE PALL PRECHARGE Automatic sequence Command sequence Simplified State Diagram ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 40 EDE2104ABSE EDE2108ABSE Operation of DDR2 SDRAM Read and write accesses to the DDR2 SDRAM are burst oriented accesses start at a select
19. by OCD calibration mode exit before any other command being issued MRS should be set before entering OCD impedance adjustment and ODT On Die Termination should be carefully controlled depending on system environment 41 MRS should be set before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment EMRS OCD calibration mode exit EMRS Drive 0 DQ DQS low DQS high Start EMRS Drive 1 DQ DQS high DQS low Need calibration EMRS OCD calibration mode exit EMRS Enter Adjust Mode Need calibration EMRS OCD calibration mode exit EMRS Enter Adjust Mode BL 4 code input to all DQs Inc Dec or NOP EMRS OCD calibration mode exit BL 4 code input to all DQs Inc Dec or NOP EMRS OCD calibration mode exit EMRS OCD calibration mode exit End OCD Flow Chart ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 45 EDE2104ABSE EDE2108ABSE Extended Mode Register Set for OCD Impedance Adjustment OCD impedance adjustment can be done using the following EMRS mode In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is dependent on EMRS bit enabling RDQS operation In Drive 1 mode all DQ DQS and RDQS signals are driven high and all DQS signals are driven low In drive 0 mode all DQ DQS and RDQS signals are driven low and all DQS signals are driven high In adjust mode BL 4 of o
20. every clock edge occurring during the tXSNR period Read commands may be issued only after tXSRD 200 clocks is satisfied Self refresh mode can only be entered from the all banks idle state Must be a legal command as defined in the command truth table Valid commands for power down entry and exit are NOP and DESL only Valid commands for self refresh exit are NOP and DESL only Power down and self refresh can not be entered while read or write operations extended mode register set operations or precharge operations are in progress See section Power down and Self Refresh Command for a detailed list of restrictions Minimum CKE high time is 3 clocks minimum CKE low time is 3 clocks The state of ODT does not affect the states described in this table The ODT function is not available during self refresh See section ODT On Die Termination The power down does not perform any refresh operations The duration of power down mode is therefore limited by the refresh requirements outlined in section automatic refresh command CKE must be maintained high while the SDRAM is in OCD calibration mode x means don t care including floating around VREF in self refresh and power down However ODT must be driven high or low in power down if the ODT function is enabled bit A2 or A6 set to 1 in EMRS 1 ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 33 EDE2104ABSE EDE2108ABSE Function Truth Table
21. gt occurs here 200 clocks ODT FE PASSEN ee ee i tAOFD gt l lt l ODT is off during Minmum 2 clocks DLL RESET required before changing frequency Stable new clock before power down exit Burst Interruption Interruption of a burst read or write cycle is prohibited No Operation Command NOP The no operation command should be used in cases when the DDR2 SDRAM is in an idle or a wait state The purpose of the no operation command is to prevent the DDR2 SDRAM from registering any unwanted commands between operations A no operation command is registered when CS is low with RAS CAS and WE held high at the rising edge of the clock A no operation command will not terminate a previous operation that is still executing such as a burst read or write cycle Deselect Command DESL The deselect command performs the same function as a no operation command Deselect Command occurs when CS is brought high at the rising edge of the clock the RAS CAS and WE signals become don t cares ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 T EDE2104ABSE EDE2108ABSE Package Drawing 68 ball FBGA Solder ball Lead free Sn Ag Cu 10 2 0 1 LE 91621618 INDEX MARK 19 0 0 1 9 1 20 max QS A c 0 1 S 0 35 0 05
22. ir j ir ir i r j r jir r IL r Oe Oe O a E a O a a a S a IRAS CAS WE ri r r r r i ir ir icmimiimix x I X us rir r r r r r T c X E I X IL E CICE IIIS II oy x I X IL Address X x BA CA A10 AP BA CA A10 AP BA RA BA A10 AP x x BA MRS OPCODE BA EMRS OPCODE X X BA CA A10 AP BA CA A10 AP BA RA BA A10 AP x x BA MRS OPCODE BA EMRS OPCODE x BA CA A10 AP BA CA A10 AP BA RA BA A10 AP x x BA MRS OPCODE BA EMRS OPCODE 36 EDE2104ABSE EDE2108ABSE Command DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS 1 2 DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS 1 2 DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS 1 2 Operation Note Nop gt Enter idle after tRP Nop gt Enter idle after tRP ILLEGAL ILLEGAL ILLEGAL Nop gt Enter idle after tRP 1 8 Nop gt Enter idle after tRP 8 ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop gt Enter bank active after tRCD Nop gt Enter bank active after tRCD
23. min derated 900ps 293ps 1193ps and tLZ DQ max derated 450ps 272ps 722ps 11 When the device is operated with input clock jitter this parameter needs to be derated by the actual tJIT per of the input clock output deratings are relative to the SDRAM input clock For example if the measured jitter into a DDR2 667 SDRAM has tJIT per min 72 5 and tJIT per max 93ps then tRPRE min derated tRPRE min tJIT per min 0 9 x tCK avg 72ps 2178ps and tRPRE max derated tRPRE max tJIT per max 1 1 x tCK avg 93ps 2843ps 12 When the device is operated with input clock jitter this parameter needs to be derated by the actual tJIT duty of the input clock output deratings are relative to the SDRAM input clock For example if the measured jitter into a DDR2 667 SDRAM has tJlT duty min 72ps and tJIT duty max 93ps then tRPST min derated tRPST min tJlT duty min 0 4 x tCK avg 72ps 928ps and tRPST max derated tRPST max tJlT duty max 0 6 x tCK avg 93ps 1592ps 13 Refer to the Clock Jitter table ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 18 EDE2104ABSE EDE2108ABSE ODT AC Electrical Characteristics Parameter Symbol min max Unit Notes ODT turn on delay tAOND 2 2 tCK tAON tAC min tAC max 700 p 13 5C tAON tAC min tAC max 1000 ps 1 ODT turn on power down mode tAONPD tAC min 2000 2tCK tAC max 1000 ps ODT tu
24. of 0 52 the tAOF max should be derated by adding 0 02 x tCK avg to it Therefore we have tAOF min derated tAC min 0 5 Min 0 5 tCH avg min x tCK avg tAOF max derated tAC max 0 6 Max 0 5 tCH avg max 0 5 x tCK avg Or tAOF min derated Min tAC min tAC min 0 5 tCH avg min x tCK avg tAOF max derated 0 6 Max tAC max tAC max tCH avg max 0 5 x tCK avg where tCH avg min and tCH avg max are the minimum and maximum of tCH avg actually measured at the DRAM input balls ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 19 AC Input Test Conditions Parameter Symbol Input reference voltage VREF Input signal maximum peak to peak swing VSWING max Input signal minimum slew rate SLEW EDE2104ABSE EDE2108ABSE Value Unit Notes 0 5 x VDDQ V 1 1 0 V 1 1 0 V ns 2 9 Notes 1 Input waveform timing is referenced to the input signal crossing through the VIH IL AC level applied to the device under test 2 The input signal minimum slew rate is to be maintained over the range from VREF to VIH AC min for rising edges and the range from VREF to VIL AC max for falling edges as shown in the below figure 3 AC timings are referenced with input waveforms switching from VIL AC to VIH AC on the positive transitions and VIH AC to VIL AC on the negative transitions VDDQ VIH AC min Se ee ype ye es VIH DC min VSWING max
25. of the DDR2 SDRAM will be in the precharged idle state A delay between the auto refresh command REF and the next activate command or subsequent auto refresh command must be greater than or equal to the auto refresh cycle time tRFC To allow for improved efficiency in scheduling and switching between tasks some flexibility in the absolute refresh interval is provided A maximum of 8 refresh commands can be posted to any given DDR2 SDRAM meaning that the maximum absolute interval between any refresh command and the next Refresh command is 9 x tREFI CKE Automatic Refresh Command ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 70 EDE2104ABSE EDE2108ABSE Self Refresh Command SELF The DDR2 SDRAM device has a built in timer to accommodate self refresh operation The self refresh command is defined by having CS RAS CAS and CKE held low with WE high at the rising edge of the clock ODT must be turned off before issuing self refresh command by either driving ODT pin low or using EMRS command Once the command is registered CKE must be held low to keep the device in self refresh mode When the DDR2 SDRAM has entered self refresh mode all of the external signals except CKE are don t care The clock is internally disabled during self refresh operation to save power The user may change the external clock frequency or halt the external clock one clock after Self Refresh entry is registered howev
26. the command code IRAS ICAS IWE input pins RAS CAS and WE along with CS define the command being entered to A14 input pins Provided the row address for Active commands and the column address and Auto Precharge bit for Read Write commands to select one location out of the memory array in the respective bank The address inputs also provide the op code during mode register set commands Address Pins Table Address AO to A14 Part number Row address Column address Note EDE2104ABSE AXO to AX14 AYO to AY9 AY11 EDE2108ABSE AXO to AX14 AYO to AY9 A10 AP input pin A10 is sampled during a precharge command to determine whether the precharge applies to one bank A10 low or all banks A10 high If only one bank is to be precharged the bank is selected by BAO BA1 and BA2 BAO BA1 input pins BAO BA1 and BA2 define to which bank an active read write or precharge command is being applied BAO and BA1 also determine if the mode register or extended mode register is to be accessed during a MRS or EMRS 1 EMRS 2 cycle Bank Select Signal Table BAO BA1 BA2 Bank O L L L Bank 1 H L L Bank 2 L H L Bank 3 H H L Bank 4 L L H Bank 5 H L H Bank 6 L H H Bank 7 H H H Remark H VIH L VIL ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 30 EDE2104ABSE EDE2108ABSE CKE input pin CKE high activates and CKE low deactivates internal clock signals and device input buffers and output
27. to 10 clocks and an activate command is issued in clock N no more than three further activate commands may be issued in clock N 1 through Tn 1 2 Tn 3 CK Command Address tCCD Additive latency AL BankO Bank1 BankO Bank1 BankO Active Active Precharge Precharge Active Bank Activate Command Cycle tRCD 3 AL 2 tRP 3 tRRD 2 tCCD 2 ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 52 EDE2104ABSE EDE2108ABSE Read and Write Access Modes After a bank has been activated a read or write cycle can be executed This is accomplished by setting RAS high CS and CAS low at the clock s rising edge WE must also be defined at this time to determine whether the access cycle is a read operation WE high or a write operation WE low The DDR2 SDRAM provides a fast column access operation A single read or write command will initiate a serial read or write operation on successive clock cycles The boundary of the burst cycle is strictly restricted to specific segments of the page length For example the 64M bits x 4 I O x 8 banks chip has a page length of 2048 bits defined by CAO to CA9 CA11 The page length of 2048 is divided into 512 uniquely addressable boundary segments 4 bits each A 4 bits burst operation will occur entirely within one of the 512 groups beginning with the column address supplied to the device during the read or write command CAO to CA9 CA11 Th
28. using the product in aerospace aeronautics nuclear power combustion control transportation traffic safety equipment medical equipment for life support or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury Product usage Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory Inc including the maximum ratings operating supply voltage range heat radiation characteristics installation conditions and other related characteristics Elpida Memory Inc bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions Even within the guaranteed ranges and conditions consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail safes so that the equipment incorporating Elpida Memory Inc products does not cause bodily injury fire or other consequential damage due to the operation of the Elpida Memory Inc product Usage environment Usage in environments with special characteristics as listed below was not considered in the design Accordingly our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below Example 1 Usage in liquids including
29. 1 2 7 4 5 6 3 2 1 0 7 6 5 4 i 100 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 101 5 6 7 4 1 2 3 0 5 4 7 6 1 0 3 2 110 6 7 8 9 2 3 0 1 6 7 8 5 2 3 0 1 111 7 4 9 6 3 0 1 2 7 6 9 4 3 2 1 0 Note Page length is a function of I O organization and column addressing 64M bits x 4 organization CAO to CA9 CA11 Page Length 2048 bits 32M bits x 8 organization CAO to CA9 Page Length 1024 bits ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 54 EDE2104ABSE EDE2108ABSE Burst Read Command READ The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock The address inputs determine the starting column address for the burst The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency RL The data strobe output DQS is driven low 1 clock cycle before valid data DQ is driven onto the data bus The first bit of the burst is synchronized with the rising edge of the data strobe DQS Each subsequent data out appears on the DQ pin in phase with the DQS signal in a source synchronous manner The RL is equal to an additive latency AL plus CAS latency CL The CL is defined by the mode register set MRS similar to the existing SDR and DDR I SDRAMs The AL is defined by the extended mode register set EMRS
30. 1050ps 106ps 272ps 1428ps For tAOFD of DDR2 533 the 1 2 clock of tCK in the 2 5 x tCK assumes a tCH input clock high pulse width of 0 5 relative to tCK tAOF min and tAOF max should each be derated by the same amount as the actual amount of tCH offset present at the DRAM input with respect to 0 5 For example if an input clock has a worst case tCH of 0 45 the tAOF min should be derated by subtracting 0 05 x tCK from it whereas if an input clock has a worst case tCH of 0 55 the tAOF max should be derated by adding 0 05 x tCK to it Therefore we have tAOF min derated tAC min 0 5 Min 0 5 tCH min x tCK tAOF max derated tAC max 0 6 Max 0 5 tCH max 0 5 x tCK Or tAOF min derated Min tAC min tAC min 0 5 tCH min x tCK tAOF max derated 0 6 Max tAC max tAC max tCH max 0 5 x tCK where tCH min and tCH max are the minimum and maximum of tCH actually measured at the DRAM input balls For tAOFD of DDR2 667 800 the 1 2 clock of nCK in the 2 5 x nCK assumes a tCH avg average input clock high pulse width of 0 5 relative to tCK avg tAOF min and tAOF max should each be derated by the same amount as the actual amount of tCH avg offset present at the DRAM input with respect to 0 5 For example if an input clock has a worst case tCH avg of 0 48 the tAOF min should be derated by subtracting 0 02 x tCK avg from it whereas if an input clock has a worst case tCH avg
31. 2 3 V 1 Power supply voltage for output VDDQ 0 5 to 2 3 V 1 Input voltage VIN 0 5 to 2 3 V 1 Output voltage VOUT 0 5 to 42 3 V 1 Storage temperature Tstg 55 to 100 C 1 2 Power dissipation PD 1 0 W 1 Short circuit output current IOUT 50 mA 1 Notes 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage temperature is the case surface temperature on the center top side of the DRAM Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability Operating Temperature Condition Parameter Symbol Rating Unit Notes Operating case temperature TC 0 to 95 C 1 2 Notes 1 Operating temperature is the case surface temperature on the center top side of the DRAM 2 Supporting 0 C to 85 C with full AC and DC specifications Supporting 0 C to 85 C and being able to extend to 95 C with doubling auto refresh c
32. 8 Min tCL abs tCH abs 2500 3000 3750 5000 125 50 0 6 tAC min 2 x tAC min tHP tQHS 0 25 0 35 0 35 0 2 0 2 0 4 max tAC max tAC max tAC max 200 0 6 6E DDR2 667 5 5 5 min 15 15 60 450 400 0 48 0 48 Min tCL abs tCH abs 3000 3000 3750 5000 175 100 0 6 0 35 tAC min 2 x tAC min tHP tQHS 0 25 0 35 0 35 0 2 0 2 0 4 max tAC max tAC max tAC max 240 0 6 Unit ns ns Ns ps ps tCK avg tCK avg tCK avg tCK avg tCK avg tCK avg tCK avg nCK tCK avg Notes 10 10 10 10 ELPIDA EDE2104ABSE EDE2108ABSE 86 6E Speed bin DDR2 800 6 6 6 DDR2 667 5 5 5 Parameter Symbol min max min max Unit Notes l tCK Write preamble tWPRE 0 35 0 35 avg Address and control input hold time tlH base 250 275 ps Address and control input setup time tIS base 175 200 ps 4 Read preamble tRPRE 0 9 1 1 0 9 1 1 e 11 avg tCK Read postamble tRPST 0 4 0 6 0 4 0 6 12 avg Active to precharge command tRAS 45 70000 45 70000 ns Active to auto precharge delay tRAP tRCD min tRCD min ns Active bank A to active bank B IRRD 75 75 command period Four active window period tFAW 35 37 5 ns ICAS to CAS command delay tCCD 2 2 nCK Write recovery time tWR 15 15 ns Auto p
33. D AL tRCD IDD 1 X tCK IDD Operating current 8G TBD TBD tCK tCK IDD tRC tRC IDD tRRD tRRD IDD Bank interleaving IDD7 6E TBD TBD mA tFAW tFAW IDD tRCD 1 x tCK IDD 5C TBD TBD CKE is H CS is H between valid commands Address bus inputs are STABLE during DESELECTs Data pattern is same as IDD4W Notes 1 IDD specifications are tested after the device is properly initialized 2 Input slew rate is specified by AC Input Test Condition 3 IDD parameters are specified with ODT disabled 4 Data bus consists of DQ DM DQS DQS RDQS and RDQS IDD values must be met with all combinations of EMRS bits 10 and 11 5 Definitions for IDD L is defined as VIN lt VIL AC max H is defined as VIN VIH AC min STABLE is defined as inputs stable at an H or L level FLOATING is defined as inputs at VREF VDDQ 2 SWITCHING is defined as inputs changing between H and L every other clock cycle once per two clocks for address and control signals and inputs changing between H and L every other data transfer once per clock for DQ signals not including masks or strobes 6 Refer to AC Timing for IDD Test Conditions ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 EDE2104ABSE EDE2108ABSE AC Timing for IDD Test Conditions For purposes of IDD testing the following parameters are to be utilized DDR2 800 DDR2 667 DDR2 533 Parameter 6 6 6 5 5 5 4 4 4 Unit CL IDD 6 5 4 tCK tRCD IDD 15 15 15 ns
34. DE2108ABSE Single ended DQS VIH DC min DOS VIL AC max Differential DOS DQS CK CK tDS1 tDH1 tDS1 tDH1 DOS CK ICK gt lt gt tDS tDS tDH tIS tIH tIS tIH VDD VIH AC min VREF to AC region VIH DC min DC to VREF region l nominal slew rate VREF DC nominal slew rate DC to VREF VIL DC max eal VREF to AC VIL AC max _ region VSS gt lt ATFS ATRH ATRS ATFH Setup slew rate _ VREF DC VIL AC max Setup slew rate _ VIH AC min VREF DC Falling signal ATES Rising signal ATRS Hold slew rate _ VREF DC VIL DC max Hold slew rate _ VIH DC min VREF DC Rising signal 7 ATRH Falling signal ATEH Slew Rate Definition Nominal ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 2 EDE2104ABSE EDE2108ABSE Single ended DQS DDO Vi BG mn DQS VRE VIL DC max VIL AC max VSS Differential DOS DQS lt gt CK CK tDS1 tDH1 tDS1 tDH1 4 gt 4 tDS tDS tIS tIS VDD VIH AC min KN VREF to AC nominal region line nominal VIH DC min mE DC to VREF region tangent VREF DC line VIL DC max nominal VREF to AC lin region VIL AC max _ NS
35. DT OX tIS tMOD max gt tMOD min Rtt Old setting Updating New Setting Note tAOFD must be met before issuing EMRS command ODT must remain low for the entire duration of tMOD window ODT update Delay Timing ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 48 EDE2104ABSE EDE2108ABSE TO T1 T2 T3 T4 T5 T6 CK zi nucum mca mim mom l i S Poe nm CKE tAXPD lt 6tCK tIS ODT Internal tAON min I tAOF min ia l tAON max tAOF max ODT Timing for Active and Standby Mode TO T1 T2 T3 T4 T5 T6 CK Ta emm mmm mte aS Sq 4l 4 CK LO CKE ED tAXPD x 6tCK US dS ODT i IAOFPD max tAOFPD min a L Internal Term Res tAONPD min e ii IAONPD max ODT Timing for Power Down Mode ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 49 CKE ODT Internal ODT Internal Term Res ODT Internal Term Res ODT Internal Term Res o EE CM uum FOO EN EMEN Term Res EDE2104ABSE EDE2108ABS
36. E Active and standby mode timings to be applied Power down mode timings to be applied Active and standby mode timings to be applied Power down mode timings to be applied ODT Timing Mode Switch at Entering Power Down Mode Preliminary Data Sheet E1196E10 Ver 1 0 50 ELPIDA EDE2104ABSE EDE2108ABSE TO T1 ICK aa NES CK seen tIS CKE i EE Active and standby imal mode timings to be applied imsmel Term Res Power down ODT mode timings to be applied Internal Term Res Active and standby ODT mode timings to be applied Internal Term Res Power down Sel mode timings to be applied Internal Term Res tIS Rtt tIS T9 T10 AS QtAOFD gt Rtt y _ tAOFPD max US 5 4 tAOND Rit tAONPD max ODT Timing Mode Switch at Exiting Power Down Mode Preliminary Data Sheet E1196E10 Ver 1 0 51 ELPIDA EDE2104ABSE EDE2108ABSE Bank Activate Command ACT The bank activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock The bank addresses BAO BA1 and BA2 are used to select the desired bank The row address AO through A14 is used to determine which row to activate in the selected bank The Bank activate command must be applied before any read or write operation can be executed
37. ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop gt Enter bank active after tWR Nop gt Enter bank active after tWR ILLEGAL New write ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL 1 6 ELPIDA Current state Write recovering with auto precharge Refresh Mode register accessing Preliminary Data Sheet E1196E10 Ver 1 0 ICS OO I IL OO IRAS CAS WE X X r r r r r r ir iTmrimiiix FIII r i c mriirizi X X m ee od X T Imrir i r iirir irmiiazix r r IICA III Address x BA CA A10 AP BA CA A10 AP BA RA BA A10 AP x x BA MRS OPCODE BA EMRS OPCODE x x BA CA A10 AP BA CA A10 AP BA RA BA A10 AP x x BA MRS OPCODE BA EMRS OPCODE X x BA CA A10 AP BA CA A10 AP BA RA BA A10 AP x x BA MRS OPCODE BA EMRS OPCODE 37 EDE2104ABSE EDE2108ABSE Command DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS 1 2 DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF
38. L L BA CA L CA 1 2 3 Write with auto precharge WRITA H H L H L L BA CA H CA 1 2 3 Read READ H H L H L H BA CA L CA 1 2 3 Read with auto precharge READA H H L H L H BA CA H CA 1 2 8 No operation NOP H x L H H H x x x x x x 1 Device deselect DESL H x H x x x x x x x 1 Power down mode entry PDEN H L H x x x x x x x x x 1 4 H L L H H H x x x x x x Power down mode exit PDEX L H H x x x x x x x x x 1 4 L H L H H H x x x x x x Remark H VIH L VIL x VIH or VIL BA Bank Address RA Row Address CA Column Address Notes 1 All DDR2 commands are defined by states of CS RAS CAS WE and CKE at the rising edge of the clock Bank select BAO BA1 and 2 determine which bank is to be operated upon Burst reads or writes should not be terminated other than specified as Reads interrupted by a Read in burst read command READ or Writes interrupted by a Write in burst write command WRIT The power down mode does not perform any refresh operations The duration of power down is therefore limited by the refresh requirements of the device One clock delay is required for mode entry and exit The state of ODT does not affect the states described in this table The ODT function is not available during self refresh Self refresh exit is asynchronous 8 bank device sequential bank activation restriction No more than 4 banks may be activated in a rolling tFAW window Converting to clocks is done by dividing tFAW ns by tCK
39. PRELIMINARY DATA SHEET 2G bits DDR2 SDRAM EDE2104ABSE 512M words x 4 bits EDE2108ABSE 256M words x 8 bits ELPIDA Specifications e Density 2G bits e Organization 64M words x 4 bits x 8 banks EDE2104ABSE 32M words x 8 bits x 8 banks EDE2108ABSE e Package 68 ball FBGA Lead free ROHS compliant Power supply VDD VDDQ 1 8V 0 1V e Data rate 800Mbps 667Mbps 533Mbps max e 1KB page size Row address AO to A14 Column address AO to A11 EDE2104ABSE to A9 EDE2108ABSE e Eight internal banks for concurrent operation e nterface SSTL 18 e Burst lengths BL 4 8 e Burst type BT Sequential 4 8 Interleave 4 8 e CAS Latency CL 3 4 5 6 e Precharge auto precharge option for each burst access e Driver strength normal weak e Refresh auto refresh self refresh e Refresh cycles 8192 cycles 64ms Average refresh period 7 8us at 0 C lt TC lt 85 C 3 9us at 85 C lt TC lt 95 C e Operating case temperature range TC C to 95 C Document No E1196E10 Ver 1 0 Date Published November 2007 K Japan Printed in Japan URL http www elpida com Features e Double data rate architecture two data transfers per clock cycle e The high speed data transfer is realized by the 4 bits prefetch pipelined architecture e Bi directional differential data strobe DOS and DQS Is transmitted received with data for
40. S Dos A a a a gt DQ AL CL i OEE Tx 1 Tx 2 Tx 3 Tx 4 Tx 6 Tx 7 Tx 8 Tx 9 eS EM 1 S TN 1 k Dandu v Start internal precharge Command AL BL 2 v PPE with tRTP 7 5ns CKE should be kept high CKE 7 until the end of burst operation vena bo C GU C E EE Write to Power Down Entry T1 TxX 1 Tx 2 13 Tx 4 Tx 5 Tx 6 Tm 2 Tm 3 Tx TO Tm 1 CK CK Command CKE tWTR DQS DQS DQ BL 4 Tx 1 Tx 2 Tx 3 De4 Command CKE DQS DQS DQ BL 8 ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 13 EDE2104ABSE EDE2108ABSE Write with Auto Precharge to Power Down Entry Tx 1 Tx 2 Tx 3 Tx4 4 Tx 6 rr 5 r 4 CK CK Command CKE DQS DQS DQ CK CK Command ct wga 4 L LLL 1 PRE CKE DQS DQS DQ Note 1 WR is programmed through MRS ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 14 EDE2104ABSE EDE2108ABSE Refresh Command to Power Down Entry TO qi T2 T3 T4 T5 T6 TZ T8 T9 T10 T11 CK CK Command p n aaa
41. SDRAM When enabled ODT is only applied to each DQ DOS DQS RDQS RDQS and DM signal for x 4 x 8 configurations The ODT pin will be ignored if the Extended Mode Register EMRS is programmed to disable ODT Any time the EMRS enables the ODT function ODT may not be driven high until eight clocks after the EMRS has been enabled VDD VSS VDDQ VSSQ power supply VDD and VSS are power supply pins for internal circuits VDDQ and VSSQ are power supply pins for the output buffers VDDL and VSSDL power supply VDDL and VSSDL are power supply pins for DLL circuits VREF Power supply SSTL 18 reference voltage 0 50 0 01 x VDDQ ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 31 EDE2104ABSE EDE2108ABSE Command Operation Command Truth Table The DDR2 SDRAM recognizes the following commands specified by the CS RAS CAS and address pins CKE Previous Current Al4to Function Symbol cycle cycle CS RAS CAS WE BAO BA1 BA2 A11 A10 A9 Notes Mode register set MRS H H L L L L L L L MRS 1 EMRS 1 H H L L L L H L L mui x 1 B EMRS 2 H H L L L L L H L ais ie 1 Auto refresh REF H H L L L H x x x x x x 1 Self refresh entry SELF H L L L L x x x x x x 1 Self refresh exit SELFX L H H x x x x x x x x x 1 6 L H L H H H x x x x x x Single bank precharge PRE H H L L H L BA x x 1 2 Precharge all banks PALL H H L L H L x x x x H x 1 Bank activate ACT H H L L H H BA RA 1 2 7 Write WRIT H H L H
42. SWITCHING all banks open tCK tCK IDD CKE Is L Other control and address bus inputs are STABLE Slow PDN Exit Data bus inputs are MRS 12 1 FLOATING all banks open tCK tCK IDD tRAS tRAS max IDD tRP tRP IDD CKE is H CS is H between valid commands Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING all banks open continuous burst reads IOUT OMA BL 4 CL CL IDD AL 0 tCK tCK IDD tRAS tRAS max IDD tRP tRP IDD CKE is H CS is H between valid commands Address bus inputs are SWITCHING Data pattern is same as IDD4W all banks open continuous burst writes BL 4 CL CL IDD AL 0 tCK tCK IDD tRAS tRAS max IDD tRP tRP IDD CKE is H CS is H between valid commands Address bus inputs are SWITCHING Data bus inputs are SWITCHING Fast PDN Exit MRS 12 0 ELPIDA EDE2104ABSE EDE2108ABSE max Parameter Symbol Grade x4 x 8 Unit Test condition tCK tCK IDD 8G TBD TBD Refresh command at every tRFC IDD interval Auto refresh current IDD5 6E TBD TBD mA CKE is H CS is H between valid commands 5C TBD TBD Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING Self Refresh Mode CK and CK at OV Self refresh current IDD6 TBD TBD mA CKE lt 0 2V Other control and address bus inputs are FLOATING Data bus inputs are FLOATING all bank interleaving reads IOUT OMA BL 4 CL CL ID
43. VDD DDR2 800 DDR2 667 DDR2 533 Maximum undershoot area below VSS DDR2 800 DDR2 667 DDR2 533 Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot Maximum overshoot area above VDD DDR2 800 667 DDR2 533 Maximum undershoot area below VSS DDR2 800 667 DDR2 533 Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot Maximum overshoot area above VDDQ DDR2 800 667 DDR2 533 Maximum undershoot area below VSSQ DDR2 800 667 DDR2 533 VDD VDDQ VSS VSSQ Volts V EDE2104ABSE EDE2108ABSE Pins Specification Unit on Address 05 0 5 V 0 66 V ns 0 8 V ns 1 0 V ns 0 66 V ns 0 8 V ns 1 0 V ns CK CK 0 5 V 0 5 V 0 23 V ns 0 28 V ns 0 23 V ns 0 28 V ns DQ DQS DQS 0 5 V RDQS RDQS DM 0 5 V 0 23 V ns 0 28 V ns 0 23 V ns 0 28 V ns Maximum amplitude Overshoot area Undershoot area Time ns Overshoot Undershoot Definition Preliminary Data Sheet E1196E10 Ver 1 0 ELPIDA EDE2104ABSE EDE2108ABSE DC Characteristics 1 TC 006 to 89506 VDD VDDQ 1 8V 0 1V Parameter Symbol Grade 8G Operating current IDDO 6E ACT PRE Operating current apt pe ACT READ PRE 5C Precharge power pis a IDD2P 6E down standby current 5C 8G Tad umen D29 E y 5C 8G Idle standby current IDD2N 6E 5C 8G IDD3P F 6E Active power down E standby current 8G IDD3P S 6E 5C 8G Acti
44. X or VOX Differential Signal Levels Preliminary Data Sheet E1196E10 Ver 1 0 11 ELPIDA EDE2104ABSE EDE2108ABSE ODT DC Electrical Characteristics TC 0 C to 85 C VDD VDDQ 1 8V 0 1V Parameter Symbol min typ max Unit Note Rtt effective impedance value for EMRS A2 0 1 75 Q Rtt1 eff 60 75 90 Q 1 Rtt effective impedance value for EMRS A6 A2 1 0 150 Q Rtt2 eff 120 150 180 Q 1 Rtt effective impedance value for EMRS A6 A2 1 1 50 Q Rtt3 eff 40 50 60 Q 1 Deviation of VM with respect to VDDQ 2 AVM 6 6 1 Note 1 Test condition for Rtt measurements Measurement Definition for Rtt eff Apply VIH AC and VIL AC to test pin separately then measure current I VIH AC and I VIL AC respectively VIH AC and VDDQ values defined in SSTL_18 VIH AC VIL AC Rtt eff I VIH AC VIL AC Measurement Definition for AVM Measure voltage VM at test pin midpoint with no load 2xVM M 1 x100 VDD OCD Default Characteristics TC 0 C to 85 C VDD VDDQ 1 8V 0 1V Parameter min typ max Unit Notes Output impedance 12 6 18 23 4 1 5 Pull up and pull down mismatch 0 4 1 2 Output slew rate 1 5 5 V ns 3 4 Notes 1 Impedance measurement condition for output source DC current VDDQ 1 7V VOUT 1420mV VOUT VDDQ IOH must be less than 23 46 for values of VOUT between VDDQ and VDDQ 280mvV Impedance measurement condition for output sink DC
45. ata Sheet E1196E10 Ver 1 0 68 EDE2104ABSE EDE2108ABSE CK l l l ay i S gt ie E DOS DQS Ma Cs A tien E RAN Y p L RL 1 4 l gt tWR gt tRP DOODO me 3 gt tRC l Auto precharge begins Burst Write with Auto Precharge Followed by an Activation to the Same Bank WL 4 BL 8 tWR 2 tRP 3 Preliminary Data Sheet E1196E10 Ver 1 0 ELPIDA 69 EDE2104ABSE EDE2108ABSE Refresh Requirements DDR2 SDRAM requires a refresh of all rows in any rolling 64ms interval Each refresh is generated in one of two ways by an explicit automatic refresh command or by an internally timed event in self refresh mode Dividing the number of device rows into the rolling 64 ms interval defines the average refresh interval tREFI which is a guideline to controllers for distributed refresh timing Automatic Refresh Command REF When CS RAS and CAS are held low and WE high at the rising edge of the clock the chip enters the automatic refresh mode REF All banks of the DDR2 SDRAM must be precharged and idle for a minimum of the precharge time tRP before the auto refresh command REF can be applied An address counter internal to the device supplies the bank address during the refresh cycle No control of the external address bus is required once this cycle has started When the refresh cycle has completed all banks
46. ate line between shaded DC level to VREF DC region use nominal slew rate for derating value See the figure of Slew Rate Definition Nominal If the actual signal is earlier than the nominal slew rate line anywhere between shaded DC to VREF DC region the slew rate of a tangent line to the actual signal from the DC level to VREF DC level is used for derating value see the figure of Slew Rate Definition Tangent Although for slow slew rates the total setup time might be negative i e a valid input signal will not have reached VIH IL AC at the time of the rising clock transition a valid input signal is still required to complete the transition and reach VIH IL AC For slew rates in between the values listed in the tables below the derating values may obtained by linear interpolation These values are typically not subject to production test They are verified by design and characterization Derating Values of tDS tDH with Differential DQS DDR2 533 DOS DQS differential slew rate 4 0V ins 3 0V ns 2 0 V ns 1 8 V ns 1 6 V ns 1 4 V ns 1 2 V ns 1 0 V ns 0 8 V ns AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH Unit 2 0 125 445 125 445 1125 44b ps 15 83 21 83 21 83 21 95 433 ps 100 0 0 oO O0 12 412 24 24 ps DQ 0 9 11 14 11 14 1 2 13 410 25 422
47. ation Stable clocks CKE tDELAY CKE asynchronously drops low Clocks can be turned off after this point ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 16 EDE2104ABSE EDE2108ABSE Input Clock Frequency Change during Precharge Power Down DDR2 SDRAM input clock frequency can be changed under following condition DDR2 SDRAM is in precharged power down mode ODT must be turned off and CKE must be at logic low level A minimum of 2 clocks must be waited after CKE goes low before clock frequency may change SDRAM input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade During input clock frequency change ODT and CKE must be held at stable low levels Once input clock frequency is changed stable new clocks must be provided to DRAM before precharge power down may be exited and DLL must be RESET via EMRS after precharge power down exit Depending on new clock frequency an additional MRS command may need to be issued to appropriately set the WR CL and soon During DLL relock period ODT must remain off After the DLL lock time the DRAM is ready to operate with new clock frequency Clock Frequency Change in Precharge Power Down Mode TO T1 12 T4 TX TX 1 Ty Ty 1 Ty 3 Ty 4 Tz M OK ius TE NE NU T Command NOP CNN NCI INIA INE p r zs Lo ow Se of meg M CKE A Frequency change
48. be taken for PW boards with semiconductor MOS devices on it 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Vpop or GND with a resistor if it is considered to have a possibility of being an output pin The unused pins must be handled in accordance with the related specifications 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power on does not necessarily define initial status of MOS devices Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the MOS devices with reset function have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers MOS devices are not initialized until the reset signal is received Reset operation must be executed immediately after power on for MOS devices having reset function CME0107 Preliminary Data Sheet E1196E10 Ver 1 0 ELPIDA 80 EDE2104ABSE EDE2108ABSE The information in this document is subject to change without notice Before using th
49. burst write Burst Write Operation RL 3 WL 2 BL 8 AL 0 CL 3 ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 58 EDE2104ABSE EDE2108ABSE 4 l Q 4l l 4 CK 1 a 1 a a I 1 1 a 1 2 1 a Posted Command NOP DOS DAS gt tWR DQ Completion of the burst write Burst Write Operation RL 5 WL 4 BL 4 tWR 3 AL 2 CL 3 TO T7 T8 T9 T10 CK 1 al pU 1 ir oY 1 i il p CK Write to Read CL 1 BU2 IWTR 2 6 Posted Command NOP BEAD NOP DQS DQS RL 5 gt i l o He Burst Write Followed by Burst Read RL 5 BL 4 WL 4 tWTR 2 AL 2 CL 3 The minimum number of clock from the burst write command to the burst read command is CL 1 BL 2 a write to read turn around time tWTR This tWTR is not a write recovery time tWR but the time required to transfer the Abit write data from the input buffer into sense amplifiers in the array Command DQS DQS Seamless Burst Write Operation RL 5 WL 4 BL 4 Enabling a write command every other clock supports the seamless burst write operation This operation is allowed regardless of same or dif
50. capturing data at the receiver e DOS is edge aligned with data for READs center aligned with data for WRITES e Differential clock inputs CK and CK e DLL aligns DQ and DOS transitions with CK transitions e Commands entered on each positive CK edge data and data mask referenced to both edges of DOS e Data mask DM for write data e Posted CAS by programmable additive latency for better command and data bus efficiency e Off Chip Driver Impedance Adjustment and On Die Termination for better signal quality e Programmable RDQS RDQS output for making x 8 organization compatible to x 4 organization e DQS RDQS can be disabled for single ended Data Strobe operation Elpida Memory Inc 2007 Ordering Information Part number EDE2104ABSE 8G E EDE2104ABSE 6E E EDE2104ABSE 5C E EDE2108ABSE 8G E EDE2108ABSE 6E E EDE2108ABSE 5C E Part Number Elpida Memory Mask Organization Internal version words x bits Banks B 512M x 4 8 256M x 8 EDE2104ABSE EDE2108ABSE Speed bin CL tRCD tRP Package DDR2 800 6 6 6 DDR2 667 5 5 5 68 ball FBGA DDR2 533 4 4 4 DDR2 800 6 6 6 DDR2 667 5 5 5 DDR2 533 4 4 4 EDE2104ABSE 8G E Type D Monolithic Device Product Family E DDR2 Density Bank 21 200 8 bank Organization 04 x4 08 x8 Power Supply Interface A 1 8V SSTL_18 Preliminary Data Sheet E1196E10 Ver 1 0 Environment c
51. current VDDQ 1 7V VOUT 280mV VOUT IOL must be less than 23 4Q for values of VOUT between OV and 280mV 2 Mismatch is absolute value between pull up and pull down both are measured at same temperature and voltage 3 Slew rate measured from VIL AC to VIH AC 4 The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC This is guaranteed by design and characterization 5 DRAM specifications for timing voltage and slew rate are no longer applicable if OCD is changed from default settings ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 12 Pin Capacitance TA 25 C VDD VDDQ 1 8V 0 1V Parameter CLK input pin capacitance Input pin capacitance 8G 6E 5C Input output pin capacitance 8G 6E 5C Notes 1 Matching within 0 25pF 2 Matching within 0 50pF Preliminary Data Sheet E1196E10 Ver 1 0 Symbol CCK CIN CI O Pins CK CK RAS CAS CS CKE ODT Address DOS DQS RDQS RDQS DM 13 EDE2104ABSE EDE2108ABSE min 1 0 1 0 1 0 2 0 2 9 max 2 0 1 75 2 0 3 9 4 0 Unit pF pF pF pF pF Notes ELPIDA EDE2104ABSE EDE2108ABSE AC Characteristics TC 0 C to 85 C VDD VDDQ 1 8V 0 1V VSS VSSQ 0V DDR2 800 667 New units tCK avg and nCK are introduced in DDR2 800 and DDR2 667 tCK avg actual tCK avg of the
52. d can be applied with power down exit latency tXP tXARD or tXARDS after CKE goes high Power down exit latency is defined at AC Characteristics table of this data sheet tCKE min tXP tXARD tXARDS tCKE min Enter power down mode VIH or VIL UA Exit power down mode Power Down Read to Power Down Entry TO T1 T2 Tx Tx 1 Tx 2 Tx 3 Tx 4 Tx 6 Tx47 Tx 8 Tx 9 CK aate AE E ME CUM di CUM TT S RE 77 CK J VS x l TE 24 Parcel Ix asl Command BID Read operation starts with a read command and E CKE should be kept high until the end of burst operation CKE DOS es DA Tx Tx 1 1 Tx 3 Tx 4 Tx 6 Tx47 Tx 8 Tx 9 Lc ue xm de xr d x ME nc NEN XEM EE 2 MUT NE al Command re 7 CKE should be kept high until the end of burst operation CKE ad DQS OKT ASA SAAS AGATA BL 8 Preliminary Data Sheet E1196E10 Ver 1 0 ELPIDA EDE2104ABSE EDE2108ABSE Read with Auto Precharge to Power Down Entry Tx TX 1 Tx 2 T3 Tx 4 Txt5 Tx 6 Tx 7 Tx 8 Tx 9 CK D mm od mm Dem s A Command PRE i 2 with tRTP i 7 5ns _ CKE should be kept high CKE ang IBAG min satisfied _1 until the end of burst operation DQ
53. drivers Taking CKE low provides precharge power down and Self Refresh operation all banks idle or active power down row active in any bank CKE is synchronous for power down entry and exit and for self refresh entry CKE is asynchronous for self refresh exit CKE must be maintained high throughout read and write accesses Input buffers excluding CK CK and CKE are disabled during power down Input buffers excluding CKE are disabled during self refresh DM input pins DM is an input mask signal for write data Input data is masked when DM is sampled high coincident with that input data during a Write access DM is sampled on both edges of DQS Although DM pins are input only the DM loading matches the DQ and DQS loading For x8 configuration DM function will be disabled when RDQS function is enabled by EMRS DQ input output pins Bi directional data bus DQS DQS input output pins Output with read data input with write data for source synchronous operation Edge aligned with read data centered in write data Used to capture write data DQS can be disabled by EMRS RDQS RDQS output pins Differential Data Strobe for READ operation only DM and RDQS functions are switch able by EMRS These pins exist only in x8 configuration RDQS output will be disabled when DQS is disabled by EMRS ODT input pins ODT On Die Termination control is a registered high signal that enables termination resistance internal to the DDR 2
54. e executed any time after power up without affecting array contents DDR2 SDRAM Mode Register Set MRS The mode register stores the data for controlling the various operating modes of DDR2 SDRAM It controls CAS latency burst length burst sequence test mode DLL reset tWR and various vendor specific options to make DDR2 SDRAM useful for various applications The default value of the mode register is not defined therefore the mode register must be written after power up for proper operation The mode register is written by asserting low on CS IRAS CAS WE BAO BA1 and BA2 while controlling the state of address pins AO to A14 The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register The mode register set command cycle time tMRD is required to complete the write operation to the mode register The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state The mode register is divided into various fields depending on functionality Burst length is defined by AO to A2 with options of 4 and 8 bit burst lengths The burst length decodes are compatible with DDR SDRAM Burst address sequence type is defined by A3 CAS latency is defined by A4 to A6 The DDR2 doesn t support half clock latency mode A7 is used for test mode A8 is used for DLL reset A7 must be set to low for normal MRS operation
55. e from CK CK DQS output access time from CK CK CK high level width CK low level width CK half period Clock cycle time CL 6 CL 5 CL 4 CL 3 DQ and DM input hold time differential strobe DQ and DM input hold time single ended strobe DQ and DM input setup time differential strobe DQ and DM input setup time single ended strobe Control and Address input pulse width for each input DQ and DM input pulse width for each input Data out high impedance time from CK CK Data out low impedance time from CK CK DQS DQ skew for DQS and associated DQ signals DQ hold skew factor DQ DQS output hold time from DQS DOS latching rising transitions to associated clock edges DQS input high pulse width DQS input low pulse width DOS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Address and control input hold time Address and control input setup time Read preamble Read postamble Active to precharge command Active to auto precharge delay Preliminary Data Sheet E1196E10 Ver 1 0 Symbol tRCD tRP tRC tAC tDQSCK tCH tCL tHP tCK tCK tCK tCK tDH base tDH1 base tDS base tDS1 base tIPW tDIPW tHZ tLZ tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE base tIS base tRPRE tRPST tRAS tRAP 16 5C DDR2 533 4 4 4 min 15 15 60 500
56. e second third and fourth access will also occur within this group segment however the burst order is a function of the starting address and the burst sequence A new burst access must not interrupt the previous 4 bit burst operation The minimum CAS to CAS delay is defined by tCCD and is a minimum of 2 clocks for read or write cycles Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM In this operation the DDR2 SDRAM allows a CAS read or write command to be issued immediately after the RAS bank activate command or any time during the RAS CAS delay time tRCD period The command is held for the time of the Additive Latency AL before it is issued inside the device The Read Latency RL is controlled by the sum of AL and the CAS latency CL Therefore if a user chooses to issue a RAW command before the tRCD min then AL greater than O must be written into the EMRS The Write Latency WL is always defined as RL 1 read latency 1 where read latency is defined as the sum of additive latency plus CAS latency RL AL CL 1 0 1 2 3 4 5 6 7 8 9 10 11 12 CK nm o CK Lee ALIA A l Command DOS DQS EN noires gt tRAC Read Followed by a Write to the Same Bank AL 2 and CL 3 RL AL CL 5 WL RL 1 4 DQS DQS 2 tRAC
57. ed location and continue for the fixed burst length of four or eight in a programmed sequence Accesses begin with the registration of an active command which is then followed by a read or write command The address bits registered coincident with the active command is used to select the bank and row to be accessed BAO BA1 and BA2 select the bank AO to A14 select the row The address bits registered coincident with the read or write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued Prior to normal operation the DDR2 SDRAM must be initialized The following sections provide detailed information covering device initialization register definition command descriptions and device operation Power On and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner Operational procedures other than those specified may result in undefined operation Power Up and Initialization Sequence The following sequence is required for power up and initialization 1 Apply power and attempt to maintain CKE below 0 2 x VDDQ and ODT at a low state all other inputs may be undefined VDD VDDL and VDDQ are driven from a single power converter output AND VTT is limited to 0 95V max AND VREF tracks VDDQ 2 or Apply VDD before or at the same time as VDDL Apply VDDL before or at the same time as VDDQ Apply VDDQ b
58. efore or at the same time as VTT and VREF at least one of these two sets of conditions must be met 2 Start clock and maintain stable condition 3 For the minimum of 200us after stable power and clock CK CK then apply NOP or DESL and take CKE high 4 Wait minimum of 400ns then issue precharge all command NOP or DESL applied during 400ns period 5 Issue EMRS 2 command To issue EMRS 2 command provide low to BAO and BA2 high to BA1 6 Issue EMRS 3 command To issue EMRS 3 command provide low to BA2 high to BAO and BA1 7 Issue EMRS to enable DLL To issue DLL enable command provide low to AO high to BAO and low to 1 BA2 and A13 A14 8 Issue a mode register set command for DLL reset To issue DLL reset command provide high to A8 and low to BAO to BA2 and A13 A14 9 ssue precharge all command 10 Issue 2 or more auto refresh commands 11 5516 a mode register set command with low to A8 to initialize device operation i e to program operating parameters without resetting the DLL 12 At least 200 clocks after step 8 execute OCD calibration Off Chip Driver impedance adjustment If OCD calibration is not used EMRS OCD default command A9 A8 A7 1 followed by EMRS OCD calibration mode exit command A9 A8 A7 0 must be issued with other operating parameters of EMRS 13 The DDR2 SDRAM is now ready for normal operation Note 1 To guarantee ODT off VREF must be valid and a low
59. ent state ICS CAS WE Address Command Operation Note Write Hox x x x DESL ew Write recovering L H H H NOP Continue burst to end Write recovering L H L H BA CA A10 READ READA ILLEGAL 1 L H L L BA CA A10 AP WRIT WRITA Burst interrupt 1 4 L L H H BA RA ACT ILLEGAL 1 L L H L BA PRE ILLEGAL 1 8 L L H L A10 AP PALL ILLEGAL 8 L L L H x REF ILLEGAL L L L H x SELF ILLEGAL L L L L BA MRS OPCODE MRS ILLEGAL L L L L EMRS 1 2 ILLEGAL L H H H x NOP to end L H L H BA CA A10 READ READA ILLEGAL 1 7 L H L L BA CA A10 AP WRIT WRITA ILLEGAL 1 7 L L H H BA RA ACT ILLEGAL 1 7 L L H L BA PRE ILLEGAL 1 7 8 L L H L A10 AP PALL ILLEGAL 7 8 L L L H x REF ILLEGAL L L L H x SELF ILLEGAL L L L L BA MRS OPCODE MRS ILLEGAL L L L L EMRS 1 2 ILLEGAL Miei ae H x x x x DESL ie eae auto precharge Continue burst to end L H H H x NOP gt Write recovering with auto precharge L H L H BA CA A10 READ READA ILLEGAL 1 7 L H L L BA CA A10 AP WRIT WRITA ILLEGAL 1 7 L L H H BA RA ACT ILLEGAL 1 7 L L H L BA PRE ILLEGAL 1 7 8 L L H L A10 AP PALL ILLEGAL 7 8 L L L H x REF ILLEGAL L L L H x SELF ILLEGAL L L L L BA MRS OPCODE MRS ILLEGAL L L L L EMRS 1 2 ILLEGAL Preliminary Data Sheet E1196E10 Ver 1 0 ELPIDA Current state Precharging Row activating Write recovering Preliminary Data Sheet E1196E10 Ver 1 0 ICS r r r ij
60. er the clock must be restarted and stable before the device can exit self refresh operation Once self refresh exit command is registered a delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device CKE must remain high for the entire self refresh exit period tXSRD for proper operation NOP or deselect commands must be registered on each positive clock edge during the self refresh exit interval ODT should also be turned off during tXSRD TO T1 T2 T3 T4 T5 T6 Tm Tn tCK l l tCH tCL ICK a pes CK oe ie p E l l CKE I LLLA tIS Notes 1 Device must be in the All banks idle state prior to entering self refresh mode 2 ODT must be turned off tAOFD before entering self refresh mode and can be turned on again when tXSRD timing is satisfied 3 tXSRD is applied for a read or a read with autoprecharge command 4 tXSNR is applied for any command except a read or a read with autoprecharge command Self Refresh Command ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 71 EDE2104ABSE EDE2108ABSE Power Down PDEN Power down is synchronously entered when CKE is registered low along with NOP or deselect command CKE is not allowed to go low while mode register or extended mode regist
61. er command time or read or write operation is in progress CKE is allowed to go low while any of other operations such as row activation precharge or auto precharge or auto refresh is in progress but power down IDD spec will not be applied until finishing those operations Timing diagrams are shown in the following pages with details for entry into power down The DLL should be in a locked state when power down is entered Otherwise DLL should be reset after exiting power down mode for proper read operation If power down occurs when all banks are idle this mode is referred to as precharge power down if power down occurs when there is a row active in any bank this mode is referred to as active power down Entering power down deactivates the input and output buffers excluding CK CK ODT and CKE Also the DLL is disabled upon entering precharge power down or slow exit active power down but the DLL is kept enabled during fast exit active power down In power down mode CKE low and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM and ODT should be in a valid state but all other input signals are Don t Care CKE low must be maintained until tCKE has been satisfied Power down duration is limited by 9 times tREFI of the device The power down state is synchronously exited when CKE is registered high along with a NOP or deselect command CKE high must be maintained until tCKE has been satisfied A valid executable comman
62. er test is referenced 2 VDDQ 1 V VOUT 1 42V VDDQ 1 7V VOUT 0 28V Unit Notes uA VDD gt VIN gt VSS uA VDDQ gt VOUT gt VSS V 5 V 5 V 1 mA 3 4 5 mA 2 4 5 3 4 The DC value of VREF applied to the receiving device is expected to be set to VTT 5 After OCD calibration to 18Q at TC 25 C VDD VDDQ 1 8V DC Characteristics 3 TC 0 C to 85 C VDD VDDQ 1 8V 0 1V Parameter Symbol AC differential input voltage VID AC AC differential cross point voltage VIX AC AC differential cross point voltage VOX AC min 0 5 0 5 x VDDQ 0 175 0 5 x VDDQ 0 125 max Unit Notes VDDQ 0 6 V 1 2 0 5xVDDQ 0 175 V 2 0 5 x VDDQ 0 125 V 3 Notes 1 VID AC specifies the input differential voltage VTR VCP required for switching where VTR is the true input signal such as CK DOS RDQS and VCP is the complementary input signal such as CK DQS RDQS The minimum value is equal to VIH AC VIL AC 2 The typical value of VIX AC is expected to be about 0 5 x VDDQ of the transmitting device and VIX AC Is expected to track variations in VDDQ VIX AC indicates the voltage at which differential input signals must cross 3 The typical value of VOX AC is expected to be about 0 5 x VDDQ of the transmitting device and VOX AC is expected to track variations in VDDQ VOX AC indicates the voltage at which differential output signals must cross VCP Crossing point VI
63. erefore the extended mode register 1 must be written after power up for proper operation The extended mode register 1 is written by asserting low on CS RAS CAS WE high on BAO and low on BA1 BA2 while controlling the states of address pins AO to A14 The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register 1 The mode register set command cycle time tMRD must be satisfied to complete the write operation to the extended mode register 1 Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state AO is used for DLL enable or disable A1 is used for enabling a half strength output driver A3 to A5 determines the additive latency A7 to A9 are used for OCD control A10 is used for DQS disable and A11 is used for RDQS enable A2 and A6 are used for ODT setting A0 Lo TT 0 Tes foas bas O60 program Rit tatency Rt DCIDUL Extended mode register MEN M ojojo mrs 0 0 1 EMRS Q 0 1 0 Emesa 0 1 1 EMRS Reserved et a ee i Driver impedance adjustment 0 0 0 OCD calibration mode exit 0 1 0 JDiv 5 5 0 00 1 0 0 Adutmode 0 0 A12 Qoff O Output buffers enabled Output buffers disabled 0 Enable m Output driver A1 impeda
64. ew rate Vins 0 7 43 54 13 24 17 6 ps 0 6 67 83 37 53 23 ps 0 5 110 125 80 95 50 65 ps 0 4 175 188 145 158 115 128 ps 0 3 285 292 255 262 225 232 ps 0 25 350 375 920 345 290 315 ps 0 2 525 500 495 470 465 440 ps 0 15 800 108 0 678 140 648 ps 0 1 1450 1125 1420 1095 1390 1065 ps ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 25 EDE2104ABSE EDE2108ABSE Derating Values of tlS tlH DDR2 667 DDR2 800 CK CK Differential Slew Rate 2 0 V ns 1 5 V ns 1 0 V ns AUS AtlH AUS AtlH AUS AtlH Unit Notes 4 0 150 94 180 124 210 154 ps 3 5 143 89 173 119 203 149 ps 3 0 133 83 163 113 193 143 ps 2 5 120 75 150 105 180 135 ps 2 0 100 45 130 75 160 105 ps 1 5 67 21 97 51 127 81 ps 1 0 0 0 30 30 60 60 ps 0 9 5 14 25 16 55 46 ps Command address 0 8 13 31 17 1 47 29 ps slew Fate Vins 0 7 22 54 8 24 38 6 ps 0 6 34 83 4 53 26 23 ps 0 5 60 125 30 95 0 65 ps 0 4 100 188 0 158 40 128 ps 0 3 168 292 138 262 108 232 ps 0 25 200 375 170 345 140 915 ps 0 2 325 500 295 470 265 440 ps 0 15 517 108 487 678 457 648 ps 0 1 1000 1125 970 1095 940 1065 ps ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 26 EDE2104ABSE E
65. f not already an integer round to the next higher integer 2 AL Additive Latency 3 MRS A12 bit defines which active power down exit timing to be applied 4 The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH AC level for a rising signal and VIL AC for a falling signal applied to the device under test 5 The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIL DC level for a rising signal and VIH DC for a falling signal applied to the device under test lt gt gt lt gt tDS tDS tDH VDDQ VIH AC min VIH DC min VREF VIL DC max VIL AC max VSS Input Waveform Timing 1 tDS tDH Input Waveform Timing 2 tIS ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 17 EDE2104ABSE EDE2108ABSE 6 tHP is the minimum of the absolute half period of the actual input clock tHP is an input parameter but not an input specification parameter It is used in conjunction with tQHS to derive the DRAM output timing tOH The value to be used for tQH calculation is determined by the following equation tHP min tCH abs abs where tCH abs is the minimum of the actual instantaneous clock high time abs is the minimum of the actual instantaneous clock low time 7 tQHS accounts for a The pulse duration distortion of on chip clock circuits which
66. ferent banks as long as the banks are activated ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 99 EDE2104ABSE EDE2108ABSE TO T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 oo so i usus A ee se eese DQS DQS Burst interrupt is only allowed at this timing Write Interrupt by Write WL 3 BL 8 Notes 1 Write burst interrupt function is only allowed on burst of 8 Burst interrupt of 4 is prohibited 2 Write burst of 8 can only be interrupted by another write command Write burst interruption by read command or precharge command is prohibited 3 Write burst interrupt must occur exactly two clocks after previous write command Any other write burst interrupt timings are prohibited Write burst interruption is allowed to any bank inside DRAM Write burst with auto precharge enabled is not allowed to interrupt Write burst interruption is allowed by another write with auto precharge command All command timings are referenced to burst length set in the mode register They are not referenced to actual burst For example minimum write to precharge timing is WL BL 2 tWR where tWR starts with the rising clock after the un interrupted burst end and not from the end of actual burst end QUIM ONE S ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 60 EDE2104ABSE EDE2108ABSE Write Data Mask One write data mask DM pin for each 8 data bits DQ wil
67. fter power up for proper operation The extended mode register 2 is written by asserting low on CS RAS CAS WE high on BA1 and low on BAO while controlling the states of address pins AO to A14 The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register 2 The mode register set command cycle time tMRD must be satisfied to complete the write operation to the extended mode register 2 Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state Extended mode register 2 Note 1 The rest bits in EMRS 2 is reserved for future use and all bits in EMRS 2 except A7 BAO and BA1 must be programmed to 0 when setting the extended mode register 2 during initialization High Temperature A7 Self refresh rate Enable EMRS 2 EMRS 3 Programming Reserved Aor e nee y wv v v v v v v v v v v v v v v v v Note 1 EMRS 8 is reserved for future use and all bits except BAO and BA1 must be programmed to 0 when setting the mode register during initialization EMRS 3 ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 44 EDE2104ABSE EDE2108ABSE Off Chip Driver OCD Impedance Adjustment DDR2 SDRAM supports driver calibration feature and the OCD Flow Chart is an example of sequence Every calibration mode command should be followed
68. i ee ee e ee bod ATFS ATRH ATRS ATFH Setup slew rate _ tangent line VREF DC VIL AC max Setup slew rate _ tangent line VIH AC min VREF DC Falling signal ATES Rising signal ATRS Hold slew rate _ tangent line VREF DC VIL DC max Hold slew rate _ tangent line VIH DC min VREF Rising signal ATRH Falling signal ATEH Slew Rate Definition Tangent Preliminary Data Sheet E1196E10 Ver 1 0 ELPIDA 28 Block Diagram CK CK CKE Clock generator Address BAO BA1 BA2 Command decoder Control logic Preliminary Data Sheet E1196E10 Ver 1 0 How address buffer and refresh counter Column address buffer and burst counter EDE2104ABSE EDE2108ABSE Row decoder 29 Memory cell array Sense amp Column decoder Data control circuit Latch circuit DOS DQS gt RDQS RDQS ODT DM ELPIDA EDE2104ABSE EDE2108ABSE Pin Function CK CK input pins CK and CK are differential clock inputs All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK Output read data is referenced to the crossings of CK and CK both directions of crossing ICS input pin All commands are masked when CS is registered high CS provides for external rank selection on systems with multiple ranks CS is considered part of
69. input clock under operation nCK one clock cycle of the input clock counting the actual clock edges Speed bin Parameter Active to read or write command delay Precharge command period Active to active auto refresh command time DQ output access time from CK CK DQS output access time from CK ICK CK high level width CK low level width CK half period Clock cycle time CL 6 CL 5 CL 4 CL 3 DQ and DM input hold time DQ and DM input setup time Control and Address input pulse width for each input DQ and DM input pulse width for each input Data out high impedance time from CK CK DOS DQS low impedance time from CK CK DQ low impedance time from CK CK DQS DQ skew for DQS and associated DQ signals DQ hold skew factor DQ DQS output hold time from DQS DOS latching rising transitions to associated clock edges DQS input high pulse width DOS input low pulse width DOS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Symbol tRCD tRP tRC tAC tDQSCK tCH avg tCL avg tHP tCK avg tCK avg tCK avg tCK avg tDH base tDS base tlPW tDIPW tHZ tLZ DQS tLZ DQ tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPST Preliminary Data Sheet E1196E10 Ver 1 0 86 DDR2 800 6 6 6 min 15 15 60 400 350 0 48 0 4
70. is document confirm that this is the latest version No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory Inc Elpida Memory Inc does not assume any liability for infringement of any intellectual property rights including but not limited to patents copyrights and circuit layout licenses of Elpida Memory Inc or third parties by or arising from the use of the products or information listed in this document No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of Elpida Memory Inc or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of the customer s equipment shall be done under the full responsibility of the customer Elpida Memory Inc assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information Product applications Be aware that this product is for use in typical electronic equipment for general purpose applications Elpida Memory Inc makes every attempt to ensure that its products are of high quality and reliability However users are instructed to contact Elpida Memory s sales office before
71. itiated by having CS CAS and WE low while holding RAS high at the rising edge of the clock The address inputs determine the starting column address Write latency WL is defined by a read latency RL minus one and is equal to AL CL 1 A data strobe signal DOS should be driven low preamble one clock prior to the WL The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DOS following the preamble The tDQSS specification must be satisfied for write cycles The subsequent burst bit data are issued on successive edges of the DQS until the burst length of 4 is completed When the burst has finished any additional data supplied to the DQ pins will be ignored The DQ Signal is ignored after the burst write operation is complete The time from the completion of the burst write to bank precharge is the write recovery time tWR CK Command DQS DQS DQ Completion of the burst write Burst Write Operation RL 3 WL 2 BL 4 tWR 2 AL 0 CL 3 T3 T4 T5 T6 T7 CK Sec heel ml o os lemma mes V Y CK Command NOP tDQSS a sce ees sh h iM la iV 1 DQS DQS li p P teed sesli WLi RL 1 2 gt tWR L T TT co eo fsa 56 Completion of the
72. l be supported on DDR2 SDRAMs Consistent with the implementation on DDR I SDRAMSs It has identical timings on write operations as the data bits and though used in a uni directional manner is internally loaded identically to data bits to insure matched system timing DM is not used during read cycles DQS Write mask latency 0 Data Mask Timing tDQSS min CK k FO y r 1 E WE Command WRIT 777777777 777777 tDQSS max DAs Das YY 77777777 YL LLL OA MMU LLL ZB Data Mask Function WL 3 AL 0 shown ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 EDE2104ABSE EDE2108ABSE Precharge Command PRE The precharge command is used to precharge or close a bank that has been activated The precharge command is triggered when CS RAS and WE are low and CAS is high at the rising edge of the clock The precharge command can be used to precharge each bank independently or all banks simultaneously Three address bits A10 BAO BA1 and BA2 are used to define which bank to precharge when the command is issued Bank Selection for Precharge by Address Bits A10 BAO BAT BA2 Precharged Bank s L L L L Bank 0 only L H L L Bank 1 only L L H L Bank 2 only L H H L Bank 3 only L L L H Bank 4 only L H L H Bank 5 only L L H H Bank 6 only L H H H Bank 7
73. level must be applied to the ODT pin tCH tCL ls 4 lens 1 tIS 3 CKE coment 1 Goo CDS CT ers C pens CT Xe CI GC TD Ceo CT Ge CD Ce CANCE XC eee 1 Ld a 0 tRP MRD MRD tMRD i tRP i o tRFC tMRD Follow OCD Flowchart OCD default OCD calibration mode i exit DLL enable DLL reset L 200 cycles min Power up and Initialization Sequence ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 41 EDE2104ABSE EDE2108ABSE Programming the Mode Register and Extended Mode Registers For application flexibility burst length burst type CAS latency DLL reset function write recovery time tWR are user defined variables and must be programmed with a mode register set command MRS Additionally DLL disable function driver impedance additive CAS latency ODT On Die Termination single ended strobe and OCD Off Chip Driver Impedance Adjustment are also user defined variables and must be programmed with an extended mode register set command EMRS Contents of the Mode Register MR or Extended Mode Registers EMR can be altered by reexecuting the MRS and EMRS commands If the user chooses to modify only a subset of the MRS or EMRS variables all variables must be redefined when the MRS or EMRS commands are issued MRS EMRS and Reset DLL do not affect array contents which means reinitialization including those can b
74. nce control size A11 A10 RDQS enable DQS enable RDQS DM RDQS DQS pas bas RDQS enable Disable Notes 1 A13 and A14 are reserved for future use and must be programmed to 0 when setting the extended mode register 2 When adjust mode is issued AL from previously set value must be applied 3 After setting to default OCD mode needs to be exited by setting A9 to A7 to 000 Refer to the chapter Off Chip Driver OCD Impedance Adjustment for detailed information EMRS 1 ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 43 EDE2104ABSE EDE2108ABSE DLL Enable Disable The DLL must be enabled for normal operation DLL enable is required during power up initialization and upon returning to normal operation after having the DLL disabled The DLL is automatically disabled when entering self refresh operation and is automatically re enabled upon exit of self refresh operation Any time the DLL is enabled and subsequently reset 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock Failing to wait for synchronization to occur may result in a violation of the tAC or tDOSCK parameters EMRS 2 Programming The extended mode register 2 controls refresh related features The default value of the extended mode register 2 is not defined therefore the extended mode register 2 must be written a
75. ns and rounding up to next integer value As an example of the rolling window if t FAW tCK rounds up to 10 clocks and an activate command is issued in clock N no more than three further activate commands may be issued in clock N 1 through ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 32 CKE Truth Table EDE2104ABSE EDE2108ABSE CKE Previous Current Command n Current state cycle n 1 cycle n ICS IRAS CAS WWE Operation n Notes Power down L L x Maintain power down 11 13 15 L H DESL or NOP Power down exit 4 8 11 13 Self refresh L L x Maintain self refresh 11 15 L H DESL or NOP Self refresh exit 4 5 9 Bank Active H L DESL or NOP Active power down entry 4 8 10 11 13 All banks idle H L DESL or NOP Precharge power down entry 4 8 10 11 13 H L SELF Self refresh entry 6 9 11 13 AY H H Refer to the Command Truth Table 7 listed above Remark H VIH L VIL x Don t care Notes 1 OND 14 15 CKE n is the logic state of CKE at clock edge n CKE n 1 was the state of CKE at the previous clock edge Current state is the state of the DDR SDRAM immediately prior to clock edge n Command n is the command registered at clock edge n and operation n is a result of Command n All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document On self refresh exit DESL or NOP commands must be issued on
76. ode E Lead Free ROHS compliant Speed 8G DDR2 800 6 6 6 6E DDR2 667 5 5 5 5C DDR2 533 4 4 4 Package SE FBGA Die Rev ELPIDA Pin Configurations Ixxx indicates active low signal 2 O NC ROE vssoDMfibas NC VDDQ O VSSQ J O O VREF CKE EDE2104ABSE EDE2108ABSE 68 ball FBGA x8 x4 organization 3 7 60 GO O VDD NU RDOS VSS VSSQ DQS VDDQ DO7 DOS VSSQ poz O VDDQ VDDQ DQO VDDQ O O O DQ3 DQ2 VSSQ ds O O O O VSS VSSDL CK VDD O RAS CAS 5 oO A2 Top view Note marked pins are for x4 organization Differential data strobe for read Pin name Function AO to A14 Address inputs BAO BA1 BA2 Bank select DQO to DQ7 Data input output DOS DQS Differential data strobe RDQS RDQS ICS Chip select IRAS CAS WE Command input CKE Clock enable CK CK Differential clock input DM Write data mask Notes 1 Not internally connected with die 2 Don t connect Internally connected Preliminary Data Sheet E1196E10 Ver 1 0 Pin name ODT VDD VSS VDDQ VSSQ VREF VDDL VSSDL NC NU Function ODT control Supply voltage for internal circuit Ground for internal circuit Supply voltage for DQ circuit Ground for DQ circuit Input reference voltage Supply voltage for DLL circuit Ground for DLL circuit connection Not usable ELPIDA
77. om the completion of the burst write to the precharge command No precharge command should be issued prior to the tWR delay as DDR2 SDRAM allows the burst interrupt operation only Read by Read or Write by Write at the boundary of burst 4 TO T1 T2 T3 T4 CK CK Posted WRIT Command DQS DQS DQ Completion of the burst write Burst Write Followed by Precharge WL RL 1 3 Posted Command WES DQS DQS DQ Completion of the burst write Burst Write Followed by Precharge WL RL 1 4 ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 64 CK CK Command DQS DQS DQ Preliminary Data Sheet E1196E10 Ver 1 0 TO Posted WRIT gt 65 EDE2104ABSE EDE2108ABSE gt tWR Completion of the burst write Burst Write Followed by Precharge WL RL 1 4 BL 8 ELPIDA EDE2104ABSE EDE2108ABSE Auto Precharge Operation Before a new row in an active bank can be opened the active bank must be precharged using either the precharge command or the auto precharge function When a read or a write command is given to the DDR2 SDRAM the CAS timing accepts one extra address column address A10 to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle If A10 is l
78. ommands in frequency to a 32ms period tREFI 3 9us and higher temperature Self Refresh entry via A7 1 on EMRS 2 ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 EDE2104ABSE EDE2108ABSE Recommended DC Operating Conditions SSTL 18 Parameter Symbol min typ max Unit Notes Supply voltage VDD 1 7 1 8 1 9 V 4 Supply voltage for output VDDQ 1 7 1 8 1 9 V 4 Input reference voltage VREF 0 49 x VDDQ 0 50 x VDDQ 0 51 x VDDQ V 1 2 Termination voltage VTT VREF 0 04 VREF VREF 0 04 V 3 DC input logic high VIH DC VREF 0 125 VDDQ 0 3 V DC input low VIL DC 0 3 VREF 0 125 V An VIH AC VREF 0 200 5C VIH AC VREF 0 250 V p VIL AC VREF 0 200 V 5C VIL AC VREF 0 250 V Notes 1 The value of VREF may be selected by the user to provide optimum noise margin in the system Typically the value of VREF is expected to be about 0 5 x VDDQ of the transmitting device and VREF are expected to track variations in VDDQ 2 Peak to peak AC noise on VREF may not exceed 2 VREF DC VTT of transmitting device must track VREF of receiving device 4 VDDQ tracks with VDD VDDL tracks with VDD AC parameters are measured with VDD VDDQ and VDDL tied together 9 ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 AC Overshoot Undershoot Specification Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot Maximum overshoot area above
79. only H x x x All banks O to 7 Remark H VIH L VIL x VIH or VIL Burst Read Operation Followed by Precharge Minimum read to precharge command spacing to the same bank AL BL 2 clocks For the earliest possible precharge the precharge command may be issued on the rising edge that is Additive latency AL BL 2 clocks after a Read command A new bank active command may be issued to the same bank after the RAS precharge time tRP A precharge command cannot be issued until tRAS is satisfied TO T1 CK MA CK Posted DAS DQS zz ooo ene EE Burst Read Operation Followed by Precharge RL 4 BL 4 AL 1 CL 3 ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 62 EDE2104ABSE EDE2108ABSE Command DQS DQS DQ 2 tRAS min DQS DQS DQ gt Burst Read Operation Followed by Precharge RL 6 AL 2 CL 4 BL 8 ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 63 EDE2104ABSE EDE2108ABSE Burst Write followed by Precharge Minimum Write to Precharge Command spacing to the same bank WL BL 2 clocks tWR For write cycles a delay must be satisfied from the completion of the last burst write cycle until the precharge command can be issued This delay is known as a write recovery time tWR referenced fr
80. ow when the read or write Command is issued then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence If A10 is high when the Read or Write Command is issued then the auto precharge function is engaged During auto precharge a read Command will execute as normal with the exception that the active bank Will begin to precharge on the rising edge which is CAS latency CL clock cycles before the end of the read burst Auto precharge can also be implemented during Write commands The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array This feature allows the precharge operation to be partially or completely hidden during burst read cycles dependent upon CAS latency thus improving system performance for random data access The RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command Burst Read with Auto Precharge READA If A10 is high when a Read Command is issued the Read with Auto Precharge function is engaged The DDR2 SDRAM starts an auto Precharge operation on the rising edge which is AL BL 2 cycles later from the read with AP command when tRAS min is satisfied If tRAS min is not satisfied at the edge the start point of auto p
81. peration code data must be used In case of OCD calibration default output driver characteristics follow approximate nominal V I curve for 180 output drivers but are not guaranteed If tighter control Is required which is controlled within 18Q 3Q driver impedance range OCD must be used OCD applies only to normal full strength output drive setting defined by EMRS 1 and if reduced strength is set OCD default output driver characteristics are not applicable When OCD calibration adjust mode is used OCD default output driver characteristics are not applicable OCD Mode Set Program A9 A8 AT Operation 0 0 0 OCD calibration mode exit 0 0 1 Drive 1 DQ DQS RDQS high and DQS low 0 1 0 Drive 0 DQ DOS RDQS low and DQS high 1 0 0 Adjust mode 1 1 1 OCD calibration default OCD Impedance Adjustment To adjust output driver impedance controllers must issue the ADJUST EMRS command along with a 4bit burst code to DDR2 SDRAM as in OCD Adjustment Program table For this operation burst length has to be set to BL 4 via MRS command before activating OCD and controllers must drive this burst code to all DQs at the same time DTO in OCD Adjustment Program table means all DQ bits at bit time O DT1 at bit time 1 and so forth The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration all DOs and DQS s of a given DDR2 SDRAM will be adjusted to the same driver strength setting The maximum step co
82. recharge operation will be delayed until tRAS min is satisfied A new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously 1 The RAS precharge time tRP has been satisfied from the clock at which the auto precharge begins 2 The RAS cycle time tRC from the previous bank activation has been satisfied TO T1 T2 T3 T4 15 T6 T7 CK iy ney eee eee CK Les i Aio 1 Posted Command READ DQS DQS 2 DQ Auto precharge begins Burst Read with Auto Precharge Followed by an Activation to the Same Bank tRC limit RL 5 BL 4 AL 2 CL 3 tRTP lt 2tCK ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 66 EDE2104ABSE EDE2108ABSE Auto precharge begins Burst Read with Auto Precharge Followed by an Activation to the Same Bank tRAS lockout case RL 5 BL 4 AL 2 CL 3 CK CK Posted Command NOP gt tRAS min ipia quse DOS DQS d en tRP min M ALz2 3 IRL 5 tO ti t2 t3 n ooog gt tRC Auto precharge begins Burst Read with Auto Precharge Followed by an Activation to the Same Bank tRP limit RL 5 BL 4
83. recharge write recovery WR WR precharge time IDAL RU tRP tCK avg RU tRP tCK avg MON Internal write to read command delay tWTR 7 5 7 5 ns Internal read to precharge command IRTP 75 75 Ae delay Exit self refresh to a non read IXSNR tREC 4 10 tRFC 10 Ws command Exit self refresh to a read command tXSRD 200 200 nCK Exit precharge power down to any 2 E 2 nCK non read command Exit active power down to read 2 I 2 I 3 command Exit active power down to read command tXARDS 8 AL 7 AL nCK 2 3 slow exit low power mode CKE minimum pulse width high and 3 I 3 nCK low pulse width Output impedance test driver delay tOIT 0 12 0 12 ns MRS command to ODT update delay tMOD 0 12 0 12 ns Auto refresh to active auto refresh tREC 195 195 uc command time Average periodic refresh interval T 7 0 C lt TC lt 85 C USER i i 85 C lt 95 C tREFI 3 9 3 9 us Minimum time clocks remains ON DELAY tIS tCK avg tIS tCK avg after CKE asynchronously drops low tlH tlH ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 15 EDE2104ABSE EDE2108ABSE AC Characteristics TC 0 C to 85 C VDD VDDQ 1 8V 0 1V VSS VSSQ DDR2 533 Speed bin Parameter Active to read or write command delay Precharge command period Active to active auto refresh command time DQ output access tim
84. represents how well the actual tHP at the input is transferred to the output and b The worst case push out of DQS on one transition followed by the worst case pull in of DQ on the next transition both of which are independent of each other due to data pin skew output pattern effects and p channel to n channel variation of the output drivers 8 tOH tHP tOHS where tHP is the minimum of the absolute half period of the actual input clock and tQHS is the specification value under the max column The less half pulse width distortion present the larger the tOH value is and the larger the valid data eye will be Examples a If the system provides tHP of 1315ps into a DDR2 667 SDRAM the DRAM provides tQH of 975ps min b If the system provides tHP of 1420ps into a DDR2 667 SDRAM the DRAM provides tQH of 1080ps min 9 RU stands for round up WR refers to the tWR parameter stored in the MRS 10 When the device is operated with input clock jitter this parameter needs to be derated by the actual tERR 6 10per of the input clock output deratings are relative to the SDRAM input clock For example if the measured jitter into a DDR2 667 SDRAM has tERR 6 10per min 272ps and tERR 6 10per max 293ps then tDQSCK min derated tDQSCK min tERR 6 10per max 400ps 293ps 693ps and tDQSCK max derated tDOSCK max tERR 6 10per min 400ps 2 2ps 672ps Similarly tLZ DQ for DDR2 667 derates to tLZ DQ
85. rn off delay tAOFD 25 2 5 tCK 5 6 ODT turn off tAOF tAC min tAC max 600 ps 2 4 5 6 ODT turn off power down mode tAOFPD tAC min 2000 2 5tCK tAC max 1000 ps ODT to power down entry latency tANPD 3 3 tCK ODT power down exit latency tAXPD 8 8 tCK Notes 1 ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on ODT turn on time max is when the ODT resistance is fully on Both are measured from tAOND 2 ODT turn off time min is when the device starts to turn off ODT resistance ODT turn off time max is when the bus is in high impedance Both are measured from tAOFD 3 When the device is operated with input clock jitter this parameter needs to be derated by the actual tERR 6 10per of the input clock output deratings are relative to the SDRAM input clock 4 When the device is operated with input clock jitter this parameter needs to be derated by tJIT duty max tERR 6 10per max and tJIT duty min tERR 6 10per min of the actual input clock output deratings are relative to the SDRAM input clock For example if the measured jitter into a DDR2 667 SDRAM has tERR 6 10per min 272ps tERR 6 10per max 293ps tJlT duty min 106ps and tJlT duty max 94ps then tAOF min derated tAOF min tJIT duty max tERR 6 10per max 450ps 94ps 29305 837ps and tAOF max derated tAOF max tJIT duty min tERR 6 10per min
86. t signals the total tIS tDS setup time and tIH tDH hold time required is calculated by adding the data sheet tIS base tDS base and base tDH base value to the AtlS AtDS and AtDH derating value respectively Example tDS total setup time tDS base AtDS Setup tIS tDS nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF DC and the first crossing of VIH AC min Setup tIS tDS nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF DC and the first crossing of VIL AC max If the actual signal is always earlier than the nominal slew rate line between shaded VREF DC to AC region use nominal slew rate for derating value See the figure of Slew Rate Definition Nominal If the actual signal is later than the nominal slew rate line anywhere between shaded VREF DC to AC region the slew rate of a tangent line to the actual signal from the AC level to DC level is used for derating value see the figure of Slew Rate Definition Tangent Hold tlH tDH nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL DC max and the first crossing of VREF DC Hold tDH nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH DC min and the first crossing of VREF DC If the actual signal is always later than the nominal slew r
87. tting Available in case tWTR is satisfied The DDR2 SDRAM supports the concurrent auto precharge feature a read with auto precharge enabled or a write with auto precharge enabled may be followed by any column command to other banks as long as that command does not interrupt the read or write data transfer and all other related limitations apply E g Conflict between READ data and WRITE data must be avoided QU OE MI oue The minimum delay from a read or write command with auto precharge enabled to a command to a different bank is summarized below To command different bank non Minimum delay From command interrupting command Concurrent AP supported Units Read w AP Read or Read w AP BL 2 tCK Write or Write w AP BL 2 2 tCK Precharge or Activate 1 tCK Write w AP Read or Read w AP CL 1 BL 2 tWTR tCK Write or Write w AP BL 2 tCK Precharge or Activate 1 tCK ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 38 EDE2104ABSE EDE2108ABSE 8 The minimum delay from the read write and precharge command to the precharge command to the same bank is summarized below Precharge and Auto Precharge Clarification Minimum delay between From From command To command command to To Command Units Notes Read Precharge to same bank as read AL BL 2 Max RTP 2 2 tCK a b Precharge all AL BL 2 Max RTP 2 2 tCK a b Read w AP Precharge to same bank as read w AP AL BL 2 Max RTP 2 2 tCK
88. unt for adjustment is 16 and when the limit is reached further increment or decrement code has no effect The default setting may be any step within the 16 step range When Adjust mode command is issued AL from previously set value must be applied OCD Adjustment Program Abits burst data inputs to all DOs Operation DTO DT1 DT2 DT3 Pull up driver strength Pull down driver strength 0 0 0 0 NOP NOP 0 0 0 1 Increase by 1 step NOP 0 0 1 0 Decrease by 1 step NOP 0 1 0 0 NOP Increase by 1 step 1 0 0 0 Decrease by 1 step 0 1 0 1 Increase by 1 step Increase by 1 step 0 1 1 0 Decrease by 1 step Increase by 1 step 1 0 0 1 Increase by 1 step Decrease by 1 step 1 0 1 0 Decrease by 1 step Decrease by 1 step Other combinations Reserved ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 46 EDE2104ABSE EDE2108ABSE For proper operation of adjust mode WL RL 1 AL CL 1 clocks and tDS tDH should be met as the Output Impedance Control Register Set Cycle For input data pattern for adjustment DTO to DT3 is a fixed order and not affected by MRS addressing mode i e sequential or interleave CK CK Command DQS DQS DQ_in A OCD adjust mode OCD calibration mode exit Output Impedance Control Register Set Cycle Drive Mode Drive mode both drive 1 and drive 0 is used for controllers to measure DDR2 SDRAM Driver impedance before OCD impedance adjustment In this mode all outputs are driven o
89. ut tOIT after Enter drive mode command and all output drivers are turned off tOIT after OCD calibration mode exit command as the Output Impedance Measurement Verify Cycle Command EMRS X NOP EMRS High Z High Z DQS DQS DQs high and DQS low for drive 1 DQs low and DQS high for drive 0 DQs high for drive 1 DQ DQs low for drive 0 Ier tOIT enter aiivemode OCD Calibration mode exit Output Impedance Measurement Verify Cycle ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 47 EDE2104ABSE EDE2108ABSE ODT On Die Termination On Die Termination ODT is a feature that allows a DRAM to turn on off termination resistance for each DQ DQS DQS RDQS RDQS and DM signal via the ODT control pin The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on off termination resistance for any or all DRAM devices The ODT function is turned off and not supported in self refresh mode VDDQ VDDQ VDDQ sw SW2 Sw3 Rval1 Rval2 Rval3 DRAM fait input B buffer i Rval1 Rval2 Rval3 sw1 sw2 sw3 VSSQ VSSQ VSSQ Switch sw1 sw2 or sw3 is enabled by ODT pin Selection between sw1 sw2 or sw3 is determined by Rtt nominal in EMRS Termination included on all DQs DM DQS DQS RDQS and RDQS pins Target Rtt Q Rval1 2 Rval2 2 or Rval3 2 Functional Representation of ODT Command EMRS X NOP tAOFD O
90. ve standby current IDD3N 6E 5C 8G Operating current IDDAR 6E Burst read operating 5C 8G Operating current IDDAW 6E Burst write operating Preliminary Data Sheet E1196E10 Ver 1 0 max x4 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD x8 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Unit mA mA mA mA mA mA mA mA mA mA Test condition one bank tCK tCK IDD tRC tRC IDD tRAS tRAS min IDD CKE is H CS is H between valid commands Address bus inputs are SWITCHING Data bus inputs are SWITCHING one bank IOUT OmA BL 4 CL CL IDD AL 0 tCK tCK IDD tRC tRC IDD tRAS tRAS min IDD tRCD tRCD IDD CKE is H CS is H between valid commands Address bus inputs are SWITCHING Data pattern is same as IDD4W all banks idle tCK tCK IDD CKE Is L Other control and address bus inputs are STABLE Data bus inputs are FLOATING all banks idle tCK tCK IDD CKE is H CS is H Other control and address bus inputs are STABLE Data bus inputs are FLOATING all banks idle tCK tCK IDD CKE is H CS is H Other control and address bus inputs are SWITCHING Data bus inputs are
91. water oils chemicals and organic solvents 2 Usage in exposure to direct sunlight or the outdoors or in dusty places 3 Usage involving exposure to significant amounts of corrosive gas including sea air CLo H2S NHs SO and 4 Usage in environments with static electricity or strong electromagnetic waves or radiation 5 Usage in places where dew forms 6 Usage in environments with mechanical vibration impact or stress 7 Usage near heating elements igniters or flammable items If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan Also if you export products technology controlled by U S export control regulations or another country s export control laws or regulations you must follow the necessary procedures in accordance with such laws or regulations If these products technology are sold leased or transferred to a third party or a third party is granted license to use these products that third party must be made aware that they are responsible for compliance with the relevant laws and regulations M01E0706 ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 81
92. ween two consecutive clock cycles tJIT cc Max of tCKj 1 tCKjl tJIT cc is defines the cycle to cycle jitter when the DLL is already locked tJIT cc Ick uses the same definition for cycle to cycle jitter during the DLL locking period only tJIT cc and tJIT cc Ick are not subject to production test 7 tERR nper is defined as the cumulative error across multiple consecutive cycles from tCK avg tERR nper is not subject to production test tERR nper 4 tCKj nxtCK avg j l 2 lt n lt 50 for tERR nper 8 These parameters are specified per their average values however it is understood that the following relationship between the average timing and the absolute instantaneous timing hold at all times minimum and maximum of spec values are to be used for calculations in the table below Parameter Symbol min max Unit Absolute clock period tCK abs tCK avg min tJIT per min tCK avg max tJIT per max ps Absolute clock high pulse tCH abs tCH avg min x tCK avg min tCH avg max x tCK avg max width tJIT duty min tJIT duty max Absolute clock low pulse CL abs tCL avg min x tCK avg min tCL avg max x tCK avg max width tJIT duty min tJIT duty max p Example For DDR2 667 tCH abs min 0 48 x 3000 ps 125ps 1315ps ELPIDA Preliminary Data Sheet E1196E10 Ver 1 0 22 EDE2104ABSE EDE2108ABSE Input Slew Rate Derating For all inpu
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ELPIDA 2G bits DDR2 SDRAM EDE2104ABSE (512M words