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SIEMENS PSB 7230 ICs for Communications handbook

1. Introduction 1 4 Pin Configuration nS aad be no zoafzs 89g90 _pyrege ChKeEMSEVHDOHDFFOHORNOWM oM400H0 QOUotL X0L L xx 50o0mft oooo o SCLK 1 76 cao ALE CD1 CS L CA1 RD vss WR C VDDP AD7 _ CD2 AD6 C CA2 AD5 L CD3 AD4 C CA3 VDDP _ VSS VSS PSB 7230 E VD VDD CD4 AD3 _ CA4 AD2 o CD5 AD1 CA5 ann P TQFP 100 Ed INTR VSS INT _ VDD A2 C CD6 FSC CA6 DCL CD7 DU CA7 DD vss CA15 LL VDD CD15 26 51 I CD8 tO MNN roo at te AB te 2563 25256 GOZO ZO OR SARSRLBR OOF gt SFSO0O0O0OF gt SF5S gt 0000 SF SWN00 00000 Figure 2 Semiconductor Group 9 Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction 1 5 Pin Description Table 1 Parallel Host Interface Pin No Symbol Function Descriptions 16 ADO O Multiplexed Bus Mode Address Data Bus Transfers 15 AD1 lO addresses from the host to JADE and data between the host and the JADE 14 AD2 I O Demultiplexed Bus Mode Data bus Transfers data 13 AD3 O between the host and the JADE 9 AD4 I O 8 AD5 1 O 7 AD6 I O 6 AD7 O 4 DS Data Strobe
2. Semiconductor Group 142 Data Sheet 1998 07 01 SIEMENS PSB 7230 Table 26 Control Status Pipeline for G 723 cont d Firmware Features Packet Control User to Status JADE AN to Comment 10 ms JADE AN User MODE OPT1 Data MODE OPT1 Data Bytes Bytes 22 60 00 0 60 80 8 23 60 00 0 60 88 8 24 60 00 0 60 90 8 25 60 00 0 60 00 8 Part 0 of valid G 723 encoded frame from JADE AN 26 60 00 0 60 08 8 Part 1 of 30 ms frame 27 60 00 0 60 10 8 Part 2 of 30 ms frame 28 60 00 0 60 00 8 Part 0 of 30 ms frame 29 60 00 0 60 08 8 Part 1 of 30 ms frame 30 00 00 0 60 10 8 Part 2 of 30 ms frame Command Neutral Mode 31 00 00 0 60 80 8 Invalid G 723 data from JADE AN internal pipeline 32 00 00 0 60 00 8 Last G 723 encoded data from JADE AN 33 00 00 0 00 00 0 4th neutral packet next can change mode 34 06 00 0 00 00 0 Command G 723 high rate decode 35 06 00 8 00 00 0 Part 0 of valid G 723 encoded frame to JADE AN 36 06 08 8 00 00 0 Part 1 of 30 ms frame 37 06 10 8 06 00 0 Part 2 of 30 ms frame first G 723 decoded data from JADE AN Semiconductor Group 143 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Table 26 Control Status Pipeline for G 723 cont d Packet Control User to Status JADE AN to Comment 10 ms JADE AN User MODE OPT1 Dat
3. Address Demultiplexed Mode Address Multiplexed Mode A0 3 Data DO 7 ADO 7 Data ADO 7 Host Write Host Read Host Write Host Read FF FE reserved reserved FD FC reserved reserved 77y Acknowledge INT MSB 76 Acknowledge INT LSB 75 Interrupt INT Interrupt INT Mask MSB Status MSB 74 Interrupt INT Interrupt INT Mask LSB Status LSB 73 Acknowledge INTR 714 Interrupt Interrupt INTR Mask INTR Status MSB MSB 70 Interrupt Interrupt INTR Mask INTH Status LSB LSB 6C reserved reserved 6A reserved reserved 61 Cntrl Host gt Cntrl DSP gt DSP MSB Host MSB 60 Cntrl Host gt Cntrl DSP gt DSP LSB Host LSB OF OE reseved Semiconductor Group 47 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization Table 12 Address Mapping of Multiplexed Demultiplexed Host Interface cont d Address Demultiplexed Mode Address Multiplexed Mode A0 3 Data DO 7 ADO 7 Data ADO 7 OD 0C reserved 58 INDB LSBit IND Interrupt Status 50 INH Interrupt INHB LSBit Status 4C Mailbox IO Mailbox IO write read 09 Data register Data register 4A Mailbox write address 08 Address Address 48 Mailbox read address register register 07 Interrupt INT Interrupt INT Mask MSB Status MSB 064 Cntrl Host gt Cntrl DSP gt 47 Ext Memory DSP MSB Host MSB Data high 05 Cntrl Host
4. Table 32 Parameter Symbol Limit Values Unit min max Interrupt acknowledge to high impedance fj44 100 ns 7 7 3 IOM 2 Interface Timing IOM 2 PCM Timing with Single Rate DCL lt TP gt TWH gt E TWL gt DCL J j Single rate CD v K TFSS gt lt TFSW gt lt TFSS gt TFSH gt FSC Y Wo 5 ISSN NS CARA RE TODD lt TOZD gt TODZ High impedance n DU DD out Bit 0 of time slot 0 A Bitt TIDS gt lt TIDH gt DU DD in VAAN Btooftime sloto X VU X Bt Figure 66 Semiconductor Group 172 Data Sheet 1998 07 01 SIEMENS PSB 7230 Electrical Specification Table 33 Parameter Symbol Limit Values Unit min max DCL period tp 244 ns DCL high tw 100 ns DCL low twe 100 ns Frame sync setup tess 120 ns Frame sync hold tesy 40 ns Frame sync width tesw 40 ns Output data delay from FSC if fozp lt topp tozp 100 ns Output data delay from DCL if topp lt tozo topp 100 ns Output data from active to high impedance fopz 80 ns Input data setup tips 20 ns Input data hold tow 40 ns IOM 2 Timing with Double Rate DCL DCL EE j oW Double rate FSC uc TODD lt TozD gt ee DU DD out scl Bit 0 of time slot 0 Bit1 TIDS gt lt TIDH DU DD in AJ BiOof mesoto Bit 1 Figure 67 Semiconductor Group 17
5. T IND 3058h 58h INT INDB 1 Interrupt request gt 32h l Acknowledge data transfer l i i Ei Start 4000h 00h n l b l f write compressed l 7 i m a audio packet into Mailbox E E mailbox dr 8 e 1 2 F Eun Backup of Interrupt IND 3061h 61h as VocoderFinished gt C0h E for slow hosts 80h t see text I 1 9 T c i AIRBITUPE request IND 3058h 58h INT INDB 1 t VocoderFinished SICoh i alternating COh 80h i o 80h o compressed audio 8 from JADE to host i E i z l Af ff ya 44 AL 1 L l gt Interrupt i gt Get Interrupt number If COh 80h f check INHB bit If INHB 0 IND 32h has been generated but was missed by the host id t Wee ae ICE do RO NO ee a Figure 51 Semiconductor Group 157 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features In this case the WCB interrupt handshake is finished correctly but the acknowledge interrupt IND 32 may be missed by the host if it is busy at that time because the next VocFin may be generated by the JADE AN before the host is able to recognize the IND 32 interrupt The IND interrupt status register then is overwritten by the VocFin interrupt If the host was busy during the time these two interrupts occured it will afterwards only detect the VocFin interrupt and miss the acknowledge of
6. Out fi Data MX Data 1 Data 1 Data 1 Data2 Data 2 Data 3 Data 3 FF FF i rd I pn as I dis as In i MR LI LI N LI V V aa ene MDR int status MDR int status MER int status MRC 1 Read MONR Read MONR MRC 0 Figure 33 Monitor Channel Data Transfer A hardware model of the Monitor channel is shown below MDR status MER status Mg M 0 lt DSP or Oky MX U s 1 lt B B Load Monitor channel X Se TELE Receive SUN MRE MRC MR strobe MX Cleck Logic VV MR Clock Mg Load MRO UT POSSE 8 Mae 8 bits m ok DD Mon_strabe MONCH Shift Register 4 X de DU DCL 2 gt Mon_Clock Bes MXC Mon_strobe FSC Sy Time slot males lla f Count VS MRE Logic V 8 bits M9 DU MXC gt Shift Register 3 U JAN X 4 DD 8 V bA M O MX_strobe MR_strobe MR_Clock gt MR u MX Clock S X 1 M s Monitor channel MXC MX strobe BOR orp OF Ze Transmission SLIN 9s N Read Logic ea Write AXE Mx yo gt Pa x 1 MDA status MEA status MAB status Figure 34 MRC has to be 1 and MONR has to be read before any new value from the same packet is loaded into MONR Thus while MRC 0 only the first byte of a packet is loaded into MONR Semiconductor Group 73 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks 4 4 2 C I Channel The two C I channels are controlled via the C I Transmit CIX and C I Receive CIR registers the C I channel Enable CIEN and the C I Change CIC interrupt sta
7. Firmware Interface Firmware Hardware Hardware Serial Audio Interface SAI i Host Interface ji IOM 2 Interface L CO Default Configuration Optional Configurations 4 amp 4 J3 Data Exchange lt amp Control Status Combination Compressed SAI and Uncompressed Host not supported Figure 41 The audio interface description is split up into two basic parts In the first part the Firmware Protocol data format data packet size and mode control inband or outband are described Chapter 6 2 1 and Chapter 6 2 2 which are independent of the selected hardware interface combination In the second part the Firmware Interface combinations for uncompressed and compressed audio i e the individual timings and handshake procedures for the selected hardware interface combination are described Chapter 6 2 3 Semiconductor Group 118 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features 6 2 1 Compressed Audio Protocols and Control of JADE AN In the following sections the protocols for the exchange of compressed audio data between the JADE AN and a user are described 6 2 1 1 Outband Control of JADE AN All times that are given in this chapter refer to realtime processing of a 10 ms frame length of the audio data which is the default setting of the JADE AN When doing offline processing compressed and uncompressed data exchanged through the
8. The rising edge marks the end of a valid read or write operation Motorola bus mode RD Read This signal indicates a read operation Siemens Intel bus mode 5 R W Read Write A 1 high identifies a valid host access as a read operation A 0 identifies a valid host access as a write operation Motorola bus mode WR Write This signal indicates a write operation Siemens Intel bus mode 3 CS Chip Select 2 ALE Address Latch Enable A high on this line indicates an address on AD 0 7 multipexed bus mode only ALE also selects the interface mode 82 AO Address Bits A 0 3 demultiplexed bus type 83 A1 19 A2 96 A3 Semiconductor Group 10 Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction Table 1 Parallel Host Interface cont d Pin No Symbol Function Descriptions 17 INTR O OD Interrupt Real time Interrupt output line for high priority interrupt status serial audio receive transmit serial HDLC data receive transmit data to host 18 INT O OD Interrupt Request Interrupt output line for all other interrupt states Table 2 IOM 2 Interface Pin No Symbol Function Descriptions 23 DD l O OD Data Downstream on IOM 2 POM interface 22 DU l O OD Data Upstream on IOM 2 PCM interface 21 DCL l O OD Data Clock Clock frequency is twice the data rate or equal to the data rate 20
9. Unused SDATA 80h 3080h DSP Host Com 40h 3040h 00h 3000h Input Output Figure 13 Not all the addresses in each of these 64 byte areas are used The functions of the register bank are detailed in the following paragraphs Semiconductor Group 35 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization 3 3 Directly Accessible Register Bank 3 3 1 Input Output Registers This area contains the locations for receiving transmitting real time audio and data between the serial interfaces IOM 2 and Serial Audio Interface and the Host or embedded DSP The PSB 7230 implements one receive and one transmit audio channel denoted RC1 and XC1 respectively Further one receive and one transmit channel is provided to access the serial data receiver input data and the serial data transmitter output respectively called HR1 and HX1 Transfer of audio samples is interrupt supported whereby two possibilities are provided interrupt status generated after a programmable number of bits 1 32 have been shifted in out interrupt indicating the start of a physical frame normally at 8 kHz either from FSC RFS or TFS frame sync pulses in this case the number of significant bits depends on the time slot length programmed for that channel on the line DU DD SR ST The interrupt statuses may generate a maskable interrupt on the high priority interrupt lines INTR Host and or INTO e
10. 0 time slot logic can start operation and thus activate a time slot only after the first frame sync pulse is detected i e on FSC RFS or TFS whichever has been selected The time slot offset register TSAX bit XCSO mark the instant when the infinite time slot will be activated after the first frame sync pulse has occurred If TFDIS 1 transmission can start immediately without the necessity to wait for the first frame sync pulse Transmit Frame Sync Disregard When TFDIS is 1 the time slot generation logic disregards frame syncs In particular if TSCO 1 and TFDIS 1 transmit time slot is immediately considered as permanently active and remains activated as long as this condition prevails Semiconductor Group 109 Data Sheet 1998 07 01 SIEMENS PSB 7230 Time Slot Assignment Receive TSAR TSR RCS Time Slot Assignment Transmit TSAX TSX XCS Semiconductor Group 110 Register Description TSAR Read Write Address 28 Bit 7 Bit 0 TSR5 TSR4 TSR3 TSR2 TSR1 TSRO RCS2 RCS1 Time Slot Receive Selects one of up to 64 possible time slots OOh 3F in which data is received TSR gives the location of the time slot in octets granularity 2 octet The bits RCS 2 0 give the exact starting point of the time slot with one bit precision In other words the time slot position with respect to the frame sync is given by TSR x 8 RCS The le
11. EE l Get Interrupt i 2 number and store a pA lt Initialize mailbox f start address 8 4Ch Read compressed E xxh audio from mailbox 9 set INDB 0 S 5 oO E e Initialize mailbox amp 2 l start address 5 4Ch ate Write compressed E i audio into mailbox 5 s i 1 o Interrupt lt INT1 INHB 1 INE E Interrupt request i Acknowledge 8 Get Interrupt compressed audio eB number i from host to JADE Start 4000h 00h read compressed lt audio packet from Mailbox i i mailbox set INHB 0 gt u Start 4000h 00h Write status data l g 1 2 packet into mailbox Mailbox s I set INHB 0 g IND 3058h 58h INT INDB 1 a Interrupt request 34h gt Interrupt 3 status data ready i 7 i l Get Interrupt t i number o Figure 53 Semiconductor Group 161 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features The SR request will be recognized by the JADE AN but not immediately be serviced It is stored in an internal interrupt buffer and the VocFin is handled first as the higher priority interrupt So the host must not wait for the SR request to be serviced but has to be able to recognize a VocFin interrupt from the JADE AN after an SR request The VocFin interrupt then is serviced as usual and only after the corresponding handshake mechanism is finished the SR request is service
12. Figure 22 Timing Generation on SAI Lines Continuous and Burst Mode The uses of these modes are as follows Case 1 When the timing is input or when it is internally generated with TCONT 1 the interface can be used as a general Time Division Multiplex highway with time slots of programmable lengths and locations for audio and data Case 2 When the timing is output with TCONT 0 the interface is typically used to transfer messages or blocks of compressed or uncompressed audio or data preceded by a header of control information pertaining to the transferred data block and synchronous to it The blocks can be received and transmitted using the serial Data Controller An application of this mode of operation is the synchronous transfer of H 221 223 oriented data between the PSB 7230 and an attached VCP Videocodec Audio Channel Transfer As mentioned in Section 3 all the serial channels 1 receive audio 1 transmit audio and one full duplex transparent data channel can be transferred between one of the serial interfaces and the DSP or the host in a flexible manner Semiconductor Group 54 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks The interface to each of the audio channels is a 32 bit wide shift register In receive direction when the shift register is filled to a programmable level up to 32 bits the whole 32 bit shift register is loaded into the receive channel read register set accessible from the D
13. High Priority Interrupts INTR FSC RFS TFS BFUL1 BEMP1 BFHR1 BFHX1 Lower Priority Interrupts INT SAIN SDATA DINT GPI MDR MER MDA MEA MAB CIC1 CIC2 Corresponding interrupt status register exist for the internal DSP The interrupt status registers are physically separate for the Host and for the DSP Thus when an interrupt status is generated the interrupt status bit is set in both registers The interrupt status disappears from the interrupt status register when the cause of the interrupt status is removed by the software or the interrupt is explicitly acknowledged Whenever possible an interrupt status is made to disappear when the cause of that interrupt status is removed example in out audio data channel interrupts in order to spare the explicit writing of an acknowledge register address In other cases the interrupt statuses are explicitely acknowledged by writing a 1 in a virtual acknowledge register The interrupt status bits have individual mask bits which have no influence on the setting of the interrupt status bits but only on the generation of the interrupt on the interrupt line When the mask bit is 0 the generation of the interrupt for the corresponding interrupt status on line INTR or INT is prevented Semiconductor Group 78 Data Sheet 1998 07 01 SIEMENS PSB 7230 5 2 Interrupt Status Registers Register Map for Host Interrupts Host Interrupt Status for INTR Regis
14. In order to cover a wide range of applications the JADE AN offers a variety of different interface combinations and protocols for the uncompressed compressed data exchange The basic interfacing is like in the figure below Compressed Data Uncompressed Data Interface Interface User JAE lt gt Audio Codec d Figure 40 Two interfaces are necessary one for compressed audio connected to a User and one for uncompressed audio connected to a Codec By switching the compressed uncompressed data stream to different hardware interfaces Host IOM Serial Audio Interface the JADE AN is able to support standalone solutions using a video processor compressed data provided on Serial Audio Interface as well as Host systems e g software video coders using the Host Interface for the compressed data or offline audio compression compressed and uncompressed audio exchanged through Host Interface See Figure 41 for the firmware layer structure and the corresponding structure of the description Semiconductor Group 117 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Firmware Layer Structure Encoder Decoder Compression Pass Through Decompression Compressed G 711 Audio Uncompressed Audio G 723 i Raw Uncompressed Data Buffer 16 bit linear Control Status Buffers Block Firmware Protocol
15. Packet end act x I 7 K SIN Latch Latch Latch Latch Rec Rec Rec Rec Data Data Data Data inact m MR act Ack Ack Ack 1st 2nd nth Byte Byte Byte Figure 30 Note For simplification of the diagram the states of MX and MR are shown as 0 or 1 during the entire 125 us frame without regard to the bit positions they actually Occupy Software Handling of Monitor Channel Transmission The idle state of the transmitter is maintained when the MXC Monitor channel Transmit Control bit is 0 In order to transmit the first byte its value is written into the MONX Monitor channel Transmit Register After the MXC bit is set to 1 the Monitor channel hardware sends the byte from MONX and controls the MX bit accordingly MX 1 0 When the hardware detects the acknowledgment from the other end received MR bit 0 it will set the MDA Monitor Data Acknowledged bit When this is detected by the software it writes the next byte in MONX register This byte is sent and the MX bit controlled accordingly The acknowledgment by the other end is again indicated by the MDA status bit This procedure is repeated until all the data is transmitted After the last MDA status the software sets the MXC bit back to 0 and the transmit channel including the MX bit returns to the idle state If an abort request from the receiving end is detected by the hardware the MAB Monitor channel Abort status bit is set In the PSB 7230 the Monitor chann
16. 0 Mis0 O07 w A YP P Pass through mode available 1 or not 0 A G 711 8 KHz sample rate A law coding available u G 711 8 KHz sample rate u law coding available M G 723 8 KHz sample rate MP MLQ 6 3 Kbit s or ACELP 5 3 Kbit s coding available S Symmetry required The JADE AN reports a 1 indicating the standards used for encoding must be the same as for decoding Asymmetry is allowed for neutral mode mixed with any other mode and mixed G 711 A u law i e A law encoder and u law decoder or vice versa C Codec connected to the JADE AN 1 or not 0 Default is 1 3 Mode Status X XIX X X xX x x EM3 EM2 EM1 EMO DM3 DM2 DM1 DMO Report the audio mode or operation as defined in the command mode word above for the data that is in this packet 4 Options Status Ix x P1 PO L2 L1 LO xIx Rel Red Rd1 Rdd led Semiconductor Group 137 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Report the audio mode or operation per the bits as defined in the command options word above for the data in this packet 5 Volume Status EV7 EV6 EV5 EVA EV3 EV2 EV1 EVO DV7 DV6 DV5 DV4 DV3 DV2 DV1 DVO Report the gain on the analog input and output Defined as in the command
17. 2005 SAI Mode SODS SPS DSE SCKIN PRSC9 PRSC8 2006 SCLK PRSC7 PRSC6 PRSC5 PRSC4 PRSC3 PRSC2 PRSC PRSCO Baud Rate 2007 RFS Mode RFIN RCONT RFE RFSEL RFPS RREP9 RREP8 2008 RFSPer RREP7 RREP6 RREP5 RPRD4 RPRD3 RPRD2 RPRD1 RPRDO Rep Rate RREP4 RREP3 RREP2 RREP1 RREPO 2009 TFS Mode TFIN TCONT TFE TFSEL TFPS TREP9 TREP8 200A TFS Per TREP7 TREP6 TREP5 TPRD4 TPRD3 TPRD2 TPRD1 TPRDO Rep Rate TREP4 TREP3 TREP2 TREP1 TREPO 200B SIO Config SAIO SOUT SINTC 200 0 0 0 0 0 0 0 200D 0 0 0 0 0 0 0 0 200E 0 0 0 0 0 0 0 200F 0 0 0 0 0 0 0 0 2010 Data Cntr HAH1 0 Access 20114 Rec Audio EN SLIN1 SLINO LEN4 LEN3 LEN2 LEN1 LENO Ch1 Cfg 2012 Rec Audio TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 Chi TS 2013 Rec Audio TSO LMOD LBIT4 LBIT3 LBIT2 LBIT1 LBITO Ch1 Mode 2014 0 0 0 0 0 0 0 0 2015 0 0 0 0 0 0 0 0 2016 0 0 0 0 0 0 0 2017 Tx Audio EN SLIN1 SLINO LEN4 LEN3 LEN2 LEN1 LENO Ch1 Cfg 2018 Tx Audio TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 Chi TS Semiconductor Group 82 Data Sheet 1998 07 01 SIEMENS PSB 7230 Table 15 Summary cont d Register Description Addr Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name 2019 Tx Audio TSO LMOD LBIT4 LBIT3 LBIT2 LBIT1 LBIT
18. The strobe signals of all audio receivers and transmitters connected tp SR and ST line will be combined by logical OR RFS polarity select 0 Rising edge marks the beginning of a new frame on the RFS line 1 Falling edge marks the beginning of a new frame on the RFS line If RFS is an output it is inverted vs RFPS 0 Period of RFS pulse generation Number of repetition of pulses When RCONT 0 RREP 9 0 gives the number of pulses RREP 1 to be generated spaced 16 bits apart up to 1024 pulses When RCONT 1 RPRD 4 0 gives the spacing of continuously generated pulses in 16 bit word increments up to 32 TFS In 0 TFS is an input 1 TFS is output Continuous generation of TFS pulses 0 A number of pulses Spaced 16 bit periods from each other equal to TREP 1 1 1024 is generated upon an STX command see serial data controller register description 1 When ETFS bit is 1 see serial data controller register description continuous pulses on TFS are generated spaced TPRD 1 1 32 16 bit words from each other Semiconductor Group 89 Data Sheet 1998 07 01 SIEMENS PSB 7230 TEE TFSEL TFPS TPRD 4 0 TREP 9 0 Register Description TFS Clock Edge 0 When TFS is generated by the PSB 7238 output it changes its state at the rising edge of the SCLK clock 1 When TFS is generated by the PSB 7238 output it changes its state at the falling edge of the SCLK clock Transmit Fr
19. and the DSP is interrupt supported via a full duplex 64 byte on chip Communication Memory Mailbox Semiconductor Group 24 Data Sheet 1998 07 01 SIEMENS PSB 7230 General Architecture and Functions One receive and one transmit audio channel are provided They are input output on the ISDN Oriented Modular IOM 2 or the Serial Audio Interface SAI interfaces in individually programmable time slots These channels are accessed from the DSP and or the Parallel Host Interface The Serial Data Controller channels can be serviced by the DSP or the Parallel Host Interface The serial data for the serial data controller is located in programmable time slots on IOM 2 and or SAI Semiconductor Group 25 Data Sheet 1998 07 01 SIEMENS PSB 7230 General Architecture and Functions 2 2 Functions 2 3 Summary of the Functions The main functions implemented by the PSB 7230 are G 723 V5 1 Compression Decompression 6 3 5 3 Kbit s G 711 Compression Decompression 64 Kbit s Accepts outputs uncompressed audio 8 bit PCM A u law or 16 bit linear format Uncompressed compressed audio switchable between different interface combinations IOM Serial Audio Interface IOM Host Host Host nband controlled H 221 H 223 oriented audio protocol e g for direct serial connection to Videocodec VCP of 8 x 8 Inc formerly IIT Inc Outband controlled audio protocol with optimized data rate Stable reaction on interr
20. 203F the host writes in the Data register the data byte to be written and in the Address register the write command Bit 7 Bit 0 0 0 A5 A4 A3 A2 A1 AO where A 5 0 gives the offset of the register to be written This causes an RACC Register Access interrupt status to the DSP The DSP software transfers the Data byte to the requested address 2000 A 5 0 and writes the RDY bit least significant bit of address 40 3040 to 1 again which was set to O by hardware at the time of writing of the Address register By sensing the state of bit RDY the host is able to start a new access to Address and Data registers when the DSP is ready For reading a Configuration Control register addresses 2000 203F the host writes in the Address register the read command Bit 7 Bit 0 1 0 A5 A4 A3 A2 A1 AO where A 5 0 gives the offset of the register to be read This causes a RACC Register Access interrupt status to the DSP The DSP software transfers the contents of the requested address 2000 A 5 0 into the Data register and writes the RDY bit to 1 Semiconductor Group 77 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description 5 Register Description 5 1 Interrupt Structure As explained in Section 3 the interrupt statuses are grouped on two interrupt lines high priority and low priority interrupts respectively They are
21. 3 Set options 4 Set volume 5 7 Reserved for future expansion 8 Compressed data 0 4 40 or 80 words 1 word 16 bit The header of the command data packet describes the JADE AN operation modes in effect for data in the next packet See Section Commands below for a detailed description of the above command words The packet that is transferred from the JADE AN to the video processor called status data consists of eight status words followed by the appropriate number of data words for the current speech algorithm Table 21 Status Data Structure Status header word Capabilities Mode status Options status Volume satus Error conditions ojoc1 5 c nrn o 7 Reserved for future expansion 8 Compressed data 0 4 40 or 80 words 1 word 16 bit The compressed data is between 0 and 80 words long depending on which of the decoding encoding modes is active neutral G 723 G 711 or 8KHz samples pass through The most significant byte of a word is received transmitted first The G 723 compressed data framing is identical with the outband controlled mode see Section 6 2 1 2 for details A header bit can indicate that the current compressed data is invalid This means that it is not decoded and instead the sound from a previous packet is repeated By that a simple interpolation of the speech signal is achieved to avoid an audible click The size of the command and data packets
22. Group 139 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Table 25 Control Status Pipeline for G 711 Identical for Pass Through cont d Packet Control User Status JADE AN Comment 10 ms to JADE AN to User MODE OPT1 Data MODE OPT1 Data Bytes Bytes 14 33 05 80 33 05 80 First G 711 u law en decoded data from JADE AN 15 33 05 80 33 05 80 16 00 00 80 33 05 80 Command Neutral Mode last G 711 data to JADE AN 17 00 00 0 33 05 80 18 00 00 0 33 05 80 Last G 711 u law en decoded data from JADE AN 19 00 00 0 00 00 0 4th neutral packet next can change mode 20 02 00 0 00 00 0 Command G 711 A law decoder only 21 02 00 80 00 00 0 First G 711 A law encoded data to JADE AN 22 02 00 80 00 00 0 23 02 00 80 02 00 0 First G 711 A law decoded data from JADE AN 24 02 00 80 02 00 0 25 00 00 80 02 00 0 Command Neutral Mode last G 711 data to JADE AN 26 00 00 0 02 00 0 27 00 00 0 02 00 0 Last G 711 A law decoded data from JADE AN 28 00 00 0 00 00 0 4th neutral packet next can change mode The pipelining is identical for the 8 kHz pass through mode Semiconductor Group 140 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features In G 723 the natural frame length of 30 ms is split up into three 10 ms packets to fit into the interface structure of the other audio modes These packets
23. H 323 standalone videophone solution for analog telephone line PAL NTSC Camera ACE Acoustic ARCOFI BA Echo Canceller Video SIEMENS SIEMENS Capture PSB 2170 PSB 2161 Video out ALIS tip rin SADEAN SIEMENS R PSB 4595 SIEMENS PSB 4596 PSB 7230 ISAR 34 SIEMENS PSB 7115 Keyboard Figure 7 Compared to a PCI plug in card a microcontroller keypad and screen need to be added for a standalone videophone The initialization and keyboard control is done by the microcontroller It substitutes the tasks of the host processor in the previous examples The screen e g standard CCD device is connected directly to the video codec via a 3 DAC The multiplexing of the video and audio bitstreams H 223 or H 225 can be either done by the video codec or the microcontroller Semiconductor Group 21 Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction The other components are already known from the previous examples so please refer to the above descriptions for details 1 6 5 Internet Telephone Access in Line Card Figure 8 shows an internet telephone access implemented in an analog line card of a common tip ring line There is no need for the user to buy a special internet telephone With his old equipment he can use the internet for rate reduced calls to overseas or to connect to a true internet telephone At the beginning or even before a new call the user may select between the standar
24. Handshake 2 3 Uncompressed Audio M ee ree Host Jade DSP Start 4000h 00h write uncompr audio 2 5ms into gt Mailbox mailbox set INHB 0 i IND 3058h 58h INT INDB 1 A fanc gt 03h gt Interrupt cknowledge uncompr audio Get Interrupt from JADE to host number pA lt Initialize mailbox start address ach Read uncompr xxh i audio from mailbox set INDB 0 oni Initialize mailbox start address ach lt Write uncompr l i audio into mailbox INT1 INHB 1 INH 3050h 50h Interrupt 02h gcn ae Get Interrupt i uncompr audio number from host to JADE Start 4000h 00h read uncompr audio packet from Mailbox mailbox Figure 48 The following steps are executed Semiconductor Group 149 Data Sheet 1998 07 01 SIEMENS PSB 7230 6 Firmware Features The JADE writes a packet of uncompressed audio 2 5 ms into the mailbox most significant byte first The JADE generates an interrupt at INT line to the host by writing a value 03 into IND interrupt status register at address 58 This interrupt acknowledges the previous INH interrupt either from the compressed data transfer or from the last uncompressed data transfer and requests the current uncompressed data exchange The host reads the uncompressed audio from the mailbox using the procedure described in Section 3 4 and may reset the INDB bit The reset of the INDB bit
25. SIEMENS PSB 7230 Electrical Specification 7 7 4 Serial Audio Interface Timing Serial Clock T TP TWH l lt WM SCLK in a N Figure 70 Table 37 Parameter Symbol Limit Values Unit min max SCLK period tp 244 ns SCLK high two 100 ns SCLK low twee 100 ns Serial Output Timing SCLK lt TFSS gt lt TFSH gt E TFSS gt TFSH gt TFS RFS in y d lt TODD gt lt TODZ gt High impedance y Vr ST SR out Bit 0 of time slot 0 A Biti Figure 71 Semiconductor Group 176 Data Sheet 1998 07 01 SIEMENS PSB 7230 Electrical Specification Table 38 Parameter Symbol Limit Values Unit min max TFS RFS setup tess 40 ns TFS RFS hold tesy 40 ns Output data delay from clock topp 100 ns Output data from active to high impedance topz 80 ns Serial Input Timing k N y 1 N lt TFSS gt lt TFSH TFSS I TFSH TFS RFS in i N SCLK TIDS gt lt TIDH ST SR out AAA AAAA A Bit 0 of time slot 0 in NC Bu Figure 72 Table 39 Parameter Symbol Limit Values Unit min max TFS RFS setup tess 40 ns TFS RFS hold tesy 40 ns Input data setup tips 20 ns Input data hold tio 40 ns Semiconductor Group 177 Data Sheet 1998 07 01 SIEMENS PSB 7230 TFS RFS Output Timing Electr
26. SIEMENS PSB 7230 Interfaces and Memory Organization The external memory interface implements protection against reading the internal ROM 3 1 5 Clock Interface The chip internal clock is derived from a crystal connected across XTAL1 2 or from an external clock input via pin XTAL1 Two different clock options are provided controlled by the clock mode pin CM1 These clock modes are CM1 0 The internal clock circuitry generates a frequency 4 5 times the input on XTAL1 2 The internal frequency required is 34 56 MHz and is obtained by providing a frequency of 7 68 MHz on XTAL1 input CM 1 The internal frequency is directly input via XTAL1 2 When using a crystal a 34 56 MHz crystal swinging at its basic harmonic has to be connected to XTAL1 2 After reset the pin CLKO outputs a frequency of 7 68 MHz independent of the selection of CM1 bit Alternatively CLKO can be programmed to output the frequency of a programmable divider CKOS bit in register 2002 Thus a clock of frequency equal to the internal clock divided by a programmable baud rate factor 1 2 3 2 can be generated When using the PLL CM1 0 itis made sure that during reset phase CLKO delivers a continuous 7 68 MHz clock When using the non PLL mode CM1 1 CLKO goes low while reset phase Semiconductor Group 33 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization 3 2 Shared Memories Note The absolute addr
27. Semiconductor Group TB Data Sheet 1998 07 01 SIEMENS PSB 7230 C I Channel Data Transfer The block diagram of the C I channel handler is shown below Functional Blocks x CIC intstatus Read PSP or Host road CIR n a N CIL CICH DLL Mee re Previous SLIN Current e A Time slot Bbits f m lt DD DCL 2 Clock a i p p Count gt Shift Register U Logic X 14E pu il 6 bits eT 2 gt Shift Register 20 M gt u CIEN Strobe Le U i Load Gls 0 H x X 4 DD T6 A AC CIX AA yi AWK SLIN CIEN Strobe AWK DSP or Host Figure 36 Read of the old changed value is the condition of loading of a new changed value Thus when several changes occur before the first changed value has been read only the first and the last change are available Semiconductor Group 76 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks 4 5 Programming Indirectly Accessible Registers Registers in the memory mapped DSP X data RAM area from 2000 upwards are read and written via the Parallel Host Interface by using two registers Conf Cont Reg Address Register at address 40 3040 and Conf Control Reg Data Register at address 41 3041 4 5 1 Programming via Parallel Host Interface see also Section 3 3 2 For writing a Configuration Control register addresses 2000
28. TFDIS Register Description Receive Time slot Continuous When RSCO is equal to one the time slot capacity normally given by register RCCR between 1 and 256 bits is infinity This means that the time slot will be always active so that data can be permanently received if RAC 1 If RFDIS 0 and if the time slot count logic has been reset by issuing RRES while RAC 0 time slot logic can start operation and thus activate atime slot only after the first frame sync pulse is detected i e on FSC RFS or TFS whichever has been selected The time slot offset register TSAR bit RCSO mark the instant when the infinite time slot will be activated after the first frame sync pulse has occurred If RFDIS 1 reception can start immediately without the necessity to wait for the first frame sync pulse Receive Frame Sync Disregard When RFDIS is 1 the time slot generation logic disregards frame syncs In particular if RSCO 1 and RFDIS 1 receive time slot is immediately considered as permanently active and remains activated as long as this condition prevails Transmit Time slot Continuous When TSCO is equal to one the time slot capacity normally given by register XCCR between 1 and 256 bits is infinity This means that the time slot will be always active so that data can be permanently transmitted if XAC 1 If TFDIS 0 and if the time slot count logic has been reset by issuing XRES while XAC
29. and transmitters to either SR or ST line are combined by logical OR and ANDed with internal SCLK Serial Clock In 0 SCLK is an input 1 SCLK is an output Prescaler SCLK is derived from the DSP clock by division through PRSC 1 1 to 1024 RFS In 0 RFS is an input 1 RFS is an output Continuous generation of RFS pulses 0 A number of pulses Spaced 16 bit periods from each other equal to RREP 1 1 1024 is generated upon an STR command see serial data controller register description 1 When ERFS bit is 1 see serial data controller register description continuous pulses on RFS are generated spaced RPRD 1 1 32 16 bit words from each other Semiconductor Group 88 Data Sheet 1998 07 01 SIEMENS PSB 7230 RFE RFSEL REPS RPRD 4 0 RREP 9 0 TFIN TCONT Register Description RFS Clock Edge 0 When RFS is generated by the PSB 7238 output it changes its state at the rising edge of the SCLK clock 1 When RFS is generated by the PSB 7238 output it changes its state at the falling edge of the SCLK clock Receive Frame Sync Select only valid if RFS is output in both cases the polarity is selected by RFPS 0 Single cycle RFS is generated 1 The data strobe is output on RFS pin This only affects the RFS pin the internal frame sync is generated and is input to the timeslot count logic of the audio receivers and transmitters connected to SR and ST line as in case RFSEL 0
30. available options for data unit sizes when pre postprocessing data are 1 2 or 4 bytes bit 31 2423 1615 87 0 LS bits of address Host 11b 10b 01b 00b Y 1st bit transmitted Data Receive and bt 34 1615 received Transmit Registers LS bits of address DSP 10b 00b lt Alignment for 1 byte Write Alignment for 2 bytes Shift out Allgnment for 4 bytes Ss Alignment for 1 byte Shift in EN Read Alignment for 2 bytes Shift in Allgnment for 4 bytes Shift in Figure 16 Semiconductor Group 38 Data Sheet 1998 07 01 PSB 7230 SIEMENS Interfaces and Memory Organization 3 3 2 DSP Host Com Area The DSP Host communication area contains the registers to support hardware and software interrupts and special purpose registers that support communication between the embedded DSP and the Host in particular for indirect programming of the Configuration and Control registers from the host see Figure 16 3 3 2 1 Access to DSP Host Com Area The address mapping in multiplexed mode is given in Table 10 Table 10 Address Mapping of DSP Host Com Area Multiplexed Mode DSP DSP Write DSP Read Host Host Write Host Read Address always always 16 Address always 8bit always 8bit 16bit wide bit wide ADO 7 wide wide FF FE reserved reserved FD FC reserved reserved 77y Acknowled
31. correctly clocked out see Figure 20 For CRS 0 0 divide by 2 DCL CRS 1 pass through V d E WV 77 Phase Detection FSC Circuit and 2 gt DCL 2 When FSC is first detected high DCL 2 must be high MN poe 27 c i Figure 20 CLKO After reset the auxiliary clock output CLKO outputs a frequency of 7 68 MHz independent of the selection of CM1 bit Alternatively CLKO can be programmed via CKOS bit in register 2002 to output a frequency obtained from the DSP clock via a programmable baud rate generator baud rate factor 1 2 3 219 The wide range for the division factor for the CLKO output allows also for the possibility to use it as a time marker period on the order of 10 ms to synchronize another device to the PSB 7230 time base When using the PLL CM1 0 itis made sure that during reset phase CLKO delivers a continuous 7 68 MHz clock When using the non PLL mode CM1 1 CLKO goes low while reset phase Semiconductor Group 51 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks 4 2 Audio and Data Reception Transmission The PSB 7230 supports a total of four independent serial l O channels one receive and one transmit audio channel and one receive and one transmit data channel pertaining to the serial Data controller The four channels are transferred between the DSP and or the
32. frame sync 0 511 LMOD Load Mode 0 Sample of length LEN 1 loaded into read register from frame 1 at the occurrence of frame sync 1 LBIT 1 x LEN 1 bits are loaded into read register when ready for software to be accessed via a Buffer Full interrupt status LBIT 4 0 Load Bits Number of bits in aggregates of LEN 1 loaded into read register when ready if LMOD 1 The number of bits loaded is equal to LBIT 1 x LEN 1 the corresponding interrupt status is BFUL1 Since the number of bits is 32 maximum the value of the product LBIT 1 x LEN 1 shall not exceed 32 Semiconductor Group 92 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Transmit Audio Channel 1 Read Write Address 2017 2019 Value after reset 00 EN Enable If inactive 0 no clock is generated for this channel and the channel is in high impedance must be set to 0 during configuration of transmit audio channel 1 SLIN 1 0 Select Line 00 Channel time slot on DU 01 Channel time slot on DD frame sync FSC clock DCL or DCL 2 frame sync FSC clock DCL or DCL 2 frame sync RFS clock SCLK 10 Channel time slot on SR 11 Channel time slot on ST frame sync TFS clock SCLK LEN 4 0 Length of channel time slot Channel time slot length in bits LEN 1 1 32 bits TS 8 0 Time slot position Position of first bit of time slot from frame sync 0 511 LMOD Load Mod
33. has the following structure MSB LSB CTRL PSEL ISEL1 ISELO FLEN 0 0 0 1 UDF 0 0 0 UDF1 UDFO 0 1 0 G723C HP723 PF723 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE EM3 EM2 EM1 EMO DM3 DM2 DM1 DMO OPTI 0 o pi po w m bo OPT2 0 0 Re1 Red Rd1 RdO e d EVOL EV7 EV6 EV5 EVA EV3 EV2 EV1 EVO DVOL DV7 DV6 DV5 DV4 DV3 DV2 DV1 DVO Note Unless otherwise indicated the host has to switch the MODE to neutral for at least 3 frames default 30 ms before it can change the control block Only the underlined bits may also be changed on the fly disregarding that rule After Reset the JADE AN is automatically in the neutral mode so changes to the control block can be done immediately after the JADE has finished its initialization phase see Section 6 2 3 Semiconductor Group 123 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Mailbox Address 00 Value after reset C1 CTRL PSEL ISEL 1 0 FLEN MSB LSB PSEL ISEL1 ISELO FLEN 0 0 0 1 Protocol Select 0 1 Outband controlled protocol selected see Current Section Inband controlled protocol selected see Section 6 2 1 3 Interface Select 00 01 10 11 Uncompressed audio Host IF Compressed data Host IF Uncompressed audio IOM IF Compressed data Host IF Uncompressed audio IOM IF Compressed data Serial Audio I
34. host the delay times in this chapter have to be substituted by the corresponding number of frames For example a delay time of 30 ms corresponds to three frames of audio data exchange when doing offline processing The host may change the JADE AN operating mode by sending a command block and the JADE AN will send back a status block if requested by the host Command and status blocks consist of 8 bit words To exchange command and status blocks the host initiates an interrupt handshake procedure See Figure 42 for the host writing a new control block to the JADE AN Semiconductor Group 119 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Write JADE Control Block TOPIC debe fe get eh ek Reka See eek ese os Host Jade 4Ah DEIN Initialize mailbox i 00h j lt l start address l 4Ch lt Write new control ERR block into mailbox Interrupt INT 1 INHB 1 ET ome Interrupt request i i for control block Get Interrupt lt write i number l Start 4000h 00h Read control block from mailbox lt Mailbox i set INHB 0 i IND 3058h 58h INT INDB 1 Interrupt request 32h l gt Interrupt l Acknowledge data transfer gt Get Interrupt i number set INDB 0 not mandatory Figure 42 The following steps are executed 1 The host writes new control block into JADE mailbox
35. if present thereafter Monitor Channel Transmit Receive Register Read Write Address 2024 Value after reset 00 MONX Monitor Transmit Register write Value of Monitor byte to be transmitted MONR Monitor Receive Register read Value of received Monitor Channel byte A read of this register enables the automatic acknowledgement of the received byte Semiconductor Group 96 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description C I Channel Mode Register Read Write Address 2025 Value after reset 00 CIEN1 2 C I Channel 1 2 Enable 0 Transmission of C I channel disabled channel in high impedance Transmission of C I channel enabled When CIEN is changed the change takes effect only after the next rising edge of FSC is detected in order to prevent sending an illegal code in the C I channel One should avoid changing the state of CIEN just when a rising edge on FSC is expected AWK1 2 Awake for C I channel 1 2 0 C I channel normal operation Ie A low is unconditionally sent on the line programmed for C I transmit channel When AWK is set to 1 the line DD or DU is immediately pulled low non synchronously with clock When AWK is set to 0 the line is set free only after the next rising edge of FSC is detected One should avoid setting AWK to 0 just when a rising edge on FSC is expected C I Channel 1 2 Configuration Registers Read Write Address 2026 2027 Value afte
36. is ee ce es PC ade Mi Initialize 60h register with O e Initialize 61h register with O Interrupt lt INT1 INHB 1 Ne ene Interrupt request for status data i Get Interrupt lt i number Set INHB 0 IND 3058h 58h INT INDB 1 Interrupt request 43h l gt Interrupt Acknowledge software reset gt Get Interrupt number lt set INDB 0 i not mandatory Restart internal firmware Figure 39 Semiconductor Group 115 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features The following steps are executed The host initializes the control registers 60 and 61 by writing a O into it 2 The host generates an interrupt to the JADE by writing value 12 into INH interrupt status register at address 50 3 The JADE resets the INHB bit and acknowledges the reception by generating an interrupt at INT line to the host by writing a value 13 into IND interrupt status register at address 58 4 The host may reset the INDB as a reaction to the JADE interrupt This step is not mandatory and may be skipped 5 The JADE restarts its internal firmware beginning with the initialization phase For the restart of the internal firmware the JADE AN needs the same initialization time like after a hardware reset So the user should wait for 10 ms before it accesses the JADE AN again 6 1 3 Power Down Command In case the JADE is not currently needed in the system the device can be p
37. is implemented in software Procedure from Host to DSP example a Host Write Mailbox 1 to 256 bytes if free released by DSP Write word in Control register 60 61 e g number of bytes in Mailbox Write 8 bit vector in INH Internally this causes an INT1 interrupt to DSP which recognizes a soft interrupt firmware DSP Services INT1 and Acknowledges by Writing an 8 bit Vector in IND Host Read IND Jump into routine pointed to by IND Mailbox release Write further data etc 3 4 1 DSP Host Com Area with a Demultiplexed Host Interface The DSP host communication area contains the registers to support hardware and software interrupts and special purpose registers that support communication between the embedded DSP and the host In demultiplexed mode data are available on pins on pins AD 0 7 whereas the address is supplied on pins A 0 3 This mode gives an additional and more microprocessor like way of accessing the DSP Host Com Area The most important registers are accessible via 3 address pins only and by the use of an additional pin A3 it is possible to access the complete range of the DSP Host Com Area The address mapping versus the multiplexed host interface is given in Table 12 Semiconductor Group 46 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization Table 12 Address Mapping of Multiplexed Demultiplexed Host Interface
38. of 10 13 is read Reset when HXH1 any of 14 174 is read Host Interrupt for INT 75 74 SAIN DINT SDATA MDR MER MDA MEA MAB GPI CIC1 CIC2 Bit 7 Bit 0 0 0 0 SAIN DINT SDATA 0 Bit 7 Bit 0 MDR MER MDA MEA MAB GPI CIC1 CIC2 Serial Audio Input Interrupt from SIO line Software interrupt from DSP Interrupt from serial data Controller Monitor Channel Data Received Monitor Channel End of Reception Monitor Channel Data Acknowledged Monitor End of Acknowledgment Monitor Channel Abort Request General Purpose Interrupt occured C I Channel 1 Change C I Channel 2 Change Semiconductor Group 80 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interrupt Status Mask Register Register Description Bit 7 Bit 0 754 SAIN DINT SDATA Bit 7 Bit 0 74 MDR MER MDA MEA MAB GPI CIC1 CIC2 A O in a bit position masks the corresponding interrupt default value i e after Reset The mask bit affects only the generation of the interrupt but not the interrupt status bit from being set Undocumented mask bits must be always set to 0 Acknowledge Register 77 Bit 7 Bit 0 SAIN Bit 7 Bit 0 MDA MEA MAB 76 MER The interrupt status bit is reset when the host writes a 1 in the correspondi
39. only by the host 256 half Host I O write words gt DSP read 256 half Host I O read N wards N DSP write Implementation as two separate memories with separate read write buses Figure 17 Since the two memories are totally independent data transfer from host to DSP can take place simultaneously with data transfer from DSP to host full duplex operation The Mailbox is seen from the host as an I O device Thus to read or write a byte in the Mailbox the host accesses a single location separate for read and for write Mailbox The address is given by an address register directly programmable by the host This address is autoincremented every time an access by the host to the Mailbox I O address is performed Thus for sequential fast access the Mailbox is seen as a 256 byte full duplex FIFO For random accesses to the Mailbox the Host has to reprogram the address register s This is summarized in Figure 18 Semiconductor Group 44 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization DSP i Address Host I O write Address red als MSB LSB JL 40FFh ie 4Ch Data gt 4Ah gt Write address Unused DSP Host Hest read Mailbox 4Ch Data 48h gt Read address 4000h 256 Half Words Figure 18 l O Access From the Host to the Mailbox Summary Read Host programs the desired start address 00
40. rate u law encoding decoding G 723 8 kHz sample rate MP MLQ 6 3 Kbit s or ACELP 5 3 Kbit s coding OJJ Pm 4 Set Options Plc P1 PO L2 L1 LO xIx Rel Red Rd1 Rdd led d decoding mute enable 1 and disable 0 After switching a ramping function is implemented to avoid audible clicks e encoding mute enable 1 and disable 0 After switching a ramping function is implemented to avoid audible clicks Re 1 0 When the encode mode is G 723 the Re bits give the desired encoding Rd 1 0 method 00 high rate don t use silence suppression 01 high rate use silence suppression 10 low rate don t use silence suppresion 11 low rate use silence suppression Hd is the same as the above but indicates the mode of the data in this packet It is the same as the corresponding bits of the G 723 packet data Semiconductor Group 135 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features L 2 0 Loopback modes used for testing the audio subsystem The following loops are implemented 000 No loopback default 001 Send received compressed data back to the user as encode data 010 Encode the decoded user data 011 Reserved 100 Reserved 101 Decode the encoded audio input data 110 Send the digital ADC output to the DAC input 111 Reserved P 1 0 Part number of the data in this packet Allows the natural period of the data to be 10 to 40 ms For G 723
41. t d aded 32 3 1 4 External Memory Interface vss y sua nee ean eo x C XR ws 32 3 1 5 Clock Interface oto kam E EEE SD mex Mate OLE 33 3 2 Shared Membotles onware anen Ea a im ck DNE kw des 34 3 3 Directly Accessible Register Bank 2000000 ee eee 36 3 3 1 Input Output Registers 22 03 Motus ete eee eee cae eet 36 3 3 2 DSP plost COM ATea acute casket rape ea meets ete xia D 39 3 3 2 1 Access to DSP Host Com Area 0 000 ees 39 3 4 Mailbox iudiueosie en rec ach e Sat ducet apu eels Mich ie aaa 44 3 4 1 DSP Host Com Area with a Demultiplexed Host Interface 46 4 Functional Blocks vss cce SEA COE aR eNOS Ga hae DRE 49 4 1 Oscillator and Baud Rate Generator 000 cece eee eee 49 4 2 Audio and Data Reception Transmission 2 00000e sees 52 4 3 Serial Data Controller icu han bases cedaetsGeeken eis eseet 64 4 4 lOM Z FUNCUONS gt ces tS eee AES ES d Reus d hu RES e eR 67 4 4 1 Monitor Channel Protocol lt 2 cese RR E EEEAVE be eens Sweet 68 4 4 2 CACHAN winor rottaa oe eat eee ten itus d S be EO A m Sn e 74 4 5 Programming Indirectly Accessible Registers sss 77 4 5 1 Programming via Parallel Host Interface 0 000 eee 77 Semiconductor Group 3 Data Sheet 1998 07 01 SIEMENS PSB 7230 Table of Contents Page 5 Register Description 00 00 ee 78 5 1 Interrupt Structure ME DE aca oe ee es Da ee a 78 5 2 Interrupt Status Registers 1x v
42. the WCB To handle this situation the host should have an internal status register indicating an outstanding acknowledge interrupt In case a VocFin is detected and an acknowledge interrupt is outstanding the host has to check the INHB bit As shown in the figure above the INHB bit is reset in the WCB acknowledge procedure see bold text If the host detects INHB 0 the WCB interrupt has been acknowledged but the host has missed the IND 32 interrupt If the host detects INHB 1 the WCB interrupt has not yet been serviced and will be serviced later For this case see also the conflict situation below 2 Write JADE Control Block Conflict with VocoderFinished Case 2 Another critical situation for the host may occur when a Write JADE Control Block WCB interrupt handshake is started in parallel with with the new VocoderFinished interrupt of the new time frame See Figure 52 Semiconductor Group 158 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Write Control VocoderFinished Conflict 2 CEE PELE EEE oats og E AE Ge te eat tens ae es Host Jade DSP aie 2 2 Start 4000h 00h i write compressed m i p audio packet into Mailbox E mailbox e 1 i E Backup of Interrupt IND 3061h 61h e j Initi
43. to FF into address register 484 Loop A read access from Host to 4C gives the data from the current location in the read Mailbox pointed to by the address register in 484 The address register is autoincremented Go to Loop Write Host programs the desired start address 00 to FF into address register 4A Loop A write access from Host to 4C writes the data into the current location in the write Mailbox pointed to by the address register in 4A The address register is autoincremented Go to Loop In the case of overflow the address register 484 or 4A wraps around to 00 Software Handling of Communication via Mailbox To indicate that data is ready to be read by the host DSP the DSP host may use a general purpose 8 bit interrupt register located in the Host DSP Comm section of the Directly Accessible Register Bank DARB associated with a 16 bit soft command and status word in the same area This protocol is implemented in software The same applies for indicating to the host DSP that data has been read in other words the memory in one direction is free See Example below for using the Mailbox involving a handshake protocol between the DSP and the Host Semiconductor Group 45 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization Simultaneous read write is not prohibited by hardware but a handshake mechanism via IND INH software interrupt registers with optional Control Data
44. value is read by the DSP the latest changed value is loaded in CIR and a CIC interrupt status is generated anew Any possible changes that occurred between the first and the latest are thus lost Semiconductor Group 74 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks With Double Last Look A change in received C I is recognized after a new value is detected in two consecutive frames This is shown in Figure 35 DSP DSP read TUR Int Status 4 CIR i Logic Eoad j 7 Old Confirmed 5 Compare I I I I j I I 1 I I I I I f Load if equal zd X 1 AN 1 l l I I I l I I I I I l I Confirmed Load if not equal Previous eS Compare Current C I Shift In Figure 35 Algorithm Current is compared to Previous f they are not equal Current is loaded into Previous and a new comparison is performed in the next frame No further actions are taken f they are equal the new value takes the place of Confirmed Confirmed is compared to Old Confirmed If they are equal no actions are taken If they are not equal Confirmed is copied to Old Confirmed If CIR register has been read Old Confirmed is compared to CIR If they are equal no actions are taken f they are not equal Old Confirmed is copied to CIR and a CIC interrupt status is generated
45. 0 to indicate that it is ready to accept a new interrupt from the DSP The 16 bit Control register located at 60 61 3060 3061 may contain additional information for the host to read after an IND interrupt Please refer to the specific interface procedures for details Registers for Accessing the External Memory In normal operation the program bus of the DSP is connected via the external memory interface to the external memory bus so that instructions are fetched from an external memory when an address between 8000 and FFFF is hit if EA High If EA Low the whole address range is for off chip programs If the bit LDMEM see description of Configuration and Control Registers Chapter 5 3 is set to 1 and bit DACC is 0 see description of Configuration and Control Registers Chapter 5 3 the external memory interface address and data buses are connected to the outputs of registers address low high at host address 44 45 and data low high at host address 46 47 respectively This feature can be used to down load programs into a memory connected to the PSB 7230 When a write access to the data high register address 47 is detected this activates the external memory interface write signal CWR for the duration of the host WR signal independent of any possible wait states in NRW 3 0 Semiconductor Group 42 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization Registers Pertai
46. 1 The JADE writes one frame of encoded audio data into the mailbox most significant byte first 2 The JADE generates a VocoderFinished interrupt at INT line to the host by writing a value COh or 80 toggling into IND interrupt status register at address 58 The value of this interrupt is each time toggling between CO and 80 to ensure that a polling host can consider a new VocoderFinished For an interrupt driven host one should just connect both numbers to the same interrupt service routine 3 The host reads the compressed audio frame from the mailbox using the procedure described in Section 3 4 and may reset the INDB bit The reset of the INDB bit is not mandatory and may be skipped 4 The host writes the compressed audio frame for the decoder into the mailbox using the procedure described in Section 3 4 5 The host generates an interrupt to the JADE by writing value 24 into INH interrupt status register at address 50 6 The JADE reads the compressed audio data from the mailbox and acknowledges the reception by resetting the INHB bit In the following four 2 5 ms packets of uncompressed audio data are exchanged See Figure 48 for the handshake procedure Semiconductor Group 148 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Host Host Interrupt
47. 2 to be loaded in multiples of the physical time slot length The maskable interrupt status bits for controlling the transfer are BFUL Buffer full RC1 BEMP Buffer empty XC1 or optionally FSC Frame Sync interrupt FSC RFS Frame Sync interrupt RFS TFS Frame Sync interrupt TFS Semiconductor Group 55 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks In addition the control bit HXA1 controls whether the audio transmit channel is loaded into the shift register from the XC1 register accessible from the DSP HXA 0 or from the host HXA 1 The block diagrams for the receive and transmit audio channels are shown in Figure 23 and Figure 24 Receive 1 Host DSP a gt SLIN RC1 SLIN LEN TS EN 32 bits 2 2 V 1 5 49 Ne Wm VY Wy 00 DU DCL 2 bx y Load d FSC M A S jotk p U 01 DD RES gt U Legie gt Shift Register lt X i SCLK J x 1 to 32 bits LBIT 10 lt SR TFS a A A SCLK 49 y T ex LMOD LBIT BFUL Figure 23 Transmit 1 Host DSP SLIN EN Strobe XC1 gt SLIN LEN TS EN 32 bits ES 2 L5 L9 V Y V 00 gt gt DU DCL 2 pEEGHUS N ai FSC gt M Pre ud sd gt due J pp RFS 7 o ul d oe gt Shift Register gt SCLK g
48. 2 functions supported by the PSB 7230 are Layer 1 functions in terms of the frame structure supporting any number n of 4 byte multiplexes n 1 16 the number is implicitly determined by the DCL clock see Section 2 One Monitor channel of programmable location Two C I channels See Figure 28 Monitor Channel Multiplex O Multiplex 1 Multiplex 15 maximum DU DD 0008 7 Data MR MX Data MR MX Data MR MX Feuille ll ee Figure 28 Parameters SLIN 0 Monitor transmit data on DU receive data on DD SLIN 1 Monitor transmit data on DD receive data on DU CH 0 3 Monitor channel in 3rd byte of multiplex 0 15 common to receive and transmit channel CH 0 3 0001 in the example C I Channels 2 Independent Channels Multiplex O Multiplex 1 Multiplex 15 maximum m o oooO Bee Cl cA C I FSCG T ey sd r4 mse 7 6 5 4 3 2 1 0 sB CIL 0 CA CIL 1 ca Figure 29 Semiconductor Group 67 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks Parameters SLIN 0 C I channel transmit data on DU receive data on DD SLIN 1 C I channel transmit data on DD receive data on DU CH 0 3 C I channel in 4th byte of multiplex 0 15 common for receive and transmit channel CH 0 3 0001 in the example CI
49. 3 Data Sheet 1998 07 01 SIEMENS PSB 7230 Electrical Specification Table 34 Parameter Symbol Limit Values Unit min max Output data from high impedance to lozp 100 ns active Output data delay from clock foDD 100 ns Output data from active to high fopz 80 ns impedance Input data setup tips 20 ns Input data hold tion 40 ns IOM 2 Input Timing with Double Rate DCL TP lt TWHS lt TWL DCL in o i Double rate ____ jp EN 2 ica TESH lt TFSS gt lt TFSH gt FSC in f E Figure 68 Table 35 Parameter Symbol Limit Values Unit min max DCL period tp 244 ns DCL low twee 100 ns Frame sync setup tess 40 ns Frame sync hold tesy 40 ns Semiconductor Group 174 Data Sheet 1998 07 01 SIEMENS PSB 7230 IOM 2 Output Timing with Double Rate DCL Electrical Specification d MNT DCL out T f Double rate Treo pen TFSD lt TFSH gt K TFSL gt FSC out f v 1 i Figure 69 Table 36 Parameter Symbol Limit Values Unit min typ max DCL period tp 520 651 782 ns DCL high tw 240 ns DCL low twee 240 ns Frame sync delay tesp 100 ns FSC period tesco 125 Us FSC high period tesy 60 62 5 65 us FSC low period tes 60 62 165 Us Semiconductor Group 175 Data Sheet 1998 07 01
50. 54 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features The following steps are performed 1 The JADE writes one frame of encoded audio data into the mailbox most significant byte first 2 The JADE writes a backup of the VocoderFinished interrupt number performed in the next step into the host accessible register 614 This is only used for detection of a missed interrupt when a slow host is connected see text below 3 The JADE generates a VocoderFinished interrupt at INT line to the host by writing a value CO or 80 toggling into IND interrupt status register at address 584 The value of this interrupt is each time toggling between CO and 80 to ensure that a polling host can consider a new VocoderFinished For an interrupt driven host one should just connect both numbers to the same interrupt service routine 4 The host reads the compressed audio frame from the mailbox using the procedure described in Section 3 4 and may reset the INDB bit The reset of the INDB bit is not mandatory and may be skipped 5 Start Point in First Frame The host writes the compressed audio frame for the decoder into the mailbox using the procedure described in Section 3 4 6 The host generates an interrupt to the JADE by writing value 24 into INH interrupt status register at address 50 7 The JADE reads the compressed audio data from the mailbox and acknowledges the reception by resetting the INHB bit To keep
51. 8 CA9 O 39 CA10 JO 37 CA11 O 32 CA12 JO 30 CA13 O 26 CA14 O 24 CA15 JO Semiconductor Group 12 Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction Table 5 External Memory Interface for Development Purposes only cont d Pin No Symbol Function Descriptions 76 CDO O C Bus Data 74 CD1 I O Data bus for external ROM or RAM Is to be left NC if not 70 CD2 l O used 68 CD3 O 64 CD4 O 62 CD5 O 57 CD6 O 55 CD7 O 51 CD8 O 49 CD9 I O 40 CD10 I O 38 CD11 I O 33 CD12 I O 31 CD13 I O 27 CD14 O 25 CD15 I O 43 EA External program Access enable When high an access to program address range 0000 7FFF fetches an instruction from on chip ROM Access to 8000 FFFF addresses external memory via the External Memory Interface When low an access to 0000 FFFF including 0000 7FFF normally reserved for on chip software accesses external program memory via the External Memory Interface 47 CRD O C Bus Read to external memories Left NC if not used 46 CWR O C Bus Write to external memories Left NC if not used 45 CPS O C Bus Select line for external program memory Left NC if not used 44 CDS O C Bus Select line for external data memory Left NC if not used Semiconductor Group 13 Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction Table 6 General
52. ATA 80h 3080h Figure 37 In the following tables the addresses are relative to the base address 80 In each row the upper line lists the read values the lower the write values of the corresponding register Semiconductor Group 101 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Table 16 Byte Read Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO Address Write Offset 00 RFIFO 1F XFIFO 20 STAR XDOV XCEC RCEC STR STX XCMD XF XRES XNEW STX 21 22 MODE 1 RAC XAC TLP ERFS ETFS MODE RAC XAC TLP ERFS ETFS 23 24 25 RCMD RMC RRES STR 26 CCRO PU RMSB XMSB CCRO PU RMSB XMSB 27 CCR1 RCSO RSCO RFDIS XCSO TSCO XFDIS CCR1 RCSO RSCO RFDIS XCSO TSCO XFDIS 28 TSAR TSR5 TSR4 TSR3 TSR2 TSR1 TSRO RCS2 RCS1 TSAR TSR5 TSR4 TSR3 TSR2 TSR1 TSRO RCS2 RCS1 29 TSAX TSX5 TSX4 TSX3 TSX2 TSX1 TSXO XCS2 XCS1 TSAX TSX5 TSX4 TSX3 TSX2 TSX1 TSXO XCS2 XCS1 2A RCCR RCC7 RCC6 RCC5 RCCA RCC3 RCC2 RCC1 RCCO RCCR RCC7 RCC6 RCC5 RCCA RCC3 RCC2 RCC1 RCCO 2B XCCR XCC7 XC
53. C6 XCC5 XCC4 XCC3 XCC2 XCC1 XCCO XCCR XCC7 XCC6 XCC5 XCC4 XCC3 XCC2 XCC1 XCCO 2C ISR RPF RFO XPR ALLS IMR RPF RFO XPR ALLS Semiconductor Group 102 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Unless otherwise indicated all register bits are initialized to O after a hardware reset During the initialization phase the firmware does a re programming on the following registers of the serial data controller to setup the default configuration for the communication with a video processor see Chapter 6 2 3 3 Table 17 Address Data Description 30A2 80 Transparent Mode 30A5 40 Receiver Reset 30A6 83 Power Up MSB first for Receiver and Transmitter 30AA OF Receiver 16 bit time slot 30AB OF Transmitter 16 bit time slot 30AC 50 Interrupt Enable for RPF and XPR When read register bits that are not in use or reserved for future use are not defined i e their value may be either 0 or 1 Receive FIFO RFIFO Read Address 00 1F The serial data receive FIFO size is 2 x 32 bytes One half of the FIFO is connected to the receiver shift register while the second half is accessible to the controlling processor Transmit FIFO XFIFO Write Address 00 1F The transmit FIFO size is 2 x 32 bytes One half is connected with the transmit shift register while the other half is accessible to the controllig p
54. Control Pin No Symbol Function Descriptions 95 CM1 Clock Mode Selects the option for the generation of the DSP internal working clock 85 SIO I O Serial I O line When programmed as input a rising or falling selectable edge on this line may generate a maskable interrupt INT host or INT1 DSP When programmed as output its state is directly controlled by the DSP or the host 84 RESET Reset input Reset time gt 1 ms Table 7 General Purpose I O Interface Pin No Symbol Function Descriptions 81 GPO l O OD General purpose l O pins 80 GP1 O OD 79 GP2 O OD 78 GP3 I O OD Table 8 Power Supply Pin No Symbol Function Descriptions 11 Vas Ground common to Vpp and Vppp 29 Vss 35 Vss 42 Vss 53 Vas 59 Vss 66 Vss 72 Vss 77 Vss 94 Vas Semiconductor Group Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction Table 8 Power Supply cont d Pin No Symbol Function Descriptions 12 Vop Positive power supply voltage 3 0 3 6 V 36 Vbp 60 Vbp 93 Vbp 34 Vbp 41 Vbp 52 Vbp 58 Vbp 65 Vbp 10 Vopp Positive power supply voltage 4 5 5 5 V for external 28 Voss interfaces 71 Vbpp 89 VbpA Separate positive power supply voltage 3 0 3 6 V for Clock Generation Unit Oscillator 92 Vasa Separate Ground 0 V for Clock Generation Unit Oscillator 87 VopaP Separate pos
55. DE AN and the analog front end AFE The DD line is output of the JADE AN DU is input to the JADE AN This configuration may be changed by the host by just overwriting the corresponding registers Semiconductor Group 162 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features The timing of the JADE AN firmware is controlled by the video processor which generates an interrupt every 10 ms at the SIO line The JADE AN then starts generating a number of frame sync signals at RFS and TFS depending on the length of the data packet that has to be exchanged The RFS and TFS bursts are asynchronously i e the RFS burst starts about 16 frame syncs before the TFS After data packet transfer the JADE AN waits for the next SIO interrupt Note During startup procedure the uncompressed interface IOM must be setup before the Serial Audio Interface is started i e the FSC and DCL signals must be stable before the first 10 ms interrupt is generated by the video processor Due to small differences in the clock of the video processor and the audio output the JADE AN is able to add or drop two uncompressed audio samples every 10 ms That means a skew of 2 5 fs 8 kHz between the communication board s clock and the audio codec s clock is acceptable to the JADE AN and should be aurally imperceptible In the following this will be called the long term skew In addition to the long term skew the JADE AN can correct for short term variances us
56. Ext Memory Data high 46 Ext Memory Data low 45 Ext Memory Addr high 44 Ext Memory Adar low 30414 Reg Data Reg Data 41 Reg Data Reg Data DSP Host Host DSP Host gt DSP DSP Host 3040 RDY LSBit Conf Cont 40 Conf Cont RDY LSBit Reg Address Reg Address The functions of these registers are described below Semiconductor Group Data Sheet 1998 07 01 PSB 7230 SIEMENS Interfaces and Memory Organization Indirect Access to Configuration and Control Registers Writing of hardwired registers Configuration and Control registers in the DSP memory from 2000 to 203F can be effected through the Parallel Host Interface For the last case two directly accessible locations are provided in the DSP Host Com area Host addresses 40 and 41 A write operation in the first of these registers with a command read write and a 6 bit address offset will cause the DSP to read or write a configuration control register in address space 2000 203F The second location Host address 41 contains the data read written from to the requested location DSP DSP Write DSP Read Host Host Write Host Read Address Always always Address Always Always 16 bit Wide 16 bit Wide ADO 7 8 Bit Wide 8 Bit Wide 30414 Reg Data Reg Data 41 Reg Data Reg Data DSP Host Host DSP Host DSP DSP Host 3040 RDY LSBit Conf Cont 40 Conf Cont RDY LSBit Reg Addre
57. F Reserved Frame Length 0 10 ms frame length selected The data packet size of compressed and uncompressed audio is determined by the frame length Value after reset 1A UDF UDF 1 0 Semiconductor Group 1 Reserved Mailbox Address 01 MSB LSB 0 0 0 UDF1 UDFO 0 1 0 Uncompressed Data Format independent of the selected audio compression 00 01 10 11 Reserved G 711 A Law G 711 u Law 16 bit uncompressed audio 124 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Mailbox Address 02 Value after reset CO MSB LSB G723C HP723 PF723 0 0 0 0 0 0 HP723 G 723 High Pass Filter On Off 0 High Pass Filter Off 1 High Pass Filter On PF723 G 723 Postfilter On Off 0 Postfilter Off 1 Postfilter On Mailbox Address 03 Value after reset 00 MSB LSB 0 0 0 0 0 0 0 0 Semiconductor Group 125 Data Sheet 1998 07 01 SIEMENS PSB 7230 Value after reset 00 MODE EM 3 0 DM 3 0 Value after reset 00 OPT1 Semiconductor Group MSB Firmware Features Mailbox Address 04 LSB EM3 EM2 EM1 EMO DM3 DM2 DM1 DMO Audio modes for encoder EM 3 0 and decoder DM 3 0 04 14 2u 3H 4u SH 64 MSB Neutral mode no compressed audio data is exchanged Pass through 8 kHz sampled data not
58. FHR1 2 is done like in the other LMODs for observation of the data stream by the DSP or host only Thus the LMOD 00 is identical with LMOD 01 except pre processing is not available and the receiver latency after reset is shortened see section below Semiconductor Group 57 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks Transmitter in LMOD 1 0 01 10 11 Similarly in the transmit direction after 1 2 or 4 bytes programmable are shifted out of the shift register the contents of the HXW1 2 write register accessible from DSP if HHX1 2 0 or host if HHX1 2 1 are loaded into the transmitter shift register In the same cycle 1 2 or 4 bytes are loaded from the HDLC transmitter output into the HXR1 2 read register physically separate for DSP and host In the next cycle the data from HXR1 2 is as a default loaded into HXW1 2 and a maskable interrupt status is generated to the DSP and host The interrupt status is generated to both DSP and host independent of the setting of HAH1 2 If the data in HXR1 2 is to be post processed the HXW1 2 register can be overwritten by the DSP or host before the next 1 2 or 4 bytes programmable have been shifted out of the shift register After reset XRES the reset status data of HXR1 2 and HXW1 2 is ignored by the transmitter i e the contents of HXR1 2 and HXW1 2 are not transmitted to the line but only the data from the HDLC transmitter In the first cycle after the transmi
59. FSC O OD Frame Sync Marks the beginning of a physical IOM 2 or PCM frame Table 3 Serial Audio Interface Pin No Symbol Function Descriptions 1 SCLK I O Serial Clock Serial clock for SR and ST 100 SR O OD Serial Data Receive Should be connected to Vss via a pulldown resistor if not used 99 ST l O OD Serial Data Transmit 98 RFS I O Audio Receive Frame Sync 97 TFS O Audio Transmit Frame Sync Semiconductor Group 11 Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction Table 4 System Clocks Pin No Symbol Function Descriptions 90 XTAL1 I Crystal In or Clock In If a crystal is used it is connected between XTAL1 and XTAL2 If a clock signal is provided via an external oscillator this signal is input via XTAL1 In this case the XTAL2 output is to be left non connected The XTAL1 input has to be 5096 duty cycle and must not exceed the voltage range between Vssa and Vpp 91 XTAL2 O Crystal Out Left unconnected if a crystal is not used 86 CLKO O Clock Out Output clock of frequency equal to the internal frequency divided by a programmable factor Table 5 External Memory Interface for Development Purposes only Pin No Symbol Function Descriptions 75 CAO O C Bus Address 73 CA1 O Used for addressing ROM or RAM external to the chip 69 CA2 O Is to be left NC if not used 67 CA3 O 63 CA4 O 61 CA5 O 56 CA6 O 54 CA7 O 50 CA8 O 4
60. JADE AN correspondingly i e if the user receives a status value of 2 from the JADE AN it also has to transmit a part 2 packet in the current 10 ms frame The P 1 0 control block bits sent by a user are ignored by the JADE AN when operating in G 723 mode This is to avoid collisions between the host and the auto increment mechanism in the JADE AN 00 First part of compressed audio packet G 723 part 1 3 01 Second part of compressed audio packet G 723 part 2 3 10 Third part of compressed audio packet G 723 part 3 3 11 Fourth part of compressed audio packet G 723 reserved L 2 0 Loopback modes see Figure 44 used for testing the audio subsystem 000 No loopback default 001 Send received compressed data back to the user as encode data 010 Encode the decoded user data 011 Reserved 100 Reserved 101 110 111 Semiconductor Group Decode the encoded audio input data Send the digital ADC output to the DAC input Reserved 127 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Loopback Modes 1 5 2 6 JADEAN Figure 44 Mailbox Address 06 Value after reset 00 MSB LSB OPT2 0 0 Re1 Red Rd1 RdO e d Re 1 0 When the encode mode is G 723 the Re bits give the desired encoding Rd 1 0 method 00 high rate don t use silence suppression 01 high rate use silence suppression 10 low rate don t use silence suppresion 11 low rate use
61. L C I channel length is 4 bits 0 or 6 bits 1 DLL Double last look yes 1 or no 0 4 4 1 Monitor Channel Protocol Use of Monitor Channel In the case where a local host is present the Monitor channel may be used e g for data exchange between the local host and another controller attached to the IOM 2 bus For this purpose the basic Monitor channel protocol as explained in this section is sufficient Note The Monitor channel protocol is not implemented on chip on the PSB 7230 The Monitor channel protocol has to be implemented via the host this allows the implementation of data exchange with a remotely located controller General Description of Monitor Channel Protocol The Monitor channel consists of 8 bits for the Monitor Data channel MON and 2 bits for the flow control MX and MR The transmitter controls the Monitor Data channel and the MX bit on one line while evaluating the condition of the MR bit on the other line The receiver evaluates the MX bit of one line and latches its Monitor Data value It controls the MR bit of the other line The Monitor channel protocol is shown in the figure below The hardware performs reception and transmission of Monitor channel messages packets byte by byte under software control The received and transmitted Monitor channel bytes are stored in the Monitor Data Transmit MONX register and Monitor Data Receive MONR register respectively The software controls the monitor channel via tw
62. O HXA Ch1 Mode 201A 0 0 0 0 0 0 0 0 201B 0 0 0 0 0 0 0 0 201C 0 0 0 0 0 0 0 0 201D SDATA Ser SLIN1 SLINO LMOD1 LMODO HHR Rec Path 201E SDATA Ser SLIN1 SLINO LMOD1 LMODO HHX Tx Path 201F 0 0 0 0 0 2020 0 0 0 0 0 2021 Mon Ch SLIN MONCH3 MONCH2 MONCH1 MONCHO Config 2022 Mon Ch 5 MRE MRC MXC Cntr 2023 IC Mon MAD7 MAD6 MAD5 MAD4 MAD3 MAD2 MAD1 MADO Channel Id 2024 Monitor MONR7 MONR6 MONRS5 MONR4 MONRS3 MONR2 MONR1 MONRO Tx Rec MONX7 MONX6 MONX5 MONX4 MONX3 MONX2 MONX1 MONXO 2025 C I Ch CIEN1 AWK1 CIEN2 AWK2 Mode 2026 C I Ch 1 SLIN CICH3 CICH2 CICH1 CICHO CIL DLL Config 2027 C I Ch 2 SLIN CICH3 CICH2 CICH1 CICHO CIL DLL Config 2028 2029 C I CIR5 CIR4 CIR3 CIR2 CIR1 CIRO Channel 1 CIX5 CIX4 CIX3 CIX2 CIX1 CIXO 202A C I CIR5 CIR4 CIR3 CIR2 CIR1 CIRO Channel 2 CIX5 CIX4 CIX3 CIX2 CIX1 CIXO 202B IOM Config B ES FODS CGEN 202C PLL Config 1 MO CM1 MAX BYPA LOCK SWCK PU 202D PLL Config 1 N4 N3 N2 N1 NO M3 M2 M1 2030 GP Output IOC3 IOC2 IOC1 IOCO Config 20314 GP Direction IOD3 IOD2 IOD1 IODO 2032 GP Data IOR3 IOR2 IOR1 IORO 2033 GP Strobe IOS3 IOS2 IOS1 lOSO 2034 GP Int IOINT3 IOINT2 IOINT1 IOINTO Status 2035 GP Int Mask IOIM3 I
63. OIM2 IOIM1 IOIMO Semiconductor Group 83 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Note VN 5 0 Read only hardwired MAD 7 0 Loaded from AD 7 0 at reset may be written thereafter MONR A read of MONR acknowledges MDR interrupt status for Host and for DSP CIR A read of CIR acknowledges the C I Change CIC int status for Host and for DSP GP Int A read of GP Int Status acknowledges the GP IO interrupt status for Host Status and DSP Semiconductor Group 84 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Description of Configuration and Control Registers Unless otherwise indicated all register bits are initialized to O after a hardware reset When read register bits that are not in use or reserved for future use are not defined i e their value may be either O or 1 During the initialization phase the firmware does a re programming on the following registers of the configuration control block to setup the default configuration for the communication with a video processor see Chapter 6 2 3 3 i e the hardware reset values given in the register description below are overwritten by the following values Address Data Description 2005 04 SCLK is an output 2006 1B SCLK Baud Rate 34 56 MHz 28 1 23 MHz 2011 8F Receive Uncompressed Audio DU line 16 bit linear 2012 10 Position of first
64. Parallel Host Interface and one of the serial interface lines DD or DU IOM 2 or SR or ST Serial Audio Interface SAI The capacity of each channel is individually determined by programming the time slot length on the selected serial interface line Timing Generation The selection of the line for each of the channels is performed via SLIN1 0 00 DU 01 DD 10 SR 11 ST The timing logic is driven by the bit clock and frame synchronization signals corresponding to the selected line These are DCL 2 and FSC for DD and DU SCLK and RFS for SR SCLK and TFS for ST The IOM 2 timing signals can be input or output of the PSB 7230 i e the circuit is a slave or master with respect to the IOM 2 interface The selection is done by the CGEN bit in register 202Bh The timing on the SAI lines SR and ST is either input or output In the case where the timing is internally generated i e the PSB 7230 functions as SAI master for SR and or ST a schematic diagram of the generation logic is shown in Figure 21 Semiconductor Group 52 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks PRSC SCKIN 110 RFIN N NI DSP clock 4 Div gt o i Baud Rate gt 0 SCLK in gt x Generator M 4 ie STR ERFS RCONT RPRD RREP X i i Baud Rate p Generator M N IN AN 1 T qi STX ETFS TCONT TPRD TREP X 7 Figure 21 Timing Generation on SAI Lines Framesync F
65. R1 is provided for this purpose Semiconductor Group 60 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks Transmit H ost sp Host DSP HXRx l o HXWx Time slot 4 parameters A0 32 bits 32 bits Ti a ae SLIN 4 a cire T 2 V N Sue XMSB V ais bit reversal lt 00 D DU o DCL 2 gt px Time slot 3 M Fse p mesye Count TS Clock j 01 gt DD ree Z Logic Shift Register A uU RFS 40 U Ser clock strobe 1 2 or 4 bytes SCLK ui gt X 10 gt gt SR TS gt a Buffer 2 V f g SCLK gt V 11 ST LMOD BFHX Bit level functions Data EST XFIFO f Transmitter v Figure 26 Caption to the Figure The data from the data transmitter is loaded into DSP accessible read registers and simultaneously into physically separate host accessible read registers Data is loaded into the shift register from the transmit channel register accessible from the DSP if HHX 0 or the register accessible from the host if HHX 1 The control bit HHX1 is provided for this purpose The access right to the receiver and transmitter input output from the DSP or the host determined bit HHR1 and HHX1 is independent of who is allowed to service the data controller determined by bits HAH1 Note on Time Slots of Data Communic
66. RR1 31 24 12h HRW1 23 16 HRR1 23 16 11h HRW1 15 8 HRR1 15 8 10h HRW1 7 0 HRR1 7 0 03h XC1 31 24 RC1 31 24 02h XC1 23 16 RC1 23 16 01h XC1 15 8 RC1 15 8 00h XC1 7 0 RC1 7 0 Figure 14 Semiconductor Group 37 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization Alignment of Data for Audio Channel The most significant bit is always the first bit received transmitted Therefore if audio is processed in units of N bits N programmable between 1 and 32 the alignment of the data for receive and transmit audio channels in the registers is as shown in Figure 15 bit 0 78 1516 23 24 31 LS bits of address Host 00b 01b 10b 11b Audio Receive and T it Registers received ransmi g transmitted bit 0 1516 31 LS bits of address DSP 00b 10b Transmit Alignment for N bits gt Shift out Receive Alignment for N bits Shift in el Figure 15 Alignment of Data for Serial Data Channel In the serial data controller the reception transmission of most significant or least significant bit can be selected by control switches RMSB XMSB Nevertheless for serial data communication the convention is that the least significant bit of user data is received transmitted first In order to have an identical format for the data in the serial controller input output registers as in the FIFOs the data is aligned in the registers as shown below the
67. SP and from the host Simultaneously a maskable interrupt status is set Similarly in the transmit direction transmit channel data is loaded from the write register pertaining to that channel either from DSP or host register as selected via a control bit into the transmit shift register when a selectable number of bits have been shifted out The buffering of up to 32 bits reduces the reaction time of the DSP software As an alternative to this the audio channel data can also be loaded from the shift register to the DSP host registers receive direction and from the DSP host registers into the shift register transmit direction at the occurrence of the frame sync pulse In this case the number of significant bits in the registers is determined by the time slot length programmed on the receive transmit line The DSP host has 125 us to read write the register while new data is assembled or the contents of the shift register are transmitted during the following frame this option could be used for DSP software synchronized on the 8 kHz time base The audio channel registers each of length 2 words 4 bytes are see Section 3 RC1 Receive channel 1 XC1 Transmit channel 1 The relevant parameters for controlling the transfer of the audio channels are independent for each channel EN Enable channel LMOD Load Mode either once per frame or after LBIT bits have been received transmitted LBIT Load Bits Gives the number of bits 1 to 3
68. Symbol Limit Values Unit Motional capacitance C 17 fF Shunt Co 5 pF Load C lt 23 42 pF Resonance resistance R recommended 50 80 Ohm 1 Note The 34 56 MHz crystal must be of the fundamental type Semiconductor Group 167 First value for 7 68 MHz crystal using internal PLL second value for 34 56 MHz crystal using bypass mode Data Sheet 1998 07 01 SIEMENS PSB 7230 7 7 AC Characteristics 7 7 1 Testing Waveform Electrical Specification Conditions as above Recommended Operating Conditions at T 0 to 70 C Inputs are driven to 2 4 V for a logical 1 and to 0 4 V for a logical 0 Timing measurements are made at 2 0 V for a logical 1 and 0 8 V for a logical O The AC testing input output waveforms are shown in Figure 57 24 j 2 0 2 0 V Device Test points under i C load 50 pF FSC DCL DU DD 08 7 0 8 el ie 30 pF W others 0 45 EIE Figure 57 7 7 2 Parallel Host Interface Timing Siemens Intel Bus Mode ta Microprocessor Read Timing Figure 58 Semiconductor Group 168 ITT00712 Data Sheet 1998 07 01 SIEMENS PSB 7230 Electrical Specification ITT00713 Figure 59 Microprocessor Write Timing ALE WR x CS or RD x CS xr Kee K II Figure 60 Multiplexed Address Timing on P LL KU ITT09661 Figure 61 Non Multiplexed Address Timing Semiconductor Gr
69. a MODE OPT1 Data Bytes Bytes 38 06 00 8 06 00 0 Part 0 of 30 ms frame 39 06 08 8 06 00 0 Part 1 of 30 ms frame 40 00 10 8 06 00 0 Part 2 of 30 ms frame Command Neutral Mode last G 723 data to JADE AN 41 00 00 0 06 00 0 42 00 00 0 06 00 0 Last G 723 decoded data from JADE AN 43 00 00 0 00 00 0 4th neutral packet next can change mode P 1 0 bits are autoincremented in outband controlled mode Thus OPT1 does not need to be explicitly written for each 10 ms packet If P 1 0 bits are written to the JADE which don t match the corresponding status bits they will be ignored Data Bytes means the number of compressed data bytes transmitted from the User to the JADE AN or from the JADE AN to the User respectively The uncompressed data is exchanged constantly with 80 samples in 10 ms 8 kHz 6 2 2 Uncompressed Data Protocol The uncompressed data protocol is quite simple The default configuration is 8 kHz sampling rate and 16 bit linear data The data format can be selected to be either 16 bit linear or 8 bit PCM G 711 A u law For a 10 ms framing the size of the uncompressed data in bytes is listed in the table below 16 bit linear G 711 A 4 law 8 kHz sampling rate 160 80 Note Independently of the interface selection for the uncompressed audio always the most significant bit of the most significant byte is transferred first e g 16 bit linear samples are split up into two by
70. a device which implements voice compression algorithms using the Algebraic Code Excited Linear Prediction ACELP and the Multi Pulse Maximum Likelihood Quantization MP MLQ standard as defined in the ITU T G 723 Recommendation In addition G 711 PCM audio coding is also supported Thus in G 723 mode it compresses the PCM 8 bit A 1 law or 16 bit linear voice signal into 5 3 Kbit s ACELP or 6 3 Kbit s MP MLQ bit stream and vice versa The implementation complies with the newest ITU T C code V5 1 and includes the G 723 Annex A Voice Activity Detection and Comfort Noise Generation The JADE AN finds applications in Analog Videophones H 324 Networks e g LANs for packetized voice H 323 Video Conference Systems Corporate Network voice concentrators multiplexers and gateways Data over voice and Voice over data terminals Other potential application areas are Networks e g LANs for packetized voice Digital Added Main Line DAML amp Digital Circuit Multiplication Equipment DCME Voice storage e g in PC based applications Message recording and distribution The interfaces of the JADE allow a seamless integration into IOM 2 based systems After the circuit is set up in the proper mode of operation and parameter settings are programmed by a controlling software the circuit runs independently of the rest of the Semiconductor Group 6 Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction syste
71. a falling edge on SIO causes an interrupt if unmasked 1 If SIO is programmed as input SIO 0 a rising edge on SIO causes an interrupt if unmasked Data Controller Access Register Read Write Address 2010 Value after reset 00 HAH1 Host Access to serial data Controller 0 The DSP services the data controller register set including FIFOs is inaccessible from Host 1 The Host services the data controller register set including FIFOs is inaccessible from DSP This bit determines the access to the register area of the data controller it is independent of the HHR and HHX bits which determine the access from DSP or Host to the serial data input and output respectively Semiconductor Group 91 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Receive Audio Channel 1 Read Write Address 2011 2013 Value after reset 00 EN Enable If inactive 0 no clock is generated for this channel must be set to 0 during configuration of receive audio channel 1 SLIN 1 0 Select Line 00 Channel time slot on DU 01 Channel time slot on DD frame sync FSC clock DCL or DCL 2 frame sync FSC clock DCL or DCL 2 frame sync RFS clock SCLK 10 Channel time slot on SR 11 Channel time slot on ST frame sync TFS clock SCLK LEN 4 0 Length of channel time slot Channel time slot length in bits LEN 1 1 32 bits TS 8 0 Time slot position Position of first bit of time slot from
72. al Architecture and Functions 2 General Architecture and Functions 2 1 Architecture Figure 9 shows a sketch of the PSB 7230 architecture with its most important functional modules AD 0 7 RD WR CS ALE SO INTR INT Reset PAS A A 4 NN pe Nue d NIE SN Parallel Host Interface EE Mon C I Control Serial Data Channels lt P N gt di Mailbox S TFS e EX 256 bytes 5 GP 0 3 DSP 32KW program ROM Core gt CLKO Config Control 8 KW data 2 KW data 1 KW data 1 KW data BAG Registers X ROM X RAM X RAM Y RAM clock gen gt XTAL2 External Memory Interface rad l A V V V WV V V y CA 0 15 CD 015 CRD CWR CPS CDS Figure 9 The audio processing of the PSB 7230 is based on a 16 bit fixed point DSP core SPCF Signal Processor Core Fast The Clock Generator is responsible for generating the internal clocks for the SPC A Baud Rate Generator provides an output clock of programmable rate The Parallel Host Interface is used to control the circuit through an associated host via interrupt handshake procedures Alternatively the circuit can be controlled via the Serial Audio Interface thus enabling stand alone applications to be implemented Communication between the Host if used
73. alize mailbox i VocoderFinished gt Ch 00h i start address v for slow hosts 80h see text ach lt Write new control aR block into mailbox e Interrupt request amp f for control block E Interrupt request ad z VocoderFinished IND COS SESS INT INDB 1 E alternating COh 80h 30h E compressed audio l from JADE to host o E o i z INT1 INHB 1 INH 3050h 50h c Interrupt 31h z Getint i t ji T z i et Interrup gt number lt i 5 E Ie Start 4000h 00h 5 Read control block E from mailbox Mailbox l SetINHB 0 a z 7 na IND 3058h 58h INT INDB 1 LLL ll lx Interrupt request 32h Aft r pt A 8 Acknowledge j y m data transfer 5 i l o T o Al d w l gt Interrupt g g f i l Get Interrupt number If IND 32h check 61h register If new l i VocoderFinished continue interrupt i service l reds oe Mee Re eee ee es ee ee ee ee ee he ee 5 Figure 52 Semiconductor Group 159 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features In this case the host generates the WCB interrupt before it has recognized the VocFin from the JADE AN and the JADE AN generates the VocFin before it has recognized the WCB from the host Immediately after the reception of WCB request the JADE AN will service that interrupt and s
74. ame Sync Select only valid if TFS is output in both cases the polarity is selected by TFPS 0 Single cycle TFS is generated 1 The data strobe is output on TFS pin This only affects the TFS pin the internal frame sync is generated and is input to the timeslot count logic of the audio receivers and transmitters connected to SR and ST line as in case TFSEL 0 The strobe signals of all audio receivers and transmitters connected tp SR and ST line will be combined by logical OR TFS polarity select 0 Rising edge marks the beginning of a new frame on the TFS line 1 Falling edge marks the beginning of a new frame on the TFS line If TFS is an output it is inverted vs TFPS 0 Period of TFS pulse generation Number of repetition of pulses When TCONT 0 TREP 9 0 gives the number of pulses TREP 1 to be generated spaced 16 bits apart up to 1024 pulses When TCONT 1 TPRD 4 0 gives the spacing of continuously generated pulses in 16 bit word increments up to 32 Semiconductor Group 90 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description SIO Configuration Register Read Write Address 200B Value after reset 00 SAIO Serial Audio Interrupt line In Out 0 SIO line is an input 1 SIO line is an output SOUT Serial Audio Out value If SAIO 1 SIO is output value of SIO line clocked out with the rising edge of SCLK SINTC Serial Audio Interrupt Configuration 0 If SIO is programmed as input SIO 0
75. and Host read register DSP or Host cf HHR1 bit write register is loaded into data receive buffer and read DSP or Host read register is loaded into DSP or Host write register for software to be accessed via a Buffer Full interrupt status HHR Host Data Receiver Access 0 DSP has access to modify data receiver input monitoring from host still possible 1 Host has access to modify data receiver input monitoring from DSP still possible Semiconductor Group 94 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Serial Data Channel Transmit Path Register Read Write Address 201E Value after reset 00 SLIN 1 0 Select Line 00 Channel on DU frame sync FSC clock DCL or DCL 2 01 Channel on DD frame sync FSC clock DCL or DCL 2 10 Channel on SR frame sync RFS clock SCLK 11 Channel on ST frame sync TFS clock SCLK LMOD 1 0 Load Mode 00 When shift register is about to become empty it as well as DSP and Host read registers is loaded from data transmitter XX When shift register contains n bytes XX 01 n 1 XX 10 n 2 XX 11 n 4 the contents is loaded into DSP and Host read register DSP or Host cf HHR bit write register is loaded into data receive buffer and read DSP or Host read register is loaded into DSP or Host write register for software to be accessed via a Buffer Empty interrupt status HHX Host Data Transmitter Access 0 DSP has access to modify data transmitter outp
76. annel one Monitor channel two C I channels one receive and one transmit data channel Audio receive channel Independently programmable on DD or Audio transmit channel DU with programmable locations start at bit 1 512 and lengths 1 32 bits w r t FSC Monitor channel Programmable on DD in DU out or DD out DU in with programmable time slot 3rd byte in multiplex O 15 after FSC Two C I channels Programmable on DD in DU out or DD out DU in with programmable length 4 or 6 bits and position 4th byte in multiplex O 15 after FSC Data receive and transmit channels Independently programmable on DD or DU with programmable locations start at bit 1 512 and lengths 1 256 bits w r t FSC The transfer of voice samples is performed with the help of an interrupt with repetition rate 8 kHz derived from the FSC signal A double buffered register is provided for each channel accessible from the DSP and from the parallel host interface The double buffered register ensures that enough time is always provided for reading and writing data before an overflow underflow occurs independent of the location of the time slots Alternatively the audio samples can be transferred between the DSP or Host and IOM 2 by using an interrupt generated when a programmable number 1 32 of bits are shifted out number independent of the time slot length on the line Outside the time slots where transmission takes place
77. ansmitter latency after reset is shortened see section below The transmission is in this case started by the setting of XAC 1 No write to HXW1 2 is necessary The start of the transmission can be in the same frame w r t the frame sync signal on the chosen line as the setting of XAC 1 since the time slot logic works independently of XAC Semiconductor Group 58 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks In transparent mode TMO 1 the transmission is only started at the beginning of the time slot time slot aligned If XAC is set to 1 during the selected time slot the transmitter waits for the beginning of the time slot in the next frame The serial data channel registers each of length 2 words 4bytes are Section 3 HRH1 Data Receive Read 1 HRW1 Data Receive Write 1 HXH1 Data Transmit Read 1 HXW1 Data Transmit Write 1 The relevant parameters for controlling the transfer of the serial data channels are LMOD 1 0 Load Mode access byte by byte without delay or access in 1 2 or 4 byte units with a corresponding serial data delay HHR Access to serial data receiver input from DSP HHR 0 or from host HHR 1 HHX Access to serial data output shift register from DSP HHX 0 or from host HHX 1 The access right to the receiver and transmitter input output from the DSP or the host determined bits HHR1 and HHX1 is independent of who is allowed to service the data controller determin
78. are executed 1 The host generates an interrupt to the JADE by writing value 19 into INH interrupt status register at address 50 2 The JADE writes the firmware version number into communication register accessible from the host at address 60 and resets the INHB bit to 0 3 The host checks the INHB bit and as soon as it reads a 0 it may get the version number from register 604 The INHB 0 polling is not supported in some previous JADE versions older than JADE 2 2 and JADE MM 1 2 Thus if also these versions need to be identified by reading the version number this can be obtained by waiting for 1 ms instead of polling the INHB 0 condition For the JADE versions supporting the INHB 0 it is ensured that the INHB 0 condition becomes true in less than 1 ms The version number of JADE AN 2 1 is xyh A3h Thus the xyh in the picture above has to be substituted by this number Semiconductor Group 114 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features 6 1 2 Software Reset A software reset is used to re initialize the JADE AN without resetting the hardware This means that e g not the whole configuration control register area is reset but only the firmware initialization see Section 5 3 and Section 5 4 is executed See Figure 39 Software Reset Jad ih as ce oa ces a es i Ses
79. are numbered by the P 1 0 bits in OPT1 for outband control OPTIONS for inband control taking on the values 0 1 or 2 for the first second or third part of a 30 ms frame respectively When entering G 723 mode the pipelining is similar to the above listing but the first G 723 packets from the JADE AN will be invalid indicate by MSB of OPT1 As mentioned above for synchronisation of input and output packets one has to wait for valid packets from the JADE When in G 723 mode mode changes will be recognized by the JADE with the beginning of the first 10 ms packet Thus the control block for a mode change request should be transmitted to the JADE during the previous 3rd packet exchange After an exit from G 723 encoder has been requested the P 1 0 counter will no longer reflect the packet numbers even during the phase of draining the JADE internal pipeline See the Example below for details high rate without voice activity detection used in this example behaviour for the other modes is similar The recommended host procedure for setting up G 723 encoding and or decoding is as follows 1 Wait for status packet showing the desired mode The firmware takes care that the 4th packet after a mode change shows the desired mode 2 Wait for the 1st valid G 723 encoded packet numbered as packet 0 All subsequent packets will be numbered correctly Table 26 Control Status Pipeline for G 723 Packet Control User to Statu
80. ata Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features G 723 compressed audio data packets 10 msec 10 msec i 10 msec S 10 msec P P 1 0 00 01 10 00 bit Rf ale byte 0 byte 0 0 0 6 3 kbit s a7 7E byte byte 0 byte 0 777 UJ byte 5 3 kbit s 7 7 7 bit bit i aie 0 7 s 0 byte byte 0 byte 0 byte SID frame Silence Insertion Descriptor 7 7 7 7 bit bit bit bit 7 0 T 0 7 0 7 0 byte 0 11 byte 0 byte 0 byte 0 11 Untransmitted 7 T Y 7 30 msec G 723 Frame valid data byte garbage data byte Figure 45 The two LSB s of the first byte inside a 30 ms frame determine the kind of frame that is currently being transmitted see Figure 45 Semiconductor Group 131 Data Sheet 1998 07 01 SIEMENS PSB 7230 Table 19 Firmware Features G 723 Mode Supported in ITU T C Code Version Bit 1 0 of First Byte Comment G 723 6 3 Kbit s 4 1 5 0 5 1 00 6 3 Kbit s Mode standard packet G 723 5 3 Kbit s 4 1 5 0 5 1 01 5 3 Kbit s Mode standard pac
81. ating Conditions s sa ex ors doa ka ERE ERE AC de pee Cadete 165 7 3 Do Ghardeleristi S assess ENTE t tothe a dew MERE EU ORE 165 7 4 CapacitantesS a suae xa siut boe ka etwelretteq ree rua pta tein grat 167 7 5 Oscillaior CI GE ere anenee a drive o E e aw ve Meese d 167 7 6 XTAL 1 2 Recommended Typical Crystal Parameters 167 7 7 AC GharactersSloS esri oto Pete e bm RE ET eae pet a 168 7 7 1 Testing Waveform 0295 mes Vete e anaana ack RR I uses a Gale a M MTS RUD s 168 7 1 2 Parallel Host Interface Timing 00 002 cee eee 168 7 7 3 IOM 2 Interface Timing eeu eb Ga Pee Rer eo aa eee wit S exe 172 7 7 4 serial Audio Interface Timing esr bre Rr hee PL ees 176 7 7 5 External Memory Interface 0002 eee eee eee 178 8 Package Outlines oinor ARE Wed he 8 RS Be hee Ce Ee Ree Ase we ss 179 Semiconductor Group 4 Data Sheet 1998 07 01 SIEMENS Joint Audio Decoder Encoder for Analog Videophone PSB 7230 JADE AN Version 2 1 1 Introduction 1 1 Feature List Functions G 723 V5 1 Compression Decompression 6 3 5 3 Kbit s Accepts outputs uncompressed audio in 8 bit PCM A u law or 16 bit linear format G 711 Compression Decompression 64 Kbit s Uncompressed compressed audio switchable between different interface combinations IOM Serial Audio Interface IOM Host Host Host Inband controlled H 221 H 223 oriented audio protocol e g for direct serial connection to Vid
82. ation Controller If a time slot is still active either in receive or transmit direction when a new frame sync pulse is detected the programmed length of the time slot is not reduced but the time slot remains active until its end However the time slot count logic for the new frame starts immediately at the detection of the new frame sync pulse A new time slot can start immediately after the currently active time slot has been closed thus permitting a permanent reception or transmission time slot length distance between two consecutive frame sync s The case where time slot length gt distance between two consecutive frame sync s should not occur Semiconductor Group 61 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks Note on Latency of Serial Data When the data receiver is enabled via bit RAC the data receiver is clocked with the serial interface clock even outside the selected time slot However the logic at the input of the data receiver is only clocked with the serial clock during the selected time slot Consequently N bits are loaded into HRR register from the serial line after N clock edges inside the selected time slot N is equal to 8 16 or 32 depending on LMOD Similarly data from HRW register is loaded into data receiver only after a certain number of clock edges inside the selected time slot have occurred The latency delay of received data from the input pin to the data FIFO is given i
83. available when Host Host is selected as interface combination for compressed uncompressed data G 711 8 kHz sample rate A law encoding decoding G 711 8 kHz sample rate u law encoding decoding Reserved Reserved G 723 8 kHz sample rate MP MLQ 6 3 Kbit s or ACELP 5 3 Kbit s coding Mailbox Address 05 LSB 0 0 P1 PO L2 L1 LO Data is invalid If is set then the compressed data in this packet was missing or had errors The data words in this packet are still sent to avoid buffer problems 0 1 Data is valid Data is invalid 126 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features P 1 0 Part number of the data in this packet Allows the natural period of the data to be 10 to 40 ms For G 723 takes on the values 0 1 or 2 corresponding to the first second or third part of a 30 ms data packet Is always 0 for the other modes Note To avoid the updating of these bits by the user in each frame when operating in G 723 mode the JADE AN auto increments the P bits Nevertheless the user has to take care that G 723 encoder and decoder are running synchronously i e the part number of the received and transmitted packet in one 10 ms frame must be identical for control and status For that after switching to G 723 mode the user has first to wait for valid packets i e wait for 0 and second to read the P 1 0 status bits to synchronize the data stream transmitted to the
84. bit in time slot 32 2013 42 Interrupt generated after 2 samples of 16 bits stored 2017 AF Transmit Uncompressed Audio DD line 16 bit linear 2018 10 Position of first bit in time slot 32 2019 42 Interrupt generated after 2 samples of 16 bits stored 201D 10 Data receiver connected to SR line 201E 18 Data transmitter connected to ST line Moreover the firmware uses registers 2007 and 2009 for setting up the appropriate number of frame syncs The firmware also initialises the PLL Config registers 202C and 202D to its appropriate values in case the PLL mode is selected via the CM1 pin In case the non PLL mode is chosen the firmware does not use these registers Chip Version Number Register Read Address 2000 Value after reset 10 VN 5 0 Version Number of Chip Semiconductor Group 85 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description External Memory Interface Register Read Write Address 2001H Value after reset 00 LDMEM Load Memory If LDMEM 0 the external memory interface is connected with the program bus It is used for connecting an external software RAM or EPROM If LDMEM 1 the external memory interface address and data buses are connected to the outputs of registers address low high at host address 44 45 and data low high at host address 46 474 respectively This mode is used to download a program into an external RAM CAEN If EA 1 and LDMEM 0 Enable addres
85. changing its MR bit to the active state 0 The transmitter recognizes this change and can now transmit the next byte of the message This is done by transmitting the value in the Monitor Data channel and setting the MX bit to the inactive idle 1 state for one frame and then changing it back to the active 0 state The receiver recognizes the transition of MX from the inactive to the active state and latches the contents of the Monitor Data channel The receiver acknowledges the data transfer by setting the MR bit to the inactive 1 state for one frame and then back to the active 0 state This procedure is repeated until all the data is transferred Once the receiver has acknowledged the last value the transmitter switches its MX bit and the Monitor channel into the idle 1 state The receiver recognizes this idle state after it has received two consecutive frames with an idle MX bit and will then set its own MR bit in the idle 1 state The transmitter recognizes the change of the MR bit and indicates the idle condition after the second frame If the receiver wants to abort a transmission then it will set its MR bit into an idle 1 condition The transmitter recognizes the abort condition after the second frame with an idle MR bit and switches its MX bit and the Monitor Data channel to idle Semiconductor Group 69 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks 125 us inact MX
86. compressed with these new settings and reporting the new settings in the status data block To change the control block data the host must first set the mode to neutral see MODE register description below for at least four frames default 40 ms Although the MODE word is part of the control block it can be changed to neutral at any time The switch to neutral mode before doing other changes to the control block is required to clear up the JADE s pipeline and make sure it does not have to process two different modes at once in the same pipeline Following the neutral mode command the host may transfer the control block with the new settings Some bits in the control block don t require this procedure volume change These are especially indicated in the description of the control block see below See Figure 43 for the host reading the current status data block from the JADE AN Semiconductor Group 121 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Read JADE Status ERATE REET e eT OTE TOT TRE n TTT TT er rT nr Host Jade DSP Interrupt INTI INHB 1 ad ie el Interrupt request l for status data Get Interrupt i i number Start 4000h 00h Write status data i packet into mailbox gt Mailbox i set INHB 0 IND 3058h 58h INT INDB 1 Interr
87. connected to the PC via a PCI Bus Interface e g the VPIC of 8 x 8 Inc The JADE AN compresses decompresses audio according to the ITU T standards G 723 5 3 and 6 3 Kbit s and G 711 used in e g LAN applications and runs a fully inband controlled protocol on the interface to the video codec It receives transmits uncompressed audio via the IOM 2 interface from to the ARCOFI SP The JADE AN is setup for this application automatically after a hardware reset so no additional initialization by a host is required Since the JADE AN has all its memories on chip no external SRAM needs to be connected Semiconductor Group 17 Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction The ARCOFI SP Audio Ringing Codec Filter is a hands free codec for 3 1 kHz voice which performs detection and elaborate balancing of the received and transmitted audio to suppress undesirable effects due to acoustical feedback of the signal from the remote subscriber The quality obtained is very close to that of echo free full duplex conferencing The video is captured by a PAL NTSC camera and digitized and demodulated e g by a standard SAA7110 which is directly connected to the video processor Alternatively a digital camera may be used which can be connected directly to the video processor The video processor compresses and decompresses video according to the ITU T standards H 263 and multiplexes demultiplexes video audio and data according to H 223 Th
88. control signals CS R W DS 2 Siemens Intel demultiplexed bus type with control signals CS WR RD 3 or of the Siemens Intel multiplexed address data bus type with control signals CS WR RD ALE The selection is performed via pin ALE as follows ALE tied to Vpp gt 1 ALE tied to Vss gt 2 Edge on ALE 3 The occurence of an edge on ALE either positive or negative at any time during the operation immediately selects the multiplexed bus type A return to one of the other is possible only if a hardware reset is issued 3 1 4 External Memory Interface The external memory interface allows the connection of both program and data memories to the PSB 7230 The access to either type of memory is determined by the signals CPS and CDS respectively In standard applications the external memory interface used as a program memory interface is normally not needed but is reserved for development purposes The upper 32k half 8000 FFFF of the address space is reserved for execution of software from external memory For executing software in the lower address range 0000 7FFF a control line EA External Access determines whether program is fetched from internal or external memory Thus in standard applications the EA line should always be high The DSP program execution can be controlled from the outside by loading the PC counter of the DSP via the parallel host interface Semiconductor Group 32 Data Sheet 1998 07 01
89. d SIEMENS PSB 7230 Table of Contents Page 1 IDIFOOHC HOT 44d ac ep swe e UR aco pig tr awh UA SINN ack es 5 1 1 Feature ISP ose eC o ato uidet Dope eu ne ed Go kas c ee 5 1 2 DRITA up quc TET uM 6 1 3 Logic Symbol vsu Cg eene theta id ase lcu viva ed a 8 1 4 Pin GOD JUoTa 2 s toram idet sube mua i vat epus scs ado ados cs 9 1 5 Pin Description ns cq ELM 10 1 6 System Integration s e Sese und aaea 16 1 6 1 H 324 Desktop Videoconferencing Solution for POTS 17 1 6 2 Low Cost H 324 Desktop Videoconferencing with Software Video 19 1 6 3 LAN Videoconferencing sw Xo xx RC X X RES awd S CORR AR On 20 1 6 4 Standalone H 324 H 323 Videophone 0000 cece eee 21 1 6 5 Internet Telephone Access in Line Card 0 000 eee eee 22 2 General Architecture and Functions 0005 24 2 1 ALCNECING sua 1 275 mud wie ulus eodeni s ict Vd oV ade eae dae a hae do 24 2 2 FUNCIONS a dries ieee dine lace c ait Bare ae wl oa ae lye e 2 he eo ges ele et 26 2 3 Summary of the Functions 0 0 ere 26 2 3 1 Audio Functions and Supplementary Features 26 3 Interfaces and Memory Organization 005 28 3 1 lusso MATE TP ere wae E Ea OE sy nae eee 28 3 1 1 IONIEZ IMeMACEs ausavic weisse worsen exa E E GEES Sexe whee at 28 3 1 2 Serial A di nterface a adem rr D ect aree M x we vids 30 3 1 3 Parallel Host Interface x ax arvo M erus SER on D Seer tat a
90. d tarif via the switching network and a reduced rate tarif transferring speech via a packetized network such as internet Since the JADE AN does the voice compression decompression complying to ITU T G 723 standard it can connect to any other telephone using the same standard e g Microsoft Netmeeting The example below shows a line card with 8 subscribers The number of JADE AN to connect to the internet may be selected between 1 and 8 depending on the statistical usage of this kind of connection Alternatively an internet access with voice compression can also be implemented in the switching network This may offer an even better statistical distribution thus optimizing the number of gateways needed Line Card SICOFI 4 Siemens A u law i or 16 bit 3 PEB 2465 linear Switching Network SICOFI 4 JADE AN JADE AN JADE AN y Siemens Siemens Siemens Siemens m PSB 7230 PSB 7230 PSB 7230 PEB 2465 Figure 8 Semiconductor Group 22 Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction The same principle may also be used for ISDN lines thus connecting common ISDN telephones to internet phones like Microsoft Netmeeting or using the internet for rate reduced overseas connections Demonstration Board Designs For Demonstration board designs containing the mentioned components please contact Siemens Semiconductor Group 23 Data Sheet 1998 07 01 SIEMENS PSB 7230 Gener
91. d by the JADE AN 6 2 3 3 Uncompressed Data IOM IF Compressed Data Serial Audio Interface SAI This is the default mode of the JADE AN ISEL 1 0 10 The complete setup of the interfaces timeslots and so on is done by the on chip firmware after Reset so that a standalone application with a video processor using the IOM SAI interface combination can be realized without the need of an additional host Compressed Audio Uncompressed Audio Serial Audio Interface IOM 1 Burst avery 10 ms Repetition rate 8 kHz Haader Data Time slot Video i BE x l a Processor 2 JADE AFE 1 Figure 54 The on chip firmware uses the data controller for the transfer of the compressed audio data over the serial audio interface During the initialization phase after a reset the internal firmware programs the configuration control registers see Section 5 3 and the data controller see Section 5 4 This results in a serial clock rate of 1 23 MHz continously generated by the JADE AN a 16 bit time slot length and MSB sent received first The frame sync signals RFS and TFS are generated by the JADE AN non continously i e during one frame only the exact number of frame syncs needed for the transfer of the current packet of data is generated in one burst The IOM Interface is in TE mode double DCL clock and IC1 2 channels are selected for the 16 bit linear data transfer between the JA
92. e 0 Sample of length LEN 1 loaded from write register into shift register for frame 1 at the occurrence of frame sync 1 When shift register is about to become empty LBIT 1 x LEN 1 bits shifted out it is loaded from write register for software to be accessed via a Buffer Empty interrupt status LBIT 4 0 Load Bits Number of bits in aggregates of LEN 1 loaded into output shift register when ready if LMOD 1 The number of bits loaded is equal to LBIT 1 x LEN 1 the corresponding interrupt status is BEMP1 Note Since the number of bits is 32 maximum the value of the product LBIT 1 x LEN 1 shall not exceed 32 HXA Host Transmit Access 0 Channel originates from DSP 1 Channel originates from Host Semiconductor Group 93 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Serial Data Channel Receive Path Register Read Write Address 201D Value after reset 00 SLIN 1 0 Select Line 00 Channel on DU frame sync FSC clock DCL or DCL 2 01 Channel on DD frame sync FSC clock DCL or DCL 2 10 Channel on SR frame sync RFS clock SCLK 11 Channel on ST frame sync TFS clock SCLK LMOD 1 0 Load Mode 00 When shift register contains one byte it is loaded into data receiver as soon as possible and in addition to DSP Host read register for monitoring XX When shift register contains n bytes XX 01 n 1 XX 10 n 2 XX 11 n 4 the contents is loaded into DSP
93. e Semiconductor Group 98 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description General Purpose I O Configuration Register Read Write Address 2030 Value after reset 00 IlOC 3 0 I O Line Configuration 0 pin GPx is open drain with internal pull up registers 1 pin GPx is push pull General Purpose I O Data Direction Register Read Write Address 2031 Value after reset 00 IIOD 3 0 I O Line Direction 0 pin GPx is input 1 pin GPx is output General Purpose I O Data Register Read Write Address 2032 Value after reset 00 IIOR 3 0 I O Line Data In a write access to GPR the value will stored in the GPR For those ports which are configured as output the value is driven on the corresponding pin GPx As aconsequence GPR can be initialized even before the coressponding pin is configured as output A read access to GPR will return the current status on the pin GPx independent of whether the pin GPx is configured as input or output General Purpose I O Strobe Register Read Write Address 2033 Value after reset 00 IIlOS 3 1 I O Strobe Select 0 input pin GPx is not strobed 1 input pin GPx performes strobed operation IIlOSO I O Strobe Mode 0 strobe mode is disabled GPO is used as general I O pin 1 strobe mode is selected only valid if GPO is configured as input If strobed operation is disabled the input pins are sampled continuously If strobed is selected input pins are latched during GPO 0 T
94. e chip and an external controller is supported by a full duplex 256 byte on chip mailbox communication memory The circuit is offered in a Quad Flat Pack package with 100 pins P TQFP 100 size 14 x 14 mm pitch 0 5 mm height 1 4 mm Note This Data Sheet gives a thorough description of the functions and hardware that forms the base of PSB 7230 It includes information that is not needed for the PSB 7230 as a ready to use plug and play G 723 G 711 audio compression device Semiconductor Group 7 Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction 1 3 Logic Symbol Parallel Host Interface r A N AD 7 A s Pf ROF Coy ALE INT INTR EA RESET R W DS Tm 4 RS Pd N ES SIO E 7 a DD SCLK o lt gt DU 1OM 2 2 i amp Interface etal SR S K DCL Audio x x Interface e X K 2 rm s B RFS Ko m lt gt PSB 7230 5 cui VDD gt VDDAP VDDP gt E xmi System Power d S N e i Clock Supply VSS y LL XTAL2 Interface VDDA gt J S gt QLKO VSSA VSSAP FA f SOE NZ Y V V Ed CA 0 15 CD 0 15 CRD CWR cPss CDS GPIO 0 3 N N External Memory Interface GP IO Interface Figure 1 Semiconductor Group 8 Data Sheet 1998 07 01 SIEMENS PSB 7230
95. e if PSB7230fH hy Fes SIEMENS ICs for Communications Joint Audio Decoder Encoder for Analog Videophone JADE AN PSB 7230 Version 2 1 Data Sheet 1998 07 01 DS 1 PSB 7230 Revision History Current Version 1998 07 01 Previous Version Prelimiinary Data Sheet 02 97 V 1 2 Page Page Subjects major changes since last revision in previous in current Version Version For questions on technology delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see our webpage at http www siemens de semiconductor communication IOM IOM 1 IOM 2 SICOFI SICOFI 2 SICOFI9 4 SICOFI 4uC SLICOFI ARCOFI ARCOFI BA ARCOFI SP EPIC 1 EPIC S ELIC IPAT 2 ITAC ISAC S ISAC S TE ISAC P ISAC P TE IDEC SICAT OCTAT P QUAT S are registered trademarks of Siemens AG MUSAC A FALC 54 IWE SARE UTPT ASM ASP DigiTape are trademarks of Siemens AG Edition 1998 07 01 Published by Siemens AG HL SP BalanstraBe 73 81541 Munchen Siemens AG 1998 All Rights Reserved Attention please As far as patents or other rights of third parties are concerned liability is only assumed for components not for applications processes and circuits implemented within components or assemblies The information describes the type of component and shall no
96. e that the receiver only receives the first byte of a packet and does not latch any further bytes in MONR until the beginning of the next packet Thus the conditions for latching the first byte of a packet is MRE 1 amp MX 0 after having been 1 in at least two consecutive frames Any further bytes are latched into MONR only if MRE x MRC 1 amp previously received byte has been read from MONR register amp MX 0 Write MONX Transmitted MX Received MR MXC 1 Be 01 E us N MDA int status Write MONX MDR int status Read MONR MRC 1 MDA int status L Write MONX gt MDR int status Read MONR MDA int status Seconde f EL gt MDR int status Write MONX e MXC 0 Read MONR MER int status s MRC 0 Figure 32 Semiconductor Group 72 Data Sheet 1998 07 01 PSB 7230 SIEMENS Functional Blocks Write MONX MDA int status MDA int status MDA int status MXC 1 Write MONX Write MONX MXC 0
97. e video processor uses DRAMs and SRAMSs to store data and program code The H 223 multiplexed data stream is either sent via the PCI interface to an external V 34 modem or via host or IOM interface to an on board modem e g Siemens ISAR 34 PSB7115 and ALIS PSB 4595 4596 The modem must be able to work in synchronous mode i e the H 223 multiplexed data shall be applied directly to the V 34 synchronous data pump When an external non integrated V 34 modem is utilized control between the modem and the terminal shall be via ITU T V 80 For the on board modem the ISAR 34 constitutes the data pump transferring the data with 33 6 Kbit s in both directions The ALIS chipset substitutes the conventional codec and DAA circuit Since the ALIS it is a programmable solution it can be configured by software to fit the approval requirements of all different countries thus one hardware solution can be produced for all markets over the world The decoupling between line and modem is done by capacitors instead of transmformers thus offering very small size and low cost implementations To achieve lip synchronization the audio may be delayed with respect to the video This is necessary because of the higher transmission delay caused by the video signal due to the elaborate H 263 video compression A delay of approximately 0 5 seconds is enough in most practical cases To make maximum use of the existing memory in the system the delay is perfor
98. eceived clocked by RFS pulses Semiconductor Group 107 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Channel Configuration Register 0 CCRO Read Write Address 26 Bit 7 Bit 0 CCRO PU RMSB XMSB PU Power Up Power down 0 or power up 1 RMSB Receive MSB first When RMSB 0 the least significant bit of a byte in the receive FIFO is the bit first received normal mode in serial data communication protocols When RMSB 1 the most significant bit of a byte in the receive FIFO is the first bit received XMSB Transmit MSB first When XMSB 0 the least significant bit of a byte in the transmit FIFO is the bit first transmitted normal mode in serial data communication protocols When XMSB 1 the most significant bit of a byte in the transmit FIFO is the first bit transmitted Channel Configuration Register 1 CCR1 Read Write Address 274 Bit 7 Bit 0 CCR1 RCSO RSCO RFDIS XCSO TSCO XFDIS RCSO Receive Clock Shift 0 Together with RCS2 and RCS1 in TSAR determines the clock shift relative to the frame synchronization signal A clock shift of 0 7 is programmable XCSO Transmit Clock Shift 0 Semiconductor Group 108 Together with XCS2 and XCS1 in TSAX determines the clock shift relative to the frame synchronization signal A clock shift of 0 7 is programmable Data Sheet 1998 07 01 SIEMENS PSB 7230 RSCO RFDIS TSCO
99. ed Interrupt from Host to DSP A write operation by the Host to address 50 INH causes a maskable INH interrupt status to be generated on INT1 to the DSP and the Interrupt Host Busy bit INHB address 50 readable by host to be set to 1 Having recognized an INH interrupt status the DSP firmware reads address 3050 INH This read operation automatically resets the HINT interrupt status bit in the DSP Interrupt Status Register for INT1 address 3074 The INHB bit can be written by the DSP again to 0 to indicate that it is ready to accept a new interrupt from the host which it would usually but not necessarily do after it has read the INH register The 16 bit Control register located at 60 61 3060 3061 may contain additional information for the DSP to read after an INH interrupt Please refer to the specific interface procedures for details Interrupt from DSP to Host For a soft interrupt from the DSP to the host the procedure is identical In this case the soft interrupt is a maskable interrupt on line INT The interrupt vector is written by the DSP in address 3058 IND Simultaneously the Interrupt DSP Busy bit INDB address 58 writable by host is set to 1 Having recognized an IND interrupt status the host reads address 58 IND which automatically resets the DINT interrupt status bit in the Host Interrupt Status Register for INT address 75 The INDB bit can be written by the host again to
100. ed by bits HAH1 The maskable interrupt status bits for controlling the transfer are BFHR Buffer full for data receiver new data can be read from HRR and written into HRW BFHX Buffer full for data transmitter new data can be read from HXR and written into HXW The block diagrams for the receive and transmit data Controller channel are shown in Figure 25 and Figure 26 Semiconductor Group 59 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks Receive nee DSP Host DSP HRRx i c HRWx Time slot SLIN parameters RAC 32 bits 32 bits 2 s k f RMSB LMOD 00 T gt bit reversal 00 DU DCLU2 gt x Time slot M FSC M frame sync Count TS Clock 01 DD ES as gt Logic gt Shift Register lt U RFS ser clock A 10 U 1 2 or 4 bytas on T _SCLK ES gt X 7 E TFS ain Buffer SCLK ai 2 y 1 lt ST LMOD BFHR acd Bit level functions N Data RFIFO N Receiver Figure 25 Caption to the Figure The data from the shift register is loaded into DSP accessible read registers and simultaneously into physically separate host accessible read registers Data to the receiver is loaded from the transmit channel register accessible from the DSP if HHR 0 or the register accessible from the host if HHR 1 The control bit HH
101. ed by the following bits XAC Transmitter Active In transparent mode when XAC is set to 1 transmission of bytes from the transmit FIFO starts time slot aligned if the transmit time slot length is a multiple of 8 bits XF Transmit Frame Initiates transmission of an entire frame or part of one up to 32 bytes XRES Transmitter Reset Resets the data transmitter clears the transmit FIFO and generates an XPR status after the command has been completed XNEW Transmitter Restart Resets the transmitter state machine without any loss of data i e FIFO data The transmission of the current frame can be restarted with the first bit of the start flag After up to 32 bytes have been written to the FIFO transmission is started by issuing the XF command The data controller requests another data block by an XPR interrupt status if there are no more than 32 bytes in the FIFO To this the software responds by writing another pool of data and issuing a transmit command XF for that data If transmission of earlier data or of a previous frame is still underway when a new transmission command XF is issued software access to the FIFO is blocked until the first transmission is completed If the transmit FIFO runs out of data the host will be advised by a Transmit Data Unterrun XDU interrupt status Semiconductor Group 66 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks 4 4 IOM 2 Functions The IOM
102. el transmitter implements the so called Maximum speed option of this protocol whereby the acknowledgment of every byte except the first by the receiving end is anticipated This means that an MDA interrupt status is generated as soon as the received MR bit is detected to go from 0 to 1 Transmission of the next byte is started as soon as the software has reacted to this interrupt Thus a maximum transfer speed of 32 Kbit s can be obtained Semiconductor Group 70 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks Each data byte is transmitted at least twice only twice if the receiver is fast enough so that the transmitter works at maximum speed namely once when MX is 1 and once when MX is 0 in the next frame The only exception is the first byte which is transmitted in three consecutive frames where MX 1 0 0 respectively In order for the transmitter to recognize that the receiver has correctly acknowledged the last byte the interrupt status MEA is set after the received MR bit is received at 1 in two consecutive frames interrupt status different from MAB The condition for generating an MEA interrupt status is the recognition of a MR 0 1 1 sequence when MXC 0 125 us inact MX in Jf Packet end Latch Latch Latch Latch Rec Rec Rec Rec Data Data Data Data inact MR out act Ack Ack Ack 1st 2nd n th Byte B
103. end the corresponding acknowledge interrupt IND 32 The VocFin interrupt status in the IND register is overwritten by that If the host was busy between VocFin and the acknowledge of WCB it will only receive one interrupt and recognize the later one which is the IND 32 To recognize that it has missed one VocFin interrupt the host should check the VocoderFinished backup register 61 If the value of this register has toggled it knows that there has been a VocFin before the IND 32 interrupt and must continue to service it Note A parallel read write access of the 3061 61 register is not prohibited by hardware Thus an invalid value maybe read by the host when it reads the register at the same time as the JADE AN writes it As a consequence the host has to implement a double last look regarding this register i e it has to read the contents until it has read the same value in two consecutive read accesses only then it is ensured that the value is valid 3 Read JADE Status Conflict with VocoderFinished Case 1 If a Read JADE Status RS interrupt handshake is initiated by the host immediately before the next time frame starts and is not completed at the time the new VocFin interrupt should occur the VocFin is delayed until the RS is finished Due to audio delay reasons the JADE AN has small internal buffers for the compressed data This leads to an overwriting of audio data very soon after a VocFin is delayed It is ens
104. eocodec VCP of 8 x 8 Inc formerly IIT Inc as well as host based solutions Outband controlled audio protocol with optimized data rate Stable reaction on interrupt handshake timing violations of e g a slow host Windows PC P TQFP 100 System On Chip Functions One universal serial transparent data controller OM 2 Monitor and C I channels Generation of programmable system clock output Interfaces 4 line IOM 2 PCM interface programmable master or slave 5 line serial audio interface e g for connection to Videocodec H 221 223 processor Parallel 8 bit Host interface 4 line general purpose interface Type Ordering Code Package PSB 7230 Q67101 H6864 P TQFP 100 Semiconductor Group 5 Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction Control Programmable via Parallel Host Interface Operating parameters and mode settings via a register bank Access to audio channels and serial transparent data controller from DSP or an external Host Interface to external software via a full duplex 256 byte on chip mailbox H 221 H 223 oriented inband configuration mode switching General Supply voltage 3 0 3 6 V Additional 4 5 to 5 5 V supply for connection to 5 V systems without external components Ambient temperature range 0 C to 70 C P TQFP 100 package 1 2 Overview The PSB 7230 Joint Audio Decoder Encoder for Analog Videophones JADE AN is
105. equired to clear the JADE s pipeline During that time the JADE AN will reorganize its memory if required and re initialize internal variables Note When a mode change is requested by the user without sending four neutral packets before the JADE AN may not work stable Commands The following section defines the commands which are sent from the user to the JADE AN Any changes in mode affects the input pipeline stage in the next 10 ms time slot 1 Command header word 94179 1139574 85 01 A 0 0 00 0 0 0 1 1 1 1 2 Checksum The sum of the six following words regarded as signed 16 bit values in the command header If the checksum is wrong no modes or options are changed and an error status is sent back in the next status header Semiconductor Group 134 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features 3 Set Mode XIXIX XIX X X x EMS8 EM2 EM1 EMO DM3 DM2 DM1 DMO Audio modes for encoder EMO 3 and decoder DMO 3 The following modes are defined Table 23 RESET special full word definition of the command mode Reset is defined as OxFFFF and returns the JADE to its power on default state 0 Neutral mode only command and status header information is exchanged Pass through 16 bit linear 8 kHz sampled data G 711 8 kHz sample rate A law encoding decoding G 711 8 kHz sample
106. erated or not independently of the corresponding mask register The mask register only decides whether an interrupt at INT line is generated After having recognized an IND interrupt status the polling host may read out the register 58 to get the interrupt number Note Some special situations have to be considered if one uses a slow host that cannot always ensure to finish the whole interrupt handshake in one frame period default 10 ms i e before the next VocoderFinished interrupt is generated by the JADE Collisions between not finished interrupts and the new VocoderFinished Interrupt may occur Interrupt Conflicts with a Slow Host In the following some special situations and the recommended handling are described to keep the host protocol stable also in situations where the host has not finished its interrupt requests before the beginning of the next time frame as long as the interrupt service delay is less than 160 ms The following descriptions apply for all encoder decoder modes If the interrupt service from the host is delayed by up to 160 ms none of the Interrupts during this time usually only one VocoderFinished every 10 ms is lost but they are delayed too until the host is able to service them Thus after a gap in interrupt service a burst of interrupts has to be serviced by the host Note G 723 mode During the interrupt burst to catch up for the delayed host interrupt service the number of interrupts ensures pro
107. eriods from each other are generated When STX command is given generation of pulses starts at the next possible 16 bit boundary This function may be used in connection with the data controller when a predefined number of data units e g words are transmitted clocked by TFS pulses Semiconductor Group 105 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Mode Register MODE Read Write Address 22 Bit 7 Bit 0 MODE 1 RAC XAC TLP ERFS ETFS RAC Receiver Active Sets the receiver in an active state Note When RAC is set to 1 storage of bytes in the receive FIFO starts time slot aligned if the receive time slot length is a multiple of 8 bits XAC Transmitter Active When XAC is set to 1 transmission of bytes from the transmit FIFO starts time slot aligned if the transmit time slot length is a multiple of 8 bits When XAC 0 the time slot assigned to the transmitter is in high impedance TLP Test Loop When 1 output of the data controller is connected to input i e what is transmitted is simultaneously received The loop is transparent ERFS Enable RFS generation Only valid when RFIN 0 RFS pulses internally generated and used if RCONT bit in RFS mode register is 1 When RCONT 1 an ERFS value of 1 enables the generation of RFS pulses of one bit duration and spaced RPRD 1 1 32 16 bit words from each other Pulses are generated indef
108. esses for the different internal register banks and memories are given here and in the rest of this Data Sheet both as seen from the host and from the embedded DSP the latter information being included for the sake of completeness only Directly Accessible Register Bank DARB The Host accesses directly via its 8 bit address bus the so called Directly Accessible Register Bank DARB located between DSP addresses 3000 and 30FF Host Address ADO AD7 DSP Address MSB LSB Coh 30COh Unused Directly mm 80h 3080h P Accessible h h Yi Register 40 3040 Z Bank 00h 3000h Figure 12 This area is in turn divided into four blocks of 64 bytes each according to their functions An overview of the functions of these 64 byte areas is given in Figure 13 please refer also to the appropriate chapters for a detailed description 1 Locations for reading and writing samples in real time from to the serial interfaces IOM 2 and Serial Audio Interface Input Output area 2 Area for communication between the host and the embedded DSP for programming parameters and reporting status conditions DSP Host Com area 3 Register bank for Serial Data Controller accessed by host if HHA1 Configuration bit is 1 SDATA 4 Reserved for future expansion Semiconductor Group 34 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization Host DSP MSB LSB Reserved 30C0h
109. face has been setup starts with the last part of the finishing handshake procedure 3 3 see figure and table below For the handshake procedure of the compressed audio see Figure 47 Semiconductor Group 146 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Host Host Interrupt Handshake 1 3 Compressed Audio Ce a CIO Host DSP Jade Start 4000h 00h Mese ru gt Mailbox mailbox eee nee IND Sone INT NDE alternating COh 80h compressed audio 80h from JADE to host gt Get Interrupt number lt an lt Initialize mailbox start address 4Ch Read compressed xxh audio from mailbox set INDB 0 00h Initialize mailbox start address aen lt Write compressed audio into mailbox Interrupt lt INT1 INHB 1 NH 3050n 50h Interrupt request Acknowledge Get Interrupt lt compressed audio number from host to JADE Start 4000h 00h read compressed audio packet from mailbox Mailbox set INHB 0 a a mc ccce Seehe she stricto ete chet ctesete te tote shee heehee tea een te bees he eke k etek ite RE Figure 47 This procedure is nearly identical with the interrupt handshake when in IOM Host mode see Chapter 6 2 3 2 and the following steps are perfomed Semiconductor Group 147 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features
110. ge INT MSB 30764 Acknowledge 76 Acknowledge INT INT LSB 75 Interrupt INT Interrupt INT Mask MSB Status MSB 30744 Interrupt INT Interrupt INT 74 Interrupt INT Interrupt INT Mask Status Mask LSB Status LSB 73 Acknowledge INTR 3072 Acknowledge INTR 714 Interrupt Interrupt INTR Mask INTR Status MSB MSB 3070 Interrupt Interrupt 70 Interrupt Interrupt INTR Mask INTR Status INTR Mask INTR Status LSB LSB 6C reserved reserved 6A reserved reserved Semiconductor Group 39 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization Table 10 Address Mapping of DSP Host Com Area Multiplexed Mode cont d DSP DSP Write DSP Read Host Host Write Host Read Address _ always always 16 Address always 8bit always 8bit 16bit wide bit wide ADO 7 wide wide 30614 Cntrl DSP gt Cntrl Host gt 61 Cntrl Host gt Cntrl DSP gt Host MSB DSP MSB DSP MSB Host MSB 30604 Cntrl DSP Cntrl Host gt 60 Cntrl Host gt Cntrl DSP gt Host LSB DSP LSB DSP LSB Host LSB Note Read and write accesses to 3060 and 3061 from the DSP are 8bit wide only 30584 IND Interrupt INDB LSBit 584 INDB LSBit IND Interrupt Status Status 30504 INHB LSBit INH Interrupt 504 INH Interrupt INHB LSBit Status Status 4C Mailbox IO Mailbox IO write read 4A Mailbox write address 48 Mailbix read address 47
111. ginning of the physical frame on ST When input Sampled with a falling edge of SCLK When output Clocked out with the rising or falling edge of SCLK duration 1 SCLK period Repetition rate continuous mode or number of pulses burst mode is programmable SCLK is derived from the chip internal DSP clock via a programmable baud rate generator division factor 1 2 3 1024 The Receive Frame Sync RFS when programmed as output has two selectable modes of operation Inthe continuous mode CONT 1 pulses are continuously generated separated by a distance 16 x PRD 1 bits from each other where PRD 0 255 In the burst mode CONT 0 pulses are generated upon command a programmable number of times REP 1 1 1024 spaced 16 bits apart from each other The same applies to TFS when it is an output Semiconductor Group 31 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization Channels Audio receive and transmit channels Independently programmable on SR ST DU or DD with programmable locations start at bit 1 512 and lengths 1 32 bits with respect to RFS TFS Data receive and transmit channels Independently programmable on SR ST DU or DD with programmable locations start at bit 1 512 and lengths 1 256 bits with respect to RFS TFS 3 1 3 Parallel Host Interface The parallel host interface can be selected to be either of the 1 Motorola type with
112. gt Cntrl DSP gt 46 Ext Memory DSP LSB Host LSB Data low 044 INDB LSBit IND Interrupt 454 Ext Memory Status Addr high 03 INH Interrupt INHB LSBit 44 Ext Memory Status Addr low 02 Mailbox IO Mailbox IO write read 01 Mailbox write address 41 Reg Data Reg Data Host gt DSP DSP Host 00 Mailbox read address 40 Conf Cont RDY LSBit Reg Address The shaded registers are mapped to the demultiplexed mode and can be accessed in demultiplexed mode by using address pins A 0 2 i e addressing 00 to 07 Using A3 gives an additional way of accessing the DSP Host Communication area by 2 registers only The address register 08 is written with the target address from the multiplexed mode and the data register 09 contains the corresponding value or can be written with a new value for the target address The function of the registers 00h to 07 is the same as described in Chapter 3 3 2 1 Semiconductor Group 48 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks 4 Functional Blocks 4 1 Oscillator and Baud Rate Generator Clocking Modes The clock generator including PLL generates the internal master clock derived from an input clock or crystal on pins XTAL 1 2 Because of integrated decoupling capacitors DC components of the input frequency on XTAL 1 2 are filtered out Consequently for a crystal input nearly a sinusoid an internal clock of nearly 50 duty cycle results The different cl
113. he latch is closed when GPO 1 Semiconductor Group 99 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description General Purpose Interrupt Status Register Read Address 2034 Value after reset 00 IOINTS 3 0 Input Interrupt Status Register 0 no state change is detected on pin GPx 1 a state change 0 1 or 1 0 is detected on pin GPx A maskable interrupt from any of the GPx pins is generated to the host if the GPI mask bit in register 74 is enabled General Purpose Interrupt Mask Register Read Write Address 2035 Value after reset 00 IOINTM 3 0 Input Interrupt Mask Register 0 a 1 in IOINTSx does not generate an INT1 to the DSP 1 a 1 in IOINTSx generates an INT1 to the DSP Semiconductor Group 100 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description 5 4 Serial Data Controller Registers As mentioned previously the addresses for the Data Controller registers are given here for the DSP for completeness only since they are only relevant for the on chip firmware The access to the register banks of the data controller is determined by the Data Controller Access from Host bit HAH1 When HAH is 0 the DSP is allowed to access the Data Controller register bank and thus to service the data controller When HAH is 1 the Host is allowed to service the data controller Host Address DSP Address AQ A7 If HAH1 1 If HAH1 0 MSB LSB BER nel SD
114. ical Specification SCLK lt TFO gt TFO TFS RFS out 7 Figure 73 Table 40 Parameter Symbol Limit Values Unit min max TFS RFS out fgg 40 ns 7 7 5 External Memory Interface No external SRAM needs to be connected to the JADE since it has all memories on chip Nevertheless an external memory interface is implemented for development purpose only The timing of this interface is not part of the test procedure for the JADE and so not specified at this point For development purpose especially tested devices including external memory interface test are available from Siemens on request in small quantities These devices are working under special conditions such as e g higher supply voltage Semiconductor Group 178 Data Sheet 1998 07 01 SIEMENS PSB 7230 Package Outlines 8 Package Outlines P TQFP 100 Plastic Thin Quad Flat Package 8 8 5 3 8 8 39 S re ZR g IE ol Jg ry li i Hs S 0 c10 08 i 0 22 0 95 80 08 0A BDICh00x Index Marking 1 Does not include plastic or metal protrusion of 0 25 max per side S A A 9 Sorts of Packing Package o
115. ideo quality the audio should require only a small fraction of the total data rate This is made possible by using parametric compression techniques such as ACELP 5 3 Kbit s or MP MLQ 6 3 Kbit s Above all the corresponding norm G 723 is an internationally adopted standard so that compatibility between equipment from different manufacturers is ensured Semiconductor Group 16 Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction 1 6 1 H 324 Desktop Videoconferencing Solution for POTS An H 324 desktop videoconferencing solution for POTS plain old telephone system line as a PCI card for commercial PC s is shown in Figure 4 ARCOFI SP ALIS oe tip ring SIEMENS SIEMENS PSB 4 Stereo DAC optional SRAM DRAM JADE AN ISAR 34 Video in Video out SIEMENS SIEMENS PSB 7230 PSB 7115 Video i Capture Bus Interface NTT 34 Modem T PCI Bus oo meam access tip ring either an on board modem or an external modem may be used Video Codec PAL NTSC Camera Figure 4 The connection to the POTS line can be done either by an on board modem or an external V 344 modem that is capable of synchronous data transfer In the case of the modem on board the videophone can be regarded as an add on modem feature The JADE AN and the video codec chip e g the Video Communication Processor VCP from 8 x 8 Inc constitute the heart of the videophone Both together with the modem are
116. ing an internal buffer mechanism This allows single SIO periods to vary by 15 Please refer to Figure 55 T 80 2 FSC periods f z8KHz T T s D m a t SIO Tsmax Tsmin T 1596 Figure 55 Semiconductor Group 163 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features The full definition is as follows Long term SIO period T T 10 ms 0 25 ms Short term SIO period Ts Ts T x 15 1596 10 ms 1 5 ms Duration of n consecutive SIO periods n nza 0x7 7 i l The basic clock for the definition of ms is the frame sync signal FSC of the uncompressed audio interface Note For maximum audio quality it is recommended to keep the skew between the IOM 2 and the SIO time base as small as possible i e to adjust T in the above definition as close to 10 ms as possible In an application with the VCP from 8x8 formerly IIT like in the Siemens 8x8 demonstration board design the SIO interrupt period is locked to the IOM 2 time base after a call is setup so no compensation on the uncompressed audio needs to be done by the JADE AN any more This ensures the maximum possible audio quality Semiconductor Group 164 Data Sheet 1998 07 01 SIEMENS PSB 7230 Electrical Specification 7 Electrical Specification 7 1 Absolute Maximum Ratings Table 27 Parameter Symbol Limit Values Unit Ambient temperature under bias Ty 0 to 70 C Storage tem
117. initely until ERFS is set to 0 again ETFS Enable TFS generation Only valid when TFIN 0 TFS pulses internally generated and used if TCONT bit in TFS mode register is 1 When TCONT 1 an ETFS value of 1 enables the generation of TFS pulses of one bit duration and spaced TPRD 1 1 32 16 bit words from each other Pulses are generated indefinitely until ETFS is set to 0 again Semiconductor Group 106 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Receive Command Register RCMD Write Address 25 Bit 7 Bit 0 RCMD RMC RRES STR RMC Receive Message Complete Acknowledges a previous RPF status Frees the FIFO pool for the next received frame or part of a frame RRES Receiver Reset When RAC 1 this command resets the data receiver and clears the receive FIFO When RRES is issued while RAC 0 this command initializes in addition the time slot count logic for this channel STR Start command for RFS generation Only valid when RFIN 0 RFS pulses internally generated and used if RCONT bit in RFS mode register is 0 When RCONT 0 when STR is set exactly RREP 9 0 pulses of one bit duration and spaced 16 bit periods from each other are generated When STR command is given generation of pulses starts at the next possible 16 bit boundary This function may be used in connection with the data controller when a predefined number of data units e g words are r
118. ion MP MLQ 6 3 Kbit s or Algebraic Code Excited Linear Prediction ACELP 5 3 Kbit s The high pass filter and the postfilter of the G 723 may be independently switched on or off The implementation complies with the newest ITU T C Code V5 1 and contains Voice Activity Detection VAD Comfort Noise Generation CNG and Discontinous Transmission DTX Serial H 221 223 Oriented Audio Protocol The PSB 7230 supports a serial H 221 223 oriented inband controlled audio protocol for direct connection to a Videocodec e g VCP of 8 x 8 Inc which means the control data for compression mode volume etc is sent in a header preceeding the compressed data This protocol provides an outband synchronization of the audio bit streams by using block structures for the compressed audio data Semiconductor Group 27 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization 3 Interfaces and Memory Organization 3 1 Interfaces 3 1 1 IOM 2 Interface Electrical interface The IOM 2 interface is a 4 wire interface with two data lines DD and DU programmable open drain or push pull a data clock line DCL input output and a frame sync signal FSC input output The data clock is by default equal to twice the data rate Double rate However DCL may be set equal to the data rate Single rate by programming In terminal applications the bit rate on the interface is normally 768 Kbit s in line card applications it is 2048 Kb
119. ion is described in Chapter 6 2 3 3 After the initialization phase is completed the JADE can be started in the default mode or be reprogrammed and then started Note The firmware features are using interrupt handshakes via the registers INH Host write to 50 and IND Host read from 58 A polling host should not directly poll the IND interrupt status register 58 but the DINT bit in INT interrupt status register 75 This bit always shows whether an interrupt from the DSP has been generated or not independently of the corresponding mask register The mask register only decides whether an interrupt at INT line is generated After having recognized an IND interrupt status the polling host may read out the register 58 to get the interrupt number Semiconductor Group 113 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features 6 1 Basic Functions 6 1 1 Firmware Version Number To obtain the version number of the on chip firmware the following interrupt handshake procedure has to be implemented by a host Read Firmware Version Number ee Host Jade i Interrupt lt INT1 INHB 1 we 3050 50h Interrupt request for status data i Get Interrupt lt i f number Write version pd neon number into 60h y Poll INHB status set INHB 0 until O Read version number Figure 38 The following steps
120. iour switching from neutral to G 711 and vice versa Semiconductor Group 138 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Note The encoder data is input through the uncompressed interface and output through the compressed interface The decoder data is input through the compressed interface and output through the uncompressed interface The Data Bytes see Table 25 transferred together with the control status information refers only to the compressed interface Table 25 Control Status Pipeline for G 711 Identical for Pass Through Packet Control User Status JADE AN Comment 10 ms to JADE AN to User MODE OPT1 Data MODE OPT1 Data Bytes Bytes 1 00 00 0 00 00 0 Neutral status after Reset 2 22 00 0 00 00 0 Command G 711 A law encode amp decode 3 22 00 80 00 00 0 First G 711 A law encoded data to JADE AN 4 22 00 80 00 00 0 5 22 00 80 22 00 80 First G 711 A law en decoded data from JADE AN 6 22 00 80 22 00 80 7 00 00 80 22 00 80 Command Neutral Mode at least 4 times last G 711 data to JADE AN 8 00 00 0 22 00 80 9 00 00 0 22 00 80 Last G 711 A law en decoded data from JADE AN 10 00 00 0 00 00 0 4th neutral packet next can change mode 11 33 05 0 00 00 0 Command G 711 u law with Loop 5 12 33 05 80 00 00 0 First dummy G 711 p law encoded data to JADE AN 13 33 05 80 00 00 0 Semiconductor
121. is implemented in the JADE AN This means that the mode settings for the JADE AN are usually done before audio data exchange is started using the procedure described in section Section 6 2 1 1 During audio data transfer the JADE AN keeps its current mode settings and only compressed audio is exchanged Compressed Audio Protocol with Outband Control The size and format of the 10 ms compressed data packets is summarized in Table 18 for the various operating modes Table 18 Compression Mode Compressed Data Packet Valid Bits Per Byte Size in Bytes Neutral 0 0 8 kHz pass through 160 8 G 711 80 8 G 723 6 3 Kbit s 8 8 G 723 5 3 Kbit s 8 0 G 723 Silence Insertion 8 8 0 Descriptor SID packets G 723 untransmitted 8 0 packets Always the most significant bits of a byte are valid and the least significant bits are ignored All different G 723 packets are transmitted with the same number of bytes which is determined by the 6 3 Kbit s mode This is to make the protocol simple not to minimize the data rate Please refer to the drawing below for details In G 723 mode the natural frame size of 30 ms is split up into three 10 ms packets To simplify the protocol handling all different G 723 modes are transmitted with the same data rate Please refer to Figure 45 for sub frame numbering with P 1 0 bits and valid bytes per packet in the corresponding G 723 packets D Semiconductor Group 130 D
122. is not mandatory and may be skipped The host writes a packet of uncompressed audio 2 5 ms into the mailbox using the procedure described in Section 3 4 The host generates an interrupt ot the JADE by writing value 02 into INH interrupt status register at address 50 The JADE reads the uncompressed audio data from the mailbox After the above procedure has been repeated four times the finishing procedure is executed see Figure 49 Semiconductor Group 150 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Host Host Interrupt Handshake 3 3 Finishing Procedure EEE EERE ET EE eee CEE EEE REET RESET ETI SEE EES Host Jade DSP Set INHB 0 Interrupt request IND 3058h 58h INT INDB 1 Acknowledge gt 04h l gt Interrupt data exchange for current frame gt Get Interrupt finished ani d i set INDB 0 not mandatory Start in first frame Any other interrupt request from Host e g Status Read or Control Write INT1 INHB 1 INH 3050h 50h Interrupt request Interrupt lt 05h i Host is ready for Get Interrupt lt next i number l VocoderFinished set INHB 0 Figure 49 The following steps are executed Semiconductor Group 151 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features 1 The JADE generates an interrupt at INT li
123. is the following header excluded Semiconductor Group 133 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Table 22 Mode Compressed Words Bytes Neutral 0 0 G 723 4 8 G 711 40 80 8 kHz pass through 80 160 D The 8 kHz pass through mode is not available when Host Host is selected as interface combination for compressed uncompressed data The communication between user and JADE AN starts in the neutral mode To initiate transfer of speech data the user sends a command data structure set to the desired compression mode s in a neutral size packet The mode change affects the JADE s input pipeline stage in the next 10 ms period This means that if the decode mode changes the next packet from the user will change in size corresponding to the new decode mode while if the encode mode changes the third packet from the JADE AN will be affected packets from the JADE AN represent the output stage of the pipeline As a general rule any changes to the current operating mode or options volume mute etc transferred to the JADE AN from the user take effect on the input captured on the next 10 ms boundary To change compression modes the user must first send four neutral mode command packets The first neutral mode command will be in a full size packet per the current operating mode while the following neutral mode command packet does only contain the 8 words header Two neutral packets are r
124. it s for details see IOM 2 Interface Reference Guide However the data rate may be different between 16 Kbit s and 4 096 Mbit s and the DCL rate correspondingly between 16 kHz and 4 096 MHz since the interface can be considered as a general purpose TDM Time Division Multiplex highway The total number of time slots on the interface is not explicitly programmed instead the FSC signal at repetition rate 8 kHz always marks the TDM physical frame beginning See Figure 10 for both IOM clock rates CRS 0 1 CRS 0 DCL lt CRS 1 thold FSC out DU DD out X X X 1gt bit X 2ndbit X 3rdbit X X X sample DU DD in X X X istbit X 2ndbit X 3rdbit X Figure 10 Semiconductor Group 28 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization DCL Bits on DU DD are clocked out with the rising edge of DCL and latched in with the falling edge of DCL Frequency 16 kHz to 4 096 MHz FSC 8 kHz Marks the beginning of the physical frame on DU and DD The first bit in the frame is output after the rising edge of FSC The first bit in the frame is latched in with the first falling edge after FSC has gone high if CRS 1 or after the second edge at 3 4 if CRS 0 Channels The following channels may be programmed on the IOM 2 interface one receive audio channel one transmit audio ch
125. itive power supply voltage 3 0 3 6 V for Clock Generation Unit PLL The power supply for the PLL requires pin 87 connected to Vppap In former versions of the JADE family pin 87 was connected to Vppp 88 Vosap Separate Ground 0 V for Clock Generation Unit PLL Semiconductor Group 15 Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction 1 6 System Integration Example of integration in videophones for analog telephone line The first example represents a low cost solution for a desktop stand alone videophone that connects to an analog telephone line The analog telephone line can carry up to 28 8 Kbit s using a V 34 modem or 33 6 Kbit s using a V 34bis modem The general aspects of videotelephony over analog telephone lines are covered by ITU T H 324 recommendations The video is compressed according to the H 263 recommendation The compressed video and audio signals are multiplexed together with additional control information into a single communication link The multiplexing is specified by the H 223 recommendation see Figure 3 CCD Camera i Video Codec lt gt LCD Monitor J Lia EMU DEMUX Modem Analog Network TEN H 223 vava lt KS R Voice Codec Audio mms SNEG G 723 lt Delay m aS NER System Control H 324 Figure 3 In order to make the best possible use of the total bandwidth and obtain the best possible v
126. ket G 723 Silence 5 0 5 1 10 Silence packet with Insertion Descriptor filter coefficients SID packets same for 6 3 and 5 3 Kbit s mode G 723 5 0 5 1 11 Silence packet untransmitted without any data packets same for 6 3 and 5 3 Kbit s mode Note Independently of the interface selection for the compressed audio always the most significant bit of the most significant byte is transferred first e g when using pass through modes the 16 bit samples are split up into two bytes and the most significant bit of the most significant byte is transferred first big endian 6 2 1 3 Compressed Audio Protocol with Inband Control The following paragraph describes an H 221 H 223 oriented protocol which transfers the control information inband with the compressed audio data The user sends commands and data and the provider sends status and data Commands and data or status and data are grouped into blocks of 16 bit words Between the user and the JADE AN one data packet is transferred each way every 10 ms The packet that is transferred from the video processor to the JADE AN called command data consists of eight command words followed by the appropriate number of data words for the current speech algorithm Semiconductor Group 132 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Table 20 Command Data Structure 0 Command header word 1 Checksum of words 2 7 2 Set mode
127. ll on going STX is reset to O 16 bit periods after the last TFS pulse has been generated This function may be used in connection with the data controller when a predefined number of data units e g words are to be transmitted clocked by TFS pulses Semiconductor Group 104 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Transmit Command Register XCMD Write Address 20 Bit 7 Bit 0 XCMD XF XRES XNEW STX XF Transmit Frame Initiates transmission of a pool of data up to 32 bytes XRES Transmitter Reset When XAC 1 this command resets the data transmitter clears the transmit FIFO and generates an XPR status after the command has been completed When XRES is issued while XAC 0 this command initializes in addition the time slot count logic for this channel XNEW Transmitter Restart When set to 1 during the transmission of the first FIFO including the start flag the transmitter state machine is reset to the starting state without any loss of data i e FIFO data XAC is reset to 0 automatically When XAC is reprogrammed to 1 the transmission of the current frame is restarted with the first bit of the start flag STX Start command for TFS generation Only valid when TFIN 0 TFS pulses internally generated and used if TCONT bit in TFS mode register is 0 When TCONT 0 when STX is set exactly TREP 9 0 pulses of one bit duration and spaced 16 bit p
128. m Status and control information to from the JADE can be transferred either inband the compressed audio data via the corresponding selected interface or outband using an 8 bit parallel host interface The audio frontend data can be exchanged either through the host interface or the IOM 2 interface In the latter case the Siemens ARCOFI SP can be connected providing half duplex handsfree or a Siemens ACE acoustic echo canceller circuit together with an ARCOFI BA providing full duplex handsfree The default configuration of the JADE is such that in a videoconferencing system using the 8x8 formerly IIT VCP Video Codec and Multimedia Communications Processor the Siemens PSB 7230 can work standalone without the need of external initialization l e no host is needed in this case and the full communication is automatically started between the VCP and the Siemens PSB 7230 The voice compression algorithms are implemented by an embedded 16 bit fixed point Digital Signal Processor with all memories internal and no external memory needed Integration of these and other features as well as perfectly matched interfaces with other ICs allows for the implementation of highly optimized low cost system solutions e g for Videophones Data over voice and Channel Multiplexing equipment For system integration a serial data channel is implemented which can be serviced by an attached host or the on chip DSP System functions and communication between th
129. mbedded DSP respectively RC1 XC1 HR1 HX1 channel registers are located in the address range 00 3F for the Host and in the memory mapped area 3000 303F for the DSP The register banks for the Host and the DSP are physically separate from each other The read registers and write registers are physically separate The addresses for these registers are such that a 32 bit sample can be accessed from the DSP via only two 16 bit read write operations 16 bit data bus From the Host the access is byte by byte 8 bit data bus List of Registers RC1 32 bit register for audio receive channel 1 read XC1 32 bit register for audio transmit channel 1 write HRR1 32 bit register for reading data from Data Receiver input shift register HRW1 32 bit register for writing data to be loaded into Data Receiver input HXR1 32 bit register for reading data from Data Transmitter output HXW1 32 bit register for writing data to Data Transmitter output shift register Semiconductor Group 36 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization Memory Map Access from the Host COh BEES Reserved 80h SDATA 40h DSP Host Com Input Output 00h Host Address A0 A7 Host Write Host Read 17h HXW1 31 24 HXR1 31 24 16h HXW1 23 16 HXR1 23 16 15h HXWA 15 8 HXR1 15 8 14h HXW1 7 0 HXR1 7 0 13h HRW1 31 24 H
130. med by the video processor with its external RAMs When decoding MPEG bitstreams the audio D A conversion is provided by a stereo audio DAC Semiconductor Group 18 Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction 1 6 2 Low Cost H 324 Desktop Videoconferencing with Software Video A low cost solution of the previous board does the video encoding decoding in software on the host See Figure 5 for low cost H 324 desktop videoconferencing ARCOFI SP ALIS m tip ring SIEMENS 4 SIEMENS PSB 4595 PSB 2169 PSB 4596 JADE AN ISAR 34 SIEMENS SIEMENS Vid Video in cp Capture PSB 7230 PSB 7115 PAL NTSC Camera PCI Bus IF PCI Bus V 34 Modem synchronous access tip ring Video Compression by Software on Host either an on board modem or an external modem may be used Figure 5 The V 34 modem can be either on board thus building a modem with additional videophone functionality or an existing external modem can be used For a description of the ISAR 34 data pump and the ALIS programmable codec and DAA worldwide solution see Chapter 1 6 1 The audio compression is done by the JADE AN thus providing high quality audio without noise or gaps when the operating system of the host processor is busy For example when opening a DOS Shell in a Microsoft Windows operating system the JADE AN enables the system to have continous audio without gaps or clicks Semic
131. n the following as a function of LMOD C s means the number of clock edges inside the active time slot C means the number of clock edges independent of the active time slot Table 13 Receiver Delays Start amp Stationary LMOD 00 8 Cr 9C LMOD 01 16 Cig 9C LMOD 10 32 Cig 17 C LMOD 11 64 Cts 33 C Similarly latencies apply in the case of the data from the output of the data transmitter FIFOs to the serial output pin Those are different for the first 1 2 or 4 bytes start and the following bytes stationary Table 14 Transmitter Delays Start Stationary LMOD 00 10C 10 C 8 Cis LMOD 01 11C At 10 C 16 Cr LMOD 10 19C At 18 C 32 Cr LMOD 11 35 C At 34 C 64 Cis At Delay between BFHX1 interrupt status and write to HXW1 register by DSP or host programmable via HHX1 Semiconductor Group 62 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks During reception transmission the delay is dynamically increased by the number of zero insertions in the path between the line and the data receiver transmitter Thus the numbers in the table refer to the beginning and the end of the frame and any state inside a frame when no zero insertions are in the pipeline The receiver latencies have to be taken into account in systems where the serial clock is not continuous but is immediately disabled after the last serial data bit has been received The
132. ne to the host by writing a value 04 into INH interrupt status register at address 504 2 The host may reset the INDB as a reaction to the JADE interrupt This step is not mandatory and may be skipped 3 Start Point in First Frame At this point the host can request other interrupts like Read Status or Write Control Block see Section 6 2 1 1 The number of interrupts and the time to execute them is not limited by the JADE but dedicated by the host itself The host may request interrupts as long as it has not executed the next step of this table 4 The host generates an interrupt to the JADE by writing value 05 into INH interrupt status register at address 50 By that the host indicates that it is ready to exchange the next frame of data 5 The JADE resets the INHB bit With this procedure the handling of one frame of data is finished and the next frame is started beginning with the exchange of the compressed audio procedure 1 3 When starting the above protocol it begins at the point marked with Start in first frame This is to enable the host to have control of the real start time so the host first has to generate a Host Ready interrupt INH 05 before the host will start with the exchange of the compressed audio procedure 1 3 After that the Host Host handshake procedure is executed cyclically Note A polling host should not directly poll the IND interrupt status register 584 but the DINT bit in INT inte
133. needs to initialize its internal memories and interfaces The time to do this is less than 10 ms The user must take care to access the JADE only after this initialization phase is completed i e 10 ms after the hardware reset Power down The actual chip internal clock DSP clock is gated with the PU bit in the general configuration control register Thus when PU is set to 0 either via the host or the DSP clock distribution is stopped and the DSP is disabled In this mode the power consumption is minimum software power down Only an interrupt to the DSP on INTO or INT1 can restart the DSP clock The initial state of the PU bit is 1 The PU bit is used by the on chip firmware for the firmware controlled power down see Chapter 6 1 3 for details IOM 2 Clocks The IOM 2 clocking is either provided by separate timing inputs DCL and FSC independent of the other clocks or maybe generated by the JADE itself CGEN bit in register 202B When generated by the JADE only double rate clocking in TE mode DCL 1 536 MHz FSC 8 kHz is supported Semiconductor Group 50 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks When input the DCL clock frequency is either equal to the data rate on DD DU if Clock Rate Select bit CRS 1 or twice the bit rate if CRS 0 default value after Reset In the last case it is ensured that the internal IOM 2 bit clock has a phase such that output bits on DD DU are
134. ng bit position The other interrupts are acknowledged as follows DINT Reset when IND Int Status register is read SDATA Reset when serial data Controller interrupt register is read MDR Reset when MONR register is read GPI Reset when GP Int Status register is read CIC1 Reset when CIR1 register is read CIC2 Reset when CIR2 register is read Note Since no direct access to the MONR CIR1 CIR2 and GP Int Status registers for the host is allowed these registers are in the Configuration and Control Register area 2000 upwards they are read using the procedure via Address and Data registers as decribed in Section 2 in principle giving the host the possibility to handle the Monitor and C I channels via the DSP Semiconductor Group 81 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description 5 3 Indirectly Accessible Configuration and Control Registers Table 15 Summary Addr Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name 2000 Chip VN5 VN4 VN3 VN2 VN1 VNO Version Nr 2001 External LDMEM CAEN DACC NRW3 NRW2 NRW1 NRWO Memory 2002 General PU CRS CKOEN CKOS ODS CKOBR18 CKOBR17 CKOBR16 Config 2003 CLKO Baud CKOBR15 CKOBR14 CKOBR13 CKOBR12 CKOBR11 CKOBR10 CKOBR9 CKOBR8 Rate2 2004 CLKO CKOBR7 CKOBR6 CKOBR5 CKOBR4 CKOBR3 CKOBR2 CKOBR1 CKOBRO Baud Rate1
135. ngth of the time slot is given by RCC 7 0 Receive Clock Shift Together with RCSO RCS1 and RCS2 mark the start of the time slot with one bit granularity TSAX Read Write Address 29 Bit 7 Bit 0 TSX5 TSX4 TSX3 TSX2 TSX1 TSXO XCS2 XCS1 Time Slot Transmit Selects one of up to 64 possible time slots OOh 3F in which data is transmitted TSX gives the location of the time slot in octets granularity octet The bits XCS 2 0 give the exact starting point of the time slot with one bit precision In other words the time slot position with respect to the frame sync is given by TSX x 8 XCS The length of the time slot is given by XCC 7 0 Transmit Clock Shift Together with XCSO XCS1 and XCS2 mark the start of the time slot with one bit granularity Data Sheet 1998 07 01 SIEMENS PSB 7230 RCCR Register Description Receive Channel Capacity Register RCCR Read Write Address 2A Bit 7 Bit 0 RCC7 RCC6 RCC5 RCC4 RCC3 RCC2 RCC1 RCCO RCC Receive Channel Capacity Defines the number of bits in the receive time slot Number of bits RCC 1 1 256 bits time slot Transmit Channel Capacity Register XCCR Read Write Address 2B Bit 7 Bit 0 XCC7 XCC6 XCC5 XCC4 XCC3 XCC2 XCC1 XCCO XCCR XCC Semiconductor Group Transmit Channel Capacity Defines the number of bit
136. ning to the Mailbox The function of these host registers is described in detail in the next section Hardware Interrupt Registers In the following the interrupts for the Host are listed as well as for completeness those for the embedded DSP The interrupts are grouped so that the high priority interrupt statuses may cause a maskable interrupt on INTR Interrupts Real time for Host and or INTO DSP and the lower priority interrupt statuses on INT Host and or INT1 DSP High priority interrupts IN T H INTO FSC RFS TFS BFUL1 BEMP1 BFHR1 BFHX1 Lower priority interrupts INT INT1 SAIN SDATA HINT to DSP or DINT to Host RACC to DSP only MDR MER MDA MAB CIC1 CIC2 The active level of INTR and INT lines is low of INTO and INT1 high The interrupt line will remain active as long as an interrupt status if unmasked is not explicitly acknowledged or the cause of the interrupt status has not been removed The registers for the interrupt status as well as the Configuration and Control registers from address 2000 upwards are described in detail in Section 5 Semiconductor Group 43 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization 3 4 Mailbox The Mailbox is implemented as physically two separate 256 byte memory blocks Only least significant bytes are used One is read only by the DSP and write only by the host the other is write only by the DSP and read
137. o control bits in the Monitor channel Control Register MRE Monitor channel Receiver Enable MRC MR bit Control MXC Monitor channel Transmitter Control Semiconductor Group 68 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks The Monitor channel status is reported to the software via four bits in the Monitor channel Status register MDR Monitor channel Data Received MER Monitor channel End of Reception MDA Monitor channel Data Acknowledged MEA Monitor End of Acknowledgement MAB Monitor channel Abort Inactivity The transmitter indicates its inactivity with the idle state of the MX bit 1 and by transmitting the value FF or high impedance in the Monitor Data channel The receiver responds to this inactivity via the idle 1 condition of the MR output bit Monitor Packet Transfer The message transfer starts when the transmitter transmits the value of the first byte of the Monitor Data channel and sets the MX bit to its active state 0 The MX bit remains active until the receiver acknowledges the data or the transmitter software aborts the transmission The receiver recognizes the change of the MX bit to the active state and latches the contents of the Monitor Data channel Since the Monitor channel address is always transmitted as the first byte of a message all receiving devices compare per hardware or software the first value with their own address If a device recognizes its address it acknowledges the data by
138. ock modes available in the PSB 7230 are as follows CM1 0 PLL is activated by firmware after reset The internal clock circuitry generates a frequency 4 5 times the input on XTAL 1 2 The internal frequency required is 34 56 MHz and is obtained by providing a frequency of 7 68 MHz on XTAL1 input CM1 1 PLL inactive The internal frequency is directly input via XTAL 1 2 When using a crystal a 34 56 MHz crystal swinging at its basic harmonic has to be connected to XTAL 1 2 For the clock generation unit a separate supply voltage pin Vbpa and Vppap and a separate ground pin Vas and Vssap are provided The block diagram of the clock circuitry is shown in Figure 19 Semiconductor Group 49 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks INTO 7 NTI OR 1 gt set PU Lf For CMI 0 input 7 68 MHz AN Ta ea m a Os cillator V 34 56 MHz DSP 1 gt IXTAL1 12 x18 12 M Lj clock p V U AND gt tide xam E X TAL2 j m CKOBR 230 DV VDDA VSSA IS CKOEN Separate 14 N Powersuppk PLL Clock generator circuit T3 7 J T3 CM1 CKOS TEN N Z V DIV 7 68 MHz Mess CKOEN T3 inte nupt s tatus gt CLKO Figure 19 For a proper initialization the required total length of the RESET is 1 ms Note After a hardware reset the JADE firmware
139. ole ex ee we OR 79 5 3 Indirectly Accessible Configuration and Control Registers 82 5 4 Serial Data Controller Registers 0 0 00 cece eee eee 101 6 Firmware Features oec hae dr awe eee cee Paw ee ae SEES 113 6 1 Basic Functions v een fate Gad e ex ge iss rar he Pod esto Eros deed Seni oon Sees 114 6 1 1 Firmware Version Number 0 000 c eee e eee eens 114 6 1 2 Software Reset S cugino qox Bors keane treibt Brut sth ined a eg 115 6 1 3 Power Down Command ioco scs era Pe Oso EP ERRORS E 116 6 2 AUG Ier Tae Soo d oae feted a E den ios Gin ita Roane des rn eec e Mrd anand x Hus 117 6 2 1 Compressed Audio Protocols and Control of JADE AN 119 6 2 1 1 Outband Control of JADE AN 0 ce eee 119 6 2 1 2 Compressed Audio Protocol with Outband Control 130 6 2 1 3 Compressed Audio Protocol with Inband Control 132 6 2 1 4 Control Pipeline uiuo uet uet Sa 2s Rem Eon Aun Rady Gave 138 6 2 2 Uncompressed Data Protocol 00000 eee eee 144 6 2 3 Audio Interface Timings 0000 cece eee eee 145 6 2 3 1 Uncompressed Data Host IF Compressed Data HostIF 145 6 2 3 2 Uncompressed Data IOM IF Compressed Data Host IF 153 6 2 3 3 Uncompressed Data IOM IF Compressed Data Serial Audio Interface SAI 162 7 Electrical Specification 2 4 0008 ossis 165 7 1 Absolute Maximum Ratings lt lt eink es a FERE NR E RR E ed aes 165 7 2 Oper
140. onductor Group 19 Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction 1 6 3 LAN Videoconferencing For videoconferencing over LAN usually high bandwidth is available thus resulting in an advantage of hardware videocoding versus software video coding In addition high audio quality with acoustic echo cancellation is requested See Figure 6 for a LAN videoconferencing board ACE Acoustic ARCOFI BA Echo Canceller SIEMENS SIEMENS PSB 2161 PSB 2170 MPEG 1 Stereo DAC optional Video JADE AN Codec Video Capture PSB 7230 Video out PAL NTSC Camera PCI Bus Interface PCI Bus LAN Subscriber Figure 6 Since the line connection is off board all kinds of connections ISDN H 320 POTS H 324 or LAN H 323 can be used with a single board The LAN standard H 323 implements a correction mechanism for non guaranteed quality of service thus enabling also videoconferencing via Internet The audio input output in this example is done via the Siemens ARCOFI BA PSB 2161 and the Siemens ACE PSB 2170 an acoustic echo canceller which implements two different algorithms switchable for minimum delay and maximum performance An MPEG playback possibility is optional in this example and can be skipped to reduce costs Semiconductor Group 20 Data Sheet 1998 07 01 SIEMENS PSB 7230 Introduction 1 6 4 Standalone H 324 H 323 Videophone The following example shows an H 324 or
141. or the frame sync signal RFS and or TFS two basic modes of operation are provided Case 1 If control bit RCONT 1 pulses on RFS are continuously and periodically generated if ERFS Enable RFS generation control bit in data controller register bank is set to 1 of one bit period length and spaced PRD 1 x 16 bits apart where PRD 0 1 31 Note It suffices that the ERFS bits in the serial Data Controller register bank is set to 1 in order for pulses to be generated Case 2 If RCONT 0 a burst of REP 1 pulses on RFS is generated of one bit period duration and spaced 16 bit periods apart when a start command is issued by setting the STR bit to 1 REP takes the a value in the range 0 to 1 023 Note It suffices that the STR command in the serial Data Controller register bank is issued in order for the generation of pulses start The same applies for TFS control bits are ETFS and STX Semiconductor Group 53 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks Example for TFS For TFIN 0 TCONT 0 SCLK ENE STX 1 command 16 periods TFS ou E E eae stop 1st 2nd TREP 1 VU bi d on a 16 bit boundary STX read bit is TCONT 1 reset 16 bit periods later While ETFS 1 16x TPRD 1 periods E TFS out Fi a oa indefinitely
142. oup 169 Data Sheet 1998 07 01 SIEMENS PSB 7230 Electrical Specification Motorola Bus Mode pr 0 0 P IIIA 9 II III ITT00716 Figure 62 Microprocessor Read Timing Figure 63 Microprocessor Write Timing CS x DS tas tay i ADO AD7 ITT09662 Figure 64 Non Multiplexed Address Timing Semiconductor Group 170 Data Sheet 1998 07 01 SIEMENS PSB 7230 Electrical Specification Table 31 Parameter Symbol Limit Values Unit min max ALE pulse width tan 50 ns Address setup time to ALE tat 15 ns Address hold time from ALE tia 10 ns Address latch setup time to WR RD tars 0 ns Address setup time tas 25 ns Address hold time tay 10 ns ALE guard time tap 15 ns DS delay after R W setup tosp 0 ns R W hold from CSxDS inactive nwp 0 ns RD pulse width ter 110 ns Data output delay from RD ten 110 ns Data float from RD tor 25 ns RD control interval try 70 ns W pulse width tww 60 ns Data setup time to WxCS tow 35 ns Data hold time WxCS two 10 ns W control interval tw 70 ns Interrupt Release Timing TIAT High Impedance INT or INTR WR f Figure 65 Semiconductor Group 171 Data Sheet 1998 07 01 SIEMENS PSB 7230 Electrical Specification
143. owered down Two options exists one power down including the PLL and one excluding it These options are selected via the contents of the control register 60 A non zero value leaves the PLL powered up while the rest of the JADE goes power down and a zero value in register 604 includes the PLL in the power down sequence and therefore is a complete power down of the chip The power up is triggered by one of the following interrupts GPIO Host interrupt and C I channel interrupt The sequence to power down the device is as follows 1 The host initializes the control registers 604 by writing a 0 or a non zero value into it PLL included or excluded see above 2 The host generates an interrupt to the JADE by writing value 374 into INH interrupt status register at address 504 3 The JADE resets the INHB bit There is no further acknowledge to this interrupt since the JADE will go to power down almost immediately 4 The host may reset the INDB as a reaction to the JADE interrupt This step is not mandatory and may be skipped 5 The JADE firmware disables the CLKO pin the PLL as selected and the DSP and can be woken up by any of the above mentioned interrupts If the PLL was powered down it takes longer to resume normal operation If the PLL remained powered up the firmware is immediately ready for resuming operation Semiconductor Group 116 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features 6 2 Audio Interfaces
144. per synchronisation after the burst but the data and packet numbering during the burst will be garbage Thus the synchronisation of encoder and decoder packets should only be done during non delayed interrupt service The interrupts Write JADE Control Block and Read JADE Status are representative for all kinds of interrupts initiated by the host so they are used in the following as an example for the corresponding type of interrupt 1 Write JADE Control Block Conflict with VocoderFinished Case 1 A critical situation for the host may occur when a Write JADE Control Block WCB interrupt handshake is done immediately before the next time frame starting with the new VocoderFinished VocFin interrupt begins See Figure 51 Semiconductor Group 156 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Write Control VocoderFinished Conflict 1 Host Initialize mailbox start address Write new control INH 3050h 50h block into mailbox Interrupt request Interrupt INT1 INHB 1 lt 31h lt Get Interrupt lt number Read control block from mailbox set INHB 0 E Start 4000h 00h Mailbox for control block write Write JADE Control Block WCB i 1
145. perature T stg 65 to 125 C Supply voltage Vbp 0 5 to 4 2 V Supply voltage Vopa 0 5 to 4 2 V Supply voltage Vbpp 0 5 to 6 0 V Voltage of pin with respect to ground Vs 0 4 to Vbp 0 5 V XTAL1 XTAL2 Voltage of any other pin with respect Vs If Vopp lt 3 V V to ground 0 4 to Vbp 0 5 If Vopp gt 3 V V 0 4 to Vbpp 0 5 ESD integrity is 500 V Note Stresses above those listed here may cause permanent damage to the device Exposure to absolute maximum rating conditions for extended periods may affect device reliability 7 2 Operating Conditions Vop 3 0 to 3 6 V Vobpe 4 5 to 5 5 V Vas 0 V Vopa 3 0 to 3 6 V Vos 0 V 7 3 DC Characteristics V Conditions Vpp 3 0 to 3 6 V Vypp 4 5 to 5 5 V Vss 0 V T 0 to 70 C All pins except XTAL1 XTAL2 Note In the operating range the functions given in the circuit description are fulfilled Semiconductor Group 165 Data Sheet 1998 07 01 SIEMENS PSB 7230 Electrical Specification Table 28 Parameter Symbol Limit Values Unit Test Condition min max High level input voltage Vi 2 0 V Low level input voltage Vi 0 8 V High level output voltage Voy 2 4 V Tou 400 uA Low level output voltage Vo 0 45 V Io 7 mA pins for DU DD SR and ST 50 pF Io 5 mA pins CA 0 15 CD 0 15 INTN INTRN 30 pF Ig 2 mA all others 30 pF Input leakage c
146. r reset 00 SLIN Select Line 0 Receive channel on DD transmit channel on DU 1 Receive channel on DU transmit channel on DD CICH 3 0 C I Channel position C I channel same time slot for receive and transmit direction located in the 4th byte of multiplex CICH 0 to 15 CIL C I Channel Length 0 4 bits 1 6 bits DLL Double Last Look 0 No double last look 1 C I channel change confirmed only after two consecutive identical values are received Semiconductor Group 97 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description C I Channel 1 Transmit Receive Register Read Write Address 2029 Value after reset 00 CIX C I Channel Transmit Value of transmitted C I channel CIR C I Channel Receive read Value of received C I channel C I Channel 2 Transmit Receive Register Read Write Address 202A Value after reset 00 CIX C I Channel Transmit Value of transmitted C I channel CIR C I Channel Receive read Value of received C I channel IOM Configuration Register Read Write Address 202B Value after reset 00 CGEN Clock Generation for IOM 2 interface TE mode 0 FSC and DCL are inputs Reset value 1 FSC and DCL are outputs DCL 1 536 MHz FSC 8 KHz FODS FSC DCL Open Drain Select 0 FSC and DCL are push pull Reset value 1 FSC and DCL are open drain PLL Configuration Register Read Write Address 202C 202D PU Power Up for PLL 0 PLL is in power down mode 1 PLL is in power up mod
147. rnal DSP system clock is input for divider connected to CLKO 1 CLKO outputs the buffered XTAL1 clock may be used to clock e g additional JADEs value during and after Reset ODS Open drain select for IOM DU and DD lines 0 DD and DU are Open Drain Reset value 1 DD and DU are Push Pull CKOBR Most significant bits of baud rate division factor for CLKO output from 18 16 DSP clock CLKO Baud Rate Registers Read Write Address 2003 2004 Value after reset 00 CKOBR 15 0 Less significant bits of baud rate division factor for CLKO output from DSP clock Semiconductor Group 87 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Serial Audio Interface Signal Register Read Write Address 2005 200A Value after reset 00 SODS SPS DSE SCKIN PRSC 9 0 RFIN RCONT Serial Audio Interface Open Drain Select for SR and ST line 0 SR and ST are push pull Reset value 1 SR and ST are open drain SCLK Polarity select 0 Data Frame Sync out on rising edge Data Frame Sync in on falling edge if DSE 1 idle position outside strobe 0 1 Data Frame Sync out on falling edge Data Frame Sync in on rising edge if DSE 1 idle position outside strobe 1 Data Strobe Enable only valid if SCLK is output 0 SCLK is permanently active 1 SCLK is active only during the programmed timeslots for SR and ST Outside the active timeslots SR and ST remain as High Z The strobe signals of all audio receivers
148. rocessor Semiconductor Group 103 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Status Register STAR Read Address 20 Bit 7 Bit 0 STAR XDOV XCEC RCEC STR STX XDOV Transmit Data Overflow Indicates that more than 32 bytes have been written into the transmit FIFO XCEC Transmitter Command Executing If 1 a command is currently executed by the transmitter and no further command may be written into the XCMD register When 0 a new command may be entered into XCMD RCEC Reveiver Command Executing If 1 a command is currently executed by the receiver and no further command may be written into the RCMD register When 0 a new command may be entered into RCMD STR Status of generation of RFS pulses Only valid when RFIN 0 RFS pulses internally generated and used if RCONT bit in RFS mode register is 0 A 1 indicates that generation of pulses as a result of a previous STR command is still on going STR is reset to O 16 bit periods after the last RFS pulse has been generated This function may be used in connection with the data controller when a predefined number of data units e g words are received clocked by RFS pulses STX Status of generation of TFS pulses Only valid when TFIN 0 TFS pulses internally generated and used if TCONT bit in TFS mode register is 0 A 1 indicates that generation of pulses as a result of a previous STX command is sti
149. rrupt status register 75 This bit always shows whether an interrupt from the DSP has been generated or not independently of the corresponding mask register The mask register only decides whether an interrupt at INT line is generated After having recognized an IND interrupt status the polling host may read out the register 58 to get the interrupt number Semiconductor Group 152 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features 6 2 3 2 Uncompressed Data IOM IF Compressed Data Host IF The JADE AN can provide the uncompressed audio via the IOM interface while exchanging the compressed audio through the host interface ISEL 1 0 01 After switching to IOM Host interface combination by programming the ISEL 1 0 bits in the control block an initialization phase is executed by the JADE AN in which the internal firmware re programs the configuration control registers like in the default configuration see Section 5 3 to setup the IOM interface for the communication with the analog front end AFE This initialization phase is 10 ms The IOM Interface is in TE mode double DCL clock and IC1 2 channels are selected for the 16 bit linear data transfer between the JADE AN and the analog front end AFE The DD line is output of the JADE AN DU is input to the JADE AN This configuration may be changed by the host by just overwriting the corresponding registers after the default initialization has been completed An interrup
150. s JADE AN to Comment 10 ms JADE AN User MODE OPT1 Data MODE OPT1 Data Bytes Bytes 1 00 00 0 00 00 0 Neutral status after Reset 2 66 00 0 00 00 0 Command G 723 high rate encode amp decode 3 66 00 8 00 00 0 First dummy G 723 encoded data to JADE AN for G 723 decoding 4 66 00 8 00 00 0 5 66 90 8 66 90 8 First invalid G 723 en decoded data from JADE AN Semiconductor Group 141 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Table 26 Control Status Pipeline for G 723 cont d Packet Control User to Status JADE AN to Comment 10 ms JADE AN User MODE OPT1 Data MODE OPT1 Data Bytes Bytes 6 66 80 8 66 80 8 7 66 88 8 66 88 8 8 66 90 8 66 90 8 9 66 00 8 66 00 8 Part 0 of valid G 723 encoded frame to from JADE AN 10 66 08 8 66 08 8 Part 1 of 30 ms frame 11 66 10 8 66 10 8 Part 2 of 30 ms frame 12 66 00 8 66 00 8 Part 0 of 30 ms frame 13 66 08 8 66 08 8 Part 1 of 30 ms frame 14 00 10 8 66 10 8 Part 2 of 30 ms frame Command Neutral Mode last G 723 data to JADE AN 15 00 00 0 66 00 8 16 00 00 0 66 00 8 Last G 723 en decoded data from JADE AN 17 00 00 0 00 00 0 4th neutral packet next can change mode 18 60 00 0 00 00 0 Command G 723 high rate encode 19 60 00 0 00 00 0 20 60 00 0 00 00 0 21 60 00 0 60 90 8 First invalid G 723 encoded data from JADE AN
151. s in the transmit time slot Number of bits XCC 1 1 256 bits time slot 111 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Interrupt Status Register ISR Read Address 2C Bit 7 Bit 0 ISR RPF RFO XPR ALLS RPF Receive Pool Full 32 bytes have been received and can be read from the FIFO RFO Receive Frame Overflow Signifies that data has been lost because no room was available in RFIFO XPR Transmit Pool Ready One data block may be entered into the transmit FIFO ALLS All Sent When 1 indicates that the last bit has been transmitted and that the XFIFO is empty Interrupt Mask Register IMR Write Address 2C A 0 in a bit position status after reset masks the correponding bit in ISR Bit 7 Bit 0 IMR RPF RFO XPR ALLS Semiconductor Group 112 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features 6 Firmware Features The JADE internal firmware starts automatically after a hardware reset Note After a hardware reset the JADE firmware needs to initialize its internal memories and interfaces The time to do this is less than 10 ms The user must take care to access the JADE only after this initialization phase is completed i e 10 ms after the hardware reset In the initialization phase the JADE will re program some of the internal registers see Section 5 3 and Section 5 4 The default interface configurat
152. s lines CA bus to external SRAM for program data fetch no meaning in other cases 0 CA bus switched off no program data fetch possible reset value 1 CA bus active external program data fetch possible DACC Data Access selects program or data memory connected to SRAN interface 0 program memory connected reset value 1 data memory connected can be written by using MOV instruction must be read by using MOVP NRW 3 0 Number of wait states for external interface The number of wait states is NRW 1111 0 wait states 0000 15 wait states takes the value 0000 after reset SRAM connected for development purpose should be capable of zero wait states Semiconductor Group 86 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description General Configuration Register Read Write Address 2002 Value after reset BO PU Power Up 0 The DSP clock is turned off It can be started again with a DSP interrupt 1 Normal operation This is the value of PU after a hardware reset CRS Clock Rate Select 0 Input DCL is twice the bit rate on IOM 2 1 Input DCL is equal to the bit rate on IOM 2 CKOEN CLKO Enable 0 CLKO disabled output high impedance CLKO generator initialized and idle 1 Enables generation of CLKO value during and after Reset Note When PU is 0 and CKOEN is 0 all outputs and input outputs of the PSB7238 are in the high impedance state CKOS Source clock for CLKO output pin 0 Inte
153. silence suppression Rd is the same as the above but indicates the mode of the data in this packet It is the same as the corresponding bits of the G 723 packet data e Encoding mute enable After switching a ramping function is implemented to avoid audible clicks 0 Encoding Mute disabled 1 Encoding Mute enabled d Decoding mute enable After switching a ramping function is implemented to avoid audible clicks 0 Decoding Mute disabled 1 Decoding Mute enabled Semiconductor Group 128 Data Sheet 1998 07 01 PSB 7230 SIEMENS Firmware Features Mailbox Address 07 Value after reset 00 MSB LSB EVOL EV7 EV6 EV5 EV4 EV3 EV2 EV1 EVO EV 7 0 Encoder Volume 00 Adjusts the gain on the analog input Realized by multiplying the FF encoder input samples with EV 7 0 1 256 i e 00 is the minimum and FF the maximum volume Mailbox Address 08 Value after reset 00 MSB LSB DVOL DV7 DV6 DV5 DV4 DV3 DV2 DV1 DVO DV 7 0 Decoder Volume 00 Adjusts the gain on the analog output Realized by multiplying FF the decoder output samples with DV 7 0 1 256 i e 00 is Semiconductor Group the minimum and FF the maximum volume 129 Data Sheet 1998 07 01 PSB 7230 SIEMENS Firmware Features 6 2 1 2 To minimize the bandwidth on the compressed audio interface an outband controlled protocol
154. slightly faster than realtime because almost all of the computational power of the JADE AN is needed to compress the audio The 8 kHz pass through mode is not available with this interface combination The basic structure of data exchange between the Host and the JADE AN is shown in the Figure 46 Usual Flow Compressed Audio 1 3 1 Uncompressed Audio 2 3 2 Uncompressed Audio 2 3 3 Uncompressed Audio 2 3 4 Uncompressed Audio 2 3 Start in www Finishing Procedure 3 3 Figure 46 Semiconductor Group 145 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features The picture shows the sequence of basic handshake procedures for one 10 ms frame Basically there are three blocks The compressed audio exchange basic procedure 1 3 the uncompressed audio exchange basic procedure 2 3 and the finishing procedure basic procedure 3 3 The compressed audio exchange 1 3 is executed only once in a 10 ms frame With the uncompressed audio handshake 2 3 2 5 ms of uncompressed data are exchanged 20 samples at 8 kHz This results in a four times repetition of this block to collect 10 ms of uncompressed data for the next frame Finally a finishing handshake 3 3 is executed which acknowledges the audio data exchange offers the possibility to the host to request for other interrupt services and starts the next frame Note The first time frame after the Host Host inter
155. ss Reg Address The procedure is described in Table 11 Table 11 For reading a register from address 2000 85 0 Host writes byte 1 0 a5 a4 a3 a2 a1 a0 to address 40 This causes RDY bit to be set to 0 Internally an RACC interrupt status INT1 line is generated to the DSP Firmware DSP reads address 3040 recognizes a read access most significant bit 1 fetches data from 2000 a5 0 writes into 3041 and sets RDY bit address 3040 40 to 1 After polling RDY bit to be 1 the host can read the data from 414 and access 40 for another operation For writing a register at address 20004 85 0 Host writes data into address 41 Host writes byte 0 0 a5 a4 a3 a2 a1 a0 to address 40 This causes RDY bit to be set to 0 Internally an RACC interrupt status INT1 line is generated to the DSP Firmware DSP reads address 3040 recognizes a write access most significant bit 0 fetches data from 3041 writes it into 2000 a5 0 and sets RDY bit address 3040 40 to 1 After polling RDY bit to be 1 the host can access 40 for another operation Semiconductor Group 41 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization Software Interrupts For communication between the host software and the DSP software the soft interrupt registers IND from DSP to Host and INH from Host to DSP can be us
156. t oy eee Strobe X x 1to 32 bits LBIT 10 gt 4 SR TFS Sy NOA scLK gt T9 V ieee LMOD LBIT BEMP Figure 24 Caption to the Figures In receive direction the input data is loaded from the shift register into DSP accessible read registers and simultaneously into physically separate host accessible read registers In the transmit direction data is loaded into the shift register from the transmit channel register accessible from the DSP if HXA 0 or the register accessible from the host if HXA 1 The control bit HXA1 is provided for this purpose Semiconductor Group 56 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks Serial Data Channel Transfer The interface between the input of the serial data receiver and the DSP or host and between the output of the transmitter and DSP or host is in each case a 32 bit long shift register Receiver in LMOD 1 0 01 10 11 In receive direction when the shift register from the serial line is filled to a programmable level 1 2 or 4 the whole 32 bit shift register is loaded into the HRR1 2 read registers physically separate for DSP and host In the same cycle the contents of the HRW1 2 write register accessible from the DSP if HHR1 2 0 or host HHR1 2 1 are loaded to the HDLC receiver input In the next cycle the data from HRR1 2 is as a default loaded into HRW1 2 and a maskable interrupt status BFHR1 2 is generated to the DSP and host The in
157. t be considered as assured characteristics Terms of delivery and rights to change design reserved Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Siemens Office Semiconductor Group Siemens AG is an approved CECC manufacturer Packing Please use the recycling operators known to you We can also help you get in touch with your nearest sales office By agreement we will take packing material back if it is sorted You must bear the costs of transport For packing material that is returned to us unsorted or which we are not obliged to accept we shall have to invoice you for any costs incurred Components used in life support devices or systems must be expressly authorized for such purpose Critical components of the Semiconductor Group of Siemens AG may only be used in life support devices or systems with the express written approval of the Semiconductor Group of Siemens AG 1 Acritical component is a component used in a life support device or system whose failure can reasonably be expected to cause the failure of that life support device or system or to affect its safety or effectiveness of that device or system 2 Life support devices or systems are intended a to be implanted in the human body or b to support and or maintain and sustain human life If they fail it is reasonable to assume that the health of the user may be en dangere
158. t handshake protocol is implemented for the data exchange on the host interface The basic timing for this protocol is determined by the uncompressed data rate at the IOM interface See Figure 50 for the interrupt handshake procedure Semiconductor Group 153 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features IOM Host Interrupt Handshake compressed audio from JADE to host Get Interrupt number pA e Initialize mailbox start address 4Ch Read compressed xxh audio from mailbox set INDB 0 EEEEE Host Jade DSP Start 4000h 00h write compressed audio packet into gt Mailbox mailbox i Backup of Interrupt IND 3061h 61h VocoderFinished gt C0h for slow hosts 80h see text nterrupt request IND 3058h 58h INT INDB 1 VocoderFinished S COh gt Interrupt alternating COh 80h 80h l ERR EEE E E ETUR LEE CORE rac E REEE ERE Start in first frame on Initialize mailbox start address seh Write compressed x audio into mailbox INT1 INHB 1 INH 3050h 50h Acknowledge compressed audio from host to JADE Get Interrupt lt number Start 4000h 00h read compressed audio packet from mailbox Mailbox set INHB 0 Interrupt lt 24h lt x Interrupt request Figure 50 Semiconductor Group 1
159. ta register bank and the Host interface bus is disconnected from the data controller When HAHI is 1 the Host is allowed to access the data register bank and the SPC data bus is disconnected from the data controller The address space of the data controllers for the Host interface bus and for the SPC data bus is shown in Figure 27 see also Section 5 Data Controller Register Description Host Address DSP Address A0 A7 If HAH1 1 If HAH1 0 MSB LSB Ep SOBER SDATA 80h 3080h Figure 27 Semiconductor Group 64 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks The received data is stored in the receive FIFO so that byte alignment in the FIFO corresponds to byte alignment in the serial time slot if the length of the time slot is a multiple of 8 bits Similarly in transmit direction the byte alignment in the FIFO corresponds to the time slot boundaries in the transmit time slot if its length is a multiple of 8 bits When the transmit FIFO is empty idle 1 is transmitted during the active time slot Outside the selected time slot the output line is in high impedance state Details on the Operation of the Serial Data Receiver The data receive FIFO size is 2 x 32 bytes One half of the FIFO is connected to the receiver shift register while the second half is accessible from the controlling software The status bits pertaining to the data receiver are RPF Recei
160. takes on the values 0 1 or 2 corresponding to the first second or third part of a 30 ms data packet Is always 0 for the other modes Note When in G 723 mode the user has to take care that G 723 encoder and decoder are running synchronously i e the part number of the received and transmitted packet in one 10 ms frame must be identical for control and status Data is invalid If is set then the compressed data in this packet was missing or had errors The data words in this packet are still sent to avoid buffer problems 5 Set Volume EV7 EV6 EV5 EV4 EV3 EV2 EV1 EVO DV7 DV6 DV5 DV4 DV3 DV2 DV1 DVO Adjusts the gain on the analog input and output Realized by multiplying the encoder samples with EV 7 0 1 256 and the decoder samples with DV 7 0 1 256 i e for maximum volume the samples are not affected and for minimum volume they are divided by 256 Semiconductor Group 136 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Status The following section defines the status information that is sent from the JADE AN to the user The status packet contains information about the current output pipeline stage i e the modes used to generate the data in the status packet itself 1 Status header word 0 1 010 1 0 0 0 0 0j 0 0 1 1 1 1 2 Capabilities C S 0 0 0 0 0 0 0
161. ter Description Bit 7 Bit 0 71 FSC RFS TFS Bit 7 Bit 0 70 BFUL1 0 BEMP1 BFHR1 BFHX1 0 FSC FSC detected RFS RFS detected TFS TFS detected BFUL1 Receive channel sample of programmable length 1 32 bits available in RC1 BEMP1 Transmit channel sample of programmable length 1 32 bits can be written in XC1 BFHR1 Data receiver shift register can be read and or written 1 2 or 4 bytes in HR1 BFHX1 Data transmitter shift register can be read and or written 1 2 or 4 bytes in Interrupt Mask Registers HX1 Bit 7 Bit 0 7 FSC RFS TFS Bit 7 Bit 0 70 BFUL1 BEMP1 BFHR1 BFHX1 A O in a bit position masks the corresponding interrupt default value i e after Reset The mask bit affects only the generation of the interrupt but not the interrupt status bit from being set Semiconductor Group 79 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Acknowledge Register 785 Bit 7 Bit 0 FSC RFS TFS The interrupt status bit is reset when the host writes a 1 in the corresponding bit position The other interrupt status bits are reset when the input output registers are read or written BFUL1 BEMP1 BFHR1 BFHX1 Reset when RC1 address 00 is read Reset when XC1 any of 00 03 is written Reset when HRR1 any
162. terrupt status is generated to both DSP and host independent of the setting of HAH1 2 If the data in HRR1 2 is to be pre processed the HRW1 2 register can be overwritten by the DSP or host before the next 1 2 or 4 bytes programmable have been shifted into the shift register After reset RRES when starting the receiver RAC 1 the reset status data of HRW and HRR is ignored by the receiver i e the contents of HRW1 2 and HRR1 2 are not forwarded to the HDLC receiver but only the data received from the line The same applies to the interrupts A BFHR1 2 interrupt is only generated after the first 1 2 or 4 bytes of line data are available in the HRR1 2 register Due to this pipeline a latency occurs in the HDLC transparent serial data reception see section below The start of the reception can be in the same frame w r t the frame sync signal on the chosen line as the setting of RAC 1 since the time slot count logic works independently of RAC In transparent mode TMO 1 the reception is only started at the beginning of the time slot time slot aligned If RAC is set to 1 during the selected time slot the receiver waits for the beginning of the time slot in the next frame Receiver in LMOD 1 0 00 The same applies for LMOD 00 except the pre processing is not available The data from the bit reversal unit is bypassed to the HDLC receiver In addition the loading of HRR1 2 HRW1 2 and the generation of the interrupt B
163. tes and the most significant bit of the most significant byte is transferred first big endian Semiconductor Group 144 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features 6 2 3 Audio Interface Timings In this chapter the timings and or interrupt handshake procedures are described for the different hardware interface selections Host Host IOM Host IOM Serial Audio Interface After a hardware reset the firmware automatically does all necessary initializations for the IOM Serial Audio Interface combination described in Chapter 6 2 3 3 The other interface combinations can be configured by configuring the control block see Chapter 6 2 1 1 Note After a hardware reset the JADE AN firmware needs to initialize its internal memories and interfaces The time to do this is less than 10 ms The user must take care to access the JADE AN only after this initialization phase is completed i e 10 ms after the hardware reset 6 2 3 1 Uncompressed Data Host IF Compressed Data Host IF This interface combination is used for offline processing of audio ISEL 1 0 00 l e the compression can be done faster than realtime because the JADE AN is in each mode able to process audio at least in realtime This definitely also depends on the capabilities of the host processor to provide a fast interrupt service to the handshake procedure described below The most complex algorithm is G 723 in this mode the maximum possible speed is only
164. the DU and DD lines are in high impedance Semiconductor Group 29 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization 3 1 2 Serial Audio Interface The Serial Audio Interface is a generic 5 line serial interface with the following lines SCLK Serial bit clock Input or Output SR Serial Receive Input Output ST Serial Transmit Input Output RFS Receive Frame Sync Input or Output TFS Transmit Frame Sync Input or Output Figure 11 shows an example where RFS is input and TFS is output SCLK out TFS out y Astbit y 2nd bit 3rd bit ST in out 7 ZK X X sampled RFS sample i Ist bit 2nd bit 3rd bit SR in out Figure 11 Semiconductor Group 30 Data Sheet 1998 07 01 SIEMENS PSB 7230 Interfaces and Memory Organization SCLK Input or output Bits on SR ST are clocked out with the rising edge of SCLK and latched in with the falling edge of SCLK When SCLK is programmed as output it is derived from a programmable baud rate generator RFS Input or output Marks the beginning of the physical frame on SR When input Sampled with a falling edge of SCLK When output Clocked out with the rising or falling edge of SCLK duration 1 SCLK period Repetition rate continuous mode or number of pulses burst mode is programmable TFS Input or output Marks the be
165. the interrupt load for the host as small as possible the JADE AN does not generate an acknowledge interrupt It is guaranteed that the INH interrupt 244 is serviced within a time of 125 us so if the host sends the interrupt 24 soon enough it is guaranteed that the interrupt handshake procedure is completed before the next VocoderFinished from the JADE AN appears So in this case the host does not need to check the status of INHB If the host wants to apply other actions e g reading or writing of the control status block it has to wait for the INHB bit to be reset to 0 All these additional actions should be completed within the current time frame default within 10 ms after the VocoderFinished interrupt Otherwise special situations in the interrupt sequence have to be considered by the host see text below When starting the above procedure it begins at the point marked with Start in first frame This is to enable the host to have control of the real start time so the host first has to deliver compressed data to the JADE AN and generate the corresponding interrupt After that the IOM Host handshake procedure is executed cyclically N Semiconductor Group 155 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Note A polling host should not directly poll the IND interrupt status register 58 but the DINT bit in INT interrupt status register 75 This bit always shows whether an interrupt from the DSP has been gen
166. transmitter latencies have to be taken into account in systems where the transmitter shall start transmitting accurately in one special frame w r t the line frame sync signal e g when the transmission has to be started in the first time slot of a frame sync burst Semiconductor Group 63 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks 4 3 Serial Data Controller The internal serial data controller of the PSB 7230 can be independently serviced either via the Parallel Host Interface or by the DSP SPCF Important Notes 1 From the point of view of the end user system manufacturer only the servicing of the data controller via the host is of relevance since the servicing via the DSP is done by on chip firmware invisible to the end user 2 If the packet oriented protocol on the Serial Audio Interface used in videophone applications with the VCP from 8x8 Inc videocodec is needed the data controller is serviced by the on chip firmware in other words it cannot be accessed by the host Only in protocols see Section 6 2 with the compressed data stream via host interface the serial data controller is available for host usage The servicing of the data controller via the host and via the embedded DSP are exclusive of each other The access to the register banks of the data controller is determined by the Data Controller Access from Host bit HAH1 When HAH is 0 the SPCF is allowed to access the da
167. tter has been activated XAC 1 the data from the HDLC transmitter is immediately passed to the HXR1 2 register for post processing The line transmission is not yet started In the first cycle after the DSP or host programmable via HHX1 2 has written the HXW1 2 register with the post processed value this value is passed through the bit reversal unit into the shift register and the transmission is started as soon as the next beginning of the selected time slot is detected The start of the transmission can be in the same frame w r t the frame sync signal on the chosen line as the setting of XAC 1 and or the writing to the HXW1 2 register since the time slot logic works independently of XAC In transparent mode TMO 1 the transmission is only started at the beginning of the time slot time slot aligned If the first write to HXW1 2 happens during the selected time slot the transmitter waits for the beginning of the time slot in the next frame Transmitter in LMOD 1 0 00 The same applies for LMOD 00 except the post processing is not available The data from the HDLC transmitter is after XAC 1 directly passed through the bit reversal unit into the shift register In addition the loading of HXR1 2 HXW1 2 and the generation of the interrupt is done like in the other LMODs for observation of the data stream by the DSP or host only Thus the LMOD 00 is identical with LMOD 01 except post processing is not available and the tr
168. tus bit In addition an Awake AWK control bit is provided When this bit is set to 1 the output line is unconditionally low until AWK is set to 0 again This bit is used in ISDN terminal applications to wake up the IOM 2 interface i e to require clocking to be generated on DCL and FSC by an upstream circuit typically an ISDN S Bus Access Controller ISAC S When the AWK bit is set to 0 the output line is released only after the next FSC pulse has been detected to avoid sending an invalid code in the outgoing C I channel C I data reception and processing begins after setting CIEN to 1 It is made sure that no invalid code is sent or receiced AWK overrides any data normally transmitted during the C I time slot even if CIEN 1 When CIEN synchronized with FSC is 0 and AWK synchronized with FSC is 0 the outgoing C I channel is permanently in high impedance state The block diagram of the C I channel handler is shown below In the receive direction a change is recognized either using Double Last Look DLL 1 or not DLL 0 Without Double Last Look A change in received C I channel is recognized after a new value is recognized once The new value is loaded into CIR for the DSP to read and a CIC interrupt status is generated If further changes in receive C I code take place before a previous changed value in CIR has been read the changed values are not loaded in CIR When the first changed
169. upt handshake timing violations of e g a slow host Windows PC Details about these functions are given in Chapter 2 3 1 For more details on the hardware necessary for a better understanding of some of the topics described in the present chapter please refer to the other chapters of this Data Sheet 2 3 1 Audio Functions and Supplementary Features General The uncompressed compressed audio is applied to the interfaces as follows Table 9 Uncompressed Audio Compressed Audio IOM 2 transparent SAI H 221 223 oriented audio protocol or transparent IOM 2 transparent Host IF interrupt handshake protocol with minimized interrupt load for the host Host IF interrupt handshake protocol Host IF interrupt handshake protocol Transparent means that data is received transmitted in a time slot without protocol Semiconductor Group 26 Data Sheet 1998 07 01 SIEMENS PSB 7230 General Architecture and Functions Full Duplex G 711 Encoding Decoding of one Audio Channel Audio coding according to ITU T G 711 recommendation using Pulse Code Modulation PCM 64 Kbit s A logarithmic function is used for coding of 8 kHz audio samples thus offering a nearly constant S N over the whole amplitude range Two different laws are defined known as A and p law Full Duplex G 723 Encoding Decoding of one Audio Channel Audio coding according to ITU T G 723 recommendation using Multipulse Maximum Likelihood Quantizat
170. upt request gt 34h gt Interrupt status data ready i Getlnterrupt number 48h 00h Initialize mailbox l start address l 4Ch l Read status data i xxh l from mailbox set INDB 0 Interrupt lt INT1 INHB 1 INH oe 0n Interrupt request Acknowledge data Get Interrupt lt transfer i number i set INHB 0 gt Figure 43 The following steps are executed 1 The host generates an interrupt to the JADE by writing value 33 into INH interrupt status register at address 50 2 JADE writes the current status data into the mailbox resets the INHB bit and generates an interrupt at INT line to the host by writing a value 34 into IND interrupt status register at address 58 3 The host reads the status data from the mailbox using the procedure described in Chapter 3 4 and may reset the INDB bit The reset of the INDB bit is not mandatory and may be skipped The host acknowledges the transfer by writing a value 35 into INH interrupt status register at address 504 and by that generating an interrupt to the JADE 4 The JADE resets the INHB bit Semiconductor Group 122 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features The structure of the control and status data blocks is identical The host writes the control block to change the settings of the JADE AN and reads the status block to evaluate the current settings of the JADE AN The control status block is organized in 8 bit words and
171. ured that the JADE AN is working stable in these situations nevertheless a graceful degradation of speech quality has to be accepted by the user which is about proportional to the real delay time of the VocFin interrupt the smaller the delay due to the busy host the smaller the degradation of quality 4 Read JADE Status Conflict with VocoderFinished Case 2 A Read JADE Status RS request from the host coming in parallel with the VocFin of the new time frame will cause the following interrupt flow Semiconductor Group 160 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Read Status VocoderFinished Conflict 2 T e lee ty Te uct et ee Host Jade DSP 2 Start 4000h 00h write compressed z l 1 gt audio packet into Mailbox i mailbox i Backup of Interrupt IND 3061h 61h l Z VocoderFinished COh l i for slow hosts 80h Interrupt request see text l for status data 5 E Interrupt request c VocoderFinished IND gossn sen INTA UNDER zn Interrupt ba alternating COh 80h 80h Ea compressed audio from JADE to host Get Interrupt E number t 1 I a INH 3050h 50h 8 INT1 INHB 1 Interrupt lt 33h
172. urrent Ij 1 1 uA 0 V lt Vn lt Vona for XTAL1 0 V lt Vn lt Vpp for CD 0 15 0 V lt Vin lt Vppp for all others Output leakage current o 10 10 uA OV Voyt lt Vpp for XTAL2 0 V lt Vout lt Von for CA 0 15 CD 0 15 CPS CDS CWR CRD 0 V lt Vout lt Vpp for all others Vbo Vppa Supply current 55s 90 mA Vppe Supply current Ippps 1 mA The power supply on voltage on Vpp Vss and Vbpa Vssa must be applied after the power supply on Vppp Vssp is applied or at the same time as Vpp is applied If this is not accomplished the device may be damaged permanently Applying voltages to signal pins when power supply is not active circuit not under bias may cause damage refer to paragraph Absolute Maximum Ratings When power supply is switched on the pads do not reach their stable bias until after 2 us maximum Semiconductor Group 166 Data Sheet 1998 07 01 SIEMENS PSB 7230 Electrical Specification 7 4 Capacitances Table 29 Parameter Symbol Limit Values Unit Test Condition min max Input capacitance Cn 7 pF I O capacitance Cio 7 pF Load capacitance Cip 93 7 pF XTAL1 2 7 5 Oscillator Circuit Cis e XTAL1 7 68 MHz C 34 56 MHz 100ppm Cis XTAL2 Figure 56 7 6 XTAL 1 2 Recommended Typical Crystal Parameters Table 30 Parameter
173. using the procedure described in Chapter 3 4 2 The host generates an interrupt to the JADE by writing value 31 into INH interrupt status register at address 50 3 The JADE reads the new control block from the mailbox resets the INHB bit and acknowledges the reception by generating an interrupt at INT line to the host by writing a value 32 into IND interrupt status register at address 58 4 The host may reset the INDB as a reaction to the JADE interrupt This step is not mandatory and may be skipped Semiconductor Group 120 Data Sheet 1998 07 01 SIEMENS PSB 7230 Firmware Features Any changes to the current operating mode of the JADE AN take effect on the next input data packets i e when a 10 ms frame length is selected the next 10 ms packet of uncompressed data will be compressed using the new settings and the next 10 ms packet of compressed data will be decompressed using the new settings too Due to internal buffering a three stages pipeline appears in the JADE AN input compression decompression output Each stage takes as long as determined by the frame length default 10 ms For that reason a mode switch affecting the input data of the JADE AN has to go through the whole pipeline before the output data reports the new settings This results in a delay of three times the frame length default 30 ms between the host requesting a new mode setting and the JADE AN delivering the first packet of data compressed de
174. ut monitoring of data output from host still possible 1 Host has access to modify data receiver input monitoring of data output from DSP still possible Monitor Channel Configuration Register Read Write Address 2021 Value after reset 00 SLIN Select Line 0 Receive channel on DD transmit channel on DU 1 Receive channel on DU transmit channel on DD MONCH 3 0 Monitor Channel position Monitor channel same time slot for receive and transmit direction located in the 3rd byte of multiplex MONCH 0 to 15 Semiconductor Group 95 Data Sheet 1998 07 01 SIEMENS PSB 7230 Register Description Monitor Channel Control Register Read Write Address 2022 Value after reset 00 MRE Monitor channel Receive Enable 0 Receive Monitor channnel inactive 1 Receive Monitor channel active MRC MR bit Control 0 No acknowledgement is sent in response to a received byte When MRE 1 and MRC 0 only the first byte of a packet can received further bytes in the case that the first byte is acknowledged by another IC are not loaded into MONR E Acknowledgement via MR bit is enabled acknowledgement takes place after MONR is read MXC Monitor Transmit Control 0 Transmit Monitor channel inactive high impedance LE Monitor channel transmission enabled Monitor Channel Address IC Identification Read Write Address 2023 Value after reset 00 MAD Monitor Address Latched at reset from lines AD 7 0 and programmable from host
175. utlines for tubes trays etc are contained in our Data Book Package Information SMD Surface Mounted Device Dimensions in mm Semiconductor Group 179 Data Sheet 1998 07 01
176. ve Pool Full 32 bytes of a frame have arrived in the receive FIFO The frame has not yet been completely received RFO Signifies that data has been lost because no room was available in RFIFO The data receiver is controlled by the following bits RAC Receiver Active When RAC is set to 1 storage of bytes in the receive FIFO starts time slot aligned if the receive time slot length is a multiple of 8 bits RMC Receive Message Complete Acknowledges a previous RPF status Frees the FIFO pool for the next received frame or part of a frame RRES Receiver Reset Resets the data receiver which goes into an idle state RAC cleared clears the receive FIFO Details on the Operation of the Serial Data Transmitter The transmit FIFO size is 2 x 32 bytes One half is connected with the transmit shift register while the other half is accessible via the controlling software The interrupt status bits pertaining to the data transmitter are XPR Transmit Pool Ready One data block may be entered into the transmit FIFO ALLS All Sent When 1 indicates that the last bit has been transmitted and that the XFIFO is empty Semiconductor Group 65 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks The following status bits are provided XDOV Transmit Data Overflow Indicates that more than 32 bytes have been written into the transmit FIFO The data transmitter is controll
177. volume word above i e 0 is the minimum volume and 255 is the maximum 6 Error Conditions E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 EO Set in response to an error either in the command sequence or an internal error All zero indicates no error Table 24 Bit Error Condition 0 Invalid checksum 1 Invalid audio mode 2 Invalid loopback mode 3 Hardware error 4 Packet timing error 5 IOM Host Mode Chapter 6 2 3 2 interrupt service from host has been delayed by more than 160 ms 6 2 1 4 Control Pipeline Like stated before there is a delay of three times the frame length default 30 ms between the transfer of a new control block from the host to the JADE AN and the new settings being reported in the status data transferred from the JADE AN to the host due to the internal buffering pipeline of the JADE AN This pipeline is independent of the chosen compressed audio protocol inband or outband Therefore this chapter is applicable to Section 6 2 1 2 and Section 6 2 1 3 In case G 723 is used it is recommended to use the inband protocol due to the fact that packet numbering information is needed on a 10 ms basis The packet numbering information is included in the inband protocol header thus there is no need to request additional status information from the JADE see Chapter 6 2 1 1 Table 25 shows the pipeline behav
178. yte Byte MX out t f N R i a act e ON ba A Packet end V l inact o MR in act Y Ack Ack Ack 1st 2nd n th Byte Byte Byte Figure 31 Figure 31 shows the general case Figure 32 the maximum speed case Software Handling of Monitor Channel Reception The receiver of the Monitor channel is controlled via the MRE bit As long as the MRE bit is zero no evaluation of the received MX bit is done If the MRE bit is set to 1 then the Monitor channel hardware waits for a start of a Monitor packet When the start of a packet is recognized with a Monitor byte matching monitor receive address acknowledgement can be enabled by the software by setting the MR Control bit MRC Semiconductor Group 71 Data Sheet 1998 07 01 SIEMENS PSB 7230 Functional Blocks to 1 The hardware performs acknowledgement by setting the transmitted MR bit to 0 Upon the reception of the next byte the hardware sets the MDR status bit When the Monitor byte is read from the MONR register this byte is acknowledged via transmit MR 0 Every new byte is similarly indicated by the MDR status and acknowledged after a read of the MONR register If the hardware recognizes the end of a packet it indicates this via the MER status MRE 1 The receiver of the PSB 7230 does not perform a double last look check on the received data i e compare the data received while MX 0 with the data in the previous frame with MX 1 When MRC 0 it is made sur

SIEMENS PSB 7230 ICs for Communications handbook

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