intersil ICL7134 14-Bit Multiplying Microprocessor-Compatible D/A Converter handbook
Contents
1. ECL FSR Figure 1 20006 006 FSR Gain Error Temperature Note 5 ELS Coefficient esee E eem AC ACCURACY Power Supply Rejection AV 21055 Figure 2 TA 25 C 0 3 3 2 e ________ _ 1 ree s mwnwee Tames ICL7134 Electrical Specification V 5v 10V TA 25 C AGND at Ground Potential Unless Otherwise Specified Continued PARAMETER TEST CONDITIONS MAX UNITS REFERENCE INPUT ANALOG OUTPUT lout Terminal DIGITAL INPUTS Note 5 POWER SUPPLY Supply Voltage Range Functional Operation Note 6 35 Supply Current Excluding Ladder Network Note 7 _ 10 25 5 3 Full Scale Range FSR is 10V for unipolar mode 20V 10V for bipolar mode Using internal feedback and reference inverting resistors Guaranteed by design not production tested Gain error tested to 0 040 FSR Specifications are not guaranteed DO 013 connected to 2 4 Switching Specifications V 5v 25 C See Timing Diagram meer puer pw eer 9 1 we er 9 E Ew we 9 f oe 12. WU ICL7134 14 Bit Multiplying December 1997 Microprocessor Compatible D A Converter Features Description 14 Bit Linearity 0 003 FSR The ICL7134 combines a four quadrant multiplying DAC using thin film resistor and CMOS circuitry with an on chip PROM controlled correction circuit to achieve true 14 bit Microprocessor Compatible with Double Buffered linearity without laser trimming Inputs No Gain Adjustment Necessary Microprocessor bus interfacing is eased using standard Bipolar Application Requires No Extra Adjustments or memory WRITE cycle timing and control signal use Two External Resistors input buffer registers are separately loaded with the 8 least significant bits LS register and the 6 most significant bits Low Linearity and Gain Temperature Coefficients MS register Their contents are then transferred to the Low Power Dissipation 14 bit DAC register which controls the current switches The DAC register can also be loaded directly from the data Full Four Quadrant Multiplication inputs in which case the MS and LS registers are transparent ICL7134 is available in two versions The ICL7134U is programmed for unipolar operation while the ICL7134B is programmed for bipolar applications The input to the most significant bit of the DAC is separated from the reference input to the remainder of the ladder For unipolar use the two reference inputs are tied together
3. FIGURE 10 BIPOLAR 275 COMPLEMENT FOUR QUADRANT MULTIPLYING CIRCUIT Offset Adjustment 1 Connect all data inputs and WR CS Ag and to DGND Adjust the offset zero adjust trim pot of the operational amplifier Ao if used for a maximum of OV 50uV at AGNDs Set data to 000000 00 Adjust the offset zero adjust trim pot of any output op amp A4 for a maximum of 50 at Connect D43 MSB data input to V Adjust the offset zero adjust trim pot of op amp Ag for a maximum of 50uV at the terminal pin 19 Gain Adjustment Optional 1 Connect WR CS and to 2 Connect Do Dy D12 to V 13 MSB to DGND 3 4 Monitor for a Vngr 1 1 213 reading To increase connect a series resistor of 100 or less between the A4 output and the terminal pin 21 To decrease connect a series resistor of 50 or less between the reference voltage and the Vpr termi nal pin 18 12 Processor Interfacing The ease of interfacing to a processor can be seen from Figure 11 which shows the ICL7134 connected to an 8035 or any other processor such as an 8049 The data bus feeds into both register inputs three port lines in combination with the WR line control the byte wide loading into these registers and then the DAC register A complete DAC set up requies 4 write instructions to the port to set up the address and CS li
4. pw qm ICL7134 Test Circuits 1 5 14 BINARY COUNTER LINEARITY ERROR 100 REFERENCE DAC FIGURE 1 NON LINEARITY TEST CIRCUIT UNGROUNDED SINE WAVE GENERATOR 40Hz 2Vp p 5kQ 10V ADJUST FOR VERROR 0 BIT 13 MSB 5V ICL7134U BIT 0 LSB FIGURE 2 POWER SUPPLY REJECTION TEST CIRCUIT ICL7134 Test Circuits Continued Veer 20Y5 6 10 kHz SINE WAVE Ver PROG BIT 13 MSB ME 7134 BIT 0 LSB FIGURE 3 FEEDTHROUGH ERROR TEST CIRCUIT 0 003 SETTLING 9t 0 01 SETTLING vt PROG OSCILLOSCOPE 5V toomv Y 22 DIGITAL INPUT EXTRAPOLATE SCHOTTKY DIODES FIGURE 4 OUTPUT CURRENT SETTLING TIME TEST CIRCUIT Timing Diagrams Using 14 Bit Transparent Addressing Dy DATA OX FIGURE 5A USING 14 BIT TRANSPARENT ADDRESSING ICL7134 Timing Diagrams Using Full Buffer 8 Bit Addressing Capability 22 MS DATA MS DATA LS DATA LS DATA LS AND MS DATA LATCH ENABLED LATCHED LATCH ENABLED LATCHED TRANSFERRED TO DAC FIGURE 5B USING FULL BUFFER 8 BIT ADDRESSING CAPABILITY ICL7134 Definition of Terms Nonlinearity Error contributed by deviation of the DAC transfer function from a straight line through the end points of the actual plot of transfer function Normally expressed as a percentage of full
5. proper operation Unipolar Binary Operation ICL7134U The circuit configuration for unipolar mode operation ICL7134U is shown in Figure 8 With positive and negative Vngr values the circuit is capable of two quadrant multiplication The digital input code analog output value table for unipolar mode is given in Table 2 The Schottky diode HP5082 2811 or equivalent protects lour from ICL7134 negative excursions which could damage the device and is only necessary with certain high spped amplifiers For applications where the output reference ground point is established somewhere other than at the DAC the circuit of Figure 9 can be used Here op amp A removes the slight error due to IR voltage drop between the internal Analog GrouND node and the external ground connection For 13 bit or lower accuracy omit Ao and connect AGNDr AGNDs directly to ground through as low a resistance as possible DATA INPUTS ICL7134U AGNDs Do LSB PROG DGND WR CS FIGURE 8 UNIPOLAR BINARY TWO QUADRANT MULTIPLYING CIRCUIT DATA INPUTS ICL7134U FIGURE 9 UNIPOLAR BINARY OPERATION WITH FORCED GROUND 11 TABLE 2 CODE TABLE UNIPOLAR BINARY OPERATION 00009000000000 p Zero Offset Adjustment 1 Connect all data inputs and WR CS Ag and to DGND Adjust offset zero adjust trim pot of the operational ampli fier Ao if used for a maximum of OV 50uV at A
6. 8085 SYSTEM INTERFACE 13 ICL7134 4 ADDRESS DECODE MC 680X 5 650 RW FIGURE 14 R650X AND MC680X FAMILIES INTERFACE TO ICL7134 ANALOG CIRCUIT ICEA 1CL7134 OPTIONAL GATE SEE TEXT FIGURE 15 AVOIDING DIGITAL FEEDTHROUGH IN AN 8048 TO ICL7134 INTERFACE FIGURE 16 1 17134 TO 8048 80 85 INTERFACE WITH LOW FEEDTHROUGH Digital Feedthrough All of the direct interfaces shown above can suffer from a capacitive coupling problem The 14 data pins and 4 control pins all tied to active lines on a microprocessor bus and in close proximity to the sensitive DAC circuitry can couple pseudo random spikes into the analog output Careful board layout and shielding can minimize the problems see PC layout and clearly wire wrap type sockets should never be used Nevertheless the inherent capacitance of the package alone can lead to unacceptable digital feedthrough in many cases The only solution is to keep the digital input lines as inactive as possible One easy way to do this is to use the peripheral interface circuitry available with all the systems previously discussed These generally allow only 8 bits to be updated at any one time but a little ingenuity will avoid diffi culties with DAC steps that would result from partial updates The problem can be solved for the 8048 family by tying the 14 port lines to the data input lines with CS Ag and A4 held low and using only the WR line to ent
7. scale range or in sub multiples of 1 LSB Resolution It is addressing the smallest distinct analog out put change that a D A converter can produce It is commonly expressed as the number of converter bits A converter with resolution of n bits can resolve output changes of 27 of the full scale range e g 27 Vper for a unipolar conversion Res olution by no means implies linearity Settling Time Time required for the output of a DAC to settle to within specified error band around its final value e g 1 2 LSB for a given digital input change i e all digital inputs LOW to HIGH and HIGH to LOW Gain Error The difference between actual and ideal analog output values at full scale range i e all digital inputs at HIGH state It is expressed as a percentage of full scale range or in sub multiples of 1 LSB Feedthrough Error Error caused by capacitive coupling from to lour with all digital inputs LOW Output Capacitance Capacitance from terminal to ground Output Leakage Current Current which appears on terminal when all DAC register outputs are LOW Detailed Description The ICL7134 consists of 14 bit primary DAC two PROM controlled correction DACs input buffer registers and microprocessor interface logic See Functional Block Diagram The 14 bit primary DAC is an R 2R thin film resistor ladder with N channel MOS SPDT current steering switches Precise balancing of the switch resistance
8. should carry minimal current tied internally to AGNDr Registers Select Lines ICL7134 Absolute Maximum Ratings Note 1 Thermal Information Supply Voltage to DGND 0 3V to 7 5 Storage Temperature Range RiNv Rep to 15 Power Dissipation Note 2 lout AGNDg 0 1V to V Derate Linearly Above 70 C 10mW C Current in AGNDs Lead Temperature Soldering 10s An Dn WR CS PROG Operating Conditions Temperature Range ICL7134XXC 0 C to 70 C ICL7134XXI 25 C to 85 C ICL7134XXM 55 C to 125 C CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTES 1 All voltages with respect to DGND 2 Assumes all leads soldered or welded to printed circuit board Electrical Specification V 5V Vpgef 10V TA 25 C AGND at Ground Potential Unless Otherwise Specified O __ ww we ws mum Non Linearity Notes 3 and 4 Figure 2 Fy 8823 Non Linearity Temperature Operating Temperature Range Note 5 ppm C Coefficient Gain Error Notes 3 and 4
9. the device 9 lout FIGURE 6 BIPOLAR OPERATION WITH INVERTED TO MSB ICL7134 Digital Section Two levels of input buffer registers allow loading of data from an 8 bit or 16 bit data bus The Ag and A4 pins select one of four operations 1 load the LS buffer register with the data at inputs to D7 2 load the MS buffer register with the data at inputs Dg to D43 3 load the DAC register with the contents of the MS and LS buffer registers and 4 load the DAC register directly from the data input pins See Table 1 The CS and WR pins must be low to allow data transfers to occur When direct loading is selected CS WR Ag and Ay low the registers are transparent and the data input pins control the DAC output directly The other modes of opera tion allow double buffered loading of the DAC from an 8 bit bus These input data pins are also used to program the PROM under control of the PROG pin This is done in manufactur ing and for normal operation the PROG pin should be tied to V 45V TABLE 1 DATA LOADING CONTROLS CONTROL I P ICL7134 OPERATION f eS WR ESXE3ESELZ o Ls pests jesse rom natat tpe pe sims feoserrom Load DAC Register from MS and LS Register NOTE Data is latched on LO HI transition of either WR or CS Applications GENERAL RECOMMENDATIONS Grounding Careful consideration m
10. while for bipolar operation the polarity of the MSB reference is reversed giving the DAC a true 2 s complement input transfer function Two resistors which facilitate the reference inversion are included on the chip so only an external is needed The PROM is coded to correct for errors in these resistors as well as the inversion of the MSB 883B Processed Versions Available Ordering Information TEMPERATURE RANGE C BIPOLAR VERSIONS VERSIONS CAUTION These devices are sensitive to electrostatic discharge follow proper Handling Procedures 1 888 INTERSIL or 321 724 7143 Intersil and design is a registered trademark of Intersil Americas Inc File Number 31 13 1 Copyright Intersil Americas Inc 2002 All Rights Reserved 1 ICL7134 Pinout ICL7134 OUTLINE DWG Jl TOP VIEW Functional Block Diagram 14 BIT DAC REGISTER DO emm RESS LU SELECT SBTLSREQISTER LS REGISTER 6 MS REGISTER REGISTER Doe 07 ICL7134 Pin Descriptions 28 LEAD CERDIP PIN DESCRIPTION Chip Select active low Enables register write WRITE active low Writes in register Equivalent to CS epe KALIKA ENSEM Input Data High True 24 Analog Ground sense line Reference point for external circuitry Pin
11. GNDs Adjust the offset zero adjust trim pot of the output op amp A4 for a maximum of OV 50uV at Gain Adjustment Optional 1 Connect all data inputs to V connect WR CS Ag and Ay to DGND Monitor Voyt for a 1 1 21 reading To decrease connect a series resistor of 50 or less between the reference voltage and the Vary and terminals pins 20 and 18 To increase connect a series resistor of 50 or less between A output and the Rep terminal pin 21 Bipolar 2 s Complement Operation ICL7134B The circuit configuration for bipolar mode operation ICL7134B is shown in Figure 10 Using 2 s complement digital input codes and positive and negative reference voltage values four quadrant multiplication is obtained The digital input code analog output value table for bipolar mode is given in Table 3 Amplifier together with internal resistors RjNy4 and forms a simple voltage inverter circuit The MSB ladder leg sees a reference input of approximately Vggr so the MSB s weight is reversed from the polarity of the other bits In addition the ICL7134B s feedback resistance is switched to 2R under PROM control so that the bipolar output range is to Vngr 1 1 213 Again the grounding arrangement of Figure 9 can be used if necessary TABLE 3 CODE TABLE BIPOLAR 275 COMPLEMENT OPERATION 009090000980000 f ICL7134 ICL7134B
12. dbook together with other material 16
13. de circuit must also be selected carefully If 14 bit accuracy is desired without adjustment low input bias current less than 1nA low offset voltage less than 50uV and high gain greater than 400k are recommended If a fixed reference voltage is used the gain requirement can be relaxed For highest accuracy better than 13 bits and additional be needed to correct for IR drop on the Analog GROUND line op amp in Figure 9 This op amp should be selected for low bias current less than 2nA and low offset voltage less than 50 The op amp requirements can be readily met by use of an ICL7650 chopper stabilized device For faster setting time an HA26XX can be used with an ICL7650 providing automatic offset null see A053 applications note for details The output amplifiers non inverting input should be tied directly to AGNDs A bias current compensation resistor is of limited use since the output impedance at the summing node depends on the code being converted in an unpredictable way If gain adjustment is required low tempco approxi mately 50ppm C resistors or trim pots should be selected Power Supplies The pin 25 power supply should have a low noise level and no transients exceeding 7 volts Note that the absolute maximum for digital input voltage is V 0 3V therefore V must be applied before digital inputs are allowed to go high Unused digital inputs must be connected to GND or V for
14. er the data into the DAC as shown in Figure 15 WR is well separated from the analog lines on the ICL7134 and is usually not a very active line in 8048 systems Additional protection can be achieved by gating the processor WR line with another port line The same type of technique can be employed in the 8080 85 systems by using an 8255 PIA peripheral Interface adaptor Figure 16 and in the MC680X and R650X systems by using 14 an MC6820 R6520 PIA Successive Approximation A D Converters Figure 17 shows an ICL7134B based circuit for a bipolar input high speed A D converter using two 251 35 to form 14 bit successive approximation register comparator is a two stage circuit with and HA2605 front end amplifier used to reduce setting time problems at the summing node see A020 Careful offset nulling of this amplifier is needed and if wide temperature range operation is desired and auto null circuit using an ICL7650 is probably advisable see A053 The clock using two Schmitt trigger TTL gates runs at a slower rate for the first 8 bits where setting time is most critical than for the last 6 bits The short cycle line is shown tied to the 15th bit if fewer bits are required it can be moved up accordingly The circuit will free run if the HOLD RUN input is held low but will stop after completing a conversion if the pin is high at that time A low going pulse will restart it The STATUS output indicates when t
15. he device is operating and the falling edge indicates the availability of new data A unipolar version may be con structed by tying the MSB 013 on an ICL7134U to pin 14 on the first 25103 deleting the reference inversion amplifier and tying and ICL7134 1 827 15 HOLD RUN FIGURE 17 SUCCESSIVE APPROXIMATION A D CONVERTER OGND ADOness FIGURE 18B TOP SIDE WITH COMPONENT PLACEMENT SIDED BOARD FIGURE 18 PRINTED CIRCUIT BOARD LAYOUT BIPOLAR CIRCUIT SEE FIGURE 10 Application Notes Great care should be taken in the board layout to minimize Some applications bulletins that may be found useful are ground loop and similar hidden resistor problems as well listed here as to minimize digital signal feedthrough A suitable layout disce A for the immediate vicinity of the ICL7134 is shown in Figure R002 Ob Data Conversion 18 and may be used as a guide PC Board Layout A018 Do s and Don ts of Applying A D Converters by Peter Bradshaw and Skip Osgood A020 A Cookbook Approach to High Speed Data Acquisition and Microprocessor Interfacing by Ed Sliger A042 Interpretation of Data Converters Accuracy Specifications 005 Interfacing Data Converters amp Microprocessor by Peter Bradshaw et al Electronics Dec 9 1976 Most of these are avilable in the Intersil Data Acquisition Han
16. nes and 3 external data transfers one a dummy for the final transfer to the DAC register A similar arrangement can be used with an 8080A 8228 and 8224 chip set Figure 12 shows the circuit which can be arranged as a memory mapped interface using MEMW or as an l O mapped interface using I O WRITE See A020 and 005 for discussions of the relative merits of memory mapped versus l O mapped interfacing as well as some other ideas on interfacing with 8080 processors The 8085 processor has a very similar interface except that the con trol lines available are slightly different as shown in Figure 13 The decoding of the IO M line which controls memory mapped or operation is arbitrary can be omitted if not necessary Neither the MC680X nor R650X processor families offer specific operations Figure 14 shows a suitable interface to either of these systems using a direct connection Several other decoding options can be used depending on the other control signals generated in the system Note that the R650X family does not require VMA to be decoded with the address lines ICL7134 ADDRESS BUS ADDRESS DECODE lour 1CL7134 5 D AGNDs MEMW ICt7134 ATA BUS No WR WRITE FIGURE 11 7134 INTERFACE TO 8048 SYSTEM FIGURE 12 INTERFACE 8080 SYSTEM 16 BIT ADDRESS BUS ADDRESS DECODE FIGURE 13
17. rnal resistors The two on chip resistors and together with the op amp form a voltage inverter which drives the MSG reference ter minal to where Vggr is the voltage applied at the less significant bits reference terminal Notice the values 1 95R and 28 for the and The absolute value is about 2 5 higher than the This is necessary so that the gain error can be corrected This reverses the weight of the MSG and gives the DAC a 2 s complement transfer function The op amp and reference connection to and can be reversed without affecting linearity but a small gain error will be introduced For unipolar operation the and terminals are both tied to and the pin is left unconnected Since the PROM correction codes required are different for bipolar and unipolar operation the ICL7134 is available in two different versions the ICL7134U which is corrected for unipolar operation and the ICL7134B which is programmed for bipolar application The feedback resistance is also differ ent in the two versions and is switched under PROM control from R in the unipolar device to 2R in the bipolar part These feedback resistors have a dummy always ON switch in series to compensate for the effect of the ladder switches This greatly improves the gain temperature coefficient and the power supply rejection of
18. s and all other resistances in the ladder results in excellent temperature stability True 14 bit linearity is achieved by programming a floating poly silicon gate PROM array which controls two correction DAC cir cuits A 6 bit gain correction DAC or G DAC diverts up to 2 of the feedback resistor s current to Analog GND and reduces the gain error to less than 1 LSB or 0 006 The 5 most TO LADDER significant outputs of the DAC register address a 31 word PROM array that controls a 12 bit linearity correction DAC or C DAC For every combination of the primary DAC s 5 most significant bits a different C DAC code is selected This allows correction of superposition errors caused by bit interaction on the primary resistor ladder s current output bus and by voltage non linearity in the feedback resistor Superposition errors can not be corrected by any method which corrects individual bits only such as laser trimming Since the PROM programming occurs in packaged form it corrects for resistor shifts caused by the thermal stresses of packaging These packaging shifts limit the accuracy that can be achieved using wafer level correction methods such as laser trimming which has also been found to degrade the time stability of thin film resistors at the 14 bit level Analog Section The ICL7134 inherently provides both unipolar and bipolar operation The bipolar application circuit Figure 6 requires one additional op amp but no exte
19. ust be given to grounding in any 14 bit accuracy system The current into the analog ground point inside the chip varies significantly with the input code value and the inevitable resistances between this point and any external connection pint can lead to significant voltage drop errors For this reason two separate leads are brought out from this point on the IC the AGNDf and AGNDs pins The varying current should be absorbed through the AGND pin and the AGNDs pin will then accurately reflect the voltage on the internal current summing point as shown in Figure 7 Thus output signals should be referenced to the sense pin AGNDs as shown in the various application circuits Operational Amplifier Selection To maintain static accuracy the potential must be exactly equal to the AGNDs potential Thus output amplifier selection is critical in particular low input bias current less than 2 low offset voltage less than 25uV are advisable if the highest accuracy is needed Maintaining a low input offset over a OV to 10V range also requires that the output amplifier has a high open loop gain Ayo gt 400k for 10 effective input offset less than 25uV VREF jour RESISTANCE GROUND TO REMAINDER OF ANALOG SYSTEM RESISTANCE W N TRUE ANALOG LEAD GROUND POINT RESISTANCE FIGURE 7 GROUND CONNECTIONS The reference inverting amplifier used in the bipolar mo
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intersil ICL7134 14 Bit Multiplying Microprocessor Compatible D/A Converter handbook