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GSI GS72108TP/J 256K x 8 2Mb Asynchronous SRAM 8 10 12 15 ns 3.3 V VDD Center VDD VSS

1. These parameters are sampled and are not 100 tested Rev 1 08 7 2002 7 12 Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com 1999 Giga Semiconductor Inc TECHNOLOGY GS72108TP J Write Cycle 1 WE control e twc Address K E NSE CE N AE i tas p4 twe tow gt oH DATA VALID Data In gt twz e gt twiz Data Out Ss HIGH IMPEDANCE Write Cycle 2 CE control Address pa twe WE tow gt toH Data Out HIGH IMPEDANCE Rev 1 08 7 2002 8 12 1999 Giga Semiconductor Inc Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com TEGNOLOGY GS72108TP J 36 Pin SOJ 400 mil Dimension in inch Dimension in mm Symbol min nom max min nom max L A 0 146 3 70 k D N A1 0 026 0 66 c gt oonnonnonnnnnnnanan TT sid A2 0 105 0 110 0 115 2 67 2 80 2 92 a B 0 013 0 017 0 021 0 33 0 43 0 53 Ww ra B1 0 024 0 028 0 032 0 61 0 71 0 81 a ed eo tose Cc 0 006 0 008 0 012 0 15 0 20 0 30 gt l e D 0 920 0 924 0 929 23 37 23 47 23 60 E 0 395 0 400 0 405 10
2. T 010 a Q 0 5 0 pe 50 Detail A Note 1 Dimension D amp E do not include interlead flash 2 Dimension B does not include dambar protrusion intrusion 3 Controlling dimension mm Rev 1 08 7 2002 10 12 1999 Giga Semiconductor Inc Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com TEGNOLOGY GS72108TP J Ordering Information Part Number Package Access Time Temp Range Status GS72108TP 8 400 mil TSOP II 8 ns Commercial GS72108TP 10 400 mil TSOP II 10 ns Commercial GS72108TP 12 400 mil TSOP II 12 ns Commercial GS72108TP 15 400 mil TSOP II 15 ns Commercial GS72108TP 81 400 mil TSOP II 8ns Industrial GS72108TP 101 400 mil TSOP II 10 ns Industrial GS72108TP 12I 400 mil TSOP II 12 ns Industrial GS72108TP 151 400 mil TSOP II 15 ns Industrial GS72108J 8 400 mil SOJ 8ns Commercial GS72108J 10 400 mil SOJ 10 ns Commercial GS72108J 12 400 mil SOJ 12 ns Commercial GS72108J 15 400 mil SOJ 15 ns Commercial GS72108J 81 400 mil SOJ 8 ns Industrial GS72108J 101 400 mil SOJ 10 ns Industrial GS72108J 12l 400 mil SOJ 12 ns Industrial GS72108J 15l 400 mil SOJ 15 ns Industrial Customers requiring delivery in Tape and Reel should add the character T to the end of the part number For example GS72108TP 8T Rev 1 08 7 2002 11 12 Specifications cited are subject to change without not
3. 4 5 6 7 ns Output disable to output in High Z OE toHZ 3 5 4 5 6 ns These parameters are sampled and are not 100 tested Read Cycle 1 CE OE Vi WE Viy tRC Address taa toH p Data Out Previous Data CK KA Data valid Rev 1 08 7 2002 6 12 Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com 1999 Giga Semiconductor Inc TEGNOLOGY GS72108TP J Read Cycle 2 WE Vin tRC Address taa gt tac gt tHz tz 5 p toe gt Mfonz OLZ Data Out OA DATA VALID High impedance Write Cycle 8 10 12 15 l Parameter Symbol l Unit Min Max Min Max Min Max Min Max Write cycle time tWC 8 10 12 15 ns Address valid to end of write tAW 5 5 7 8 10 ns Chip enable to end of write tCw 5 5 7 8 10 ns Data set up time tDW 4 5 6 7 ns Data hold time tDH 0 0 0 0 ns Write pulse width tWP 5 5 7 8 10 ns Address set up time tAS 0 0 0 0 ns Write recovery time WE tWR 0 0 0 0 ns Write recovery time CE tWR1 0 0 0 0 ns Output Low Z from end of write t WLZ 3 3 3 3 ns Write to output in High Z tWHZ 35 4 5 6 ns
4. 04 10 16 10 28 N e 0 05 1 27 pt es Gp A B He 0 430 0 435 0 440 10 93 11 05 11 17 x ne i K B1 GE 0 354 0 366 0 378 9 00 9 30 9 60 Detail A Q L oo2 l2 y 0 004 0 10 Q 0 10 0 10 Note 1 Dimension D amp E do not include interlead flash 2 Dimension B1 does not include dambar protrusion intrusion 3 Controlling dimension inches Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com TECHNOLOGY GS72108TP J 44 Pin 400 mil TSOP II Dimension in inch Dimension in mm K D gt Symbol min nom max min nom max 44 23 gt f RHA AAR AAA ARAB ARERR ART A ef see NOOR ee eee silt ah A 000s S eas one cae A2 0 037 0 039 0 041 0 95 1 00 1 05 wW A B 0 01 0 014 0 018 0 25 0 35 0 45 Cc 0 006 0 15 SEE CEECEECEECECCECCE CL ae D 0 721 0 725 0 729 18 31 18 41 18 51 1 22 2 kg E 0 396 0 400 0 404 10 06 10 16 10 26 e 003 0 80 E He 0 455 0 463 0 471 11 56 11 76 11 96 ze Ny L 0 016 0 020 0 024 0 40 0 50 0 60 y EN lt e L1 003 0 80 7 i y oo
5. 08I 10E Ny Fi TEGINOLOGY GS72108TP J SOJ TSOP 256K X 8 8 10 12 15 ns Commercial Temp 3 3 V Vop Industrial Temp 2Mb Asynchronous SRAM center Vpp and Vss Features SOJ 256K x 8 Pin Configuration e Fast access time 8 10 12 15 ns M 10 36 NC e CMOS low power operation 150 125 110 90 mA at re 2 35 A5 minimum cycle time R 3 34 ie e Single 3 3 V 0 3 V power supply 33 All inputs and outputs are TTL compatible M i AT e Fully static operation A0 5 ae A8 e Industrial Temperature Option 40 to 85 C CE 6 31 OE e Package line up DQ1 7 30 DQ8 J 400 mil 36 pin SOJ package DQ2 8 36 pin 29 DQ7 TP 400 mil 44 pin TSOP Type II package V 9 28 v w 400 mil SOJ a ys Vss 10 27 Voo Description Das 1 26 Das The GS72108 is a high speed CMOS Static RAM organized as D4 12 25 DQ5 262 144 words by 8 bits Static design eliminates the need for WE 13 24 Ag external clocks or timing strobes The GS operates on a single A17 14 23 A10 3 3 V power supply and all inputs and outputs are TTL com A16 15 22 A11 patible The GS72108 is available in 400 mil SOJ and 400 mil M5 16 4 M2 TSOP Type II packages Ria 17 2 NC A13 18 19 NC Pin Descriptions Symbol Description Ao A17 Address input DQi D
6. LOGY GS72108TP J Truth Table CE OE WE DQ1 to Dds Vpp Current H X X Not Selected ISB1 ISB2 L L H Read L X L Write IDD L H H High Z Note X H or L Absolute Maximum Ratings Parameter Symbol Rating Unit Supply Voltage VoD 0 5 to 4 6 V 0 5 to Vpp 0 5 Input Voltage ViN lt 4 6 V max V 0 5 to Vpp 0 5 Output Voltage Vout lt 4 6 V max V Allowable power dissipation PD 0 7 W Storage temperature TsTG 55 to 150 C Note Permanent device damage may occur if Absolute Maximum Ratings are exceeded Functional operation shall be restricted to Rec ommended Operating Conditions Exposure to higher than recommended voltages for extended periods of time could affect device reliability Rev 1 08 7 2002 3 12 1999 Giga Semiconductor Inc Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com TEGNOLOGY GS72108TP J Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply Voltage for 10 12 15 VDp 3 0 3 3 3 6 V Supply Voltage for 8 Vpp 3 135 3 3 3 6 V Input High Voltage VIH 2 0 Vpp 0 3 V Input Low Voltage ViL 0 3 0 8 V Ambient Temperature 5 Commercial Range it ie C Ambient Temperature Industrial Range ge zi _ eS C
7. Note 1 Input overshoot voltage should be less than Vpp 2 V and not exceed 20 ns 2 Input undershoot voltage should be greater than 2 V and not exceed 20 ns Capacitance Parameter Symbol Test Condition Max Unit Input Capacitance Cin Vin 0V 5 pF Output Capacitance Cout Vout 0V 7 pF Notes 1 Tested at Ta 25 C f 1 MHz 2 These parameters are sampled and are not 100 tested DC I O Pin Characteristics Parameter Symbol Test Conditions Min Max Input Leakage z Current liL Vn 0 to Vpp 1uA 1 uA Output Leakage Output High Z C rrent ILo Vout 0 to Vpp 1 uA 1 uA Output High Voltage VoH loH 4mA 2 4 Output Low Voltage VoL ILo 4mA 0 4 V Rev 1 08 7 2002 4 12 1999 Giga Semiconductor Inc Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com TECHNOLOGY GS72108TP J Power Supply Currents a 0 to 70 C 40 to 85 C Parameter Symbol Test Conditions 8ns 10ns 12ns 15ns 10ns 12ns 15ns CE lt Vi Operating All other inputs Supply Ipp max gt Vu or lt Vit 150mA 125mA 110mA 90mA 135mA 120mA 100 mA Current Min cycle time lout 0 mA CE gt VH Standby All other inputs Current IsB1 max gt Vi or lt V 55mA 50mA 45mA 40mA 60 mA 55 mA 50 mA Min cycle time CE gt Vpp 0 2 V Standby All other inputs Curre
8. Qs Data input output CE Chip enable input WE Write enable input OE Output enable input Vpop 3 3 V power supply Vss Ground NC No connect Rev 1 08 7 2002 1 12 1999 Giga Semiconductor Inc Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com TEGNOLOGY GS72108TP J TSOP II 256K x 8 Pin Configuration NC 10 44 NC NC 2 43 NC A4 3 42 NC A3 4 41 A5 A2 5 40 A6 A1 6 39 A7 Ao 7 38 A8 CE 8 37 OE Dai 9 36 DQs DQ2 10 35 DQ7 Vpp 11 44 pin 34 Vss Vss 12 400 mil TSOP II 33 VoD DQ3 13 32 DQG DQ4 14 31 DQ5 WE 15 30 A9 A17 16 29 A10 A16 17 28 A11 A15 18 27 A12 A14 19 26 NC A13 20 25 NC NC 21 24 NC NC 22 23 NC Block Diagram Ao e e Row 2 Memory Array e Decoder e Address Input e Buffer e e eee g Column A17 2 Decoder MEEA eco CE a oe ean I O Buffer eee DQ1 DQ8 Rev 1 08 7 2002 2 12 Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com 1999 Giga Semiconductor Inc TEGNO
9. ice For latest documentation see http www gsitechnology com 1999 Giga Semiconductor Inc TEGNOLOGY GS72108TP J Revision History Old f Chan PEV E oc Types of Changes Page Revisions Reason New Format or Content 72108 1 04d 5 1999 721081 05 1 e Page 2 Pins 16 20 and 26 30 on 44 pin TSOP II Pin Configuration 2000 Content Correction GS72108Rev1 05 10 19991 re Tae GSI Logo 2000K Rev 5 2 2000L e Corrected TSOP II pin configuration diagram A17 A13 in lower left pele eevee Ganten quadrant A9 A12 A18 in lower right quadrant e Updated format to comply with Technical Publications standard Format e Specifically noted that numbers in Power Supply Currents table are worst case scenario 72108_11_07 72108 11_08 Content e Removed all references to U package Rev 1 08 7 2002 12 12 1999 Giga Semiconductor Inc Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com
10. nt Jeez man gt Vpp 0 2 V or mA aoma lt 0 2V AC Test Conditions Output Load 1 Parameter Conditions DQ a oe N Input high level VH 2 4 V N J lt al 1 Input low level Vi 0 4 V ae 30pF Input rise time tr 1V ns VT 1 4V Input fall time tf 1V ns Input reference level 1 4 V Output Load 2 Output reference level 1 4 V 3 3 V Output load Fig 1 amp 2 DQ an Note 1 Include scope and jig capacitance 5pF 4340 2 Test conditions as specified with output loading as shown in Fig 1 unless otherwise noted 3 Output load 2 for tz tHz toz and tonz Rev 1 08 7 2002 5 12 1999 Giga Semiconductor Inc Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com TEGNOLOGY GS72108TP J AC Characteristics Read Cycle 8 10 12 15 Parameter Symbol Unit Min Max Min Max Min Max Min Max Read cycle time tRC 8 10 12 15 ns Address access time taa 8 10 12 15 ns Chip enable access time CE tac 8 10 12 15 ns Output enable to output valid OE toe 3 5 4 5 6 ns Output hold from address change toH 3 3 3 3 ns Chip enable to output in low Z CE tz 3 3 3 3 ns Output enable to output in low Z OE torz 0 0 0 0 ns Chip disable to output in High Z CE tHz

GSI GS72108TP/J 256K x 8 2Mb Asynchronous SRAM 8 10 12 15 ns 3.3 V VDD Center VDD VSS

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