AMD AM28F010 memory
Contents
1. 485 T 447 495 m 453 009 i 015 v E 425 056 585 M Pin 1 I D 140 T 595 J 080 547 s r 95 Ww SEATING U L PLANE La 400 REF la 490 013 530 Y IT 021 pm e050 REF 16 038FPO 5 e a PL 032 032 DA79 TOP VIEW SIDE VIEW 6 28 94 ae 32 Am28F010 PHYSICAL DIMENSIONS AMDA TS032 32 Pin Standard Thin Small Outline Package measured in millimeters 0 95 1 05 aay A 8 10 4 Y 18 30 18 50 19 80 20 20 Am28F010 16 038 TSOP 2 TS 032 DA95 3 25 97 Iv 33 AMD PHYSICAL DIMENSIONS TSR032 32 Pin Reversed Thin Small Outline Package measured in millimeters p 18 30 18 50 19 80 0 95 1 05 20 20 34 Am28F010 16 038 TSOP 2 TSR032 DA95 3 25 97 lv REVISION SUMMARY FOR AM28F010 Revision G 1 Distinctive Characteristics High Performance The fastest speed option available is now 70 ns General Description Paragraph 2 Changed fastest speed option to 70 ns Product Selector Guide Added 70 deleted 95 and 250 speed options Ordering Infor2. Y Apply VppL Y Programming Completed Figure 3 Flashrite Programming Algorithm Am28F010 y Apply VppL y Device Failed 11559G 8 Bus Operations AMDA Table 5 Flashrite Programming Algorithm Command Comments Wait for Vpp Ramp to Vppy Note 1 Initialize Pulse counter Program Setup Data 40h Program Valid Address Data Duration of Programming Operation tyHwu1 Program Verify Note 2 Data COh Stops Program Operation Write Recovery Time before Read 6 us Read Byte to Verify Programming Compare Data Output to Data Expected Data FFh resets the register for read operations Notes Wait for Vpp Ramp to Vpp Note 1 1 See AC and DC Characteristics for values of Vpp parameters The Vpp power supply can be hard wired to the device or switchable When Vpp is switched Vpp may be ground no connect with a resistor tied to ground or less than Vog 2 0 V 2 Program Verify is performed only after byte programming A final read compare may be performed optional after the register is written with the read command Am28F010 17 AMDA Section Addresses Bus Cycle Time out Program Address Program Data Command 11559G 9 D E F G Time out Standby COh Stops Program Compare Data Program Command Latch Address and Data Program Setup Program Function 10 u
3. V N Input Pulse Levels Vv Input timing measurement reference levels Note Diodes are IN3064 or equivalent Output timing measurement reference levels 11559H 14 Fiaure 6 Test Setun Am28F010 25 AMD SWITCHING TEST WAVEFORMS 3V 24V 2 0 V 2 0 V gt Test Points d 0 8 V 0 8 V est Points Ov 0 45 V Input Output Input Output AC Testing all speed options except 70 Inputs are driven at AC Testing for 70 devices Inputs are driven at 3 0 V for a 2 4 V for a logic 1 and 0 45 V for a logic 0 Input pulse rise logic 1 and 0 V for a logic 0 Input pulse rise and fall times and fall times are lt 10 ns are lt 10 ns 11559H 15 SWITCHING CHARACTERISTICS over operating range unless otherwise specified AC Characteristics Read Only Operation Parameter Symbols Am28F010 Speed Options JEDEC Standard Parameter Description 90 120 150 Read Cycle Time Note 2 Chip Enable AccessTime Address Access Time Output Enable Access Time Chip Enable to Output in Low Z Note 2 Chip Disable to Output in High Z Note 1 Output Enable to Output in Low Z Note 2 Output Disable to Output in High Z Note 2 Output Hold from first of Address CE or OE Change Note 2 Write Recovery Time before Read Voc Setup Time to Valid Read Note 2 Notes 1 Guaranteed b
4. out the program pulse width 10 us prior to issuing the Program verify command An integrated stop timer prevents any possibility of overprogramming 3 Program Verify Write the Program verify com mand to the command register This command ter minates the programming operation In addition this command verifies the margin and outputs the byte just programmed in order to compare the array data with the original data programmed After suc cessful data verification the programming se quence is initiated again for the next byte address to be programmed If data is not verified successfully the Program se quence is repeated until a successful comparison is verified or the sequence is repeated 25 times Data Protection The device is designed to offer protection against acci dental erasure or programming caused by spurious System level signals that may exist during power transi tions The device powers up in its read only state Also with its control register architecture alteration of the memory contents only occurs after successful comple tion of specific command sequences The device also incorporates several features to pre vent inadvertent write cycles resulting from Vcc power up and power down transitions or system noise Low Vcc Write Inhibit To avoid initiation of a write cycle during Vcc power up and power down the device locks out write cycles for Am28F010 7 AMDA Voc lt Vi ko see DC Characteristics
5. gt 5 0V gt e lvcs terav tce gt r tvPEL 11559G 17 Figure 8 AC Waveforms for Erase Operations Am28F010 29 AMDA SWITCHING WAVEFORMS Program Command Power up SetupProgram Latch Address Verify Programming Standby Standby Command and Data Programming Command Verification Power down Addresses SS SS tavav tac gt ln teroz tor gt ae tavav two tavw tas CE Est tei wr tcs gt gt i twHen tcp OE G f tei X gt Le tanw toes HGL teHaz tor lt SS WER W 7 N N f terav toe gt twLwH twp aes M les wHw pG gt I tarax tolz ipvwH tps HIGH Z Data DQ tei ox tz gt 50V gt lvcs terav tce gt Le Voc OV I tvPEL VppH Vpp VppL 11559G 18 Figure 9 AC Waveforms for Programming Operations 30 Am28F010 AMDA ERASE AND PROGRAMMING PERFORMANCE Limits Typ Max Parameter i Note 1 Note 2 Comments Chip Erase Time Excludes 00h programming prior to erasure Chip Programming Time Excludes system level overhead Write Erase Cycles Notes 1 25 C 12 V Vpp 2 Maximum time specified is lower than worst case Worst case is derived from the Flasherase Flashrite pulse count Flasherase 1000 max and Flashrite 25 max Typical worst case for program
6. C to 125 C Vcc Supply Voltages Vep ea nekiena ETE 4 50 V to 5 50 V Vpp Voltages Head inaa as 0 5 V to 12 6 V Program Erase and Verify 11 4 V to 12 6 V Operating ranges define those limits between which the functionality of the device is guaranteed Am28F010 21 AMD MAXIMUM OVERSHOOT 20 ns 20 ns 0 8 V 0 5 V 2 0V aR 20 ns 11559H 10 Maximum Negative Input Overshoot 20 ns a 2 0 V 20 ns 20 ns 11559H 11 Maximum Positive Input Overshoot 20 ns a 14 0 V 13 5 V 20 ns 20 ns 11559H 12 Maximum Vpp Overshoot 22 Am28F010 AMDA DC CHARACTERISTICS over operating range unless otherwise specified TTL NMOS Compatible Parameter Symbol Parameter Description Input Leakage Current Test Conditions Voc Voc Max Vin Voc or Vss Output Leakage Current Voc Voc Max Vout Vog Or Vss Voc Standby Current Vcc Vec Max CE Vin Voc Active Read Current Vcc Voc Max CE Vit OE Vin lout 0 mA at 6 MHz Vec Programming Current CE Vy Programming in Progress Note 4 Voc Erase Current CE Vj Erasure in Progress Note 4 Vpp Standby Current Vpp VppL Vpp Read Current Vpp VepH Vpp VppL Vpp Programming Current Vpp VepH Programming in Progress Note 4 Vpp Erase Current Vpp VepH Erasure in Progress Note 4 Input Low Voltage Input High Voltage Output Low Voltage
7. Operations Analysis of Erase Timing Waveform Note This analysis does not include the requirement to program the entire array to OOh data prior to erasure Refer to the Flashrite Programming algorithm Erase Setup Erase This analysis illustrates the use of two cycle erase commands section A and B The first erase com mand 20h is a Setup command and does not affect the array data section A The second erase com mand 20h initiates the erase operation section B on the rising edge of this WE pulse All bytes of the memory array are erased in parallel No address infor mation is required The erase pulse occurs in section C Time Out A software timing routine 10 ms duration must be ini tiated on the rising edge of the WE pulse of section B Note An integrated stop timer prevents any possibil ity of overerasure by limiting each time out period of 10 ms Erase Verify Upon completion of the erase software timing routine the microprocessor must write the Erase verify com mand AOh This command terminates the erase oper ation on the rising edge of the WE pulse section D The Erase verify command also stages the device for data verification section F After each erase operation each byte must be verified The byte address to be verified must be supplied with 14 Am28F010 the Erase verify command section D Addresses are latched on the falling edge of the WE pulse Another software timing routin
8. Setup Erase command to the command register again The second command initiates the erase operation The system software routines must now time out the erase pulse width 10 ms prior to issuing the Erase verify command An integrated stop timer prevents any possibility of overerasure 3 Erase Verify Write the Erase verify command to the command register This command terminates the erase operation After the erase operation each byte of the array must be verified Address in AMDA formation must be supplied with the Erase verify command This command verifies the margin and outputs the addressed byte in order to compare the array data with FFh data Byte erased After successful data verification the Erase verify command is written again with new address infor mation Each byte of the array is sequentially veri fied in this manner If data of the addressed location is not verified the Erase sequence is repeated until the entire array is successfully verified or the sequence is repeated 1000 times Flashrite Programming Sequence A three step command sequence a two cycle Program command and one cycle Verify command is required to program a byte of the Flash array Refer to the Flash rite Algorithm 1 Program Setup Write the Setup Program com mand to the command register 2 Program Write the Program command to the com mand register with the appropriate Address and Data The system software routines must now time
9. a program pulse The program operation must be terminated at the conclusion of the timing routine or prior to exe cuting any system interrupts that may occur during the programming operation 4 A fourth timing delay associated with both the Flasherase and Flashrite algorithms is the write re covery time 6 ms During this time internal circuitry is changing voltage levels from the erase program level to those used for margin verify and read oper ations An attempt to read the device during this pe riod will result in possible false data it may appear the device is not properly erased or programmed Note Software timing routines should be written in machine language for each of the delays Code written in machine language requires knowledge of the appro priate microprocessor clock speed in order to accu rately time each delay AMDA Parallel Device Erasure Many applications will use more than one Flash memory device Total erase time may be minimized by implementing a parallel erase algorithm Flash memories may erase at different rates Therefore each device must be verified separately When a device is completely erased and verified use a masking code to prevent further erasure The other devices will continue to erase until verified The masking code applied could be the read command 00h Power Up Power Down Sequence The device powers up in the Read only mode Power supply sequencing is not required Note that if Vo
10. may be sol dered to the circuit board upon receipt of shipment and programmed in system Alternatively the device may initially be programmed in a PROM programmer prior to soldering the device to the board Am28F010 19 AMDA Auto Select Command AMD s Flash memories are designed for use in applica tions where the local CPU alters memory contents Ac cordingly manufacturer and device codes must be accessible while the device resides in the target sys tem PROM programmers typically access the signa ture codes by raising A9 to a high voltage However multiplexing high voltage onto address lines is not a generally desired system design practice The device contains an Auto Select operation to sup plement traditional PROM programming methodology The operation is initiated by writing 80h or 90h into the command register Following this command a read cycle address 0000h retrieves the manufacturer code of O1h A read cycle from address 0001h returns the device code To terminate the operation it is necessary to write another valid command such as Reset FFh into the register 20 Am28F010 ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages 65 C to 125 C Ambient Temperature with Power Applied 55 C to 125 C Voltage with Respect To Ground All pins except A9 and Vpp Note 1 2 0 V to 47 0 V Voc Note 11 2 0 V to 47 0 V A9 Note 2 asnar apr 2 0 V t
11. prior to soldering the device to the board The Auto select mode allows the reading out of a binary code from the device that will identify its manufacturer and type This mode is intended for the purpose of automatically matching the device to be pro grammed with its corresponding programming algo rithm This mode is functional over the entire temperature range of the device Programming In A PROM Programmer To activate this mode the programming equipment must force Vip 11 5 V to 13 0 V on address A9 Two identifier bytes may then be sequenced from the device outputs by toggling address Ag from Vj to Vi All other address lines must be held at Vi and Vpp must be less than or equal to Vcc 2 0 V while using this Auto select mode Byte 0 AO Vi represents the manufac turer code and byte 1 AO V the device identifier code For the device these two bytes are given in Table 2 below All identifiers for manufacturer and device codes will exhibit odd parity with the MSB DQ7 de fined as the parity bit Table 2 Am28F010 Auto Select Code pe MEME NN Manufacturer Code Device Code A7 Am28F010 9 AMDA ERASE PROGRAM AND READ MODE When Vpp is equal to 12 0 V 5 the command reg ister is active All functions are available That is the device can program erase read array or autoselect data or be standby mode Write Operations High voltage must be applied to the Vpp pin in order to activate the
12. 00 tested Am28F010 27 AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady ANN Changing from H to L A Changing from L to H XXX X XX Don t Care Any Change Permitted Changing State Unknown HHK Does Not Apply Center Line is High Impedance State High Z SWITCHING WAVEFORMS Device and Outputs Data Power up Standby Address Selection Enabled Valid Standby Power down Addresses X X X X X X X X Addresses Stable ub XXX L tavav tac m gt CE E u cael 0l Xs WE Wit taLav tog D terav tce tvcs gt gt High Z La ter ox tz Output Valid Data DQ tavav acc 5 0V Veo f OV Figure 7 AC Waveforms for Read Operations 11559H 16 28 Am28F010 AMD SWITCHING WAVEFORMS Power up Setup Erase Erase Erase Verify Erase Standby Standby Command Command Erasure Command Verification Power down 5 SS Addresses VVVVVVVVVV 0X OIA A E tavav two gt tavav tRc tavw tas gt petwiax an CE Ef rm ua n tew tcs ae leuaz tor gt a lt tWHen tch 55 OE G f ty es X Te tenw toes wie gt teHaz fpE e pz WE W F terav toep gt twi wH twp gt Ke twnw tweH gt taLax oLz tpvwu tps HIGH Z twupx tox Data DQ teLax tz
13. PA Data latched on the rising edge of WE PVD Data read from location PA during program verify PA is latched on the Program command 4 Refer to the appropriate section for algorithms and timing diagrams 10 Am28F010 FLASHERASE ERASE SEQUENCE Erase Setup Erase Setup is the first of a two cycle erase command It is command only operation that stages the device for bulk chip erase The array contents are not altered with this command 20h is written to the command reg ister in order to perform the Erase Setup operation Erase The second two cycle erase command initiates the bulk erase operation You must write the Erase com mand 20h again to the register The erase operation begins with the rising edge of the WE pulse The erase operation must be terminated by writing a new command Erase verify to the register This two step sequence of the Setup and Erase com mands helps to ensure that memory contents are not accidentally erased Also chip erasure can only occur when high voltage is applied to the Vpp pin and all con trol pins are in their proper state In absence of this high voltage memory contents cannot be altered Refer to AC Erase Characteristics and Waveforms for specific timing parameters Note The Flash memory device must be fully programmed to 00h data prior to erasure This equalizes the charge on all memory cells ensuring reliable erasure Erase Verify Command The erase operation erases all by
14. Register The command register is enabled only when high volt age is applied to the Vpp pin The erase and repro gramming operations are only accessed via the register In addition two cycle commands are required for erase and reprogramming operations The tradi tional read standby output disable and Auto select modes are available via the register The device s command register is written using stan dard microprocessor write timings The register con trols an internal state machine that manages all device operations For system design simplification the de vice is designed to support either WE or CE con trolled writes During a system write cycle addresses are latched on the falling edge of WE or CE which ever occurs last Data is latched on the rising edge of WE or CE whichever occur first To simplify the fol lowing discussion the WE pin is used as the write cycle control pin throughout the rest of this text All setup and hold times are with respect to the WEZ sig nal Overview of Erase Program Operations Flasherase Sequence A multiple step command sequence is required to erase the Flash device a two cycle Erase command and repeated one cycle verify commands Note The Flash memory array must be completely programmed to 0 s prior to erasure Refer to the Flashrite Programming Algorithm 1 Erase Setup Write the Setup Erase command to the command register 2 Erase Write the Erase command same as
15. SET Amni AMD Am28F010 1 Megabit 128 K x 8 Bit CMOS 12 0 Volt Bulk Erase Flash Memory DISTINCTIVE CHARACTERISTICS B High performance 70 ns maximum access time B CMOS Low power consumption 30 mA maximum active current 100 pA maximum standby current No data retention power consumption B Compatible with JEDEC standard byte wide 32 Pin EPROM pinouts 32 pin PDIP 32 pin PLCC 32 pin TSOP B 10 000 write erase cycles minimum Write and erase voltage 12 0 V 5 E Latch up protected to 100 mA from 1 V to Voc 1 V GENERAL DESCRIPTION The Am28F010 is a 1 Megabit Flash memory orga nized as 128 Kbytes of 8 bits each AMD s Flash mem ories offer the most cost effective and reliable read write non volatile random access memory The Am28F010 is packaged in 32 pin PDIP PLCC and TSOP versions It is designed to be reprogrammed and erased in system or in standard EPROM pro grammers The Am28F010 is erased when shipped from the factory The standard Am28F010 offers access times as fast as 70 ns allowing operation of high speed microproces sors without wait states To eliminate bus contention the Am28F010 has separate chip enable CE and output enable OE controls AMD s Flash memories augment EPROM functionality with in circuit electrical erasure and programming The Am28F010 uses a command register to manage this functionality while maintaining a JEDEC Flash Stan dard 32 pin pinout Th
16. Vpp is high To read from the device write 00h into the command register Standard microproces sor read cycles access data from the memory The de vice will remain in the read mode until the command register contents are altered The command register defaults to 00h read mode upon Vpp power up The 00h Read Mode register de fault helps ensure that inadvertent alteration of the memory contents does not occur during the Vpp power transition Refer to the AC Read Characteristics and Waveforms for the specific timing parameters Table 3 Am28F010 Command Definitions First Bus Cycle Second Bus Cycle Operation Command Note 4 Note 1 Read Memory Address Note 2 Data Operation Address Data Note 3 Note 1 Note 2 Note 3 00h FFh RA RD Read Auto select 80h or 90h 00h 01h 01h A7h Erase Setup Erase Write 20h 20h Erase Verify AOh EVD Program Setup Program 40h PD Program Verify COh Reset Notes 1 Bus operations are defined in Table 1 2 RA Address of the memory location to be read FFh EA Address of the memory location to be read during erase verify PA Address of the memory location to be programmed X Don t care Addresses are latched on the falling edge of the WE pulse 3 RD Data read from location RA during read operation EVD Data Read from location EA during erase verify PD Data to be programmed at location
17. and erase is significantly less than the actual device limit LATCHUP CHARACTERISTICS Parameter Input Voltage with respect to Vgg on all pins except I O pins Including A9 and Vpp 13 5 V Input Voltage with respect to Vgg on all pins I O pins Veco 1 0 V Current 100 mA Includes all pins except Vcc Test conditions Vcc 5 0 V one pin at a time PIN CAPACITANCE Parameter Symbol Parameter Description Test Conditions Input Capacitance Output Capacitance Vpp Input Capacitance Note Sampled not 100 tested Test conditions 1 25 C f 1 0 MHz DATA RETENTION C 10 Minimum Pattern Data Retention Time Am28F010 31 AMDA PHYSICAL DIMENSIONS PD032 32 Pin Plastic DIP measured in inches 1 640 ig 1 670 E 32 17 530 Pin 1 1 D mag ILI LT J J TT I 045 065 005 MIN ET La 140 2 f SEATING PLANE b s d T UTI I m Dr 016 a md E 625 rr 630 700 gt PL032 32 Pin Plastic Leaded Chip Carrier measured in inches 16 038 8 AG PD 032 EC75 5 28 97 lv
18. ation is formed by a combination of AM28F010 70 J C B Ie OPTIONAL PROCESSING Blank Standard Processing B Burn In Contact an AMD representative for more information TEMPERATURE RANGE C Commercial 0 C to 70 C Industrial 40 C to 85 C E Extended 55 C to 125 C PACKAGE TYPE P 32 Pin Plastic DIP PD 032 J 32 Pin Rectangular Plastic Leaded Chip Carrier PL 032 E 32 Pin Thin Small Outline Package TSOP Standard Pinout TS 032 F 32 Pin Thin Small Outline Package TSOP Reverse Pinout TSR032 SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER DESCRIPTION Am28F010 1 Megabit 128 K x 8 Bit CMOS Flash Memory Valid Combinations Valid Combinations m Valid Combinations list configurations planned to be sup AM28F010 70 ported in volume for this device Consult the local AMD sales office to confirm availability of specific valid combinations and AM28F010 90 de ji JE to check on newly released combinations AM28F010 120 EL Tr EC El EE AM28F010 150 FC Fl FE AM28F010 200 Am28F010 5 AMDA PIN DESCRIPTION A0 A16 Address Inputs for memory locations Internal latches hold addresses during write cycles CE Ez Chip Enable active low input activates the chip s con trol logic and input buffers Chip Enable high will dese lect the device and operates the chip in stand by mode DQ0 DQ7 Data Inputs durin
19. c 2 V normal TTL or CMOS input levels where n 0 or 9 Notes 1 Vpp may be grounded connected with a resistor to ground or lt Voc 2 0 V Vppy is the programming voltage specified for the device Refer to the DC characteristics When Vpp Vppi memory contents can be read but not written or erased Refer to Table 3 for valid Dj during a write operation N 99 O9 a addresses except A9 and AO must be held at Vu Manufacturer and device codes may also be accessed via a command register write sequence Refer to Table 2 11 5 lt Vip lt 13 0 V Minimum Vip rise time and fall time between 0 and Vin voltages is 500 ns Read operation with Vpp Vpp may access array data or the Auto select codes With Vpp at high voltage the standby current is log lpp standby All inputs are Don t Care unless otherwise stated where Don t Care is either V or Vj levels In the Auto select mode all 8 If Voc S 1 0 Volt the voltage difference between Vpp and Vcc should not exceed 10 0 volts Also the Am28F010 has a Vpp rise time and fall time specification of 500 ns minimum Am28F010 READ ONLY MODE When Vppis less than Vcc 2 V the command register is inactive The device can either read array or autose lect data or be standby mode Read The device functions as a read only memory when Vpp lt Vog 2 V The device has two control functions Both must be satisfied in order to output data CE controls power to the d
20. command register Data written to the reg ister serves as input to the internal state machine The output of the state machine determines the operational function of the device The command register does not occupy an addressable memory location The register is a latch that stores the command along with the address and data information needed to execute the command The register is written by bringing WE and CE to Vi while OE is at Vip Addresses are latched on the falling edge of WE while data is latched on the rising edge of the WE pulse Standard microprocessor write timings are used The device requires the OE pin to be Vi for write op erations This condition eliminates the possibility for bus contention during programming operations In order to write OE must be Vin and CE and WE must be Vj If any pin is not in the correct state a write command will not be executed Refer to AC Write Characteristics and the Erase Pro gramming Waveforms for specific timing parameters Command Definitions The contents of the command register default to 00h Read Mode in the absence of high voltage applied to the Vpp pin The device operates as a read only mem ory High voltage on the Vpp pin enables the command register Device operations are selected by writing spe cific data codes into the command register Table 3 de fines these register commands Read Command Memory contents can be accessed via the read com mand when
21. e 6 us duration must be executed to allow for generation of internal voltages for margin checking and read operation section E During Erase verification section F each address that returns FFh data is successfully erased Each address of the array is sequentially verified in this manner by re peating sections D thru F until the entire array is veri fied or an address fails to verify Should an address FLASHRITE PROGRAMMING SEQUENCE Program Setup The device is programmed byte by byte Bytes may be programmed sequentially or at random Program Setup is the first of a two cycle program command It stages the device for byte programming The Program Setup operation is performed by writing 40h to the command register Program Only after the program Setup operation is completed will the next WE pulse initiate the active programming operation The appropriate address and data for pro gramming must be available on the second WE pulse Addresses and data are internally latched on the falling and rising edge of the WE pulse respectively The ris ing edge of WE also begins the programming opera tion You must write the Program verify command to terminate the programming operation This two step sequence of the Setup and Program commands helps to ensure that memory contents are not accidentally written Also programming can only occur when high voltage is applied to the Vpp pin and all control pins are in their proper state In ab
22. e 4 the Flasherase electrical erase algorithm illustrate how commands and bus operations are combined to per form electrical erasure Refer to AC Erase Characteris tics and Waveforms for specific timing parameters Am28F010 11 AMDA FLASHERASE ELECTRICAL ERASE ALGORITHM This Flash memory device erases the entire array in parallel The erase time depends on Vpp temperature and number of erase program cycles on the device In general reprogramming time increases as the number of erase program cycles increases The Flasherase electrical erase algorithm employs an interactive closed loop flow to simultaneously erase all bits in the array Erasure begins with a read of the mem ory contents The device is erased when shipped from the factory Reading FFh data from the device would immediately be followed by executing the Flashrite pro gramming algorithm with the appropriate data pattern Should the device be currently programmed data other than FFh will be returned from address locations Follow the Flasherase algorithm Uniform and reliable erasure is ensured by first programming all bits in the device to their charged state Data 00h This is accomplished using the Flashrite Programming Table 4 Bus Operations Command algorithm Erasure then continues with an initial erase operation Erase verification Data FFh begins at address 0000h and continues through the array to the last address or until data other than FFh i
23. e command register allows for 10096 TTL level control inputs and fixed power supply levels during erase and programming while maintain ing maximum EPROM compatibility Publication 11559 Rev H Amendment 2 Issue Date January 1998 B Flasherase Electrical Bulk Chip Erase One second typical chip erase B Flashrite Programming 10 US typical byte program Two seconds typical chip program B Command register architecture for microprocessor microcontroller compatible write interface B On chip address and data latches R Advanced CMOS flash memory technology Low cost single transistor memory cell B Automatic write erase pulse stop timer AMD s Flash technology reliably stores memory con tents even after 10 000 erase and program cycles The AMD cell is designed to optimize the erase and pro gramming mechanisms In addition the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling The Am28F010 uses a 12 0V X596 Vpp high voltage input to perform the Flasherase and Flashrite algorithms The highest degree of latch up protection is achieved with AMD s proprietary non epi process Latch up pro tection is provided for stresses up to 100 milliamps on address and data pins from 1 V to Vcc 1 V The Am28F010 is byte programmable using 10 ms pro gramming pulses in accordance with AMD s Flashrite programming algorithm The typ
24. evice This pin should be used for spe cific device selection OE controls the device outputs and should be used to gate data to the output pins if a device is selected Address access time tacc is equal to the delay from stable addresses to valid output data The chip enable access time tog is the delay from stable addresses and stable CE to valid data at the output pins The output enable access time is the delay from the falling edge of OE to valid data at the output pins assuming the ad dresses have been stable at least tacc top Standby Mode The device has two standby modes The CMOS standby mode CE input held at Vog 0 5 V con sumes less than 100 pA of current TTL standby mode CE is held at Vj reduces the current requirements to less than 1mA When in the standby mode the out puts are in a high impedance state independent of the OE input If the device is deselected during erasure program ming or program erase verification the device will draw active current until the operation is terminated Output Disable Output from the device is disabled when OE is at a logic high level When disabled output pins are in a high impedance state AMDA Auto Select Flash memories can be programmed in system or in a standard PROM programmer The device may be sol dered to the circuit board upon receipt of shipment and programmed in system Alternatively the device may initially be programmed in a PROM programmer
25. g lt 1 0 Volt the voltage difference between Vpp and Vcc should not exceed 10 0 Volts Also the device has Vpp rise time and fall time specification of 500 ns minimum Reset Command The Reset command initializes the Flash memory de vice to the Read mode In addition it also provides the user with a safe method to abort any device operation including program or erase The Reset command must be written two consecutive times after the setup Program command 40h This will reset the device to the Read mode Following any other Flash command write the Reset command once to the device This will safely abort any previous operation and initialize the device to the Read mode The Setup Program command 40h is the only com mand that requires a two sequence reset cycle The first Reset command is interpreted as program data However FFh data is considered null data during pro gramming operations memory cells are only pro grammed from a logical 1 to 0 The second Reset command safely aborts the programming operation and resets the device to the Read mode Memory contents are not altered in any case This detailed information is for your reference It may prove easier to always issue the Reset command two consecutive times This eliminates the need to deter mine if you are in the setup Program state or not Programming In System Flash memories can be programmed in system or in a standard PROM programmer The device
26. g memory write cycles Internal latches hold data during write cycles Data Outputs during memory read cycles NC No Connect corresponding pin is not connected internally to the die OE G Output Enable active low input gates the outputs of the device through the data buffers during memory read cycles Output Enable is high during command sequencing and program erase operations Vcc Power supply for device operation 5 0 V 596 or 10 Vpp Program voltage input Vpp must be at high voltage in order to write to the command register The command register controls all functions required to alter the mem ory array contents Memory contents cannot be altered when Vpp lt Voc 2 V Vss Ground WE Wit Write Enable active low input controls the write function of the command register to the memory array The tar get address is latched on the falling edge of the Write Enable pulse and the appropriate data is latched on the rising edge of the pulse Write Enable high inhibits writing to the device 6 Am28F010 BASIC PRINCIPLES The device uses 10096 TTL level control inputs to manage the command register Erase and repro gramming operations use a fixed 12 0 V 5 high voltage input Read Only Memory Without high Vpp voltage the device functions as a read only memory and operates like a standard EPROM The control inputs still manage traditional read standby output disable and Auto select modes Command
27. he byte fail to verify reprogram refer to Program Setup Program Figure 3 and Table 5 indi cate how instructions are combined with the bus oper ations to perform byte programming Refer to AC Programming Characteristics and Waveforms for spe cific timing parameters Flashrite Programming Algorithm The device Flashrite Programming algorithm employs an interactive closed loop flow to program data byte by byte Bytes may be programmed sequentially or at ran dom The Flashrite Programming algorithm uses 10 us programming pulses Each operation is followed by a byte verification to determine when the addressed byte has been successfully programmed The program al gorithm allows for up to 25 programming operations per byte per reprogramming cycle Most bytes verify after the first or second pulse The entire sequence of pro gramming and byte verification is performed with high voltage applied to the Vpp pin Figure 3 and Table 5 il lustrate the programming algorithm Am28F010 15 AMDA 16 Start y Apply VppH y PLSCNT 0 y Write Program Setup Command y Write Program Command A D y Time out 10 us Y Write Program Verify Command Increment Address Y Time out 6 us Read Data from Device Verify Byte Yes i Yes Increment PLSCNT Write Reset Command
28. ical room temperature programming time of the Am28F010 is two seconds The entire chip is bulk erased using 10 ms erase pulses according to AMD s Flasherase alrogithm Typical era sure at room temperature is accomplished in less than one second The windowed package and the 15 20 AMDA minutes required for EPROM erasure using ultra violet light are eliminated Commands are written to the command register using standard microprocessor write timings Register con tents serve as inputs to an internal state machine which controls the erase and programming circuitry During write cycles the command register internally latches address and data needed for the programming and erase operations For system design simplifica tion the Am28F010 is designed to support either WE or CE controlled writes During a system write cycle addresses are latched on the falling edge of WE or CE whichever occurs last Data is latched on the ris BLOCK DIAGRAM Voc gt V Erase Voltage State WERE Control Command Register iam Voltage Switch CER OE ing edge of WE or CE whichever occurs first To simplify the following discussion the WE pin is used as the write cycle control pin throughout the rest of this text All setup and hold times are with respect to the WE signal AMD s Flash technology combines years of EPROM and EEPROM experience to produce the highest levels of quality reliability and co
29. lot 5 8 mA Vcc Voc Min Output High Voltage lou 2 5 mA Vec Vec Min A9 Auto Select Voltage A9 Vip A9 Auto Select Current A9 Vip Max Voc Voc Max Vpp during Read Only Operations Note Erase Program are inhibited when Vpp VepL Vpp during Read Write Operations Notes Low Vcc Lock out Voltage 1 Caution The Am28F010 must not be removed from or inserted into a socket when Vcc or Vpp is applied If Voc lt 1 0 Volt the voltage difference between Vpp and Vcc should not exceed 10 0 Volts Also the Am28F010 has a Vpp rise time and fall time specification of 500 ns minimum 2 lec is tested with OE Vi to simulate open outputs 3 Maximum active power usage is the sum of loc and lpp 4 Not 100 tested Am28F010 23 AMDA DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Input Leakage Current Test Conditions Voc Voc Max Vin Voc or Vss Output Leakage Current Voc Voc Max Vout Vog or Vss Vec Standby Current Voc Vec Max CE Vec 0 5V Voc Active Read Current Voc Vec Max CE Vi OE Vin lout 0 mA at 6 MHz Vec Programming Current CE Vi Programming in Progress Note 4 Voc Erase Current CE Vi Erasure in Progress Note 4 Vpp Standby Current Vpp VepL Vpp Read Current Vpp VepH Vpp Programming Current Vpp VppH Programming in Pr
30. mation Standard Products The 70 speed option is now listed in the example Valid Combinations Added 70 deleted 95 and 250 combinations Operating Ranges Vcc Supply Voltages Added 70 deleted 95 and 250 speed options AC Characteristics Read Only Operations Characteristics Added the 70 column and test conditions Deleted 95 and 250 speed options Trademarks Copyright 1998 Advanced Micro Devices Inc All rights reserved ExpressFlash is a trademark of Advanced Micro Devices Inc AMDA AC Characteristics Write Erase Program Operations Added the 70 col umn Deleted 95 and 250 speed options Changed speed option in Note 2 to 70 Switching Test Waveforms In the 3 0 V waveform caption changed 95 to 70 Revision H Matched formatting to other current data sheets Revision H 1 Figure 3 Flashrite Programming Algorithm Moved end of arrow originating from Increment Address box so that it points to the PLSCNT 0 box not the Write Pro gram Verify Command box This is a correction to the diagram on page 6 189 of the 1998 Flash Memory Data Book Revision H 2 Programming In A PROM Programmer Deleted the paragraph Refer to the AUTO SELECT paragraph in the ERASE PROGRAM and READ MODE section for programming the Flash memory de vice in system AMD the AMD logo and combinations thereof are registered trademarks of Advanced Micro Devices Inc Product names used in this
31. o 414 0 V Vpp Note 21 nanananannaaa 2 0 V to 414 0 V Output Short Circuit Current Note 3 200 mA Notes 1 Minimum DC voltage on input or I O pins is 0 5 V During voltage transitions inputs may overshoot V ss to 2 0 V for periods of up to 20 ns Maximum DC voltage on input and VO pins is Vog 0 5 V During voltage transitions input and I O pins may overshoot to Voc 2 0V for periods up lo 20ns 2 Minimum DC input voltage on A9 and Vpp pins is 0 5 V During voltage transitions A9 and Vpp may overshoot Vss to 2 0 V for periods of up to 20 ns Maximum DC input voltage on A9 and Vpp is 413 0 V which may overshoot to 14 0 V for periods up to 20 ns 3 No more than one output shorted to ground at a time Duration of the short circuit should not be greater than one second Stresses above those listed under Absolute Maximum Rat ings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the opera tional sections of this specification is not implied Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability AND OPERATING RANGES Commercial C Devices Ambient Temperature TA 0 C to 70 C Industrial I Devices Ambient Temperature TA 40 C to 85 C Extended E Devices Ambient Temperature Ta 55
32. ogress Note 4 Vpp Erase Current Vpp VppH Erasure in Progress Note 4 Input Low Voltage Input High Voltage Output Low Voltage lot 5 8 mA Voc Vec Min Output High Voltage lou 2 5 mA Vac Voc Min lou 100 HA Vec Vec Min A9 Auto Select Voltage A9 Auto Select Current A9 Vip Max Voc Voc Max Vpp during Read Only Operations Note Erase Program are inhibited when Vpp VepL Vpp during Read Write Operations Low Vcc Lock out Voltage Notes 1 Caution The Am28F010 must not be removed from or inserted into a socket when Vog or Vpp is applied If Voc lt 1 0 volt the voltage difference between Vpp and Vcc should not exceed 10 0 volts Also the Am28F010 has a Vpp rise time and fall time specification of 500 ns minimum 2 loc is tested with OE Vi to simulate open outputs 3 Maximum active power usage is the sum of loc and lpp 4 Not 100 tested 24 Am28F010 AMDA 25 20 15 lcc Active in mA 0 1 2 3 4 5 6 7 8 9 10 11 12 Frequency in MHz 11559G 13 Figure 5 Am28F010 Average Icc Active vs Frequency Voc 5 5 V Addressing Pattern Minmax Data Pattern Checkerboar TEST CONDITIONS Table 6 Test Specifications Test Condition All others 2 7 KQ Output Load 1 TTL gate Output Load Capacitance C including jig capacitance 100 GE 6 2 kQ Input Rise and Fall Times
33. or margin checking and read operations section E During program verification section F each byte just programmed is read to compare array data with original program data When successfully verified the next de sired address is programmed Should a byte fail to ver ify reprogram the byte repeat section A thru F Each data change sequence allows the device to use up to 25 program pulses per byte Typically bytes are verified within one or two pulses Algorithm Timing Delays There are four different timing delays associated with the Flasherase and Flashrite algorithms 1 The first delay is associated with the Vpp rise time when Vpp first turns on The capacitors on the Vpp bus cause an RC ramp After switching on the Vpp the delay required is proportional to the number of devices being erased and the 0 1 mF device Vpp must reach its final value 100 ns before commands are executed 2 The second delay time is the erase time pulse width 10 ms A software timing routine should be run by the local microprocessor to time out the delay The erase operation must be terminated at the conclu sion of the timing routine or prior to executing any System interrupts that may occur during the erase operation To ensure proper device operation write the Erase verify operation after each pulse 3 Athird delay time is required for each programming pulse width 10 ms The programming algorithm is interactive and verifies each byte after
34. publication are for identification purposes only and may be trademarks of their respective companies Am28F010 35 WWW ALLDATASHEET COM Copyright Each Manufacturing Company All Datasheets cannot be modified without permission This datasheet has been download from www AllDataSheet com 10096 Free DataSheet Search Site Free Download No Register Fast Search System www AllDataSheet com
35. rs The Vpp power supply can be hard wired to the device or switchable When Vpp is switched Vpp may be ground no connect with a resistor tied to ground or less than Vog 2 0 V 2 Erase Verify is performed only after chip erasure A final read compare may be performed optional after the register is written with the read command 3 The erase algorithm Must Be Followed to ensure proper and reliable operation of the device 12 Am28F010 Start Ws Data 00h y No Program All Bytes to 00h Y gt Apply Veru Y Address 00h PLSCNT 0 y Write Erase Setup Command Y Write Erase Command Y Time out 10 ms Y Write Erase Verify Time out 6 us Y Read Data from Device Increment PLSCNT Apply VppL Y Erase Error Figure 1 Yes AMDA Increment Address y Write Reset Command y Apply VppL y Erasure Completed Am28F010 Flasherase Electrical Erase Algorithm 11559G 6 AMDA Section A B 2 VA AV KOM Addresses Bus Cycle Command 11559G 7 D E F G Time out Standby Compare WA Data N A Function Proceed per Erase Algorithm Erase Verification Transition 6 us Figure 2 AC Waveforms For Erase
36. s Proceed per Programming Algorithm Program Transition Verify 6 us Program Verification Figure 4 AC Waveforms for Programming Operations ANALYSIS OF PROGRAM TIMING WAVEFORMS Program Setup Program Two cycle write commands are required for program operations section A and B The first program com mand 40h is a Setup command and does not affect the array data section A The second program com mand latches address and data required for program ming on the falling and rising edge of WE respectively section B The rising edge of this WE pulse section B also initiates the programming pulse The device is programmed on a byte by byte basis either sequentially or randomly The program pulse occurs in section C Time Out A software timing routine 10 us duration must be initi ated on the rising edge of the WE pulse of section B Note An integrated stop timer prevents any possibility of overprogramming by limiting each time out period of 10 us Program Verify Upon completion of the program timing routine the mi croprocessor must write the program verify command COh This command terminates the programming op eration on the rising edge of the WE pulse section D The program verify command also stages the device for data verification section F Another software timing 18 Am28F010 routine 6 US duration must be executed to allow for generation of internal voltages f
37. s encountered If a byte fails to verify the device is erased again With each erase operation an increasing number of bytes verify to the erased state Typically devices are erased in less than 100 pulses one second Erase efficiency may be improved by storing the address of the last byte that fails to verify in a register Following the next erase operation verification may start at the stored address location A total of 1000 erase pulses are allowed per reprogram cycle which corresponds to approximately 10 seconds of cumulative erase time The entire sequence of erase and byte verification is performed with high voltage applied to the Vpp pin Figure 1 illustrates the electrical erase algorithm Flasherase Electrical Erase Algorithm Comments Entire memory must 00h before erasure Note 3 Note Use Flashrite programming algorithm Figure 3 for programming Wait for Vpp Ramp to Vpp Note 1 Initialize Addresses PLSCNT Pulse count Erase Setup Data 20h Erase Data 20h Duration of Erase Operation twHwH2 Erase Verify Note 2 Address Byte to Verify Data AOh Stops Erase Operation Write Recovery Time before Read 6 us Read byte to verify erasure Compare output to FFh Increment pulse count Data FFh reset the register for read operations Notes Wait for Vpp Ramp to Vpp Note 1 1 See AC and DC Characteristics for values of Vpp paramete
38. section for voltages When Vog lt Vi ko the command register is disabled all internal program erase circuits are disabled and the device resets to the read mode The device ignores all writes until Voc gt Vi ko The user must ensure that the control pins are in the correct logic state when Vcc gt Vi o to prevent uninitentional writes Write Pulse Glitch Protection Noise pulses of less than 10 ns typical on OE CE or WE will not initiate a write cycle FUNCTIONAL DESCRIPTION Description of User Modes Logical Inhibit Writing is inhibited by holding any one of OE Vj CE Vy or WE Vip To initiate a write cycle CE and WE must be a logical zero while OE is a logical one Power Up Write Inhibit Power up of the device with WE CE Vi and OE V p will not accept commands on the rising edge of WE The internal state machine is automat ically reset to the read mode on power up Table 1 Am28F010 Device Bus Operations Operation CE Ef Read OE G WE W Note 1 Vpp Standby Output Disable Read Onl 9a y Auto Select Manufacturer Code Note 2 Auto Select Device Code Note 2 Read Standby Note 5 Read Write Output Disable Write Legend X Don t care where Don t Care is either Vi or Viz levels Vpp Vpp Voc 2 V See DC Characteristics for voltage levels of Vppy 0 V lt An lt Vo
39. sence of this high voltage memory contents cannot be programmed Refer to AC Characteristics and Waveforms for specific timing parameters Program Verify Command Following each programming operation the byte just programmed must be verified Write COh into the command register in order to initiate the Program verify operation The rising edge of this WE pulse terminates the programming operation The AMDA location fail to verify to FFh data erase the device again Repeat sections A thru F Resume verification section D with the failed address Each data change sequence allows the device to use up to 1 000 erase pulses to completely erase Typically 100 erase pulses are required Note All address locations must be programmed to 00h prior to erase This equalizes the charge on all memory cells and ensures reliable erasure Program verify operation stages the device for verifica tion of the last byte programmed Addresses were pre viously latched No new information is required Margin Verify During the Program verify operation the device applies an internally generated margin voltage to the ad dressed byte A normal microprocessor read cycle out puts the data A successful comparison between the programmed byte and the true data indicates that the byte was successfully programmed The original pro grammed data should be stored for comparison Pro gramming then proceeds to the next desired byte location Should t
40. st effectiveness The Am28F010 electrically erases all bits simultaneously using Fowler Nordheim tunneling The bytes are pro grammed one byte at a time using the EPROM pro gramming mechanism of hot electron injection DQ0 DQ7 Input Output Buffers To Array Chip Enable Output Enable Logic Program Erase Detector A0 A16 PRODUCT SELECTOR GUIDE Family Part Number Y Decoder 1 048 576 Bit X Decoder Cell Matrix Address Latch 11559H 1 Am28F010 Speed Options Vcc 5 0 V 10 120 Max Access Time ns 120 CE E Access ns 120 OE G Access ns 50 2 Am28F010 AMDA CONNECTION DIAGRAMS PDIP VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 AO DQO bat DQ2 Vss 4 2 3 4 5 6 7 8 9 1 1 ere o N O Oo A O Note Pin 1 is marked for orientation Am28F010 Vcc WE W NC A14 A13 A8 A9 A11 OE G A10 CE E DQ7 DQ6 DQ5 DQ4 DQ3 11559H 2 11559H 3 AMDA CONNECTION DIAGRAMS continued TSOP O 1 2 3 4 5 6 7 8 9 eo 32 Pin TSOP Standard Pinout 4 32 Pin TSOP Reverse Pinout 11559H 4 LOGIC SYMBOL DQ0 DQ7 11559H 5 4 Am28F010 AMDA ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges The order number Valid Combin
41. tes of the array in parallel After the erase operation all bytes must be sequentially verified The Erase verify operation is initi AMDA ated by writing AOh to the register The byte address to be verified must be supplied with the command Ad dresses are latched on the falling edge of the WE pulse or CE pulse whichever occurs later The rising edge of the WE pulse terminates the erase operation Margin Verify During the Erase verify operation the device applies an internally generated margin voltage to the addressed byte Reading FFh from the addressed byte indicates that all bits in the byte are properly erased Verify Next Address You must write the Erase verify command with the ap propriate address to the register prior to verification of each address Each new address is latched on the fall ing edge of WE or CE pulse whichever occurs later The process continues for each byte in the memory array until a byte does not return FFh data or all the bytes in the array are accessed and verified If an address is not verified to FFh data the entire chip is erased again refer to Erase Setup Erase Erase verification then resumes at the address that failed to verify Erase is complete when all bytes in the array have been verified The device is now ready to be pro grammed At this point the verification operation is ter minated by writing a valid command e g Program Setup to the command register Figure 1 and Tabl
42. y design not tested 2 Not 100 tested 26 Am28F010 AMDA AC CHARACTERISTICS Write Erase Program Operations Parameter Symbols Am28F010 Speed Options JEDEC Standard Description 70 90 120 150 Write Cycle Time Note 4 Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Recovery Time Before Read Read Recovery TIme Before Write CE Setup Time CE Hold Time Write Pulse Width Write Pulse Width High Duration of Programming Operation Note 2 Duration of Erase Operation Note 2 Vpp Setup Time to Chip Enable Low Note 4 Voc Setup Time to Chip Enable Low Note 4 Vpp Rise Time Note 4 90 Vppy Vpp Fall Time Note 4 10 Vpp Voc lt Vio to Reset Note 4 Notes 1 Read timing characteristics during read write operations are the same as during read only operations Refer to AC Characteristics for Read Only operations 2 Maximum pulse widths not required because the on chip program erase stop timer will terminate the pulse widths internally on the device 3 Chip Enable Controlled Writes Write operations are driven by the valid combination of Chip Enable and Write Enable In systems where Chip Enable defines the Write Pulse Width within a longer Write Enable timing waveform all set up hold and inactive Write Enable times should be measured relative to the Chip Enable waveform 4 Not 1
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