IDT 256K x 36 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O Burst Counter Pipelined Outputs IDT71V65602 IDT71V65802
Contents
1. REVISIONS DEN REV DESCRIPTION APPROVED 0 p ja 0172 572 P1 EVEN LEAD SIDES ODD LEAD SIDES A m n j y pu SEE DETAL A E i 1 E ECT A 8 OR 0 LE HB d DETAIL A EI L r3 I 91 4 4 E JZ aa er I r3 1 1 17 15 y RDB MIN S20 TCT A 8TO SEXE TRTA 8 TO E R08 20 PLANE SEE DETAIL 8 25 E 17 15 1 e EEUU i 202. ZBT Feature 2 5V I O Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges 119 Ball Grid Array BGA Package Diagram Outline REVISIONS DON REV DESCRIPTION DATE APPROVED 0626 oo INITIAL RELEASE 40 16 97 T vu 01 SWITCH amp D DIMENSIONS 04 25 00 ID CORNER M ID CORNER 4 50 MAX BREAK AX pS ee JD 1 i p D T i JO 0f EN 09 D 4 C O0O000000 25120 c ATE 25120 c A T8 119 BALL SHOWN 2 is tn s eee A 1 S L CUu Queer 2 bib JE 1 Al SEATING PLANE integrated Device Teebncigy Inc DECIMAL ANGULAR 2975 Stender Way Sonta Giora 85064 P f 727 118 FAX 409 491 9574 WX 910 536 2070 APPROVALS DATE TITLE BG PACKAGE OUTLINE PRAWN lover 14 0 X 22 0 mm BODY PBCA REY E PSC 4065 01 DO NDI SCALE DRAWING SHEET 1 OF 2 REVONS DON REV DESCRIPTION DATE APPROVED DR 90626 vo INTIAL RELEASE 1 7 T vu 01 SWITCH E amp 0 DIMENSIONS 04 28 00 T VU
3. 2 og19ui Jo eu eouenbes eu ui 1 INO eu 10 LY pue oy SHA zy eseq y jo 1 y ejep jxeu eui 27 q zy euieyxe y 392 ay suasauda zy q Hy sseuppe oj 1511 ay 1 a gt 20 058 SIM SWIM euijedig 151 lt HM euredig gt oers emu oy 86 5 20 H 11ueuno sdeJM sing GH S ufiu N32 H as awa Xe ev a awa wa Commercial and Industrial Temperature Ranges N EP gt 851 2H p 2 55 us SRAMSs with lt p VS e lt RP 5 o 52 nS 98 Jc T x ns 4 v 8 oo i2 e om gt Te EG aN a 10 O gt TA re m Timing Waveform of Write Cycles 1 2 3 4 5
4. DL e pep pe pe e Eo Depp prese Deo ela bb NOTES 5308 12 1 L is defined CE1 L L and CE2 is defined as CE1 H H or CE L 2 H High L Low X Don t Care Z High Impedance r gt lt gt lt gt lt E gt lt gt lt x 5 HERE Read Operation E S CARE RS Setup Vai we x x x x j x x eons oases ho Rend ou 5308 tbl 13 NOTES 1 H High L Low X Don t Care 2 High Impedance __ e 2 L is defined CE1 L CE2 L and CE2 H CE is defined as H CE or L IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMS with ZBT Feature 2 5V Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges Burst Read Operation 0 X X X 5308 tbl 14 NOTES 1 H High Low X Don t Care 2 High Impedance 2 E L is defined as CE1 L L and CE2 H is defined as CE1 H H or L Write Operation 5303 tbl 15 E L is defined as CE1 L L and CE2 is defined as CE1 H H or L Burst Wr
5. D D H D QOO J D K D D 00000 00000 D OQ 0 9 O Q N D 1100000000000 R H Tks EH e 9 15 A B uale 2 40 U 165 BALL SHOWN M SEATING PLANE 591 DINEM Deos PENSAU ne Dz Stender Woy Sonia Clore D 06054 enone 727 018 ER d FAX 408 492 8674 TWX 910 838 2070 APPROVALS DATE Wit BQ PACKAGE OUTLINE DRAWN P 13 0 X 15 0 mm BODY CHEERED FPBCA SE DRAWING RET C PSC 4086 00 NOT SCALE DRAWING SHEET 1 oF 2 REVISIONS DESCRIPTION DATE APPROVED en ges 00 05 01 08 B t NOTES 1 DIMENSIONING AND TOLERANCING CONFORM TO ASVE Y14 5M 1994 LL DIMENSI D TOLERANCING CONFORM T ASME Y14 5M 199 00000 00000 2 16 REPRESENTS THE BASIC SOLDER BALL GRID PITCH 00000 00000 3 W REPRESENTS THE MAXIMUM SOLDER BALL MATRIX SIZE 4 REPRESENTS THE BALLCOUNT NUMBER DMENSDN b E MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TG PRIMARY DATUM 6 K SEATING PLANE AND PRIMARY DATUM 0 ARE DEFINED BY THE GOD OU 00 5 5 SPHERICAL CROWNS OF THE SOLDER BALLS L
6. gt 5 7 WVHS ojuoo pue 5 5 Mau jeu s eur 5 eui M Jo sseooe 15 y jo enjeu yL HOIH perdues Busing WYHS S Suidwes Aq WHS pue ssejppe Meu ueuw jsing 5 S 230 uo MOT 230 pue 39 ueuw ejdurexe 104 speufis 239 pue 49 eui yng eonuep 230 2 Indu 087 34 ay 1 4 pow 10 y pue Qv SYA ssejppe eseq jo eouenbes sunq 3xeu y sjuesa1dei 1 2 zy 55 eui sjuese1dei zy Hy ssejppe OY 1ndino 15 BU 51 1y D 1 2 SALON s 90 5058 lt 5 euijedig 1sung peed 5 TON 8 gt 5 5 200 AX ez 0 XX Wd XX inoviva Wels H 11ueuno 00 gt Sa a 00 gt 8 sdeJM sing tor yry N39 tMd
7. T71V 65602 A 256 36 512 18 3 3V Synchronous ZBT SRAMs DIL 2 5V Burst Counter Pipelined Outputs Features 256K x 36 512K x 18 memory configurations Supports high performance system speed 150MHz 3 8ns Clock to Data Access ZBT Feature No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R W READ WRITE control pin Positive clock edge triggered address data and control signal registers for fully pipelined applications 4 word burst capability interleaved or linear Individual byte write BW4 control May tie active Three chip enables for simple depth expansion 3 3V power supply 5 2 5V I O Supply Power down controlled by ZZ input Packaged in a JEDEC standard 100 pin plastic thin quad and flatpack TQFP 119 ball grid array BGA and 165 fine pitch ball grid array fBGA Description The IDT71V65602 5802 are 3 3V high speed 9 437 184 bit 9 Megabit synchronous SRAMs They are designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads Thus they have been given the name 2817 or Zero Bus Turnaround Pin Description Summary A C 00 031 1 4 Address and control signals are applied to the SRAM during one clock cycle andtwocycleslaterthe associated datacycleoccurs beitreadorwrite
8. av X x Iv Ss3udav kA 4 gt gt w wwe w ww lt tc 7 E gt gt ED x lt x ite x lt x ive gt 7 N H 12 gt T 4 5 Q EJ 5 5 gt N 5 a gt p N 5 N Timing Waveform of Read Cycle 1 2 3 4 3 17 9ui 0 s enjoe ay OM UI apum ejAq MOT s jeuBls ueuw ejo o v pue uo eq ysnw xma sjeufis eyuM 34g G E NVHS 3y jouos pue Meu M Y eui Jo IS eui Aq s M JO pee sseooe jsinq eu jo eeu WYHS SI WH v Suidwes eui pepeo pue Meu spue Ising 2 S 239 siy uo MOT 239 pue 139 104 sjeuis z3 pue 35 0 yng
9. LK ADV LD LBO Z Vss ga Eom _ ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology Inc and the architecture is supported by Micron Technology and Motorola Inc 5308 tbl 01 OCTOBER 2004 2004 Integrated Device Technology Inc DSC 5303 05 IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMs with ZBT Feature 2 5V Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges Pin Definitions MIN E Address Synchronous Address inputs The address register is triggered by combination of the Ed edge of CLK ADV LD low CEN low and true chip enables d Advance E Load ADVILD is a synchronous input that is used to load the intemal registers with new address and control when itis sampled low at the rising edge of clock with the chip selected When ADV LD is low with the chip deselected any burstin progress is terminated When ADV LD is sampled high then the internal burst counter is advanced for any burst that was in progress The extemal addresses are ignored when ADV LD is sampled high Read Write R W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array The data bus activity for the current cycle takes place two clock cycles later Clock Enable Synchronous Clock Enable
10. gt m N e gt T N a 4 5 Q EJ a 5 5 N 5 a gt p N 5 7 ru an N Timing Waveform of Combined Read and Write Cycles 1 2 3 19 INVHS 99 s jenjoe ay amp OM uoneuuojul aum EYL MOT si jeufis pareu 1 9 o o 1 pue uo eq 1 xma sreu amp rs eig 7 9 015 snoi eJd I WHS 5 1000 JOU pip H 7 eui se ji ped SUL vus eui y jo uonisuen H 7 JEU 0019 490 9 Jo eu uo ufu N39 E S 250 sjy uo MOT 230 pue 139 ejdurexe 104 sjeubis pue 139 eui 1nq eonuep 239 2 ey 0 9 109 WYHS sjuesejde zy q HY ay ndino su eu sjueseudei O S231O0N s E 60 5058 5 7121 E E ev O WO a9 ur
11. 2 Pin 84 is reserved for a future 16M 3 DNU Do not use Pins 38 39 42 and 43 are reserved for respective JTAG pins TMS TDI TDO and TCK The current die revision allows these pins to be left unconnected tied Low Vss or tied High 100 TQFP Capacitance 25 C f 1 0MHz Coons ues vs 165 fBGA Capacitance 25 C f 1 0MHz Symbol Parameter Conditions wax Unit On Input cepectanes ToD e Oe O cepactance ToD e 5303 tb 07b NOTE Commercial and Industrial Temperature Ranges Absolute Maximum Ratings Terminal Voltage with Respect to GND Vren Terminal Voltage with 0 5 to V Respect to GND 49 Terminal Voltage with 0 5 to 40 5 V Respect to GND Terminal Voltage with 0 5 to 0 5 V Respect to GND TA Temperature Tero Storage Temperature 5303 tbl 06 NOTES 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability Vpop terminals only terminals only Input terminals only terminal
12. IE ELI dC D A5 15 SEE DEAL C Tb E Lo eI 100 REF 5 48i OC AB ODS DETAIL 5 REF wo PLATING n DEGMAL ANGULAR 2075 Stender Way Senta Clore Ch 05054 A 09 20 09 16 AY XX SEBI 44 PHONE 408 727 8116 NG FAX 408 492 8674 WX 910 338 2070 T 1 APPROVALS oa TLE PACKAGE DUTUNE DRAWN 08 09 94 14 0 X 200 X 1 4 mm TOFP 1 00 10 FORM SIE DRAWING RE DETAIL PSC 4045 DO NOT SCALE DRANNG SHEET 1 OF 2 REVISIONS DCN REV DESCRIPTION DATE APPROVED i VARIATION 0 5 ww WX E LAND PATTERN DIMENSIONS iol 1 60 M 205 10 5 2 1 35 140 145 P1 D 22 00 BSC 4 DI 20 00 BSC B2 1609 650 14 00 BSC 52 c N 100 co F ND 3D 5 2b ES e 65 BX 5 2 32 38 7 E 22 30 33 ELE ES 9 cct 10 co da 13 E co 3 LI co cl co d 1 ALL DIMENSIONING AND TOLERANCING CONFORM ANSI Y14 5M 1982 ZX PACKAGE MAY BE SMALLER THAN BOTTOM PACKAGE BY 15 mm 5 A 8 ano 0 TO BE DETERMINED DATUM PLANE H 2 ZX DIMENSIONS D AND E ARE BE DETERMINED AT SEATING PLANE C MIN MAX DIMENSIONS DI AND E1 00 NOT INCLUDE MOLD PROTRUSION ALLOWABLE P 3280 2100 MOLD PROTRUSION IS 25 mm PER SIDE 01 AND ARE MAXIMUM BODY SIZE DIMENSIONS INCLUDING MOLD MISM
13. The IDT71V65602 5802 contain data I O address and control signal registers Outputenableisthe only asynchronous signal andcan beusedto disablethe outputs atany giventime A Clock Enable CEN pin allows operation ofthe IDT71V65602 5802 tobe suspendedas long as necessary All synchronous inputs are ignored when CEN ishigh andthe internal device registers will hold their previous values There are three chip enable pins CE1 CE2 CE that allow the user to deselectthe device when desired If any one of these three are not asserted when ADV LD is low no new memory operation can be initiated However any pendingdatatransfers reads orwrites willbe completed The databuswilltri statetwo cycles after chipis deselected ora write is initiated The IDT71V65602 5802 have an on chip burst counter In the burst mode the IDT71V65602 5802 can provide four cycles of data for a single address presentedtothe SRAM The order of the burstsequenceis defined bythe LBOinputpin The LBOpinselects between linearandinterleaved burst sequence The ADV LD signalis used toload anew external address ADV LD LOW orincrementthe intemal burst counter ADV LD HIGH The IDT71V65602 5802 SRAM utilize IDT s latest high performance CMOS process andarepackagedina JEDEC Standard 14mmx20mm 100 pin thin plastic quad flatpack TQFP as wellas a 119 ball grid array BGA and a 165 fine pitch ball grid array fBGA foe 0 18 RW CEN BWi BWe BWs
14. 15 Integrated Device Tecbnalogy tnc bbb 25 DECMAL ANGULAR j jam Stender Nay Sonta lore 9500 hou i EE gg me 35 FAX 408 42 8574 910 538 2070 ddd E APPROVALS TITLE BG PACKAGE OUTLINE 10 honar 14 0 X 22 0 mm BODY E PBGA SZE TORAMNG Wa REY C PSC 4065 02 DO NOT SCALE DRAWING SHEET 2 OF 2 IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMS with ZBT Feature 2 5V Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges 165 Fine Pitch Ball Grid Array fBGA Package Diagram Outline REVISIONS DCN DESCRIPTION Date APPROVED 00 RELEASE 05 01 06 10 B M ID CORNER e 6 D Q O OO D 8 D QOO c 2d D OOO 0 0 D D D
15. 78524223521 02 CHANGE PACKAGE THICKNESS 08 05 06 8 C 0 NOTES 1 NL DIMENSIONING AND TOLERANCNG CONFORM TO ANSI Y14 5N 1982 t 66000000 4 ZX SEATING PLANE AND PRIMARY DATUM CC ARE DEFINED BY THE ded i SPHERICAL CROWNS OF THE SOLDER BALLS K 3 WD IS THE BALL MATRIX SIZE IN THE D DIRECTION WE IS THE BALL MATRIX SIZE IN THE E DIRECTION L P N IS THE MAXIMUM ALLOWABLE NUMBER OF SOLDER BALLS Com N A PACKAGE MAY EXTEND EDGE PERIPHERY AND MAY CONSIST OF MOLDING COMPOUND EPOXY METAL CERAMIC OR OTHER MATERIAL DIMENSION b 5 MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER 1 PARALLEL TO PRIMARY DATUM Sas A 1 ID CORNER MUST BE IDENTIFIED IDENTIFICATION MAY BE BY MEANS OF CHAMFER METALLIZED OR INK MARK INDENTATION OR OTHER FEATURE 119 BALL OF THE PACKAGE BODY MARK MUST BE VISIBLE FROM TOP SURFACE ACTUAL SHAPE OF THIS FEATURE IS OPTIONAL DIMENSIONS ARE IN MILLIMETERS i JEDEC VARIATION N 9 DRAWING CONFORMS TO PUBLICATION 95 REGISTRATION MS 028 M VARIATION AA 2 MN NM MX lt 245 2 36 M 50 60 70 120 D 22 00 BSC 01 20 32 BSC E 14 00 BSC El 7 52 BSC ND 17 3 7 3 N 119 3 e 127 85 h e 5 90 5 lt 51 58 81 aoo
16. LN ID CORNER MUST BE IDENTIFED BY CHAMFER INK MARK METALLIZED O OOo MARKING INDENTATION OR OTHER FEATURE GN PACKAGE BODY N IF M ID CORNER 5 ON PACKAGE BODY IT MUST BE LOCATED WITHIN THE ZONE INDICATED P o o o o o 9 ALL DIMENSIONS ARE IN MILLIMETERS R 165 BALL JEDEC VARIATION NOT YET REGISTERED 9 MN NOM MX E A 1 20 30 5 40 A2 85 92 D 1500 BSC E 13 00 5 11 X 15 3 N 165 4 TOLERANEES Slee Woy Sonta landar Way Sonta b 35 4 50 5 L3 Ao INSULAR ESSI ut nme Geos 727 500 CENTER FAX 408 492 8574 910 338 2070 BALL MATRIX N A APPROVALS DATE TITLE BQ PACKAGE OUTLINE DRAWN 150 X 15 0 mm BODY FPBOA SZE ORAWNG RE 6 4086 00 SCALE DIAVNG sweet Z oF 2 IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMS with ZBT Feature 2 5V I O Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges Timing Waveform of OE Operation tOHZ DATAOUT Valid 5303 drw 11 NOTE M 1 A read operation is assumed to be in progress Ordering Information IDT XXXX S XX XX X Process Device Power Speed Package Temperature Range Type Blank Commercial 0 C to 70 C f Industrial 40 C to 85 C
17. P VOP4 VSS A0 VSS 1 00 5 LBO VDD VDD 1 A13 NC O 10 11 14 27 O O O O O O O u __VDDQ DNU 9 DNUG DNU DNU DNUS VDDQ 5303 drw 13A Top View Pin Configuration 512K X 18 119 BGA 1 2 3 4 5 6 7 e 4 2 8 A16 VDDQ O O O B NC CE A3 ADV LD A9 O O O O 7 A2 VDD 13 17 o 1 08 NC vss NC vss l OP1 NC O 1 09 VSS CE1 VSS NC o F VDDQ NC VSS OE VSS 1 06 VDDQ O O o 1 010 BW2 A18 VSS NC O O o H NC vss RAN VSS 1 04 NC O VDDQ VDD VDD 1 VDD VDD 1 VDD VDDQ K NC 1 012 VSS CLK vss NC 1 03 O o O O O L 1 013 NC VSS NC BW1 02 NC M VDDQ 1 014 VSS EN VSS NC VDDQ O O o O O O N 1015 NC VSS A1 VSS O O o o O P NC 2 vss A0 vss NC 1 00 O o o NC A5 LBO VDD VDD 1 A12 NC o T NC A10 A15 NC 14 11 ZZ O O O U __VDDQ DNU 3 DNUG DNUG DNUG DNUG VDDQ 5303 drw 13B Top View NOTES 1 J3 J5 and R5 do not have to be directly connected to as long as the input voltage is gt 2 M is reserved for future 16M 3 DNU Do not use Pin U2 U3 U4 U5 and U6 are reserved for respective JTAG pins TMS TDI and TRST The current die revision allows these pins to be left unconnected
18. 5 WVHS 24 0 pejueseid s enoe y 5 OM UI apum MOT pejduies si jeuBls ueuw pareu s pue uo eq snu XMa sjeuis eg e HOIH S 239 sjy uo 239 pue 130 ejdurexe 104 sjeuBls 232 pue 139 eu 0 jng eonuepi 239 5 WHS eur 0 y zy Hy 5 y 1ndjno 1511 eu sueseJdei 1Y O E SELON 2 z 80 0 9 4 gt a gt lt gt v 3 4y O x WO X WO 5 gt tio 2821 4 00 5 lt gt a gt sy a lt gt dH ds do dH 4 89 4 4280 30 _ 4 lt 1 p OS ay n oy gy vy ely ay 55 gt YS WH gt d gt MS _ 4 IH 701 351 n lt tc 72 o 3 c O gt 72 gt e N 10 x N a Is
19. Input When CEN is sampled high all other synchronous inputs including clock are ignored and outputs remain unchanged The effect of CEN sampled high on the device outputs is as if the low to high clock transition did not occur For normal operation CEN must be sampled low at rising edge of clock BWi BWa Individual Byte LOW Synchronous byte write enables Each 9 bit byte has its own active low byte write enable Write Enables On load write cycles When P W and ADV LD are sampled low the appropriate byte write signal BWi BW4 must be valid The byte write signal must also be valid on each cycle of burst write Byte Write signals are ignored when R W is sampled high The appropriate byte s of data are written into the device two cycles later can all be tied low if always doing write to the entire 36 bit word Chip Enables LOW Synchronous active low chip enable and CE are used with CE2 to enable the IDT71V65602 5802 or CE sampled high or CE2 sampled low and ADV LD low at the rising edge of clock initiates a deselect cycle The ZBT has a two cycle deselect i e the data bus will tri state two clock cycles after deselect is initiated Chip Enable HIGH Synchronous active high chip enable CE2 is used with and CE to enable the chip temm CE has inverted polarity but otherwise identical to CE1 and CEs Clock This is the clock input to the IDT71V65602 5802 Except for OE all timing references fo
20. be in High Z after the first rising edge of clock upon power up Write Operation with Chip Enable Used ELEME t x 2 Bees e fefe f t z x x t nfe x z lt x gt lt gt lt Aias owein x qx Pot gj s x P x z pss x Jor xg wp E x deed a ef e fefe t z 8 ________ t X x m Deed 5303 tbl 20 lt x x 5 1 H High L Low X Don t Care 2 Don t Know Z High Impedance 2 E L is defined as CE1 L CE2 L and CE2 is defined as CE1 H or CE L IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMs with ZBT Feature 2 5V I O Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 3 3V 5 Input Leakage Current Max VN OV to 5308 tbl 21 1 The LBO pin will be internally pulled to if it is not actively driven in the application and the ZZ pin will be internally pulled to Vss if not actively driven DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range von 3 3V 5 Parameter Test Conditions Operating Power Device Selected Outputs Open Supply Curre
21. data bus will tri state two cycles after deselect is initiated 4 When CEN is sampled high at the rising edge of clock that clock edge is blocked from propogating through the part The state of all the internal registers and the Os remains unchanged 5 To select the chip requires CE1 L CE2 L CE2 on these chip enables Chip is deselected if any one of the chip enables is false Device Outputs are ensured to be in High Z after the first rising edge of clock upon power up 7 Q Data read from the device D data written to the device Partial Truth Table for Writes rend m Tee He T tr E LICUIT MN CN NUNC ON CUNT H L WRITE BYTE 4 0 24 31 as pow ee x rc 5308 tbl 09 NOTES 1 L H X Don t Care 2 Multiple bytes may be selected during the same cycle 3 N A for X18 configuration IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMS with ZBT Feature 2 5V Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges Interleaved Burst Sequence Table LBO Vpp First Address NOTE 1 Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting 5308 tbl 10 Linear Burst Sequence Table LBO Vss Third Address 5303 tb
22. ATCH ME ES DETALS OF PIN 1 IDENTIFIER IS OPTIONAL BUT MUST BE LOCATED WITHIN 1680 1700 THE ZONE INDICATED 13 80 1400 ZX DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR 92 PROTRUSION IS 08 mm IN EXCESS OF THE b DIMENSION AT MAXIMUM x 30 50 MATERIAL CONDITION DAMBAR CANNOT BE LOCATED THE LOWER RADIUS e 65 BSC OR THE FOOT N 100 EXACT 5 EACH CORNER 15 OPTIONAL Prep Em Integrated Technology Inc DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN DCCMAL ANGULAR 2975 Stende Woy Sonta CA 95054 pa mam 10 AND 25 mm FROM THE LEAD EN alat Cee an 10 ALL DIMENSIONS ARE IN MILLIMETERS APPROVALS nne PK PACKAGE OUTLINE DRAWN 140 X 200 X 1 4 mm TOFP i1 THIS DUTUNE CONFORMS TO JEDEC PUBLICATION 95 REGISTRATION MO 136 ecran 1 00 10 FORM VARIATION DJ AND SIZE DRAWING Ne REV c P5C 4045 DO NOT SCALE DRAWING SHEET 2 OF 2 IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMs with
23. E1 L CE2 L and CE2 CE is defined as H CE or L Write Operation with C Clock Enable U Used CE SEIL Pe fe trs 277 7 DE EO DS 5303 11 18 gt lt gt lt gt lt 5 1 H High L Low X Don t Care Z High Impedance __ nm 2 L is defined as CE1 L CE2 L and CE CE H is defined as CE1 H CE2 or CE IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMS with ZBT Feature 2 5V Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges Read Operation with Chip Enable Used eC i pe pem oo e e e Ce Hn E a TII NN m a u t gj t fe x 1 gt _____ C C MN 5303 tbl 19 x lt ee ae T T NOTES 1 H High L Low X Don t Care 2 Don t Know Z High Impedance 2 CE L is defined as CE1 L CE2 L and CE CE His defined as CE1 H CE2 H or CE L 3 Device Outputs are ensured to
24. HS eu jo H 7 YEU 40019 Jo Buisu eui uo YBly pejdures E I HOIH S 239 Siy uo MOT 239 pue 139 ejdurexe 404 sjeufiis 239 pue 139 yng jeonuepi 239 2 ey SSauppe 0 y sjuesaidal y q Hy ssejppe 1ndjno 15 1 eu sjuese1dei O 5 SALON LE T 01 5058 2 z o N avo c toy 5 75501 gt 9 md zo ds X 30 5 gt 5 5 lt gt 891 4 lt 280 120 5 5 z e OH 26 1 se d e o N a 9 v of V V IN Ss3qudav MEO VHI gt gt 191 SE 5 Wu ow o e gt 9 5 um MS 44 V QYAGV S 8 4 8 R Ssi gt 9 4 ES a 4 SH 4 mq 10 a gt D AS 4 Be XM 8 5 _ mE an ___ NN NS E a OA ye te E 21 IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMS with ZBT Feature 2 5V Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges 100 Pin Thin Plastic Quad Flatpack TQFP Package Diagram Outline
25. PF q 100 pin Plastic Thin Quad Flatpack 100 pin BG gt 119 Ball Grid Array BGA BQ J 165 Fine Pitch Ball Grid Array fBGA 150 133 gt Clock Frequency Megahertz 100 IDT71V65602 256Kx36 Pipelined ZBT SRAM IDT71V65802 512Kx18 Pipelined ZBT SRAM 5303 drw 12 IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMS with ZBT Feature 2 5V Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges Datasheet Document History 12 31 99 03 04 00 04 20 00 05 16 00 07 28 00 11 04 00 12 04 02 12 19 02 10 15 04 IDT Pg 1 14 15 Pg 5 6 Pg 7 Pg 21 Pg 23 Pg 5 8 Pg 7 8 Pg 23 Pg 15 Pg 8 Pg 1 26 Pg 5 6 15 16 25 Pg 1 2 5 6 7 8 Pg 7 Pg 5 6 Pg 7 Created new datasheet from obsolete devices IDT71V656 and IDT71V658 Removed 166MHz speed grade offering Added 150MHz speed grade offering Add JTAG test pins to TQFP pin configuration removed footnote Addclarification note to Recommended Operating Temperature and Absolute Max Ratings tables Add note to BGA Pin configuration corrected typo in pinout Insert TQFP Package Diagram Outline Add new package offering 13 x 15mm 165fBGA Correcterror inthe 119 BGA Package Diagram Outline Remove JTAG pins from TQFP BG119 and BQ165 pinouts refer to IDT71V656xx and IDT71V658xx device errata Correct error in pinout B2 on BG119 and B1 on 80165 pinout Update BG119 Package Diagram Dimens
26. ck 5303 drw 01a Data I O 0 31 P 1 4 IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMS with ZBT Feature 2 5V Burst Counter and Pipelined Outputs Functional Block Diagram Commercial and Industrial Temperature Ranges LBO E Address A 0 18 CE2 CE2 RW gt 2 ADVLD BWx Clk 512x18 BIT MEMORY ARRAY m Address Control Control Logic M m Sel 2 Output Register Clock Y Gate pu Recommended DC Operating Conditions Smo we ws Core Supply Voltage 3 135 VO Supply Voltage 2 375 Input High Voltage Inputs Input High Voltage I O Input Low Voltage NN Cu perve s NN 5308 tbl B NOTES 1 ViL min 1 0 for pulse width less than tcvc 2 once per cycle y 5303 drw 01 Data I O 0 15 P 1 2 IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMS with ZBT Feature 2 5V I O Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges Recommended Operating Temperature and Supply Voltage Ambient Vss Temperature 0 C to 470 C 3 3 5 2 5 5 40 C to 85 3 3V45 2 5 5 NOTES 5 05 1 During production testing the case temperature equals the ambie
27. haracteristics 3 3V 5 Commercial and Industrial Temperature Ranges rant Cus v ________ _ _ _ NEC ________ _ 72290 eres o pene TR DEL pe es esee Output Parameters E Be perra pe pep Advance Load ADV LD Setup Time 5 5 Chip Enable Select Setup Time Byte Write Enable BWx Setup Time E E EU E 15 Clock Enable Hold Time Address Hold Time Data In Hold Time Read Write RW Hold Time Advance Load ADV LD Hold Time gt 5 5 ES e e e e e e gt gt Chip Enable Select Hold Time Byte Write Enable Hold Time NOTES 5303 tbl 24 tF t tcvc Measured as HIGH above 0 6 and LOW below 0 4Vppa Transition is measured 200mV from steady state These parameters are guaranteed with the AC load Figure 1 by device characterization They are not production tested To avoid bus contention the output buffers are designed such that tcuz device turn off is about 1ns faster than 1212 device turn on at a given temperature and voltage The specs as shown do not imply bus contention because 1212 is a Min parameter that is worse case at totally different test conditions 0 deg C 3 465V than tcxz which is a Max parameter worse case at 70 deg C 3 135V
28. ions AddIzz parameter to DC Electrical Characteristics Add note to pin on the 80165 pinout reserved for JTAG TRST Changed datasheet from Preliminary to Final Release Added tempto datasheet Removed JTAG functionality for current die revision Corrected x36 119BGA pin configuration Switched pins 1 00 and Updated temperature Ta note Updated pin configuration 512K x 18 for the 119 BGA reordered I O signals on P7 N6 L6 K7 H6 G7 F6 E7 D6 CORPORATE HEADQUARTERS for SALES for Tech Support 2975 Stender Way 800 345 7015 or 408 727 6116 sramhelp idt com Santa Clara CA 95054 fax 408 492 8674 800 544 7726 www idt com The IDT logo is a registered trademark of Integrated Device Technology Inc 26 Copyright Each Manufacturing Company Datasheets cannot modified without permission This datasheet has been download from www AllDataSheet com 10096 Free DataSheet Search Site Free Download No Register Fast Search System www AllDataSheet com
29. ite Operation s _ tot 1 0 Comments X Address and Control meet setup X Clock Setup Valid Inc Count Address Ao Write Inc Count Do 1 Address Ao 1 Write Inc Count Do 2 Address Ao 2 Write Inc Count Do 3 Address Ao 3 Write Load A1 Address Ao Write Inc Count Di Address A1 Write Inc Count OE uo Eee ENES X ow x x x x 01 1 Address A1 1 Write Load A2 5308 tbl 16 5 1 High L Low X Don t Care 2 Don t Know 2 High Impedance 2 E L is defined as CE1 L CE2 L and CE2 is defined CE1 H CE CE L IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMS with ZBT Feature 2 5V I O Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges Read Operation with Clock Enable Used ee eee x oases ea oma mete Tx e a e L L L L L j gt lt gt lt L x r gt lt a u t fe 1 qon Pot og tr tj x P t a out pustas m u t e fe x Reed ou pustas _____ 5303 tbl 17 gt lt x x rc rc NOTES 1 H High L Low X Don t Care 2 High Impedance m 2 is defined C
30. l 11 NOTE 1 Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting Functional Timing Diagram CYCLE n 29 n 30 n 31 n 32 33 34 35 36 37 _ t LT Lt Lo 2 ADDRESS A29 A30 A31 A32 A33 A34 A35 A36 A37 A0 A17 2 CONTROL RAW ADV LD BWx C29 C30 C31 C32 C33 C34 C35 C36 C37 2 pata D Q27 D Q28 D Q29 D Q30 D Q31 D Q32 D Q33 D Q34 D Q35 0 31 P 1 4 5303 drw 03 NOTES 1 This assumes CEN CE1 CE CE all true 2 All Address Control and Data In are only required to meet set up and hold time with respect to the rising edge of clock Data Out is valid after clock to data delay from the rising edge of clock IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMs with ZBT Feature 2 5V I O Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges Device Operation Showing Mixed Load Burst Deselect and NOOP Cycles Cycle Address W ADVID cgo CEN BW OE lO Comments CE D p EL pesas 3 as ED Poe fos L Deselect or STOP i pepe pe EDD E EE e o e pepe Cow
31. ma 091 gt m ZHO NIVLVd rr dS N 30 gt dS X39 39 _ 4 lt OS sv ey ay x ss3uaav gt VSI 4 p MS 19 pa HO pu 72 o 5 2 c gt 72 gt N 10 ire N e Is gt a e 19 O gt m N H a 4 5 Q EJ Pn 5 gt N E a 2 gt D N I 5 c o N Timing Waveform of CEN Operation 1 2 3 4 20 24 0 s jenjoe eui sejoKo SUL MOT si jeu amp is ueuw 51 apum v pue apum uo eq 1 xma aM ex g 7 eyeis snoi eJd urejei IM WHS peurejur 1000 E JOU pip 201 H 7 eui i se ji Wed 1 WY
32. not have to be directly connected to as long as the input voltage is gt VH 2 B9 B11 A1 R2 and P2 is reserved for future 18M 36M 72M 144M and 288M respectively 3 DNU Do not use Pins P5 R5 P7 R7 and N5 are reserved for respective JTAG pins TDI TMS TDO TCK and TRST on future revisions The current die revision allows these pins to be left unconnected tied LOW Vss or tied HIGH IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMs with ZBT Feature 2 5V I O Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges Synchronous Truth Table CEN RW Chip ADV LD ADDRESS PREVIOUS CYCLE CURRENT CYCLE 1 0 Enable USED 2 later Select LOAD READ X Valid Internal B WRITE BURST WRITE BURST WRITE Advance burst counter Internal LOAD READ BURST READ BURST READ Advance burst counter ao DESELECT or STOP i HER 5308 tbl 08 Deselect 5 1 Vi H X Don t Care 2 When ADV LD signal is sampled high the internal burst counter is incremented The R W signal is ignored when the counter is advanced Therefore the nature of the burst cycle Read or Write is determined by the status of the R W signal when the first address is loaded at the beginning of the burst cycle 3 Deselect cycle is initiated when either CE1 or CE2 is sampled high CE is sampled low and ADV LD is sampled low at rising edge of clock The
33. nt ADV LD X Voo Max VN gt VH or lt Vit f CMOS Standby Power Device Deselected Outputs Open Supply Current Max VN gt or lt VLD 023 Clock Running Power Device Deselected Outputs Open Supply Current Max VN gt or lt VLD f fax 29 Idle Power Device Selected Outputs Open Supply Current CEN gt Max VN gt or lt f Device Selected Outputs Open CEN lt Von Max ZZ gt Vin gt or lt Vib f Full Sleep Mode Supply Current NOTES 5303 16122 1 All values are maximum guaranteed values 2 Af fmax inputs are cycling at the maximum frequency of read cycles of 1 tcvc f 0 means no input lines are changing 3 For I Os 0 2V Vip 0 2V For other inputs Voo 0 2V Vip 0 2V AC Test Load AC Test Conditions 2 5 500 2 Input Pulse Levels 0 2 5V 8 Input Rise Fall Times 2ns 5 Input Timing Reference Levels 2 li Output Timing Reference Levels 2 E AC Test Load See Figure 1 5308 161 23 2030 50 80 100 200 Capacitance pF 5303 drw 05 Figure 2 Lumped Capacitive Load Typical Derating IDT71V65602 IDT71V65802 256K x 36 512K 18 3 3V Synchronous SRAMS with ZBT Feature 2 5V Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges AC Electrical C
34. nt temperature Pin Configuration 256K x 36 _ 9 AN gt Sa e zE 3 352 Op3L_ 1 2 l O16L 2 __ 15 V O17L_ 3 __ 1 014 4 55 05 _ Vss 6 1 013 l O19L 7 1 012 O20L_ 8 1 011 21 9 l O10 VssL_ 10 Vss 11 22 ___ 12 l Oo 23 13 1 08 Vss VppL_ 15 VoD VDD VssL 17 77 O24L_ 18 1 07 O25L_ 19 1 06 VppaL 20 VDDQ VssL 21 Vss O26L_ 22 1 05 1 027 23 1 04 O2z8L_ 24 1 03 O2z9L_ 25 VssL_ 26 Vss 27 VDDQ 28 1 01 1 031 29 _ 4 1 5303 drw 02 8 Qo Top View 100 TQFP NOTES 1 Pins 14 16 and 66 do not have to be connected directly to as long as the input voltage is gt 2 Pin 84 is reserved for a future 16M 3 DNU Do not use Pins 38 39 42 and 43 are reserved for respective JTAG pins TMS TDI TDO and TCK The current die revision allows these pins to be left unconnected tied Low Vss or tied High IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMS with ZBT Feature 2 5V Burst Counter and Pipelined Outputs Pin Configuration 512K x 18 5303 drw 02a Top View 100 TQFP NOTES 1 Pins 14 16 and 66 do not have to be connected directly to as long as the input voltage is gt
35. r the device are made with respect to the rising edge of CLK l Oo l Os1 Data Input Output Synchronous data input output pins Both the data input path and data output path are VOp1 VOp4 registered and triggered by the rising edge of CLK Linear Burst Order LOW Burst order selection input When LBO is high the Interleaved burst sequence is selected When LBO is low the Linear burst sequence is selected LBO is a static input and it must not change during device operation OE Output Enable Asynchronous output enable OE must be low to read data from the IDT71V65602 5802 When OE is high the VO pins are in a high impedance state OE does not need to be actively controlled for read and write cycles In normal operation OE can be tied low 27 Sleep Mode HIGH Asynchronous sleep mode input ZZ HIGH will gate the CLK internally and power down 71V65602 5802 to the lowest power consumption level Data retention is guaranteed in Sleep Mode Power Supply 3 3V core power supply 5303 tbl 02 NOTE 1 Allsynchronous inputs must meet specified setup and hold times with respect to CLK IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMS with ZBT Feature 2 5V I O Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges Functional Block Diagram LBO 256Kx36 BIT MEMORY ARRAY Address A 0 17 Address CE1 CE2 CE2 R W CEN ADV LD Control Input Register Control Logic Clo
36. s only This is a steady state DC parameter that applies after the power supply has reached its nominal operating value Power sequencing is not necessary however the voltage on any input or I O pin cannot exceed during power supply ramp up 7 During production testing the case temperature equals TA Commercial amp Industrial 55 10 125 55 to 125 oof WwW n5 119 BGA Capacitance 25 C f 1 0MHz Input Capacitance Vin 3dV VO Capacitance Vout 3dV 5303 tbl 07a 1 This parameter is guaranteed by device characterization but not production tested IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMS with ZBT Feature 2 5V I O Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges Pin Configuration 256K X 36 119 BGA 1 2 3 4 5 6 A VDDQ A6 2 A4 NC 2 A8 A16 VDDQ O O O NC CE A3 ADV LD A9 CE2 NC O C NC A7 A2 VDD A12 A15 NC O O D 1 016 VOP3 VSS NC VSS 2 1 015 O E 017 1 018 VSS vss 1 013 1 014 F VDDQ 1 019 vss OE vss 1 012 VDDQ O 1 020 1 021 BW3 A17 BW2 1 011 1 010 O H 1 022 1 023 VSS RW VSS 1 09 1 08 J VDDQ VDD VDD 1 VDD VDD 1 VDD VDDQ K 1 024 1 026 VSS CLK VSS 1 06 1 07 O L 025 1 027 BW4 1 04 1 05 M VDDQ 1 028 VSS CEN VSS 1 03 VDDQ N 1029 1 080 VSS A1 VSS 1 02 voi O O O O O Q
37. tied LOW Vss or tied HIGH IDT71V65602 IDT71V65802 256K x 36 512K x 18 3 3V Synchronous SRAMS with ZBT Feature 2 5V Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges Pin Configuration 256K X 36 165 fBGA 1 2 3 4 5 6 7 8 9 10 11 A NC 7 CE BWs BW CE CEN ADVILD A8 NC B NC A6 CE2 BWa Ag C l OP3 NC VDDQ Vss NC D V017 l O16 VDDQ VDD V015 V014 E V019 V018 VDDQ VDD V013 V012 F V021 l O20 VDDQ VDD VO11 VO10 G VO V022 VDDQ VDD 09 H Vpop NC 27 025 l O24 VDDQ VDD V07 1 06 K V027 026 VDDQ 5 04 L 1 029 VO28 VDDQ VDD M vost vow vma vss 101 100 N l OP4 NC VDDQ Vss Vss VDDQ NC VOP1 P NC NC A5 A2 A10 A13 14 R LBO 4 12 15 16 5303 tbl 25a Pin Configuration 512K X 18 165 fBGA 1 2 3 4 5 6 7 8 9 10 11 A 7 CE BW NC CE ADV LD A18 A8 A10 C NC Vss Vss Vss Vss Vss lOP1 D NC Vss Vss Vss 1 07 E NC VO9 VDD Vss Vss Vss VDD 1 06 F NC VDD Vss Vss Vss VDD 05 G NC Vss Vss Vss 1 04 H Vpop VDD Vss Vss Vss VDD 27 J vor Vss Vss Vss Vb NC K 013 Vss Vss Vss 2 NC L l O14 Vss Vss Vss V01 NC M l O15 VDD Vss Vss Vss VOo NC N An 15 LBO A12 A13 A16 A17 NOTES 5303 1256 1 H1 H2 and N7 do
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IDT 256K x 36 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O Burst Counter Pipelined Outputs IDT71V65