AMD Am28F512A handbook
Contents
1. 8 10 20 20 Am28F512A 16 038 TSOP 2 TS 032 DA95 3 25 97 lv PHYSICAL DIMENSIONS AMDA TSR032 32 Pin Reversed Thin Small Outline Package measured in millimeters 0 95 1 05 A n 7 90 EG E 8 10 D ia 0 50 BSC Y J ii I 18 50 19 80 20 20 08 16 038 TSOP 2 lt 0 20 TSR032 i DA95 Y Y 0 10 3 25 97 Iv DATA SHEET REVISION SUMMARY FOR AM28F512A Revision C Deleted 75 95 and 250 speed options Matched for matting to other current data sheets Revision C 1 Programming In A PROM Programmer Deleted the paragraph Refer to the AUTO SELECT paragraph in the ERASE PROGRAM and READ MODE section for programming the Flash memory de vice in system Trademarks Copyright 1998 Advanced Micro Devices Inc All rights reserved ExpressFlash is a trademark of Advanced Micro Devices Inc Revision C 2 Product Selector Guide Corrected maximum access time for 200 to 200 ns Connection Diagrams On standard TSOP corrected pin 9 to Vpp and pin 10 to NC On reverse TSOP corrected pin 23 to NC and pin 24 to Vpp AMD the AMD logo and combinations thereof are registered trademarks of Advanced Micro Devices Inc P2. 1 Caution The Am28F512A must not be removed from or inserted into a socket when Vcc or Vpp is applied If Voc lt 1 0 volt the voltage difference between Vpp and Vcc should not exceed 10 0 volts Also the Am28F512A has a Vpp rise time and fall time specification of 500 ns minimum lcc1 is tested with OE Vi to simulate open outputs 3 Maximum active power usage is the sum of loc and lpp 4 Not 100 tested Am28F512A 21 AMDA DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Input Leakage Current Test Conditions Voc Voc Max Vin Vcc or Vss Output Leakage Current Voc Voc Max Vout Voc or Vss Voc Standby Current Voc Voc Max CE Voc 0 5 V Vcc Active Read Current Voc Voc Max CE Vi OE Vin lout 0 mA at 6 MHz Vec Programming Current CE Vy Programming in Progress Note 4 Voc Erase Current CE Vy Erasure in Progress Note 4 Vpp Standby Current Vpp VppL Vpp Read Current Vpp VppH Vpp Programming Current Vpp VppH Programming in Progress Note 4 Vpp Erase Current Vpp VppH Erasure in Progress Note 4 Input Low Voltage Input High Voltage Output Low Voltage lot 5 8 mA Voc Voc Min Output High Voltage loH 2 5 mA Voc Voc Min lou 100 HA Voc Voc Min A9 Auto Select Voltage A9 Vip A9 Auto Select Current A9 Vip Max Voc
3. Auto Select Flash memories can be programmed in system or in a standard PROM programmer The device may be sol dered to the circuit board upon receipt of shipment and programmed in system Alternatively the device may initially be programmed in a PROM programmer prior to soldering the device to the board The Auto select mode allows the reading out of a binary code from the device that will identify its manufacturer and type This mode is intended for the purpose of automati cally matching the device to be programmed with its cor responding programming algorithm This mode is functional over the entire temperature range of the device Programming In A PROM Programmer To activate this mode the programming equipment must force Vip 11 5 V to 13 0 V on address A9 Two identifier bytes may then be sequenced from the device outputs by toggling address AO from Vi to Vi All other address lines must be held at Vj and Vpp must be less than or equal to Vcc 2 0 V while using this Auto select mode Byte 0 AO Vj represents the manufac turer code and byte 1 AO V p the device identifier code For the device the two bytes are given in the table 2 of the device data sheet All identifiers for manufac turer and device codes will exhibit odd parity with the MSB DQ7 defined as the parity bit Table 2 Am28F512A Auto Select Code Type Manufacturer Code Device Code 10 Am28F512A ERASE PROGRAM AND READ M
4. Read Standby Note 5 Read Write Output Disable Write Legend X Don t care where Don t Care is either Vy or Vj levels Vpp Vpp lt Voc 2 V See DC Characteristics for voltage levels of Vppy 0 V lt An lt Voc 2 V normal TTL or CMOS input levels where n 0 or 9 Notes 1 Vpp may be grounded connected with a resistor to ground or lt Voc 2 0 V Vppy is the programming voltage specified for the device Refer to the DC characteristics When Vpp Vpp memory contents can be read but not written or erased Manufacturer and device codes may also be accessed via a command register write sequence Refer to Table 2 11 5 lt Vip lt 13 0 V Minimum Vip rise time and fall time between 0 and Vp voltages is 500 ns Read operation with Vpp Vppy may access array data or the Auto select codes With Vpp at high voltage the standby current is loc lpp standby Refer to Table 3 for valid D y during a write operation All inputs are Don t Care unless otherwise stated where Don t Care is either Vy or Vi levels In the Auto select mode all addresses except Ag and Ag must be held at V If Vcc x 1 0 Volt the voltage difference between Vpp and Vcc should not exceed 10 0 volts Also the Am28F256 has a Vpp rise time and fall time specification of 500 ns minimum NQaAAWND So Am28F512A 9 AMDA READ ONLY MODE When Vppis less than Vcc 2 V the command register is
5. Input Output AC Testing all speed options except 70 Inputs are driven at 2 4 V for a logic 1 and 0 45 V for a logic 0 Input pulse rise and fall times are 10 ns AMDA 3V 4 _ Test Points 0v Input Output AC Testing for 70 devices Inputs are driven at 3 0 V for a logic 1 and 0 V for a logic 0 Input pulse rise and fall times are lt 10 ns 18880C 17 SWITCHING CHARACTERISTICS over operating range unless otherwise specified AC Characteristics Read Only Operation Parameter Symbols JEDEC Standard Read Cycle Time Note 2 Parameter Description Am28F512A Speed Options 70 90 120 150 Chip Enable Access Time Address Access Time Output Enable Access Time Chip Enable to Output in Low Z Note 2 Note 1 Chip Disable to Output in High Z Note 2 Output Enable to Output in Low Z Output Disable to Output in High Z Note 2 CE or OE Change Note 2 Output Hold from first of Address Voc Setup Time to Valid Read Note 2 Notes 1 Guaranteed by design not tested 2 Not 100 tested Am28F512A 24 AMDA AC Characteristics Write Erase Program Operations Parameter Symbols Am28F512A Speed Options JEDEC Standard Parameter Description 90 120 150 tavav Write Cycle Time Note 4 tavwL Address Setup Time twLAX Address Hold Time tovwH Dat
6. Voc Max Vpp during Read Only Operations Note Erase Program are inhibited when Vpp VppL Vpp during Read Write Operations Low Vcc Lock out Voltage Notes 1 Caution The Am28F512A must not be removed from or inserted into a socket when Voc or Vppis applied If Voc lt 1 0 volt the voltage difference between Vpp and Vcc should not exceed 10 0 volts Also the Am28F512A has a Vpprise time and fall time specification of 500 ns minimum 2 Iccy is tested with OE Vi to simulate open outputs 3 Maximum active power usage is the sum of loc and lpp 4 Not 100 tested 22 Am28F512A AMDA 25 20 lt E 15 o 2 lt Q S 0 1 2 3 4 5 6 7 8 9 10 11 12 Frequency in MHz 18880B 15 Figure 7 Am28F512A Average lcc Active vs Frequency Voc 5 5 V Addressing Pattern Minmax Data Pattern Checkerboard TEST CONDITIONS Table 6 Test Specifications a o lt Test Condition All others 2 7kQ Output Load 1 TTL gate Output Load Capacitance C including jig capacitance 100 EE 6 2 kQ Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels IHH Note Diodes are IN3064 or equivalent Output timing measurement reference levels 18880C 16 Fiaure 8 Test Setup 23 Am28F512A SWITCHING TEST WAVEFORMS 24V 2 0V 2 0V Test Points lt 0 8V 0 8V 0 45 V
7. 2 Minimum DC input voltage on A9 and V pp pins is 0 5 V During voltage transitions A9 and Vpp may overshoot Vss to 2 0 V for periods of up to 20 ns Maximum DC input voltage on A9 and Vpp is 13 0 V which may overshoot to 14 0 V for periods up to 20 ns 3 No more than one output shorted to ground at a time Duration of the short circuit should not be greater than one second Stresses above those listed under Absolute Maximum Rat ings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the opera tional sections of this specification is not implied Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability AMDA OPERATING RANGES Commercial C Devices Ambient Temperature Ta 0 C to 70 C Industrial 1 Devices Ambient Temperature TA 40 C to 85 C Extended E Devices Ambient Temperature Ta 55 C to 125 C Vcc Supply Voltages VOO excede mI ee Mat du aah 4 50 V to 5 50 V Vpp Voltages Read iss fol Va EISE 0 5 V to 412 6 V Program Erase and Verify 11 4 V to 12 6 V Operating ranges define those limits between which the functionality of the device is guaranteed Am28F512A 19 AMDA MAXIMUM OVERSHOOT 20 ns 20 ns 0 8 V 0 5 V 2 0V gt 20 ns 18880C 12 Maximum Negat
8. Command Register Program Voltage Switch Chip Enable Output Enable Logic CE OE Embedded y Algorithms Program Erase Detector A0 A15 524 288 X Decoder Bit Cell Matrix Am28F512A 120 120 Address Latch 18880C 1 PRODUCT SELECTOR GUIDE Family Part Number Speed Options Vcc 5 0 V 10 Max Access Time ns CE E Access ns OE G Access ns 120 50 Am28F512A AMDA CONNECTION DIAGRAMS PDIP vpp 1 Voc NC 2 WE W A15 3 NC A12 4 A14 A7 15 A13 A6 16 A8 AS 17 A9 A4 18 A11 A3 9 OE Gif A2 10 A10 A1 11 CE E Ao 12 DQ7 DQO 13 DQ6 bai 14 DQ5 nua DQ2 15 DQ4 Vss 16 DQ3 18880C 2 Note Pin 1 is marked for orientation 4 Am28F512A AMDA CONNECTION DIAGRAMS Continued A11 A9 A8 A13 A14 NC WE Voc Vpp NC A15 A12 A7 A6 A5 A4 OE A10 CE D7 D6 D5 D4 D3 Vss D2 D1 DO AO Al A2 A3 LOGIC SYMBOL 1 2 3 4 5 6 7 8 9 O DONDUIDSDDWIN O 4 OE A10 CE D7 D6 D5 D4 D3 Vss D2 D1 DO AO Al A2 AZ 32 Pin TSOP Standard Pinout A11 A9 A8 A13 A14 NC WE Voc Vpp NC A15 A12 A7 A6 A5 A4 32 Pin TSOP Reverse Pinout 18880C 4 DQ0 DQ7 Gz gt CE EH OE G WE Wf 18880C 5 Am28F512A 5 AMDA ORDERING INFORMATION Standard Product
9. Program Setup Program Data Polling Addresses CE OE tEHEH3 OR 4 gt WE Data let tvPEL 18880C 21 Notes 1 Din Is data input to the device 2 DQ7 is the complement of the data written to the device 3 Doyr is the data written to the device Figure 12 AC Waveforms for Embedded Programming Operation Using CE Controlled Writes Am28F512A 30 AMDA ERASE AND PROGRAMMING PERFORMANCE Limits Typ Max Parameter i Note 1 Note 2 Comments Chip Erase Time Excludes 00h programming prior to erasure Chip Programming Time Excludes system level overhead Write Erase Cycles 100 000 Byte Programming Time Notes 1 25 C 12 V Vpp 2 Maximum time specified is lower than worst case Worst case is derived from the Embedded Algorithm internal counter which allows for a maximum 6000 pulses for both program and erase operations Typical worst case for program and erase is significantly less than the actual device limit 3 Typical worst case 84 us DQ5 1 only after a byte takes longer than 96 ms to program LATCHUP CHARACTERISTICS Parameter Input Voltage with respect to Vgg on all pins except I O pins Including A9 and Vpp Input Voltage with respect to Vgs on all pins I O pins Current Includes all pins except Vcc Test conditions Vcc 5 0 V one pin at a time PIN CAPACITANCE Parameter Symbol Parameter
10. Description Test Conditions Input Capacitance Output Capacitance Vpp Input Capacitance Note Sampled not 100 tested Test conditions T4 25 C f 1 0 MHz DATA RETENTION 10 Minimum Pattern Data Retention Time 31 Am28F512A AMDA PHYSICAL DIMENSIONS PD032 32 Pin Plastic DIP measured in inches 1 640 1 670 di 600 530 Pin 1 1 D 580 Y fl L sl y U U UU I LT LT mM 045 0 065 005 MIN 10 140 225 T H zx p 4 HE NM PLANE 16 038 8 AG PD 032 m ois 120 410 016 EC75 5 28 97 lv 160 022 Sla al PL032 32 Pin Plastic Leaded Chip Carrier measured in inches lt Ea n LO a I 015 I D 042 E 45 056 585 4403 i i 595 L 080 547 F4 095 553 SEATING Y L PLANE La 400 REF L LI 490 i 013 530 Y i o US Por 050 REF 16 038FPO 5 032 7 PL 032 j DA79 TOP VIEW SIDE VIEW 6 28 94 ae Am28F512A 32 AMDA PHYSICAL DIMENSIONS TS032 32 Pin Standard Thin Small Outline Package measured in millimeters 7 90 33 18 30 18 50 19 80
11. command is a command only operation that stages the device for automatic electrical erasure of all bytes in the array Embedded Erase Setup is performed by writing 30h to the com mand register To commence automatic chip erase the command 30h must be written again to the command register The au tomatic erase begins on the rising edge of the WE and terminates when the data on DQ7 is 1 see Write Op eration Status section at which time the device returns to Read mode Figure 1 and Table 4 illustrate the Embedded Erase al gorithm a typical command string and bus operation START Apply Vppy Write Embedded Erase Setup Command Write Embedded Erase Command Data Poll from Device Erasure Completed 18880C 6 Figure 1 Embedded Erase Algorithm Table 4 Embedded Erase Algorithm Bus Operations Command Comments Wait for Vpp Ramp to Vppy see Note Embedded Erase Setup Command Data 30h Embedded Erase Command Data 30h Data Polling to Verify Erasure Compare Output to FFh Available for Read Operations Note See AC and DC Characteristics for values of Vpp parameters The Vpp power supply can be hard wired to the device or switchable When Vpp is switched Vpp may be ground no connect with a resistor tied to ground or less than Voc 2 0 V Refer to Functional Description 12 Am28F512A Embedded Programming Algorithm The Embedded Program Setup is a command only op eration
12. that stages the device for automatic program ming Embedded Program Setup is performed by writing 10h or 50h to the command register Once the Embedded Setup Program operation is per formed the next WE pulse causes a transition to an active programming operation Addresses are latched on the falling edge of CE or WE pulse whichever happens later Data is latched on the rising edge of WE or CE whichever happens first The rising edge AMDA of WE also begins the programming operation The system is not required to provide further controls or timings The device will automatically provide an ade quate internally generated program pulse and verify margin The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit see Write Operation Status section at which time the device returns to Read mode Figure 2 and Table 5 illustrate the Embedded Program algorithm a typical command string and bus operation START Apply Increment Address Last Address Yes Programming Completed VPPH Write Embedded Setup Program Command Write Embedded Program Command A D Data Poll Device 18880C 7 Figure 2 Embedded Programming Algorithm Table 5 Embedded Programming Algorithm Bus Operations Command Comments Wait for Vpp Ramp to Vppy see Note Embedded Program Setup Command Data 10h or 50h Embedded Program Command Valid Address Dat
13. 2518 AM 28F512A fth f A AMA AMD Am28F512A 512 Kilobit 64 K x 8 Bit CMOS 12 0 Volt Bulk Erase Flash Memory with Embedded Algorithms DISTINCTIVE CHARACTERISTICS B High performance 70 ns maximum access time B CMOS low power consumption 30 mA maximum active current 100 pA maximum standby current No data retention power consumption B Compatible with JEDEC standard byte wide 32 Pin EPROM pinouts 32 pin PDIP 32 pin PLCC 32 pin TSOP E 100 000 write erase cycles minimum B Write and erase voltage 12 0 V 5 E Latch up protected to 100 mA from 1 V to Vec 1 V GENERAL DESCRIPTION The Am28F512A is a 512 Kbit Flash memory orga nized as 64 Kbytes of 8 bits each AMD s Flash memo ries offer the most cost effective and reliable read write non volatile random access memory The Am28F512A is packaged in 32 pin PDIP PLCC and TSOP versions It is designed to be reprogrammed and erased in sys tem or in standard EPROM programmers The Am28F512A is erased when shipped from the factory The standard Am28F512A offers access times as fast as 70 ns allowing operation of high speed micropro cessors without wait states To eliminate bus conten tion the Am28F512A has separate chip enable CE and output enable OE controls AMD s Flash memories augment EPROM functionality with in circuit electrical erasure and programming The Am28F512A uses a command register to manage this functionality
14. Definitions table rather than Table 1 Refer to the corresponding data sheet for the actual table or figure The Am28FxxxA family uses 100 TTL level control inputs to manage the command register Erase and reprogramming operations use a fixed 12 0 V 5 high voltage input Read Only Memory Without high Vpp voltage the device functions as a read only memory and operates like a standard EPROM The control inputs still manage traditional read standby output disable and Auto select modes Command Register The command register is enabled only when high volt age is applied to the Vpp pin The erase and repro gramming operations are only accessed via the register In addition two cycle commands are required for erase and reprogramming operations The tradi tional read standby output disable and Auto select modes are available via the register The device s command register is written using standard microprocessor write timings The register controls an internal state machine that manages all device opera tions For system design simplification the device is de signed to support either WE or CE controlled writes During a system write cycle addresses are latched on the falling edge of WE or CE whichever occurs last Data is latched on the rising edge of WE or CE which ever occur first To simplify the following discussion the WEZ pin is used as the write cycle control pin throughout the rest of this text Al
15. ODE When Vpp is equal to 12 0 V 5 the command reg ister is active All functions are available That is the device can program erase read array or autoselect data or be standby mode Write Operations High voltage must be applied to the Vpp pin in order to activate the command register Data written to the reg ister serves as input to the internal state machine The output of the state machine determines the operational function of the device The command register does not occupy an address able memory location The register is a latch that stores the command along with the address and data infor mation needed to execute the command The register is written by bringing WE and CE to Vj while OE is at Vi Addresses are latched on the falling edge of WE while data is latched on the rising edge of the WE pulse Standard microprocessor write timings are used The device requires the OE pin to be Vj for write op erations This condition eliminates the possibility for bus contention during programming operations In order to write OE must be V y and CE and WE must be Vj If any pin is not in the correct state a write command will not be executed AMDA Refer to AC Write Characteristics and the Erase Pro gramming Waveforms for specific timing parameters Command Definitions The contents of the command register default to 00h Read Mode in the absence of high voltage applied to the Vpp pin The device opera
16. a Data Polling to Verify Completion Available for Read Operations Note See AC and DC Characteristics for values of Vpp parameters The Vpp power supply can be hard wired to the device or switchable When V pp is switched Vpp may be ground no connect with a resistor tied to ground or less than Voc 2 0 V Refer to Functional Description Device is either powered down erase inhibit or program inhibit Am28F512A 13 AMDA Write Operation Status Data Polling DQ7 The device features Data Polling as a method to indi cate to the host system that the Embedded algorithms are either in progress or completed While the Embedded Programming algorithm is in oper ation an attempt to read the device at a valid address will produce the complement of expected Valid data on DQ7 Upon completion of the Embedded Program algo rithm an attempt to read the device at a valid address will produce Valid data on DQ7 The Data Polling feature is valid after the rising edge of the second WE pulse of the two write pulse sequence Read Byte DQ0 DQ7 Addr VA Read Byte DQ0 DQ7 Addr VA Note While the Embedded Erase algorithm is in operation DQ7 will read 0 until the erase operation is com pleted Upon completion of the erase operation the data on DQ7 will read 1 The Data Polling feature is valid after the rising edge of the second WE pulse of the two Write pulse sequence The Data Polling f
17. a Setup Time twHDX Data Hold Time t Output Enable Hold Time QER for Embedded Algorithm only tGHWL Read Recovery Time before Write Chip Enable Embedded Algorithm tELWLE Setup Time tWHEH Chip Enable Hold Time twLwH Write Pulse Width twHWL Write Pulse Width HIGH t Embedded Programming Operation WHWH3 Note 2 twHwH4 Embedded Erase Operation Note 2 t Vpp Setup Time to Chip Enable LOW VEEL Note 4 t Voc Setup Time to Chip Enable LOW VCS Note 4 tvppr Vpp Rise Time 90 VPppH Note 4 tvppr Vpp Fall Time 10 VPppL Note 4 tLko Voc lt ViKo to Reset Note 4 Notes 1 Read timing characteristics during read write operations are the same as during read only operations Refer to AC Characteristics for Read Only operations 2 Embedded Program Operation of 14 us consists of 10 us program pulse and 4 ms write recovery before read This is the minimum time for one pass through the programming algorithm 3 Embedded Erase Operation of 5 sec consists of 4 sec array pre programming time and one sec array erase time This is a typical time for one embedded erase operation 4 Not 100 tested 25 Am28F512A AMDA KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady AAA Changing from H to L ITF Changing from L to H XAO Don t Care Any Change Permitted Changing State Unknown Ct Does Not Apply Center Line is High Impe
18. ata If there is not a match the sequence is repeated until there is a match or the sequence has been repeated 1 000 times Commands are written to the command register using standard microprocessor write timings Register con tents serve as inputs to an internal state machine which controls the erase and programming circuitry During write cycles the command register internally latches address and data needed for the program ming and erase operations For system design simpli fication the Am28F512A is designed to support either WE or CE controlled writes During a system write cycle addresses are latched on the falling edge of WE or CE whichever occurs last Data is latched on the rising edge of WE or CE whichever occurs first To simplify the following discussion the WE pin is used as the write cycle control pin throughout the rest of this text All setup and hold times are with respect to the WE signal AMD s Flash technology combines years of EPROM and EEPROM experience to produce the highest lev els of quality reliability and cost effectiveness The Am28F512A electrically erases all bits simulta neously using Fowler Nordheim tunneling The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection 2 Am28F512A AMDA BLOCK DIAGRAM DQ0 DQ7 Voc gt Vss gt V Erase Voltage Input Output dd Switch Buffers To Array State WE Control
19. dance State High Z SWITCHING WAVEFORMS Device and Outputs Data Power up Standby Address Selection Enabled X Valid Standby Power down Addresses X Addresses Stable AAA lt tavav tnc WE W gt taLav toe e terav tce gt taxax ton gt taLox toLz lvcs Output Valid teLax tz Data DQ H tavav tacc 5 0V Voc OV 18880C 18 Figure 9 AC Waveforms for Read Operations Am28F512A 26 AMD SWITCHING WAVEFORMS Embedded Embedded l Erase Setup Erase Erase Data Polling Standby Read Addresses CE laHwL 4 a OE twp WHWH3 OR 4 gt Data Voc m lvPEL 18880C 19 Note DQ7 is the complement of the data written to the device Figure 10 AC Waveforms for Embedded Erase Operation 27 Am28F512A AMDA SWITCHING WAVEFORMS Embedded Embedded Program Setup Program Data Polling Read Addresses gt lt lwHwH3 OR 4 gt gt tVPEL 18880C 20 Notes 1 Dim Is data input to the device 2 DQ7 is the complement of the data written to the device 3 Doyr is the data written to the device Figure 11 AC Waveforms for Embedded Programming Operation Am28F512A 28 AMDA AC CHARACTERISTICS WRITE ERASE PROGRAM OPERATIONS Alternate CE Con
20. described in the Command Definitions table in the corresponding device data sheet Parallel Device Erasure The Embedded Erase algorithm greatly simplifies par allel device erasure Since the erase process is internal to the device a single erase command can be given to multiple devices concurrently By implementing a paral lel erase algorithm total erase time may be minimized Note that the Flash memories may erase at different rates If this is the case when a device is completely erased use a masking code to prevent further erasure over erasure The other devices will continue to erase until verified The masking code applied could be the read command 00h Power Up Power Down Sequence The device powers up in the Read only mode Power supply sequencing is not required Note that if Vcc 1 0 Volt the voltage difference between Vpp and Voc should not exceed 10 0 Volts Also the device has a rise Vpp rise time and fall time specification of 500 ns minimum Reset Command The Reset command initializes the Flash memory de vice to the Read mode In addition it also provides the user with a safe method to abort any device operation including program or erase The Reset must be written two consecutive times after the Setup Program command 10h or 50h This will reset the device to the Read mode Following any other Flash command write the Reset command once to the device This will safely abort any previous operatio
21. dvertent write cycles resulting from Vcc power up and power down transitions or system noise Low Vcc Write Inhibit To avoid initiation of a write cycle during Vcc power up and power down the device locks out write cycles for Voc lt Viko see DC characteristics section for volt ages When Vcc lt Vi o the command register is dis abled all internal program erase circuits are disabled and the device resets to the read mode The device ig nores all writes until Vcc gt Vi o The user must ensure that the control pins are in the correct logic state when Voc gt Vi o to prevent unintentional writes Write Pulse Glitch Protection Noise pulses of less than 10 ns typical on OE CE or WE will not initiate a write cycle Logical Inhibit Writing is inhibited by holding any one of OE Vi CE Viy or WE Vip To initiate a write cycle CE and WE must be a logical zero while OE is a logical one Power Up Write Inhibit Power up of the device with WE CE Vi and OE V y will not accept commands on the rising edge of WE The internal state machine is automati cally reset to the read mode on power up 8 Am28F512A AMDA FUNCTIONAL DESCRIPTION Description Of User Modes Table 1 Am28F512A Device Bus Operations Notes 7 and 8 Vpp Operation Note 1 Read Standby Output Disable Read Only Auto select Manufacturer Code Note 2 Auto select Device Code Note 2
22. eature is only active during Embed ded Programming or erase algorithms See Figures 3 and 4 for the Data Polling timing spec ifications and diagrams Data Polling is the standard method to check the write operation status however an alternative method is available using Toggle Bit VA Byte address for programming XXXXh during chip erase Pass 18880C 8 DQ7 is rechecked even if DQ5 1 because DQ7 may change simultaneously with DQ5 or after DOS Figure 3 Data Polling Algorithm 14 Am28F512A CE OE lt lt tWHWH 3 or 4 DQ0 DQ6 WM DQO0 DGe Invalid DQ7 Valid Data The device has completed the Embedded operation Am28F512A DQ0 DQ7 AN Valid Data L Figure 4 AC Waveforms for Data Polling during Embedded Algorithm Operations AMDA 18880C 9 15 AMDA Toggle Bit DQ6 The device also features a Toggle Bit as a method to indicate to the host system that the Embedded algo rithms are either in progress or completed Successive attempts to read data from the device at a valid address while the Embedded Program algorithm is in progress or at any address while the Embedded Erase algorithm is in progress will result in DQ6 tog gling between one and zero Once the Embedded Pro gram or Erase algorithm is completed DQ6 will stop Read Byte DQ0 DQ7 Addr VA Read Byte DQ0 DQ7 Addr VA Note toggling to indicate the completi
23. inactive The device can either read array or autose lect data or be standby mode Read The device functions as a read only memory when Vpp lt Vcc 2 V The device has two control functions Both must be satisfied in order to output data CE controls power to the device This pin should be used for spe cific device selection OE controls the device outputs and should be used to gate data to the output pins if a device is selected Address access time tacc is equal to the delay from stable addresses to valid output data The chip enable access time tcp is the delay from stable addresses and stable CE to valid data at the output pins The output enable access time is the delay from the falling edge of OE to valid data at the output pins assuming the ad dresses have been stable at least tacc tog Standby Mode The device has two standby modes The CMOS standby mode CE input held at Vcc 0 5 V con sumes less than 100 pA of current TTL standby mode CE is held at Vj reduces the current requirements to less than 1 mA When in the standby mode the out puts are in a high impedance state independent of the OE input If the device is deselected during erasure program ming or program erase verification the device will draw active current until the operation is terminated Output Disable Output from the device is disabled when OE is at a logic high level When disabled output pins are in a high impedance state
24. ive Input Overshoot 20 ns gt Voc 2 0 V Voc 0 5 V 2 0V 20 ns 20 ns 18880C 13 Maximum Positive Input Overshoot 20 ns gt 140V 13 5 V Voc 0 5 V 20 ns 20 ns 18880C 14 Maximum Vpp Overshoot 20 Am28F512A AMDA DC CHARACTERISTICS over operating range unless otherwise specified TTL NMOS Compatible Parameter Symbol Parameter Description Input Leakage Current Test Conditions Voc Voc Max Vin Vcc or Vss Output Leakage Current Voc Voc Max Vout Vcc or Vss Voc Standby Current Voc Voc Max CE Vin Vcc Active Read Current Voc S Voc Max CE Vi OEA Vin lout 0 mA at 6 MHz Vec Programming Current CE Vi Programming in Progress Note 4 Vcc Erase Current CE ViL Erasure in Progress Note 4 Vpp Standby Current Vpp VppL Vpp Read Current Vpp VppH Vpp VppL Vpp Programming Current Vpp VppH Programming in Progress Note 4 Vpp Erase Current Vpp VppH Erasure in Progress Note 4 Input Low Voltage Input High Voltage Output Low Voltage loL 5 8 mA Voc Voc Min Output High Voltage lon 2 5 mA Voc Voc Min A9 Auto Select Voltage A9 Vip A9 Auto Select Current A9 Vip Max Voc Voc Max Vpp during Read Only Operations Note Erase Program are inhibited when Vpp VppL Vpp during Read Write Operations Notes Low Vcc Lock out Voltage
25. l setup and hold times are with re spect to the WEZ signal OVERVIEW OF ERASE PROGRAM OPERATIONS Embedded Erase Algorithm AMD now makes erasure extremely simple and reli able The Embedded Erase algorithm requires the user to only write an erase setup command and erase com mand The device will automatically pre program and verify the entire array The device automatically times the erase pulse width provides the erase verify and counts the number of sequences A status bit Data Polling provides feedback to the user as to the status of the erase operation Embedded Programming Algorithm AMD now makes programming extremely simple and reliable The Embedded Programming algorithm re quires the user to only write a program setup command and a program command The device automatically times the programming pulse width provides the pro gram verify and counts the number of sequences A status bit Data Polling provides feedback to the user as to the status of the programming operation DATA PROTECTION The device is designed to offer protection against acci dental erasure or programming caused by spurious system level signals that may exist during power transi tions The device powers up in its read only state Also with its control register architecture alteration of the memory contents only occurs after successful comple tion of specific command sequences The device also incorporates several features to pre vent ina
26. multiplexing high voltage onto address lines is not a generally desired system design practice The device contains an Auto Select operation to supple ment traditional PROM programming methodologies The operation is initiated by writing 80h or 90h into the command register Following this command a read cycle address 0000h retrieves the manufacturer code of 01h AMD A read cycle from address 0001h returns the device code see the Auto Select Code table of the corresponding device data sheet To terminate the op eration it is necessary to write another valid command such as Reset 00h or FFh into the register 18 Am28F512A ABSOLUTE MAXIMUM RATINGS Storage Temperature 65 C to 150 C Plastic Packages 65 C to 125 C Ambient Temperature with Power Applied 55 C to 125 C Voltage with Respect To Ground All pins except A9 and Vpp Note 1 ses Shuey ere chess ached 2 0 V to 7 0 V Vee Note 1 2 0 V to 47 0 V AG Note llevara rte gs 2 0 V to 14 0 V Vpp Note 2 2 0 V to 14 0 V Output Short Circuit Current Note 3 200 mA Notes 1 Minimum DC voltage on input or I O pins is 0 5 V During voltage transitions inputs may overshoot Vgg to 2 0 V for periods of up to 20 ns Maximum DC voltage on input and I O pins is Vcc 0 5 V During voltage transitions input and I O pins may overshoot to Voc 2 0 V for periods up to 20ns
27. n and initialize the device to the Read mode The Setup Program command 10h or 50h is the only command that requires a two sequence reset cycle The first Reset command is interpreted as program data However FFh data is considered as null data during pro gramming operations memory cells are only pro grammed from a logical 1 to 0 The second Reset command safely aborts the programming operation and resets the device to the Read mode Memory contents are not altered in any case Am28F512A 17 AMDA This detailed information is for your reference It may prove easier to always issue the Reset command two consecutive times This eliminates the need to deter mine if you are in the Setup Program state or not In System Programming Considerations Flash memories can be programmed in system or in a standard PROM programmer The device may be sol dered to the circuit board upon receipt of shipment and programmed in system Alternatively the device may initially be programmed in a PROM programmer prior to soldering the device to the circuit board Auto Select Command AMD s Flash memories are designed for use in appli cations where the local CPU alters memory contents In order to correctly program any Flash memories in system manufacturer and device codes must be accessible while the device resides in the target system PROM programmers typically access the sig nature codes by raising A9 to a high voltage However
28. nd a program verify command followed by a read and compare operation The user is required to time the programming pulse width in order to issue the program verify command An integrated stop timer prevents any possibility of overprogramming Upon completion of this sequence the data is read back from the device and compared by the user with the data intended to be written if there is not a match the sequence is repeated until there is a match or the sequence has been repeated 25 times Embedded Erase Algorithm vs Flasherase Erase Algorithm erase operation status AMD s Embedded Erase algorithm requires the user to only write an erase set up command and erase command The device automatically pre programs and verifies the entire array The device then automatically times the erase pulse width verifies the erase operation and counts the number of sequences A status bit Data Polling provides the user with the The Flasherase Erase algorithm requires the device to be completely programmed prior to executing an erase command To invoke the erase operation the user writes an erase set up command an erase command and an erase verify command The user is required to time the erase pulse width in order to issue the erase verify command An integrated stop timer prevents any possibility of overerasure Upon completion of this sequence the data is read back from the device and compared by the user with erased d
29. on of either Embedded operation Only on the next read cycle will valid data be obtained The toggle bit is valid after the rising edge of the first WE pulse of the two write pulse sequence un like Data Polling which is valid after the rising edge of the second WE pulse This feature allows the user to determine if the device is partially through the two write pulse sequence See Figures 5 and 6 for the Toggle Bit timing specifica tions and diagrams VA Byte address for programming XXXXh during chip erase Y 18880C 10 DQ6 is rechecked even if DQ5 1 because DQ6 may stop toggling at the same time as DQ5 changing to 1 Figure 5 Toggle Bit Algorithm 16 Am28F512A OE Note 18880C 11 DQ6 stops toggling The device has completed the Embedded operation Figure 6 AC Waveforms for Toggle Bit during Embedded Algorithm Operations DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits This is a failure condi tion and the device may not be used again internal pulse count exceeded Under these conditions DQ5 will produce a 1 The program or erase cycle was not successfully completed Data Polling is the only op erating function of the device under this condition The CE circuit will partially power down the device under these conditions to approximately 2 mA The OE and WE pins will control the output disable functions as
30. roduct names used in this publication are for identification purposes only and may be trademarks of their respective companies Am28F512A 34
31. s AMD standard products are available in several packages and operating ranges The order number Valid Combination is formed by a combination of AM28F512A 70 J C B OPTIONAL PROCESSING Blank Standard Processing B Burn In Contact an AMD representative for more information TEMPERATURE RANGE C Commercial 0 C to 70 C Industrial 40 C to 85 C E Extended 55 C to 125 C PACKAGE TYPE P 32 Pin Plastic DIP PD 032 J 32 Pin Rectangular Plastic Leaded Chip Carrier PL 032 E 32 Pin Thin Small Outline Package TSOP Standard Pinout TS 032 F 32 Pin Thin Small Outline Package TSOP Reverse Pinout TSR032 SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER DESCRIPTION Am28F512A 512 Kilobit 64 K x 8 Bit 12 0 Volt CMOS Flash Memory with Embedded Algorithms umm Valid Combinations Valid Combinations Valid Combinations list configurations planned to be sup AM28F512A 70 ported in volume for this device Consult the local AMD sales office to confirm availability of specific valid combinations and AM28F512A 90 de P sE to check on newly released combinations AM28F512A 120 EC El EE AM28F512A 150 FC FI FE AM28F512A 200 6 Am28F512A PIN DESCRIPTION A0 A15 Address Inputs for memory locations Internal latches hold addresses during write cycles CE E Chip Enable active low input activates the chip s con trol logic and inp
32. sing the Em bedded Programming algorithm The Embedded Pro gramming algorithm does not require the system to time out or verify the data programmed The typical room temperature programming time of the Am28F512A is one second Embedded Erase The entire chip is bulk erased using the Embedded Erase algorithm The Embedded Erase algorithm auto matically programs the entire array prior to electrical erase The timing and verification of electrical erase are AMDA controlled internal to the device Typical erasure at room temperature is accomplished in two seconds including AMD s Am28F512A is entirely pin and software com patible with AMD Am28F020A Am28F010A and programming Am28F256A Flash memories Comparing Embedded Algorithms with Flasherase and Flashrite Algorithms Am28F512A with Embedded Algorithms Am28F512 using AMD Flashrite and Flasherase Algorithms Embedded Programming Algorithm vs Flashrite Programming Algorithm AMD s Embedded Programming algorithm requires the user to only write a program set up command and a program command program data and address The device automatically times the programming pulse width verifies the programming and counts the number of sequences A status bit Data Polling provides the user with the programming operation status The Flashrite Programming algorithm requires the user to write a program set up command a program command program data and address a
33. sses are latched on the falling edge of the WE pulse X Dont care 3 RD Data read from location RA during read operation 00h FFh 00h FFh PD Data to be programmed at location PA Data latched on the rising edge of WE 4 Please reference Reset Command section Am28F512A 11 AMDA FLASH MEMORY PROGRAM ERASE OPERATIONS Embedded Erase Algorithm The automatic chip erase does not require the device to be entirely pre programmed prior to executing the Embedded set up erase command and Embedded erase command Upon executing the Embedded erase command the device automatically will program and verify the entire memory for an all zero data pattern The system is not required to provide any controls or timing during these operations When the device is automatically verified to contain an all zero pattern a self timed chip erase and verify be gin The erase and verify operation are complete when the data on DQ7 is 1 see Write Operation Status sec tion atwhich time the device returns to Read mode The system is not required to provide any control or timing during these operations When using the Embedded Erase algorithm the erase automatically terminates when adequate erase margin has been achieved for the memory array no erase ver ify command is required The margin voltages are in ternally generated in the same manner as when the standard erase verify command is used The Embedded Erase Set Up
34. tes as a read only memory High voltage on the Vpp pin enables the command register Device operations are selected by writing specific data codes into the command register Table 3 in the device data sheet defines these register commands Read Command Memory contents can be accessed via the read com mand when Vpp is high To read from the device write 00h into the command register Standard microproces sor read cycles access data from the memory The de vice will remain in the read mode until the command register contents are altered The command register defaults to 00h read mode upon Vpp power up The 00h Read Mode register de fault helps ensure that inadvertent alteration of the memory contents does not occur during the Vpp power transition Refer to the AC Read Characteristics and Waveforms for the specific timing parameters Table 3 Am28F512A Command Definitions First Bus Cycle Second Bus Cycle Address Note 2 Operation Command Note 1 Read Memory Note 4 Data Operation Address Data Note 3 Note 1 Note 2 Note 3 00h FFh RA RD Read Auto select 80h or 90h 00h 01h 01h AEh Embedded Erase Set up Embedded Erase 30h X 30h Embedded Program Set up Embedded Program 10h or 50h PA PD Reset Note 4 Notes 1 Bus operations are defined in Table 1 2 HA Adaress of the memory location to be read PA Adaress of the memory location to be programmed Addre
35. trolled Writes Parameter Symbols Am28F512A Speed Options JEDEC Standard Parameter Description 90 120 150 200 tavav Write Cycle Time Note 4 taveL Address Setup Time tELAX Address Hold Time tpyEH Data Setup Time tEHDX Data Hold Time t Output Enable Hold Time OEH for Embedded Algorithm only tGHEL Read Recovery Time before Write tWLEL WE Setup Time by CE tEHWK WE Hold Time tELEH Write Pulse Width tEHEL Write Pulse Width HIGH t Embedded Programming Operation EHEH3 Note 2 tEHEH4 Embedded Erase Operation Note 3 oi Vpp Setup Time to Chip Enable LOW Note 4 t Vcc Setup Time to Chip Enable LOW ves Note 4 tvpprR Vpp Rise Time 90 VppyH Note 4 typpr Vpp Fall Time 10 VPppL Note 4 tLko Voc VLko to Reset Note 4 Notes 1 Readtiming characteristics during read write operations are the same as during read only operations Refer to AC Characteristics for Read Only operations 2 Embedded Program Operation of 14 us consists of 10 us program pulse and 4 ms write recovery before read This is the minimum time for one pass through the programming algorithm 3 Embedded Erase Operation of 5 sec consists of 4 sec array pre programming time and one sec array erase time This is a typical time for one embedded erase operation 4 Not 100 tested 29 Am28F512A AMD SWITCHING WAVEFORMS Embedded Embedded
36. ut buffers Chip Enable high will dese lect the device and operates the chip in stand by mode DQ0 DQ7 Data Inputs during memory write cycles Internal latches hold data during write cycles Data Outputs during memory read cycles NC No Connect corresponding pin is not connected internally to the die OE G Output Enable active low input gates the outputs of the device through the data buffers during memory read cycles Output Enable is high during command sequencing and program erase operations AMDA Vcc Power supply for device operation 5 0 V 5 or 10 Vpp Program voltage input Vpp must be at high voltage in order to write to the command register The command register controls all functions required to alter the mem ory array contents Memory contents cannot be altered when Vpp lt Voc 2 V Vss Ground WE W4 Write Enable active low input controls the write function of the command register to the memory array The tar get address is latched on the falling edge of the Write Enable pulse and the appropriate data is latched on the rising edge of the pulse Write Enable high inhibits writing to the device Am28F512A 7 AMDA BASIC PRINCIPLES This section contains descriptions about the device read erase and program operations and write opera tion status of the Am29FxxxA 12 0 volt family of Flash devices References to some tables or figures may be given in generic form such as Command
37. while maintaining a JEDEC Flash stan dard 32 pin pinout The command register allows for 100 TTL level control inputs and fixed power supply levels during erase and programming AMD s Flash technology reliably stores memory con tents even after 100 000 erase and program cycles The AMD cell is designed to optimize the erase and Publications 18880 Rev C Amendment 2 Issue Date April 1998 E Embedded Erase Electrical Bulk Chip Erase Two seconds typical chip erase including pre programming B Embedded Program 4 ys typical byte program including time out One second typical chip program B Command register architecture for microprocessor microcontroller compatible write interface B On chip address and data latches E Advanced CMOS flash memory technology Low cost single transistor memory cell B Embedded algorithms for completely self timed write erase operations programming mechanisms In addition the combina tion of advanced tunnel oxide processing and low inter nal electric fields for erase and programming operations produces reliable cycling The Am28F512A uses a 12 0V15 Vpp high voltage input to perform the erase and programming functions The highest degree of latch up protection is achieved with AMD s proprietary non epi process Latch up pro tection is provided for stresses up to 100 milliamps on address and data pins from 1 V to Vcc 1 V Embedded Program The Am28F512A is byte programmable u
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