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NEC PD789426 789436 789446 789456 Subseries User Manual

1. 249 13 4 Setting LCD Controller Driver 253 13 5 LCD Display Data Memory U U U u u uuu u uuu uu u u u u u 253 13 6 Common and Segment Signals U u u u u 254 13 7 Display uuu l k w u uw a 256 13 7 1 Three time slot display example 256 13 7 2 Four time slot display example 22 0004 400 eee ene een tenente nnns 259 14 User s Manual U15075EJ1VOUMOO CHAPTER 14 INTERRUPT 5 2 1 1 1 263 141 Interrupt Function Types 263 14 2 Interrupt Sources and Configuration 263 14 3 Registers Controlling Interrupt Function J u uu u u u u 266 14 4 Interrupt Servicing Operation l u uu u uu u u u u 272 14 4 1 Non maskable interrupt request acknowledgment operation 272 14 4 2 Maskable interrupt request acknowledgment 274 14 4 3 Multiple interrupt servicing x rri ERE reete 275 14 4 4 Putting interrupt requests on 10 04444000444
2. 774 7 157 User s Manual U15075EJ1VOUMOO 7 8 3 Operation as square wave output with 16 bit resolution Square waves of any frequency can be output at an interval specified by the count value preset in CR50 and CR60 To operate as a square wave output with 16 bit resolution settings must be made in the following sequence 1 Disable operation of TM50 and TM60 50 0 TCE60 0 2 Disable output of TO50 and TO60 50 0 60 0 lt 3 gt Seta count clock for timer 60 4 Select either TO60 or TO61 as the timer output pin If TO60 is selected Set P32 to the output mode PM32 0 set the P32 output latch to 0 and set 60 to output enable 1 Use of TO50 is prohibited If TO61 is selected Set P33 to the output mode PM33 0 set the P33 output latch to 0 and set TO61 to output enable TOE61 1 Use of TO5O is prohibited b Set count values in CR50 and CR60 6 Enable the operation of TM60 TCE60 1 Note Start and clear of the timer in the 16 bit timer counter mode are controlled by TCE60 the value of TCE50 is invalid When the count values of TM50 and TM60 simultaneously match the values set in CR50 and CR60 respectively the TO60 pin output will be inverted Through application of this mechanism square waves of any frequency can be output As soon as a match occurs TM50 and
3. La os o ema nene enoe twp oon Remark fx Main system clock oscillation frequency 144 User s Manual U15075EJ1V0UM00 7 8 Figure 7 8 Timing of Interval Timer Operation with 8 Bit Resolution Basic Operation d coma 1 1 I TMn0 CRn0 Count start I 1 INTTMnO Interrupt acknowledgement Interrupt acknowledgement Interrupt acknowledgement 1 1 Count stop Interval time Interval time Interval Remarks 1 Interval N 1 x t N to 2 5 6 nm 50 60 61 Figure 7 9 Timing of Interval Timer Operation with 8 Bit Resolution When 0 Is Set to 00H LI LILI LELIELELELELELELELELELEI TMnO 00H _ G ll s crop oooO INE TCEnO Count start 1 1 er ETT Remark 5 6 50 60 61 User s Manual U15075EJ1VO0UMOO 145 7 8 Figure 7 10 Timing of Interval Timer Operation with 8 Bit Resolution When CRnO Is Set to ewe LE LELELEILILILI LILI LT LE LT LT TT I CD GE GD CI GY ED COD Ga OD Count start INTTMnO Clear Clear
4. 99 Pull up resistor option register B7 100 Pull up resistor option register B8 100 Pull up resistor option register B9 2 0 0 000 i a 101 R Receive buffer register 20 RXB20 prn hr ERR EH ERR EE uere kao uat ues 214 S Serial operation mode register 20 20 215 222 225 237 Subclock control register 107 Suboscillation mode register SCKM 00 enne nennen nnne nnne en nns nnn 106 16 bit capt re register 90 ha tee sei e ERR te Tea and 118 16 bit compare register 90 90 2 222224 4 entretenir innen nentes ettet niens enter nennen nene 118 16 bit timer counter etra ee D b de Mp ree b hdi p bete 118 16 bit timer mode control register 90 90 119 120 T Transmit shiftiregister 20 TXS20 u iie ertet Fed oes te sus asa hene 214 W Watch timer mode control register 173 Watchdog timer clock select register WDC9S l 179 Watchdog timer mode register 180 318 User s Manual U15075EJ1V0UM00 APPENDIX REGISTER INDEX C 2 Register Index
5. 2 Suboscillation mode register SCKM SCKM selects a feedback resistor for the subsystem clock and controls the oscillation of the clock SCKM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SCKM to 00H Figure 5 3 Format of Suboscillation Mode Register Symbol 7 6 Address After reset R W 5 4 3 2 1 0 o o o ese see Feedback resistor selection On chip feedback resistor used On chip feedback resistor not used ontrol of subsystem clock oscillator operation Operation enabled Operation disabled Caution Bits 2 to 7 must be set to 0 106 User s Manual U15075EJ1V0UMO0 CHAPTER 5 CLOCK GENERATOR 3 Subclock control register CSS CSS specifies whether the main system or subsystem clock oscillator is to be selected It also specifies the CPU clock operation status CSS is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSS to 00H Figure 5 4 Format of Subclock Control Register Symbol 7 6 Address After reset R W 5 4 3 2 1 0 o fosfo o nw EN Operation based on the output of the divided main system clock Operation based on the subsystem clock 550 Selection of the main system or subsystem clock oscillator E Divided output from the main system clock oscillator Output from the subsystem clock oscillator Note Bit 5 is read only Caution Bi
6. nennen nennen en nennen entere u 48 3 3 Memory Map uPD798F94306 55 tiet etre teilte Met ned iq cette dei eee 49 3 4 Memory uPD789445 789455 n nennen nene SS ai en nennen 50 3 5 Memory uPD789446 789456 U nennen enne rennen nennen rennen 51 3 6 Memory Map uPD798E94506 D te pete e b ad E DR E 52 3 7 Data Memory Addressing uPD789425 789435 55 3 8 Data Memory Addressing uPD789426 789436 enne 56 3 9 Data Memory Addressing uPD78F9436 57 3 10 Data Memory Addressing uPD789445 789455 menn enne 58 3 11 Data Memory Addressing uPD789446 789456 sss eene enne nns 59 3 12 Data Memory Addressing 078 9456 60 3 13 Program Counter Config ratioh riecht reete ceno react 61 3 14 Program Status Word Configuration 61 3 15 Stack Pointer Configuration edoceri oce ay 63 3 16 Data to Be Saved to Stack Memory 0 4 001000 essent enne nennen enter enses 63 3 17 Data to Be Restored from Stack Memory enn sen nennen enne 63 3 18 General Purpose Register Configuration
7. 119 6 4 16 Timer 123 6 4 1 Operation as timer en nnne en nennen nnns einen 123 6 4 2 Operation as timer u a 125 64 3 Gapt re operation eee DE u HERE RE RR ERE RR REA 126 6 4 4 16 bit timer counter 90 readout ont mi err teer GR Go aaa as 127 0 45 Buzzer OUTPUT reete ederet iter odere eee eee 128 6 5 Notes on Using 16 Bit Timer l 129 CHAPTER 7 8 BIT l 131 7 1 8 BitTimer Functions J u u u uu J J J 131 7 2 8 Bit Timer Config ratlOn 2 2 euer e diee u eee 132 7 3 Registers Controlling 8 Bit Timer nnns 138 7 4 8 Bit Timer Operation suu UU are vans 143 7 4 1 Operation 8 bit timer counter nennen nennen nennen nnn enne 143 7 4 2 Operation as 16 bit timer counter 153 7 4 8 Operation as carri
8. K aon L9O L 10 0901 yoyew JOU seop OSL Jdnueyu juawebpe mouyoe 1dnueiu esneoeq pejejeue jou 1dnueiu 1 1 O9IALLLNI 09851 1 1 09 11 pue esneoeq jou seop OGL esneoeq JON 1 v 1 007 1 7 nn HOO omen noo oan 1 UI JHI U P P P TI uonnjoseg 119 91 eAeM ejenbs jo 81 2 4 159 User s Manual U15075EJ1VOUMOO 7 8 7 4 3 Operation as carrier generator An arbitrary carrier clock generated by TM60 can be output in the cycle set in TM50 To operate timer 50 and timer 60 as carrier generators settings must be made in the following sequence 1 2 3 4 5 6 lt 7 gt lt 8 gt Disable operation of TM50 60 50 0 TCE60 0 Disable timer output of TO50 and 60 50 0 TOE60 0 Set count values in CR50 CR60 and CRH60 Set the operation mode of timer 50 and timer 60 to carrier generator mode see Figures 7 4 and 7 5 Set the count clock for timer 50 and timer 60 Set remote control output to carrier pulse RMC6O bit 2 of carrier generator output control register 60 60 0 Input the required value to NRZB60 bit 1 of TCA60 by program Input a value to NRZ60 bi
9. _ 8 re o gt 0 43 5 80 81 80 81 PUBS Pull up resistor option register B8 PM Port mode register RD Port 8 read signal WR Port 8 write signal 94 User s Manual U15075EJ1VOUMOO CHAPTER 4 PORT FUNCTIONS 4 2 9 Port 9 uPD789426 789436 Subseries only This is an 8 bit I O port with an output latch Port 9 can be specified in the input or output mode in 1 bit units by using port mode register 9 PM9 When using the pins of this port as input port pins on chip pull up resistors can be connected in 1 bit units by using pull up resistor option register B9 PUB9 This port is set in the input mode when the RESET signal is input Figure 4 17 shows a block diagram of port 9 Figure 4 17 Block Diagram of P90 to P97 1 Selector 5 2 inim Output latch P90 to P97 P90 to P97 9 d WRem PM90 to PM97 ENS 9 Pull up resistor option register 9 PM Port mode register RD Port 9 read signal WR Port 9 write signal User s Manual U15075EJ1VOUMOO 95 CHAPTER 4 PORT FUNCTIONS 4 3 Registers Controlling Port Function The ports are controlled by the following two types of registers Port mode registers PMO to 5 7 to PM9 Pull up resistor option registers PUO PUB2 PUB3 PUB7 to PU
10. 298 User s Manual U15075EJ1VOUMOO CHAPTER 19 INSTRUCTION SET This chapter lists the instruction set of the 789426 789436 789446 and 789456 Subseries For the details of the operation and machine language instruction code of each instruction refer to 78K 0S Series Instructions User s Manual U11047E 19 1 Operation 19 1 1 Operand identifiers and description methods Operands are described in Operand column of each instruction in accordance with the description method of the instruction operand identifier refer to the assembler specifications for detail When there are two or more description methods select one of them Alphabetic letters in capitals and symbols are key words and are described as they are Each symbol has the following meaning Immediate data specification 5 Relative address specification e Absolute address specification Indirect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either functional names X A C etc or absolute names names in parenthesis in the table below RO R1 R2 etc can be used for description Table 19 1 Operand Identifiers and Description Methods Description Method X RO A R1 C R2 B R3 E R4 D R5 L R6 H R7 AX RPO BC RP1 DE
11. nente inneren tnter nn nene ten nnne nn 267 Interrupt request flag register 1 l U nennen neret enn nennen nennen 267 External interrupt mode register 0 269 External interrupt mode register 1 00000810 nennen enne nnne nnn nne 269 270 Key return mode register 00 440 0 0 uu u nennen 271 LCD clock coritrol registet u ua Sa 251 LCD display mode register u n S eme deme boe date i mt ba 249 280 LCD voltage amplification control register 0 a 252 Interrupt mask flag 0 U u 268 Interruptirmaskflag register 268 Oscillation stabilization time select register 280 Port Que e e Hm race Dn RM sites 81 Portia un J 82 tu Rea 83 Porti eL eer eee e el edie Rer BOE 89 User s Manual U15075EJ1V0UMO0 319 5 P6 P7 P8 P9 PCC PMO 2 PMB 7 8 9 PUO PUB2 PUB3 PUB7 8 9 R RXB20 S SCKM T TCA60 TCP90 TM50 TM60 90 50 60 TMC90 TXS20 W WDCS WDTM WTM 320 APPENDIX C REGISTER INDEX p
12. 09 41 09 10 8 64 1 1 0901 0 Jae OG 9 1 4 4 0SO L O9IIA L 10 99 9S INL 19 8 09W91 09 1e1s16e1 jndino saeg 09H ejedulo0 19 9 X 090 1 09 1 18 8 pusau 09 jo Z Z User s Manual U15075EJ1VOUMOO 134 1 2 3 CHAPTER 7 8 BIT TIMER Figure 7 3 Block Diagram of Output Controller Timer 60 P32 P33 PM32 PM33 2 TO61 P33 I I I I I I TO60 P32 I I T Timer 60 output signal 8 bit compare register 50 CR50 This 8 bit register is used to continually compare the value set to CR50 with the count value in 8 bit timer counter 50 TM50 and to generate an interrupt request 50 when a match occurs CR50 is set with an 8 bit memory manipulation instruction RESET input makes CR50 undefined Cautions 1 If the CR50 is overwritten during timer operation in the PWM output mode TMD501 1 TMD500 0 a high level may be output
13. T 181 9 4 1 Operation as watchdog crt ett e Re EE RR Fe EE Fra 181 9 422 Operation as interval timet pede ne DE Eee ELE Pega deo 182 CHAPTER 10 8 BIT A D CONVERTER uPD789426 AND 789446 SUBSERIES 183 10 1 8 Bit A D Converter 4 183 10 2 8 Bit A D Converter Configuration u u u u u 183 10 3 8 Bit A D Converter Control Registers u u u 186 10 4 8 Bit A D Converter Operation uu u uu u u u 188 10 4 1 Basic operation of 8 bit A D u rennen 188 10 4 2 Input voltage and conversion result 189 10 4 3 Operation mode of 8 bit A D converter L L a 191 10 5 Cautions Related to 8 Bit A D Converter l u u u u u u 192 CHAPTER 11 10 A D CONVERTER uPD789436 AND 789456 SUBSERIES 197 11 1 10 Bit A D Converter 40 197 11 2 10 Bit A D Converter Configuration 197 11 3 10 Bit A D Converter Control Registers u u u 200 11 4 10 Bit A D Converter Operation
14. nennen L n u 64 4 1 Port Types uPD789426 789436 5 22 244 100000000 eene nennen nennen enne nennen 77 4 2 Port Types uPD789446 789456 Subseries L nnne nnne 78 4 3 Block Diagram ot POO epe e epe E ete E E ete ERR 81 4 4 Block Diagram oft PT0 and ite p OR RE RED 82 4 5 Block Diagram ot P20 d toe et d e ie c dci uie rca redu oth 83 4 6 Block Diagram ot P2 and P206 1 ioi ate 84 4 7 Block Diagram ot P222 rn t qure edd Dr aea ET ben 85 4 8 Block 2 ue e serit re du eter od oett utet ite kanaa ep eate tor ire dete 86 4 9 Block Diagramo 24 etuer EU edie A EEUU eet 87 4 10 Block Diagram f P25 eoe E qure bee de EE Ee de ded 88 4 11 Block Diagram ot P30 m tua ertt rn ttt e x Tene Reg 89 4 12 3 dis EUR FREU 90 4 13 Block Diagram ot P50To P 53 retient ente tt ents tie ed 91 4 14 Block Diagram ot Port 6 riim RED EHE tr LETRAS 92 4 15 Block Diagram of P70 o P72 93 4 16 Block Diagram ot P80 P8 eati etie er de redi ee c Pe oe et 94 4 17 Block Diagram of P90 10 P97 Ec ed een ed nde teris 95 4 18 Format of P
15. u u u u u u u u uuu u 202 11 4 1 Basic operation of 10 bit A D converter enm eene 202 11 4 2 Input voltage and conversion emen eene 203 11 4 3 Operation mode of 10 bit A D nennen 205 11 5 Cautions Related to 10 Bit A D Converter l u 206 CHAPTER 12 SERIAL INTERFACE 20 u u uuu u u u 211 12 1 Serial Interface 20 Functions u u 211 12 2 Serial Interface 20 Configuration uu 211 12 3 Serial Interface 20 Control Registers l l u u uuu u u u u J 215 12 4 Serial Interface 20 Operation U u u u uu u u T T T 222 12 41 Operation Stop mode un asta ch di iere cope fr ted teste hasa su tes 222 12 4 2 Asynchronous serial interface UART 224 1243 3 wire serial I O MODS cette eite h uu evasion Pe Ae 237 CHAPTER 13 LCD 4 4 4 247 13 1 LCD Controller Driver Functions 247 13 2 LCD Controller Driver Configuration 247 13 3 Registers Controlling LCD
16. i I 1 INTTM50 Count start 1 1 1 TO60 TO50 i 148 User s Manual U15075EJ1V0UMO0 2 7 8 Operation as external event counter with 8 bit resolution timer 60 only The external event counter counts the number of external clock pulses input to the TMI60 P31 INTP1 TO50 by using 8 bit timer counter 60 60 To operate timer 60 as an external event counter settings must be made in the following sequence 1 2 lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt 7 gt Disable operation of 8 bit timer counter 60 TM60 0 Disable timer output of TO60 TOE60 0 Set P31 to input mode PM31 1 Select the external input clock for timer 60 see Table 7 5 Set the operation mode of timer 60 to 8 bit timer counter mode see Figures 7 4 and 7 5 Set a count value in CR60 Enable the operation of TM60 TCE60 1 Each time the valid edge is input the value of TM60 is incremented When the count value of TM60 matches the value set in CR60 60 is cleared to 00H and continues counting At the same time an interrupt request signal 60 is generated Figure 7 14 shows the timing of the external event counter operation Caution Be sure to stop the timer operation before overwriting the count clock with different data User s Manual U15075EJ1VO0UMOO 149 7 8 150 Figure 7 1
17. ss 91 veh tein beh niunt iunii tem 92 nn Emden Ree Ree Ete osten 93 ioni eS PE PP I 94 E 95 Processor clock control 24440444400 u u en nennen enne 105 Port mode register ce ae ie e edle el ak a et reet 96 97 Port mode register 1 o sas Ev huc doe dud 96 97 Por Mode registeri2 sn estu etd ee e eade ee a teet gui eot bends 96 97 122 Portmode regist r ne E TR tede 96 97 142 Port mode register b ice ce e edet ce enge ss UE LO ee 96 97 Port mode tregister 7 mau tnd oon eed be dc Ue uta 96 97 Portmode registet 8 ED REEL Re 96 97 Port mode register 9 iue i endete ette 96 97 Pull up resistor optiori register Os sonic nete eee Feier 98 Pull up resistor option register 2 0 99 Pull up resistor option register 3 99 Pull up resistor option register 7 4 0 100 Pull up resistor option register eeepc e erede dS ee 100 Pull up resistor option register 9 00 nennen nnne 101 Receive buffer reg
18. 61 3 22 Generalpurpose registers 22222 eie eee re riter Been rne Re REPE Entra 64 3 2 8 Special function registers 6 2444 0 10 enne nennen nennen nnne nnnm ens 65 3 3 Instruction Address Addressing eese u u u u J T 68 3 3 1 Relative addressing eiit aie e eene o Ee ea eoi 68 3 9 2 Immediate addressing iiie tte iE RR M RR RR rne 69 3 3 3 Table indirectaddressirig ed ee 70 3 9 4 Register addressing since eee arn bale did rete 70 3 4 Operand Address Addressing U u u u u u 71 3 4 1 Direct addressing snie 71 3 4 2 Short direct addressitig 2 imi a anu to pt ie E e eot Hb ee 72 3 4 3 Special function register SFR 73 3 4 44 Register addressing eee tetti 74 3 45 Register indirect addressing eese 75 3 46 76 3 47 Stack addressing 76 CHAPTER 4 6 65 77 MEE cde pec 77 4 2 Port
19. 67 es To 7 6 5 1 0 15 8 7 Memory Table 0 Low Addr Effective address 1 High Adar 15 8 7 0 PC 3 3 4 Register addressing Function The register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR instruction is executed Illustration 70 User s Manual U15075EJ1VOUMOO CHAPTER 3 CPU ARCHITECTURE 3 4 Operand Address Addressing The following various methods are available to specify the register and memory addressing which undergo manipulation during instruction execution 3 4 1 Direct addressing Function The memory indicated with immediate data in an instruction word is directly addressed Operand format addr16 Label or 16 bit immediate data Description example MOV A When setting addr16 to Instruction code 0 0 1 0 1 0 0 1 OP code 0 0 0 0 0 0 1 1 1 1 1 1 1 0 FEH Illustration OP code addr16 Lower addr16 Higher Memory User s Manual U15075EJ1VO0UMOO 71 CHAPTER 3 CPU ARCHITECTURE 3 4 2 Short direct addressing Function The memory to be manipulated in the fixed space is directly addressed with 8 bit data in an instruction word The fixed space is the 256 byte space FE20H to FF1FH where the addressing is applied Internal high speed RA
20. messem wao razna mensem mensem emen __ umm i eenn Turas o femnes msecemo i ezn fcl 2 610 Hz 211 38 Hz fcl 2 19 Hz fcl 211 16 Hz og E ez fcl 21 305 Hz 212 19 Hz fel 2 2 10 Hz fel 2 2 8 Hz fcl 213 153 Hz fcl 213 10 Hz fcl 213 5 Hz fcl 213 4 Hz BZOE90 Buzzer port output control Disables buzzer port output Enables buzzer port output Note Bits 4 to 7 must be set to O Caution If the subclock is selected as the count clock TCL901 1 TCL900 1 see Figure 6 2 Format of 16 Bit Timer Mode Control Register 90 the subclock is not synchronized when buzzer port output is enabled In this case the capture function and TM90 read function are disabled In addition the count value of TM90 is undefined Remarks 1 fx Main system clock oscillation frequency 2 fxt Subsystem clock oscillation frequency 3 The parenthesized values apply to operation at fx 5 0 MHz or fxt 32 768 kHz User s Manual U15075EJ1V0UMOO 121 CHAPTER 6 16 BIT TIMER 3 Port mode register 2 PM2 2 is used to set each bit of port 3 to input or output When pin P26 ITO90 is used for timer output reset the output latch of P26 and PM26 to 0 when pin 21 82090 is used for buzzer output reset the output latch of P26 and PM26 to 0 2 is set with a 1 bit or 8 bit memory manipulation instruction RESE
21. 3 Figure 3 11 Data Memory Addressing uPD789446 789456 FFFFH Special function registers SFRs SFR add 256 8 bits du 247 4 FF1FH FFOOH FEFFH Internal high speed RAM ee 512 x 8 bits 9 FE20FL fe anus a uka weet Salt a 2 2 1 FE1FH FD00H FCFFH Reserved FA0FH FA0EH LCD display RAM 15 x 4 bits FA00H F9FFH Reserved 4000H 3FFFH Internal ROM 16384 x 8 bits 0000H Direct addressing Register indirect addressing Based addressing User s Manual U15075EJ1V0UM00 59 CHAPTER 3 CPU ARCHITECTURE Figure 3 12 Data Memory Addressing uPD78F9456 FFFFH Special function registers SFRs SFR add 256 x 8 bits A FF1FH 4 FFOOH FEFFH h Internal high speed RAM d 512 x 8 bits 9 FE20H Direct addressing Register indirect Reseved addressing FAOEH Based addressing LCD display RAM 15 x 4 bits F9FFH Reserved 4000H 3FFFH Flash memory 16384 x 8 bits 0000H Y User s Manual U15075EJ1VOUMOO CHAPTER 3 CPU ARCHITECTURE 3 2 Processor Registers The uPD789426 789436 789446 and 789456 Subseries provide the following on chip processor registers 3 2 1 Control registers The control registers contain special functions to control the program sequence statuses and stac
22. 174 9 1 Watchdog Timer Runaway Detector nennen nennen 177 9 2 Interval Times u otto detect ede as 177 9 3 Configuration of Watchdog 1 1 T tenter entres internen 178 9 4 Watchdog Timer Runaway Detection 181 9 5 Interval Time of Interval u u u e rccte tte erp e e e epe cedo rea a 182 10 1 Configuration of 8 Bit A D Converter 183 11 1 Configuration of 10 Bit A D en master 197 22 User s Manual U15075EJ1VOUMO0 LIST TABLES 2 2 Table Title Page 12 1 Configuration of Serial Interface 20 enne nennen entere enn nnns 211 12 2 Serial Interface 20 Operating Mode Settings nennen nen 217 12 3 Example of Relationships Between System Clock and Baud 220 12 4 Relationship Between 20 Pin Input Frequency and Baud Rate When BRGC20 Is Set to 8 221 12 5 Example of Relationships Between System Clock and Baud 229 12 6 Relationship Between ASCK20 Pin Input Frequency and Baud Rate When BRGC20 Is Set to 80 230 12 7 Receive Error Causes x pie EI e redes e PE e
23. WDTIF flag is R W enabled only when a watchdog timer is used as an interval timer If the watchdog timer mode 1 or 2 is used set the WDTIF flag to O 3 Because port 3 has an alternate function as the external interrupt input when the output level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore the interrupt mask flag should be set to 1 before using the output mode User s Manual U15075EJ1V0UMO0 267 CHAPTER 14 INTERRUPT FUNCTIONS 2 Interrupt mask flag registers 0 1 and MK1 The interrupt mask flag is used to enable disable the corresponding maskable interrupt service and are set with 1 bit or 8 bit memory manipulation instruction RESET input sets and MK1 to Figure 14 3 Format of Interrupt Mask Flag Registers Symbol 7 6 b 4 9 lt gt lt gt 0 Address After reset R W MKO STMKa 1 2 2 1 PMKO WDTMK FFE4H FFH R W lt gt lt 7 lt 6 gt b 4 lt gt lt 2 gt 0 gt 1 uo WTMK ADMKO TMMK40 TMMK30 TMMK20 WTIMK 5 R W XXMK Interrupt servicing control MK1 Interrupt servicing enabled Interrupt servicing disabled Cautions 1 Bits 7 of MK1 and bit 6 of must be set to 1 2 If the WDTMK flag is read when the watchdog timer is used in watchdog timer mode 1 or 2 its value becomes undefined 3 Because port 3 ha
24. pe 80 4 22 em nca tte ee pa pis 81 4 22 82 42 9 eet suds B ERR LUPO RE be EE RD MERE 83 LA MEM c E 89 42 5 oe oL Rod eis ced eet 91 4 2 6 esed eed ECHO ne d E DU ED ER ii peer PE as 92 4 27 mahala sayasqas bau uhu amp asha h hunu ua 93 4 2 8 Port 8 uPD789426 789436 Subseries only sse eene eene 94 4 2 9 Port 9 0789426 789436 Subseries only sse 95 4 3 Registers Controlling Port Function J J J J J J 96 4 4 Port Function Operation I 102 4 4 1 Writing to DOTT uia entere eee te Deep E UR e RO 102 4 4 2 gt Reading from DOFE nte rere eerte 102 4 4 3 Arithmetic operation of I O port nennen nennen nennen nnns enne 102 CHAPTER 5 CLOCK 22 4 103 51 Clock Generator Functions 103 5 2 Clock Generator Configuration 103 5 3 Registers Controlling Clock Generator esses
25. 99S 910N jeuJelu 5 ee 01 2 3 0619 9 ayoytoyeroueb 024150 8784 OZISOLNI OZHSLNI indui yoojo 020948 JojeJeueb eje pneg oz 1 1 101 U09 jndino yoo 1 00258 02531 z0cSd L 0cSd L peioejep uondeoeu 02050 __ 93249 0231659 00495 6d 0239S uono l q uonoeiep uelis 519012 014999 pue UOISSIUJSUEI p jqeu Jejunoo OZ LS LNI __ 1 oseud 10854 00254 010 0016 Jejunoo UoISSIUISUEJ dois uonippe dois uone4edo lt 2 0255 4 143 UOISSIUISUEJ 025 1 02 IUS UOISSIUISUIJ oz isoz1o 00 5 1025 0c3Xu 029 1 0214167 02 19181691 2119 snouoJuou sv 1541 jo 025 02 15161 uius 1 1516 od 0205 02
26. 5 6 Disable operation of 8 bit timer counter 50 50 and 8 bit timer counter 60 TM60 0 TCE60 0 Disable timer output of TO60 TOE60 0 Set the count clock for timer 60 see Tables 7 5 and 7 6 Set the operation mode of timer 50 and 8 bit timer 60 to 16 bit timer counter mode see Figures 7 4 and 7 5 Set a count value in CR50 and CR60 Enable the operation of TM50 and TM60 TCE60 1 Note Start and clear of the timer in the 16 bit timer counter mode are controlled by TCE60 the value of TCE50 is invalid When the count values of TM50 and TM60 match the values set in CR50 and CR60 respectively both TM50 and 60 are simultaneously cleared to 00H and counting continues At the same time an interrupt request signal 60 is generated INTTM50 is not generated Table 7 7 shows interval time and Figure 7 16 shows the timing of the interval timer operation Cautions 1 Be sure to stop the timer operation before overwriting the count clock with different data 2 In the 16 bit timer counter mode TO50 cannot be used sure to set 50 0 to disable TO50 output User s Manual U15075EJ1V0UMO0 153 7 8 Table 7 7 Interval Time with 16 Bit Resolution During fx 5 0 MHz Operation TCL602 TCL601 TCL600 Minimum Interval Time Maximum Interval Time NEM ENT 1 fx 0 2 us 2 fx 13 1 ms 1 fx 0 2 us ERNEUT 2 fx 0 4 us 2 fx 26 2 ms
27. Other than above Setting prohibited Remarks 1 fx Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency 3 fw Watch timer clock frequency 174 User s Manual U15075EJ1VO0UMOO CHAPTER 8 WATCH TIMER Figure 8 3 Watch Timer Interval Timer Operation Timing 5 bit counter Overflow Overflow _ oy Bobo paq gt pa 0 fw 29 Watch timer interrupt J L_ INTWT Interval timer interrupt 2 gt Watch timer interrupt time 0 5 s Watch timer interrupt time 0 5 s Interval i T timer T Caution When operation of the watch timer and 5 bit counter operation is enabled by setting bit 0 WTM0 of the watch mode timer mode control register WTM to 1 the interval until the first interrupt request INTWT is generated after the register is set does not exactly match the specification made with WTM3 bit 3 of WTM This is because there is a delay of one 9 bit pre scaler output cycle until the 5 bit counter starts counting Subsequently however the INTWT signal is generated at the specified intervals Remarks 1 fw Watch timer clock frequency 2 The parenthesized values apply to operation at fw 32 768 kHz User s Manual U15075EJ1VO0UMOO 175 176 Users Manual U15075EJ1VOUMOO CHAPTER 9 WATCHDOG 9 1 Watchdog Timer Functions The watchdo
28. is left set If it is lower than half of the MSB is reset Bit 8 of SAR is set automatically and comparison shifts to the next stage The next tap voltage of the series resistor string is selected according to bit 9 which reflects the previous comparison result as follows e Bit 9 1 Three quarters of Bit 9 0 One quarter of The tap voltage is compared with the analog input voltage Bit 8 is set or reset according to the result of comparison Analog input voltage gt tap voltage Bit 8 1 e Analog input voltage lt tap voltage Bit 8 0 Comparison is repeated until bit O of SAR is reached When comparison is completed for all of the 10 bits a significant digital result is left SAR This value is sent to and latched in A D conversion result register 0 ADCRO At the same time it is possible to generate an A D conversion end interrupt request INTADO Cautions 1 The first A D conversion value immediately after A D conversion has been started may be 202 undefined 2 In standby mode A D converter operation is stopped User s Manual U15075EJ1VO0UMOO CHAPTER 11 10 A D CONVERTER uPD789436 AND 789456 SUBSERIES Figure 11 4 Basic Operation of 10 Bit A D Converter Conversion time gt Sampling time 4 A D converter operation Sampling A D conversion Conversion SAR Undefined result Conversion result INTADO A D conversio
29. tnmen nnne 277 CHAPTER 15 STANDBY FUNCTION 8 279 15 1 Standby Function and Configuration J u 279 Standby function er a RED UT ume emendi 279 15 1 2 Register controlling standby 280 15 2 Standby Function Operation 281 15 2 1 iae ot u RR a 281 15 2 2 5 u eter etaed ed ti a aqapana u h qala 284 CHAPTER 16 RESET 287 CHAPTER 17 pPD78F9436 78 9456 2222 291 17 1 Flash Memory Programming u u uu uuu u uu u u J 292 17 1 1 Selecting communication mode n aaa 292 17 1 2 Function of flash memory 0 293 17 1 3 connection a entente nnnc 293 17 1 4 Example of settings for Flashpro 295 CHAPTER 18 8 20 dede Or RP dde CORR 297 CHAPTER 19 INSTRUCTION 6 299 TOS A 299 19 1 1 identifier
30. 1 1 RIEN ERES 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 1024 2048 1024 2048 1024 2048 Input voltage AVop 204 User s Manual U15075EJ1VO0UMOO CHAPTER 11 10 A D CONVERTER uPD789436 AND 789456 SUBSERIES 11 4 3 Operation mode of 10 bit A D converter The A D converter is initially in select mode In this mode analog input channel specification register 0 ADSO is used to select an analog input channel from ANIO to ANI5 for A D conversion A D conversion can be started only by software that is by setting A D converter mode register 0 ADMO The A D conversion result is saved to A D conversion result register 0 ADCRO At the same time an interrupt request signal INTADO is generated Software started A D conversion Setting bit 7 ADCSO of A D converter mode register 0 ADMO to 1 triggers A D conversion for a voltage applied to the analog input pin specified in A D input selection register 0 ADSO Upon completion of A D conversion the conversion result is saved to A D conversion result register 0 ADCRO At the same time an interrupt request signal INTADO is generated Once A D conversion is activated and completed another session of A D conversion is started A D conversion is repeated until new data is written to ADMO If data where ADCSO is 1 is written to ADMO again during A D conversion the ongoing session of A D conversion is discontinued and a new session of A D conversion begins for the new d
31. Operation stop mode Asynchronous serial interface UART mode e 3 wire serial mode 12 4 1 Operation stop mode In operation stop mode serial transfer is not executed thereby reducing the power consumption The P23 SCK20 ASCK20 P24 SO20 TxD20 and P25 SI20 RxD20 pins can be used as normal ports 1 Register setting Operation stop mode is set by serial operation mode register 20 CSIM20 and asynchronous serial interface mode register 20 ASIM20 a Serial operation mode register 20 CSIM20 CSIM2O is set with 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM20 to 00H Symbol 7 Address After reset R W 6 5 4 3 2 1 0 CSIM20 CSIE20 SSE20 arrn DAP20 DIR20 csck20 ckP20 FF72H 00H R W CSIE20 Operation control 3 wire serial mode mm Operation disabled Operation enabled Caution Bits 4 and 5 must be set to 0 222 Users Manual U15075EJ1VOUMOO CHAPTER 12 SERIAL INTERFACE 20 b Asynchronous serial interface mode register 20 ASIM20 ASIM20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM20 to 00H Symbol 7 Address After reset R W lt 6 gt 5 4 3 2 1 0 20 Transmit operation control EM Transmit operation stopped Transmit operation enabled RXE20 Receive operation control Receive operation stopped Receive operation enabled Caution Bits 0 and 1 must be set to 0 Users Manual U15075EJ1VOUMOO 223
32. pue 9 768 0 j dde p z s yju ed 05 ENOJ 20409 0400 IMA GOI J0128 es otze Tt Agidsiq 49104 0VAG91 0 19481691 ejdsip GOT 10 93 8S 09097 0 GOT 1 091 JO 71 User s Manual U15075EJ1VOUMOO 248 CHAPTER 13 LCD CONTROLLER DRIVER 13 3 Registers Controlling LCD Controller Driver LCD display mode register 0 LCDMO LCD clock control register 0 LCDCO LCD voltage amplification control register 0 LCDVAO 1 LCD display mode register 0 LCDMO LCDMO specifies whether to enable display operation It also specifies the operation mode LCD drive power supply and display mode LCDMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets LCDMO to 00H User s Manual U15075EJ1V0UMO0 249 CHAPTER 13 LCD CONTROLLER DRIVER Figure 13 2 Format of LCD Display Mode Register 0 Symbol 7 lt Address After reset R W
33. Main system clock fx Subsystem clock fxr CPU clock _ fcpu Clock to peripheral hardware The operation and function of the clock generator is determined by the processor clock control register PCC suboscillation mode register SCKM and subclock control register CSS as follows 112 a The low speed mode 2fceu 1 6 us at 5 0 MHz operation of the main system clock is selected when the RESET signal is generated PCC 02H While a low level is input to the RESET pin oscillation of the main system clock is stopped Three types of CPU clocks fceu 0 2 us and 0 8 us main system clock at 5 0 MHz operation 61 ys subsystem clock at 32 768 kHz operation can be selected by the PCC SCKM and CSS settings Two standby modes STOP and HALT can be used with the main system clock selected In a system where no subsystem clock is used setting bit 1 FRC of the SCKM so that the on chip feedback resistor cannot be used reduces current consumption in STOP mode In a system where a subsystem clock is used setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation CSS bit 4 CSSO can be used to select the subsystem clock so that low current consumption operation is used 122 us at 32 768 kHz operation With the subsystem clock selected it is possible to cause the main system clock to stop oscillating using bit 7 MCC of PCC The HALT mode can be used but the STOP mode cannot The clock pulse for the peri
34. m 89438 0 O User s Manual 0789426 789436 789446 789456 Subseries 8 Bit Single Chip Microcontrollers 789425 789445 789426 789446 789435 789455 789436 789456 uPD78F9436 uPD78F9456 Document No U15075EJ1 VOUMOO 1st edition Date Published November 2000 N CP K NEC Corporation 2000 Printed in Japan 2 User s Manual U15075EJ1VOUMOO NOTES FOR CMOS DEVICES D PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfuncti
35. 1 50 Even number 1 1 1 1 X gt i CR50 2N 50 A 1 1 50 i TO50 166 User s Manual U15075EJ1V0UMO0 7 8 Figure 7 24 Operation Timing PWM Free Running Mode When Both Edges Are Selected 2 2 2 When CR50 Odd number 1 1 1 Count clock 1 1 Overflow Overflow Overflow D 0 I 50 2N 1 1 1 1 1 1 1 I 1 1 1 50 INTTM50 TO50 Caution When both edges selected do not set CR50 to 00H 01H If the 50 is set to these values PWM output may not be performed normally Figure 7 25 Operation Timing in PWM Free Running Mode When Both Edges Are Selected When CR50 Is Overwritten Count clock 1 1 1 1 1 Yorn Noza XY av om en X A Overflow 1 Overflow Overflow 1 1 1 1 50 2N X 2N 1 1 1 1 1 1 1 1 TCE50 1 I 1 Count start 50 TO50 CR50 overwrite User s Manual U15075EJ1V0UM00 167 7 8 7 4 5 Operation PWM output timer 60 In the PWM pulse generator mod
36. 2 1 Alternate function PUBS Pull up resistor option register B3 PM Port mode register RD Port 3 read signal WR Port 3 write signal 90 User s Manual U15075EJ1V0UMO0 CHAPTER 4 PORT FUNCTIONS 4 2 5 Port 5 This is a 4 bit N ch open drain port with an output latch Port 5 can be specified in the input or output mode in 1 bit units by using port mode register 5 PM5 For a mask ROM version use of an on chip pull up resistor can be specified by a mask option This port is set in the input mode when the RESET signal is input Figure 4 13 shows a block diagram of port 5 Figure 4 13 Block Diagram of P50 to P53 RD N t Mask option resistor Mask ROM version only For flash memory version a pull up resistor is not incorporated lt o 50 to P53 WRport 1 Output latch P50 to P53 N ch WRPM TIT PM50 to PM53 exe PM Port mode register RD 5 read signal WR Port 5 write signal User s Manual U15075EJ1VOUMOO 91 CHAPTER 4 PORT FUNCTIONS 4 2 6 Port 6 This is an 8 bit input only port This port is also used as the analog input of an A D converter Figure 4 14 shows a block diagram of Port 6 Figure 4 14 Block Diagram of Port 6 RD A D converter VREF Internal bus P60 ANIO to P65 ANI5 92 User s Manual U15075EJ1
37. PG FP3 Make the following settings when writing to flash memory using Flashpro PG FP3 1 Load the parameter file 2 Select the serial mode and serial clock using the type command 3 An example of settings for the is shown below Table 17 4 Example of Settings for PG FP3 Communication Mode Example of Settings for PG FP3 Number of Ver Pulses CPU CLK On Target Board In Flashpro On Target Board 4 1943 MHz SIO CLK 1 0 MHz In Flashpro SIO CLK Notes 1 The number of VPP pulses supplied from Flashpro Ill when serial communication is initialized pins to be used for communication are determined according to the number of these pulses 2 Select one of 9600 bps 19200 bps 38400 bps or 76800 bps Remark COMM PORT Selection of serial port SIO CLK Selection of serial clock frequency CPU CLK Selection of source of CPU clock to be input User s Manual U15075EJ1V0UMO0 295 296 User s Manual U15075EJ1V0UMO0 18 5 Table 18 1 Selection of Mask Option for Pins P50 to P53 Whether a pull up resistor is to be incorporated can be specified in 1 bit units For P50 to P53 port 5 a mask option is used to specify whether a pull up resistor is to be incorporated The mask option is selectable in 1 bit units Caution Flash memory versions do not have a mask option based on chip pull up resistor function User s Manual U15075EJ1V0UMO0 297
38. 2 1 0 PE20 Parity error flag EM No parity error has occured A parity error has occured when the parity of transmit data does not match FE20 Framing error flag EM No framing error has occured A framing error has occured when stop bit is not detected 1 Overrun error flag No overrun error has occured An overrun error has occuredNete 2 when the next receive operation is completed before data is read from reception buffer register 20 Notes 1 Even when the stop bit length is set to 2 bits by setting bit 2 SL20 of asynchronous serial interface mode register 20 ASIM20 the stop bit detection at reception is performed with 1 bit 2 Be sure to read reception buffer register 20 RXB20 when an overrun error occurs not every time the data is received an overrun error will occur Users Manual U15075EJ1VOUMOO 227 CHAPTER 12 SERIAL INTERFACE 20 d Baud rate generator control register 20 BRGC20 Symbol BRGC2O is set with an 8 bit memory manipulation instruction RESET input sets BRGC20 to 00H 7 Address After reset R W 228 o l o o ea 71 o o ee s o i Jes _ T o c 7 77 _ Te __ jema ___________ o 7 pt External clock input to ASCK20 pinNete Other than above Setting prohibited Note Can only be used in the UART mode Cautions 1 When writing to BRGC20 during a communication ope
39. 32 1 6 2 Block diagram of uPD789446 789456 Subseries sse 33 1 7 Overview of Functions ceder 34 CHAPTER 2 PIN FUNCTIONS cr aee nce Enc EE TRE c CE TA ese 37 2 1 Eist of Pin FUNCTIONS i 37 2 2 Description of Pin Functions J U U u uu uu uuu uuu 40 2 2 1 POOTO ie oie ukawa ai kus 40 2 2 2 iie eret n rere uu uu sum u uu u uses aso 40 2 2 3 P20 to P26 POrt 2 uu eee bier lee creo ee aa ok uwa sss 40 2 2 4 lt ctiain scere SED samasaa 41 2 2 5 P50 to o 41 2 2 6 P65 o ege Le coed hte 41 2 27 P72 7 Sas Q re ERE ERE 42 2 2 8 PST en e e etse ee e EE SD erede 42 2 2 9 P90to POrE9 sc ees te Ee oe tete asal 42 2 25 10 S0 1009 143 iiobis ii tutti cid cest cetus 42 2 21 GOMO oO COMB UL E Ig CUIRE n 42 2 27 12 ids edades tede de oe ie d ede decade eoe decade sued esee edes
40. 6 gt 5 lt 4 gt 3 2 1 0 LCDMO VAONO o uso o FFBOH 00H R W LCDONO LCD display enable disable Display off Display on VAONO LCD controller driver operation modeNete internal voltage amplification Normal operation Internal voltage amplification enabled Low voltage operation LIPSO Segment pin common pin output control bitNete Output ground level to segment common pin Output deselect level to segment pin and LCD waveform to common pin Note When the LCD display panel is not used the VAONO and LIPSO must be set to 0 to reduce power consumption Cautions 1 Bits 1 to 3 and 5 must be set to O 2 When operating follow the procedure described below A To stop voltage amplification after switching display status from on to off 1 Set to display off status by setting LCDONO 0 2 Disable outputs of all the segment buffers and common buffers by setting LIPSO 0 3 Stop voltage amplification by setting VAONO 0 B To stop voltage amplification during display on status Setting prohibited Be sure to stop voltage amplification after setting display off C set display on from voltage amplification stop status 1 Start voltage amplification by setting VAONO 1 then wait for about 500 ms 2 Set all the segment buffers and common buffers to non display output status by setting LIPSO 1 3 Set display on by setting LCDONO 1 250 User s Manual U15075EJ1
41. Capell i E Bit Wate A D A D Subseries Name Small scale uPD789046 tch 1 ch package 89026 4 16 general purpose HPD789074 2 applications uPD789014 2 4 E Small scale soe 16Kto24K 3ch 1ch 8ch 1 ch UART uPD789167 8 16 1ch Er 2Kto8K converter er uPD789104A Inverter 789842 8 16 3ch 1 ch 1ch 8 control Serial Interface 1 ch UART 1 ch P e 1 ch 1 ch UART Na E Remarks E pem On chip EEPROM RC oscillation version _ sev re _ _ 8 LCD drive uPD789488 3 ch 789417 K to uPD789407A eee A 12 K to 2 ch n uPD789446 19 Ig uPD789426 8Kto16K uPD789306 m ELTE drive 60K 1 ch 1 User s Manual U15075EJ1VOUMOO ich 1ch p UART 1 ch 7 eh 1 ch UART 6 ch m 2 ch UART 1 ch 1 ch 2 ch UART 1 ch 2 ch USB 1 Ah oe 4Kto24K 2ch uPD789327 uPD789800 789840 uPD789861 4 Note 10 bit 1 channel 1 ch UART L oscillation 8 V On chip LCD lucos 2 8v 14 1 8 V RC oscillation version on chip EEPROM On chip EEPROM 31 CHAPTER 1 GENERAL 1 6 Block Diagram 1 6 1 Block diag
42. Clear CRnO FFH TCEn0 I l 1 Remark 5 6 50 60 61 Figure 7 11 Timing of Interval Timer Operation with 8 Bit Resolution When 0 Changes from to lt M muno Koo n JO I Clear Clear Clear CRnO N X M TCEnO 1 Count start INTTMnO l 1 1 Interrupt acknowledgement 1 Interrupt acknowledgement 1 1 I 1 0 overwritten Remark 5 6 50 60 61 146 User s Manual U15075EJ1V0UMO0 7 8 Figure 7 12 Timing of Interval Timer Operation with 8 Bit Resolution When 0 Changes from to M N gt LE LILI LEUTE LE LE LT LE LE LE LE LE U I 1 0 CRnO TCEnO 0 overflows because M N INTTMnO 1 Remark 5 6 50 60 61 User s Manual U15075EJ1VOUMOO 147 7 8 Figure 7 13 Timing of Interval Timer Operation with 8 Bit Resolution When Timer 60 Match Signal Is Selected for Timer 50 Count Clock Timer 60 count clock two om Row X Xm I CR60 N X M TCE60 I 1 1 1 1 1 Count start i INTTM60 Input clock to timer 50 timer 60 match signal 1 1 I CR50 Y TCE50
43. Mnemonic Operands Byte Clock Operation Z AC CY s z p G Es saddr CY saddr byte CY poe Aben o s Taere Sid s e e s vcA Mtewm x Us 28 77 E amm a nmm foel o henee _ Am ______ s cass d saddr byte EH saddr lt saddr v byte s T s o o aw e hawo Kea e see ae s E Am a Awam s s aca s ames el e aca e Remark One instruction clock cycle is one CPU clock cycle selected by the processor clock control register PCC User s Manual 015075 303 CHAPTER 19 INSTRUCTION SET Tem ROAD 3 Awam o o ens Ana Dum _______ s meme es s os forea um pre jem saddr lt saddr saddr lt saddr 1 rp lt rp 1 La s s m sw pese eer lt 1 Remark instruction clock cycle is one CPU clock cycle selected by the processor clock control register PCC 304 User s Manual U15075EJ1V0UMO0 CHAPTER 19 INSTRUCTION SET Mnemonic Operands Byte Clock Operation
44. When a match occurs between TM60 and CRH60 When the 60 count value overflows User s Manual U15075EJ1VO0UMOO 137 7 8 7 3 Registers Controlling 8 Bit Timer The 8 bit timer is controlled by the following four registers 8 bit timer mode control register 50 TMC50 8 bit timer mode control register 60 TMC60 e Carrier generator output control register 60 60 Port mode register 3 PM3 1 8 bit timer mode control register 50 TMC50 8 bit timer mode control register 50 TMC50 is used to control the timer 50 count clock setting and the operation mode setting TMC50 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC50 to 00H 138 User s Manual U15075EJ1V0UMO0 7 8 Figure 7 4 Format of 8 Bit Timer Mode Control Register 50 Symbol lt 7 gt lt lt 0 gt Address After reset R W 6 gt 5 4 3 2 1 TMC50 TCE50 TEG50 TCL502 TCL501 TCL500 TMD501 TMD500 TOE50 FF4DH 00H R W TCE50 Control of TM50 count operation Clears 50 count value and stops operation Starts count operation TEG50 Valid edge selection for TM50 count clock a Counts at the rising edge of the count clock Counts at both edges of the count clock s o eme SCS Timer 60 match signal Timer 50 PWM free running mode Timer 60 PWM pulse generator mode Setting prohibited ontrol of timer output Output disa
45. dua dte da 287 16 2 Reset Timing by RESET Input Rue Ecl A LM e 288 16 3 Reset Timing by Overflow in Watchdog Timer 288 16 4 Reset Timing by RESET Input in STOP tte 288 17 1 Communication Mode Selection 292 17 2 Flashpro Connection Example in 3 Wire Serial Mode 293 17 3 Flashpro Connection Example in UART nennen nnne nnne nennen ens 294 A 1 Development Tools tob th Ea o DECORE E REOR E 310 User s Manual U15075EJ1VOUMOO 21 LIST OF TABLES 1 2 Table No Title Page 2 1 Types of Pin Input Outp t CircUits 44 3 1 Internal ROM Gabpacily 53 3 2 Vector Table ass 53 3 3 LGD Display RAM Capacity uuu s s eaten el eb 54 3 4 Special Function Hegister s oiii cet ip e Pere Ra dee E ede 66 4 1 Port Functions inane pti A aliua pete 79 4 2 Cconfig ratior of xz ei e C en ee EGER RO EAE rp eec aite c LESE E a Fea 80 4 3 Port Mode Register and Output Latch Settings When Using Alternate Functions 98
46. 1 Vector table area The 34 byte area of addresses 0000H to 0021H is reserved as a vector table area This area stores program start addresses to be used when branching by the RESET input or an interrupt request generation Of a 16 bit program address the lower 8 bits are stored in an even address and the higher 8 bits are stored in an odd address Table 3 2 Vector Table 2 CALLT instruction table area The subroutine entry address of a 1 byte call instruction CALLT can be stored in the 64 byte area of addresses 0040H to 007FH User s Manual U15075EJ1VOUMOO 53 3 3 1 2 Internal data memory internal high speed RAM space The uPD789426 789436 789446 and 789456 Subseries products incorporate the following RAM 1 Internal high speed RAM Internal high speed RAM is incorporated in the area between FDOOH and FEFFH The internal high speed RAM is also used as a stack 2 LCD display RAM LCD display RAM is incorporated The LCD display RAM can also be used as ordinary RAM Each subseries incorporates LCD display RAM with the following capacity Table 3 3 LCD Display RAM Capacity 789426 789436 Subseries to 4 789446 789456 Subseries to 15 x 4 bits 3 1 3 Special function register SFR area Special function registers SFRs of on chip peripheral hardware are allocated in the area between FFOOH to FFFFH se
47. 2 fx 0 4 us erae wenoo o o o soos Ls oem ene Remark fx Main system clock oscillation frequency 154 User s Manual U15075EJ1V0UM00 7 8 H44 0 H00 N 01 HOO X 1X 1 N X9SZ eun xeuieg euin la 1901 10 0901 yoyew jou esneoeq pereJeueb jou 1dnu lul O9WLINI 1816 OSWL 09391 0949 Ajsnosueynuls yew 09 pue osL vi junoo 09 11 1lunoo 1 1 1 1 1 1 1 1 1 I 1 D 1 1 1 18 91 jo 791 7 4 155 User s Manual U15075EJ1VOUMOO 7 8 2 Operation as external event counter with 16 bit resolution The external event counter counts the number of external clock pulses input to the TMI60 P31 INTP1 TO50 pin by TM50 and 60 To operate as an external event counter with 16 bit resolution settings must be made in the following 156 sequence 1 Disable operation of 50 and TM60
48. 3 x don t care User s Manual U15075EJ1VO0UMOO 113 5 5 6 2 Switching between system clock and CPU clock The following figure illustrates how the CPU clock and system clock switch Figure 5 8 Switching Between System Clock and CPU Clock RESET Interrupt request signal 1 2 lt 3 gt lt 4 gt 114 System clock fx fx fxr fx CPU clock Low speed High speed Subsystem clock High speed operation operation operation operation Wait 6 55 ms at 5 0 MHz operation Internal reset operation The CPU is reset when the RESET pin is made low on power application The effect of resetting is released when the RESET pin is later made high and the main system clock starts oscillating At this time the oscillation stabilization time 2 is automatically secured After that the CPU starts instruction execution at the slow speed of the main system clock 1 6 us at 5 0 MHz operation After the time required for the voltage to rise to the level at which the CPU can operate at high speed has elapsed bit 1 PCC1 of the processor clock control register PCC and bit 4 CSSO of the subclock control register CSS are rewritten so that high speed operation can be selected A drop of the voltage is detected with an interrupt request signal The clock is switched to the subsystem clock at this moment the subsystem clock must be in the oscillation stabilizati
49. 60 are cleared to 00H and counting continues At the same time an interrupt request signal INTTM60 is generated 50 is not generated The square wave output is cleared to 0 by setting TCE60 to 0 Table 7 8 shows the square wave output range and Figure 7 18 shows timing of square wave output Cautions 1 Be sure to stop the timer operation before overwriting the count clock with different data 2 In the 16 bit timer counter mode TO50 cannot be used Be sure to set 50 0 to disable TO50 output Remark Items in parentheses for when the TO61 pin is selected for timer output Table 7 8 Square Wave Output Range with 16 Bit Resolution During fx 5 0 MHz Operation TCL602 TCL601 TCL600 Minimum Pulse Width Maximum Pulse Width a E WU 1 fx 0 2 us 2 f lt 13 1 ms 1 fx 0 2 o o 1 2 fx 0 4 us 2 tx 26 2 ms 2 fx 0 4 us EARRA fmi input cycle input cycle x 2 input cycle ug mmc co fw input cycle frw 2 input cycle x 2 frw 2 input cycle com frw 2 input cycle frw 2 input cycle x 2 frw 2 input cycle frw 2 input cycle frw 2 input cycle x 2 frw 2 input cycle 158 Remark fx Main system clock oscillation frequency User s Manual U15075EJ1VOUMOO 7 8 H44 0 HOO N HAS 0 jndino SI 901 10 0901 JO AON
50. CHAPTER 12 SERIAL INTERFACE 20 12 4 2 Asynchronous serial interface UART mode In this mode the one byte data following the start bit is transmitted received enabling full duplex communication This device incorporates UART dedicated baud rate generator that enables communications at the desired baud rate In addition the baud rate can also be defined by dividing the clock input to the ASCK20 pin The UART dedicated baud rate generator also can output the 31 25 kbps baud rate that complies with the MIDI standard 1 Register setting UART mode is set by serial operation mode register 20 CSIM20 asynchronous serial interface mode register 20 ASIM20 asynchronous serial interface status register 20 ASIS20 and baud rate generator control register 20 BRGC20 224 User s Manual U15075EJ1VO0UMOO CHAPTER 12 SERIAL INTERFACE 20 a Serial operation mode register 20 CSIM20 CSIM2O is set with 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM20 to 00H Set CSIM20 to 00H when UART mode is selected Symbol 7 6 Address After reset R W 5 4 3 2 1 0 CSIM20 DAP20 DIR20 8 20 ckP20 FF72H 00H R W CSIE20 3 wire serial I O mode operation control Operation disabled Operation enabled SSE20 5520 pin selection Function of SS20 P22 pin Communication status 1 Used PF 0 SES Communication enabled Communication disabled DAP20 3 wire serial mode data phase selection EN Outputs at the f
51. Conversely to the even parity the parity bit is determined so that the number of bits with a value of 1 in the transmit data including parity bit may be odd The parity bit value should be as follows The number of bits with a value of 1 is an odd number in transmit data 0 The number of bits with a value of 1 is an even number in transmit data 1 e At reception The number of bits with a value of 1 in the receive data including parity bit is counted and if the number is even a parity error occurs iii 0 parity When transmitting the parity bit is set to O irrespective of the transmit data At reception a parity bit check is not performed Therefore a parity error does not occur irrespective of whether the parity bit is set to O or 1 iv No parity A parity bit is not added to the transmit data At reception data is received assuming that there is no parity bit Since there is no parity bit a parity error does not occur User s Manual U15075EJ1VOUMO0O0 CHAPTER 12 SERIAL INTERFACE 20 c Transmission A transmit operation is started by writing transmit data to transmission shift register 20 TXS20 The start bit parity bit and stop bit s are added automatically When the transmit operation starts the data in TXS20 is shifted out and when TXS20 is empty a transmission completion interrupt INTST20 is generated Figure 12 8 Asynchronous Serial Interface Transmission Completion I
52. Four Time Slot LCD Drive Waveform Examples COMO COM1 2 COM3 52 1 3 52 0 1 1 3 1 52 0 1 3 User s Manual U15075EJ1V0UMO0 261 262 User s Manual U15075EJ1V0UMO0 CHAPTER 14 INTERRUPT FUNCTIONS 14 1 Interrupt Function Types The following two types of interrupt functions are used 1 Non maskable interrupt This interrupt is acknowledged unconditionally It does not undergo interrupt priority control and is given top priority over all other interrupt requests A standby release signal is generated One interrupt source from the watchdog timer is incorporated as a non maskable interrupt 2 Maskable interrupt This interrupt undergoes mask control If two or more interrupts with the same priority are simultaneously generated each interrupt has a predetermined priority as shown in Table 14 1 A standby release signal is generated 5 external and 9 internal interrupt sources are incorporated as maskable interrupts 14 2 Interrupt Sources and Configuration A total of 15 non maskable and maskable interrupts are incorporated as interrupt sources see Table 14 1 User s Manual U15075EJ1V0UMO0 263 CHAPTER 14 INTERRUPT FUN
53. L 05141 Led Ld1NI O9IN L 0S01 05 8 E __ 2 4 8 x OSIALLLNI 7 2 7 en14 09IAL JO 2 19 epeoseo _ X OG 4 Z Z 01 0899 06 1 5 428 100400 09301 0050 1090141 0098121 1108121 209191 06931 09301 OSOWL 08 1 5 4 2 2 06 JO 71 133 User s Manual U15075EJ1VOUMOO 7 8 uonoeuuoo 4 1 wo epeoseo euss yoyew 09 11 ped IguBis 1senbeij 09 g eun amp i4 01 3 L 4 m6 q oL O9IALLLNI 4 4 eJnBi4 ees sjrejiop 104 JON uonoeuuoo ul 08 0 peusis ue s 1 4 01 uonoeuuoo epeoseo O9IALL JO Z v 1 2 01 uonoeuuoo 10je1eue ULY 5 1ndino 09 10 Buunp 0 1 2 d d1NV L9O1 Oy ao rang
54. Notes 1 The specifications of FRO2 FRO1 FR00 must be such that the A D conversion time is at least 14 us 2 These bit combinations must not be used as the A D conversion time will fall below 14 us Cautions 1 Bits 0 to 2 and 6 must be set to O 2 Theresult of conversion performed immediately after setting ADCSO is undefined 3 The conversion result may be undefined after clearing ADCSO Remarks 1 fx Main system clock oscillation frequency 2 The parenthesized values apply to operation at fx 5 0 MHz 186 User s Manual U15075EJ1V0UMOO CHAPTER 10 8 A D CONVERTER uPD789426 AND 789446 SUBSERIES 2 Analog input channel specification register 0 ADSO ADSO specifies the port used to input the analog voltage to be converted to a digital signal ADSO is set with 1 bit or 8 bit memory manipulation instruction RESET input sets ADSO to 00H Figure 10 3 Format of Analog Input Channel Specification Register 0 Symbol 7 Address After reset R W aaae _ a o al d Caution Bits 3 to 7 must be set to 0 User s Manual U15075EJ1V0UMOO 187 CHAPTER 10 8 BIT A D CONVERTER uPD789426 AND 789446 SUBSERIES 10 4 8 Bit A D Converter Operation 10 4 1 Basic operation of 8 bit A D converter 1 2 3 d 5 6 T 8 Select a channel for A D conversion using analog input c
55. Serial interfaces Switchable between 3 wire serial mode and UART mode 1 channel LCD controller driver Segment signal outputs 5 max Segment signal outputs 15 max e Common signal outputs 4 max Common signal outputs 4 max 64 pin plastic TQFP fine pitch 12 x 12 34 User s Manual U15075EJ1VOUMOO CHAPTER 1 GENERAL An outline of the timer is shown below 16 Bit 8 Bit 8 Bit Watch Timer Watchdog 50 60 Timer Operation Interval timer 1 tchannel 1 chame 1 1 channel 1 channel 1 channel 1 channel 1 mede External event 1 channel oe Function Timer Timer outputs r u Capture 1 tiu Interrupt Sources Notes 1 The watch timer can perform both watch timer and interval timer functions at the same time 2 The watchdog timer has the watchdog timer and interval timer functions However use the watchdog timer by selecting either the watchdog timer function or interval timer function User s Manual U15075EJ1VOUMOO 36 User s Manual U15075EJ1VOUMOO 2 2 1 List of Pin Functions 1 Port pins 1 2 to Port 0 4 bit port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register 0 PUO or key return mode register 00 KR
56. User s Manual 1 15075 1 00 00 141 CHAPTER 7 8 TIMER 3 Carrier generator output control register 60 TCA60 This register is used to set the timer output data in carrier generator mode is set with an 8 bit memory manipulation instruction RESET input sets TCA60 to OOH Figure 7 6 Format of Carrier Generator Output Control Register 60 Symbol 7 0 Address After reset R W 6 5 4 3 lt 2 gt lt 1 gt 0 60 60 NRZB60 NRZ60 00H 60 Control of remote control output When NRZB60 1 a carrier pulse is output When NRZB60 0 a low level is output 1 When NRZB60 1 high level signal is output When NRZB60 0 a low level is output NRZB60O This is the bit that stores the next data to be output to NRZ60 When a match signal occurs for a match with timer 50 the data is output to NRZ60 Input the required value to NRZ60 by program beforehand NRZ60 No return zero data Outputs low level signal carrier clock is stopped 1 Outputs carrier pulse Caution TCA60 cannot be set with a 1 bit memory manipulation instruction Be sure to use an 8 bit memory manipulation instruction to set TCA60 4 Port mode register 3 This register is used to set the mode of port 3 in 1 bit units When using the P31 TO50 INTP1 TMI60 pin as a timer output set the PM31 and P31 output latch to 0 When using the P32 TO60 INTP2 as a t
57. Z AC CY CALL laddr16 3 SP 1 lt PC SP 2 lt PC 3 PC lt addr16 SP lt SP 2 CALLT addr5 1 SP 1 lt PC 1 SP 2 lt 1 L 00000000 addr5 1 lt 00000000 addr5 SP lt SP 2 RET i e PO 5 2 1 PCH SP 1 PC lt SP PSW lt SP 2 SP SP 3 NMIS 0 s 2 s mcr _____ Dx os samo s e s 2 s sfr bit addr16 PC 4 jdisp8 if sfr bit 1 PSW bit addr16 PC PC 4 jdisp8 if PSW bit 1 saddr bit addr16 PC lt PC 4 jdisp8 if saddr bit 1 saddr bit addr16 PC lt 4 jdisp8 if saddr bit 0 saddr16 2 6 PC 2 jdisp8 if Z 0 sfr bit addr16 PC PC 4 jdisp8 if sfr bit 0 A bit addr16 PC lt 3 jdisp8 if A bit 0 PSW bit addr16 10 PC lt PC 4 jdisp8 if PSW bit 0 A bit addr16 PC 3 jdisp8 if A bit 1 B addr16 lt B 1 then PC lt 2 jdisp8 if B z 0 C addr16 2 C 1 then PC PC 2 jdisp8 if C 0 saddr addr16 3 saddr lt saddr 1 then PC c 3 jdisp8 if 0 AS sp si IE lt 1 Enable interrupt lm s s comosa Dr se Remark One instruction clock cycle is one CPU clock cycle selected by the processor clock control reg
58. and then an operation mode is set The operation status in the STOP mode is shown in the following table Table 15 3 STOP Mode Operating Status 8 bit timer Operation enabled Operation enabled Notes 1 Operation is enabled only when input signal from timer 60 timer 60 operation is enabled is selected as the count clock Operation is enabled when TMI60 is selected as the count clock Operation is enabled while the subsystem clock is selected Operation is enabled only when external clock is selected m RON Maskable interrupt that is not masked 284 User s Manual U15075EJ1V0UMO0 CHAPTER 15 STANDBY FUNCTION 2 Releasing STOP mode The STOP mode can be released by the following two types of sources a Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request In this case if the interrupt is enabled to be acknowledged vectored interrupt processing is performed after the oscillation stabilization time has elapsed If the interrupt is disabled the instruction at the next address is executed Figure 15 4 Releasing STOP Mode by Interrupt Wait STOP set time by OSTS instruction Standby Y release signal fe ee eee Operation Oscillation stabilization Operation mode STOP mode wait status mode Oscillation Clock Oscillation stops Oscillation Remark broken line indicates the case where the interrupt request that has released the stand
59. be set RESET input sets CR90 to FFFFH Cautions 1 CR90 is designed to be manipulated with a 16 bit memory manipulation instruction However it can also be manipulated with an 8 bit memory manipulation instruction When an 8 bit memory manipulation instruction is used to set CR90 it must be accessed by direct addressing 2 To overwrite CR90 during a count operation it is necessary to disable interrupts in advance using interrupt mask flag register 1 MK1 It is also necessary to disable inversion of the timer output data using 16 bit timer mode control register 90 TMC90 If the value in CR90 is rewritten in the interrupt enabled state an interrupt request may occur at the moment of rewrite 2 16 bit timer counter 90 TM90 90 is used to count the number of pulses The contents of TM90 are read with an 8 bit or 16 bit memory manipulation instruction RESET input sets TM90 to 0000H Cautions 1 The count becomes undefined when STOP mode is deselected because the count operation is performed before oscillation stabilizes 2 90 is designed to be manipulated with a 16 bit memory manipulation instruction However it can also be manipulated with an 8 bit memory manipulation instruction When an 8 bit memory instruction is used to manipulate TM90 it must be accessed by direct addressing 3 When an 8 bit memory manipulation instruction is used to manipulate TM90 the lower and higher bytes must be read as a pair in this orde
60. 5 1 Configuration of Clock Generator U ese 103 5 2 Maximum Time Required for Switching CPU 113 6 1 16 Bit Timer Gonfig ration 5 1 reiecit rre 116 6 2 Interval Time of 16 Bit Timer oer eere HR edan 123 6 3 Settings of Capture Edge EEE e eS Re Pe e cx ene 126 6 4 B zzer Frequency ot 16 Brt liimel oe ite edet em ae ena tel i 128 7 1 131 7 2 8 Bit Timer ConfigUEaltiOn s csset eio recette pert feo ad tese ter iode EI de een Qa 132 7 3 Interval Time of 50 e RU mei ete elie ete 144 7 4 Interval Time of Timer GO eee quenter iue robin be 144 7 5 Square Wave Output Range of Timer 50 During fx 5 0 MHz Operation 151 7 6 Square Wave Output Range of Timer 60 During fx 5 0 MHz Operation 152 7 7 Interval Time with 16 Bit Resolution During fx 5 0 MHz 154 7 8 Square Wave Output Range with 16 Bit Resolution During fx 5 0 MHz 158 8 1 Interval Generated Using the Interval Timer a 172 8 2 Watch Timer Config ration iieri tcr 172 8 3 Interval Time of Interval
61. 5520 pin selection Function of SS20 P22 pin Communication status 1 Used a Communication enabled Communication disabled DAP20 3 wire serial mode data phase selection EN Outputs at the falling edge of SCK20 Outputs at the rising edge of SCK20 DIR20 First bit specification CSCK20 3 wire serial mode clock selection EN External clock input to the SCK20 pin Output of the dedicated baud rate generator CKP20 3 wire serial I O mode clock phase selection Clock is low active and 5 20 is at high level in the idle state Clock is high active and SCK20 is at low level in the idle state Caution Bits 4 and 5 must be set to 0 Users Manual U15075EJ1VOUMOO 237 CHAPTER 12 SERIAL INTERFACE 20 b Asynchronous serial interface mode register 20 ASIM20 ASIM20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM20 to 00H When 3 wire serial mode is selected ASIM20 must be set to 00H lt 7 gt Address X After reset R W 238 TXE20 Transmit operation control Transmit operation stopped Transmit operation enabled RXE20 Receive operation control n Receive operation stopped Receive operation enabled PS201 PS200 Parity bit specification 1 Always add 0 parity at transmission Parity check is not performed at reception No parity error occurs CL20 Transmit data character length specification Cautions 1 Bits 0 and 1 must be set to O
62. Alphabetic Order of Register Symbol A ADCRO ADMO ADSO ASIM20 ASIS20 B BRGC20 BZC90 50 CR60 CR90 CRH60 CSIM20 CSS 1 IFO IF1 INTMO INTM1 K KRMOO L LCDCO LCDMO LCDVAO M MK0 MK1 O OSTS P P0 P1 P2 P3 A D conversion result register 0 nnne nter seien nene 184 198 A D converter mode register 0 186 200 Analog input channel specification register 0 187 201 Asynchronous serial interface mode register 20 216 223 226 238 Asynchronous serial interface status register 20 218 227 Baud rate generator control register 20 0004000 219 228 239 Buzzer output control register 90 een rte neri triti ha t EE ER RR ca 121 amp bit compare register 50 ii eere UP pt o i pe E RE e 135 8 register 60 eee Tuer neenon ene ua De TRI Re LEER ene Dre 135 16 bit compare register 90 2 co epi e eene e re OE 118 8 bit compare register H60 og ee Ead 135 Serial operation mode register 20 215 222 225 237 Subclock control t giSter EP PREGA PER EATER RE 107 Interrupt request flag register 0 0 0
63. Blank Unchanged 0 Cleared to 0 1 Set to 1 x Set cleared according to the result R Previously saved value is restored 300 User s Manual U15075EJ1V0UM00 CHAPTER 19 INSTRUCTION SET 19 2 Operation List Mnemonic Operands Byte Clock Operation Z AC CY umm ps os pem Pam a s eme mme s C mp ee EL a re LL Dem a heme uma C j j 2 emen Dem a ten LE a j j ae Awam s s s s emsa pre mem pet A HL byte Notes 1 Exceptr A 2 Exceptr X Remark instruction clock cycle is one CPU clock cycle selected by the processor clock control register PCC User s Manual U15075EJ1V0UMO0 301 CHAPTER 19 INSTRUCTION SET Mnemonic Operands Byte Operation Z AC CY saddr CY byte x CY A r A saddr A CY lt saddr Ix x x A laddr16 A CY lt addr16 Ix x x rr A CY A saddr CY A CY A HL byte CY A byte A CY lt A byte 9 s e Note Only when rp BC DE or HL x x x x x x x x x x x x x x x x x x x x x x x saddr byte Remark One instruction clock cycle is one CPU clock cycle selected by the processor clock control register PCC 302 User s Manual U15075EJ1V0UMO0 CHAPTER 19 INSTRUCTION SET
64. CHAPTER 12 SERIAL INTERFACE 20 Table 12 2 Serial Interface 20 Operating Mode Settings PM24 P24 PM23 First Shift P25 SI20 P24 SO20 P23 SCK20 Bit Clock RxD20 Pin TxD20 Pin ASCK20 Pin Function Function Function x x x 1 Operation stop mode ASIM20 CSIM20 TXE20 RXE20 CSIE20 DIR20 CSCK20 Note 1 x Other than above Setting prohibited 2 3 serial mode P25 SI20 P24 SO20 P23 SCK20 RxD20 Pin TxD20 Pin ASCK20 Pin Function Function Function ASIM20 CSIM20 20 20 CSIE20 DIR20 CSCK20 5120 5020 5 20 CMOS output input Other than above Setting prohibited 3 Asynchronous serial interface mode P24 SO20 P23 SCK20 TxD20 Pin ASCK20 Pin P25 SI20 RxD20 Pin ASIM20 CSIM20 20 20 CSIE20 DIR20 CSCK20 Function Function TxD20 CMOS output Function ASCK20 input ASCK20 input CMOS output TxD20 ASCK20 input Notes 1 These pins can be used for port functions Other than above Setting prohibited 2 When only transmission is used this pin be used P25 CMOS Remark don t care User s Manual U15075EJ1VO0UMOO 217 218 CHAPTER 12 SERIAL INTERFACE 20 3 Asynchronous serial i
65. COMO to COM3 lt Vico to CAPH CAPL LCD controller driver ROM flash memory 78K 0S CPU core Vss IC RESET 1 System control X2 XT1 XT2 INTPO P30 INTP1 P31 INTP2 P32 C Interrupt control P INTP3 P33 KRO POO to KR3 P03 VPP Remarks 1 The internal ROM capacity varies depending on the product 2 The parenthesized values apply to the 78 9456 User s Manual U15075EJ1VOUMOO 33 CHAPTER 1 GENERAL 1 7 Overview of Functions 0789425 uPD789426 uPD78F9436 uPD789445 uPD789446 78 9456 789435 789436 789455 789456 Internal memory Mask ROM Mask ROM Flash Flash memory memory 12 KB 16 KB 12 KB 16 KB High speed RAM 512 bytes Minimum instruction execution time 0 4 us 1 6 us 5 0 MHz operation with main system clock 122 us 32 768 kHz operation with subsystem clock General purpose registers 8 bits x 8 registers Instruction set 16 bit operations Bit manipulations such as set reset and test ports Total Total CMOS I O CMOS I O CMOS input CMOS input N ch open drain N ch open drain Timers 16 bit timer 1 channel 8 bit timer 2 channels Watch timer 1 channel Watchdog timer 1 channel A D converter 8 bit resolution x 6 channels uPD789426 789446 Subseries 10 bit resolution x 6 channels uPD789436 789456 Subseries
66. CRnO Set the operation mode of timer nO to 8 bit timer counter mode see Figures 7 4 and 7 5 Set the count clock for timer see Tables 7 3 to 7 6 Enable the operation of TMnO TCEnO 1 When the count value of 8 bit timer counter TMnO matches the value set in 0 is cleared to and continues counting At the same time an interrupt request signal 0 is generated Tables 7 3 to 7 6 show interval time and Figures 7 8 to 7 13 show the timing of the interval timer operation Caution Be sure to stop the timer operation before overwriting the count clock with different data Remark 5 6 User s Manual U15075EJ1VO0UMOO 143 7 8 Table 7 3 Interval Time of Timer 50 ___ 30 59 30 5 us 2 27 781msy 7 81 ms 1a 3059 30 5 us Input cycle of timer 60 match Input cycle of timer 60 match Input cycle of timer 60 match signal signal x 8 signal pape Input cycle of timer 60 output Input cycle of timer 60 output Input cycle of timer 60 x8 Remarks 1 fx Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency Table 7 4 Interval Time of Timer 60 TCL602 TCL601 TCL600 Minimum Interval Time Maximum Interval Time EUN WEN 1 fx 0 2 us 2 fx 51 2 us 1 fx 0 2 us BEEN 2 fx 0 4 us 2 fx 1 02 us 2 fx 0 4 us namaos o
67. Diagram of 16 Bit RE ad E HR CURE e eate b os 117 6 2 Format of 16 Bit Timer Mode Control Register 90 nennen nmn 120 6 3 Format of Buzzer Output Control Register 90 121 6 4 Forimat ot Port Mode Register aee D ERE UR t ahay eue de 122 6 5 Settings of 16 Bit Timer Mode Control Register 90 for Timer Interrupt Operation 123 6 6 Timing of Timer Interrupt Operation ennemi nnne nnne nnns 124 6 7 Settings of 16 Bit Timer Mode Control Register 90 for Timer Output Operation 125 6 8 Timer s srw etd as tpe ehe Sa ta hee 125 6 9 Settings of 16 Bit Timer Mode Control Register 90 for Capture Operation 126 6 10 Capture Operation Timing Both Edges of CPT90 Pin Are Specified 126 6 11 16 Bit Timer Counter 90 Readout Timing U nennen minns nennen 127 6 12 Settings of Buzzer Output Control Register 90 for Buzzer Output 128 7 1 Block Diagram OA Timer 50 ub 133 7 2 Block Diagram of Timer 60 iecit tete bene Led ag aa erectas exe cese guten dune ca 134 7 8 Block Diagram of Output Controller Timer 60 nennen nnns
68. Name encounter problems in the documentation Please complete this form whenever Company you d like to report errors or suggest improvements to us Tel FAX Address Thank you for your kind support North America Hong Kong Philippines Oceania Asian Nations except Philippines NEC Electronics Inc NEC Electronics Hong Kong Ltd NEC Electronics Singapore Pte Ltd Corporate Communications Dept Fax 852 2886 9022 9044 Fax 465 250 3583 Fax 1 800 729 9288 1 408 588 6130 Korea Japan NEC Electronics Hong Kong Ltd NEC Semiconductor Technical Hotline ctl Branch Fax 044 435 9608 Fax 02 528 4411 Europe Technical Documentation Dept Fax 49 211 6503 274 South America Taiwan NEC do Brasil S A NEC Electronics Taiwan Ltd Fax 455 11 6462 6829 Fax 02 2719 5951 would like to report the following error make the following suggestion Document title Document number Page number If possible please fax the referenced page or drawing Document Rating Excellent Acceptable Clarity m Technical Accuracy Organization
69. acies 235 13 1 Number of Segment Outputs and Maximum Number of 247 13 2 Configuration of LCD Controller Driver essen eren nennen 247 13 3 Frame Frequencies Hz 3n einn aot aei iab pee nig 251 13 4 Signals C 254 13 5 LCD Drive Voltage die deiode ue dis sd Riedel ee ep Anat tee 254 13 6 Select and Deselect Voltages COMO to COMO enter nnne en 256 13 7 Select and Deselect Voltages COMO to COM9 S 259 14 1 Interrupt Source ice ee cere et e dee c EC dep 264 14 2 Flags Corresponding to Interrupt Request Signal 266 14 3 Time from Generation of Maskable Interrupt Request to 274 15 1 HAL T Mode Operating Status d o per ee tete ette oae cedit te io ee 281 15 2 Operation After Releasing HALT Mode 283 15 3 STOP Mode Operating Piel 284 15 4 Operation After Releasing STOP Mode 000000600 a 286 16 1 Hardware Status After Reset arc certe reduce tee for atin do ade 289 17 1 Differences Between uPD78F9436 78F9456 and Mask ROM 291 17 2 Communication ss ua
70. addressing mode memory is manipulated according to the contents of a register pair specified as an operand The register pair to be accessed is specified by the register pair specification code in an instruction code This addressing can be carried out for all the memory spaces Operand format HU Description example MOV A DE When selecting register pair DE Instruction code 0 0 1 0 1 0 1 1 Illustration Memory address specified with Addressed memory register pair DE contents are transferred 7 0 C User s Manual U15075EJ1V0UM00 75 3 3 4 6 Based addressing Function 8 bit immediate data is added to the contents of the base register that is the HL register pair and the sum is used to address the memory Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Description example MOV A HL 10 When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 3 4 7 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and return instructions are executed or the register is saved restored upon generation of an interrupt request Only the intern
71. amplification level during the voltage amplifier operation Figure 13 4 Format of LCD Voltage Amplification Control Register 0 Symbol 7 6 5 4 3 2 1 lt 0 gt Address After reset R W LCDVAO fo o o o o foan FFB3H 00H R W Reference voltage Vicz level selection e e 1 5 times specification of the LCD panel used is 4 5 V 1 0 times specification of the LCD panel used is 3 V Note Select the settings according to the specifications of the LCD panel that is used Caution Before changing the LCDVAO setting be sure to stop voltage amplification VAONO 0 Remark value is indicated as the reference voltage Vica value 252 User s Manual U15075EJ1V0UMO0 CHAPTER 13 LCD CONTROLLER DRIVER 13 4 Setting LCD Controller Driver Set the LCD controller driver using the following procedure 1 Setthe frame frequency using LCD clock control register 0 LCDCO 2 Setthe voltage amplification level using LCD voltage amplification control register 0 LCDVAO GAIN 0 Vico 4 5 V Vici 3 V Vice 1 5 V GAIN 1 Vico 3 V 2 V 1 V 3 Set the time division using LCDMOO bit 0 of LCD display mode register 0 LCDMO 4 Enable voltage amplification by setting VAONO bit 6 of LCDM0 VAONO 1 5 Wait for 500 ms or more after setting VAONO 6 Set LIPSO bit 4 of 0 LIPSO 1 and output the deselect potential 7 Start output corresponding to each data me
72. chip pull up resistor can be specified by means of pull up resistor option register B9 PUB9 Note uPD789426 789436 Subseries only 4 2 Port Configuration Ports have the following hardware configuration Table 4 2 Configuration of Port Control registers Port mode register PMm m 010 3 5 7 to 9 Pull up resistor option register PUO PUB2 7 to PUB9 Ports 789426 789436 Total 40 CMOS I O 30 CMOS input 6 N ch open drain I O 4 Subseries 789446 789456 Total 30 CMOS I O 20 CMOS input 6 open drain I O 4 Subseries Pull up 789426 789436 Total 34 software control 30 mask option specification 4 resistors Subseries 789446 789456 Total 24 software control 20 mask option specification 4 Subseries 80 User s Manual U15075EJ1V0UMO0 4 2 1 Port 0 CHAPTER 4 PORT FUNCTIONS This is 4 bit I O port with an output latch Port 0 can be specified in the input or output mode in 1 bit units by using the port mode register 0 PMO resistors can be connected in 4 bit units by using pull up resistor option register O PUO Port 0 is set in the input mode when the RESET signal is input Figure 4 3 shows a block diagram of port 0 Internal bus Figure 4 3 Block Diagram of P00 to Dt WRpeuo PUOO RD lt RD WR Selector When the to pins
73. enabled is selected as the count clock Operation is enabled when TMI60 is selected as the count clock Operation is enabled while the main system clock is selected Operation is enabled while the subsystem clock is selected Operation is enabled only when external clock is selected Maskable interrupt that is not masked p G N User s Manual U15075EJ1V0UM00 281 CHAPTER 15 STANDBY FUNCTION 2 Releasing HALT mode The HALT mode can be released by the following three types of sources a Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request In this case if the interrupt is enabled to be acknowledged vectored interrupt processing is performed If the interrupt is disabled the instruction at the next address is executed Figure 15 2 Releasing HALT Mode by Interrupt HALT instruction Standby release signal Operation HALT mode Wait Operation mode Clock Oscillation Remarks 1 The broken line indicates the case where the interrupt request that has released the standby mode is acknowledged 2 The wait time is as follows When vectored interrupt processing is performed 9 to 10 clocks e When vectored interrupt processing is not performed 1 to 2 clocks b Releasing by non maskable interrupt request The HALT mode is released regardless of whether the interrupt is enabled or disabled and vectored interrupt processing is performed 2
74. enhanced A D converter 4PD789104A with enhanced timer 0789146 with enhanced A D converter 4PD789104A with added EEPROM 4PD7891244A with enhanced A D converter RC oscillation version of the 789104 HPD789104A with enhanced A D converter 4PD789026 with added A D converter and multiplier On chip inverter controller and UART Total display outputs 25 converter and on chip voltage booster type LCD 28 x 4 4PD789407A with enhanced A D converter A D converter and resistance division type LCD 28 x 4 4PD789446 with enhanced A D converter converter and on chip voltage booster type LCD 15 x 4 789426 with enhanced A D A D converter and on chip voltage booster type LCD 5 x 4 RC oscillation version of the 789306 On chip voltage booster type LCD 24 x 4 Segment common outputs 96 Segments 40 commons 16 4 PD789488 with added remote control receiver and resistance division type LCD For remote controller with A D converter and on chip voltage booster type LCD For remote controller with SIO and resistance division type LCD For PC keyboard on chip USB HUB function For PC keyboard on chip USB function For keypad on chip POC RC oscillation version of the PD789860 For keyless entry on chip POC and key return circuit User s Manual U15075EJ1VOUMOO CHAPTER 1 GENERAL The major functional differences among the subseries are listed below ROM 8 Bit 10 Bit Bit 16 Bit Watch WDT
75. for 1 cycle immediately after If this waveform poses a problem for the application either 1 stop the timer when overwriting the 50 or 2 overwrite the CR50 with the 50 in a cleared status 2 If the valid edge of the count clock is selected for both edges in the PWM output mode 5 1 do not set 00H 01H and FFH to the 50 If the rising edge is selected 50 0 do not set 00H to CR50 8 bit compare register 60 CR60 This 8 bit register is used to continually compare the value set to CR60 with the count value in 8 bit timer counter 60 TM60 and to generate an interrupt request INTTM60 when a match occurs When connected to TM50 via a cascade connection and used as 16 bit timer event counter the interrupt request INTTM60 occurs only when matches occur simultaneously between CR50 and 50 and between CR60 and TM60 50 does not occur CR60 is set with an 8 bit memory manipulation instruction RESET input makes CR60 undefined 8 bit compare register H60 CRH60 In PWM output mode the high level width of timer output is set by writing a value to CRH60 CRH60 is set with an 8 bit memory manipulation instruction RESET input makes CRH60 undefined User s Manual U15075EJ1V0UMO0 135 7 8 4 8 bit timer counters 50 and 60 TM50 and TM60 These are 8 bit registers that are used to count the count pulse 50 and 60 are read with 8 bit me
76. high speed RAM 512 x 8 bits Reserved LCD display RAM 5x4 bits Reserved memo i 3FFFH Program ry space 0000H Flash memory 16384 x 8 bits 0080 007 CALLT table area 0040H 003FH Program area 0022H 0021H Vector table area 0000H User s Manual U15075EJ1VOUMOO 49 50 Data memor CHAPTER 3 CPU ARCHITECTURE Figure 3 4 Memory Map uPD789445 789455 Y Y memory space 0000H FFFFH Special function registers 256 x 8 bits FEFFH Internal high speed RAM 512 x 8 bits FDOOH FCFFH Reserved FAOFH LCD display RAM 15 x 4 bits y space FA00H F9FFH eserve 3000H 2 Internal ROM 12288 x 8 bits 2FFFH Program area 0080H 007FH CALLT table area 0040H 003FH Program area 0022H 0021H Vector table area 0000H User s Manual U15075EJ1VOUMOO CHAPTER 3 CPU ARCHITECTURE Figure 3 5 Memory Map 789446 789456 FFFFH Special function registers 256 x 8 bits FFOOH FEFFH Internal high speed RAM 512 x 8 bits FDOOH FCFFH Reserved FAOFH LCD display Data 15 x 4 bits memory space 00 F9FFH d eserve 4000H i i 3FFFH Program Internal ROM memory space 16384 x 8 bits 0000H 3FFFH Program area 0080H 007FH CALLT tab
77. in analog input channel specification register 0 ADSO Upon completion of A D conversion the conversion result is saved to A D conversion result register 0 ADCRO At the same time an interrupt request signal INTADO is generated Once A D conversion is activated and completed another session of A D conversion is started A D conversion is repeated until new data is written to ADMO data where ADCSO is 1 is written to ADMO again during A D conversion the ongoing session of A D conversion is discontinued and a new session of A D conversion begins for the new data If data where ADCSO is 0 is written to ADMO again during A D conversion A D conversion is stopped immediately Figure 10 6 Software Started A D Conversion Rewriting ADMO Rewriting ADMO ADCSO 1 ADCSO0 1 ADCS0 0 A D conversion discontinued no conversion result is preserved INTADO Remarks 1 0105 2 0105 So Conversion is User s Manual U15075EJ1V0UMOO 191 CHAPTER 10 8 A D CONVERTER uPD789426 AND 789446 SUBSERIES 10 5 Cautions Related to 8 Bit A D Converter 1 Current consumption in standby mode In standby mode the A D converter stops operation Stopping conversion bit 7 ADCSO of A D converter mode register 0 ADMO 0 can reduce the current consumption Figure 10 7 shows how to reduce the current consumption in standby mode Figure 10 7 How to Reduce Current Consumption in Standby
78. occurrence 3 1 9 watchdog timer mode 1 Generates non maskable interrupt upon overflow occurence watondog timer mode 2 Starts reset operation upon overtiow occurrence Notes 1 Once RUN has been set 1 it cannot be cleared 0 by software Therefore when counting is started it cannot be stopped by any means other than RESET input 2 Once WDTM3 and WDTM4 have been set 1 they cannot be cleared 0 by software 3 The watchdog timer starts operation as an interval timer when RUN is set to 1 Cautions 1 When the watchdog timer is cleared by setting RUN to 1 the actual overflow time is up to 0 8 shorter than the time set by the watchdog timer clock select register WDCS 2 To set watchdog timer mode 1 or 2 set WDTM4 to 1 after confirming TMIF4 bit 0 of the interrupt request flag register 0 IFO is set to 0 When watchdog timer mode 1 2 is selected with TMIF4 set to 1 a non maskable interrupt is generated upon the completion of rewriting WDTM4 User s Manual U15075EJ1VOUMOO0 CHAPTER 9 WATCHDOG 9 4 Watchdog Timer Operation 9 4 1 Operation as watchdog timer The watchdog timer detects a program runaway when bit 4 WDTM4 of the watchdog timer mode register WDTM is set to 1 The count clock runaway detection time interval of the watchdog timer can be selected by bits 0 to 2 WDCSO to WDCS2 of watchdog timer clock select register WDCS By setting bit 7 RUN of WDTM to 1 the wat
79. on the number of VPP pulses shown in Table 17 2 Figure 17 1 Communication Mode Selection Format Vop Vss User s Manual U15075EJ1VOUMOO CHAPTER 17 78 9436 78F9456 17 1 2 Function of flash memory programming By transmitting receiving commands and data in the selected communication mode operations such as writing to the flash memory are performed Table 17 3 shows the major functions of flash memory programming Table 17 3 Functions of Flash Memory Programming Erases all contents of memory Batch blank check Checks erased state of entire memory Write to flash memory based on write start address and number of data written number of bytes Batch verify Compares all contents of memory with input data 17 1 3 Flashpro connection example How the Flashpro is connected to the uPD78F9436 or 78F9456 differs depending on the communication mode 3 wire serial I O UART Figures 17 2 and 17 3 show the connection in the respective modes Figure 17 2 Flashpro Connection Example in 3 Wire Serial I O Mode Flashpro lll HPD78F9436 78F9456 Note n 1 2 User s Manual 015075 293 CHAPTER 17 78 9436 78F9456 Figure 17 3 Flashpro Connection Example UART Mode Flashpro HPD78F9436 78F9456 Note n 1 2 294 User s Manual U15075EJ1V0UMO0 CHAPTER 17 78 9436 78F9456 17 1 4 Example of settings for Flashpro
80. or o tw input cyce Remark Main system clock oscillation frequency Figure 7 15 Timing of Square Wave Output with 8 Bit Resolution TMnO CRnO N 1 1 1 I 1 1 Count start INTTMnO Interrupt acknowledgement 1 Interrupt acknowledgement Interrupt acknowledgement TOnmNete 0 I Note The initial value of TOnm is low level when output is enabled TOEnm 1 Remark n 5 6 nm 50 60 61 152 User s Manual U15075EJ1V0UMO0 7 8 7 4 2 Operation as 16 bit timer counter Timer 50 and timer 60 can be used as a 16 bit timer counter using cascade connection In this case 8 bit timer counter 50 50 is the higher 8 bits and 8 bit timer counter 60 60 is the lower 8 bits 8 bit timer 60 controls reset and clear The following modes can be used for the 16 bit timer counter e Interval timer with 16 bit resolution e External event counter with 16 bit resolution Square wave output with 16 bit resolution 1 Operation as interval timer with 16 bit resolution The interval timer with 16 bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8 bit compare register 50 CR50 and 8 bit compare register 60 CR60 To operate as an interval timer with 16 bit resolution settings must be made in the following sequence 1 2 3 4
81. register in question can be read or written R W Read write R Read only W Write only Bit manipulation unit Indicates the bit units 1 8 16 in which the special function register in question can be manipulated After reset Indicates the status of the special function register when the RESET signal is input User s Manual U15075EJ1VOUMOO 65 CHAPTER 3 CPU ARCHITECTURE Table 3 4 Special Function Register List 1 2 Address Special Function Register SFR Name Symbol R W Bit Manipulation Unit After Reset Pres pr Een fees e Los w sj Pot 9 ew UE 8 bit compare register 60 CREO Che 8 bit compare register 50 8 bit timer counter 60 Pee persa 8 bit timer counter 50 7 Mises Receive buffer register 20 A D conversion result register 0 ADCR0 Y 0000H 16 bit compare register 90 90 m 16 bit timer counter 90 TM90 ymsa oo00H m EX E Ee L INEI T mn Lu P Notes 1 0789426 and 789436 Subseries only 2 Name of SFR dedicated for 16 bit access 3 Only in short direct addressing 16 bit access is possible EN 4 These 16 bit access dedicated registers however 8 bit access is possible When performing 8 bit access access using direct addressing
82. segment signals becomes higher than a specific voltage LCD drive voltage Vico It turns off when the potential difference becomes lower than Vicp Applying DC voltage to the common and segment signals for an LCD panel would deteriorate it To avoid this problem this LCD panel is driven with AC voltage 1 Common signals Each common signal is selected sequentially according to a specified number of time slots at the timing listed in Table 13 4 In the static display mode the same signal is output to COMO to COMG in common In the three time slot mode keep the COMG pin open Table 13 4 COM Signals COMO COM1 COM2 Number of Time Slots 2 Segment signals The segment signals correspond to LCD display data memory Bits 0 1 2 and 3 of each byte are read in synchronization with COMO COM1 2 and respectively If the contents of each bit are 1 it is converted to the select voltage and if 0 it is converted to the deselect voltage The conversion results are output to the segment pins Check with the information given above what combination of the front surface electrodes corresponding to the segment signals and the rear surface electrodes corresponding to the common signals forms display patterns in the LCD display data memory and write the bit data that corresponds to the desired display pattern on a one to one basis Bit 3 of the LCD display data memory is not used for LCD display in the thr
83. the serial clock To obtain the frequency to be set use the following expression When an external clock is used setting BRGC20 is not necessary f Serial clock frequency aa Hz fx Main system clock oscillation frequency n Values in the above table determined by the settings of TPS200 to TPS203 1 lt n lt 8 User s Manual U15075EJ1VOUMO0 239 CHAPTER 12 SERIAL INTERFACE 20 2 Communication operation 3 wire serial mode data transmission reception is performed 8 bit units Data is transmitted received bit by bit in synchronization with the serial clock Transmission shift register TXS20 SIO20 and reception shift register RXS20 shift operations are performed in synchronization with the fall of the serial clock SCK20 Then transmit data is held in the SO20 latch and output from the SO20 pin Also receive data input to the SI20 pin is latched in the reception buffer register RXB20 SIO20 on the rise of SCK20 At the end of an 8 bit transfer the operation of TXS20 SIO20 and RXS20 stops automatically and the interrupt request signal INTCSI20 is generated Figure 12 11 3 Wire Serial I O Mode Timing 1 7 i Master operation timing when DAP20 0 CKP20 0 SSE20 0 SIO20 write 5 20 5020 Note SI20 INTCSI20 240 Note value of the last bit previously output is output User s Manual U15075EJ1VO0UMOO CHAPTER 12 SERIAL INTERFACE 20 Figure 12 11 3 Wire Serial I O Mode Timing
84. to ANI5 of analog inputs A D conversion can only be started by software One of analog inputs ANIO to is selected for A D conversion A D conversion is performed repeatedly with an interrupt request INTADO being issued each time A D conversion is complete 11 2 10 Bit A D Converter Configuration The 10 bit A D converter includes the following hardware Table 11 1 Configuration of 10 Bit A D Converter Analog inputs 6 channels ANIO to ANI5 Registers Successive approximation register SAR A D conversion result register 0 ADCRO Control registers A D converter mode register 0 ADMO Analog input channel specification register 0 ADSO User s Manual U15075EJ1V0UMOO 197 CHAPTER 11 10 A D CONVERTER uPD789436 AND 789456 SUBSERIES Figure 11 1 Block Diagram of 10 Bit A D Converter ANIO P60 61 ANI2 P62 6 ANI3 P63 4 64 G ANI5 P65 0 gt Voltage comparator Sample amp hold circuit 9 ET N Successive approximation register SAR Controller gt INTADO A D conversion result register 0 ADCRO 0502 501 500 Analog input channel A D converter mode specification register 0 ADSO register 0 ADMO Internal bus ADCSO 02 FRO1 FROO 1 Successive approximation register SAR The SAR receives the result of comparing an analog input vol
85. to be changed to backup power the pin must be supplied with the same voltage level as the pin as shown in Figure 11 12 Figure 11 12 Pin Handling Main power Backup supply capacitor 10 pin input impedance A series resistor string of several ten of is connected between the and AVss pins Consequently if the output impedance of the reference voltage supply is high the reference voltage supply will form a parallel connection with the series resistor string creating a large reference voltage differential User s Manual U15075EJ1V0UMOO 209 210 Users Manual U15075EJ1VOUMOO CHAPTER 12 SERIAL INTERFACE 20 12 1 Serial Interface 20 Functions Serial interface 20 has the following three modes Operation stop mode Asynchronous serial interface UART mode e 3 wire serial I O mode 1 2 3 Operation stop mode This mode is used when serial transfer is not performed Power consumption is minimized in this mode Asynchronous serial interface UART mode This mode is used to send and receive the one byte of data that follows a start bit It supports full duplex communication Serial interface 20 contains an UART dedicated baud rate generator enabling communication over a wide range of baud rates It is also possible to define baud rates by dividing the frequency of the clock input to the 20 pin 3 wire serial mode switc
86. x Master operation when DAP20 1 CKP20 1 SSE20 0 SIO20 write SCK20 SO20 5120 INTCSI20 Note The value of the last bit previously output is output xi Slave operation when DAP20 1 CKP20 1 SSE20 0 SIO20 write SCK20 5120 5020 INTCSI20 Note The value of the last bit previously output is output User s Manual U15075EJ1VO0UMOO 245 CHAPTER 12 SERIAL INTERFACE 20 Figure 12 11 3 Wire Serial I O Mode Timing 7 7 xii Slave operation when DAP20 1 CKP20 1 SSE20 1 write 5120 ix INTCSI20 2 sns s edi Notes 1 The value of the last bit previously output is output 2 000 is output until SS20 rises When SS20 is high SO20 is in a high impedance state 3 Transfer start Serial transfer is started by setting transfer data to the transmission shift register 520 51020 when the following two conditions are satisfied e Bit 7 CSIE20 of serial operation mode register 20 CSIM20 1 Internal serial clock is stopped or SCK20 is high after 8 bit serial transfer Caution If CSIE20 is set to 1 after data is written to TXS20 SIO20 transfer does not start Termination of 8 bit transfer stops the serial transfer automatically and generates the interrupt request signal INTCSI20 246 User s Manual U15075EJ1VO0UMOO CHAPTER 13 LCD CONTROLLER DRIVER 13 1 LCD Controller Driver Functions The functions of the LCD controller driver of the
87. 0 O P25 SI20 RxD20 O P30 INTPO CPT90 O P31 INTP1 TO50 TMI60 O P32 INTP2 TO60 O P33 INTP3 TO61 O P26 TO90 N 6 0 A P61 ANI1 O Q 5 IC Vep XT1O OP72 XT2 O OP71 OP70 Vss 81 X10 OP80 X20 OP97 RESET OP96 POO KRO 36 95 P01 KR1 O 35 OP94 P02 KR2 OP93 POS KR3 O 16 33 OP92 T 2858O0r 4o0o0 u xoior O OOO Cautions 1 Connect the IC Internally Connected pin directly to Vss 2 Connect the pin to 3 Connect the AVss pin to Vss Remark The parenthesized values apply to the uPD78F9436 User s Manual U15075EJ1VOUMOO 27 CHAPTER 1 GENERAL 1 4 2 Pin configuration of uPD789446 789456 Subseries Top view 64 pin plastic TQFP fine pitch 12 x 12 7894450 9 789446 789455 789456 uPD78F9456GK 9ET O P22 SS20 O P31 INTP1 TO50 TMI60 O P23 SCK20 ASCK20 O P24 SO20 TxD20 O P25 SI20 RxD20 O P26 TO90 90 2 2 60 O P33 INTP3 TO61 O P61 ANI1 O P60 ANIO c c 1 2 3 4 5
88. 075 1 00 00 CHAPTER 5 CLOCK GENERATOR 5 3 Registers Controlling Clock Generator The clock generator is controlled by the following registers Processor clock control register PCC Suboscillation mode register SCKM Subclock control register CSS 1 Processor clock control register PCC PCC sets CPU clock selection and the division ratio PCC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PCC to 02H Figure 5 2 Format of Processor Clock Control Register Symbol 7 Address After reset R W roo Ts Fee me am Operation enabled Operation disabled CSS0 CPU clock selectionNete p ESEA Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control register PCC and the 550 flag in the subclock control register CSS Refer to 5 3 3 Subclock control register 55 Cautions 1 Bits 0 and 2 to 6 must be set to 0 2 The MCC can be set only when the subsystem clock has been selected as the CPU clock Remarks 1 fx Main system clock oscillation frequency 2 Subsystem clock oscillation frequency 3 parenthesized values apply to operation at fx 5 0 MHz or fxr 32 768 kHz 4 Minimum instruction execution time 2fcPu fcPU 0 2 us 0 4 us e 0 8 1 6 us e fcpu 61 us 122 us User s Manual U15075EJ1V0UMO0 105 5
89. 1 8 6 824 0215 023 0295 03 jenas snouoJuou sy jenas 5 02 1 JO 2018 71 21 User s Manual U15075EJ1VO0UMOO 212 CHAPTER 12 SERIAL INTERFACE 20 U 02058 02 1eisibe eyes pneg 0025441 102641 200541 0cSd L uondeoeH 02 150 6 00495 00425 101 m ei 24012995 0 Jejunoo uondeoeH 10 99 8S 10 99 9S 0c3X1 4145 uondeoeu Jejunoo z UOISSILUSUP 49015 HIUS uoissiuusueJ O00 uondeoeH Oc 1012 pneg jo 72 21 4 213 User s Manual U15075EJ1VO0UMOO 1 2 3 4 5 214 CHAPTER 12 SERIAL INTERFACE 20 Transmission shift register 20 TXS20 TXS20 is a register in which transmission data is prepared The transmission data is output from TXS20 bit serially When the data length is seven bits bits O to 6 of the data in TXS20 will be transmission data Writing data to TXS20 triggers transmission TXS20 can be written with an 8 bit memory man
90. 1 through 3 6 show the memory maps Figure 3 1 Memory 789425 789435 FFFFH Special function registers 256 x 8 bits FFOOH FEFFH Internal high speed RAM 512 x 8 bits FDOOH FCFFH Reserved 05 FA04H LCD display RAM Data 5x4 bits memory space F9FFH 2FFFH Reserved 3000H A 2FFFH Program area Program Internal ROM 0080H 122 i 007FH emay Spase CALLT table area 0040H 003FH Program area 0022H 0021H Vector table area 0000H 0000H User s Manual 1 15075 1 00 00 47 48 Data memor CHAPTER 3 CPU ARCHITECTURE Figure 3 2 Memory 789426 789436 Y Y memory space 0000H FFFFH Special function registers 256 x 8 bits Internal high speed 512 x 8 bits FDOOH FCFFH Reserved FA05H FA04H LCD display RAM 5 x 4 bits y space FA00H F9FFH eserve 4000H k i 3FFFH Program Internal ROM 16384 x 8 bits 0080 007 CALLT table area 0040H 003FH Program area 0022H 0021H Vector table area 0000H User s Manual U15075EJ1VOUMOO FFFFH FF00H FEFFH FD00H FCFFH FA05H FA04H F9FFH 4000H CHAPTER 3 CPU ARCHITECTURE Figure 3 3 Memory Map uPD78F9436 Special function registers 256 x 8 bits Internal
91. 15075EJ1V0UMO0 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14 1 Basic Configuration of Interrupt Function A Internal non maskable interrupt T Internal bus S Interrupt request B Internal maskable interrupt Vector table address generator Standby release signal Internal bus Y Interrupt request Vector table address generator C External maskable interrupt Standby release signal Internal bus 6 4 INTMO INTM1 KRMOO Interrupts Edge request detector Vector table address generator Standby INTMO External interrupt mode register 0 INTM1 External interrupt mode register 1 KRMOO Key return mode register 00 IF Interrupt request flag IE Interrupt enable flag Interrupt mask User s Manual U15075EJ1VOUMOO release signal 265 CHAPTER 14 INTERRUPT FUNCTIONS 14 3 Registers Controlling Interrupt Function The following five types of registers are used to control the interrupt functions e Interrupt request flag registers 0 1 IFO and IF1 Interrupt mask flag registers 0 1 MKO and MK1 External interrupt mode registers 0 1 INTMO and INTM1 Program status word PSW Key return mode register 00 KRMOO Table 14 2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests Table 14 2 Flags Corresponding to Interrupt Request Signal
92. 2 Pull up resistor option register B2 PUB2 sets whether on chip pull up resistors on P20 to P26 are used or not On the port specified to use an on chip pull up resistor by PUB2 the pull up resistor can be internally used only for the bits set in the input mode No on chip pull up resistors can be used for the bits set in the output mode regardless of the setting of PUB2 This also applies to cases when the pins are used for alternate functions PUB2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PUB2 to 00H Figure 4 20 Format of Pull Up Resistor Option Register B2 Symbol 7 gt lt gt 0 Address X After reset R W lt 6 gt lt 5 gt lt 4 gt lt 3 gt lt 2 gt PUB2 26 25 24 2 22 21 20 FF32H 00H R W P2n on chip pull up resistor selection 0 to 6 On chip pull up resistor not used On chip pull up resistor used 4 Pull up resistor option register B3 PUB3 Pull up resistor option register PUB3 sets whether on chip pull up resistors on P30 to P33 are used or not On the port specified to use an on chip pull up resistor by PUB3 the pull up resistor can be internally used only for the bits set in the input mode No on chip pull up resistors can be used for the bits set in the output mode regardless of the setting of PUB3 This also applies to cases when the pins are used for alternate functions PUBS is set with a 1 bit or 8 bit memor
93. 2 Switch operating modes after halting the serial transmit receive operation User s Manual U15075EJ1VO0UMOO CHAPTER 12 SERIAL INTERFACE 20 c Baud rate generator control register 20 BRGC20 BRGC2O is set with an 8 bit memory manipulation instruction RESET input sets BRGC20 to 00H Symbol 7 6 5 4 Address X After reset R W 3 2 1 0 Pe Tao esa is o po eme s o ern _ Other than above Setting prohibited Cautions 1 When writing to BRGC20 during a communication operation the baud rate generator output is disrupted and communications cannot be performed normally Be sure not to write to BRGC20 during a communication operation 2 Be sure not to select n 1 during operation at fx 5 0 MHz because the resulting baud rate exceeds the rated range 3 When the external input clock is selected set port mode register 2 PM2 to input mode Remarks 1 fx Main system clock oscillation frequency 2 n Values determined by the settings of TPS200 to TPS203 1 lt n lt 8 3 The parenthesized values apply to operation at fx 5 0 MHz If the internal clock is used as the serial clock for 3 wire serial I O mode set bits TPS200 to TPS203 to Set the frequency of
94. 2 fx Main system clock oscillation frequency 3 fxr Subsystem clock oscillation frequency 4 The parenthesized values apply to operation at fw 32 768 kHz User s Manual U15075EJ1V0UMOO 173 CHAPTER 8 WATCH TIMER 8 4 Watch Timer Operation 8 4 1 Operation as watch timer The main system clock 4 19 MHz or subsystem clock 32 768 kHz is used to enable the watch timer to operate at 0 5 second intervals The watch timer is used to generate an interrupt request at specified intervals By setting bits 0 and 1 WTMO and WTM1 of the watch timer mode control register WTM to 1 the watch timer starts counting By setting them to 0 the 5 bit counter is cleared and the watch timer stops counting It is possible to start the watch timer only from zero seconds by clearing WTM1 to 0 when the interval timer and watch timer operate at the same time In this case however an error of up to 2 x 1 fw seconds may occur in the overflow INTWT after the zero second start of the watch timer because the 9 bit prescaler is not cleared to 0 8 4 2 Operation as interval timer The interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count value The interval be selected by bits 4 to 6 WTM4 to WTM6 of the watch timer mode control register WTM Table 8 3 Interval Time of Interval Timer Po wee fee ee e sew mee ee o o pee em
95. 2 7 ii Slave operation timing when DAP20 0 CKP20 0 SSE20 0 SIO20 write SCK20 5120 5020 INTCSI20 Note The value of the last bit previously output is output iii Slave operation when DAP20 0 CKP20 0 SSE20 1 SS20 SIO20 write SCK20 INTCSI20 Notes 1 The value of the last bit previously output is output 2 000 15 output until SS20 rises When SS20 is high SO20 is in a high impedance state User s Manual U15075EJ1VO0UMOO 241 CHAPTER 12 SERIAL INTERFACE 20 Figure 12 11 3 Wire Serial I O Mode Timing 3 7 Master operation when DAP20 0 CKP20 1 SSE20 0 SIO20 write SCK20 SO20 SI20 INTCSI20 v Slave operation when DAP20 0 CKP20 1 SSE20 0 SIO20 write SCK20 51020 write master Nete ae X e Y 5120 5020 INTCSI20 Note The data of SI20 is loaded at the first rising edge of SCK20 Make sure that the master outputs the first bit before the first rising of SCK20 242 User s Manual U15075EJ1VO0UMOO CHAPTER 12 SERIAL INTERFACE 20 Figure 12 11 3 Wire Serial I O Mode Timing 4 7 vi Slave operation when DAP20 0 CKP20 1 SSE20 1 SS20 A 51020 write SCK20 1 2 3 4 5 6 7 81 51020 write master Not 1 Cor JCoe X os XC INTCSI20 Notes 1 The data of 5120 is loaded at the first rising edge of
96. 4 Timing of Operation of External Event Counter with 8 Bit Resolution LE LI LILI LT bI LT ET LE LT LT LI OOH Kore Kos X XN IX N Koon Kor CR60 N 60 60 Remark N 00H to FFH User s Manual U15075EJ1VOUMOO 7 8 3 Operation as square wave output with 8 bit resolution Square waves of any frequency can be output at an interval specified by the value preset in 8 bit compare register CRnO To operate timer nO for square wave output settings must be made in the following sequence 1 When using timer 50 set P31 to output mode PM31 0 When using timer 60 set P32 to output mode PM32 0 or set P33 to output mode PM33 0 When TO61 is selected as timer output 2 Setthe output latches of P31 P32 and P33 to O 3 Disable operation of timer counter 0 TCEnO 0 4 Seta count clock for timer and enable output of TOnO 1 b Seta count value in CRnO 6 Enable the operation of TMnO TCEnO 1 When the count value of TMnO matches the value set in CRnO the 0 pin output will be inverted Through application of this mechanism square waves of any frequency can be output As soon as a match occurs TMnO is cleared to 00H and continues counting At the same time an interrupt request signal 0 is genera
97. 42 2 2 13 e eee re ebd Feed ere Tune ce edere eulos t 42 2 214 5 T Ged ala 42 2 255 eode 42 26 qp 42 NOD t ed iod koran dade tse 43 2 218 43 2 219 VPP uPD78F9436 78F9456 u 43 2 2 20 mask ROM version eese enne nennen nennen enn 43 2 3 Pin Input Output Circuits and Recommended Connection of Unused Pins 44 CHAPTER 3 CPU ARCHITECTURE ccc rese ccce aae cce rra dec Ee Tus 47 3 1 Memory Space REPERI H 47 3 1 1 Internal program memory 53 User s Manual U15075EJ1VOUMOO 11 3 1 2 Internal data memory internal high speed RAM space 54 3 1 3 Special function register SFR area 54 3 1 4 memory addressing eee ert eripe ea A et 55 3 2 Processor Regislets nei eai e a a ores 61 3 2 1 Control registers den ede Oei A
98. 5 0 TCE60 0 2 Disable timer output of TO60 TOE60 0 9 Set P31 to input mode PM31 1 4 Select the external input clock for timer 60 see Tables 7 5 and 7 6 5 Set the operation mode of timer 50 and 8 bit timer 60 to 16 bit timer counter mode see Figures 7 4 and 7 5 6 Seta count value in CR50 and CR60 7 Enable the operation of TM50 and TM60 TCE60 1 Note Start and clear of the timer in the 16 bit timer counter mode are controlled by TCE60 the value of is invalid Each time the valid edge is input the values of TM50 and TM60 are incremented When the count values of TM50 and TM60 simultaneously match the values set in CR50 and CR60 respectively both TM50 and 60 are cleared to 00H and counting continues At the same time an interrupt request signal INTTM60 is generated INTTM50 is not generated Figure 7 17 shows the timing of the external event counter operation Caution Be sure to stop the timer operation before overwriting the count clock with different data User s Manual U15075EJ1VOUMOO 7 8 01 HOO N HAS 01 H00 X jueuieDpe wouyoe 17 jou seop esneoeq pejejeueb jou K O9WLLNI 09849 05 11 es nd 1unoo 06 11 09321 0940 09 11 19 91
99. 5 When used as an 8 bit A D converter uPD789426 and 789446 Subseries only 8 bit access is possible In this case the address is FF15H When used as a 10 bit A D converter uPD789436 and 789456 Subseries only 16 bit access is possible When the uPD78F9436 a flash memory version of the 789425 or uPD789426 is used this register can be accessed in 8 bit units However only an object file assembled with the 789425 or uPD789426 can be used same is also true for the uPD78F9456 a flash memory version of the uPD789445 or uPD789446 this register can be accessed 8 bit units but only an object file assembled with the 789445 or uPD789446 can be used 66 User s Manual U15075EJ1V0UMO0 3 Table 3 4 Special Function Register List 2 2 Address Special Function Register SFR Name Symbol Bit Manipulation Unit After Reset FF4DH 8 bit timer mode control register 50 R W 00H FF4EH 8 bit timer mode control register 60 FF4FH Carrier generator output control register 60 FF70H Asynchronous serial interface mode register 20 FF71H Asynchronous serial interface status register 20 5190 n FF72H Serial operation mode register 20 R W FF73H Baud rate generator control register 20 FF80H A D converter mode register 0 FF84H Analog input channel specification register 0 FFBOH LCD display mode register 0 FFB2H LCD clock control register 0 FFB3H LCD voltage amplification control
100. 5 7 Examples of Incorrect Resonator Connection 2 2 e Signal is fetched f Parallel and near signal lines of main system clock and subsystem clock XT2 is wired parallel to X1 Remark When using the subsystem clock read X1 and X2 as XT1 and XT2 respectively and connect a resistor to XT2 in series Caution If the X1 wire is in parallel with the XT2 wire crosstalk noise may occur between the X1 and XT2 resulting in a malfunction To avoid this do not lay the X1 and XT2 wires in parallel 5 4 3 Divider circuit The divider circuit divides the output of the main system clock oscillator fx to generate various clocks 5 4 4 When no subsystem clock is used If a subsystem clock is not necessary for example for low power consumption operation or clock operation handle the XT1 and XT2 pins as follows XT1 Connect to Vss XT2 Leave open In this case however a small current leaks via the on chip feedback resistor in the subsystem clock oscillator when the main system clock is stopped To avoid this set bit 1 FRC of the suboscillation mode register SCKM so that the on chip feedback resistor will not be used Also in this case handle the XT1 and XT2 pins as stated above User s Manual U15075EJ1VO0UMOO 111 5 5 5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU such as the standby mode
101. 6 7 8 P00 KRO O 7 PO1 KR10O P02 KR2 O P03 KR3 O 255 lt 7 9 lt c O O O Cautions 1 Connect the IC Internally Connected pin directly to Vss 2 Connect the pin to 3 Connect the AVss pin to Vss Remark The parenthesized values apply to the uPD78F9456 28 User s Manual U15075EJ1VOUMOO ASCK20 AVss BZO90 CAPH CAPL COMO to CPT90 IC INTPO to INTP3 to 00 10 11 20 26 P30 to P33 P50 to P53 P60 to P65 P70 to P72 81 CHAPTER 1 GENERAL Analog input Asynchronous serial input Analog power supply Analog ground Buzzer output LCD power supply capacitance control Common output Capture trigger input Internally connected External interrupt input Key return Port 0 Port 1 Port 2 Port 3 Port 5 Port 6 Port 7 Port 8 Notes 1 789426 789436 Subseries only 2 uPD789446 789456 Subseries only P90 to P97 RESET RxD20 5520 S0 to 54 55 to 514 SCK20 120 020 TMI60 TO90 50 TO60 TO61 TxD20 Vico to Vice VPP Vss X1 X2 XT1 XT2 User s Manual U15075EJ1V0UM00 Port 9 Reset Receive data Serial chip select Segment output Serial clock Serial input Serial output Timer input Timer output Transmi
102. 7 1 Three time slot display example Figure 13 9 shows how the 5 digit LCD panel having the display pattern shown in Figure 13 8 is connected to the segment signals 50 to 514 and the common signals COMO to 2 of the uPD789446 or uPD789456 Subseries chip This example displays data 123 45 in the LCD panel The contents of the display data memory addresses to FAOEH correspond to this display The following description focuses on numeral 3 3 displayed in the third digit To display 3 in the LCD panel it is necessary to apply the select or deselect voltage to the S6 to S8 pins according to Table 13 6 at the timing of the common signals COMO to 2 Table 13 6 Select and Deselect Voltages COMO to COM2 Segment S6 S7 S8 Common According to Table 13 6 it is determined that the display data memory location 06 that corresponds to S6 must contain x111 Figure 13 10 shows examples of LCD drive waveforms between the S6 signal and each common signal When the select voltage is applied to S6 at the timing of COM1 2 an alternate rectangle waveform Vi cp Vicp is generated to turn on the corresponding LCD segment Figure 13 8 Three Time Slot LCD Display Pattern and Electrode Connections Sanc COMO San jas Remark 0104 256 User s Manual U15075EJ1V0UMO0 CHAPTER 13 LCD CONTROLLER DRIVER Figure 13 9 Example of Connecting Three Time Slot LCD Panel COM3 Open CO
103. 7 26 and 7 27 show the operation timing in the PWM output mode 168 User s Manual U15075EJ1VOUMOO 7 8 Figure 7 26 PWM Pulse Generator Mode Timing Basic Operation 1 FLELELFLEFLELFLFLELELI LELELEI TM60 count value CR60 CRH60 TCE60 Count start 60 TO61Nete E Note The initial value of TO60 is low level when output is enabled TOE60 1 Figure 7 27 PWM Output Mode Timing When CR60 and CRH60 Are Overwritten PLI LI LILI LS TM60 count value Count start INTTM60 60 TO61Nete Note The initial value of TO60 is low level when output is enabled TOE60 1 User s Manual U15075EJ1V0UMO0 169 7 8 7 5 Notes on Using 8 Bit Timer 1 Error on starting timer An error of up to 1 clock is included in the time between the timer being started and a match signal being generated This is because 8 bit timer counter is started asynchronously to the count pulse Figure 7 28 Start Timing of 8 Bit Timer Counter Count pulse 0 00H 01H 02H 03H 04H count value Timer start Remark n 5 6 2 Setting of 8 bit compare register nO 8 bit compare register 0 be set to OOH Therefore one pulse can be counted when the 8 bit timer operates as an event co
104. 82 User s Manual U15075EJ1V0UMO0 CHAPTER 15 STANDBY FUNCTION c Releasing by RESET input When the HALT mode is released by the RESET signal execution branches to the reset vector address in the same manner as the ordinary reset operation and program execution is started Figure 15 3 Releasing HALT Mode by RESET Input HALT Wait instruction 2 5 6 55 ms RESET signal Oscillation Operation Reset stabilization Operation mode HALT mode period wait status mode A lt gt gt 4 Oscillation Clock Oscillation Sl stops ME Oscillation Remark fx Main system clock oscillation frequency Table 15 2 Operation After Releasing HALT Mode PC ADI NAE 7 x x Non maskable interrupt request Executes interrupt servicing x don t User s Manual U15075EJ1V0UMO0 283 CHAPTER 15 STANDBY FUNCTION 15 2 2 STOP mode 1 Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction Caution Because the standby mode can be released by an interrupt request signal the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset When the STOP mode is set therefore the HALT mode is set immediately after the STOP instruction has been executed the wait time set by the oscillation stabilization time select register OSTS elapses
105. 8F9436 78F9456 only A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified Directly connect this pin to Vss in the normal operation mode 2 2 20 IC mask ROM version only The IC Internally Connected pin is used to set the 789426 789436 789446 and 789456 Subseries in the test mode before shipment In the normal operation mode directly connect this pin to the Vss pin with as short a wiring length as possible If a potential difference is generated between the IC pin and Vss pin due to a long wiring length or an external noise superimposed on the IC pin the user program may not run correctly Directly connect the IC pin to the Vss pin Vss 1 Keep short User s Manual U15075EJ1V0UM00 43 2 5 2 3 Pin Input Output Circuits and Recommended Connection of Unused Pins The input output circuit type of each pin and recommended connection of unused pins are shown in Table 2 1 For the input output circuit configuration of each type see Figure 2 1 Table 2 1 Types of Pin Input Output Circuits I O Circuit Recommended Connection of Unused Pins Type P20 po P33 INPT3 TO61 P50 to P53 Mask ROM version ion P50 to P53 Flash memory version Input Independently connect Voo or Vss via a resistor Output Leave open Input Independently connect to Vss a resistor Ou
106. 9446 SUBSERIES Figure 10 11 A D Conversion End Interrupt Request Generation Timing Rewriting to ADMO Rewriting to ADMO to begin conversion to begin conversion ADIFO has been set but conversion for ANIn for ANIm for ANIm has not been completed A D conversion ADCRO INTADO Remarks 1 0105 2 0105 9 AVbp The pin is used to supply power to the analog circuit It is also used to supply power to the to input circuit If your application is designed to be changed to backup power the pin must be supplied with the same voltage level as the pin as shown in Figure 10 12 Figure 10 12 Pin Handling Main power Backup Source capacitor 10 pin input impedance A series resistor string of several ten of is connected between the AVpp and AVss pins Consequently if the output impedance of the reference voltage supply is high the reference voltage supply will form a parallel connection with the series resistor string creating a large reference voltage differential Users Manual U15075EJ1VOUMOO 195 196 User s Manual U15075EJ1V0UMOO CHAPTER 11 10 A D CONVERTER 789436 AND 789456 SUBSERIES 11 1 10 Bit A D Converter Functions The 10 bit A D converter is a 10 bit resolution converter used to convert analog inputs into digital signals This converter can control six channels ANIO
107. A D Converter Control Registers The 10 bit A D converter is controlled by the following two registers A D converter mode register 0 ADMO Analog input channel specification register 0 ADSO 1 200 A D converter mode register 0 ADMO ADMO specifies the conversion time for analog inputs It also specifies whether to enable conversion ADMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADMO to 00H Figure 11 2 Format of A D Converter Mode Register 0 lt 7 gt 6 Address After reset R W 5 4 3 2 1 0 ADCSO A D conversion control Ew Conversion disabled Conversion enabled 02 FROO A D conversion time selectionNete 1 oq mmus fer pm Gee 9 1 eom S 48 fx Setting prohibitedNete 2 Other than above Setting prohibited Notes 1 The specifications of FRO2 FRO1 and FR00 must be such that the A D conversion time is at least 14 us 2 These bit combinations must not be used as the A D conversion time will fall below 14 us Cautions 1 Bits 0 to 2 and 6 must be set to 0 2 Theresult of conversion performed immediately after setting ADCSO is undefined 3 The conversion result may be undefined after clearing ADCSO Remarks 1 fx Main system clock oscillation frequency 2 The parenthesized values apply to operation at fx 2 5 0 MHz User s Manual U15075EJ1VO0UMOO CH
108. APTER 11 10 BIT A D CONVERTER uPD789436 AND 789456 SUBSERIES 2 Analog input channel specification register 0 ADSO ADSO specifies the port used to input the analog voltage to be converted to a digital signal ADSO is set with 1 bit or 8 bit memory manipulation instruction RESET input clears ADSO to 00H Figure 11 3 Format of Analog Input Channel Specification Register 0 Symbol 7 6 Address After reset R W 5 4 3 2 1 0 1 Other than above Setting prohibited Caution Bits 3 to 7 must be set to 0 Users Manual U15075EJ1VOUMOO 201 CHAPTER 11 10 BIT A D CONVERTER uPD789436 AND 789456 SUBSERIES 11 4 10 Bit A D Converter Operation 11 4 1 Basic operation of 10 bit A D converter 1 2 3 d 5 6 T 8 Select a channel for A D conversion using analog input channel specification register 0 ADSO The voltage supplied to the selected analog input channel is sampled using the sample amp hold circuit After sampling continues for a certain period of time the sample amp hold circuit is put on hold to keep the input analog voltage until A D conversion is completed Bit 9 of the successive approximation register SAR is set The series resistor string tap voltage at the tap selector is set to half of AVpp The series resistor string tap voltage is compared with the analog input voltage using the voltage comparator If the analog input voltage is higher than half of AVpp the MSB of
109. B2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal User s Manual U15075EJ1VOUMOO CHAPTER 4 PORT FUNCTIONS 4 2 4 Port 3 This is 4 bit port with an output latch Port can be specified in the input or output mode in 1 bit units by using port mode register 3 PM3 When using the P30 to P33 pins as input port pins on chip pull up resistors can be connected in 1 bit units by using pull up resistor option register B3 PUB3 This port is also used as an external interrupt input capture input and timer This port is set in the input mode when the RESET signal is input Figures 4 11 and 4 12 show block diagrams of port 3 Figure 4 11 Block Diagram of P30 D ae WRpuses Alternate function RD 4 Selector Internal bus WRport Output latch P30 P30 INTPO CPT90 PUBS3 Pull up resistor option register B3 PM Port mode register RD Port 3 read signal WR Port 3 write signal User s Manual 015075 89 CHAPTER 4 PORT FUNCTIONS Figure 4 12 Block Diagram of P31 to P33 1 to Alternate function RD off seo n PORT Internal bus Output latch d P31 to P33 P32 INTP2 TO60 P33 INTP3 TO61 J gt 1 Q P31 INTP1 TO50 TMI60 z
110. B9 1 Port mode registers to PM3 PM5 PM7 to PM9 These registers are used to set port input output in 1 bit units The port mode registers are independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the registers to FFH When port pins are used as alternate function pins set the port mode register and output latch according to Table 4 3 Caution As port 3 has an alternate function as external interrupt input when the port function output mode is specified and the output level is changed the interrupt request flag is set When the output mode is used therefore the interrupt mask flag should be preset to 1 96 User s Manual U15075EJ1V0UMO0 CHAPTER 4 PORT FUNCTIONS Figure 4 18 Format of Port Mode Register Symbol 7 6 Address After reset R W s nw eve errem nw es Tr T T ewe FF20H FFH R W Pmn pin input output mode selection m 0103 5 7t09 0107 Output mode output buffer Input mode output buffer OFF Note Incorporated only the 789426 and 789436 Subseries User s Manual U15075EJ1VOUMOO 97 CHAPTER 4 PORT FUNCTIONS Table 4 3 Port Mode Register and Output Latch S
111. Bit 155 7 17 Timing of External Event Counter Operation with 16 Bit 157 7 18 Timing of Square Wave Output with 16 Bit Resolution essen 159 7 19 Timing of Carrier Generator Operation When CR60 CRH60 M M gt N 161 7 20 Timing of Carrier Generator Operation When CR60 CRH60 M M N Phases of Carrier Clock and NRZ60 Are Asynchronous 162 7 21 Timing of Carrier Generator Operation When CR60 CRH60 163 7 22 Operation Timing in PWM Free Running Mode When Rising Edge Is Selected 165 7 23 Operation Timing When Overwriting CR50 When Rising Edge Is Selected 165 7 24 Operation Timing in PWM Free Running Mode When Both Edges Are Selected 166 7 25 Operation Timing in PWM Free Running Mode When Both Edges Are Selected When CR50 Is Overwritten eere tt eene the Tec ep oda due 167 7 26 PWM Pulse Generator Mode Timing Basic 169 7 27 PWM Output Mode Timing When CR60 and CRH60 Are 169 7 28 Start Timing of 8 Bit Timer Gounter 0 enne enne nennen innen in
112. CTIONS Table 14 1 Interrupt Source List Note 1 Interrupt Type Priority Non maskable Interrupt Source Internal Vector Basic Name Trigger External Table Configuration Address INTWDT Watchdog timer overflow with Internal 0004H watchdog timer mode 1 selected INTWDT Watchdog timer overflow with interval timer mode selected 1 INTPO Pin input edge detection External 0006H C INTP1 0008H INTP2 000AH INTP3 000CH INTSR20 End of serial interface 20 UART Internal 000EH B reception INTCSI20 End of serial interface 20 3 wire SIO transfer reception INTST20 End of serial interface 20 UART 0012H transmission 7 INTWTI Interval timer interrupt 0014H INTTM90 Generation of match signal of 16 bit 0016H timer 90 50 Generation of match signal of 8 bit 0018H timer 50 INTTM60 Generation of match signal of 8 bit 001AH timer 60 INTADO End of A D conversion signal 001CH 1 INTWT Watch timer interrupt 001EH 13 INTKROO Key return signal detection 0020H Notes 1 Priority is the priority order when several maskable interrupts are generated at the same time 0 is the highest order and 13 is the lowest order 2 Basic configuration types A to C correspond to A to C in Figure 14 1 1 0 11 2 Remark There are two interrupt sources for the watchdog timer INTWDT non maskable and maskable interrupts internal Either one but not both should be selected for actual use 264 User s Manual U
113. EJ1V0UMO0 313 APPENDIX DEVELOPMENT TOOLS A 3 2 Software ID78KOS NS Control program for debugging 78K 0S Series Integrated debugger This program provides a graphical use interface It runs on Windows for personal computer Supports in circuit emulator users and on OSF Motif for engineering work station users and has visual designs and IE 78K0S NS operationability that comply with these operating systems In addition it has a powerful debug function that supports C language Therefore trace results can be displayed at a C language level by the window integration function that links source program disassembled display and memory display to the trace result This software also allows users to add other function extension modules such as task debugger and system performance analyzer to improve the debug efficiency for programs using a real time operating system Used in combination with optional device file DF789456 Part number wSxxxxID78KOS NS Remark the part number differs depending on the host machines and operating systems to be used USxxxxID78KOS NS AA13 PC 9800 series Japanese Windows 3 5 2HD FD IBM PC AT compatibles Japanese Windows 3 5 2HC FD English Windows Note Also operates under the DOS environment 5 78 05 Debugs program at C source level assembler level while simulating operation of target System simulator system on host machine SM78KOS runs under Window
114. End of A D conversion End of A D conversion ADCRO Normal conversion result Undefined value INTADO ADCSO Normal conversion result is read A D conversion Undefined value stops is read Figure 11 9 Conversion Result Read Timing If Conversion Result Is Normal End of A D conversion ADCRO X Normal conversion result INTADO ADCSO A D conversion stops Normal conversion result is read Users Manual U15075EJ1VOUMOO 207 6 7 8 208 CHAPTER 11 10 BIT A D CONVERTER uPD789436 AND 789456 SUBSERIES Noise prevention To maintain a resolution of 10 bits watch for noise to the and to ANI5 pins The higher the output impedance of the analog input source the larger the effect by noise To reduce noise attach an external capacitor to the relevant pins as shown in Figure 11 10 Figure 11 10 Analog Input Pin Treatment If noise not lower than AVpp or not higher than AVss is likely to come to the AVop pin clamp the voltage at the pin by attaching a diode with a small Vr 0 3 V or lower C 100 to 1 000 pF A ANI0 to ANI5 The analog input pins ANI0 to ANI5 are alternate function pins They are also used as port pins P60 to P65 If any of ANI0 to ANI5 has been selected for A D conversion do not execute input instructions for the ports otherwise the conversion resolution may be reduced If a digital pulse is applied to a pin adjacent to the analog input
115. HALT mode In both modes the previous contents of the registers flags and data memory before setting the standby mode are all retained In addition the statuses of the output latch of the ports and output buffer are also retained Caution To set the STOP mode be sure to stop the operations of the peripheral hardware and then execute the STOP instruction User s Manual U15075EJ1V0UMO0 279 CHAPTER 15 STANDBY FUNCTION 15 1 2 Register controlling standby function The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled with the oscillation stabilization time select register OSTS OSTS is set with an 8 bit memory manipulation instruction RESET input sets OSTS to 04H However it takes 2 fx not 2 fx after RESET input Figure 15 1 Format of Oscillation Stabilization Time Select Register Symbol 7 6 Address After reset R W 5 4 3 2 1 0 OSTS OSTS2 OSTS1 OSTSO FFFAH 04H R W o o 056206750750 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection INERENTI 215 fx 6 55 ms o Other than above Setting prohibited Caution The wait time after the STOP mode is released does not include the time from STOP mode release to clock oscillation start a in the figure below regardless of whether STOP mode is released by RESET input or by interrupt generation STOP mode release X1 pin voltage waveform Vss 2 Re
116. J1VOUMOO CHAPTER 9 WATCHDOG 9 3 Watchdog Timer Control Registers The watchdog timer is controlled by the following two registers Watchdog timer clock select register WDCS Watchdog timer mode register WDTM 1 Watchdog timer clock select register WDCS This register sets the watchdog timer count clock WDCS is set with an 8 bit memory manipulation instruction RESET input sets WDCS to 00H Figure 9 2 Format of Watchdog Timer Clock Select Register Symbol 7 Address After reset R W WDCS2 WDCS1 WDCSO Watchdog timer count clock selection 6 26 78 1 kHz D 1 64 ms 6 28 19 5 kHz 2 5 fx 6 55 ms fx 2 0 4 88 kHz 217 26 2 ms Other than above Setting prohibited Remarks 1 fx Main system clock oscillation frequency 2 The parenthesized values apply to operation at fx 2 5 0 MHz User s Manual U15075EJ1V0UMOO 179 2 WDTM 180 CHAPTER 9 WATCHDOG TIMER Watchdog timer mode register WDTM This register sets the operation mode of the watchdog timer and enables disables counting of the watchdog timer WDTM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets WDTM to 00H Figure 9 3 Format of Watchdog Timer Mode Register lt 7 gt Address After reset R W Watchdog timer operation selection EN Stops counting Clears counter and starts counting Interval mode Generates a maskable interrupt upon overflow
117. M 2 COM 1 COM 0 Timing strobe 50 51 52 53 54 55 56 57 58 59 510 511 512 513 514 LCD panel OMAN DA FW IM Data memory address x Can be used to store any data because there is no corresponding segment in the LCD panel x Can always be used to store any data because of the three time slot mode being used User s Manual U15075EJ1VO0UMOO 257 CHAPTER 13 LCD CONTROLLER DRIVER 258 Figure 13 10 Three Time Slot LCD Drive Waveform Examples Vico Vici Vic2 COMO Vsso Vico Vici Vic2 COM1 Vsso Vico Vici Vice 2 Vsso Vico Vici Vic2 S6 Vsso 1 3 56 0 1 3V cp 1 3 1 56 0 1 3 1 3 2 56 0 1 3Vicp User s Manual U15075EJ1VOUMOO CHAPTER 13 LCD CONTROLLER DRIVER 13 7 2 Four time slot display example Figure 13 12 shows how the 7 digit LCD panel having the display pattern shown in Figure 13 11 is connected to the segment signals SO to S14 and the common signals COMO to of the uPD789446 or uPD789456 Subseries chip This example displays data 123456 7 in the LCD panel T
118. M and special function registers SFRs are mapped at FE20H to FEFFH and FFOOH to FF1FH respectively The SFR area FFOOH to FF1FH where short direct addressing is applied is a part of the whole SFR area Ports that are frequently accessed in a program and the compare register of the timer event counter are mapped in this area and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at to 1FH bit 8 is setto 1 See Illustration below Operand format Label or FE20H to FF1FH immediate data Label or FE20H to FF1FH immediate data even address only Description example MOV FE90H 50 When setting saddr to FE90H and the immediate data to 50H Instruction code 1 1 1 1 0 1 0 1 OP code 1 0 O 1 0 0 0 0 90H 0 1 0 1 0 0 0 0 50H Immediate data Illustration OP code saddr offset Short direct memory Effective address When 8 bit immediate data is 20H to FFH H When 8 bit immediate data is OOH to 1FH a 72 User s Manual U15075EJ1VOUMOO 3 3 4 3 Special function register SFR addressing Function The memory mapped special function registers SFRs are addressed with 8 bit immediate data in an instruction word This addressing is applied to the 256 byte space FFOOH to FFFFH However the SFRs mappe
119. M versions Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions When pre producing an application set with the flash memory version and then mass producing it with the mask ROM version be sure to conduct sufficient evaluations for the commercial samples not engineering samples of the mask ROM version User s Manual U15075EJ1V0UMO0 291 CHAPTER 17 JPD78F9436 78F9456 17 1 Flash Memory Programming The on chip program memory in the uPD78F9436 78F9456 is a flash memory The flash memory can be written with the 78 9436 and 78F9456 mounted on the target system on board Connect the dedicated flash writer Flashpro part no FL PR3 PG FP3 to the host machine and target system to write the flash memory Remark is made by Densei Machida Mfg Co Ltd 17 1 1 Selecting communication mode The flash memory is written by using Flashpro and by means of serial communication Select a communication mode from those listed in Table 17 2 To select a communication mode the format shown in Figure 17 1 is used Each communication mode is selected by the number of VPP pulses shown in Table 17 2 292 Table 17 2 Communication Mode Communication Mode Number of VPP Pulses 3 wire serial I O SCK20 ASCK20 P23 SO20 TxD20 P24 SI20 RxD20 P25 UART TxD20 SO20 P24 RxD20 SI20 P25 Caution Be sure to select a communication mode depending
120. MOO P10 to P13 Port 1 4 bit port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register 0 PUO Port 2 7 bit port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register B2 PUB2 Port 3 4 bit port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register B3 P50 to P53 Port 5 4 bit N ch open drain I O port Input output can be specified in 1 bit units For a mask ROM version an on chip pull up resistor can be specified by the mask option B NN Input 9 INTP1 TO50 E NTPSTOG ubl P60 to P65 Input Port 6 Input to 5 6 bit input port P70 to P72 Port 7 3 bit port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register B7 PUB7 User s Manual U15075EJ1VOUMOO I 37 2 5 1 Port pins 2 2 811 Port 8 Input 2 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resist
121. Mode 4 md lt 1 ADCSO Series resistor string AVss 2 Input range for pins ANIO to ANI5 Be sure to keep the input voltage at ANIO to ANI5 within the rating If a voltage not lower than or not higher than AVss even within the absolute maximum rating is input into a conversion channel the conversion output of the channel becomes undefined which may affect the conversion output of the other channels 3 Conflict 1 Conflict between writing to A D conversion result register 0 ADCRO at the end of conversion and reading from ADCRO using instruction Reading from ADCRO takes precedence After reading the new conversion result is written to ADCRO 2 Conflict between writing to ADCRO at the end of conversion and writing to A D converter mode register 0 ADMO or analog input channel specification register 0 ADSO Writing to ADMO or ADSO takes precedence ADCRO is not written to No A D conversion end interrupt request signal INTADO is generated 4 Conversion result immediately after start of A D conversion The first A D conversion value immediately after A D conversion has been started is undefined Poll the A D conversion end interrupt request INTADO and drop the first conversion result 192 Users Manual U15075EJ1VOUMOO CHAPTER 10 8 A D CONVERTER uPD789426 AND 789446 SUBSERIES 5 Timing of undefined A D conversion result The A D conversion value may
122. Name Interrupt Request Signal Name Interrupt Request Flag Interrupt Mask Flag INTWDT WDTIF WDTMK INTPO PIFO PMKO INTP1 PIF1 PMK1 INTP2 PIF2 PMK2 INTSR20 INTCSI20 SRIF20 SRMK20 INTST20 STIF20 STMK20 INTWTI WTIIF WTIMK INTTM90 TMIF90 TMMK90 50 TMIF50 TMMK50 INTTM60 TMIF60 TMMK60 INTADO ADIFO ADMKO INTWT WTIF WTMK INTKROO KRIFOO KRMKO0O 266 User s Manual U15075EJ1V0UMO0 CHAPTER 14 INTERRUPT FUNCTIONS 1 Interrupt request flag registers 0 1 IFO and IF1 The interrupt request flag is set 1 when the corresponding interrupt request is generated or an instruction is executed It is cleared 0 when an instruction is executed upon acknowledgement of an interrupt request or upon RESET input IFO and are set with a 1 bit or 8 bit memory manipulation instruction RESET input sets IFO and to OOH Figure 14 2 Format of Interrupt Request Flag Registers Symbol 7 6 b 4 9 2 lt gt 0 Address X After reset R W IFO sTIF20 SRIF20 PIF2 PIF1 FFEOH 00H R W gt lt gt lt 0 7 lt 6 gt lt 5 gt 4 lt 3 gt lt 2 gt IF1 EX 00 WTIF 40 TMIF30 TMIF20 WTIIF FFE1H 00H R W XXIFX Interrupt request flag No interrupt request signal is generated Interrupt request signal is generated Interrupt request state Cautions 1 Bit 7 of IF1 and bit 6 of IF0 must be set to 0 2
123. P gt Ponr Output latch P22 P22 SS20 WRem PM22 PRS PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal User s Manual U15075EJ1VOUMOO 86 CHAPTER 4 PORT FUNCTIONS Figure 4 8 Block Diagram of P23 PUB23 Alternate gt Es function lt q Output latch i 23 P23 ASCK20 5 20 a PM23 WRpeus2 RD 5 5 TIN PUB2 PM RD WR Alternate function Y Pull up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User s Manual U15075EJ1VOUMOO CHAPTER 4 PORT FUNCTIONS Figure 4 9 Block Diagram of P24 5 lt o _ o n WhReonr Output latch utput latc 24 l2 P24 SO20 TxD20 WRPM PM24 PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal User s Manual U15075EJ1VOUMOO 87 CHAPTER 4 PORT FUNCTIONS Figure 4 10 Block Diagram of P25 D Es Alternate function RD 5 5 WRP gt Ponr Output latch P25 SI20 P25 RxD20 25 0 2 PU
124. RP2 HL RP3 Special function register symbol FE20H to FF1FH Immediate data or labels FE20H to FF1FH Immediate data or labels even addresses only 0000H to FFFFH Immediate data or labels only even addresses for 16 bit data transfer instructions 0040H to 007FH Immediate data or labels even addresses only 16 bit immediate data or label 8 bit immediate data or label 3 bit immediate data or label Remark See Table 3 4 Special Function Register List for symbols of special function registers User s Manual U15075EJ1V0UMO0 299 CHAPTER 19 INSTRUCTION SET 19 1 2 Description of Operation column A A register 8 bit accumulator X X register B B register C C register D D register E E register H H register L L register AX AX register pair 16 bit accumulator BC BC register pair DE DE register pair HL HL register pair PC Program counter SP Stack pointer PSW Program status word CY Carry flag AC Auxiliary carry flag Z Zero flag IE Interrupt request enable flag NMIS Flag indicating non maskable interrupt servicing in progress Memory contents indicated by address or register contents in parenthesis XH Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR V Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Signed 8 bit data displacement value 19 1 3 Description of Flag column
125. SCK20 Make sure that the master outputs the first bit before the first rising of SCK20 2 5020 is high until 5520 rises after completion of DOO output When 5520 is high 5020 is in a high impedance state vii Master operation when DAP20 1 CKP20 0 SSE20 0 SIO20 write SCK20 5020 5120 INTCSI20 User s Manual U15075EJ1VO0UMOO 243 CHAPTER 12 SERIAL INTERFACE 20 Figure 12 11 3 Wire Serial I O Mode Timing 5 7 viii Slave operation when DAP20 1 CKP20 0 SSE20 0 SIO20 write SCK20 51020 write master Nete E Cor Y oe X X r X po X 5120 5020 aor os X pos X pos X 5 X por X ay INTCSI20 i Note data of 120 is loaded at the first falling edge of SCK20 Make sure that the master outputs the first bit before the first falling of SCK20 ix Slave operation when DAP20 1 CKP20 0 SSE20 1 SS20 SIO20 write SCK20 51020 write master e e 1 Cor X pe Y CR Y 5120 INTCSI20 Notes 1 The data of 5120 is loaded at the first falling edge of SCK20 Make sure that the master outputs the first bit before the first falling of SCK20 2 5020 is high until 5520 rises after completion of DO0 output When 5520 is high 5020 15 high impedance state 244 User s Manual U15075EJ1VO0UMOO CHAPTER 12 SERIAL INTERFACE 20 Figure 12 11 3 Wire Serial I O Mode Timing 6 7
126. SPARCSstation is a trademark of SPARC International Inc Solaris and SunOS are trademarks of Sun Microsystems Inc OSF Motif is a trademark of Open Software Foundation Inc NEWS and NEWS OS are trademarks of Sony Corporation TRON is an abbreviation of The Realtime Operating system Nucleus ITRON is an abbreviation of Industrial TRON User s Manual U15075EJ1VOUMOO The export of these products from Japan is regulated by the Japanese government The export of some or all of these products may be prohibited without governmental license To export or re export some or all of these products from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative License not needed LPD78F9436 78F9456 The customer must judge the need for license 789425 789426 789435 789436 789445 789446 789455 789456 The information in this document is current as of September 2000 The information is subject to change without notice For actual design in refer to the latest publications of NEC s data sheets or data books etc for the most up to date specifications of NEC semiconductor products Not all products and or types are available in every country Please check with an NEC sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC NEC assumes no r
127. T input sets PM2 to Figure 6 4 Format of Port Mode Register 2 Symbol 7 6 Address After reset R W PM2 PM26 22 FFH Output mode output buffer Input mode output buffer OFF 122 Users Manual U15075EJ1VOUMOO CHAPTER 6 16 BIT 6 4 16 Bit Timer Operation 6 4 1 Operation as timer interrupt In the timer interrupt function interrupts are repeatedly generated at the count value preset in 16 bit compare register 90 CR90 based on the intervals of the value set in TCL901 and TCL900 To operate the 16 bit timer as a timer interrupt the following settings are required Set count values in CR90 Set 16 bit timer mode control register 90 TMC90 as shown in Figure 6 5 Figure 6 5 Settings of 16 Bit Timer Mode Control Register 90 for Timer Interrupt Operation TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 TMC90 0 1 0 1 0 1 0 1 0 0 1 0 1 wm on Caution If both the CPT901 and CPT900 flags are set to 0 the capture operation is prohibited Setting of count clock see Table 6 2 When the count value of 16 bit timer counter 90 TM90 matches the value set in CR90 counting of TM90 continues and an interrupt request signal 90 is generated Table 6 2 shows interval time and Figure 6 6 shows timing of timer interrupt operation Caution When rewriting the value in CR90 during a count operation be sure to execute the following processing 1 Setin
128. V0UMO0 CHAPTER 13 LCD CONTROLLER DRIVER 2 LCD clock control register 0 LCDCO LCDCO specifies the LCD clock and frame frequency LCDCO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets LCDCO to 00H Figure 13 3 Format of LCD Clock Control Register 0 Symbol 7 Address After reset R W c s Ts s gt pespepespes LCDC03 LCDC02 Internal clock fico selectionNete Es 1 2 156 3 2 LCD clock LCDCL selection Note Specify an internal clock fico frequency of at least 32 kHz Cautions 1 Bits 4 to 7 must be set to 0 2 Before changing the LCDCO setting be sure to stop voltage amplification VAONO 0 3 Set the frame frequency to 128 Hz or lower Remarks 1 fx Main system clock oscillation frequency 2 Subsystem clock oscillation frequency 3 The parenthesized values apply to operation at fx 5 0 MHz fxr 32 768 kHz Table 13 3 lists the frame frequencies used when fxr 32 768 kHz is supplied to the internal clock fcuk1 Table 13 3 Frame Frequencies Hz LCD Clock fico 2 2 fx1 2 fx1 2 Display Duty Ratio 64 Hz 128 Hz 256 Hz 512 Hz _____ _ __ _ o m Note This setting is prohibited because it causes the frame frequency to exceed 128 Hz User s Manual U15075EJ1V0UM00 251 CHAPTER 13 LCD CONTROLLER DRIVER 3 LCD voltage amplification control register 0 LCDVAO LCDVAO controls the voltage
129. V0UMO0 CHAPTER 4 PORT FUNCTIONS 4 2 7 Port 7 This is a 3 bit port with an output latch Port 7 can be specified in the input or output mode in 1 bit units by using port mode register 7 PM7 When using the P70 to P72 pins as input port pins on chip pull up resistors can be connected in 1 bit units by using pull up resistor option register B7 PUB7 This port is set in the input mode when the RESET signal is input Figure 4 15 shows a block diagram of Port 7 Figure 4 15 Block Diagram of P70 to P72 7 Selector o 2 a 9 2 Output latch P7 P72 P70 to P72 P701o WRPM PM70 to PM72 AZ PUB7 Pull up resistor option register B7 PM Port mode register RD Port 7 read signal WR Port 7 write signal User s Manual U15075EJ1V0UMO0 93 CHAPTER 4 PORT FUNCTIONS 4 2 8 Port 8 uPD789426 789436 Subseries only This is a 2 bit port with an output latch Port 8 can be specified in the input or output mode in 1 bit units by using port mode register 8 PM8 When using pins P80 and P81 as input port pins on chip pull up resistors can be connected in 1 bit units by using pull up resistor option register B8 8 This port is set in the input mode when the RESET signal is input Figure 4 16 shows a block diagram of port 8 Figure 4 16 Block Diagram of P80 and P81 WRPuss lI MA
130. VO0UMOO 131 7 8 b Timer 60 Pulse generator mode The timer output status inverts repeatedly due to the settings of TM60 CR60 and 60 and pulses of any duty ratio are output either P32 INTP2 TO60 or P33 INTP3 TO61 can be selected as the timer output pin using software 7 2 8 Bit Timer Configuration The 8 bit timer includes the following hardware Table 7 2 8 Bit Timer Configuration Control registers 8 bit timer mode control register 50 TMC50 8 bit timer mode control register 60 TMC60 Carrier generator output control register 60 TCA60 Port mode register 3 132 User s Manual U15075EJ1V0UMO0 7 8 uonoeuuoo epeoseo 5 uonejedo punog 2 4 woi epeoseo 09 3 amp 4 uomnoeuuoo 2 jeuBis 06 9 2 2 4 01 2 2 en614 ULY e 1ndjno 09 10 ul 20 499 2 4 Jopejes ru is sanba 1dnu lu 09
131. al falling edge of port 0 KRMOO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets KRMOO to 00H Figure 14 7 Format of Key Return Mode Register 00 Address After reset R W Symbol 7 6 FFF5H 00H R W 5 4 3 2 1 0 wo o T T T Tees KRM000 Key return signal detection control No detection Detection detecting falling edge of port 0 Cautions 1 Bits 1 to 7 must be set to 0 2 Before setting KRMOO always set bit 6 of MK1 KRMKOO 1 to disable interrupts After setting KRM00 clear KRMKOO after clearing bit 6 of IF1 KRIFOO 0 to enable interrupts 3 When P00 to are in input mode on chip pull up resistors are connected to P00 to by the setting of KRMOOO After switching to output mode the on chip pull up resistors are cut off However key return signal detection continues Figure 14 8 Block Diagram of Falling Edge Detector Key return mode register 00 KRMOO POO KRO P01 KR1 PO2 KR2 POS KR3 Falling edge detector KRIFOO set signal Le Standby release KRMKOO signal Note Selector that selects the pin used for falling edge input Selector User s Manual U15075EJ1VOUMOO 271 CHAPTER 14 INTERRUPT FUNCTIONS 14 4 Interrupt Servicing Operation 14 4 1 Non maskable interrupt request acknowledgment operation The non maskable interrupt request is unconditionally acknowledged even when interrupts are disable
132. al high speed RAM area can be addressed using stack addressing Description example In the case of PUSH DE Instruction code 1 0 1 01 0 1 O 76 User s Manual U15075EJ1V0UM00 CHAPTER 4 PORT FUNCTIONS 4 1 Port Functions The uPD789426 789436 789446 and 789456 Subseries provide the ports shown in Figures 4 1 and 4 2 enabling various methods of control Numerous other functions are provided that can be used in addition to the digital port functions For more information on these additional functions see CHAPTER 2 PIN FUNCTIONS Figure 4 1 Port Types uPD789426 789436 Subseries Port 0 Port 6 gt Port 1 Port 7 4 Port 2 Port 8 gt Port 9 gt Port5 User s Manual U15075EJ1VO0UMOO 77 CHAPTER 4 PORT FUNCTIONS Figure 4 2 Port Types uPD789446 789456 Subseries Port5 lt gt Port 0 gt Port 1 Port 6 Port 2 Port 7 gt User s Manual U15075EJ1VOUMOO CHAPTER 4 PORT FUNCTIONS Table 4 1 Port Functions 1 2 to Port 0 Input KRO to 4 bit port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register 0 PUO or key return mode register 00 10 11 Port 1 Input 2 bit port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specifie
133. alling edge of SCK20 1 Outputs at the rising edge of SCK20 DIR20 First bit specification CSCK20 3 wire serial mode clock selection EN External clock input to the SCK20 pin Output of the dedicated baud rate generator CKP20 3 wire serial mode clock phase selection Clock is low active and SCK20 is high level in the idle state Clock is high active and SCK20 is low level in the idle state Caution Bits 4 and 5 must be set to 0 Users Manual U15075EJ1VOUMOO 225 CHAPTER 12 SERIAL INTERFACE 20 b Asynchronous serial interface mode register 20 ASIM20 ASIM20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM20 to 00H Symbol 7 Address After reset R W lt 6 gt 5 4 3 2 1 0 TXE20 Transmit operation control Transmit operation stopped Transmit operation enabled Receive operation stopped Receive operation enabled No parity Odd parity 1 Always add 0 at transmission Parity check is not performed at reception No parity error is generated Even parity Cautions 1 Bits 0 and 1 must be set to O 2 Switch operating modes after halting the serial transmit receive operation 226 Users Manual U15075EJ1VOUMOO CHAPTER 12 SERIAL INTERFACE 20 c Asynchronous serial interface status register 20 ASIS20 ASIS20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIS20 to 00H Symbol 7 6 gt Address After reset R W 5 4 3
134. als 15 common signals 4 uPD789446 789456 Subseries Vectored interrupt sources 15 Power supply voltage 1 8 to 5 5 V Operating ambient temperature TA 40 to 85 1 2 Applications Portable audio cameras healthcare equipment etc User s Manual U15075EJ1VOUMOO 25 1 3 Ordering Information CHAPTER 1 GENERAL Part Number Package Internal ROM LPD789425GK ooc9ET 64 pin plastic TQFP 12 x 12 mm Mask ROM UPD789426GK xxx 9ET 64 pin plastic TQFP 12 x 12 mm Mask ROM UPD789435GK xxx 9ET 64 pin plastic TQFP 12 x 12 mm Mask ROM uUPD789436GK xxx 9ET 64 pin plastic TQFP 12 x 12 mm Mask ROM UPD789445GK xxx 9ET 64 pin plastic TQFP 12 x 12 mm Mask ROM uUPD789446GK xxx 9ET 64 pin plastic TQFP 12 x 12 mm Mask ROM UPD789455GK xxx 9ET 64 pin plastic TQFP 12 x 12 mm Mask ROM uUPD789456GK xxx 9ET 64 pin plastic TQFP 12 x 12 mm Mask ROM UPD78F9436GK 9ET 64 pin plastic TQFP 12 x 12 mm Flash memory UPD78F9456GK 9ET 64 pin plastic TQFP 12 x 12 mm Flash memory Remark indicates ROM code suffix 26 User s Manual U15075EJ1VOUMOO CHAPTER 1 GENERAL 1 4 Pin Configuration Top View 1 4 1 Pin configuration of 789426 789436 Subseries Top view 64 pin plastic TQFP fine pitch 12 x 12 789425 9 789426 789435 uPD789436GK ooc9ET uPD78F9436GK 9ET e e e 4 N N oa O P23 SCK20 ASCK20 O P24 SO20 TxD2
135. analog inputs from the input circuit one by one and sends them to the voltage comparator The sampled analog input voltage is held during A D conversion Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string Series resistor string The series resistor string is configured between and AVss generates the reference voltages against which analog inputs are compared to ANI5 Pins ANIO to ANI5 are the 6 channel analog input pins for the A D converter They are used to receive the analog signals for A D conversion Caution Do not supply pins to ANI5 with voltages that fall outside the rated range If a voltage greater than or less than AVss even if within the absolute maximum rating is applied to any of these pins the conversion value for the corresponding channel will be undefined Furthermore the conversion values for the other channels may also be affected AVss pin The AVss pin is a ground potential pin for the A D converter This pin must be held at the same potential as the Vss pin even while the A D converter is not being used pin The pin is an analog power supply pin for the A D converter This pin must be held at the same potential as the pin even while the A D converter is not being used User s Manual U15075EJ1V0UMOO 199 CHAPTER 11 10 BIT A D CONVERTER uPD789436 AND 789456 SUBSERIES 11 3 10 Bit
136. anipulation instruction 2 When setting the carrier generator operation again after stopping it once reset NRZB60 because the previous value is not retained In this case also a 1 bit memory manipulation instruction cannot be used Be sure to use an 8 bit memory manipulation instruction Figures 7 19 to 7 21 show the operation timing of the carrier generator 160 User s Manual U15075EJ1VOUMOO 7 8 CRH60 M gt Figure 7 19 Timing of Carrier Generator Operation When CR60 Count clock Clear count value N CR60 M CRH60 TCE60 Count start INTTM60 Carrier clock Count pulse CR50 50 50 NRZB60 NRZ60 Carrier clock TO60 or TO61 161 User s Manual U15075EJ1VOUMOO 7 8 Figure 7 20 Timing of Carrier Generator Operation When CR60 N CRH60 M M N Phases of Carrier Clock and NRZ60 Are Asynchronous Count clock LPFLILI LILI LS TM60 count value CR60 CRH60 M TCE60 A Count start i INTTM60 Carrier clock Count pulse LT LJ LI 1 50 CR50 5 INTTM50 ______ _____ 0 0 NRZ60 0 62404090010 0 60 TO61 162 User s Manual U15075EJ1V0UMO0 7 8 CRH60 Figure 7 21 Timing of Carrier Generator Operation Wh
137. ans NEC Corporation and also includes its majority owned subsidiaries 2 NEC semiconductor products means any semiconductor product developed or manufactured by or for NEC as defined above M8E 00 4 4 User s Manual U15075EJ1VOUMOO Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Te
138. apture register 16 bits x 1 TCP90 Timer outputs 1 090 Control registers 16 bit timer mode control register 90 TMC90 Buzzer output control register 90 BZC90 Port mode register 2 PM2 116 Users Manual U15075EJ1VOUMO0 CHAPTER 6 16 BIT snq euJeju S 2 4 06278 1 151 lonuoo jndjno aezzng M 4ejjnq peeJ 06421 06 Jejunoo 110 90 lejsiDaJ enjdeo 10 9 oye O d L8l L Od LNI 06d LO O6WL 06 48 UNOD 119 9 129 06079 O6IA LLNI 924 0601 1009125 uoneziuoJuouAS 10 99 8S 0680 06 E 0580 CL sa 119 91 10 99 9S 06301 00612111061210620 1006142 106142 06 01 062 1 06 1 15 14 9 snq S 19 91 Jo xoo g 71 9 4 1 117 User s Manual U15075EJ1VO0UMOO CHAPTER 6 16 1 16 bit compare register 90 CR90 A value specified in CR90 is compared with the count in 16 bit timer register 90 TM90 If they match an interrupt request INTTM90 is issued by CR90 90 is set with an 8 bit or 16 bit memory manipulation instruction Any value from 0000H to FFFFH can
139. are used as input port pins on chip pull up Output latch to Key return mode register 00 Pull up resistor option register 0 Port mode register Port 0 read signal Port 0 write signal User s Manual U15075EJ1VOUMOO POO KRO to 81 CHAPTER 4 PORT FUNCTIONS 4 2 2 Port 1 This is a 2 bit I O port with an output latch Port 1 can be specified in the input or output mode in 1 bit units by using port mode register 1 PM1 When using the P10 and P11 pins as input port pins on chip pull up resistors can be connected in 2 bit units by using pull up resistor option register 0 PUO This port is set in the input mode when the RESET signal is input Figure 4 4 shows a block diagram of port 1 Figure 4 4 Block Diagram of P10 and P11 WRPuo P10 P11 Selector WRP gt Ponr Internal bus Output latch 10 11 10 11 PUO Pull up resistor option register 0 PM Port mode register RD Port 1 read signal WR Port 1 write signal 82 User s Manual U15075EJ1V0UMO0 CHAPTER 4 PORT FUNCTIONS 4 2 3 Port 2 This is 7 bit port with an output latch Port 2 can be specified in the input or output mode in 1 bit units by using port mode register 2 PM2 When using the P20 to P26 pins as input port pins on chip pull up resistors can be connected in 1 bit units by using pull up resistor option register B2 PUB2 Th
140. ata If data where ADCSO is 0 is written to ADMO again during A D conversion A D conversion is stopped immediately Figure 11 6 Software Started A D Conversion Rewriting ADMO Overwriting ADMO ADCSO 1 ADCSO0 1 ADCS0 0 A D conversion discontinued no conversion Conversion is result is preserved INTADO Remarks 1 0105 2 0105 User s Manual U15075EJ1V0UMOO 205 CHAPTER 11 10 A D CONVERTER uPD789436 AND 789456 SUBSERIES 11 5 Cautions Related to 10 Bit A D Converter 1 Current consumption in standby mode In standby mode the A D converter stops operation Stopping conversion bit 7 ADCSO of A D converter mode register 0 ADMO 0 can reduce the current consumption Figure 11 7 shows how to reduce the current consumption in standby mode Figure 11 7 How to Reduce Current Consumption in Standby Mode 4 lt ADCS0 Series resistor string AVss 2 Inputrange for pins ANI0 to ANI5 Be sure to keep the input voltage at ANIO to ANI5 within the rating If a voltage not lower than or not higher than AVss even within the absolute maximum rating is input into a conversion channel the conversion output of the channel becomes undefined which may affect the conversion output of the other channels 3 Conflict 1 Conflict between writing to A D conversion result re
141. based application Use this software in the DOS prompt when running it on Windows Part number 78 05 Remark the part number differs depending on the host machines and operating systems to be used USXxxxMX78K0S AA13 PC 9800 series Japanese Windows 3 5 2HD FD IBM PC AT compatibles Japanese Windows 3 5 2HC FD English Windows Note Also operates under the DOS environment User s Manual U15075EJ1V0UMO0 315 316 User s Manual U15075EJ1VOUMOO APPENDIX REGISTER INDEX C 1 Register Index Alphabetic Order of Register Name A Analog input channel specification register 0 50 187 201 A D conversion result register 0 184 198 A D converter mode register 0 186 200 Asynchronous serial interface mode register 20 5 20 216 223 226 238 Asynchronous serial interface status register 20 51520 218 227 B Baud rate generator control register 20 20 219 228 239 Buzzer output control register 90 BZC90 sse nennen nennen nennen nens nnne nnne 121 C Carrier generator output control register 60 142 E 8 bit compare register 50 GRbO i un pedo de
142. become undefined if the timing of the completion of A D conversion and that to stop the A D conversion operation conflict Therefore read the A D conversion result while the A D conversion operation is in progress To read the A D conversion result after the A D conversion operation has been stopped stop the A D conversion operation before the next conversion operation is completed Figures 10 8 and 10 9 show the timing at which the conversion result is read Figure 10 8 Conversion Result Read Timing If Conversion Result Is Undefined End of A D conversion End of A D conversion ADCRO Normal conversion result Undefined value INTADO ADCSO Normal conversion result is read A D conversion Undefined value stops is read Figure 10 9 Conversion Result Read Timing If Conversion Result Is Normal End of A D conversion ADCRO X Normal conversion result INTADO ADCSO A D conversion stops Normal conversion result is read User s Manual U15075EJ1V0UMOO 193 6 7 8 194 CHAPTER 10 8 BIT A D CONVERTER uPD789426 AND 789446 SUBSERIES Noise prevention To maintain a resolution of 8 bits watch for noise to the AVop and ANIO to ANI5 pins The higher the output impedance of the analog input source the larger the effect by noise To reduce noise attach an external capacitor to the relevant pins as shown in Figure 10 10 Figure 10 10 Analog Input Pin Treatment If noise not lower than AVpp
143. bled Output enabled Notes 1 Since the count operation is controlled by 40 bit 7 of TMC40 in cascade connection mode any setting for is ignored 2 The selection of both edges is valid only in the PWM output mode In 8 bit counter mode or cascade connection mode counting is done using the rising edge even if 50 is set to 1 3 The operation mode selection is set to both the register and 40 register User s Manual U15075EJ1V0UMO0 139 CHAPTER 7 8 TIMER Cautions 1 In cascade connection mode the output signal of timer 60 is forcibly selected as the count clock 2 When operating 50 be sure to perform settings in the following order 1 Stop TM50 count operation 2 Set the operation mode and the count clock 3 Start count operation Remarks 1 fx Main system clock oscillation frequency ceramic crystal oscillation 2 fcc Main system clock oscillation frequency RC oscillation 2 8 bit timer mode control register 60 TMC60 8 bit timer mode control register 60 TMC60 is used to control the timer 60 count clock setting and the operation mode setting is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC60 to 00H 140 User s Manual U15075EJ1VO0UMOO 7 8 Figure 7 5 Format of 8 Bit Timer Mode Control Register 60 Symbol lt 7 gt lt 6 gt 5 4 3 2 0 Address After reset R W wc
144. by mode 15 acknowledged User s Manual U15075EJ1V0UMO0 285 CHAPTER 15 STANDBY FUNCTION b Releasing by RESET input When the STOP mode is released by the RESET signal the reset operation is performed after the oscillation stabilization time has elapsed Figure 15 5 Releasing STOP Mode by RESET Input STOP oo signal Oscillation Operation Reset stabilization Operation mode STOP mode period wait status mode Oscillation Clock Oscillation stops _ Oscillation Remark fx Main system clock oscillation frequency Table 15 4 Operation After Releasing STOP Mode Maskable interrupt request E c4 2 d Executes next address instruction x don t care 286 User s Manual U15075EJ1V0UMO0 CHAPTER 16 RESET FUNCTION The following two operations are available to generate reset signals 1 External reset input by RESET pin 2 Internal reset by watchdog timer runaway time detection External and internal reset have no functional differences In both cases program execution starts at the address at 0000H and 0001H by RESET input When a low level is input to the RESET pin or the watchdog timer overflows a reset is applied and each hardware is set to the status shown in Table 16 1 Each pin has a high impedance during reset input or during oscillation stabilization time just after reset clear When a high level is input to the RESET pin the reset is cleared and program execution is star
145. c tem esee Y Direct addressi FE1FH agaressing FD00H Register indirect FCFFH addressing Reserved FA05H FA04H Based addressing LCD display RAM 5 x 4 bits 00 F9FFH Reserved 4000H 3FFFH Internal ROM 16384 x 8 bits 0000H User s Manual U15075EJ1VOUMOO 3 Figure 3 9 Data Memory Addressing uPD78F9436 FFFFH Special function registers SFRs SFR add 256 x 8 bits 4 FFOOH FEFFH Internal high speed RAM ee 512 x 8 bits 9 FE20H FEIEH Direct addressing Pere Register indirect Reserved addressing FA04H Based addressing LCD display RAM 5 x 4 bits F9FFH Reserved 4000H 3FFFH Flash memory 16384 x 8 bits 0000H User s Manual U15075EJ1VOUMOO CHAPTER 3 CPU ARCHITECTURE Figure 3 10 Data Memory Addressing uPD789445 789455 FFFFH Special function registers SFRs SFR add 256 x 8 bits ORE ERR 215 FF1FH 00 h Internal high speed 4 512 x 8 bits Dir et dd 1 agaressing FD00H Register indirect FCFFH addressing Reserved FAOFH 2 FAOEH Based addressing LCD display RAM 15 x4 bits F9FFH Reserved 3000H 2FFFH Internal ROM 12288 x 8 bits 0000H Y User s Manual U15075EJ1VOUMOO
146. chdog timer is started Set RUN to 1 within the set runaway detection time interval after the watchdog timer has been started By setting RUN to 1 the watchdog timer can be cleared and start counting If RUN is not set to 1 and the runaway detection time is exceeded a system reset signal or a non maskable interrupt is generated depending on the value of bit 3 WDTMS of WDTM The watchdog timer continues operation in HALT mode but stops in STOP mode Therefore first set RUN to 1 to clear the watchdog timer before executing the STOP instruction Cautions 1 The actual runaway detection time may up to 0 8 shorter than the set time 2 When the subsystem clock is selected as the CPU clock the watchdog timer count operation is stopped Even when the main system clock continues oscillating in this case watchdog timer count operation is stopped Table 9 4 Watchdog Timer Runaway Detection Time WDCS2 WDCS1 WDCSO Runaway Detection Time At fx 2 5 0 MHz o o zh 41046 fx Main system clock oscillation frequency User s Manual U15075EJ1V0UMOO 181 CHAPTER 9 WATCHDOG TIMER 9 4 2 Operation as interval timer When bits 4 and 3 WDTM4 WDTM3 of the watchdog timer mode register WDTM are set to 0 and 1 respectively the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value Select a count clock or interval by setting bits 0 to 2 WDCSO to WDCS2
147. count value of 16 bit timer register 90 TM90 into a capture register in synchronization with a capture trigger and retaining the count value Set TMC90 as shown in Figure 6 9 to allow the 16 bit timer to start the capture operation Figure 6 9 Settings of 16 Bit Timer Mode Control Register 90 for Capture Operation TOD90 TOF90 CPT901 CPT900 90 1901 TCL900 TOE90 TMC90 OA Count clock selection Capture edge selection see Table 6 3 16 bit capture register 90 TCP90 starts a capture operation after a CPT90 capture trigger edge is detected and latches and retains the count value of 16 bit timer register 90 The 90 fetches the count value within 2 clocks and retains the count value until the next capture edge detection Table 6 3 and Figure 6 10 show the settings of the capture edge and the capture operation timing respectively Table 6 3 Settings of Capture Edge CPT901 CPT900 Capture Edge Selection 3 Capture operation prohibited Caution Because TCP90 is rewritten when a capture trigger edge is detected during TCP90 read disable the capture trigger edge detection during TCP90 read Figure 6 10 Capture Operation Timing Both Edges of CPT90 Pin Are Specified Count clock TM90 0000H 0001H Count read buffer 0000H X 0001H T T 1 TCP90 Undefined N Capture start Capture start CPT90 l Capture edge detection Capture edge detect
148. ctions The clock generator generates the clock to be supplied to the CPU and peripheral hardware The following two types of system clock oscillators are used Main system clock oscillator This circuit oscillates at 1 0 to 5 0 MHz Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register PCC Subsystem clock oscillator This circuit oscillates at 32 768 kHz Oscillation can be stopped by the suboscillation mode register SCKM 5 2 Clock Generator Configuration The clock generator includes the following hardware Table 5 1 Configuration of Clock Generator Control registers Processor clock control register PCC Suboscillation mode register SCKM Subclock control register CSS Oscillators Main system clock oscillator Subsystem clock oscillator User s Manual U15075EJ1V0UMO0 103 CHAPTER 5 CLOCK GENERATOR Figure 5 1 Block Diagram of Clock Generator Internal bus Suboscillation mode register SCKM 16 bit timer 90 8 bit timer 60 XT1 Subsystem clock gt Watch timer AIEO oscillator LCD controller driver Prescaler Ue Clock to peripheral fxt hardware X1 Main system oscillator Standby Wait CPU clock controller controller fcpu Selector CLS CSSO Subclock control register CSS Processor clock control register PCC Internal bus 104 User s Manual 1 15
149. d It is not subject to interrupt priority control and takes precedence over all other interrupts When the non maskable interrupt request is acknowledged PSW and PC are saved to the stack in that order the IE flag is reset to 0 the contents of the vector table are loaded to the PC and then program execution branches Figure 14 9 shows the flow from non maskable interrupt request generation to acknowledgement Figure 14 10 shows the timing of non maskable interrupt acknowledgement and Figure 14 11 shows the acknowledgement operation when a number of non maskable interrupts are generated Caution During non maskable interrupt service program execution do not input another non maskable interrupt request if it is input the service program will be interrupted and the new non maskable interrupt request will be acknowledged 272 User s Manual U15075EJ1V0UMO0 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14 9 Flow from Generation of Non Maskable Interrupt Request to Acknowledgment WDTMA 1 watchdog timer mode is selected E Yes WDT overflows Yes 0 non maskable interrupt is selected Yes Interrupt request is generated Interrupt servicing starts Interval timer Reset processing WDTM Watchdog timer mode register WDT Watchdog timer Figure 14 10 Timing of Non Maskable Interrupt Request Acknowledgment ing PSW and PC CPU processing Instruction Instruction Inter
150. d at FFOOH to FF1FH can also be accessed with short direct addressing Operand format Special function register name Description example MOV A When selecting PMO for sfr Instruction code 1 1 1 00 1 1 1 Illustration OP code sfr offset Effective Address User s Manual U15075EJ1VOUMOO 73 3 3 4 4 Register addressing Function In the register addressing mode general purpose registers are accessed as operands The general purpose register to be accessed is specified by a register specification code or functional name in the instruction code Register addressing is carried out when an instruction with the following operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format r and rp can be described with absolute names RO to R7 and RPO to RP3 as well as function names X A C BB E D L H AX BC DE and HL Description example MOV A C When selecting the C register for r Instruction code 1 0 0 O 1 00 O Register specification code INCW DE When selecting the DE register pair for rp Instruction code 0 0001 0 1 0 0 0 1 0 0 1 0 1 Register specification code 74 User s Manual 1 15075 1 00 00 3 3 4 5 Register indirect addressing Function In the register indirect
151. d by pull up resistor option register 0 PUO Port 2 Input 21 7 bit port _ I LE Input output can be specified in 1 bit units P22 When used as an input port an on chip pull up resistor 5520 23 can be specified by means of pull up resistor option register B2 PUB2 Port 3 4 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor INTP2 TO6O be specified by means of pull up resistor option INTP3 TO61 register PUB3 P50 to P53 Port 5 Input 4 bit port Input output can be specified in 1 bit units For a mask ROM version an on chip pull up resistor can be specified by a mask option P60 to P65 Input Port 6 Input to ANI5 6 bit input port P70 to P72 Port 7 Input 3 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register B7 PUB7 User s Manual U15075EJ1VOUMOO 79 CHAPTER 4 PORT FUNCTIONS Table 4 1 Port Functions 2 2 811 Port 8 Input 2 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register B8 8 P90 to P97 Port 9 Input 8 bit I O port Input output can be specified in 1 bit units When used as an input port an on
152. d into the following three quality grades Standard Special and Specific The Specific quality grade applies only to semiconductor products developed based on a customer designated quality assurance program for a specific application The recommended applications of a semiconductor product depend on its quality grade as indicated below Customers must check the quality grade of each semiconductor product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster Systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC semiconductor products is Standard unless otherwise expressly specified in NEC s data sheets or data books etc customers wish to use NEC semiconductor products in applications not intended by NEC they must contact an NEC sales representative in advance to determine NEC s willingness to support a given application Note 1 NEC as used in this statement me
153. d rate exceeds the rated range Users Manual U15075EJ1VOUMOO 229 CHAPTER 12 SERIAL INTERFACE 20 ii Generation of baud rate transmit receive clock from external clock input to ASCK20 pin The transmit receive clock is generated by scaling the clock input from the ASCK20 pin The baud rate of a clock generated from the clock input to the 20 pin is estimated by using the following expression _fasck Baud rate 46 _ Hz fasck Frequency of clock input to ASCK20 pin Table 12 6 Relationship Between ASCK20 Pin Input Frequency and Baud Rate When BRGC20 Is Set to 80H Baud Rate bps ASCK20 Pin Input Frequency kHz 38 400 614 4 230 User s Manual U15075EJ1V0UMOO CHAPTER 12 SERIAL INTERFACE 20 2 Communication operation a Data format The transmit receive data format is as shown in Figure 12 7 One data frame consists of a start bit character bits parity bit and stop bit s The specification of character bit length in one data frame parity selection and specification of stop bit length is carried out with asynchronous serial interface mode register 20 ASIM20 Figure 12 7 Format of Asynchronous Serial Interface Transmit Receive Data One data frame Stop bit e Start bits 1 bit e Character bits 7 bits 8 bits e Parity bits Even parity odd parity 0 parity no parity Stop bits 1 bit 2 bits When 7 bits are se
154. de ore ede cher 135 8 bit compare register 60 GBRO0 csetera en t et relate HER Eh E EE a er SE RE nu Er eer EROR 135 8 bit compare register H60 CRH60 135 8 bit timer counter 50 5 tor ette ae 136 8 bit timer counter 60 TMO0 rer ret irre RO RET Rae e ME LERRA Led geht rete Eg cd 136 8 bit timer mode control register 50 5 L 138 139 8 bit timer mode control register 60 TMC60 S 140 141 External interrupt mode register 0 0 2 269 External interrupt mode register 269 270 1 Interrupt mask flag register 0 1 268 Interrupt request flag register 0 1 267 Key return mode register 00 0 A 271 L LCD clock control register 0 LGDC0 u uiii ee itd rere au e e d 251 LCD display mode register O LCDM0 00 en nnns nnn enn snnt rens nnne 249 250 LCD voltage amplification control register O LCDVA0 00000 nnne 252 0 Oscillation stabilization time select register 0575 280 P Porto P0 i e pte I eti de
155. dge of SCK20 DIR20 First bit specification EN NN CSCK20 3 wire serial mode clock selection EN External clock input to the SCK20 pin Output of the dedicated baud rate generator CKP20 3 wire serial mode clock phase selection Clock is low active and 5 20 is at high level in the idle state Clock is high active and SCK20 is at low level in the idle state Cautions 1 Bits 4 and 5 must be set to 0 2 CSIM20 must be cleared to 00H if UART mode is selected Users Manual U15075EJ1VOUMOO 215 CHAPTER 12 SERIAL INTERFACE 20 2 Asynchronous serial interface mode register 20 ASIM20 ASIM20 is used to make the settings related to asynchronous serial interface mode ASIM20 is set with 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM20 to 00H Figure 12 4 Format of Asynchronous Serial Interface Mode Register 20 Symbol 7 6 5 4 3 Address After reset R W 2 1 0 ASIM20 CL20 520 o FF70H 00H R W TXE20 Transmit operation control EN Transmit operation stop Transmit operation enable RXE20 Receive operation control Receive operation stop Always add 0 parity at transmission Parity check is not performed at reception No parity error is generated Cautions 1 Bits 0 and 1 must be set to O 2 If 3 wire serial 1 mode is selected ASIM20 must be set to 00H 3 Switch operating modes after halting the serial transmit receive operation 216 Users Manual U15075EJ1VOUMOO
156. e a pulse of any duty ratio can be output by setting a low level width using CR60 and a high level width using CRH60 To operate timer 60 in PWM output mode settings must be made in the following sequence 1 2 3 4 5 6 lt 7 gt Disable operation of TM60 TCE60 0 Disable timer output of TO60 TOE60 0 Set count values in CR60 and CRH60 Set the operation mode of timer 60 to the PWM pulse generator mode see Figure 7 5 Set the count clock for timer 60 Set P32 to the output mode PM32 0 and the P32 output latch to 0 and enable timer output of TO60 TOE60 1 Enable the operation of TM60 TCE60 1 The operation in the PWM output mode is as follows 1 2 lt 3 gt lt 4 gt When the count value of TM60 matches the value CR6O an interrupt request signal INTTM60 is generated and output of timer 60 is inverted which makes the compare register switch from CR60 to CRH60 A match between TM60 and CR60 clears the TM60 value to 00H and then counting starts again After that when the count value of TM60 matches the value set in CRH60 an interrupt request signal 60 is generated and output of timer 60 is inverted again which makes the compare register switch from CRH60 to CR60 A match between TM60 and 60 clears the TM60 value to and then counting starts again A pulse of any duty ratio is output by repeating 1 to 4 above Figures
157. e ELI B np e p eee 81 User s Manual U15075EJ1VOUMOO 317 APPENDIX REGISTER INDEX Port 1 et ue depu 82 POPE2 P2 buen d eeu t et aliunde in tua i nM 83 Port 3 P9 iicet ie re ep Re te HO Lr e eL RE E ai ie Re Dau etn ede eeu 89 PORES RS PLE 91 Pott 6 PG be aiiud ad bim 92 ce E a 93 ordi 94 Port 9 P9 ani ce Era o E pco ee ee ee 95 Port mode register 0 PMO uu uu u uuu nter ie ee anie 96 97 Portmode register ret e e HERBAL E ERR 96 97 Port mode register 2 ER o E e EE e au HP RAE Cv dep c tUe dota 96 97 122 Port mode register 3 P k ua m a te u a usa Qhatu maaa ka oa 96 97 142 Port mode register 5 5 rer e n usuta e 96 97 Port mode register 7 PM7 96 97 Port znode register 9 P MB iet o nre eb eee utr te osi In UE u 96 97 Port mode register 9 iet pd E RR Hr DER ED tere ees 96 97 Processor clock control register rennen tenente 105 Pull up resistor option register 0 0 98 Pull up resistor option register B2 2 te sete nne I den 99 Pull up resistor option register
158. e No Title Page 14 7 Format of Key Return Mode Register 00 271 14 8 Block Diagram of Falling Edge 2 004044 0 271 14 9 Flow from Generation of Non Maskable Interrupt Request to Acknowledgmen t 273 14 10 Timing of Non Maskable Interrupt Request 273 14 11 Non Maskable Interrupt Request 273 14 12 Interrupt Request Acknowledgment Program 274 14 13 Interrupt Request Acknowledgment Timing Example eme 275 14 14 Interrupt Request Acknowledgment Timing When Interrupt Request Is Generated in Final Clock Under Execution u tnmen nen 275 14 15 Example of Mu ltiple Interrpts u 2 uuu rie dt e dre t oct 276 15 1 Format of Oscillation Stabilization Time Select Register 280 15 2 Releasing HALT Mode by 2 040 4 000000 a nennt enitn nein nnns 282 15 3 Releasing HALT Mode by RESET Input tnter tenentes 283 15 4 Releasing STOP Mode by Interrupt nenne tnnt Qa 285 15 5 Releasing STOP Mode by RESET Input nennen nennen nennen nennen nnne msn ens 286 16 1 Block Diagram of Reset Furctlon d ete
159. e Table 3 4 54 User s Manual U15075EJ1V0UMO0 CHAPTER 3 CPU ARCHITECTURE 3 1 4 Data memory addressing The uPD789426 789436 789446 and 789456 Subseries are provided with a variety of addressing modes to make memory manipulation as efficient as possible At the addresses corresponding to data memory area FDOOH to FFFFH especially specific addressing modes that correspond to the particular function an area such as the special function registers are available Figures 3 7 through 3 12 show the data memory addressing modes Figure 3 7 Data Memory Addressing uPD789425 789435 FFFFH Special function registers SFRs 256 x 8 bits SFR addressing FF20F2 mee osea ene so a rer T re Rm eee FF1FH i FFOOH FEFFH h Internal high speed RAM 512 x 8 bits i a Direct adressing FDOOH FCFFH Register indirect Reserved addressing 05 FA04H Based addressing LCD display RAM 5 x 4 bits F9FFH Reserved 3000H 2FFFH Internal ROM 12288 x 8 bits 0000H Y User s Manual U15075EJ1V0UM00 55 3 Figure 3 8 Data Memory Addressing uPD789426 789436 FFFFH Special function registers SFRs SFR addressi 256 x 8 bits acoressing O E OA 215 FF1FH FFOOH FEFFH h Internal high speed 4 512 x 8 bits 9 coed ee
160. e port is also used as the serial interface I O buzzer output and timer output This port is set in the input mode when the RESET signal is input Figures 4 5 to 4 10 show block diagrams of port 2 Caution When using the pins of port 2 as the serial interface the or output latch must be set according to the function to be used For how to set the latches see Figure 12 2 Settings of Serial Interface 20 Operating Mode Figure 4 5 Block Diagram of P20 Selector Internal bus Output latch P20 P20 ONS PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal User s Manual 015075 83 84 CHAPTER 4 PORT FUNCTIONS Figure 4 6 Block Diagram of P21 and P26 Selector O AE m2 eg NJ PUB21 PUB26 RD e 1 WRP gt Ponr 5 i E 3 WRem PM21 PM26 Alternate function UN PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal User s Manual U15075EJ1VOUMOO i 21 2090 P26 TO90 CHAPTER 4 PORT FUNCTIONS Figure 4 7 Block Diagram of P22 NJ WRru amp 2 PUB22 Alternate function RD 5 4 4 off Las o 4 o 2 a WR
161. ed values apply to operation at fx 5 0 MHz fxr 32 768 kHz 128 Users Manual U15075EJ1VOUMOO CHAPTER 6 16 BIT 6 5 Notes on Using 16 Bit Timer Usable functions differ according to the settings of the count clock selection CPU clock operation system clock oscillation status and BZOE90 bit 0 of buzzer output control register 90 BZC90 Refer to the following table CP 2 SystemClock Clock BZOE90 Capture TM90 Buzzer Timer Timer Stopped mL 80 Oscillating Stopped ee Oscillating Stopped STOP mode Stopped Notes 1 TM90 is enabled only when the CPU clock is in high speed mode 2 Output is enabled when BZOE90 1 Cautions 1 The capture function uses fx 2 for control refer to Figure 6 1 Block Diagram of 16 Bit Timer Therefore the capture function cannot be used when the main system clock is stopped 2 The read function of TM90 uses the CPU clock for control refer to Figure 6 1 and reads an undefined value when the CPU clock is slower than the count clock values are not guaranteed When reading TM90 set the count clock to the same speed as the CPU clock when the CPU clock is the main system clock high speed mode is set or select a clock slower than the CPU clock 3 When the subsystem clock is selected as the count clock and BZOE90 is set to 0 the subsystem clock selected as the TM90 count clock is one that has been synchronized with the main system clock refer to Fig
162. ee time slot mode So this bit can be used for purposes other than display LCD display data memory bits 4 to 7 are fixed to 0 3 Output waveforms of common and segment signals Voltages listed in Table 13 5 are output as common and segment signals When both common and segment signals are at the select voltage a display on voltage of Vicp is obtained The other combinations of the signals correspond to the display off voltage Table 13 5 LCD Drive Voltage Segment Signal Select Signal Level Deselect Signal Level 1 1 1 1 1 1 Deselect signal level cu Vico T3 254 User s Manual U15075EJ1VO0UMOO CHAPTER 13 LCD CONTROLLER DRIVER Figure 13 6 shows the common signal waveforms and Figure 13 7 shows the voltages and phases of the common and segment signals Figure 13 6 Common Signal Waveforms Hanc Sc M A veru Vico COMn T3 T3 1 pmx r r Vict V Vico at 1 LC2 Three time slot mode mm ss stss Vss 3 cc po ei rU eg ee E c eura Vico 4 Vict V Vico TT LC2 Four time slot mode Ye Vss T One LCD clock period Frame frequency Figure 13 7 Voltages and Phases of Common and Segment Signals Select Deselect Common signal Vico Segment signal T One LCD clock period User s Manual U15075EJ1V0UMO0 255 CHAPTER 13 LCD CONTROLLER DRIVER 13 7 Display Modes 13
163. en CR60 Count clock count value CR60 CRH60 TCE60 Count start INTTM60 Carrier clock Count pulse CR50 50 50 NRZB60 NRZ60 Carrier clock TO60 or TO61 163 User s Manual U15075EJ1VOUMOO 7 8 7 4 4 PWM free running mode operation timer 50 In the PWM free running mode TO50 becomes high level when 50 overflows and TO50 becomes low level when CR50 and TM50 match It is thus possible to output a pulse with any duty ratio To operate timer 50 in the PWM free running mode setting must be made in the following sequence 1 2 3 4 5 6 lt 7 gt Disable operation of TM50 50 0 Disable timer output of TO50 TOE50 0 Set a count value to CR50 Set the operation mode of timer 50 to the PWM free running mode see Figure 7 4 Set the count clock for timer 50 Set P31 to the output mode PM31 0 and the P31 output latch to 0 and enable timer output of 50 1 Enable the operation of TM50 5 1 The operation in the PWM free running mode is as follows 1 2 When the count value of TM50 matches the value set in CR50 an interrupt request signal INTTM50 is generated and low level is output by the TO50 The 50 continues counting without being cleared TO50 outputs a high level when the 50 overflows A pulse of any duty is output by repeati
164. en the BR addr16 instruction or a conditional branch instruction is executed Illustration 15 0 PC is the start address of PC the next instruction of a BR instruction 15 8 7 6 0 L ee jdisp8 15 0 When 0 indicates all bits 0 When 1 indicates all bits 1 68 User s Manual U15075EJ1V0UMO0 3 3 3 2 Immediate addressing Function Immediate data in the instruction word is transferred to the program counter PC and branched This function is carried out when the CALL addr16 or BR addr16 instruction is executed CALL addr16 and BR addr16 instructions can be branched to any location in the memory space Illustration In case of CALL addr16 and BR addr16 instructions 7 0 CALL or BR Low Addr High Addr 15 87 0 User s Manual U15075EJ1VOUMOO 69 3 3 3 3 Table indirect addressing Function Table contents branch destination address of the particular location to be addressed by the lower 5 bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter PC and branched This function is carried out when the CALLT addr5 instruction is executed The instruction enables a branch to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH Illustration 7 6 5 1 0
165. eo ceo vox ace missos rosso aw TCE60 Control of TM60 count operation Clears TM60 count value and stops operation the count value is also cleared for TM50 in cascade connection mode Starts count operation the count operation is also started for TM50 in cascade connection mode vocem rome Le o esm meea TMD501 TMD500 TMD601 TMD600 Selection of operation mode for timer 50 and timer 60 E Discrete mode 8 bit timer counter mode 1 Carrier generator mode 1 1 Timer 50 PWM free running mode Timer 60 PWM pulse generator mode Other than above Setting prohibited 2 Cascade connection mode 16 bit timer counter mode TOE61 TOE60 Control of timer output Output disabled Output enabled only for TO60 Output enabled only for TO61 Setting prohibited Notes 1 Since the count operation is controlled by 60 bit 7 of TMC60 in cascade connection mode any setting for TCE50 is ignored 2 The operation mode selection is set to both the TMC50 register and TMC60 register Caution When operating the 60 be sure to perform settings in the following order 1 Stop the TM60 count operation 2 Set the operation mode and the count clock 3 Start count operation Remarks 1 fx Main system clock oscillation frequency 2 The parenthesized values apply to operation at fx 5 0 MHz
166. er generator enne nnne en nennen rennen ener 160 7 4 4 free running mode operation timer 50 164 7 4 5 Operation as PWM output timer 60 168 7 5 Notes on Using 8 Bit Timer nenne nnnm nnne nan 170 CHAPTER 8 WATCH TIMER S cede cce ceder ca dot eta deos ie 171 8 1 Watch Timer Functions 2 n iiia neuen ede eel 171 8 2 Watch Timer Configuration a a u nn tasa inani nnn S 172 8 3 Watch Timer Control u u u 173 8 4 Watch 174 8 4 1 Operationi as Waltch 174 8 4 2 Operation as 174 CHAPTER 9 WATCHDOG nnn 177 91 Watchdog Timer Functions U U U u u uu uu uu u u u 177 9 2 Watchdog Timer Configuration U u u uu uuu u u u 178 9 3 Watchdog Timer Control Registers u u u u 179 User s Manual U15075EJ1V0UM00 13 9 4 Watchdog Timer Operation u
167. esponsibility for any errors that may appear in this document NEC does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of customer s equipment shall be done under the full responsibility of customer NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC semiconductor products are classifie
168. et Timing by RESET Input in STOP Mode NN STOP instruction execution During normal operation i Oscillation During normal Stop status ____ Reset period 4 stabilization Normal operation operation oscillation stops oscillation stops time wait reset processing 1 1 De su Pe in i Internal reset signal 1 1 288 User s Manual U15075EJ1V0UMO0 CHAPTER 16 RESET FUNCTION Table 16 1 Hardware Status After Reset 1 2 Program counter The contents of reset vector tables 0000H and 0001H are set MM Port P8 P9 Output latch Port mode register to PM3 5 PM7 ET Port mode register PM8 PM9 Pull up resistor option register PUO PUB2 PUB7 Pull up resistor option register PUB8 PUB9 suemereege Mode control register WTM 0 Serial interface Serial operation mode register CSIM20 Asynchronous serial interface mode register ASIM20 Baud rate generator control register BRGC20 Transmit shift register TXS20 FFH Receive buffer register RXB20 Undefined A D converter A D conversion result register ADCRO 0000H Analog input channel specification register ADSO Notes 1 During reset input and oscillation stabilization time wait only the PC contents among the hardware FH 00H 00H 2H OH 00H OH
169. ettings When Using Alternate Functions Alternate Function Pin Name PMxx Pxx ow o Dos ow Pos _ o Caution When port 2 is used as a serial interface pin the I O latch or output latch must be set according to its function For the setting method see Table 12 2 Settings of Serial Interface 20 Operating Mode Remark x don t care PMxx Port mode register Pxx Port output latch 2 Pull up resistor option register 0 PUO Pull up resistor option register 0 PUO sets whether on chip pull up registers are used on ports 0 and 1 or not On the port specified to use an on chip pull up resistor by PUO the pull up resistor can be internally used only for the bits set in the input mode No on chip pull up resistors can be used for the bits set in the output mode regardless of the setting of PUO This also applies to cases when the pins are used for alternate functions PUO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PUO to 00H Figure 4 19 Format of Pull Up Resistor Option Register 0 Symbol 7 6 5 4 3 2 lt gt 0 Address After reset R W ew o Pm on chip pull up resistor selection m 0 1 ES On chip pull up resistor not used On chip pull up resistor used Caution Bits 2 to 7 must be set to 0 98 User s Manual U15075EJ1V0UMO0 CHAPTER 4 PORT FUNCTIONS 3 Pull up resistor option register B2 PUB
170. f 16 bit timer 90 INTP0 to INTP3 These are external interrupt input pins for which valid edges rising edge falling edge or both rising and falling edges can be specified 2 2 5 P50 to P53 Port 5 These pins function as 4 bit N ch open drain I O port Port 5 can be set in the input or output port mode in 1 bit units by port mode register 5 PM5 In the mask ROM version use of an on chip pull up resistor can be specified by a mask option 2 2 6 P60 to P65 Port 6 This is a 6 bit input only port In addition to a general purpose input port function it has an A D converter input function 1 In this mode P60 to P65 function as 6 bit input only port 2 Control mode In this mode P60 to P65 function as analog inputs to of A D converter User s Manual U15075EJ1V0UMO0 41 CHAPTER 2 PIN FUNCTIONS 2 2 7 P70 to P72 Port 7 These pins constitute a 3 bit I O port Port 7 can be set in the input or output mode 1 bit units by port mode register 7 PM7 When used as an input port use of an on chip pull up resistor can be specified by pull up resistor option register B7 PUB7 in port units 2 2 8 P80 P81 Port 8 These pins constitute a 2 bit I O port Port 8 can be set in the input or output mode 1 bit units by port mode register 8 PM8 When used as an input port use of an on chip pull up resistor can be specified by pull up resistor option register B8 8 in port un
171. functions using the following organization Two manuals are available for the 789426 789436 789446 and 789456 Subseries This manual and the instruction manual common to the 78K 0S Series 789426 789436 789446 78 05 and 789456 Subseries User s Manual User s Manual Instructions e Pin functions e CPU function e Internal block functions e Instruction set Interrupts e Instruction description Other internal peripheral functions It is assumed that the readers of this manual have general knowledge of electrical engineering logic circuits and microcontrollers e To understand the overall functions of the 789426 789436 789446 789456 Subseries Read this manual in the order of the CONTENTS How to read register formats The name of a bit whose number is enclosed in brackets is reserved for the assembler and is defined for the C compiler by the header file sfrbit h To learn the detailed functions of a register whose register name is known See APPENDIX C REGISTER INDEX To learn the details of the instruction functions of the 78K 0S series Refer to 78K 0S Series Instructions User s Manual U11047E separately available User s Manual U15075EJ1VOUMOO 7 Conventions Data significance Higher digits on the left and lower digits on the right Active low representation overscore over pin or signal name Note Footnote for item marked with Note in the text Caut
172. g timer has the following functions Watchdog timer nterval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register WDTM 1 Watchdog timer The watchdog timer is used to detect a program runaway When a runaway is detected a non maskable interrupt or the RESET signal can be generated Table 9 1 Watchdog Timer Runaway Detection Time Runaway Detection Time At fx 2 5 0 MHz 2 x 1 fx 410 us fx Main system clock oscillation frequency 2 Interval timer The interval timer generates an interrupt at an arbitrary preset interval Table 9 2 Interval Time 2 x 1 fx 410 us fx Main system clock oscillation frequency User s Manual U15075EJ1V0UMOO 177 CHAPTER 9 WATCHDOG TIMER 9 2 Watchdog Timer Configuration The watchdog timer includes the following hardware Table 9 3 Configuration of Watchdog Timer Control registers Watchdog timer clock select register WDCS Watchdog timer mode register WDTM Figure 9 1 Block Diagram of Watchdog Timer C Internal bus C Controller TCL22 TCL21 TCL20 WDTM4 WDTM3 Watchdog timer clock select register WDCS Watchdog timer mode register WDTM C Internal bus C fx 24 INTWDT Maskable interrupt request RESET INTWDT Non maskable interrupt request 7 bit counter Clear Selector 178 Users Manual U15075E
173. gister 0 ADCRO at the end of conversion and reading from ADCRO using instruction Reading from ADCRO takes precedence After reading the new conversion result is written to ADCRO 2 Conflict between writing to ADCRO at the end of conversion and writing to A D converter mode register 0 ADMO or analog input channel specification register 0 ADSO Writing to ADMO or ADSO takes precedence ADCRO is not written to No A D conversion end interrupt request signal INTADO is generated 4 Conversion result immediately after start of A D conversion The first A D conversion value immediately after A D conversion has been started is undefined Poll the A D conversion end interrupt request INTADO and drop the first conversion result 206 User s Manual U15075EJ1V0UMOO CHAPTER 11 10 A D CONVERTER uPD789436 AND 789456 SUBSERIES 5 Timing of undefined A D conversion result The A D conversion value may become undefined if the timing of the completion of A D conversion and that to stop the A D conversion operation conflict Therefore read the A D conversion result while the A D conversion operation is in progress To read the A D conversion result after the A D conversion operation has been stopped stop the A D conversion operation before the next conversion operation is completed Figures 11 8 and 11 9 show the timing at which the conversion result is read Figure 11 8 Conversion Result Read Timing If Conversion Result Is Undefined
174. hable between MSB first and LSB first transmission This mode is used to transmit 8 bit data using three lines a serial clock SCK20 line and two serial data lines SI20 and SO20 As it supports simultaneous transmission and reception 3 wire serial mode requires less processing time for data transmission than asynchronous serial interface mode Because in 3 wire serial mode it is possible to select whether 8 bit data transmission begins with the MSB or LSB serial interface 20 can be connected to any device regardless of whether that device is designed for MSB first or LSB first transmission 3 wire serial mode is useful for connecting peripheral circuits and display controllers having conventional synchronous serial interfaces such as those of the 75XL 78K and 17K Series devices 12 2 Serial Interface 20 Configuration Serial interface 20 includes the following hardware Table 12 1 Configuration of Serial Interface 20 Registers Transmission shift register 20 TXS20 Reception shift register 20 RXS20 Reception buffer register 20 RXB20 Control registers Serial operation mode register 20 CSIM20 Asynchronous serial interface mode register 20 ASIM20 Asynchronous serial interface status register 20 ASIS20 Baud rate generator control register 20 BRGC20 User s Manual U15075EJ1V0UMOO 211 CHAPTER 12 SERIAL INTERFACE 20 ayes pneq y jo y JO Z Z
175. hannel specification register 0 ADSO The voltage supplied to the selected analog input channel is sampled using the sample amp hold circuit After sampling continues for a certain period of time the sample amp hold circuit is put on hold to keep the input analog voltage until A D conversion is completed Bit 7 of the successive approximation register SAR is set The series resistor string tap voltage at the tap selector is set to half of AVpp The series resistor string tap voltage is compared with the analog input voltage using the voltage comparator If the analog input voltage is higher than half of AVpp the MSB of is left set If it is lower than half of AVpp the MSB is reset Bit 6 of SAR is set automatically and comparison shifts to the next stage The next tap voltage of the series resistor string is selected according to bit 7 which reflects the previous comparison result as follows e Bit 7 1 Three quarters of Bit 7 0 One quarter of The tap voltage is compared with the analog input voltage Bit 6 is set or reset according to the result of comparison e Analog input voltage gt tap voltage Bit 6 1 e Analog input voltage lt tap voltage Bit 6 0 Comparison is repeated until bit O of SAR is reached When comparison is completed for all of the 8 bits a significant digital result is left in SAR This value is sent to and latched in A D conversion result register 0 ADCRO At the same t
176. he ASCK20 pin a Generation of baud rate transmit receive clock form system clock The transmit receive clock is generated by scaling the system clock The baud rate of a clock generated from the system clock is estimated by using the following expression Baud rate fx Main system clock oscillation frequency n Values in Figure 12 6 determined by the values of TPS200 to TPS203 2 lt lt 8 Table 12 3 Example of Relationships Between System Clock and Baud Rate Baud Rate bps BRGC20 Set Value Error 96 fx 2 5 0 MHz fx 2 4 9152 MHz Caution Do not select n 1 during operation at fx 5 0 MHz because the resulting baud rate exceeds the rated range 220 Users Manual U15075EJ1VOUMOO CHAPTER 12 SERIAL INTERFACE 20 b Generation of baud rate transmit receive clock from external clock input to ASCK20 pin The transmit receive clock is generated by scaling the clock input from the ASCK20 pin The baud rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following expression Baud rate Hz fasck Frequency of clock input to the ASCK20 Table 12 4 Relationship Between ASCK20 Pin Input Frequency and Baud Rate When BRGC20 Is Set to 80H Baud Rate bps 20 Pin Input Frequency kHz 38 400 614 4 Users Manual U15075EJ1VOUMOO 221 CHAPTER 12 SERIAL INTERFACE 20 12 4 Serial Interface 20 Operation Serial interface 20 provides the following three modes
177. he contents of the display data memory addresses to FAOEH correspond to this display The following description focuses on numeral 6 displayed in the seventh digit To display 6 in the LCD panel it is necessary to apply the select or deselect voltage to the S2 and S3 pins according to Table 13 7 at the timing of the common signals COMO to Table 13 7 Select and Deselect Voltages COMO to According to Table 13 7 it is determined that the display data memory location 2 that corresponds to S2 must contain 1101 Figure 13 13 shows examples of LCD drive waveforms between the S2 signal and the COMO or COM signal the waveforms for COM2 and COMG have been left out from the drawing When the select voltage is applied to S2 at the timing of COMO an alternate rectangle waveform is generated to turn on the corresponding LCD segment Figure 13 11 Four Time Slot LCD Display Pattern and Electrode Connections S gt COM0 COM1 COM2 V Son Remark 0 7 User s Manual U15075EJ1V0UMO0 259 260 Data memory address CHAPTER 13 LCD CONTROLLER DRIVER Figure 13 12 Example of Connecting Four Time Slot LCD Panel Timing strobe DOAN DA KRW User s Manual U15075EJ1VOUMOO LCD panel CHAPTER 13 LCD CONTROLLER DRIVER Figure 13 13
178. he serial clock for serial interface 20 BRGC20 is set with an 8 bit memory manipulation instruction RESET input sets BRGC20 to 00H Figure 12 6 Format of Baud Rate Generator Control Register 20 Symbol 7 6 5 4 3 Address After reset R W 2 4 0 BRGC20 FF73H 00H R W pem _ j eeek 1 tr wos mus DOCU RN Other than above Setting prohibited Note An external clock can be used only in UART mode Cautions 1 When writing to BRGCOO during a communication operation the output of the baud rate generator is disrupted and communications cannot be performed normally Be sure not to write to BRGC00 during a communication operation 2 Be sure not to select n z 1 during operation at fx z 5 0 MHz because the resulting baud rate exceeds the rated range 3 When the external input clock is selected set port mode register 2 PM2 to input mode Remarks 1 fx Main system clock oscillation frequency 2 n Values determined by the settings of TPS200 to 203 1 lt n lt 8 3 The parenthesized values apply to operation at fx 2 5 0 MHz User s Manual U15075EJ1VO0UMOO 219 CHAPTER 12 SERIAL INTERFACE 20 The baud rate transmit receive clock to be generated is either a signal scaled from the system clock or a signal scaled from the clock input to t
179. ime it is possible to generate an A D conversion end interrupt request INTADO Cautions 1 The first A D conversion value immediately after A D conversion has been started may be 188 undefined 2 In standby mode A D converter operation is stopped User s Manual U15075EJ1VO0UMOO CHAPTER 10 8 BIT A D CONVERTER uPD789426 AND 789446 SUBSERIES Figure 10 4 Basic Operation of 8 Bit A D Converter Conversion a time Sampling time A D converter operation Sampling A D conversion Conversion SAR Undefined result Conversion result INTADO A D conversion continues until bit 7 ADCSO of A D converter mode register 0 ADMO is reset 0 by software If an attempt is made to write to ADMO or analog input channel specification register 0 ADSO during A D conversion the ongoing A D conversion is canceled In this case A D conversion is restarted from the beginning if ADCSO is set 1 RESET input makes A D conversion result register 0 ADCRO undefined ADCRO 10 4 2 Input voltage and conversion result The relationships between the analog input voltage at the analog input pins ANIO to ANI5 and the A D conversion result A D conversion result register 0 ADCRO are represented by ADCRO INT x 256 0 5 or ADCR0 0 5 x Pt lt Vin lt ADCRO 0 5 x ES Function that returns the integer part of a parenthesized value Analog i
180. imer output set the PM32 and P32 output latch to 0 When using the P33 TO61 INTP3 pin as a timer output set the PM33 and P33 output latch to 0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets to FFH Figure 7 7 Format of Port Mode Register 3 Symbol 7 6 Address After reset R W 5 4 3 2 1 0 1 PM33 PM32 1 FF23H FFH R W mode of P3n pin n 0 to 3 Output mode output buffer is ON 1 Input mode output buffer is OFF 142 User s Manual U15075EJ1VO0UMOO 7 8 7 4 8 Bit Timer Operation 7 4 1 Operation as 8 bit timer counter Timer 50 and timer 60 can be independently used as 8 bit timer counters The following modes can be used for the 8 bit timer counter e Interval timer with 8 bit resolution e External event counter with 8 bit resolution timer 60 only Square wave output with 8 bit resolution 1 Operation as interval timer with 8 bit resolution The interval timer with 8 bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset 8 bit compare register CRnO To operate 8 bit timer nO as an interval timer settings must be made in the following sequence 1 2 lt 3 gt lt 4 gt lt 5 gt lt 6 gt Disable operation of 8 bit timer counter 0 Disable timer output of 0 TOEnO 0 Set a count value in
181. iming CPU clock De E re e b HE E SEU T dsl Count clock TMo Comes Read signal latch prohibited period User s Manual U15075EJ1V0UMOO 127 CHAPTER 6 16 BIT 6 4 5 Buzzer output operation The buzzer frequency is set using buzzer output control register 90 BZC90 based on the count clock selected with TCL901 and TCL900 of TMC90 source clock A square wave of the set buzzer frequency is output Table 6 4 shows the buzzer frequency Set the 16 bit timer as follows to use it for buzzer output Set P21 to output mode PM21 0 e Reset output latch of P21 to 0 e Set a count clock using TCL901 and TCL900 Set BZC90 as shown in Figure 6 12 Figure 6 12 Settings of Buzzer Output Control Register 90 for Buzzer Output Operation BCS902 BCS901 BCS900 BZOE90 o Enables buzzer output Setting of buzzer frequency see Table 6 4 Table 6 4 Buzzer Frequency of 16 Bit Timer BCS902 BCS901 BCS900 Buzzer Frequency fcl 2 1 22 kHz fcl 2 76 Hz fcl 2 38 Hz 2 32 Hz fcl 2 610 Hz fcl 2 38 Hz fcl 2 19 Hz 2 16 Hz EARTEN fcl 2 305 Hz fcl 2 19 Hz fcl 2 10 Hz fcl 2 8 Hz fcl 2 153 Hz fcl 2 10 Hz fcl 2 5 Hz fcl 2 4 Hz Remarks 1 fx Main system clock oscillation frequency 2 Subsystem clock oscillation frequency 3 The parenthesiz
182. ination with optional device file DF789456 Caution when used under PC environment gt The assembler package is a DOS based application but may be used under the Windows environment by using Project Manager of Windows included in the assembler package Part number 78 05 78 05 Program that converts program written C language into object codes that be C compiler package executed by microcontroller Used in combination with optional assembler package RA78KOS and device file 0 789316 Caution when used under PC environment The C compiler package is a DOS based application but may be used under the Windows environment by using Project Manager of Windows included in the assembler package Part number wSxxxxCC78K0S DF789456 File containing the information inherent to the device Device file Used in combination with optional RA78K0S 78 05 and SM78KO0S Part number uSxxxxDF789456 CC78K0S L Source file of functions for generating object library included in C compiler package C compiler source file Necessary for changing object library included in C compiler package according to customer s specifications Since this is a source file its working environment does not depend on any particular operating system Part number wSxxxxCC78K0S L Note DF789456 is common file that can be used RA78KOS CC78KOS and 5 78 05 Remark the part number differs depending o
183. ion 126 User s Manual U15075EJ1VOUMOO CHAPTER 6 16 BIT 6 4 4 16 bit timer counter 90 readout The count value of 16 bit timer counter 90 TM90 is read out using a 16 bit manipulation instruction TM90 readout is performed through a counter read buffer The counter read buffer latches the TM90 count value and the buffer operation is held pending at the CPU clock falling edge after the read signal of the TM90 lower byte rises and the count value is retained The retained counter read buffer value can be read out as the count value Cancellation of the pending state is performed at the CPU clock falling edge after the read signal of the TM90 higher byte falls RESET input sets TM90 to 0000H and 90 starts freerunning Figure 6 11 shows the timing of 16 bit timer counter 90 readout Cautions 1 The count value after releasing stop becomes undefined because the count operation is executed during the oscillation stabilization time 2 Though 90 is designed for a 16 bit transfer instruction an 8 bit transfer instruction can also be used When using an 8 bit transfer instruction execute it by direct addressing 3 When using an 8 bit transfer instruction execute in the order from lower byte to higher byte in pairs If only the lower byte is read the pending state of the counter read buffer is not canceled and if only the higher byte is read an undefined count value is read Figure 6 11 16 Bit Timer Counter 90 Readout T
184. ion Information requiring particular attention Remark Supplementary information Numerical representation Binary xxxx or xxxxB Decimal Xxxx Hexadecimal xxxxH Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Documents Related to Devices Document No LP D789425 789426 789435 789436 789445 789446 789455 789456 014493 U14493E Preliminary Product Information Documents Related to Development Tools User s Manuals Document No RA78KOS Assembler Package U11622J U11622E Assembly Language U11599J U11599E Structured Assembly U11623J U11623E ee CC78K 0S C Compiler Operation U11816E 5 78 05 SM78KO0 System Simulator Ver 2 10 or Later Operation U14611J To be prepared Windows Based SM78K Series System Simulator External Part User Open U10092J U10092E Interface ID78KOS NS ID78KOS NS Integrated Debugger Windows Based Debugger Windows Based Reference 612900 lume ID78K0 NS ID78KOS NS Integrated Debugger 2 20 Operation U14910J To be prepared or Later Windows Based IE 78KOS NS 013549 3549 13549 3549 IE 789456 NS EM1 To be prepared To be prepared Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document for designing 8 User s Manual U15075EJ1VOUMOO Docume
185. ions An 8 bit timer one channel timer 50 and an 8 bit timer event counter one channel timer 60 are incorporated in the uPD789426 789436 799446 789456 Subseries The operation modes listed in the following table can be set via mode register settings Table 7 1 Operation Modes Pa a 8 bit timer counter mode Available Available Discrete mode 16 bit timer counter mode Available Cascade connection mode Carrier generator mode Available PWM output mode Available Available Free running mode Pulse generator mode 1 8 bit timer counter mode discrete mode The following functions can be used in this mode Interval timer with 8 bit resolution External event counter with 8 bit resolution timer 40 only Square wave output with 8 bit resolution 2 16 bit timer counter mode cascade connection mode Operation as a 16 bit timer event counter is enabled during cascade connection mode The following functions can be used in this mode e Interval timer with 16 bit resolution e External event counter with 16 bit resolution Square wave output with 16 bit resolution 3 Carrier generator mode The carrier clock generated by timer 60 is output in cycles set by timer 50 4 PWM output mode a Timer 50 Free running mode The timer output status inverts repeatedly due to a match between TM50 and CR50 and 50 overflow and pulses of any duty ratio are output User s Manual U15075EJ1
186. ipulation instruction but cannot be read RESET input sets TXS20 to FFH Caution Do not write to TXS20 during transmission TXS20 and reception buffer register 20 RXB20 are mapped at the same address such that any attempt to read from TXS20 results in a value being read from RXB20 Reception shift register 20 RXS20 RXS20 is register in which serial data received at the RxD20 pin is converted to parallel data Once one entire byte has been received RXS20 feeds the reception data to reception buffer register 20 RXB20 RXS20 cannot be manipulated directly by a program Reception buffer register 20 RXB20 RXB20 holds a reception data A new reception data is transferred from reception shift register 20 RXS20 every 1 byte data reception When the data length is seven bits the reception data is sent to bits 0 to 6 of RXB20 in which the MSB 15 always fixed to 0 RXB20 can be read with an 8 bit memory manipulation instruction but cannot be written RESET input makes RXB20 undefined Caution RXB20 and transmission shift register 20 TXS20 are mapped at the same address such that any attempt to write to RXB20 results in a value being written to TXS20 Transmission controller The transmission controller controls transmission For example it adds start parity and stop bits to the data in transmission shift register 20 TXS20 according to the setting of asynchronous serial interface mode register 20 ASIM20 Reception co
187. ister 20 e arsusa aqa hasa Cai kalah apa kasuy Quds d exe tuin chua dosa 214 Suboscillation mode U U u a a al h asun nne 106 Carrier generator output control register 60 L L nennen nnne nen 142 16 bit Capture register 90_ u te ever Soc uer eines 118 amp bititimer Counter 50 ERR ce taies bee etta 136 8 bit tirer counter GOs set EC ed EH o e E eU e E ue ve 136 16 bit timer counter t EE 118 8 bit timer mode control register 50 138 139 8 bit timer mode control register 60 140 141 16 bit timer mode control register 90 0 ens 119 120 Transmit shittiregister 20 5 oen eee e bei pie p e EE inae 214 Watchdog timer clock select register 4040 u u nnne nennen nnn 179 Watchdog timer mode uu nennen 180 Watch timer mode control register 4 44 173 User s Manual U15075EJ1VOUMOO Although NEC has taken possible steps essage to ensure thatthe documentation supplied to our customers is complete bug free and up to date we readily accept that From errors may occur Despite all care and precautions we ve taken you may
188. ister PCC User s Manual 015075 305 CHAPTER 19 INSTRUCTION SET 19 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP INC DEC ROR ROL RORC ROLC PUSH POP DBNZ 2nd Operand byte saddr 6 PSW DE HL HL byte addr16 None 1st Operand Note Exceptr A 306 User s Manual U15075EJ1V0UMO0 CHAPTER 19 INSTRUCTION SET 2 16 bit instructions MOVW XCHW ADDW SUBW CMPW PUSH POP INCW DECW 2nd Operand word saddrp None 1st Operand ADDW MOVW MOVW MOVW SUBW XCHW CMPW u 111 Note Only when DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd Operand addr16 None 1st Operand A bit BT SET1 BF CLR1 sfr bit BT SET1 BF CLR1 sadar bit BT CLR1 PSW bit BT CLR1 HL bit CLR1 User s Manual U15075EJ1VOUMOO 307 CHAPTER 19 INSTRUCTION SET 4 Call instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd Operand laddr16 addr5 addr16 1st Operand Basic Instructions TH Sag CALLT 5 Other instructions RET RETI El DI HALT STOP 308 User s Manual U15075EJ1V0UMO0 APPENDIX DEVELOPMENT TOOLS The following development tools are available for development of systems using the 789426 789436 789446 and 789456 Subseries Figure A 1 shows development tools Sup
189. its Note Only the 789426 and uPD789436 Subseries 2 2 9 P90 to P97 Port 9 These pins constitute an 8 bit I O port Port 9 can be set in the input or output mode in 1 bit units by port mode register 9 PM9 When used as an input port use of an on chip pull up resistor can be specified by pull up resistor option register B9 PUB9 in port units Note Only the uPD789426 and uPD789436 Subseries 2 2 10 50 to 514 These pins are segment signal output pins for the LCD controller driver Note 50 to S4 in the case of the 789426 and 789436 Subseries 2 2 11 COMO to COM3 These pins are common signal output pins for the LCD controller driver 2 2 12 Vico to Vic2 These pins are power supply voltage pins to drive the LCD 2 2 13 CAPH CAPL These pins are capacitor connection pins to drive the LCD 2 2 14 RESET This pin inputs an active low system reset signal 2 2 15 X1 X2 These pins are used to connect a crystal resonator for main system clock oscillation To supply an external clock input the clock to X1 and input the inverted signal to X2 2 2 16 XT1 XT2 These pins are used to connect a crystal resonator for subsystem clock oscillation To supply an external clock input the clock to XT1 and input the inverted signal to XT2 42 User s Manual U15075EJ1VOUMOO CHAPTER 2 PIN FUNCTIONS 2 2 17 This is the positive power supply pin 2 2 18 Vss This is the ground pin 2 2 19 VPP uPD7
190. k memory The program counter program status word and stack pointer are control registers 1 Program counter PC The program counter is a 16 bit register that holds the address information of the next program to be executed In normal operation the PC is automatically incremented according to the number of bytes of the instruction to be fetched When a branch instruction is executed immediate data or register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 13 Program Counter Configuration 15 0 PC 2 Program status word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruction execution The program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions RESET input sets PSW to 02H Figure 3 14 Program Status Word Configuration 7 0 5 User s Manual U15075EJ1VOUMOO 61 62 b c d CHAPTER 3 CPU ARCHITECTURE Interrupt enable flag IE This flag controls interrupt request acknowledgement operations of the CPU When 0 IE is set to the interrupt disable status DI and interrupt requests other than non maskable interrupt are all disabled When 1 IE is set to the interrupt enable status El Interrupt re
191. kus pansa ut e cd io tet e phe deve eee 292 17 3 Functions of Flash Memory 293 17 4 Example of Settings for PG F P9 ice e greed oet qr eig TE 295 18 1 Selection of Mask Option for Ping concentrer edge nest ayasa 297 19 1 Operand Identifiers and Description 0 299 User s Manual U15075EJ1V0UMO0 23 24 User s Manual U15075EJ1VOUMOO CHAPTER 1 GENERAL 1 1 Features ROM and RAM capacities Program Memory Data Memory ROM Internal High Speed LCD Display RAM RAM Mask ROM 512 bytes 5 bytes 16 KB Flash memory 16 KB uPD789445 789455 Mask ROM 12 KB 15 bytes 789446 789456 16 KB 78 9456 Flash memory Minimum instruction execution time can be changed from high speed 0 4 us 5 0 MHz operation with main System clock to ultra low speed 122 us 32 768 kHz operation with subsystem clock e ports 40 uPD789426 789436 Subseries 30 uPD789446 789456 Subseries Timer 5 channels 16 bit timer 1 channel e 8 bit timer 2 channels Watch timer 1 channel e Watchdog timer 1 channel A D converter 8 bit resolution 6 channels uPD789426 789446 Subseries 10 bit resolution 6 channels uPD789436 789456 Subseries Serial interface 1 channel LCD controller driver Segment signals 5 common signals 4 uPD789426 789436 Subseries Segment sign
192. l 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Madrid Office Madrid Spain Tel 91 504 2787 Fax 91 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 User s Manual U15075EJ1VOUMOO NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd United Square Singapore Tel 65 253 8311 Fax 65 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC do Brasil S A Electron Devices Division Guarulhos SP Brasil Tel 55 11 6462 6810 Fax 55 11 6462 6829 J00 7 6 User s Manual U15075EJ1VOUMOO Target Readers Purpose Organization How to Use This Manual INTRODUCTION This manual is intended to give user engineers an understanding of the functions of the 789426 789436 789446 and 789456 Subseries to design and develop its application systems and programs Target products e uPD789426 Subseries 789425 789426 e uPD789436 Subseries 789435 789436 e uPD789446 Subseries 789445 789446 e uPD789456 Subseries 789455 789456 This manual is designed to deepen your understanding of the following
193. le area 0040H 0022H 0021H 0000H Vector table area User s Manual U15075EJ1VOUMOO 51 52 FFFFH FF00H FEFFH FD00H FCFFH F9FFH 4000H CHAPTER 3 CPU ARCHITECTURE Figure 3 6 Memory Map uPD78F9456 Special function registers 256 x 8 bits Internal high speed RAM 512 x 8 bits Reserved LCD display RAM 15 x 4 bits Reserved memo i 3FFFH Program ry space 0000H Flash memory 16384 x 8 bits 3FFFH Program area 0080H 007FH CALLT table area 0040H 003FH Program area 0022H 0021H 0000H Vector table area User s Manual U15075EJ1VOUMOO 3 3 1 1 Internal program memory space The internal program memory space stores programs and table data This space is usually addressed by the program counter PC The uPD789426 789436 789446 and 789456 Subseries provide internal ROM or flash memory with the following capacity for each product Table 3 1 Internal ROM Capacity Part Number Internal ROM 0789425 789435 Mask ROM 12288 x 8 bits 789445 789455 789426 789436 16384 x 8 bits 789446 789456 UPD78F9436 78F9456 Flash memory 16384 x 8 bits The following areas are allocated to the internal program memory space
194. lected as the number of character bits only the lower 7 bits bits 0 to 6 are valid in transmission the most significant bit bit 7 is ignored and in reception the most significant bit bit 7 is always 0 The serial transfer rate is selected by ASIM20 and baud rate generator control register 20 BRGC20 If a serial data receive error occurs the receive error contents can be determined by reading the status of asynchronous serial interface status register 20 ASIS20 Users Manual U15075EJ1V0UM00 231 232 CHAPTER 12 SERIAL INTERFACE 20 b Parity types and operation The parity bit is used to detect a bit error in the communication data Normally the same kind of parity bit is used on the transmitting side and the receiving side With even parity and odd parity a one bit odd number error can be detected With O parity and no parity an error cannot be detected i Even parity e At transmission The parity bit is determined so that the number of bits with a value of 1 in the transmit data including the parity bit may be even The parity bit value should be as follows The number of bits with a value of 1 is an odd number in transmit data 1 The number of bits with a value of 1 is an even number in transmit data 0 e At reception The number of bits with a value of 1 in the receive data including parity bit is counted and if the number is odd a parity error occurs ii Odd parity e At transmission
195. lt Is 193 10 10 Analog Input Pin Treatment u u u uuu u tenen tnter Ite ene tr 194 10 11 Conversion End Interrupt Request Generation 195 10 12 AVpr Pin Elandling oce tee a ede cs 195 11 1 Block Diagram of 10 Bit A D Converter nennen nennen rennen nennen nennen ns 198 11 2 Format of A D Converter Mode Register 0 nennen nennen nennen nennen ns 200 11 3 Format of Analog Input Channel Specification Register 0 224000000 201 11 4 Basic Operation of 10 Bit A D 0 00 nennen enne enne 203 User s Manual U15075EJ1VOUMOO 19 20 LIST FIGURES 4 5 User s Manual U15075EJ1VOUMOO Figure No Title Page 11 5 Relationship Between Analog Input Voltage and A D Conversion 204 11 6 Software Started A D Conversion ennemi e sn nennen nnne 205 11 7 How to Reduce Current Consumption in Standby 206 11 8 Conversion Result Read Timing If Conversion Result Is Undefined a 207 11 9 Conversion Result Read Timing If Conversion Result Is Normal 207 11210 Analog Input Pin Treatment Hn Ere Ert ce Fert reete ae eer Pe REO 208 11 11 Co
196. marks 1 fx Main system clock oscillation frequency 2 The parenthesized values apply to operation at fx 5 0 MHz 280 User s Manual U15075EJ1V0UMO0 CHAPTER 15 STANDBY FUNCTION 15 2 Standby Function Operation 15 2 1 HALT mode 1 HALT mode The HALT mode is set by executing the HALT instruction The operation status in the HALT mode is shown in the following table Table 15 1 HALT Mode Operating Status HALT Mode Operation Status While The Main HALT Mode Operation Status While The System Clock Is Running Subsystem Clock Is Running While the subsystem While the subsystem While the main system While the main system clock is running clock is not running clock is running clock is not running Main system clock Oscillation enabled Oscillation stopped Operation stopped Port output latch Remains in the state existing before the selection of HALT mode Operation enabled Operation stopped 8 bit timer 50 Operation enabled Operation enabled TM60 Operation enabled Watch timer Operation enabled Operation enabled Operation enabled Operation enabled Watchdog timer Operation enabled Operation stopped Serial interface Operation enabled Operation stopped A D converter Operation stopped LCD controller driver Operation enabled Operation enabled Operation enabled Operation enabled External interrupt Operation enabled Notes 1 Operation is enabled only when input signal from timer 60 timer 60 operation is
197. mer output data is 0 Timer output data is 1 TOF90 Overflow flag control EN Reset or cleared by software Set when the 16 bit timer overflows o o foma ve 90 Timer output data inversion control EN Inversion disabled Inversion enabled o una SSCS 90 16 bit timer counter 90 output control EN Output disabled port mode Output enabled Note Bit 7 is read only Caution Disable interrupts in advance by using the interrupt mask flag register MK1 to change the data of TCL901 and TCL900 Also prevent the timer output data from being inverted by setting TOC90 101 Remarks 1 fx Main system clock oscillation frequency 2 fxt Subsystem clock oscillation frequency 3 The parenthesized values apply to operation at fx 5 0 MHz or 32 768 kHz 120 Users Manual U15075EJ1VOUMOO CHAPTER 6 16 BIT 2 Buzzer output control register 90 BZC90 This register selects a buzzer frequency based on fcl selected with the count clock select bits TCL901 and TCL900 and controls the output of the square wave 7 90 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets BZC90 to 00H Figure 6 3 Format of Buzzer Output Control Register 90 Symbol 7 0 Address After reset R W a 5902 BCS901 5900 Buzzer frequency Ed rarer umama c mesma
198. mory by setting LCDONO bit 7 of LCDMO LCDONO 1 13 5 LCD Display Data Memory LCD display data memory is mapped at addresses to FAOEH Data in the LCD display data memory can be displayed on the LCD panel using the LCD controller driver Figure 13 5 shows the relationship between the contents of the LCD display data memory and the segment common outputs That part of the display data memory which is not used for display can be used as ordinary RAM Figure 13 5 Relationship Between LCD Display Data Memory Contents and Segment Common Outputs uPD789446 789456 Subseries Address b7 be bs ba bs be b bo Ie gt eg rece 814 CELER RES eter ERE FAODH 513 Tay Sapa p Ee FAOCH 512 Sasa 511 EE 1 BERE 2 TERM DEUS CN 1 Eee oem Peu Eo 50 COM3 COM2 COMO Caution No memory has been installed as the higher 4 bits of the LCD display data memory Be sure to set 0 to them User s Manual U15075EJ1V0UMO0 253 CHAPTER 13 LCD CONTROLLER DRIVER 13 6 Common and Segment Signals Each pixel of the LCD panel turns on when the potential difference between the corresponding common and
199. mory manipulation instruction RESET input sets TM50 and 60 to 00H 50 and 60 are cleared to 00H under the following conditions a Discrete mode i TM50 e After reset e When 5 bit 7 of 8 bit timer mode control register 50 TMC50 is cleared to 0 When match occurs between TM50 and CR50 When the TM50 count value overflows ii TM60 After reset e When TCE60 bit 7 of 8 bit timer mode control register 60 TMC60 is cleared to 0 When a match occurs between TM60 and CR60 When the 60 count value overflows b Cascade connection mode TM50 and TM60 are simultaneously cleared to 00H e After reset e When the TCE60 flag is cleared to 0 e When matches occur simultaneously between TM50 and CR50 and between TM60 and CR60 e When the TM50 and TM60 count values overflow simultaneously c Carrier generator mode TM50 After reset e When the TCE50 flag is cleared to 0 When a match occurs between TM50 and CR50 ii TM60 After reset e When the TCE60 flag is cleared to 0 When a match occurs between TM60 and CR60 When a match occurs between TM60 and CRH60 136 User s Manual U15075EJ1V0UMO0 7 8 PWM output mode i TM50 After reset e When the 5 flag is cleared to 0 When a match occurs between TM50 and CR50 When the 5 count value overflows ii TM60 Reset e When the TCE60 flag is cleared to 0
200. mpletion of A D conversion the SAR sends its contents to A D conversion result register 0 ADCRO A D conversion result register 0 ADCRO ADCRO holds the result of A D conversion Each time A D conversion ends the conversion result in the successive approximation register is loaded into ADCRO which is an 8 bit register ADCRO can be read with an 8 bit memory manipulation instruction RESET input makes ADCRO undefined Sample amp hold circuit The sample amp hold circuit samples consecutive analog inputs from the input circuit one by one and sends them to the voltage comparator The sampled analog input voltage is held during A D conversion User s Manual U15075EJ1VO0UMOO 4 5 6 7 8 CHAPTER 10 8 BIT A D CONVERTER uPD789426 AND 789446 SUBSERIES Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string Series resistor string The series resistor string is configured between and AVss It generates the reference voltages with which analog inputs are compared to ANI5 Pins to are the 6 channel analog input pins for the A D converter They are used to receive the analog signals for A D conversion Caution Do not supply pins to ANI5 with voltages that fall outside the rated range If a voltage greater than or less than AVss even if within the absolute maximum rating is applied to any of these pi
201. n RESET input sets PUB9 to 00H Note Incorporated only in the 0789426 789436 Subseries Figure 4 24 Format of Pull Up Resistor Option Register B9 Symbol 7 gt lt gt 0 Address After reset R W lt 6 gt 5b 4 35 2 gt 9 PUB97 PUB96 PUB95 PUB94 PUB93 PUBS92 PUB91 90 00H R W P9n on chip pull up resistor selection n 2 0 to 7 On chip pull up resistor not used 1 On chip pull up resistor used User s Manual U15075EJ1V0UMO0 101 CHAPTER 4 PORT FUNCTIONS 4 4 Port Function Operation The operation of a port differs depending on whether the port is set in the input or output mode as described below 4 4 1 Writing to I O port 1 2 In output mode A value can be written to the output latch of a port by using a transfer instruction The contents of the output latch can be output from the pins of the port Data once written to the output latch is retained until new data is written to the output latch In input mode A value can be written to the output latch by using a transfer instruction However the status of the port pin is not changed because the output buffer is OFF Data once written to the output latch is retained until new data is written to the output latch Caution A 1 bit memory manipulation instruction is executed to manipulate 1 bit of a port However this instruction accesses the port in 8 bit units When this instruction is executed to mani
202. n continues until bit 7 ADCSO of A D converter mode register 0 ADMO is reset 0 by software If an attempt is made to write to ADMO or analog input channel specification register 0 ADSO during A D conversion the ongoing A D conversion is canceled In this case A D conversion is restarted from the beginning if ADCSO is set 1 RESET input makes A D conversion result register 0 ADCRO undefined ADCRO 11 4 2 Input voltage and conversion result The relationships between the analog input voltage at the analog input pins ANIO to ANI5 and the A D conversion result A D conversion result register 0 ADCRO are represented by ADCRO INT x 1 024 0 5 or AVpp AVpp ADCR0 0 5 lt Vin lt ADCRO 0 5 DORE OP gag cs 05 4024 Function that returns the integer part of a parenthesized value Analog input voltage Supply voltage for the A D converter ADCRO Value in A D conversion result register 0 ADCRO Figure 11 5 shows the relationship between the analog input voltage and the A D conversion result User s Manual U15075EJ1V0UMOO 203 CHAPTER 11 10 BIT A D CONVERTER uPD789436 AND 789456 SUBSERIES Figure 11 5 Relationship Between Analog Input Voltage and A D Conversion Result 1023 em 1022 1021 A D conversion result ADCRO
203. n the host machines and operating systems to be used Lu SxxxxRA78K0S LSxxxxCC78K08 LSxxxxDF789456 USxxxxCC78K0S L AA13 PC 9800 series Japanese Windows 3 5 2HD FD IBM PC AT compatibles Japanese Windows 3 5 2HC FD English Windows 3 16 9000 series 7007 HP UX Rel 10 10 DAT DDS SPARCstation SunOS Rel 4 1 1 3 5 2HC FD Solaris Rel 2 5 1 1 4 CGMT Note Also operates under the DOS environment User s Manual U15075EJ1VOUMOO 311 APPENDIX DEVELOPMENT TOOLS A 2 Flash Memory Writing Tools Flashpro 111 Dedicated flash programmer for microcomputers incorporating flash memory Part No FL PR3 PG FP3 Flash programmer FA 64GK Adapter for writing to flash memory and connected to Flashpro lll Flash memory writing adapter FA 64GK for 64 pin plastic TQFP fine pitch GK 9ET type Remark FL PR3 and FA 64GK are products made by Densei Machida Mfg Co Ltd TEL 81 44 822 3813 312 User s Manual U15075EJ1V0UMO0 APPENDIX DEVELOPMENT TOOLS Debugging Tools A 3 1 Hardware IE 78K0S NS In circuit emulator IE 70000 MC PS B AC adapter IE 70000 98 IF C Interface adapter IE 70000 CD IF A PC card interface IE 70000 PC IF C Interface adapter IE 70000 PCI IF Interface adapter IE 789456 NS EM1 Emulation board NP 64GK Emulation probe In circuit emulator for debugging hardware and software of application system using 78 05 Se
204. ng the above procedure Figures 7 22 to 7 25 show the operation timing in the PWM free running mode 164 User s Manual U15075EJ1VOUMOO 7 8 Figure 7 22 Operation Timing PWM Free Running Mode When Rising Edge Is Selected LE LILI LIL LILI LILI LI LILI Ly LI I TM50 CR50 50 Count start 50 5 Caution When the rising edge is selected do not set the 50 to OOH If the CR50 is set to PWM output may not be performed normally Figure 7 23 Operation Timing When Overwriting CR50 When Rising Edge Is Selected 1 2 1 When setting CR50 gt 50 after overflow ewe LE LILI LILI LILI LI LJ LE LE TE TI 50 50 50 Count start 50 050 50 overwrite User s Manual U15075EJ1V0UMO0 165 7 8 Figure 7 23 Operation Timing When CR50 When Rising Edge Is Selected 2 2 2 When setting CR50 TM50 after overflow ewe LE LILI LILI LILI LILI LILI LL TM50 Overflow Overflow Overflow CR50 N 01 1 1 1 l l L TCE50 Count start INTTM50 TO50 CR50 overwrite Overflow occurs but no change takes place because 50 is high level Figure 7 24 Operation Timing in PWM Free Running Mode When Both Edges Are Selected 1 2
205. nipulation instruction RESET input sets INTM1 to 00H Figure 14 5 Format of External Interrupt Mode Register 1 Symbol 7 6 Address X After reset R W 5 4 3 2 1 0 To 2531 530 INTPS valid edge selection Falling edge Setting prohibited Both rising and falling edges Cautions 1 Bits 2 to 7 must be set to 0 2 Before setting INTM1 set to 1 to disable interrupts After that clear 0 PIF3 then set to 0 to enable interrupts 5 Program status word PSW The program status word is a register used to hold the instruction execution result and the current status for interrupt requests The IE flag to set maskable interrupt enable disable is mapped Besides 8 bit unit read write this register can carry out operations with a bit manipulation instruction and dedicated instructions El 01 When a vectored interrupt is acknowledged the PSW is automatically saved into a stack and the IE flag is reset to O RESET input sets PSW to 02H Figure 14 6 Configuration of Program Status Word After reset 02H Symbol 7 6 PSW 5 4 3 2 1 0 t jor Used when normal instruction is executed Interrupt acknowledgement enabled disabled 0 Disabled 1 Enabled 270 User s Manual U15075EJ1V0UMO0 CHAPTER 14 INTERRUPT FUNCTIONS 6 Key return mode register 00 0 This register sets the pin that detects a key return sign
206. nnne 135 7 4 Format of 8 Bit Timer Mode Control Register 50 nennen menter 139 7 5 Format of 8 Bit Timer Mode Control Register 60 nennen msn 141 7 6 Format of Carrier Generator Output Control Register 60 142 7 7 Format of Port Mode Riegister 3 ieee a ER ERES UNE HEEL e EL CR e E EROR 142 7 8 Timing of Interval Timer Operation with 8 Bit Resolution Basic Operation 145 7 9 Timing of Interval Timer Operation with 8 Bit Resolution When Is Set to OOH 145 7 10 Timing of Interval Timer Operation with 8 Bit Resolution When Is Set to FFH 146 7 11 Timing of Interval Timer Operation with 8 Bit Resolution When CRnO Changes from to M N lt M 146 7 12 Timing of Interval Timer Operation with 8 Bit Resolution When CRnO Changes from to M N gt M 147 7 13 Timing of Interval Timer Operation with 8 Bit Resolution When Timer 60 Match Signal Is Selected for Timer 50 Gount Glock s t iret einbinden tud bec is 148 7 14 Timing of Operation of External Event Counter with 8 Bit Resolution a 150 7 15 Timing of Square Wave Output with 8 Bit 1 152 User s Manual U15075EJ1VOUMOO LIST OF FIGURES 3 5 Figure No Title Page 7 16 Timing of Interval Timer Operation with 16
207. nput voltage Supply voltage for the A D converter ADCRO Value in A D conversion result register 0 ADCRO Figure 10 5 shows the relationship between the analog input voltage and the A D conversion result User s Manual U15075EJ1V0UMOO 189 CHAPTER 10 8 A D CONVERTER uPD789426 AND 789446 SUBSERIES Figure 10 5 Relationship Between Analog Input Voltage and A D Conversion Result 255 254 253 A D conversion result ADCRO 1 Ae c9 cR 255 59 507 254 509 255 511 1 512 256 512 256 512 256 512 256 512 256 512 Input voltage AVop 190 User s Manual U15075EJ1V0UMOO CHAPTER 10 8 BIT A D CONVERTER uPD789426 AND 789446 SUBSERIES 10 4 3 Operation mode of 8 bit A D converter The A D converter is initially in select mode In this mode analog input channel specification register 0 ADSO is used to select an analog input channel from ANIO to ANI5 for A D conversion A D conversion can be started only by software that is by setting A D converter mode register 0 ADMO The A D conversion result is saved to A D conversion result register 0 ADCRO At the same time an interrupt request signal INTADO is generated Software started A D conversion Setting bit 7 ADCSO of A D converter mode register 0 ADMO to 1 triggers A D conversion for a voltage applied to the analog input pin specified
208. ns the conversion value for the corresponding channel will be undefined Furthermore the conversion values for the other channels may also be affected AVss pin The AVss pin is a ground potential pin for the A D converter This pin must be held at the same potential as the Vss pin even while the A D converter is not being used pin The pin is an analog power supply pin for the A D converter This pin must be held at the same potential as the pin even while the A D converter is not being used Users Manual U15075EJ1VOUMOO 185 CHAPTER 10 8 BIT A D CONVERTER uPD789426 AND 789446 SUBSERIES 10 3 8 Bit A D Converter Control Registers The 8 bit A D converter is controlled by the following two registers A D converter mode register 0 ADMO Analog input channel specification register 0 ADSO 1 A D converter mode register 0 ADMO ADMO specifies the conversion time for analog inputs It also specifies whether to enable conversion ADMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADMO to 00H Figure 10 2 Format of A D Converter Mode Register 0 Symbol lt 7 gt 6 Address After reset R W 5 4 3 2 1 0 ADCSO A D conversion control 282 Conversion disabled Conversion enabled 9191 jem 60 fx Setting prohibitedNete 2 48 fx Setting prohibitedNete 2 Other than above Setting prohibited _ o foi e o fm omea o KEEA
209. ns nennen 170 7 29 Timing of Operation as External Event Counter 8 Bit Resolution eee 170 8 1 Block Diagram ot Watch Tiera au iiio ote tea e e o DER e retra aaa n pae td 171 8 2 Format of Watch Timer Mode Control Register 173 8 3 Watch Timer Interval Timer Operation Timing U enne 175 9 1 Block Diagram of Watchdog TIMET p ae A eh p Eee iin 178 9 2 Format of Watchdog Timer Clock Select Register sse nnne 179 9 3 Format of Watchdog Timer Mode Register essen 180 10 1 Block Diagram of 8 Bit A D Converter U en nennen 184 10 2 Format of A D Converter Mode Register 0 7 7 7 186 10 3 Format of Analog Input Channel Specification Register 0 187 10 4 Basic Operation of 8 Bit A D Converter nennen ennt 189 10 5 Relationship Between Analog Input Voltage and A D Conversion 190 10 6 Software Started A D Conversion innen terrens 191 10 7 How to Reduce Current Consumption in Standby 192 10 8 Conversion Result Read Timing If Conversion Result Is 193 10 9 Conversion Result Read Timing If Conversion Resu
210. nt Related to Embedded Software User s Manual Document No 78K 0S Series OS 78 05 U12938J U12938E Other Related Documents Document No SEMICONDUCTOR SELECTION GUIDE Products amp Packages CD ROM X13769X Semiconductor Device Mounting Technology Manual C10535J C10535E Caution The related documents listed above are subject to change without notice sure to use the latest version of each document for designing User s Manual U15075EJ1VOUMOO 9 10 User s Manual U15075EJ1VOUMOO 5 CHAPTER 1 GENERAL 25 UNUM VIC RE 25 1 2 a 25 1 3 Ordering 1 26 1 4 Pin Configuration Top View 27 1 4 1 Pin configuration of uPD789426 789436 Subseries Top View 27 1 4 8 Pin configuration of 789446 789456 Subseries Top View 28 1 5 78K 0S Series Lineup rrr eere ertet edunt eerie un aa 30 1 6 Block Diagram a edic rr 32 1 6 1 Block diagram of uPD789426 789436 5
211. nterface status register 20 ASIS20 ASIS20 indicates the type of a reception error if it occurs while asynchronous serial interface mode is set ASIS20 is set with a 1 bit or 8 bit memory manipulation instruction The contents of ASIS20 are undefined 3 wire serial I O mode RESET input sets ASIS20 to 00H Symbol Figure 12 5 Format of Asynchronous Serial Interface Status Register 20 2 lt gt lt 0 Address After reset R W LoDo Le rem om PE20 Parity error flag EN No parity error has occurred A parity error has occurred when the parity of transmit data does not match FE20 Flaming error flag No framing error has occurred A framing error has occurred when stop bit is not detected Ne e 1 OVE20 Overrun error flag overrun error has occurred 1 An overrun error has occurred e when the next receive operation is completed before the data is read from reception buffer register 20 Notes 1 Even when the stop bit length is set to 2 bits by setting bit 2 SL20 of asynchronous serial interface mode register 20 ASIM20 the stop bit detection at reception is performed with 1 bit Be sure to read reception buffer register 20 RXB20 when an overrun error occurs If not every time the data is received an overrun error will occur User s Manual U15075EJ1VO0UMOO CHAPTER 12 SERIAL INTERFACE 20 4 Baud rate generator control register 20 BRGC20 BRGC20 is used to specify t
212. nterrupt Timing a Stop bit length 1 START INTST20 b Stop bit length 2 START INTST20 Caution Do not rewrite asynchronous serial interface mode register 20 ASIM20 during transmit operation If the ASIM20 register is rewritten during transmission subsequent transmission may not be able to be performed the normal state is restored by RESET input It is possible to determine whether transmission is in progress by software by using a transmission completion interrupt INTST20 or the interrupt request flag STIF20 set by INTST20 User s Manual U15075EJ1V0UMOO 233 234 CHAPTER 12 SERIAL INTERFACE 20 d Reception When bit 6 RXE20 of asynchronous serial interface mode register 20 ASIM20 is set 1 a receive operation is enabled and sampling of the RxD20 pin input is performed RxD20 pin input sampling is performed using the serial clock specified by ASIM20 When the RxD20 pin input becomes low the 3 bit counter starts counting and when half the time determined by the specified baud rate has passed the data sampling start timing signal is output If the RxD20 pin input sampled again as a result of this start timing signal is low it is identified as a start bit the 3 bit counter is initialized and starts counting and data sampling is performed When character data a parity bit and one stop bit are detected after the start bit reception of one frame of data ends When one frame of data has been recei
213. nterrupts Example 1 Acknowledging multiple interrupts Main servicing INTxx servicing INTyy servicing INTxx INTyy RETI RETI Y The interrupt request INTyy is acknowledged during the servicing of interrupt INTxx and multiple interrupts are performed Before each interrupt request is acknowledged the El instruction is issued and the interrupt request is enabled Example 2 Multiple interrupts are not performed because interrupts are disabled Main servicing INTxx servicing INTyy servicing IE 0 is held pending RETI INTxx IE 0 Because interrupt requests are disabled the EI instruction has not been issued in the interrupt INTxx servicing the interrupt request INTyy is not acknowledged and multiple interrupts not performed is held pending and is acknowledged after INTxx servicing is completed IE 0 Interrupt requests disabled 276 User s Manual U15075EJ1V0UMO0 CHAPTER 14 INTERRUPT FUNCTIONS 14 4 4 Putting interrupt requests on hold If an interrupt request such as a maskable non maskable or external interrupt is generated when a certain type of instruction is being executed the interrupt request will not be acknowledged until the instruction is completed Such instructions interrupt request pending instructions are as follows e Instructions that manipulate interrupt request flag registers 0 1 IFO and IF1 e Instruc
214. ntroller The reception controller controls reception according to the setting of asynchronous serial interface mode register 20 ASIM20 It also checks for errors such as parity errors during reception If an error is detected asynchronous serial interface status register 20 ASIS20 is set according to the status of the error User s Manual U15075EJ1VO0UMOO CHAPTER 12 SERIAL INTERFACE 20 12 3 Serial Interface 20 Control Registers Serial interface 20 is controlled by the following registers Serial operation mode register 20 CSIM20 Asynchronous serial interface mode register 20 ASIM20 Asynchronous serial interface status register 20 ASIS20 Baud rate generator control register 20 BRGC20 1 Serial operation mode register 20 CSIM20 CSIM20 is used to make the settings related to 3 wire serial mode CSIM20 is set with a 1 bit 8 bit memory manipulation instruction RESET input sets CSIM20 to 00H Figure 12 3 Format of Serial Operation Mode Register 20 Symbol 7 6 Address After reset R W 5 4 3 2 1 0 CSIM20 0 papz0 DIR20 28 20 ckPao FF72H 00H R W CSIE20 3 wire serial I O mode operation control m3 Operation disabled Operation enabled SSE20 5520 pin selection Function of SS20 P22 pin Communication status 1 Used ____ Communication enabled Communication disabled DAP20 3 wire serial mode data phase selection E Outputs at the falling edge of SCK20 Outputs at the rising e
215. nversion End Interrupt Request Generation Timing 209 14512 ect e E Pet e at dine Mat 209 12 1 Block Diagram of Serial Interface 20 212 12 2 Block Diagram of Baud Rate Generator 20 L nennen nnne nere nen 213 12 3 Format of Serial Operation Mode Register 20 8 215 12 4 Format of Asynchronous Serial Interface Mode Register 20 216 12 5 Format of Asynchronous Serial Interface Status Register 20 218 12 6 Format of Baud Rate Generator Control Register 20 219 12 7 Format of Asynchronous Serial Interface Transmit Receive 231 12 8 Asynchronous Serial Interface Transmission Completion Interrupt 233 12 9 Asynchronous Serial Interface Reception Completion Interrupt Timing esee 234 12 10 Receive Error Timing eet e re HE Re t E RE RR MEER RE Re HE HR D ER MR 235 12 11 3 Wire Serial Mode TimIng u ak nnne en nennt 240 13 1 Block Diagram of LCD Controller Driver n renes rennes 248 13 2 Format of LCD Display Mode Register 0 250 13 3 Format of LCD Clock Control Register 0 essent nennen enne 251 13 4 Format of LCD Voltage Amplification Control Register 0 252 13 5 Relation
216. nversion is complete 10 2 8 Bit A D Converter Configuration The 8 bit A D converter includes the following hardware Table 10 1 Configuration of 8 Bit A D Converter Analog inputs 6 channels ANIO to ANI5 Registers Successive approximation register SAR A D conversion result register 0 ADCRO Control registers A D converter mode register 0 ADMO Analog input channel specification register 0 ADSO User s Manual U15075EJ1V0UMOO 183 ANIO P60 G ANH P61 ANI2 P62 ANIS P63 ANI4 P64 G 65 1 2 3 184 CHAPTER 10 8 BIT A D CONVERTER uPD789426 AND 789446 SUBSERIES Figure 10 1 Block Diagram of 8 Bit A D Converter gt Voltage comparator Sample amp hold circuit 2 o N Successive approximation register SAR Controller gt INTADO A D conversion result register 0 ADCRO m zy 502 ADS01 ADS00 Analog input channel A D converter mode specification register 0 ADSO register 0 ADMO ADCSO 02 FRO1 FROO Internal bus Successive approximation register SAR The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap comparison voltage received from the series resistor string starting from the most significant bit MSB Upon receiving all the bits down to the least significant bit LSB that is upon the co
217. of the watchdog timer clock select register WDCS The watchdog timer starts operation as an interval timer when the RUN bit bit 7 of WDTM is set to 1 In interval timer mode the interrupt mask flag WDTMK is valid and a maskable interrupt INTWDT can be generated The priority of INTWDT is set as the highest of all the maskable interrupts The interval timer continues operation in HALT mode but stops in STOP mode Therefore first set RUN to 1 to clear the interval timer before executing the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 when watchdog timer mode is selected interval timer mode is not set unless the RESET signal is input 2 The interval time may be up to 0 8 shorter than the set time when WDTM has just been set Table 9 5 Interval Time of Interval Timer wocse woosi wocso OMe o sous fx Main system clock oscillation frequency 182 Users Manual U15075EJ1VOUMOO CHAPTER 10 8 BIT A D CONVERTER 2 0789426 AND 789446 SUBSERIES 10 1 8 Bit A D Converter Functions The 8 bit A D converter is an 8 bit resolution converter used to convert analog inputs into digital signals This converter can control six channels ANIO to ANI5 of analog inputs A D conversion can only be started by software One of analog inputs ANIO to is selected for A D conversion A D conversion is performed repeatedly with an interrupt request INTADO being issued each time A D co
218. on If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected or GND with a resistor if it is considered to have a possibility of being an output pin handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function EEPROM is a trademark of NEC Corporation Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries PC AT is a trademark of International Business Machines Corporation HP9000 series 700 and HP UX are trademarks of Hewlett Packard Company
219. on status A recover of the voltage is detected with an interrupt request signal Bit of PCC is set to 0 and then the main system clock starts oscillating After the time required for the oscillation to stabilize has elapsed PCC1 and 550 are rewritten so that high speed operation can be selected again Caution When the main system clock is stopped and the device is operating on the subsystem clock wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock User s Manual U15075EJ1VOUMOO CHAPTER 6 16 BIT TIMER 6 1 16 Bit Timer Functions The 16 bit timer has the following functions Timer interrupt Timer output Buzzer output Count value capture 1 Timer interrupt An interrupt is generated when a count value and compare value matches 2 Timer output Timer output can be controlled when a count value and compare value matches 3 Buzzer output Buzzer output can be controlled by software 4 Count value capture A count value of 16 bit timer counter 90 90 is latched into a capture register synchronizing with the capture trigger and retained User s Manual U15075EJ1V0UMOO 115 6 16 6 2 16 Bit Timer Configuration The 16 bit timer includes the following hardware Table 6 1 16 Bit Timer Configuration Timer counters 16 bits x 1 TM90 Registers Compare register 16 bits x 1 CR90 C
220. or can be specified by means of pull up resistor option register B8 8 P90 to 97 Port 9 Input 8 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register B9 PUB9 Note 0789426 789436 Subseries only 38 User s Manual U15075EJ1V0UMO0 2 5 2 Non port pins Input External interrupt input for which the valid edge rising edge Input falling edge or both rising and falling edges can be specified Serial interface 51020 chip select Serial interface 20 serial clock input output 16 bit timer TM90 output 8 bit timer TM60 output P32 INTP2 to ANI5 A D converter analog input P60 to P65 SO to S4 Output LCD controller driver segment signal output S5 to S14 Output Sets flash memory programming mode Applies high voltage when a program is written or verified Connect directly to Vss in normal operation mode Note uPD789446 789456 Subseries only User s Manual 015075 39 CHAPTER 2 PIN FUNCTIONS 2 2 Description of Pin Functions 2 2 1 to Port 0 These pins constitute a 4 bit port In addition these pins enable key return signal detection Port 0 can be specified in the following operation modes in 1 bit units 1 Port mode These pins constitute a 4 bit I O port and can be set in the input
221. or not higher than AVss is likely to come to the AVop pin clamp the voltage at the pin by attaching a diode with a small Vr 0 3 V or lower C 100 to 1 000 pF A to ANI5 The analog input pins ANIO to ANI5 are alternate function pins They are also used as port pins P60 to P65 If any of ANIO to ANI5 has been selected for A D conversion do not execute input instructions for the ports otherwise the conversion resolution may be reduced If a digital pulse is applied to a pin adjacent to the analog input pins during A D conversion coupling noise may occur that prevents an A D conversion result from being obtained as expected Avoid applying a digital pulse to pins adjacent to the analog input pins during A D conversion Interrupt request ADIFO Changing the contents of A D converter mode register 0 ADMO does not clear the interrupt request flag ADIFO If the analog input pins are changed during A D conversion therefore the A D conversion result and the conversion end interrupt request flag may reflect the previous analog input immediately before writing to ADMO occurs In this case ADIFO may already be set if it is read accessed immediately after ADMO is write accessed even when A D conversion has not been completed for the new analog input In addition when A D conversion is restarted ADIFO must be cleared beforehand User s Manual U15075EJ1VO0UMOO CHAPTER 10 8 BIT A D CONVERTER uPD789426 AND 78
222. or output port mode 1 bit units by port mode register 0 PMO When used as an input port use of an on chip pull up resistor can be specified by pull up resistor option register 0 PUO in port units 2 Control mode In this mode POO to function as key return signal detection pins KRO to 2 2 2 P10 P11 Port 1 These pins constitute a 2 bit port can be set in the input or output port mode in 1 bit units by port mode register 1 PM1 When used as an input port use of an on chip pull up resistor can be specified by pull up resistor option register 0 PUO in port units 2 2 3 P20 to P26 Port 2 These pins constitute a 7 bit I O port In addition these pins enable buzzer output timer output serial interface data and serial clock I O Port 2 can be specified in the following operation modes in 1 bit units 1 Port mode In this mode P20 to P26 function as 7 bit I O port Port 2 can be set in the input or output port mode 1 bit units by port mode register 2 PM2 When used as an input port use of an on chip pull up resistor can be specified by pull up resistor option register B2 PUB2 in 1 bit units 2 Control mode In this mode P20 to P26 function as the buzzer output timer output serial interface data I O and serial clock a Buzzer output This is the buzzer output pin of 16 bit timer 90 b TO90 This is the timer output pin of 16 bit timer 90 120 5020 The
223. ort Mode 97 4 19 Format of Pull Up Resistor Option Register 0 nennen nenne nennen 98 4 20 Format of Pull Up Resistor Option Register 2 99 4 21 Format of Pull Up Resistor Option Register 99 User s Manual U15075EJ1VO0UMOO 17 LIST FIGURES 2 5 Figure No Title Page 4 22 Format of Pull Up Resistor Option Register 7 nnne 100 4 23 Format of Pull Up Resistor Option Register 8 enne nnn nnne 100 4 24 Format of Pull Up Resistor Option Register 9 101 5 1 Block Diagram of Clock Generator iriiria iarra a a entente a 104 5 2 Format of Processor Clock Control Register eene eene nennen enne nnne nnne 105 5 3 Format of Suboscillation Mode Register 110000 enne nre nnne nnne 106 5 4 Format of Subclock Control 107 5 5 External Circuit of Main System Clock Oscillator a 108 5 6 External Circuit of Subsystem Clock Oscillator nene nnn 109 5 7 Examples of Incorrect Resonator Connection enne nennen nnne 110 5 8 Switching Between System Clock and CPU nennen nnne 114 6 1 Block
224. output mode PM26 0 Reset output latch of P26 to 0 Set the count value in CR90 Set 16 bit timer mode control register 90 TMC90 as shown in Figure 6 7 Figure 6 7 Settings of 16 Bit Timer Mode Control Register 90 for Timer Output Operation TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 mco or mo TO90 output enable Setting of count clock see Table 6 2 Inverse enable of timer output data Caution If both the CPT901 flag and CPT900 flag are set to 0 the capture operation is prohibited When the count value of 16 bit timer counter 90 TM90 matches the value set in CR90 the output status of the TO90 P26 pin is inverted This enables timer output At that time TM90 counting continues and an interrupt request signal 90 is generated Figure 6 8 shows the timing of timer output see Table 6 2 for the interval time of the 16 bit timer Figure 6 8 Timer Output Timing FULL AL TM90 count vale 0000H X 0001H T FFFFH 0000H TEUER CL hl t acknowledgement Interrupt acknowledgement TOgONete I 90 t rIA Note The initial value of TO90 becomes low level when output is enabled TOE90 1 Remark N 0000H to FFFFH User s Manual U15075EJ1VO0UMOO 125 CHAPTER 6 16 BIT 6 4 3 Capture operation The capture operation consists of latching the
225. p pull up resistors on P80 and P81 are used or not On the port specified to use an on chip pull up resistor by PUBS the pull up resistor can be internally used only for bits set in the input mode No on chip pull up resistors can be used for the bits set in the output mode regardless of the setting of PUB8 This also applies to when the pins are used for alternate functions PUBBS is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PUB8 to 00H Note Incorporated only in the uPD789426 and 789436 Subseries Figure 4 23 Format of Pull Up Resistor Option Register B8 Symbol 7 6 1 0 Address After reset R W 5 4 3 2 PUB8 PUB81 PUB80 FF38H 00H R W oj o oo Pune used PUB8n P8n on chip pull up resistor selection n 0 1 On chip pull up resistor not used On chip pull up resistor used 100 User s Manual U15075EJ1V0UMO0 CHAPTER 4 PORT FUNCTIONS Note 7 Pull up resistor option register B9 PUB9 Pull up resistor option register B9 PUB9 sets whether on chip pull up resistors on P90 to P97 are used or not On the port specified to use an on chip pull up resistor by PUBS the pull up resistor can be internally used only for bits set in the input mode No on chip pull up resistors can be used for the bits set in the output mode regardless of the setting of PUBY This also applies to when the pins are used for alternate function PUB9 is set with a 1 bit or 8 bit memory manipulation instructio
226. pheral hardware is generated by dividing the frequency of the main system clock but the subsystem clock pulse is only supplied to the 16 bit timer 8 bit timer watch timer and LCD controller driver The 16 bit timer 8 bit timer watch timer and LCD controller driver can therefore keep running even during standby The other hardware stops when the main system clock stops because it runs based on the main system clock except for external input clock operations User s Manual U15075EJ1VOUMOO CHAPTER 5 CLOCK GENERATOR 5 6 Changing Setting of System Clock and CPU Clock 5 6 1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 PCC1 of the processor clock control register PCC and bit 4 550 of the subclock control register CSS Actually the specified clock is not selected immediately after the setting of PCC has been changed and the old clock is used for the duration of several instructions after that see Table 5 2 Table 5 2 Maximum Time Required for Switching CPU Clock Set Value Before Switching Set Value After Switching 4 clocks 2fx fxt clocks 306 clocks 1 2 clocks fx 2fxr clocks 76 clocks EMEN EN t Remarks 1 Two clocks are the minimum instruction execution time of the CPU clock before switching 2 The parenthesized values apply to operation at fx 5 0 MHz or fxr 32 768 kHz
227. pins during A D conversion coupling noise may occur that prevents an A D conversion result from being obtained as expected Avoid applying a digital pulse to pins adjacent to the analog input pins during A D conversion Interrupt request flag ADIF0 Changing the contents of A D converter mode register 0 ADM0 does not clear the interrupt request flag ADIF0 If the analog input pins are changed during A D conversion therefore the A D conversion result and the conversion end interrupt request flag may reflect the previous analog input immediately before writing to ADMO occurs In this case ADIF0 may already be set if it is read accessed immediately after ADMO is write accessed even when A D conversion has not been completed for the new analog input In addition when A D conversion is restarted ADIFO must be cleared beforehand User s Manual U15075EJ1VO0UMOO CHAPTER 11 10 A D CONVERTER uPD789436 AND 789456 SUBSERIES Figure 11 11 A D Conversion End Interrupt Request Generation Timing Rewriting to ADMO Rewriting to ADMO to begin conversion to begin conversion ADIFO has been set but conversion for for ANIm for ANIm has not been completed A D conversion ADCRO INTADO Remarks 1 0105 2 0105 9 The pin is used to supply power to the analog circuit It is also used to supply power to the to input circuit If your application is designed
228. port to PC98 NX Series Unless specified otherwise the products supported by IBM compatibles can be used in PC98 NX Series When using the PC98 NX Series refer to the explanation of IBM PC AT compatibles Windows Unless specified otherwise Windows indicates the following operating systems Windows 3 1 Windows 95 Windows 4 0 User s Manual 015075 309 310 APPENDIX DEVELOPMENT TOOLS Figure A 1 Development Tools Language processing software Assembler package Embedded software compiler package System simulator OS Device file compiler source file Integrated debugger Host machine PC or EWS Interface adapter Flash memory writing tools Flash programmer In circuit emulator Emulation board Flash memory writing adapter Flash memory Emulation probe Conversion adapter Target system User s Manual U15075EJ1VOUMOO Power supply unit APPENDIX DEVELOPMENT TOOLS A 1 Language Processing Software RA78K0S Program that converts program written in mnemonic into object codes that can be executed Assembler package by microcontroller In addition automatic functions to generate symbol table and optimize branch instructions are also provided Used in comb
229. pulate a bit of an input output port therefore the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined 4 4 2 Reading from port 1 2 output mode The status of an output latch can be read by using a transfer instruction The contents of the output latch are not changed In input mode The status of a pin can be read by using a transfer instruction The contents of the output latch are not changed 4 4 3 Arithmetic operation of port 1 2 102 In output mode An arithmetic operation can be performed with the contents of the output latch The result of the operation is written to the output latch The contents of the output latch are output from the port pins Data once written to the output latch is retained until new data is written to the output latch In input mode The contents of the output latch become undefined However the status of the pin is not changed because the output buffer is OFF Caution A 1 bit memory manipulation instruction is executed to manipulate 1 bit of a port However this instruction accesses the port in 8 bit units When this instruction is executed to manipulate a bit of an input output port therefore the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined User s Manual U15075EJ1VOUMOO CHAPTER 5 CLOCK GENERATOR 5 1 Clock Generator Fun
230. quest acknowledgement enable is controlled with an interrupt mask flag for various interrupt sources IE is reset 0 upon DI instruction execution or interrupt acknowledgment and is set 1 upon El instruction execution Zero flag Z When the operation result is zero this flag is set 1 It is reset 0 in all other cases Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases Carry flag CY This flag stores overflow and underflow upon add subtract instruction execution It stores the shift out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution User s Manual U15075EJ1VOUMOO CHAPTER 3 CPU ARCHITECTURE 3 Stack pointer SP This is a 16 bit register to hold the start address of the memory stack area Only the internal high speed RAM area can be set as the stack area Figure 3 15 Stack Pointer Configuration SP 15 0 The SP is decremented ahead of write save to the stack memory and is incremented after read restore from the stack memory Each stack operation saves restores data as shown in Figures 3 16 and 3 17 Caution Since RESET input makes the SP contents undefined be sure to initialize the SP before instruction execution Figure 3 16 Data to Be Saved to Stack Memory PUSH rp CALL CALLT Interrupt instr
231. quest is acknowledged the PSW and PC are saved to the stack in that order the IE flag is reset to 0 and the data in the vector table determined for each interrupt request is loaded to the PC and execution branches To return from interrupt servicing use the RETI instruction Figure 14 12 Interrupt Request Acknowledgment Program Algorithm Yes Interrupt request generated Yes Interrupt request pending Vectored interrupt servicing xxlF Interrupt request flag xxMK Interrupt mask flag IE Flag to control maskable interrupt request acknowledgement 1 enable 0 disable 274 User s Manual 1 15075 1 00 00 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14 13 Interrupt Request Acknowledgment Timing Example MOV A r 8 clocks Clock 22 L Saving PSW and PC and CPU jump 10 interrupt servicing Interrupt servicing program Interrupt If the interrupt request has generated an interrupt request flag XXIF by the time the instruction clocks under execution n clocks n 4 to 10 are n 1 interrupt request acknowledgment processing will start following the completion of the instruction under execution Figure 14 13 shows an example using the 8 bit data transfer instruction MOV A r Because this instruction is executed in 4 clocks if an interrupt request is generated between the start of execution and the 3rd clock interrupt request acknowledgment processing will
232. r 3 16 bit capture register 90 TCP90 TCP90 captures the contents of TM90 It is set with an 8 bit or 16 bit memory manipulation instruction RESET input makes TCP90 undefined Caution TCP90 is designed to be manipulated with a 16 bit memory manipulation instruction However it can also be manipulated with an 8 bit memory manipulation instruction When an 8 bit memory manipulation instruction is used to manipulate TCP90 it must be accessed by direct addressing 4 16 bit counter read buffer 90 This buffer is used to latch and hold the count value for TM90 118 Users Manual U15075EJ1VOUMO0 CHAPTER 6 16 BIT 6 3 Registers Controlling 16 Bit Timer The 16 bit timer is controlled by the following three registers 16 bit timer mode control register 90 TMC90 Buzzer output control register 90 BZC90 Port mode register 2 PM2 1 16 bit timer mode control register 90 TMC90 16 bit timer mode control register 90 TMC90 controls the setting of a count clock capture edge etc 90 is set with a 1 bit 8 bit memory manipulation instruction RESET input sets TMC90 to 00H User s Manual U15075EJ1VO0UMOO 119 CHAPTER 6 16 BIT TIMER Figure 6 2 Format of 16 Bit Timer Mode Control Register 90 Symbol lt gt 6 5 4 3 2 1 lt 0 Address After reset R W gt 90 90 90 901 9001 0 90 1901 1900 0 90 FF48H 00H R WNete TOD90 Timer output data EN Ti
233. r 20 RXB20 or receiving the next data if there is an error in the next data the corresponding error flag is set Table 12 7 Receive Error Causes Transmission time parity and reception data parity do not match Reception of next data is completed before data is read from reception buffer register Figure 12 10 Receive Error Timing a Parity error occurrence STOP RxD20 input D1 D2 D7 START INTSR20 b Framing error or overrun error occurrence START INTSR20 Cautions 1 The contents of the ASIS20 register are reset 0 by reading reception buffer register 20 RXB20 or receiving the next data To ascertain the error contents read ASIS20 before reading RXB20 2 Be sure to read reception buffer register 20 RXB20 even if a receive error occurs If RXB20 is not read an overrun error will occur when the next data is received and the receive error state will continue indefinitely User s Manual U15075EJ1VOUMO0 235 CHAPTER 12 SERIAL INTERFACE 20 3 Cautions related to UART mode a When bit 7 TXE20 of asynchronous serial interface mode register 20 ASIM20 is cleared during transmission be sure to set transmission shift register 20 TXS20 to FFH then set TXE20 to 1 before executing the next transmission b When bit 6 RXE20 of asynchronous serial interface mode register 20 ASIM20 is cleared during reception reception buffer register 20 RXB20 and the receive completion interrupt INTSR20 a
234. ram of 789426 789436 Subseries 50 60 P31 TO60 P32 TO61 P33 Port 1 P10 P11 60 050 Cascadedk gt Port 0 K PO00 timer 50 16 bit timer event counter 60 counter TO90 P26 90 30 16 bit timer 90 BZO90 P21 Port 3 30 to P33 Watch timer K gt Port 5 P50 to P53 flash Watchdog timer K gt flas memor Port 7 P70 to P72 ANIO P60 to ANI5 P65 AVss A D converter SCK20 ASCK20 P23 SO20 TxD20 P24 Serial SI20 RxD20 P25 linterface 20 5520 22 System control X2 XT1 XT2 S0 to S4 lt lt COMO to COM3 LCD controller INTP1 P31 Vico to Vic2 driver INTP2 P32 CAPH lt Interrupt control CAPL P INTP3 P33 KR0 P00 to KR3 P03 Vss IC VPP Remarks 1 The internal ROM capacity varies depending on the product 2 The parenthesized values apply to the 078 9436 32 User s Manual U15075EJ1V0UM00 CHAPTER 1 GENERAL 1 6 2 Block diagram of 0789446 789456 Subseries 50 60 P31 TO60 P32 TO61 P33 TMI60 TO50 P31 TO90 P26 CPT90 P30 2090 21 ANIO P60 to ANI5 P65 AVss SO20 TxD20 P24 120 RxD20 P25 5520 22 16 bit timer 90 pe SCK20 ASCK20 P23 Serial linterface 20 5010 S4 lt lt
235. ration the output of the baud rate generator is disrupted and communications cannot be performed normally Be sure not to write to BRGC20 during a communication operation 2 Be sure not to select n 1 during operation at fx 5 0 MHz because the resulting baud rate exceeds the rated range 3 When the external input clock is selected set port mode register 2 PM2 to input mode Remarks 1 Main system clock oscillation frequency 2 n Values determined by the settings of TPS200 to TPS203 1 lt n lt 8 3 The parenthesized values apply to operation at fx 5 0 MHz User s Manual U15075EJ1VO0UMOO CHAPTER 12 SERIAL INTERFACE 20 The baud rate transmit receive clock to be generated is either a signal scaled from the system clock or a signal scaled from the clock input to the 5 20 pin i Generation of baud rate transmit receive clock from system clock The transmit receive clock is generated by scaling the system clock The baud rate of a clock generated from the system clock is estimated by using the following expression fx Baud rate U xg Hz fx Main system clock oscillation frequency n Values in the above table determined by the settings of TPS200 to TPS203 2 lt n lt 8 Table 12 5 Example of Relationships Between System Clock and Baud Rate Baud Rate bps BRGC20 Set Value Error 96 fx 2 5 0 MHz fx 2 4 9152 MHz Caution Do not select n 1 during operation at fx 5 0 MHz because the resulting bau
236. re as follows INTSR20 l When RXE20 is set to 0 at a time indicated by lt 1 gt RXB20 holds the previous data and INTSR20 15 not generated When RXE20 is set to 0 at a time indicated by lt 2 gt RXB20 renews the data and INTSR20 is not generated When RXE20 is set to 0 at a time indicated by lt 3 gt RXB20 renews the data and INTSR20 is generated 236 User s Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 12 4 3 3 wire serial mode The 3 serial mode is useful for connection of peripheral l Os and display controllers etc which incorporate a conventional clocked serial interface such as the 75XL Series 78K Series and 17K Series Communication is performed using three lines a serial clock SCK20 serial output SO20 and serial input SI20 1 Register setting 3 wire serial I O mode settings are performed using serial operation mode register 20 CSIM20 asynchronous serial interface mode register 20 ASIM20 and baud rate generator control register 20 BRGC20 a Serial operation mode register 20 CSIM20 CSIM2O is set with 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM20 to 00H Symbol 7 6 Address After reset R W Be 4 3 2 141 0 CSIM20 cSIE20 SSE20 DAP20 DIR20 CSCK20 20 FF72H 00H R W CSIE20 3 wire serial I O mode operation control Operation disabled Operation enabled SSE20
237. re as follows in the area enclosed by the broken lines in Figures 5 5 and 5 6 to avoid an adverse effect from wiring capacitance e Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as Vss Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator When using the subsystem clock particular care is required because the subsystem clock oscillator is designed as a low amplitude circuit for reducing current consumption Figure 5 7 shows examples of incorrect resonator connection User s Manual U15075EJ1V0UMO0 109 CHAPTER 5 CLOCK GENERATOR Figure 5 7 Examples of Incorrect Resonator Connection 1 2 a Too long wiring b Crossed signal line PORTn 0 to 3 5 Vss X1 X2 LL 77 77 Wiring near high fluctuating current d Current flowing through ground line of oscillator potential at points A B and C fluctuates E ANN K Vss X1 X2 High current E current Remark When using the subsystem clock read X1 and X2 as XT1 and XT2 respectively and connect a resistor to XT2 in series 110 User s Manual 1 15075 1 00 00 CHAPTER 5 CLOCK GENERATOR Figure
238. register 0 Interrupt request flag register 0 IFO FFE4H Interrupt mask flag register 0 MK0 FFECH FFEDH FFF0H FFF2H Subclock control register CSS FFF5H FFF7H Pull up resistor option register 0 PUO FFF9H FFFAH FFFBH Processor clock control register PCC Note uPD789426 and 789436 Subseries only User s Manual U15075EJ1VOUMOO 67 CHAPTER 3 CPU ARCHITECTURE 3 3 Instruction Address Addressing An instruction address is determined by the program counter PC contents The PC contents are normally incremented 1 for each byte automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed When a branch instruction is executed the branch destination information is set to the PC and branched by the following addressing for details of each instruction refer to 78K 0S Series Instructions User s Manual U11047E 3 3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit This means that information is relatively branched to a location between 128 and 127 from the start address of the next instruction when relative addressing is used This function is carried out wh
239. ries Supports integrated debugger ID78KOS NS Used in combination with AC adapter emulation probe and interface adapter for connecting the host machine Adapter for supplying power from AC 100 to 240 V outlet Adapter necessary when using PC 9800 series PC except notebook type as host machine of IE 78K0S NS C bus supported card and interface cable necessary when using notebook PC as host machine of IE 78KOS NS PCMCIA socket supported Interface adapter necessary when using IBM PC AT compatible as host machine of IE 78K0S NS ISA bus supported Adapter necessary when using personal computer incorporating PCI bus as host machine of IE 78K0S NS Board for emulating the peripheral hardware inherent to the device Used in combination with in circuit emulator Probe to connect the in circuit emulator and target system Used in combination with the TGK 064SBW and TGK 064SBP TGK 064SBW Conversion socket to connect the NP 64GK and a target system board on which a 64 pin plastic TGK 064SBP Conversion adapter TQFP fine pitch GK 9ET type can be mounted Remarks 1 The NP 64GK is a product made by Naito Densei Machida Mfg Co Ltd TEL 81 44 822 3813 2 The TGK 064SBW and TGK 064SBP are products made by TOKYO ELETECH CORPORATION For further information contact Daimaru Kogyo Ltd Tokyo Electronics Department TEL 81 3 3820 7112 Osaka Electronics Department TEL 81 6 6244 6672 User s Manual U15075
240. rupt servicing program Figure 14 11 Non Maskable Interrupt Request Acknowledgment Main routine First interrupt servicing NMI request second I request first Second interrupt servicing User s Manual U15075EJ1V0UMO0 273 CHAPTER 14 INTERRUPT FUNCTIONS 14 4 2 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0 vectored interrupt is acknowledged in the interrupt enabled status when the IE flag is set to 1 The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in Table 14 3 Refer to Figures 14 13 and 14 14 for the timing of interrupt request acknowledgement Table 14 3 Time from Generation of Maskable Interrupt Request to Servicing Minimum Time Maximum Time Note The wait time is maximum when an interrupt request is generated immediately before BT or BF instruction Remark 1 clock fcPu CPU clock When two or more maskable interrupt requests are generated at the same time they are acknowledged starting from the one assigned the highest priority by the priority specification flag A pending interrupt is acknowledged when the status where it can be acknowledged is set Figure 14 12 shows the algorithm of interrupt request acknowledgement When a maskable interrupt re
241. s By using SM78KOS the logic and performance of an application can be verified independently of hardware development even when the in circuit emulator is not used This enhances development efficiency and improves software quality Used in combination with optional device file DF789456 Part number 5 78 05 DF789456 File containing the information inherent to the device Device file Used in combination with the optional RA78KOS 78 05 and SM78KO0S Part number uSxxxxDF789456 Note DF789456 is a common file that can be used with RA78K0S 78 05 and SM78KO0S Remark the part number differs depending on the host machines and operating systems to be used LSxxxx8M78K0S AA13 PC 9800 series Japanese Windows 3 5 2HD FD IBM PC AT compatibles Japanese Windows 3 5 2HC FD English Windows Note Also operates under the DOS environment 314 User s Manual U15075EJ1VOUMOO APPENDIX EMBEDDED SOFTWARE The following embedded software is provided to perform the program development and maintenance of the 789426 789436 789446 789456 Subseries effectively 78 05 Subset OS conformed to uITRON Includes the nucleus of the MX78KO0S Task control OS event control and time control are performed In the task control task execution sequences are controlled to switch the task to be executed next Caution when used under PC environment gt The MX78KOS is a DOS
242. s an alternate function as the external interrupt input when the output level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore the interrupt mask flag should be set to 1 before using the output mode 268 User s Manual U15075EJ1V0UMO0 CHAPTER 14 INTERRUPT FUNCTIONS 3 External interrupt mode register 0 INTMO This register is used to specify a valid edge for INTPO to INTP2 INTMO is set with an 8 bit memory manipulation instruction RESET input sets INTMO to 00H Symbol Figure 14 4 Format of External Interrupt Mode Register 0 7 Address After reset R W we ES11 ES10 INTP1 valid edge selection Falling edge o nana ease Setting prohibited Both rising and falling edges o fo ramen T 1 Rising edge Pi fo r Cautions 1 Bits 0 and 1 must be set to 0 2 Before setting the INTM0 register be sure to set the relevant interrupt mask to 1 to disable interrupts After that clear 0 the interrupt request flag then set the interrupt mask flag to 0 to enable interrupts User s Manual U15075EJ1V0UM00 269 CHAPTER 14 INTERRUPT FUNCTIONS 4 External interrupt mode register 1 1 is used to specify a valid edge for INTP3 is set with an 8 bit memory ma
243. s and description 0 299 19 1 2 Description of Operation column u nnne enne 300 1971 3 Descriptionvof Flag aiio e e c PR mL e E e Sau ette 300 19 2 Operation List uen Drei es uqa cid 301 19 3 Instructions Listed by Addressing Type 306 APPENDIX DEVELOPMENT 5 309 Language Processing Software U 311 A 2 Flash Memory Writing Tools 312 Debugging TOGS uk u ka s u 313 A3 a E O 71 313 3 2 SOflWatQe s tede e Si bia tu id e a E E 314 User s Manual U15075EJ1VO0UMOO 15 APPENDIX EMBEDDED APPENDIX REGISTER INDEX C 1 Register Index Alphabetic Order of Register Name C 2 Register Index Alphabetic Order of Register Symbol 16 User s Manual U15075EJ1VOUMOO LIST OF FIGURES 1 5 Figure No Title Page 2 1 Pin Input Output Circuits REEL 45 3 1 Memory uPD789425 789435 nennen terrens enter enn enter entren nennen 47 3 2 Memory uPD789426 789436
244. se are the serial data pins of the serial interface d SCK20 This is the serial clock I O pin of the serial interface RxD20 TxD20 These are the serial data pins of the asynchronous serial interface 40 User s Manual U15075EJ1VOUMOO Caution f CHAPTER 2 PIN FUNCTIONS ASCK20 This is the serial clock input pin of the asynchronous serial interface When using P20 to P26 as serial interface pins the mode and output latch must be set according to the functions to be used For the details of the setting refer to Table 12 2 Settings of Serial Interface 20 Operating Mode 2 2 4 P30 to P33 Port 3 These pins constitute a 4 bit I O port In addition they also function as timer I O and external interrupt input Port 3 can be specified in the following operation mode in 1 bit units 1 2 In this mode P30 to P33 functions as 4 bit I O port Port 3 can be set in the input or output mode in 1 bit units by port mode register 3 PM3 When used as an input port use of an on chip pull up resistor can be specified by pull up resistor option register in 1 bit units Control mode In this mode P30 to P33 function as timer and external interrupt input a b c d TMI60 This is the external clock input pin to timer 60 TO50 TO60 TO61 These are the timer output pins of timer 50 and timer 60 CPT90 This is the capture edge input pin o
245. ship Between LCD Display Data Memory Contents and Segment Common Outputs uPD789446 789456 Subseries nie p te RE E B rene PESE HERE UMEN Rex 253 13 6 Common Sigrial Maveforiris 255 13 7 Voltages and Phases of Common and Segment 255 13 8 Three Time Slot LCD Display Pattern and Electrode n 256 13 9 Example of Connecting Three Time Slot LCD Panel enne 257 13 10 Three Time Slot LCD Drive Waveform nennen nennen tenens 258 13 11 Four Time Slot LCD Display Pattern and Electrode 259 13 12 Example of Connecting Four Time Slot LCD Panel ua 260 13 13 Four Time Slot LCD Drive Waveform nns 261 14 1 Basic Configuration of Interrupt Function nnne nennen nennen nennen nene 265 14 2 Format of Interrupt Request Flag 267 14 3 Format of Interrupt Mask Flag Registers eene nennen enne nennen enne 268 14 4 Format of External Interrupt Mode Register 0 269 14 5 Format of External Interrupt Mode Register 1 270 14 6 Configuration of Program Status WOoOrd 270 LIST OF FIGURES 5 5 Figur
246. statuses become undefined All other hardware remains unchanged after reset 2 The post reset values are retained in the standby mode 3 uPD789426 789436 Subseries only User s Manual U15075EJ1V0UMO0 289 CHAPTER 16 RESET FUNCTION Table 16 1 Hardware Status After Reset 2 2 LCD controller driver Display mode register LCDMO Clock control register LCDCO Voltage amplification control register m ita rept rm 290 User s Manual U15075EJ1V0UMO0 CHAPTER 17 078 9436 78F9456 The uPD78F9436 78F9456 are available as the flash memory versions of the wPD789426 789436 789446 and 789456 Subseries The uPD78F9436 is a version with the internal ROM of the uPD789426 and 789436 Subseries replaced with flash memory and the uPD78F9456 is a version with the internal ROM of the 789446 and 789456 Subseries replaced with flash memory The differences between the uPD78F9436 78F9456 and the mask ROM versions are shown in Table 17 1 Table 17 1 Differences Between 78F9456 and Mask ROM Versions Part Number Flash Flash Memory Version Version Mask ROM Version HPD78F9436 uPD78F9456 uPD789425 uPD789426 789445 uPD789446 789435 789436 789455 789456 Internal ____ 12 16 KB 12 16 KB 12 16 memory High speed 512 bytes IC pin Not provided Provided Electrical specifications Varies depending on flash memory or mask RO
247. ster each special function register has a special function The special function registers are allocated in the 256 byte area of FF00H to FFFFH Special function registers can be manipulated like general purpose registers by operation transfer and bit manipulation instructions The manipulatable bit units 1 8 and 16 differ depending on the special function register type The manipulatable bits can be specified as follows 1 bit manipulation Describes a symbol reserved by the assembler for the 1 bit manipulation instruction operand sfr bit This manipulation can also be specified with an address 8 bit manipulation Describes a symbol reserved by the assembler for the 8 bit manipulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describes a symbol reserved by the assembler for the 16 bit manipulation instruction operand When addressing an address describe an even address Table 3 4 lists the special function registers The meanings of the symbols in this table are as follows Symbol Indicates the addresses of the implemented special function registers The symbols shown in this column are the reserved words of the assembler and have already been defined in the header file called sfrbit h of the C compiler Therefore these symbols can be used as instruction operands if an assembler or integrated debugger is used RW Indicates whether the special function
248. t 0 of TCA60 before it is reloaded from NRZB60 Select either TO60 or TO61 as the timer output pin If TO60 is selected Set P32 to the output mode PM32 0 set the P32 output latch to 0 and set 60 to output enable TOE60 1 If TO61 is selected Set P33 to the output mode PM33 0 set the P33 output latch to 0 and set TOE61 to output enable TOE60 1 Enable the operation of TM50 and TM60 50 1 TCE60 1 The operation of the carrier generator is as follows 1 2 lt 3 gt lt 4 gt lt 5 gt When the count value of 60 matches the value 60 an interrupt request signal 60 is generated and output of timer 60 is inverted which makes the compare register switch from CR60 to CRH60 After that when the count value of TM60 matches the value set in CRH60 an interrupt request signal 60 is generated and output of timer 60 is inverted again which makes the compare register switch from CRH60 to CR60 The carrier clock is generated by repeating 1 and 2 above When the count value of TM50 matches the value set CR50 an interrupt request signal INTTM50 is generated The rising edge of INTTM50 is the data reload signal of NRZB60 and is transferred to NRZ60 When NRZ60 is 1 a carrier clock is output from the 60 pin or the TO61 pin Cautions 1 TCA60 cannot set with 1 bit memory manipulation instruction Be sure to use an 8 bit memory m
249. t data Power supply LCD power supply Programming power supply Ground Crystal main system clock Crystal subsystem clock 29 1 5 78K 0S Series Lineup CHAPTER 1 GENERAL The products in the 78K 0S Series are listed below The names enclosed in boxes are subseries names 44 pin 42 44 pin 30 pin 28 pin 44 pin 44 pin 30 pin 30 pin 30 pin 30 pin 30 pin 30 pin 44 78 05 Series 52 pin 144 pin 88 pin 80 pin 52 pin 52 pin 64 pin 44 pin 44 pin 20 pin 20 pin 30 uf Products in mass production Products under development Y Subseries products support SMB Small scale package general purpose applications 4PD789046 789026 HPD789074 with added subsystem clock HPD789014 with enhanced timer and increased ROM RAM capacity 4PD789026 with enhanced timer On chip UART and capable of low voltage 1 8 V operation Small scale package general purpose applications and A D converter 4uPD789177 HPD789167 789156 4 Dr CASE r 090789146 uPD789134A PD789124A P P 7 uPD789114A 789104 Inverter control uPD789871 UPD789456 7 D uPD789835 2 0 Z uPD789477 2 44 0789467 77 PD789803 4PD789800 7 uPD789861 190789860 4PD789177Y 4PD789167Y 4PD789167 with
250. tage and a voltage at a voltage tap comparison voltage received from the series resistor string starting from the most significant bit MSB Upon receiving all the bits down to the least significant bit LSB that is upon the completion of A D conversion the SAR sends its contents to A D conversion result register 0 ADCRO 2 A D conversion result register 0 ADCRO ADCRO holds the result of A D conversion Each time A D conversion ends the conversion result in the successive approximation register is loaded into ADCRO which is a 10 bit register ADCRO can be read with a 16 bit memory manipulation instruction RESET input makes ADCRO undefined ADCROH FF14H ADCROL FF14H Address After reset R W smo o Caution When the uPD78F9436 a flash memory version of the 789425 or 789426 is used this register can be accessed in 8 bit units However only an object file assembled with the 2 0789425 or uPD789426 be used The same is also true for the wPD78F9456 flash memory version of the 789445 or uPD789446 This register be accessed 8 bit units but only an object file assembled with the uPD789445 789446 be used 198 User s Manual U15075EJ1V0UMOO 3 4 5 6 7 8 CHAPTER 11 10 A D CONVERTER uPD789436 AND 789456 SUBSERIES Sample amp hold circuit The sample amp hold circuit samples consecutive
251. take place following the completion of MOV A r Figure 14 14 Interrupt Request Acknowledgment Timing When Interrupt Request Flag Is Generated in Final Clock Under Execution 8 clocks Clock ES pensi SS spes ET Pb es ups Saving PSW and PC and Interrupt servicing RES jump to interrupt servicing program Interrupt If the interrupt request flag XXIF is generated in the final clock of the instruction interrupt request acknowledgment processing will begin after execution of the next instruction is complete Figure 14 14 shows an example whereby an interrupt request was generated in the 2nd clock of NOP a 2 clock instruction In this case the interrupt request will be processed after execution of MOV A r which follows NOP is complete Caution When interrupt request flag registers 0 and 1 IFO and IF1 or interrupt mask flag registers 0 and 1 and MK1 are being accessed interrupt requests will be held pending 14 4 3 Multiple interrupt servicing Multiple interrupts in which another interrupt request is acknowledged while an interrupt request being serviced can be serviced using the priority order If multiple interrupts are generated at the same time they are serviced in the order according to the priority assigned to each interrupt request in advance refer to Table 14 1 User s Manual U15075EJ1VO0UMOO 275 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14 15 Example of Multiple I
252. ted The square wave output is cleared to 0 by setting TCEn0 to 0 Tables 7 5 and 7 6 show the square wave output range and Figure 7 15 shows the timing of square wave output Note the case of timer 60 either TO60 or TO61 can be selected as the timer output pin If TO61 is selected set TOE61 1 Caution Be sure to stop the timer operation before overwriting the count clock with different data Remark 5 6 Table 7 5 Square Wave Output Range of Timer 50 During fx 5 0 MHz Operation e o wee emo 1 fxr 30 5 2 eim 7 81 ms 1 fxr 30 5 Input cycle of 60 match Input cycle of timer 60 match Input cycle of timer 60 match signal signal x 8 signal ied Input cycle of timer 60 output nm cycle of timer 60 output Input cycle of timer 60 Remarks 1 fx Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency User s Manual U15075EJ1VO0UMOO 151 7 8 Table 7 6 Square Wave Output Range of Timer 60 During fx 5 0 MHz Operation TCL602 TCL601 TCL600 Minimum Pulse Width Maximum Pulse Width 6 1 fx 0 2 us 2 51 2 us 1 fx 0 2 us 4 2 fx 0 4 2 fx 1 02 ms 2 fx 0 4 us oo 1 o ____ oo 1 t ___ or mozno
253. ted after the oscillation stabilization time has elapsed The reset applied by the watchdog timer overflow is automatically cleared after reset and program execution is started after the oscillation stabilization time has elapsed see Figures 16 2 to 16 4 Cautions 1 For an external reset input a low level for 10 ws or more to the RESET pin 2 When the STOP mode is cleared by reset the STOP mode contents are held during reset input However the port pins become high impedance Figure 16 1 Block Diagram of Reset Function Reset controller Reset signal Count clock Watchdog timer Interrupt function User s Manual U15075EJ1V0UMO0 287 CHAPTER 16 RESET FUNCTION Figure 16 2 Reset Timing by RESET Input NND I AN VN Oscillation Reset period stabilization Normal operation oscillation stops time wait reset processing 1 1 i RESET N f 3 l l Internal reset signal MEE 1 1 Hi Z 2 a AIR SE SS ae Figure 16 3 Reset Timing by Overflow Watchdog Timer NE During normal Reset period Oscillation died Nan Normal operation stabilization 6 operation continues time wait reset processing watchdog timer 1 i Internal reset signal Hi Z PoOrpii uci Du Ier pee Figure 16 4 Res
254. terrupt disabled set TMMK90 bit 4 of interrupt mask flag register 1 MK1 to 1 2 Disable inversion control of timer output data set TOC90 to 0 If the value in CR90 is rewritten in the interrupt enabled state an interrupt request may occur at the moment of rewrite Table 6 2 Interval Time of 16 Bit Timer 208 TE ete 12 8 o 2 ES 3 _ __ ea Remarks 1 fx Main system clock oscillation frequency 2 Subsystem clock oscillation frequency 3 The parenthesized values apply to operation at fx 5 0 MHz or fxr 32 768 kHz User s Manual U15075EJ1VO0UMOO 123 6 16 Figure 6 6 Timing of Timer Interrupt Operation eec FU PL yA 90 count vale 0000H X 0001H 0000H 90 L s L t Interrupt acknowledgement Interrupt i N gt gt gt w acknowledgement TO90 S i _ 90 i Overflow flag set Remark N 0000H to FFFFH 124 User s Manual U15075EJ1VO0UMOO CHAPTER 6 16 BIT 6 4 2 Operation as timer output Timer outputs are repeatedly generated at the count value preset in 16 bit compare register 90 CR90 based on the intervals of the value set in TCL901 and TCL900 To operate the 16 bit timer as a timer output the following settings are required Set P26 to
255. tions that manipulate interrupt mask flag registers 0 1 and MK1 User s Manual U15075EJ1VO0UMOO 277 278 User s Manual U15075EJ1V0UMO0 CHAPTER 15 STANDBY FUNCTION 15 1 Standby Function and Configuration 15 1 1 Standby function The standby function is to reduce the power consumption of the system and can be effected in the following two modes 1 HALT mode This mode is set when the HALT instruction is executed The HALT mode stops the operation clock of the CPU The system clock oscillator continues oscillating This mode does not reduce the power consumption as much as the STOP mode but is useful for resuming processing immediately when an interrupt request is generated or for intermittent operations 2 STOP mode This mode is set when the STOP instruction is executed The STOP mode stops the main system clock oscillator and stops the entire system The power consumption of the CPU can be substantially reduced in this mode The data memory be retained at the low voltage 1 8 V Therefore this mode is useful for retaining the contents of the data memory at an extremely low current The STOP mode can be released by an interrupt request so that this mode can be used for intermittent operation However some time is required until the system clock oscillator stabilizes after the STOP mode has been released If processing must be resumed immediately by using an interrupt request therefore use the
256. tput Leave open W Input Independently connect to Voo via a resistor Output Leave open V 13 13 Connect directly to Voo or Vss Input Independently connect to Voo or Vss via a resistor Output Leave open Leave open Connect to Vss Leave open Connect to Vss 2 Notes 1 When using the uPD789426 and 789436 Subseries 2 When using the uPD789446 and 789456 Subseries 44 User s Manual U15075EJ1VOUMOO CHAPTER 2 PIN FUNCTIONS Figure 2 1 Pin Input Output Circuits Type 13 V Output data gt Output disable H Bech Vss IN OUT Input enable Schmitt triggered input with hysteresis characteristics Middle voltage input buffer Type 13 W Pull up resistor 7 gt mask option gt gt Output data gt Output disable H Neen IN OUT 77 Output Vss disable IN OUT Input enable Middle voltage input buffer Input enable Pull 2 Satis De IE Vpop c Data gt H P ch IN OUT Output disable Comparator EF gt VREF Threshold voltage User s Manual 1 15075 1 00 00 45 46 User s Manual U15075EJ1VOUMOO CHAPTER 3 CPU ARCHITECTURE 3 1 Memory Space The uPD789426 789436 789446 and 789456 Subseries can access 64 KB of memory space Figures 3
257. ts 0 to 3 6 and 7 must be set to 0 User s Manual U15075EJ1VO0UMOO 107 CHAPTER 5 CLOCK GENERATOR 5 4 System Clock Oscillators 5 4 1 Main system clock oscillator The main system clock oscillator is oscillated by the crystal or ceramic resonator 5 0 MHz TYP connected across the X1 and X2 pins An external clock can also be input to the circuit In this case input the clock signal to the X1 pin and input the inverted signal to the X2 pin Figure 5 5 shows the external circuit of the main system clock oscillator Figure 5 5 External Circuit of Main System Clock Oscillator a Crystal or ceramic oscillation b External clock External clock 2 108 User s Manual U15075EJ1V0UMO0 CHAPTER 5 CLOCK GENERATOR 5 4 2 Subsystem clock oscillator The subsystem clock oscillator is oscillated by the crystal resonator 32 768 kHz TYP connected across the XT1 and XT2 pins An external clock can also be input to the circuit In this case input the clock signal to the XT1 pin and input the inverted signal to the XT2 pin Figure 5 6 shows the external circuit of the subsystem clock oscillator Figure 5 6 External Circuit of Subsystem Clock Oscillator a Crystal oscillation b External clock Vss External sii p T XT1 clock 32 768 25 32 kHz 1 XT2 ii Crystal resonator Caution When using the main system or subsystem clock oscillator wi
258. u u 105 5 4 System Clock Oscillators guilde 108 5 4 1 Main system clock oscillator ennenee nennen nennen trennen antenne nnne 108 12 User s Manual U15075EJ1VOUMOO 542 S bsystem clock oscillator 2 cente dt enter tacet e ee edes 109 5 43 DiVider Pt oc backs e p ee 111 5 4 When no subsystem clock is used 111 5 5 Clock Generator Operation 112 5 6 Changing Setting of System Clock and CPU Clock 113 5 6 1 Time required for switching between system clock and CPU 113 5 6 2 Switching between system clock and CPU 114 CHAPTER 6 16 BIT I I Pase e RACE ced 115 6 1 16 Bit Timer Functions 1 u 115 6 2 16 Bit Timer Configuration 116 6 3 Registers Controlling 16 Bit
259. uction instructions SP SP 3 SP lt SP _2 SP lt SP 2 SP 3 PC7 to PCO SP 2 DS MM SP 2 PC7 to PCO SP 2 PC15 to PC8 register pairs _1 AL MNA SP 1 PC15 to PC8 SP 1 PSW register pairs A SP SP gt SP gt Figure 3 17 Data to Be Restored from Stack Memory POP rp RET instruction instruction instruction SP ditor baje SP PC7toPCO SP _ 710 PCO s 5 pairs SP 1 PC15 to PC8 SP 1 PC15 to PC8 SP SP 2 SP SP 2 SP 42 PSW SP SP 3 User s Manual 015075 63 3 3 2 2 General purpose registers The general purpose registers consist of eight 8 bit registers X A C B E D L and H Each register can be used as an 8 bit register or two 8 bit registers in pairs can be used as a 16 bit register AX BC DE and HL General purpose registers can be described in terms of function names X A C B E D L H AX BC DE or HL or absolute names RO to R7 and RPO Figure 3 18 General Purpose Register Configuration a Absolute names 16 bit processing 8 bit processing RP3 RP2 b Function names 16 bit processing 8 bit processing HL BC AX 64 User s Manual U15075EJ1VOUMOO CHAPTER 3 CPU ARCHITECTURE 3 2 3 Special function registers SFRs Unlike a general purpose regi
260. unter Figure 7 29 Timing of Operation as External Event Counter 8 Bit Resolution 60 input L CR60 00H TM60 00H 00H 00H 00H count value Interrupt request flag 170 User s Manual U15075EJ1V0UMO0 8 81 Watch Timer Functions The watch timer has the following functions e Watch timer e Interval timer The watch and interval timers can be used at the same time Figure 8 1 is a block diagram of the watch timer Figure 8 1 Block Diagram of Watch Timer 5 bit counter 7INTWT Clear Clear 9 bit prescaler fx 27 Selector fxr INTWTI Selector Watch timer mode control register WTM Internal bus 0 User s Manual U15075EJ1V0UMOO 171 CHAPTER 8 WATCH TIMER 1 Watch timer The 4 19 MHz main system clock or 32 768 kHz subsystem clock is used to issue an interrupt request INTWT at 0 5 second intervals Caution When the main system clock is operating at 5 0 MHz it cannot be used to generate a 0 5 second interval In this case the subsystem clock which operates at 32 768 kHz should be used instead 2 Interval timer The interval timer is used to generate an interrupt request INTWTI at specified intervals Table 8 1 Interval Generated Using the Interval Timer At fx 5 0 MHz At fx 4 19 MHz At fxr 32 768 kHz 2 x 1 fw 409 6 us 489
261. ure 6 1 Therefore when the main system clock oscillation is stopped the timer operation is stopped because the clock supplied to the 16 bit timer is stopped timer interrupt is not generated Moreover when the subsystem clock is selected as the count clock and BZOE90 is set to 1 the capture and TM90 read values are not guaranteed because the subsystem clock is not synchronized Therefore be sure to set BZOE90 to 0 when using the capture and TM90 read functions when the subsystem clock is selected as the count clock buzzer output capture and TM90 read functions cannot be used at the same time User s Manual U15075EJ1VO0UMOO 129 CHAPTER 6 16 BIT Make the following settings when stopping the main system clock oscillation to support low current consumption and releasing the HALT mode Count clock Subsystem clock CPU clock Subsystem clock Main system clock Oscillation stopped BZOE90 1 Buzzer output enabled At this time when the setting of P21 the buzzer output alternate function pin is PM21 0 P21 0 a square wave of the buzzer frequency is output from P21 To avoid outputting the buzzer frequency make either of the following settings e Set P21 to input mode 21 1 e If P21 cannot be set to input mode set the port latch value of P21 to 1 P21 1 In this case a high level is output from P21 130 User s Manual U15075EJ1V0UMOO 7 8 7 1 8 Bit Timer Funct
262. us 488 us 2 x 1 fw 819 2 us 978 us 977 us Remarks 1 fw Watch timer clock frequency fx 2 or fxr 2 fx Main system clock oscillation frequency 3 fxr Subsystem clock oscillation frequency 8 2 Watch Timer Configuration The watch timer includes the following hardware Table 8 2 Watch Timer Configuration Control register Watch timer mode control register WTM 172 Users Manual U15075EJ1VOUMOO CHAPTER 8 WATCH TIMER 8 3 Watch Timer Control Register The watch timer is controlled by the watch timer mode control register WTM Symbol 4 3 2 1 0 Watch timer mode control register WTM WTM selects a count clock for the watch timer and specifies whether to enable operation of the timer It also specifies the prescaler interval and how the 5 bit counter is controlled WTM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets WTM to 00H Figure 8 2 Format of Watch Timer Mode Control Register 7 6 5 Address After reset R W WTM7 Watch timer count clock selection 2 89 1 kHz fxr 32 768 kHz WTM6 WTM5 WTM4 Prescaler interval selection Co 7 o 7 o 1 emossa __ _ Setting prohibited WTM1 Control of 5 bit counter operation RUS Cleared after stop Started WTM0 Watch timer operation ED Operation disabled both prescaler and timer cleared Operation enabled 1 Remarks 1 fw Watch timer clock frequency fx 2 or fxr
263. ved the receive data in the shift register is transferred to reception buffer register 20 RXB20 and a reception completion interrupt INTSR20 is generated If an error occurs the receive data in which the error occurred is still transferred to RXB20 and INTSR20 is generated If the RXE20 bit is reset 0 during the receive operation the receive operation is stopped immediately In this case the contents of RXB20 and asynchronous serial interface status register 20 ASIS20 are not changed and INTSR20 is not generated Figure 12 9 Asynchronous Serial Interface Reception Completion Interrupt Timing START INTSR20 Caution Be sure to read reception buffer register 20 RXB20 even if a receive error occurs If 20 is not read an overrun error will occur when the next data is received and the receive error state will continue indefinitely User s Manual U15075EJ1VO0UMOO CHAPTER 12 SERIAL INTERFACE 20 e Receive errors The following three errors may occur during a receive operation a parity error framing error and overrun error After data reception an error flag is set in asynchronous serial interface status register 20 ASIS20 Receive error causes are shown in Table 12 7 It is possible to determine what kind of error occurred during reception by reading the contents of ASIS20 in the reception error interrupt servicing see Figures 12 9 and 12 10 The contents of ASIS20 are reset 0 by reading reception buffer registe
264. wPD789426 789436 789446 and 789456 Subseries are as follows 1 Automatic output of segment and common signals based on automatic display data memory read 2 Two different display modes 1 3 duty 1 3 bias 1 4 duty 1 3 bias 3 Four different frame frequencies selectable in each display mode 4 Operation with a subsystem clock Table 13 1 lists the maximum number of pixels that can be displayed in each display mode Table 13 1 Number of Segment Outputs and Maximum Number of Pixels Bias Method Time Slots Signals Maximum Number Maximum Number of Pixels Used of Segments 789426 789436 1 3 COMO to COM2 15 5 x 3 commons Subseries COMO to COM3 20 5 20 5 segments x 4 commons x 4 commons 789446 789456 COMO to COM2 45 15 segments x 3 commons Subseries COMO to COM3 60 15 segments x 4 commons 13 2 LCD Controller Driver Configuration The LCD controller driver includes the following hardware Table 13 2 Configuration of LCD Controller Driver Configuration Display outputs Segment signals 5 uPD789426 and 789436 Subseries 15 uPD789446 and 789456 Subseries Common signals 4 COM0 to COM3 Control registers LCD display mode register 0 LCDMO LCD clock control register 0 LCDCO LCD voltage amplification control register 0 User s Manual U15075EJ1VO0UMOO 247 CHAPTER 13 LCD CONTROLLER DRIVER 15 75 J AHD seuesqns 9
265. y manipulation instruction RESET input sets PUB3 to OOH Figure 4 21 Format of Pull Up Resistor Option Register B3 Symbol 7 6 5 4 lt 3 gt lt 2 gt lt gt lt 0 gt Address After reset R W PUB3 fo o PUB33 PUB31 FF33H 00H R W P3n on chip pull up resistor selection n 0 to 3 On chip pull up resistor not used 1 On chip pull up resistor used User s Manual U15075EJ1V0UMO0 99 CHAPTER 4 PORT FUNCTIONS 5 Pull up resistor option register B7 PUB7 Pull up resistor option register B7 PUB sets whether on chip pull up resistors on P70 to P72 are used or not On the port specified to use an on chip pull up resistor by PUBT the pull up resistor can be internally used only for bits set in the input mode No on chip pull up resistors can be used for the bits set in the output mode regardless of the setting of PUB7 This also applies to when the pins are used for alternate function is set with 1 bit or 8 bit memory manipulation instructions RESET input sets PUB7 to 00H Figure 4 22 Format of Pull Up Resistor Option Register B7 Symbol 7 6 5 4 3 2 lt gt lt 0 gt Address After reset R W PUB7 PUB72 PUB71 PUB70 FF37H 00H R W P7n on chip pull up resistor selection n 0 to 2 On chip pull up resistor not used On chip pull up resistor used 6 Pull up resistor option register B8 PUB8 Pull up resistor option register B8 8 sets whether on chi

NEC PD789426 789436 789446 789456 Subseries User Manual

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