intersil HI5760 handbook
Contents
1. DVpp 0 3V Maximum Junction Temperature i eed X50uA HOO PT TIE AVpp 0 3V Maximum Storage Temperature Range ERR 24mA Maximum Lead Temperature Soldering 10s SOIC Lead Tips Only 40 C to 85 C CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE 1 is measured with the component mounted on an evaluation PC board in free air Electrical Specifications AVpp DVpp 5V Vper Internal 1 2V IOUTFS 20mA Ta 25 C for All Typical Values HI5760 TA 40 C TO 85 C PARAMETER TEST CONDITIONS MIN TYP MAX UNITS SYSTEM PERFORMANCE Resolution 10 Bits Integral Linearity Error INL Best Fit Straight Line Note 7 1 0 5 1 LSB Differential Linearity Error DNL Note 7 0 5 0 25 0 5 LSB Offset Error log Note 7 0 025 0 025 FSR Offset Drift Coefficient Note 7 0 1 ppm FSR C Full Scale Gain Error FSE With External Reference Notes 2 7 10 2 10 FSR With Internal Reference Notes 2 7 10 1 10 FSR Full Scale Gain Drift With External Reference Note 7 3 50 FSR C With Internal Reference Note 7 gt2. Digital Inputs and Termination The H15760 digital inputs are guaranteed to CMOS levels However TTL compatibility can be achieved by lowering the supply voltage to 3V due to the digital threshold of the input buffer being approximately half of the supply voltage The internal register is updated on the rising edge of the clock To minimize reflections proper termination should be implemented If the lines driving the clock and the digital inputs are 509 lines then 509 termination resistors should be placed as close to the converter inputs as possible to the digital ground plane if separate grounds are used Ground Plane s If separate digital and analog ground planes are used then all of the digital functions of the device and their corresponding components should be over the digital ground plane and terminated to the digital ground plane The same is true for the analog components and the analog ground plane The converter will function properly with a single ground plane as the Evaluation Board is configured in this matter Refer to the Application Note on the HI5760 Evaluation Board for further discussion of the ground plane s upon availability Noise Reduction To minimize power supply noise 0 1uF capacitors should be placed as close as possible to the converter s power supply pins AVpp and DVpp Also should the layout be designed using separate digital and analog ground planes these capacitors should be terminated to t
3. 40 SFDR 71 4dBc IN A WINDOW 50 60 70 80 90 WA 100 0 5 15 1 45MHz DIV FIGURE 14 FOUR TONE CLOCK 100MSPS 10 5 fi 50MSPS 20 four 1 9 2 2 2 8 3 1MHz 30 COMBINED AMPLITUDE 0dBFS 40 SFDR 73 6dBc IN A WINDOW 50 60 70 80 90 TANYA 100 0 5 950kHz DIV 10 FREQUENCY MHz FIGURE 16 FOUR TONE CLOCK 50MSPS 0 4 0 2 0 0 2 0 4 0 200 400 600 800 1000 FIGURE 18 INTEGRAL NONLINEARITY 8 intersil HI5760 Typical Performance Curves 5V Power Supply Continued 160 155 150 145 140 135 130 POWER mW 125 120 115 110 105 0 20 40 60 80 100 120 CLOCK RATE MSPS FIGURE 19 POWER vs CLOCK RATE fci 10 lout 20mA Typical Performance Curves 3V Power Supply SFDR dBc SFDR dBc 80 75 70 65 60 55 50 0 02 04 06 08 1 12 14 16 18 2 OUTPUT FREQUENCY MHz FIGURE 20 SFDR vs fout CLOCK 5MSPS 0 2 4 6 8 10 12 14 16 18 20 OUTPUT FREQUENCY MHz FIGURE 22 SFDR vs fourt CLOCK 50MSPS SFDR dBc SFDR dBc 80 T T 75
4. TABLE 1 INPUT CODING vs OUTPUT CURRENT INPUT CODE D9 DO IOUTA mA IOUTB mA 11111 11111 20 0 10000 00000 10 10 00000 00000 0 20 Outputs IOUTA and IOUTB are complementary current outputs The sum of the two currents is always equal to the full scale output current minus one LSB If single ended use is desired a load resistor can be used to convert the output current to a voltage It is recommended that the unused output be either grounded or equally terminated The voltage developed at the output must not violate the output voltage compliance range of 0 3V to 1 25V should be chosen so that the desired output voltage is produced in conjunction with the output full scale current which is described above in the Reference section If a known line impedance is to be driven then the output load resistor should be chosen to match this impedance The output voltage equation is Vout lout X Ri oAD These outputs can be used in a differential to single ended arrangement to achieve better harmonic rejection The SFDR measurements in this data sheet were performed with a 1 1 transformer on the output of the DAC see Figure 1 With the center tap grounded the output swing of pins 21 and 22 will be biased at zero volts It is important to note here that the negative voltage output compliance range limit is 300mV imposing a maximum of 600mVp p amplitude with this configuration The loading as shown i
5. 100MSPS 10 100MSPS 40 four 9 95MHz 30 AMPLITUDE OdBFS SFDR 63dBc 40 14dB EXTERNAL 50 ANALYZER ATTENUATION 60 70 80 90 7100 t aos Wadi 110 5MHZ DIV 50 FREQUENCY MHz FIGURE 31 SINGLE TONE SFDR 10 r r 100MSPS 20 four 3 8 4 4 5 6 6 2MHz 1 30 COMBINED PEAK AMPLITUDE 0dBFS 40 SFDR 70 6dBc IN A WINDOW 50 60 70 80 790 fd QL AT UY 100 0 5 1 45MHz DIV 15 FREQUENCY MHz FIGURE 33 FOUR TONE CLOCK 100MSPS T 50MSPS four 1 9 2 2 2 8 3 1MHz COMBINED PEAK AMPLITUDE OdBFS SFDR 74 2dBc IN A WINDOW V A Al ng 950kHz DIV 10 FREQUENCY MHz FIGURE 35 FOUR TONE CLOCK 50MSPS 11 intersil HI5760 Typical Performance Curves 3V Power Supply continued 0 4 0 4 0 2 0 2 m do JLab Bo AN yal 0 2 0 2 0 4 0 4 0 200 200 600 800 1000 0 200 400 600 800 1000 CODE CODE FIGURE 36 DIFFERENTIAL NONLINEARITY FIGURE 37 INTEGRAL NONLINEARITY 76 74 72 70 68 Q 66 64 62 60 0 20 40 60 8
6. 70 65 60 1 2 3 4 5 6 7 8 9 10 OUTPUT FREQUENCY MHz FIGURE 21 SFDR vs CLOCK 25MSPS 80 i OdBFS 75 70 6dBFS 65 12dBFS 60 55 50 45 0 5 10 15 20 25 30 35 40 45 OUTPUT FREQUENCY MHz FIGURE 23 SFDR vs four CLOCK 100MSPS 9 intersil HI5760 Typical Performance Curves 3V Power Supply continued SFDR dBc SFDR dBc SFDR dBc 80 T OdBFS 75 70 65 6dBFS 60 12dBFS 55 15 20 25 30 35 40 45 50 OUTPUT FREQUENCY MHz FIGURE 24 SFDR vs fourt CLOCK 125MSPS 80 75 100MSPS 125MSPS 20 15 10 5 0 AMPLITUDE dBFS FIGURE 26 SFDR vs AMPLITUDE fci k fouT 5 80 2 5MHz 75 70 65 10MHz 60 20MHz 55 50 40MHz 45 2 4 6 8 10 12 14 16 18 20 lour MA FIGURE 28 SFDR vs Ig 7 CLOCK 100MSPS SFDR dBc SFDR dBc 80 75 70 65 125MSPS 60 55 50 45 25 20 AMPLITUDE dBFS FIGURE 25 SFDR vs AMPLITUDE fci K fQUT 10 75 70 e 25MSPS 3 38 3 63MHz 60 j 50MSPS 55 6 75 7 25MHz 100MSPS 50 13 5 14 5MHz m 125MSPS 16
7. SFOR tO Nyquist 60MSPS four 10 1MHz 30MHz Span Notes 4 7 50MSPS four 20 2MHz 25MHz Span Notes 4 7 50MSPS four 2 51MHz 25MHz Span Notes 4 7 50MSPS four 1 00MHz 25MHz Span Notes 4 7 50MSPS four 5 02MHz 25MHz Span Notes 4 7 s 68 dBc 25MSPS four 5 02MHz 25MHz Span Notes 4 7 VOLTAGE REFERENCE Internal Reference Voltage Vesapy Pin 18 Voltage with Internal Reference 1 04 1 16 1 28 V Internal Reference Voltage Drift 60 9 Internal Reference Output Current 0 1 Sink Source Capability Reference Input Impedance 1 MO Reference Input Multiplying Bandwidth Note 7 1 4 MHz 4 intersil HI5760 Electrical Specifications AVpp DVpp 5V Vper Internal 1 2V IOUTFS 20mA Ta 25 C for All Typical Values Continued HI5760 TA 40 C TO 85 C PARAMETER TEST CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS D9 DO CLK Input Logic High Voltage with Note 3 3 5 5 V 5V Supply Input Logic High Voltage with Note 3 2 1 3 V 3V Supply Viu Input Logic Low Voltage with Note 3 0 1 3 V 5V Supply Vi Input Logic Low Voltage with Note 3 0 0 9 V 3V Supply Vj Input Logic Current lij 10 10 I
8. segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time The five MSBs are represented by 31 major current sources of equivalent current The five LSBs are comprised of binary weighted current sources Consider an input waveform to the converter which is ramped through all the codes from 0 to 1023 The five LSB current sources would begin to count up When they reached the all high state decimal value of 31 and needed to count to the next code they would all turn off and the first major current source would turn on To continue counting upward the 5 LSBs would count up another 31 codes and then the next major current source would turn on and the five LSBs would all turn off The process of the single equivalent major current source turning on and the five LSBs turning off each time the converter reaches another 31 codes greatly reduces the glitch at any one switching point In previous architectures that contained all binary weighted current sources or a binary weighted resistor ladder the converter might have a substantially larger amount of current turning on and off at certain worst case transition points such as mid scale and quarter scale transitions By greatly reducing the amount of current switching at certain major transitions the overall glitch of the converter is dramatically reduced improving settling times and transient problems 14 intersil HI5760
9. 100 FSR C Full Scale Output Current lfs 2 4 20 mA Output Voltage Compliance Range Note 3 0 3 1 25 V DYNAMIC CHARACTERISTICS Maximum Clock Rate Note 3 125 2 2 Output Settling Time 0 2 1 LSB equivalent to 9 Bits Note 7 20 ns 0 1 41 2 LSB equivalent to 10 Bits Note 7 35 ns Singlet Glitch Area Peak Glitch Rj 250 Note 7 5 5 Output Rise Time Full Scale Step 1 0 ns Output Fall Time Full Scale Step 1 5 ns Output Capacitance 10 pF Output Noise IOUTFS 20mA 50 pA NHz IOUTFS 2mA 30 pA NHz 3 intersil HI5760 Electrical Specifications AVpp DVpp 5V Vper Internal 1 2V IOUTFS 20mA Ta 25 C for All Typical Values Continued HI5760 40 C TO 85 C PARAMETER TEST CONDITIONS MIN TYP MAX UNITS AC CHARACTERISTICS HI5760BIB 5760 125MHz Spurious Free Dynamic Range 125MSPS four 32 9MHz 10MHz Span Notes 4 7 gt 75 dBc 100MSPS four 5 04MHz 4MHz Span Notes 4 7 76 dBc 60MSPS four 10 1MHz 10MHz Span Notes 4 7 5 75 dBc 50MSPS four 5 02 2 2MHz Span Notes 4 7 76 i dBc 50MSPS four 1 00MHz 2MHz Span Notes 4 7 x 78 dBc Total Harmonic Distortion THD to 100MSPS four 2 00MHz Notes 4 7 71 dBc Nyquist 50MSPS four 2 00
10. 7 10 1MHz 40 SFDR 64dBc 14dB EXTERNAL ANALYZER ATTENUATION 95 1 4 g 5 m 8 60 760 z m 55 lt 70 80 50 90 45 40 4MHz 100 E dii a ee aa a aan 40 110 40 20 0 20 40 60 80 0 5MHz DIV 50 TEMPERATURE C FREQUENCY MHz FIGURE 11 SFDR vs TEMPERATURE CLOCK 100MSPS FIGURE 12 SINGLE TONE SFDR 7 intersil HI5760 Typical Performance Curves 5V Power Supply continued AMP dB 20 y ok amp MA ET 100MSPS fourt 2 6 3 2 3 8 4 4 5 6 6 2 6 8MHz 40 COMBINED PEAK AMPLITUDE 04 5 50 SFDR 67dBc IN A WINDOW 7 60 70 80 90 9 n oo MA TW TT E 1 95MHz DIV 0 4 0 2 100MSPS four 13 5 14 5MHz COMBINED PEAK AMPLITUDE OdBFS SFDR 62 9dBc 14dB EXTERNAL ANALYZER ATTENUATION 5MHz DIV FREQUENCY MHz FIGURE 13 TWO TONE CLOCK 100MSPS 50 FREQUENCY MHz FIGURE 15 EIGHT TONE CLOCK 100MSPS 20 0 200 400 600 800 1000 CODE FIGURE 17 DIFFERENTIAL NONLINEARITY 10 100MSPS 20 four 3 8 4 4 5 6 6 2MHz ET COMBINED PEAK AMPLITUDE 0dBFS
11. 9 18 1MHz 40 25 20 15 10 5 0 AMPLITUDE dBFS FIGURE 27 SFDR vs AMPLITUDE OF TWO TONES fci 7 SFDR dBc 80 75 70 65 60 6dBFS SINGLE 6dBFS DIFF 55 50 5 10 15 20 2 30 35 40 OUTPUT FREQUENCY MHz FIGURE 29 DIFFERENTIAL vs SINGLE ENDED CLOCK 100MSPS 10 intersil HI5760 Typical Performance Curves 3V Power Supply continued 80 75 2 5MHz 70 10 1MHz 65 t 5 60 a 55 50 40 4MHz 45 40 40 20 0 20 40 TEMPERATURE C 60 80 FIGURE 30 SFDR vs TEMPERATURE CLOCK 100MSPS 20 m 100MSPS four 13 5 14 5MHz 40 COMBINED PEAK AMPLITUDE OdBFS 50 SFDR 61 5dBc 14dB EXTERNAL 5 60 ANALYZER ATTENUATION a 70 80 90 100 Hy i 110 5MHz DIV 50 FREQUENCY MHz FIGURE 32 TWO TONE CLOCK 100MSPS 20 O T T T T fcLk 100MSPS 30 four 2 6 3 2 3 8 4 4 40 5 6 6 2 6 8MHz COMBINED PEAK 50 AMPLITUDE OdBFS SFDR 67 4dBc 5 60 IN A WINDOW a z E 0 80 90 N soo M n AA lg 110 0 5 1 95MHz DIV 20 FREQUENCY MHz FIGURE 34 EIGHT TONE CLOCK
12. Linearity 1 LSB Adjustable Full Scale Output Current 2mA to 20mA SFDR to Nyquist at 5MHz Output 68dBc Internal 1 2V Temperature Compensated Bandgap Voltage Reference Single Power Supply from 5V to 3V CMOS Compatible Inputs Excellent Spurious Free Dynamic Range Pb Free Available ROHS Compliant Applications Cable Modems Set Top Boxes Wireless Communications Direct Digital Frequency Synthesis Signal Reconstruction Test Instrumentation High Resolution Imaging Systems Arbitrary Waveform Generators NOTE Intersil Pb free products employ special Pb free material Pinout sets molding compounds die attach materials and 10096 matte tin plate termination finish which are RoHS compliant and compatible HI5760 SOIC TSSOP with both SnPb and Pb free soldering operations Intersil Pb free TOP VIEW products are MSL classified at Pb free peak reflow temperatures that meet or exceed the Pb free requirements of IPC JEDEC J STD 020 MSB 1 28 CLK D8 2 DVpp D7 3 26 DCOM D6 4 25 NC 05 5 24 AVpp D4 23 NC D3 22 OUTA D2 8 21 OUTB Di 20 ACOM DO LSB 10 19 COMP1 NC 11 18 FSADJ NC 12 REFIO NC 13 16 REFLO NC 14 15 SLEEP 1 CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures 1 888 INTERSIL or 321 724 7143 Intersil and design is a registered t
13. input This also aids the ability to resolve the specified error band without overdriving the oscilloscope Singlet Glitch Area is the switching transient appearing on the output during a code transition It is measured as the area under the overshoot portion of the curve and is expressed as a Volt Time specification Full Scale Gain Error is the error from an ideal ratio of 32 between the output current and the full scale adjust current through Rsgr Full Scale Gain Drift is measured by setting the data inputs to all ones and measuring the output voltage through a known resistance as the temperature is varied from to Tmax It is defined as the maximum deviation from the value measured at room temperature to the value measured at either or Tmax The units are ppm of FSR full scale range per degree C Total Harmonic Distortion THD is the ratio of the DAC output fundamental to the RMS sum of the first five harmonics Spurious Free Dynamic Range SFDR is the amplitude difference from the fundamental to the largest harmonically or non harmonically related spur within the specified window Output Voltage Compliance Range is the voltage limit imposed on the output The output impedance load should be chosen such that the voltage developed does not violate the compliance range Offset Error is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance Offset er
14. shown for reference only The lead width B as measured 0 36mm 0 014 inch or greater above the seating plane shall not exceed a maximum value of 0 61mm 0 024 inch 10 Controlling dimension MILLIMETER Converted inch dimen sions are not necessarily exact 28 3 MS 013 AE ISSUE C 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES 0 026 0 1043 235 265 A1 0 0040 0 0118 0 10 0 30 5 B 0 013 0 0200 0 33 0 51 9 0 0091 0 0125 0 23 0 32 D 0 6969 0 7125 17 70 18 10 3 E 0 2914 0 2992 7 40 7 60 4 e 0 05 BSC 1 27 BSC H 0 394 0 419 10 00 10 65 h 0 01 0 029 0 25 0 75 5 L 0 016 0 050 0 40 1 27 6 N 28 28 7 a 0 8 0 8 Rev 0 12 93 17 intersil HI5760 Thin Shrink Small Outline Plastic Packages TSSOP M28 173 28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A o07 12 A1 0 000 0 000 0 05 0 15 A2 0 081 0 051 0 80 1 05 b 0 0075 0 0118 0 19 0 30 9 0 0035 0 0079 009 0 20 D 0 378 0 386 9 60 9 80 3 E1 0 169 0 177 430 4 50 4 e 0 026 BSC 0 65 BSC E 0 246 0 256 625 6 50 Kb 0 10 0 004 C S L 0 0177 0 0295 0 45 0 75 N 28 28 NOTES a 0 80 0
15. 0 100 120 CLOCK RATE MSPS FIGURE 38 POWER vs CLOCK RATE fci 10 lout 20mA 12 intersil HI5760 Timing Diagrams GLITCH AREA 1 5 x W A 1 2 LSB ERROR BAND n HEIGHT H louT WIDTH W t ps a SEIT A f tpp FIGURE 39 OUTPUT SETTLING TIME DIAGRAM FIGURE 40 PEAK GLITCH AREA SINGLET MEASUREMENT METHOD tsu oo tsu 1 tsu H gt gt gt lup D9 DO louT Lg Ii t LI li t gt amp SETT e tpp lt SETT i i FIGURE 41 PROPAGATION DELAY SETUP TIME HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 13 imntersil HI5760 Definition of Specifications Integral Linearity Error INL is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve Differential Linearity Error DNL is the measure of the step size output deviation from code to code Ideally the step size should be 1 LSB A DNL specification of 1 LSB or less guarantees monotonicity Output Settling Time is the time required for the output voltage to settle to within a specified error band measured from the beginning of the output transition In the case of the HI5760 the measurement was done by switching from code 0 to 256 or quarter scale Termination impedance was 250 due to the parallel resistance of the output 500 and the oscilloscope s 500
16. 35 40 45 50 45 0 5 10 25 20 15 10 5 0 OUTPUT FREQUENCY MHz AMPLITUDE dBFS FIGURE 5 SFDR vs fourt CLOCK 125 5 5 FIGURE 6 SFDR vs AMPLITUDE fci k foyT 10 6 intersil HI5760 Typical Performance Curves 5V Power Supply Continued 80 75 25MSPS 75 70 3 38 3 63MHz 70 65 Wd 9 2 1 a m 60 50MSPS 60 6 75 7 25 2 e 55 lb 55 5 100MSPS 50 13 5 14 5MHz 50 45 125MSPS 45 16 9 18 1MHz 40 40 d on p Us E E 0 25 20 15 10 5 0 AMPLITUDE dBFS AMPLITUDE TOTAL PEAK POWER OF COMBINED TONES dBFS FIGURE 7 SFDR vs AMPLITUDE fci K fQuT 5 FIGURE 8 SFDR vs AMPLITUDE OF TWO TONES fc_k fout 7 75 75 70 2 5MHz 6dBFS DIFF 65 10MHz 65 OdBFS DIFF 8 60 20MHz a a 6 55 H 5 40MHz 50 s 6dBFS SINGLE 45 OdBFS SINGLE 40 45 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30 35 40 lour mA OUTPUT FREQUENCY MHz FIGURE 9 SFDR vs lour CLOCK 100MSPS FIGURE 10 DIFFERENTIAL vs SINGLE ENDED CLOCK 100MSPS 80 r r 0r 2 5 2 20 100MSPS four 9 95MHz 30 AMPLITUDE OdBFS
17. 9 8 1 These package dimensions are within allowable dimensions of Rev 0 6 98 JEDEC MO 153 AE Issue E 2 Dimensioning and tolerancing per ANSI Y14 5M 1982 3 Dimension D does not include mold flash protrusions or gate burrs Mold flash protrusion and gate burrs shall not exceed 0 15mm 0 006 inch per side 4 Dimension E1 does not include interlead flash or protrusions Inter lead flash and protrusions shall not exceed 0 15mm 0 006 inch per side 5 The chamfer on the body is optional If it is not present a visual index feature must be located within the crosshatched area L is the length of terminal for soldering to a substrate N is the number of terminal positions Terminal numbers are shown for reference only Dimension b does not include dambar protrusion Allowable dambar protrusion shall be 0 08mm 0 003 inch total in excess of b dimen sion at maximum material condition Minimum space between protru sion and adjacent lead is 0 07mm 0 0027 inch 10 Controlling dimension MILLIMETER Converted inch dimensions are not necessarily exact Angles in degrees All Intersil U S products are manufactured assembled and tested utilizing 1509000 quality systems Intersil Corporation s quality certifications can be viewed at www intersil com design quality Intersil products are sold by description only Intersil Corporation reserves the right to make chang
18. MHz Notes 4 7 71 dBc 50MSPS four 1 00MHz Notes 4 7 76 dBc Spurious Free Dynamic Range 125MSPS fourt 32 9MHz 62 5MHz Span Notes 4 7 54 dBc SEDR to Nyquist folk 125MSPS four 10 1MHz 62 5MHz Span Notes 4 7 64 dBc 100MSPS four 40 4MHz 50MHz Span Notes 4 7 52 dBc foLk 100MSPS four 20 2MHz 50MHz Span Notes 4 7 5 60 dBc 100MSPS four 5 04MHz 50MHz Span Notes 4 7 68 dBc foLk 100MSPS four 2 51MHz 50MHz Span Notes 4 7 74 dBc 60MSPS four 10 1MHz 30MHz Span Notes 4 7 50MSPS four 20 2MHz 25MHz Span Notes 4 7 5OMSPS four 2 51MHz 25MHz Span Notes 4 7 50MSPS four 5 02 2 25MHz Span Notes 4 7 68 dBc 50MSPS four 1 00MHz 25MHz Span Notes 4 7 AC CHARACTERISTICS HI5760 6IB 5760 6 60MHz Spurious Free Dynamic Range 60MSPS four 10 1MHz 10MHz Span Notes 4 7 75 dBc 50MSPS fourt 5 02MHz 2MHz Span Notes 4 7 76 dBc 50MSPS four 1 00MHz 2MHz Span Notes 4 7 78 dBc Total Harmonic Distortion THD to 50MSPS four 2 00MHz Notes 4 7 7i dBc Nyquist folk 50MSPS four 1 00MHz Notes 4 7 76 2 dBc Spurious Free Dynamic Range 60MSPS four 20 2MHz 30MHz Span Notes 4 7
19. es in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see www intersil com 18 intersil
20. he digital ground for DVpp and to the analog ground for AVpp Additional filtering of the power supplies on the board is recommended See the Application Note on the HI5760 Evaluation Board for more information upon availability Voltage Reference The internal voltage reference of the device has a nominal value of 1 2V with a 60 ppm C drift coefficient over the full temperature range of the converter It is recommended that a 0 1uF capacitor be placed as close as possible to the REFIO pin connected to the analog ground The REFLO pin 16 selects the reference The internal reference can be selected if pin 16 is tied low ground If an external reference is desired then pin 16 should be tied high to the analog supply voltage and the external reference driven into REFIO pin 17 The full scale output current of the converter is a function of the voltage reference used and the value of Rsgr should be within the 2mA to 20mA range through operation below 2mA is possible with performance degradation If the internal reference is used VEsAp will equal approximately 1 16V pin 18 If an external reference is used Vesap Will equal the external reference The calculation for lout Full Scale is lout Full Scale VEsApJ RsET X 32 If the full scale output current is set to 20mA by using the internal voltage reference 1 16V and a 1 86kQ Reet resistor then the input coding to output current will resemble the following
21. n Figure 1 will result in a 500mV signal at the output of the transformer if the full scale output current of the DAC is set to 20mA PIN 21 PIN 22 HI5760 FIGURE 42 Vout 2 X lout Req where Req is 12 50 15 intersil HI5760 Pin Descriptions PIN NO PIN NAME PIN DESCRIPTION 1 10 D9 MSB Through Digital Data Bit 9 Most Significant Bit through Digital Data Bit 0 Least Significant Bit DO LSB 11 14 NC No Connect Recommend ground 15 SLEEP Control Pin for Power Down mode Sleep Mode is active high Connect to ground for Normal Mode Sleep pin has internal 20uA active pulldown current 16 REFLO Connect to analog ground to enable internal 1 2V reference or connect to AVpp to disable internal reference 17 REFIO Reference voltage input if internal reference is disabled Reference voltage output if internal reference is enabled Use 0 1yF cap to ground when internal reference is enabled 18 FSADJ Full Scale Current Adjust Use a resistor to ground to adjust full scale output current Full Scale Output Current 32 x VEsApJ RsET 19 COMP1 For use in reducing bandwidth noise Recommended connect 0 1uF to AVpp 20 ACOM Analog Ground 21 IOUTB The complimentary current output of the device Full scale output current is achieved when all input bits are set to binary 0 22 IOUTA Current output of the device Full scale output current is achieved whe
22. n all input bits are set to binary 1 23 NC Internally connected to ACOM via a resistor Recommend leave disconnected Adding a capacitor to ACOM for upward compatibility is valid Grounding to ACOM is valid For upward compatibility to 12 bit and 14 bit devices pin 23 needs the ability to have a 0 1uF capacitor to 24 AVpp Analog Supply 3V to 5V 25 NC No Connect For upward compatibility to 12 and 14b devices pin 25 needs to be grounded to ACOM 26 DCOM Digital Ground 27 DVpp Digital Supply 3V to 5V 28 CLK Input for clock Positive edge of clock latches data 16 intersil HI5760 Small Outline Plastic Packages SOIC n SEATING PLANE pangan M ppano KOO NOTES 1 Symbols are defined in the MO Series Symbol List in Section 2 2 of Publication Number 95 2 Dimensioning and tolerancing per ANSI Y14 5M 1982 3 Dimension D does not include mold flash protrusions or gate burrs Mold flash protrusion and gate burrs shall not exceed 0 15mm 0 006 inch per side 4 Dimension E does not include interlead flash or protrusions In terlead flash and protrusions shall not exceed 0 25mm 0 010 inch per side 5 The chamfer on the body is optional If it is not present a visual index feature must be located within the crosshatched area L is the length of terminal for soldering to a substrate N is the number of terminal positions Terminal numbers are
23. nput Logic Current lj 10 10 Digital Input Capacitance 5 pF TIMING CHARACTERISTICS Data Setup Time See Figure 41 Note 3 ns Data Hold Time tj p See Figure 41 Note 3 3 ns Propagation Delay Time tpp See Figure 41 1 ns CLK Pulse Width tpw1 tpwo See Figure 41 Note 3 4 ns POWER SUPPLY CHARACTERISTICS AVpp Power Supply Note 8 2 7 5 0 5 5 DVpp Power Supply Note 8 2 7 5 0 5 5 V Analog Supply Current laypp 5V 3V IOUTFS 20mA 23 30 mA 5V or 3V IOUTFS 2mA 4 Digital Supply Current Ipypp 5V IOUTFS Don t Care Note 5 3 5 mA 3V IOUTFS Don t Care Note 5 1 5 mA Supply Current laypp Sleep Mode 5V or 3V IOUTFS Don t Care 1 6 3 mA Power Dissipation 5V IOUTFS 20mA Note 6 165 mW IOUTFS 2mA Note 6 70 mW 5V IOUTFS 20mA Note 9 150 mW 3 3V IOUTFS 20mA Note 9 75 mW 3V IOUTFS 20mA Note 6 85 mW 3V IOUTFS 20mA Note 9 67 mW JV IOUTFS 2mA Note 6 27 mW Power Supply Rejection Single Supply Note 7 0 2 40 2 96 FSR V NOTES 2 Gain Error measured as the error in the ratio between the full scale output current and the current through Rgg7 typically 625 Ideally the ratio should be 31 969 See Definition of Specifications ON DO do not have to be equal Parameter guaranteed by design or characterization and not production tested Spectral mea
24. rademark of Intersil Americas Inc Copyright Intersil Americas Inc 2003 2005 All Rights Reserved All other trademarks mentioned are the property of their respective owners HI5760 Typical Applications Circuit HI5760 11 14 25 15 SLEEP 16 REFLO D9 MSB 1 D8 2 D7 3 D6 4 D5 5 D4 6 D3 7 22 IOUTA D2 8 D1 9 DO LSB 10 17 REFIO 18 FSADJ 21 IOUTB CLK 28 23 NC 19 COMP1 DCOM 26 20 ACOM FERRITE BEAD FERRITE BEAD DVpp 27 24 AVDD Functional Block Diagram IOUTA IOUTB LSB DO D1 D2 D3 D4 SWITCH MATRIX D5 D6 D7 D8 MSB D9 CLK INT EXT INT EXT VOLTAGE REFERENCE SELECT REFERENCE AVpp DVpp DCOM REFLO REFIO 2kQ CASCODE CURRENT SOURCE 5 LSBs 31 MSB SEGMENTS BIAS GENERATION FSADJ SLEEP 45V OR 3V Vpp y COMP1 2 intersil HI5760 Absolute Maximum Ratings Digital Supply Voltage DVpp to DCOM Analog Supply Voltage AVpp to ACOM Grounds ACOM TO DCOM Digital Input Voltages D9 DO CLK SLEEP Internal Reference Output Current Reference Input Voltage Range Analog Output Current louT Operating Conditions Temperature Range Thermal Information iv petias tenete iet 45 5V Thermal Resistance Typical Note 1 I 5 5V SOIC 0 3V 0 3V TSSOP Package
25. ror is defined as the maximum deviation of the output current from a value of OmA Offset Drift is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance as the temperature is varied from Tmin to TMAX It is defined as the maximum deviation from the value measured at room temperature to the value measured at either or Tmax The units are ppm of FSR full scale range per degree C Power Supply Rejection is measured using a single power supply Its nominal 5V is varied 10 and the change in the DAC full scale output is noted Reference Input Multiplying Bandwidth is defined as the 3dB bandwidth of the voltage reference input It is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s The frequency is increased until the amplitude of the output waveform is 0 707 of its original value Internal Reference Voltage Drift is defined as the maximum deviation from the value measured at room temperature to the value measured at either Tmin or Tmax The units are ppm per degree C Detailed Description The HI5760 is a 10 bit current out CMOS digital to analog converter Its maximum update rate is 125MSPS and can be powered by either single or dual power supplies in the recommended range of 3V to 5V It consumes less than 165mW of power when using a 5V supply with the data switching at 100MSPS The architecture is based on a
26. surements made with differential coupled transformer Measured with the clock at 50MSPS and the output frequency at 1MHz Measured with the clock at 100MSPS and the output frequency at 40MHz 9 Measured with the clock at 60MSPS and the output frequency at 10MHz Itis recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V DVpp and AVpp 5 intersil HI5760 Typical Performance Curves 5V Power Supply 80 76 74 75 72 6dBFS 70 m 3 a a kJ 65 x 68 LI 12dBFS a a 66 60 64 55 62 OdBFS 50 60 0 02 04 06 08 1 12 14 16 18 2 1 2 3 4 5 6 7 8 9 10 OUTPUT FREQUENCY MHz OUTPUT FREQUENCY MHz FIGURE 1 SFDR vs fout CLOCK 5MSPS FIGURE 2 SFDR vs fout CLOCK 25MSPS 80 75 5 70 8 m 3 a 65 o 60 55 45 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30 35 40 45 OUTPUT FREQUENCY MHz OUTPUT FREQUENCY MHz FIGURE 3 SFDR vs fout CLOCK 50MSPS FIGURE 4 SFDR vs four CLOCK 100MSPS 80 25MSPS 75 50MSPS 1 5 10 100MSPS m B t 65 kJ Q o Q 60 o 55 50 1 15 20 25 30
27. x uar Data Sheet 10 Bit 125 60MSPS High Speed D A Converter The HI5760 is a 10 bit 125MSPS high speed low power D A converter which is implemented in an advanced CMOS process Operating from a single 3V to 5V supply the converter provides 20mA of full scale output current and includes edge triggered CMOS input data latches Low glitch energy and excellent frequency domain performance are achieved using a segmented current source architecture For an equivalent performance dual version see the HI5728 This device complements the HI5X60 family of high speed converters offered by Intersil which includes 8 10 12 and 14 bit devices Ordering Information PART TEMP PKG CLOCK NUMBER _ RANGE C PACKAGE NO SPEED HI5760BIB 40to85 28LdSOIC M28 3 125MHz HI5760BIBZ 40 to 85 28Ld SOIC M28 3 125MHz See Note Pb free 57601 40 to 85 28 Ld TSSOP 28 173 125 2 HI57601AZ 40 to 85 28 Ld TSSOP M28 173 125MHz See Note Pb free HI5760 6IB 40 85 28 Ld SOIC M28 3 60MHz HI5760 6IBZ 40 85 28Ld SOIC M28 3 60MHz See Note Pb free HI5760EVAL1 25 Evaluation Platform 125MHz Add T suffix for tape and reel HI5760 FN4320 8 March 30 2005 Features e Throughput Rate 125MSPS e Low Power 165mW at 5V 27mW at 3V Power Down Mode 23mW at 5V 10mW at 3V Integral
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