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ANALOG DEVICES ADP1850 handbookRev A

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1. sse 17 Input Capacitor Selection sse 18 Input FIG ua tert EP RUE 18 Boost Capacitor Selection sse 18 Ind ctor Selection iones Pe eene 18 Output Capacitor Selection see 19 MOSFET Selection ree HT e BRA IRURE 19 Loop Compensation Single Phase Operation 21 Configuration and Loop Compensation Dual Phase 22 Switching Noise and Overshoot Reduction 22 Voltage Tracking anai 23 Indepdendent Power Stage Input Voltage 24 PCB Layout Guidelines iter ttt 25 MOSFETs Input Bulk Capacitor and Bypass Capacitor 25 High Current and Current Sense 25 Signal Paths entere It HR RR ENS 25 PGND 25 Feedback and Current Limit Sense 25 Switch 26 Gate Driver Paths 26 Output 26 Typical Operating Circuits seen 27 Outline Dimensions iiie tbe ein 31 Ordering Guide iecore prn 31 Rev A Page 2 of 32 SPECIFICATIONS ADP1850 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control SQC Vin 12 V The specifications are valid for Tj 40 C to 125 C unless otherwise specified Typical values are
2. 10V M2ms A CH1 11 2V CH3 500mV CH4 10A 09440 029 Figure 28 Current Limit Hiccup Mode 20 A Current Limit ADP1850 SHUTDOWN CONTROL The 1 and EN2 pins are used to enable or disable Channel 1 and Channel 2 of the ADP1850 The precision enable minimum threshold for EN1 EN2 is 0 57 V When the voltage at EN1 EN2 rises above the threshold voltage the ADP1850 is enabled and starts normal operation after the soft start period And when the voltage at EN1 EN2 drops typically 30 mV hysteresis below the threshold voltage the switchers and the internal circuits in the ADP1850 are turned off Note that EN1 EN2 cannot shut down the LDO at VCCO which is always active For the purpose of start up power sequencing the startup of the ADP1850 can be programmed by connecting an appropriate resistor divider from the master power supply to the EN1 EN2 pin as shown in Figure 29 For instance if the desired start up voltage from the master power supply is 10 V R1 and R2 can be set to 156 and 10 respectively MASTER SUPPLY VOLTAGE Vout 09440 030 Figure 29 Optional Power Up Sequencing Circuit THERMAL OVERLOAD PROTECTION The ADP1850 has an internal temperature sensor that senses the junction temperature of the chip When the junction temperature of the ADP1850 reaches approximately 155 C the ADP1850 goes into thermal shutdown the converter is turned off and SS discharges toward zero through an intern
3. Rev A Page 10 of 32 CH1 10V 2V M10ms CH2 3 76V 2V CH4 2V Q 09440 014 Figure 13 Thermal Shutdown Waveform REFERENCED AT 2 75V 600kHz 300kHz TEMPERATURE Figure 15 fsw vs Temperature 09440 015 09440 016 ADP1850 350 25 C OUTPUT IS LOADED HS FET BSCO80NO3LS 300 LS FET BSCO30N03LS DH MINIMUM OFF TIME 250 vo 2 200 lt 150 A DH MINIMUM ON TIM 100 DEAD TIME BETWEEN SW FALLING EDGE 50 AND DL RISING EDGE INCLUDING DIODE RECOVERY TIME 2 5 5 0 7 5 100 125 15 0 17 5 200 0 5 10 15 20 amp Vin 3 Vin V 3 Figure 16 Typical DH Minimum On Time and Off Time Figure 19 Dead Time vs 4 600 Vin 2 75V TO 20V 2 580 5 3 DH MINIMUM OFF TIME 560 z 2 A E 540 Lu 9 1 z 520 DH MINIMUM ON TIME a S o 500 gt z 480 1 460 o 2 z 440 5 3 420 E 400 40 15 10 35 60 85 110 135 5 40 15 10 35 60 85 110 135 8 TEMPERATURE E TEMPERATURE 3 Figure 17 DH Minimum On Time and Off Time Over Temperature Figure 20 Gm of Error Amplifier vs Temperature 35 4 5 Vin 12V 34 OUTPUT IS LOA
4. to simplify calculation Cc is ignored for the stability compensation analysis 09440 034 Figure 33 Compensation Components The open loop gain transfer function at angular frequency s is given by G Ga x E x Zcomp S X Zu salis 1 OUT where is the transconductance of the error amplifier 500 uS Gcs is the tranconductance of the power stage Zcowp is the impedance of the compensation network is the impedance of the output filter Vrer 0 6 V Gcs with units of A V is given by 1 Gos 2 Acs Rpson where Acsis the current sense gain of either 3 V V 6 V V 12 V V or 24 V V set by the gain resistor between DLx and PGNDx Rpson mn is the low side MOSFET minimum on resistance If a sense resistor Rs is added in series with the low side FET then Gcs becomes 1 Acs Rpson_min Bs Ges Because the zero produced by the ESR of the output capacitor is not needed to stabilize the control loop assuming ESR is small the ESR is ignored for analysis Then Zener is given by 1 E 3 FILTER sC OUT Z Because Cc is small relative to Ccomp Zcow can be simplified to 1 1 5 X comp 4 SCcomp SCcomp Z ADP1850 At the crossover frequency the open loop transfer function is unity or 0 dB fcross 1 Combining Equation 1 and Equation 3 2 at the crossover frequency can be written as
5. 3 V 2 Q DHx Maximum Duty Cycle fsw 300 kHz 90 96 DHx Maximum Duty Cycle fsw 1500 kHz 50 96 Minimum DHx On Time fsw 200 kHz to 1500 kHz 135 ns Minimum DHx Off Time fsw 200 kHz to 1500 kHz 335 ns Minimum DLx On Time fsw 200 kHz to 1500 kHz 285 ns COMPx VOLTAGE RANGE COMPx Pulse Skip Threshold VcomeTHRES In pulse skip mode 0 9 V COMPx Clamp High Voltage VcoweHicH 2 25 V THERMAL SHUTDOWN Thermal Shutdown Threshold 155 C Thermal Shutdown Hysteresis 20 C OVERVOLTAGE AND POWER GOOD THRESHOLDS FBx Overvoltage Threshold Vov Vrs rising 0 635 0 65 0 665 V FBx Overvoltage Hysteresis 30 mV FBx Undervoltage Threshold Vrs falling 0 525 0 55 0 578 V FBx Undervoltage Hysteresis 30 mV TRKx INPUT VOLTAGE RANGE 0 5 V FBx TO TRKx OFFSET VOLTAGE 0 1 V to 0 57 V offset 10 0 10 mV SOFT START SSx Output Current Iss During start up 4 6 6 5 8 4 uA SSx Pull Down Resistor During a fault condition 3 kQ FBx to SSx Offset Vss 0 1 V to 0 6 V offset Vrs Vss 10 10 mV PGOODx PGOODx Pull up Resistor Recoob Internal pull up resistor to VCCO 12 5 PGOODx Delay 12 Hs Over Voltage or Under Voltage This is the minimum duration required to trip 10 us the PGOOD signal Minimum Duration ILIM1 ILIM2 Threshold Voltage Relative to PGNDx 5 0 5 mV ILIM1 ILIM2 Output Current ILIMx PGNDx 47 50 53 Current Sense Blanking Period After DLx goes high current limit is not sensed 100 ns during this perio
6. energy efficiency at light load and standby conditions The accurate current limit 6 allows the power architect to design within a narrower range of tolerances and can reduce overall converter size and cost The ADP1850 provides a configurable architecture capable of wide range input operation to provide the designer with maximum re use opportunities and improved time to market Additional flexibility is provided by external programmability of loop compensation soft start frequency setting power saving mode current limit and current sense gain can all be programmed using external components The ADP1850 includes a high level of integration in a small size package The start up linear regulator and the boot strap diode for the high side drive are included Protection features include undervoltage lock out overvoltage overcurrent short circuit and over temperature The ADP1850 is available in a compact 32 lead LFCSP 5 mm x 5 mm thermally enhanced package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2010 2012 Analog Devices Inc All rights reserved ADP1850 TABLE OF CONTENTS Features EE 1 Applications veniae ten 1 General Descriptions oerte tits eie 1 Typical Operation Circuit essent 1 R vision Histoby 2 Sp cifications etre ette te t t tere 3 Abso
7. Efficiency Plot of Figure 44 Figure 7 LDO Line Regulation 0 01 0 1 1 10 100 LOAD A 09440 005 09440 008 1 8V PSM EFFICIENCY e o VCCO V Vo 5 PWM 1 8V PWM 1 Vin 12V 750kHz 0 01 0 1 1 10 LOAD 0 1 2 3 4 5 Vin V Figure 5 Efficiency Plot of Figure 45 Figure 8 VCCO vs 100mA LOAD 09440 006 09440 009 0 05 b 50mA LOAD AVCCO V b 0 20 0 25 2 2 5 3 0 3 5 4 0 4 5 50 5 10V CH2 10V 1 5 60 5 Vin V i Figure 6 LDO Load Regulation Figure 9 An Example of Synchronization 600 kHz Rev A Page 9 of 32 ADP1850 _____ 8A 13A STEP LOAD OUTPUT RESPONSE CH1 20mV By M200ys 11 5A CH4 5AQ Figure 10 Step Load Transient of Figure 44 DH1 DL1 j VOUT1 IL1 Vin 12V Vour 1 8V OUTPUT PRECHARGED TO 1V CH1 5V 5V Mims 24V 1V 1AQ Figure 11 Soft Start into Precharged Output SS CH4 B 1v CH1 10V CH2 2V M10ms 2 7 1 52V Figure 12 Enable Start Up Function 09440 011 09440 012 09440 013 CHANGE IN few 96 CHANGE IN fey
8. SENSE AMPLIFIER OVER LIM1 CONTROL Figure 2 Rev A Page 6 of 32 09440 003 ADP1850 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EN1 1 sw1 SYNC 2 DH1 VIN 3 ADP1850 PGND1 VCCO 4 TOP VIEW DL1 VDL 5 Not to Scale DL2 AGND 6 cC PGND2 FREQ 7 DH2 EN2 8 Sw2 NOTES 1 CONNECT THE BOTTOM EXPOSED PAD OF THE LFCSP PACKAGE TO SYSTEM AGND PLANE 09440 004 Figure 3 Pin Configuration Table 3 Pin Function Descriptions Pin No Mnemonic Description 1 1 Enable Input for Channel 1 Drive EN1 high to turn on the Channel 1 controller and drive EN1 low to turn off the Channel 1 controller Tie EN1 to VIN for automatic startup For a precision UVLO put an appropriately sized resistor divider from VIN to AGND and tie the midpoint to this pin 2 SYNC Frequency Synchronization Input Accepts an external signal between 1x and 2 3x of the internal oscillator frequency fsw set by the FREQ pin The controller operates in forced PWM when a signal is detected at SYNC or when SYNC is high The resulting switching frequency is of the SYNC frequency When SYNC is low or left floating the controller operates in pulse skip mode For dual phase operation connect SYNC to a logic high or an external clock 3 VIN Connect to Main Power Supply Bypass with a 1 uF or larger ceramic capacitor connected as close to this pin as possible and PGNDx 4 VCCO Output of the Internal Low Dropout Regulator LDO Bypass VCCO to
9. Vsp is the switching point where the MOSFET fully conducts this voltage can be estimated by inspecting the gate charge graph given in the MOSFET data sheet is the on resistance of the ADP1850 internal driver given in Table 1 when charging the MOSFET is the on resistance of the ADP1850 internal driver given in Table 1 when discharging the MOSFET is the on gate resistance of MOSFET given in the MOSFET data sheet If an external gate resistor is added add this external resistance to Reare The total power dissipation of the high side MOSFET is the sum of conduction and transition losses Pus Po P The synchronous rectifier or low side MOSFET carries the inductor current when the high side MOSFET is off The low side MOSFET transition loss is small and can be neglected in the calculation For high input voltage and low output voltage the low side MOSFET carries the current most of the time Therefore to achieve high efficiency it is critical to optimize the low side MOSFET for low on resistance In cases where the power loss exceeds the MOSFET rating or lower resistance is required than is available in a single MOSFET connect multiple low side MOSFETs in parallel The equation for low side MOSFET conduction power loss is Pas X Rpsoy 08 There is also additional power loss during the time known as dead time between the turn off of the high side switch and the
10. absolute maximum rating conditions for extended periods may affect device reliability Absolute maximum ratings apply individually only not in combination Unless otherwise specified all other voltages are referenced to GND ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Measured with exposed pad attached to PCB Junction to ambient thermal resistance of the package was calculated or simulated on multilayer PCB The junction temperature of the device is dependent on the ambient temperature Ta the power dissipation of the device Pp and the junction to ambient thermal resistance of the package Maximum junction temperature is calculated from the ambient temperature and power dissipation using the formula T Ta Po x Rev A Page 5 of 32 ADP1850 SIMPLIFIED BLOCK DIAGRAM VIN vcco DUPLICATE FOR CHANNEL 2 ERROR AMPLIFIER DRIVER LOGIC OVER_LIM1 CONTROL AND STATE oxi MACHINE O 5V FAULT LOSIC EN1 OVER LIM1 PWM ZERO CROSS COMPARATOR DETECT SLOPE COMP AND CS GAIN GENERATOR 8 12 24 CURRENT
11. below the minimum on time condition the slave channel operates in pulse skip mode while keeping the output regulated and tracked to the master channel Also when TRKx or FBx drops below the PGOOD undervoltage threshold the PGOOD signal gets tripped and becomes active low MASTER VOLTAGE SLAVE VOLTAGE VOLTAGE V 09440 038 TIME Figure 38 Ratiometric Tracking 3 3V EN Vour1 MASTER EN2 ADP1850 49 9kO 0 55V RrRKB 10kO 8 lt od lt 09440 039 Figure 39 Example of a Ratiometric Tracking Circuit Rev A Page 23 of 32 ADP1850 Another ratiometric tracking configuration is having the slave channel rise more quickly than the master channel as shown in Figure 40 and Figure 41 The tracking circuits in Figure 39 and Figure 41 are virtually identical with the exception that gt as shown in Figure 41 MASTER VOLTAGE 2 SLAVE VOLTAGE a 9 gt 3 TIME 4 Figure 40 Ratiometric Tracking Slave Channel Has a Faster Ramp Rate 3 3V EN Vour4 MASTER 1 2 ADP1850 QTRK1 FB1 RrRKT 5 2 2 RrRKB 10 09440 041 VouT2_SLAVE Figure 41 Example of a Ratiometric Tracking Circuit Slave Channel Has a Faster Ramp Rate INDEPDENDENT POWER STAGE INPUT VOLTAGE In addition to the single power supply configuration the power stage input voltage of the dc to dc converter can come f
12. resistance The gate charging loss is approximated by the equation Ps EV x Qc fow where is the gate driver supply voltage Qc is the MOSFET total gate charge Note that the gate charging power loss is not dissipated in the MOSFET but rather in the ADP1850 internal drivers This power loss should be taken into consideration when calculating the overall power efficiency Rev A Page 19 of 32 ADP1850 The high side MOSFET transition loss is approximated by the equation Pom Vin X X tg tg X fow T E 2 where Pris the high side MOSFET switching loss power tris the rise time in charging the high side MOSFET tr is the fall time in discharging the high side MOSFET tr and tr can be estimated by 1 DRIVER RISE DRIVER FALL where Ocsw is the gate charge of the MOSFET during switching and is given in the MOSFET data sheet Inriver and Ipriver rar are the driver current put out by the ADP1850 internal gate drivers If Qcsw is not given in the data sheet it can be approximated by where and Qas are the gate to drain and gate to source charges given in the MOSFET data sheet Ipriver rise and Ipriver rau be estimated by Vp DRIVER RISE R ON SOURCE V SP R GATE I DRIVER FALL Ron D where Vppis the input supply voltage to the driver and is between 2 75 V and 5 V depending on the input voltage
13. that the internal minimum amplified voltage is above 0 4 V and the maximum amplified voltage Vcsmax is 2 1 V Note that or Vcsmax is not the same as Vcomp which has a range of 0 85 V to 2 25 V Make sure that the maximum Vcomp Vcompmax does not exceed 2 2 V to account for temperature and part to part variations See the following equations for Vcsmax and 0 75 i 2 V xR CSMIN LPP pson _ X Acs 1 Vesmax 0 75 V 1 7 5 Tipp Rpson X Acs Vy 0 2 100 pF x Rp where Vcsm is the minimum amplified voltage of the internal current sense amplifier at zero output current is the maximum amplified voltage of the internal current sense amplifier at maximum output current Rpson uix is the low side MOSFET minimum on resistance The zero current level voltage of the current sense amplifier is 0 75 V Irr is the peak to peak ripple current in the inductor is the maximum output dc load current is the maximum voltage at the COMP pin 100 pF is an internal parameter tow is the high side driver DH on time Rev A Page 17 of 32 ADP1850 INPUT CAPACITOR SELECTION The input current to a buck converter is a pulse waveform It is zero when the high side switch is off and approximately equal to the load current when it is on The input capacitor carries the input ripple c
14. the Current Sense Gain section for more details Roson is temperature dependent and can vary as much as 0 4 C Choose Rosos at the maximum operating temperature The voltage at RAMPx is fixed at 0 2 V and the current going into RAMPx should be between 10 uA and 160 uA Make sure that the following condition is satisfied Viy 70 2 V 10 uA 160 uA RAMP For instance with an input voltage of 12 V Rramp should not exceed 1 1 If the calculated Reamp produces less than 10 uA then select an Rram value that produces between 10 uA and 15 uA Figure 31 illustrates the connection ofthe slope compensation resistor and the current sense gain resistor Rcsc ADP1850 09440 032 Figure 31 Slope Compensation and CS Gain Connection SETTING THE CURRENT SENSE GAIN The voltage drop across the external low side MOSFET is sensed by a current sense amplifier by multiplying the peak inductor current and the Roson of the MOSFET The result is then amplified by a gain factor of either 3 V V 6 V V 12 V V or 24 V V which is programmable by an external resistor connected to the DLx pin This gain is sensed only during power up and not during normal operation The amplified voltage is summed with the slope compensation ramp voltage and fed into the PWM controller for a stable regulation voltage The voltage range of the internal node Vcs is between 0 4 V and 2 2 V Select the current sense gain such
15. turn on of the low side switch when the body diode of the low side MOSFET conducts the output current The power loss in the body diode is given by X p X fsw X Io where Vris the forward voltage drop of the body diode typically 0 7 V tp is the dead time in the ADP1850 typically 30 ns when driving some medium size MOSFETs with input capacitance Cis of approximately 3 nF The dead time is not fixed Its effective value varies with gate drive resistance and Cis so increases in high load current designs and low voltage designs Then the power loss in the low side MOSFET is Pors Psopypiopr Note that MOSFET Roson increases with increasing tempera ture with a typical temperature coefficient of 0 4 C The MOSFET junction temperature Tj rise over the ambient temperature is Tj Tat Pp where is the thermal resistance of the MOSFET package Ta is the ambient temperature 18 the total power dissipated in the MOSFET Rev A Page 20 of 32 LOOP COMPENSATION SINGLE PHASE OPERATION As with most current mode step down controller a transcon ductance error amplifier is used to stabilize the external voltage loop Compensating the ADP1850 is fairly easy an RC compen sator is needed between COMPx and AGND Figure 33 shows the configuration of the compensation components Rcomp Ccomp and Because Cc is very small compared to
16. 1 BST1 09440 035 Figure 35 Application Circuit with a Snubber Rev A Page 22 of 32 VOLTAGE TRACKING The ADP1850 includes a tracking feature that tracks a master voltage This feature is especially important when the ADP1850 is providing separate power supply voltages to a single integrated circuit such as the core and I O voltages of a DSP FPGA or microcontroller In these cases improper sequencing can cause damage to the load IC In all tracking configurations the output can be set as low as 0 6 V for a given operating condition The soft start time setting of the master voltage should be longer than the soft start of the slave voltage This forces the rise time of the master voltage to be imposed on the slave voltage If the soft start setting of the slave voltage is longer the slave comes up more slowly and the tracking relationship is not seen at the output Two tracking configurations are possible with the ADP1850 coincident and ratiometric trackings Coincident Tracking The most common application is coincident tracking used in core vs I O voltage sequencing and similar applications Coincident tracking forces the slave output voltages ramp rate to be the same as the master s until the slave output reaches its regulation Connect the slave TRKx input to a resistor divider from the master voltage that is the same as the divider used on the slave FBx pin This forces the slave volt
17. 27 PGOODI Power Good Open drain power good indicator logic output with an internal 12 kO resistor connected between PGOOD and VCCO PGOODI is pulled to ground when the Channel 1 output is outside the regulation window An external pull up resistor is not required 28 SS1 Soft Start Input for Channel 1 Connect a capacitor from SS1 to AGND to set the soft start period This node is internally pulled up to 5 V with a 6 5 pA current source 29 RAMP1 Connect a resistor from RAMP1 to VIN to set up a ramp current for slope compensation in Channel 1 The voltage at RAMP2 is 0 2 V This pin is high impedance when the channel is disabled 30 COMP1 Compensation Node for Channel 1 Output of Channel 1 error amplifier Connect a series resistor capacitor network from COMP1 to AGND to compensate the regulation control loop 31 FB1 Output Voltage Feedback for Channel 1 Connect to Output 1 via a resistor divider 32 TRK1 Tracking Input for Channel 1 Connect TRK1 to VCCO if tracking is not used 33 Exposed Pad Connect the bottom exposed pad of the LFCSP package to the system AGND plane EPAD EPAD Rev A Page 8 of 32 ADP1850 TYPICAL PERFORMANCE CHARACTERISTICS 100 100mA LOAD 3 3V PWM lt EFFICIENCY e 5 VCCO V Vin 12V 600 2 5 7 9 11 13 15 17 Vin V Figure 4
18. 2nx f Cour XV Z coup 1 NN our 5 The zero produced by and Ccow is 1 fno 6 27 X At the crossover frequency Equation 4 can be shown as 4 fzero2 7 f CROSS 2 cou f cnoss Rcomp Combining Equation 5 and Equation 7 and solving for gives R _ fcross Ces Son x Vour 8 COMP 4 Jers x Ges REF Choose the crossover and zero frequencies as follows 12 9 _ Ssw 2 55 _ JSW_ 10 ZERO 4 48 10 Substituting Equation 2 Equation 9 and Equation 10 into Equation 8 yields 21x Ros 0 97 Awe Saos OUT OUT 11 where Gm is the transconductance of the error amplifier 500 uS Acs is the current sense gain of 3 V V 6 V V 12 V V or 24 V V Roson is on resistance of the low side MOSFET Vrer 0 6 V And combining Equation 6 and Equation 10 yields 2 Coop z ZF 12 X fcross Note that the previous simplified compensation equations for and Ccowp yield reasonable results in fcross and phase margin assuming that the compensation ramp current is ideal Varying the ramp current or deviating the ramp current from ideal can affect fcross and phase margin And lastly set Cc to 1 1 50 come lt Sip me 13 Rev A Page 21 of 32 ADP1850 CONFIGURATION AND LOOP COMPENSATION DUA
19. 4 fsw kHz Figure 23 Rrreo vs Rev A Page 12 of 32 MODES OF OPERATION The SYNC pin is a multifunctional pin PWM mode is enabled when SYNC is connected to VCCO or a high logic With SYNC connected to ground or left floating the pulse skip mode is enabled Switching SYNC from low to high or high to low on the fly causes the controller to transition from forced PWM to pulse skip mode or pulse skip mode to forced PWM respec tively in two clock cycles Table 5 Mode of Operation Truth Table SYNC Pin Mode of Operation Low Pulse skip mode High Forced PWM or two phase operation No Connect Pulse skip mode Clock Signal Forced PWM or two phase operation The ADP1850 has a pulse skip sensing circuitry that allows the controller to skip PWM pulses thus reducing the switching frequency at light loads and therefore maintaining high efficiency during a light load operation The switching frequency is a fraction of the natural oscillator frequency and is automatically adjusted to regulate the output voltage The resulting output ripple is larger than that of the fixed frequency forced PWM Figure 24 shows that the ADP1850 operates in PSM under a very light load Pulse skip frequency under light load is dependent on the inductor output capacitance output load and input and output voltages UT RIPPLE CH1 10V 200 M200ys 20mV CH4 2A Figure 24
20. 90 kHz SYNC Input Frequency Range fswc fswc 2 fsw 400 3000 kHz SYNC Input Pulse Width 100 ns SYNC Pin Capacitance to GND 5 pF LINEAR REGULATOR VCCO Output Voltage Iveco 100 mA 4 7 5 0 5 3 V VCCO Load Regulation lvcco 0 mA to 100 mA 35 mV VCCO Line Regulation Vin 5 5 V to 20 V lvcco 20 mA 10 mV VCCO Current Limit VCCO drops to 4 V from 5 V 350 mA VCCO Short Circuit Current VCCO lt 0 5 V 370 400 mA VIN to VCCO Dropout Voltage Vpropout 100 mA Vin x 5V 0 33 V LOGIC INPUTS 1 EN2 1 2 rising 0 57 0 63 0 68 V EN1 EN2 Hysteresis 0 03 V EN1 EN2 Input Leakage Current len Vin 2 75 V to 20V 1 200 nA SYNC Logic Input Low 1 3 V SYNC Logic Input High 1 9 V SYNC Input Pull Down Resistance Rsync 1 Rev A Page 3 of 32 ADP1850 Parameter Symbol Conditions Min Typ Max Unit GATE DRIVERS DHx Rise Time Cpu 3 Vast 5 V 16 ns DHx Fall Time Cpu 3 nF Vest 5 V 14 ns DLx Rise Time Co 3 nF 16 ns DLx Fall Time Co 3 nF 14 ns DHx to DLx Dead Time External 3 nF is connected to DHx and DLx 25 ns DHx or DLx Driver Ron Sourcing Ron_source Sourcing 2 A with a 100 ns pulse 2 Q Current Sourcing 1 A with a 100 ns pulse Vin 3 V 2 3 Q DHx or DLx Driver Ron Tempco TCron Vin 3Vor12V 0 3 DHx DLx Driver Row Sinking Row siNK Sinking 2 A with a 100 ns pulse 1 5 Q Current Sinking 1 A with a 100 ns pulse Vn
21. 96 and 4096 of the maximum dc output load current Generally a larger inductor current ripple generates more power loss in the inductor and larger voltage ripples at the output Check the inductor data sheet to make sure that the saturation current of the inductor is well above the peak inductor current of a particular design Choose the inductor value by the following equation is Vin Vour x Vour fow XAT Vin where L is the inductor value fswis the switching frequency Vour is the output voltage Vin is the input voltage is the peak to peak inductor ripple current Rev A Page 18 of 32 OUTPUT CAPACITOR SELECTION Choose the output bulk capacitor to set the desired output voltage ripple The impedance of the output capacitor at the switching frequency multiplied by the ripple current gives the output voltage ripple The impedance is made up of the capacitive impedance plus the nonideal parasitic characteristics the equivalent series resistance ESR and the equivalent series inductance ESL The output voltage ripple can be approximated by AVour AI 4fow X bn 8fsw X Cour where AVour is the output ripple voltage is the inductor ripple current is the equivalent series resistance of the output capacitor or the parallel combination of ESR of all output capacitors Les is the equivalent series inductance of the output capacitor or the parallel combination of ESL of all c
22. AGND with a 1 uF or larger ceramic capacitor The VCCO output remains active even when EN1 and EN2 are low For operation with VIN below 5 V VIN may be shorted to VCCO Do not use the LDO to power other auxiliary system loads 5 VDL Power Supply for the Low Side Driver Bypass VDL to PGNDx with a 1 uF or greater ceramic capacitor Connect VCCO to VDL 6 AGND Analog Ground 7 FREQ Sets the desired operating frequency between 200 kHz and 1 5 MHz with one resistor between FREQ and AGND Connect FREQ to AGND for a preprogrammed 300 kHz or FREQ to VCCO for 600 kHz operating frequency 8 EN2 Enable Input for Channel 2 Drive EN2 high to turn on the Channel 2 controller and drive EN2 low to turn off the Channel 2 controller Tie EN2 to VIN for automatic startup For a precision UVLO put an appropriately sized resistor divider from VIN to AGND and tie the midpoint to this pin 9 TRK2 Tracking Input for Channel 2 Connect TRK2 to VCCO if tracking is not used 10 FB2 Output Voltage Feedback for Channel 2 Connect to Output 2 via a resistor divider 11 COMP2 Compensation Node for Channel 2 Output of Channel 2 error amplifier Connect a series resistor capacitor network from COMP2 to AGND to compensate the regulation control loop 12 RAMP2 Connect a resistor from 2 to VIN to set up a ramp current for slope compensation in Channel 2 The voltage at RAMP2 is 0 2 V This pin is high impedance when the channel is disabled 13 SS2 Soft Start Input for Ch
23. ANALOG DEVICES FEATURES Wide range input 2 75 V to 20V Power stage input voltage 1 V to 20 V Output voltage range 0 6 V up to 9096 Vin Output current to more than 25 A per channel Accurate current sharing between channels interleaved Programmable frequency 200 kHz to 1 5 MHz 180 phase shift between channels for reduced input capacitance 0 85 reference voltage accuracy from 40 to 85 Integrated boost diodes Power saving mode PSM at light loads Accurate power good with internal pull up resistor Accurate voltage tracking capability Independent channel precision enable Overvoltage and overcurrent limit protection Externally programmable soft start slope compensation and current sense gain Synchronization input Thermal overload protection Input undervoltage lockout UVLO Available in 32 lead 5 mm x 5 mm LFCSP APPLICATIONS High current single and dual output intermediate bus and point of load converters requiring sequencing and tracking capability including converters for Point of load power supplies Telecom base station and networking Consumer Industrial and instrumentation Healthcare and medical GENERAL DESCRIPTION The ADP1850 is a configurable dual output or two phase single output dc to dc synchronous buck controller capable of running from commonly used 3 3 V to 12 V up to 20 V voltage inputs The device operates in current mode for improved transient response and uses valley current
24. DED T HS FET BSC080N03LS LS FET BSCO30NO3LS Vin 2 75V SOURCING 3 5 32 3 0 o 31 z Vin 12V SOURCING u 25 z 30 a 8 E 2 0 Vin 2 75V SINKING a ui 28 gt 15 Vin 12V SINKING 27 1 0 26 0 5 DEAD TIME BETWEEN SW FALLING EDGE 25 LAND DL RISING EDGE INCLUDING DIODE RECOVERY TIME 40 20 0 20 40 60 80 100 120 140 5 15 10 35 60 85 110 135 8 3 3 TEMPERATURE C TEMPERATURE 3 Figure 18 Dead Time vs Temperature Figure 21 Driver Resistance vs Temperature Rev A Page 11 of 32 ADP1850 THEORY OF OPERATION The ADP1850 is a current mode dual channel step down switching controller with integrated MOSFET drivers for external N channel synchronous power MOSFETs The two outputs are phase shifted 180 This reduces the input RMS ripple current thus minimizing required input capacitance In addition the two outputs can be combined for dual phase PWM operation that can deliver more than 50 A output current and the two channels are optimized for current sharing The ADP1850 can be set to operate in pulse skip high efficiency mode power saving mode under light load or in forced PWM The integrated boost diodes in the ADP1850 reduce the overall system cost and component count The ADP1850 includes programmable soft start output overvoltage protection program mable current limit power good and tracking function The ADP1850 can be set to operate in any switching
25. Example of Pulse Skip Mode Under Light Load A CH1 7 8V 09440 025 When the output load is greater than the pulse skip threshold current that is Vcomp reaches the threshold of 0 9 V the ADP1850 exits the pulse skip mode of operation and enters the fixed frequency discontinuous conduction mode DCM as shown in Figure 25 When the load increases further the ADP1850 enters ADP1850 INDUCTOR CURRENT CH1 10V CH2 5V 1 5 20mV CH4 2 A CH1 13 4V 09440 026 Figure 25 Example of Discontinuous Conduction Mode DCM Waveform In forced PWM the ADP1850 always operates in CCM at any load The inductor current is always continuous thus efficiency is poor at light loads SYNCHRONIZATION The switching frequency of the ADP1850 can be synchronized to an external clock by connecting SYNC to a clock signal The external clock should be between 1x and 2 3x of the internal oscillator frequency fsw The resulting switching frequency is of the external SYNC frequency because the SYNC input is divided by 2 and the resulting phases are used to clock the two channels alternately In synchronization the ADP1850 operates in PWM When an external clock is detected at the first SYNC edge the internal oscillator is reset and the clock control shifts to SYNC The SYNC edges then trigger subsequent clocking of the PWM outputs The DHI DH2 rising edges appear approximately 100 ns
26. FET 20 DL2 Low Side Synchronous Rectifier Gate Driver Output for Channel 2 To set the gain of the current sense amplifier connect a resistor between DL2 and PGND2 Capable of driving MOSFETs with a total input capacitance up to 20 nF 21 DL1 Low Side Synchronous Rectifier Gate Driver Output for Channel 1 To set the gain of the current sense amplifier connect a resistor between DL1 and PGND1 Capable of driving MOSFETs with a total input capacitance up to 20 nF 22 PGND1 Power Ground for Channel 1 Ground for internal Channel 1 driver Differential current is sensed between SW1 and PGND1 Use the Kelvin sensing connection technique between PGND1 and source of the low side MOSFET 23 DH1 High Side Switch Gate Driver Output for Channel 1 Capable of driving MOSFETs with a total input capacitance up to 20 nF 24 SW1 Power Switch Node for Channel 1 Connect to source of the high side N channel MOSFET and the drain of the low side N channel MOSFET of Channel 1 25 BST1 Boot Strapped Upper Rail of High Side Internal Driver for Channel 1 Connect a multilayer ceramic capacitor 0 1 uF to 0 22 uF between BST1 SW1 There is an internal boost diode or rectifier connected between VDL and BST1 26 ILIM1 Current Limit Sense Comparator Inverting Input for Channel 1 Connect a resistor between ILIM1 and SW1 to set the current limit offset For accurate current limit sensing connect ILIM1 to a current sense resistor at the source of the low side MOSFET
27. L PHASE OPERATION In dual phase operation the two outputs of the switching regulators are shorted together and can source more than 50 A of output current depending on the selection of the power components Internal parameters in the ADP1850 are optimized and trimmed in the factory to minimize the mismatch in output currents between the two channels See Figure 34 and Figure 47 for a configuration of a typical dual phase application circuit Note that FB1 shorts to FB2 551 to 552 and COMPI to 2 where the outputs of the two error amplifiers are shared Furthermore the controller needs to be placed in forced PWM operation by connecting SYNC to VCCO or logic high The equations for calculating the loop compensation compo nents are identical to the single phase operation but the combined value of Gm of the error amplifiers the modulator gain and the effective fsw are all doubled Vin RAMP1 VIN ADP1850 09440 002 Figure 34 Dual Phase Circuit SWITCHING NOISE AND OVERSHOOT REDUCTION In any high speed step down regulator high frequency noise generally in the range of 50 MHz to 100 MHz and voltage overshoot are always present at the gate the switch node SW and the drains of the external MOSFETS The high frequency noise and overshoot are caused by the parasitic capacitance Co of the external MOSFET and the parasitic inductance of the gate trace and the packages of the MOSFETs When the high current is switc
28. acitor exceeds the maximum input current ripple of a particular design INPUT FILTER Normally 0 1 uF or greater value bypass capacitor from the input pin VIN to AGND is sufficient for filtering out any unwanted switching noise However depending on the PCB layout some switching noise can enter the ADP1850 internal circuitry therefore it is recommended to have a low pass filter at the VIN pin Connecting a resistor between 2 and 5 Q in series with VIN and a 1 uF ceramic capacitor between VIN and AGND creates a low pass filter that effectively filters out any unwanted glitches caused by the switching regulator Keep in mind that the input current could be larger than 100 mA when driving large MOSFETs A 100 mA across 5 resistor creates a 0 5 V drop which is the same voltage drop in VCCO In this case a lower resistor value is desirable ADP1850 VIN 20 50 09440 033 Figure 32 Input Filter Configuration BOOST CAPACITOR SELECTION To lower system component count and cost the ADP1850 has an integrated rectifier equivalent to the boost diode between VCCO and Choose boost ceramic capacitor with value between 0 1 uF and 0 22 uF this capacitor provides the current for the high side driver during switching INDUCTOR SELECTION The output LC filter smoothes the switched voltage at SWx For most applications choose an inductor value such that the inductor ripple current is between 20
29. after the corresponding SYNC edge and the frequency is locked to the external signal Depending on the start up conditions of Channel 1 and Channel 2 either Channel 1 or Channel 2 can be the first channel synchronized to the rising edge of the SYNC clock If the external SYNC signal disappears during operation the ADP1850 reverts to its internal oscillator When the SYNC function is used it is recommended to connect a pull up resistor from SYNC to VCCO so that when the SYNC signal is lost the ADP1850 continues to operate in PWM Rev A Page 13 of 32 ADP1850 SYNCHRONOUS RECTIFIER AND DEAD TIME The synchronous rectifier low side MOSFET improves efficiency by replacing the Schottky diode that is normally used in an asynchronous buck regulator In the ADP1850 the antishoot through circuit monitors the SW and DL nodes and adjusts the low side and high side drivers to ensure break before make switching which prevents cross conduction or shoot through between the high side and low side MOSFETs This break before make switching is known as dead time which is not fixed and depends on how fast the MOSFETS are turned on and off In a typical application circuit that uses medium sized MOSFETs with input capacitance of approximately 3 nF the typical dead time is approximately 30 ns When small and fast MOSFETs with fast diode recovery time are used the dead time can be as low as 13 ns INPUT UNDERVOLTAGE LOCKOUT When the bias input vo
30. age to be the same as the master voltage For coincident tracking use Rrrxr and Rrexs Reor as shown in Figure 37 MASTER VOLTAGE SLAVE VOLTAGE VOLTAGE V 09440 036 TIME Figure 36 Coincident Tracking 3 3V EN Vour1 MASTER EN2 20kQ 1850 m FB1 RTRKB 10 09440 037 VouT2_SLAVE Figure 37 Example of a Coincident Tracking Circuit The ratio of the slave output voltage to the master voltage is a function of the two dividers ADP1850 Rrop Vour_sLave _ Vour_ MASTER d TRKB As the master voltage rises the slave voltage rises identically Eventually the slave voltage reaches its regulation voltage where the internal reference takes over the regulation while the TRKx input continues to increase and thus removes itself from influencing the output voltage To ensure that the output voltage accuracy is not compromised by the TRKx pin being too close in voltage to the reference voltage Vm typically 0 6 V make sure that the final value of the TRKx voltage of the slave channel is at least 30 mV above Vre Ratiometric Tracking Ratiometric tracking limits the output voltage to a fraction of the master voltage as illustrated in Figure 38 and Figure 39 The final TRKx voltage of the slave channel should be set to at least 30 mV below the FB voltage of the master channel When the TRKx voltage of the slave channel drops to a level that s
31. al 1 kQ resistor At the same time VCCO discharges to zero When the junction temperature drops below 135 C the ADP1850 resumes normal operation after the soft start sequence Rev A Page 15 of 32 ADP1850 APPLICATIONS INFORMATION SETTING THE OUTPUT VOLTAGE The output voltage is set using a resistive voltage divider from the output to FB The voltage divider divides down the output voltage to the 0 6 V FB regulation voltage to set the regulation output voltage The output voltage can be set to as low as 0 6 V and as high as 9096 of the power input voltage The maximum input bias current into FB is 100 nA For a 0 1596 degradation in regulation voltage and with 100 nA bias current the low side resistor must be less than 9 which results in 67 pA of divider current For Reor use a 1 to 20 resistor A larger value resistor can be used but results in a reduction in output voltage accuracy due to the input bias current at the FBx pin while lower values cause increased quiescent current consumption Choose to set the output voltage by using the following equation Vour where is the high side voltage divider resistance 18 the low side voltage divider resistance Vovris the regulated output voltage Vrs is the feedback regulation threshold 0 6 V The minimum output voltage is dependent on fsw and minimum DH on time The maximum output
32. and bottom FETs is a pulse with very high dI dt therefore the path to through and from each individual FET should be as short as possible and the two paths should be commoned as much as possible In designs that use a pair of D Pak or a pair of SO 8 FETs on one side of the PCB it is best to counter rotate the two so that the switch node is on one side of the pair This allows the high side FET s drain to be bypassed to the low side FET s source with a suitable ceramic bypass capacitor placed as close as possible to the FETs Close proximity of the bypass capacitor minimizes the inductance around the loop through the FETs and capacitor The recommended bypass ceramic capacitor values range from 1 uF to 22 uF depending on the output current The ceramic bypass capacitor is usually connected to a larger value bulk filter capacitor and should be grounded to the PGNDx plane HIGH CURRENT AND CURRENT SENSE PATHS Part of the ADP1850 architecture is sensing the current across the low side FET between the SWx and PGNDx pins The switching GND currents of one channel creates noise and can be picked up by the other channel It is essential to have Kelvin sensing connection between SWx and the drain of the respective low side MOSFET and between PGNDx and the source of the respective low side MOSFET as illustrated in Figure 43 Place these Kelvin connections very close to the FETs to achieve accurate current sensing Figure 43 illustrates the pr
33. and inductive noise pickup It is best to position any series resistors and capacitors as close as possible to these pins Avoid running these traces close and or parallel to high dI dt traces Rev A Page 25 of 32 ADP1850 SWITCH NODE The switch node is the noisiest place in the switcher circuit with large ac and dc voltages and currents This node should be wide to minimize resistive voltage drop To minimize capacitively coupled noise the total area should be small Place the FETs and inductor close together on a small copper plane to minimize series resistance and keep the copper area small GATE DRIVER PATHS Gate drive traces DH and DL handle high dI dt and tend to produce noise and ringing They should be as short and direct as possible If vias are needed it is best to use two relatively large ones in parallel to reduce the peak current density and the current in each via If the overall PCB layout is less than optimal slowing down the gate drive slightly can be helpful to reduce noise and ringing It is occasionally helpful to place small value resistors such as between 2 and 4 on the DHx and DLx pins These be populated with 0 resistors if resistance is not needed Note that the added gate resistance increases the switching rise and fall times as well as increasing switching power loss in the MOSFET OUTPUT CAPACITORS The negative terminal of the output filter capacitors should be tied close to th
34. annel 2 Connect a capacitor from SS2 to AGND to set the soft start period The node is internally pulled up to 5 V with a 6 5 pA current source 14 PGOOD2 Power Good Open drain power good indicator logic output with an internal 12 kO resistor connected between PGOOD2 and VCCO PGOOD2 is pulled to ground when the Channel 2 output is outside the regulation window An external pull up resistor is not required Rev A Page 7 of 32 ADP1850 Pin No Mnemonic Description 15 ILIM2 Current Limit Sense Comparator Inverting Input for Channel 2 Connect a resistor between ILIM2 and SW2 to set the current limit offset For accurate current limit sensing connect ILIM2 to a current sense resistor at the source of the low side MOSFET 16 BST2 Boot Strapped Upper Rail of High Side Internal Driver for Channel 2 Connect a multilayer ceramic capacitor 0 1 uF to 0 22 uF between BST2 and SW2 There is an internal boost rectifier connected between VDL and BST2 17 SW2 Switch Node for Channel 2 Connect to source of the high side N channel MOSFET and the drain of the low side N channel MOSFET of Channel 2 18 DH2 High Side Switch Gate Driver Output for Channel 2 Capable of driving MOSFETs with total input capacitance up to 20 nF 19 PGND2 Power Ground for Channel 2 Ground for internal Channel 2 driver Differential current is sensed between SW2 and PGND2 Use the Kelvin sensing connection technique between PGND2 and source of the low side MOS
35. apacitors Solving Cour in the previous equation yields 1 Cour x 8fsw AVour AT Ruse AAT fsw 2 Lys Usually the capacitor impedance is dominated by ESR The maximum ESR rating of the capacitor such as in electrolytic or polymer capacitors is provided the manufacturer s data sheet therefore output ripple reduces to AL xR OUT ESR Electrolytic capacitors also have significant ESL on the order of 5 nH to 20 nH depending on type size and geometry PCB traces contribute some ESR and ESL as well However using the maximum ESR rating from the capacitor data sheet usually provides some margin such that measuring the ESL is not usually required In the case of output capacitors where the impedance of the ESR and ESL are small at the switching frequency for instance where the output capacitor is a bank of parallel MLCC capaci tors the capacitive impedance dominates and the output capacitance equation reduces to OUT 8 AVour x Make sure that the ripple current rating of the output capacitors is greater than the maximum inductor ripple current During a load step transient on the output for instance when the load is suddenly increased the output capacitor supplies the load until the control loop has a chance to ramp the inductor current This initial output voltage deviation results in a voltage droop or undershoot The output capacitance assuming 0 ADP1850 SR re
36. ard in Dual Phase Mode with 50 A Output 17 RoHS Compliant Part Rev A Page 31 of 32 ADP1850 NOTES 2010 2012 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D09440 0 4 12 A DEVICES www analo g com Rev A Page 32 of 32
37. at Ta 25 C Table 1 Parameter Symbol Conditions Min Typ Max Unit POWER SUPPLY Input Voltage Vin 2 75 20 V Undervoltage Lockout Threshold INuvio Vin rising 2 45 2 6 2 75 V Vin falling 2 4 2 5 2 6 Undervoltage Lockout Hysteresis 0 1 V Quiescent Current lin EN1 EN2 Vin 12 V Vrs Veco in PWM mode 4 5 5 8 mA no switching EN1 EN2 Vu 12 V Vcco in PSM mode 2 8 mA Shutdown Current 50 EN1 EN2 GND 5 5 or 20V 100 200 ERROR AMPLIFIER FBx Input Bias Current les 100 1 100 nA Transconductance Gn Sink or source 1 pA 385 550 715 uS TRK1 TRK2 Input Bias Current Irak OV lt Vr Vrgo 5 V 100 1 100 nA CURRENT SENSE AMPLIFIER GAIN Acs Gain resistor connected to DLx 24 3 3 6 V V 47 5 Gain resistor connected to DLx 5 2 6 6 9 V V Rcs 22 5 Default setting Ress open 10 5 12 13 5 V A Gain resistor connected to DLx 20 5 24 26 5 V V Ress 100 5 OUTPUT CHARACTERICTISTICS Feedback Accuracy Voltage Ves T 40 C to 85 C 0 6 V 0 85 40 6 0 85 V T 40 C to 125 C Ves 0 6 V 1 5 0 6 1 5 V Line Regulation of PWM AVre AVin 0 015 V Load Regulation of PWM AVre AVcome range 0 9 V to 2 2 V 0 3 OSCILLATOR Frequency fsw 340 to AGND 170 200 235 kHz Rrrea 78 7 to AGND 720 800 880 kHz Rrrea 39 2 to AGND 1275 1500 1725 kHz FREQ to AGND 235 300 345 kHz FREQ to VCCO 475 600 6
38. cally 0 4 Iipr X 47 LPK where is the peak inductor current Rev A Page 16 of 32 ACCURATE CURRENT LIMIT SENSING Roson of the MOSFET can vary by more than 5096 over the temperature range Accurate current limit sensing is achieved by adding a current sense resistor from the source of the low side MOSFET to PGNDx Make sure that the power rating of the current sense resistor is adequate for the application Apply the previous equation and calculate Rum by replacing with Rsense Figure 30 illustrates the implementation of accurate current limit sensing 09440 031 Figure 30 Accurate Current Limit Sensing SETTING THE SLOPE COMPENSATION In a current mode control topology slope compensation is needed to prevent subharmonic oscillations in the inductor current and to maintain a stable output The external slope compensation is implemented by summing the amplified sense signal and a scaled voltage at the RAMPx pin To implement the slope compensation connect a resistor between RAMPx and the input voltage The resistor is calculated by 7x10 L RAMP Ac xR R DSON _ MAX where 7 x 10 is an internal parameter L is the inductance with units in H of the inductor Rpson max is the low side MOSFET maximum on resistance Acs is the gain either 3 V V 6 V V 12 V V or 24 V V of the current sense amplifier see the Setting
39. d INTEGRATED RECTIFIER At 20 mA forward current 16 Q BOOST DIODE RESISTANCE ZERO CURRENT CROSS OFFSET In pulse skip mode only fsw 600 kHz 0 2 4 mV SWx TO PGNDx 1 Guaranteed by design 2 Connect Vin to VCCO when 2 75 V lt Vin lt 5 5 V Rev A Page 4 of 32 ABSOLUTE MAXIMUM RATINGS Table 2 Parameter Rating VIN EN1 EN2 RAMP1 RAMP2 21V FB1 FB2 COMP1 COMP2 551 552 TRK1 TRK2 0 3 V to 6 V FREQ SYNC VCCO VDL PGOOD1 PGOOD2 ILIM1 ILIM2 SW1 SW2 to PGND1 PGND2 0 3 V to 21 V BST1 BST2 DH1 DH2 to PGND1 PGND2 0 3 V to 28 V DL1 DL2 to PGND1 PGND2 0 3V to VCCO 0 3 V BST1 BST2 to SW1 SW2 0 3 V to 6 V BST1 BST2 to PGND1 PGND2 32V 20 ns Transients SW1 SW2 to PGND1 PGND2 25V 20 ns Transients DL1 DL2 SW1 SW2 ILIM1 ILIM2 to 8V PGND1 PGND2 20 ns Negative Transients PGND1 PGND2 to AGND 0 3 V to 40 3 V PGND1 PGND2 to AGND 20 ns Transients 8 V 4 V on Multilayer PCB Natural Convection 32 6 C W Operating Junction Temperature Range 40 to 125 C Storage Temperature Range 65 to 150 C Maximum Soldering Lead Temperature 260 C ADP1850 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to
40. e source of the low side FET Doing this helps to minimize voltage differences between AGND and PGNDx Rev A Page 26 of 32 ADP1850 TYPICAL OPERATING CIRCUITS 330pF 422 4TpF Vin 10 TO 18V ADP1850 Vour2 O 1 8V 14A 560pF 23 2 4 nb 10kQ 20kQ fsw 600kHz CIN4 10uF X7R 25V 1210 2 GRM32DR71E106KA12 MURATA CIN 150yF 20V OS CON 20SEP150M SANYO COUT 44 COUT21 330pF 6 3V POSCAP 2 6TPF330M9L SANYO L1 L2 1 2uH WURTH ELEKTRONIK 744325120 COUT 42 COUT 9 22uF X5R 0805 6 3V x 3 GRM21BR60J226ME39 MURATA M1 3 BSCO80N03LS M2 M4 BSCO30N03LS 09440 044 Figure 44 Typical 14 A Operating Circuit Rev A Page 27 of 32 ADP1850 560pF 33pF Vin 10V TO 20V ADP1850 We 10kQ 20kO fsw 750kHz PULSE SKIP MODE CIN4 10 5 5 16 1206 2 GRM31CR61C106KA88 MURATA L1 20H WURTH ELEKTRONIK 744310200 M1 M2 SI944DY OR BSONO3MD 5 L2 1 15 WURTH ELEKTRONIK 744310115 COUT COUT 22uF XR5 1210 6 3V 3 GRM32DR60J226KA01 MURATA Figure 45 Typical Low Current Operating Circuit Rev A Page 28 of 32 ADP1850 33pF Vin 5 5V ADP1850 800kHz PULSE SKIP MODE 4 7 5 16 0805 x 2 GRM219R60J475KE19 MURATA L1 L2 14H D62LCB1ROM COUT COUT 22uF XR5 0805 6 3V GRM21BR60J226ME39 MURATA M1 M2 M3 M4 SI2302ADS SOT23 09440 046 Figure 46 Typical Low Current Applicatio
41. frequency between 200 kHz and 1 5 MHz with one external resistor CONTROL ARCHITECTURE The ADP1850 is based on a fixed frequency current mode PWM control architecture The inductor current is sensed by the voltage drop measured across the external low side MOSFET Roson during the off period of the switching cycle valley inductor current The current sense signal is further processed by the current sense amplifier The output of the current sense amplifier is held and the emulated current ramp is multiplexed and fed into the PWM comparator as shown in Figure 22 The valley current information is captured at the end of the off period and the emulated current ramp is applied at that point when the next on cycle begins An error amplifier integrates the error between the feedback voltage and the generated error voltage from the COMPx pin from error amplifier in Figure 22 TO DRIVERS FROM LOW SIDE MOSFET FROM ERROR AMP 09440 023 Figure 22 Simplified Control Architecture As shown in Figure 22 the emulated current ramp is generated inside the IC but offers programmability through the RAMPx pin Selecting an appropriate value resistor from V to the RAMPXx pin programs a desired slope compensation value and at the same time provides a feed forward feature The benefits realized by deploying this type of control scheme are that there is no need to worry about the turn on current spike corrupting the current ramp Al
42. hed electromagnetic interference EMI is generated which can affect the operation of the surrounding circuits To reduce voltage ringing and noise it is recommended to add an RC snubber between SWx and PGNDx for high current applications as illustrated in Figure 35 In most applications Rsxus is typically 2 to 4 and Csnus typically 1 2 nF to 3 nF Rsnus can be estimated by R 2 L wosrer SNUB C OSS And can be estimated by Conus Coss where Lmosrer is the total parasitic inductance of the high side and low side MOSFETs typically 3 nH and is package dependent Coss is the total output capacitance of the high side and low side MOSFETs given in the MOSFET data sheet The size of the RC snubber components needs to be chosen correctly to handle the power dissipation The power dissipated in Rsnup is 22929 X X fsw In most applications a component size 0805 for is sufficient However the use of an RC snubber reduces the overall efficiency generally by an amount in the range of 0 196 to 0 596 The RC snubber does not reduce the voltage overshoot A resistor shown as in Figure 35 at the BSTx pin helps to reduce overshoot and is generally between 2 and 4 Adding a resistor in series typically between 2 and 4 with the gate driver also helps to reduce overshoot If a gate resistor is added then Rus is not needed VDL ADP1850 CHANNEL
43. ltage Vm is less than the undervoltage lockout UVLO threshold the switch drivers stay inactive When Vn exceeds the UVLO threshold the switchers start switching INTERNAL LINEAR REGULATOR The internal linear regulator is low dropout LDO meaning it can regulate its output voltage VCCO VCCO powers up the internal control circuitry and provides power for the gate drivers It is guaranteed to have more than 200 mA of output current capability which is sufficient to handle the gate drive requirements of typical logic threshold MOSFETS driven at up to 1 5 MHz VCCO is always active and cannot be shut down by the and EN2 pins Bypass VCCO to AGND with a 1 uF or greater capacitor Because the LDO supplies the gate drive current the output of VCCO is subject to sharp transient currents as the drivers switch and the boost capacitors recharge during each switching cycle The LDO has been optimized to handle these transients without overload faults Due to the gate drive loading using the VCCO output for other external auxiliary system loads is not recommended The LDO includes a current limit well above the expected maximum gate drive load This current limit also includes a short circuit fold back to further limit the VCCO current in the event of a short circuit fault The VDL pin provides power to the low side driver Connect VDL to VCCO Bypass VDL to PGNDx with a 1 minimum ceramic capacitor which must be placed close t
44. lute Maximum Ratings seen 5 ESD M 5 Simplified Block Diagram seen 6 Pin Configuration and Function 7 Typical Performance Characteristics sss 9 Theory of 12 Control Architecture ertet 12 Oscillator Frequency 12 Modes of Operation sse 13 Synchronization eet e RH ERES 13 Synchronous Rectifier and Dead Time 14 Input Undervoltage Lockout sss 14 Internal Linear Regulator sse 14 Overvoltage Protection 14 Power eer apte 14 Short Circuit and Current Limit 15 Shutdown Control titer 15 Thermal Overload Protection sss 15 Applications Information eee 16 Setting the Output Voltage seen 16 A TT OET 16 Setting the Current Limit eene 16 REVISION HISTORY 4 12 Rev 0 to Rev A Changes to Setting the Current Sense Gain Section 17 Updated Outline Dimensions seen 31 11 10 Revision 0 Initial Version Accurate Current Limit Sensing sse 17 Setting the Slope Compensation sse 17 Setting the Current Sense Gain
45. n scheme in action in PSM CH1 20 0V CH2 5 00V 100 5 CH3 1 00V CH4 10 0V A CH1 10 0V 09440 028 Figure 27 Overvoltage Protection in PSM POWER GOOD The PGOODx pin is an open drain NMOSFET with an internal 12 pull up resistor connected between PGOODx and VCCO PGOODx is internally pulled up to VCCO during normal operation and is active low when tripped When the feedback voltage Ves rises above the overvoltage threshold or drops below the undervoltage threshold the PGOODx output is pulled to ground after a delay of 12 us The overvoltage or undervoltage condition must exist for more than 10 ps for PGOODx to become active The PGOODx output also becomes active if a thermal overload condition is detected Rev A Page 14 of 32 SHORT CIRCUIT AND CURRENT LIMIT PROTECTION When the output is shorted or the output current exceeds the current limit set by the current limit setting resistor between ILIMx and SWx for eight consecutive cycles the ADP1850 shuts off both the high side and low side drivers and restarts the soft start sequence every 10 ms which is known as hiccup mode The SS node discharges to zero through an internal 1 resistor during an overcurrent or short circuit event Figure 28 shows that the ADP1850 on a high current application circuit is entering current limit hiccup mode when the output is shorted INDUCTOR CURRI
46. n with Vin lt 5 5 V Rev A Page 29 of 32 ADP1850 3 3nF 887 Vin 10V TO 44V Q ADP1850 Vout O 1 09V 50A fsw 300kHz CIN44 CIN42 CIN24 CIN22 100F X7R 25V 1210 MURATA CIN 180pF 16V x 4 165 180 OS CON SANYO COUT 21 2SEPC560MZ x 3 560uF OSCON SANYO M1 M2 M5 M6 BSC080NO3IS COUT42 COUT22 GRM31CR60J476ME19 2 470V 1206 6 3V MURATA M3 4 M7 M8 BSCO30NO3LS L1 L2 SER1408 301 300nH COILCRAFT OR 744355147 0 4pH WURTH ELECTRONIK Figure 47 Dual Phase Circuit 50 A Output Rev A Page 30 of 32 09440 047 OUTLINE DIMENSIONS 0 30 0 25 j PIN 1 0 18 INDICATOR PIN 1 INDICATOR 0 50 n BSC P 3 65 3 50 sQ 3 45 0 50 0 25 MIN TOP VIEW 0401 0 30 0 80 0 75 FOR PROPER CONNECTION OF 0 70 0 05 MAX THE EXPOSED PAD REFER TO 0 02 THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 227 SUPE SECTION OF THIS DATA SHEET SEATING PLANE 0 20 REF 04 02 2012 A COMPLIANT TO JEDEC STANDARDS MO 220 WHHD Figure 48 32 Lead Lead Frame Chip Scale Package LFCSP_WQ 5mm 5 mm Body Very Very Thin Quad CP 32 11 Dimensions shown in millimeters ADP1850 ORDERING GUIDE Model Temperature Range Package Description Package Option ADP1850ACPZ R7 40 to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 32 11 ADP1850SP EVALZ ADP1850DP EVALZ Evaluation Board in Single Phase Mode with 14 A Output Evaluation Bo
47. o the VDL pin For an input voltage less than 5 5 V it is recommended to bypass the LDO by connecting VIN to VCCO as shown in Figure 26 thus eliminating the dropout voltage However if the input range is 4 V to 7 V the LDO cannot be bypassed by shorting VIN to VCCO because the 7 V input has exceeded the maximum voltage rating of the VCCO pin In this case use the LDO to drive the internal drivers but keep in mind that there is a dropout when Vi is less than 5 V Vin 2 75V 5 5V VIN vcco ADP1850 09440 027 Figure 26 Configuration for lt 5 5 V OVERVOLTAGE PROTECTION The ADP1850 has a built in circuit for detecting output over voltage at the FB node When the FB voltage Vrs rises above the overvoltage threshold the low side N channel MOSFET NMOSFET is immediately turned on and the high side NMOSFET is turned off until the Vrs drops below the undervoltage threshold This action is known as the crow bar overvoltage protection If the overvoltage condition is not removed the controller maintains the feedback voltage between the overvoltage and undervoltage thresholds and the output is regulated to within typically 8 and 896 of the regulation voltage During an overvoltage event the SS node discharges toward zero through an internal 3 pull down resistor When the voltage at FBx drops below the undervoltage threshold the soft start sequence restarts Figure 27 shows the overvoltage protectio
48. oper connection technique for the SW1 SW2 PGND 1 PGND2 and PGND plane VIN ADP1850 DH1 23 24 DL1 27 PGND1 22 CpEcouPLE1 CpEcouPLE2 09440 043 Figure 43 Grounding Technique for Two Channels SIGNAL PATHS The negative terminals of VIN bypass compensation components soft start capacitor and the bottom end of the output feedback divider resistors should be tied to a small AGND plane These connections should attach from their respective pins to the AGND plane and should be as short as possible No high current or high dI dt signals should be connected to this AGND plane The AGND area should be connected through one wide trace to the negative terminal of the output filter capacitors PGND PLANE The PGNDx pin handles a high dI dt gate drive current returning from the source of the low side MOSFET The voltage at this pin also establishes the 0 V reference for the overcurrent limit protection function and the ILIMx pin A PGND plane should connect the PGNDx pin and the VDL bypass capacitor 1 uE through a wide and direct path to the source of the low side MOSFET The placement of CIN is critical for controlling ground bounce The negative terminal of CIN must be placed very close to the source of the low side MOSFET FEEDBACK AND CURRENT LIMIT SENSE PATHS Avoid long traces or large copper areas at the FBx and ILIMx pins which are low level signal inputs that are sensitive to capacitive
49. quired to satisfy the voltage droop requirement is approximated by Al C p ee OUT X fsw where is the step load is the voltage droop at the output When a load is suddenly removed from the output the energy stored in the inductor rushes into the capacitor causing the output to overshoot The output capacitance required to satisfy the output overshoot requirement can be approximated by 2 28 Al srep L OUT 2 2 Vour AVovgnsuoor Vovr where AVoversuoor is the overshoot voltage during the step load Select the largest output capacitance given by any of the previous three equations MOSFET SELECTION The choice of MOSFET directly affects the dc to dc converter performance A MOSFET with low on resistance reduces losses and low gate charge reduces transition losses The MOSFET should have low thermal resistance to ensure that the power dissipated in the MOSFET does not result in excessive MOSFET die temperature The high side MOSFET carries the load current during on time and usually carries most of the transition losses of the converter Typically the lower the on resistance of the MOSFET the higher the gate charge and vice versa Therefore it is important to choose a high side MOSFET that balances the two losses The conduction loss of the high side MOSFET is determined by the equation V Po Loan a IN where Roson is the MOSFET on
50. rom a different voltage supply as illustrated in Figure 42 The range of the power stage input voltage Vpn is 1 V to 20 V For instance the bias input voltage Vix is 5 V Vpn can be as low as 1 V or as high as 20 V The user needs to make sure that the minimum or the maximum duty cycle is not violated in this operating condition Furthermore note that Rramp is connected to Vow Vpin 1V TO 20V 2 7 20 VIN RAMP1 ADP1850 DH1 Vouri O 5 1 1 DL1 PGND1 09440 042 Figure 42 Independent Power Stage Input Voltage Simplified Schematic Rev A Page 24 of 32 ADP1850 PCB LAYOUT GUIDELINES In any switching converter there are some circuit paths that carry high dI dt which can create spikes and noise Some circuit paths are sensitive to noise while other circuits carry high dc current and can produce significant IR voltage drops The key to proper PCB layout of a switching converter is to identify these critical paths and arrange the components and the copper area accordingly When designing PCB layouts be sure to keep high current loops small In addition keep compensation and feedback components away from the switch nodes and their associated components The following is a list of recommended layout practices for the synchronous buck controller arranged by decreasing order of importance MOSFETS INPUT BULK CAPACITOR AND BYPASS CAPACITOR The current waveform in the top
51. sensing for enhanced noise immunity The architecture enables accurate current sharing between interleaved phases for high current outputs The ADP1850 is ideal in system applications requiring multiple output voltages the ADP1850 includes a synchronization fea ture to eliminate beat frequencies between switching devices provides accurate tracking capability between supplies and includes precision enable for simple robust sequencing Rev Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property their respective owners Wide Range Input Dual Two Phase DC to DC Synchronous Buck Controller ADP1850 TYPICAL OPERATION CIRCUIT ViN RAMP1 ADP1850 DH1 BST1 Sw1 ILIM1 FB1 DL1 09440 001 Figure 1 Single Phase Circuit The ADP1850 provides high speed high peak current drive capability with dead time optimization to enable energy efficient power conversion For low load operation the device can be configured to operate in power saving mode PSM by skipping pulses and reducing switching losses to improve the
52. so the current signal is stable because the current signal is sampled at the end of the turn off period which gives time for the switch node ringing to settle Other benefits of using current mode control scheme still apply such as simplicity of loop compensation Control logic enforces antishoot through operation to limit cross conduction of the internal drivers and external MOSFETS OSCILLATOR FREQUENCY The internal oscillator frequency which ranges from 200 kHz to 1 5 MHz is set by an external resistor Rrazo at the FREQ pin Some popular fsw values are shown in Table 4 and a graph ical relationship is shown in Figure 23 For instance a 78 7 resistor sets the oscillator frequency to 800 kHz Furthermore connecting FREQ to AGND or FREQ to VCCO sets the oscil lator frequency to 300 kHz 600 kHz respectively For other frequencies that are not listed in Table 4 the values of Renzo and fsw can be obtained from Figure 23 or use the following empirical formula to calculate these values R pgo 96568 x f KHz Table 4 Setting the Oscillator Frequency Rrrea fsw Typical 332 200 kHz 78 7 800 kHz 60 4 1000 kHz 51 1200 40 2 1500 kHz FREQ to AGND 300 kHz FREQ to VCCO 600 kHz 410 ReREQ 96 568 fgyy kHz 1 065 360 310 _ 260 g 210 160 110 60 10 100 400 700 1000 1300 1600 1900 09440 02
53. urrent allowing the input power source to supply only the direct current The input capacitor needs sufficient ripple current rating to handle the input ripple as well as an ESR that is low enough to mitigate input voltage ripple For the usual current ranges for these converters it is good practice to use two parallel capacitors placed close to the drains of the high side switch MOSFETS one bulk capacitor of sufficiently high current rating and a 10 uF ceramic decoupling capacitor typically Select an input bulk capacitor based on its ripple current rating First determine the duty cycle of the output D Vour Vin The input capacitor RMS ripple current is given by Tams 7 Io D D where Iois the output current Dis the duty cycle The minimum input capacitance required for a particular load is I x D 1 D Vpp Io x Resp Msw C n iN where Vpr is the desired input ripple voltage Rese is the equivalent series resistance of the capacitor If an MLCC capacitor is used the ESR is near 0 then the equation is simplified to D 1 D C m Min I x Vpp X fsw The capacitance of MLCC is voltage dependent The actual capacitance of the selected capacitor must be derated according to the manufacturer s specification In addition add more bulk capacitance such as by using electrolytic or polymer capacitors as necessary for large step load transients Make sure the current ripple rating of the bulk cap
54. voltage is dependent on fsw the minimum DH off time and the IR drop across the high side NMOSFET and the DCR of the inductor For example with fsw of 600 kHz or 1 67 us and a minimum on time of 130 ns the minimum duty cycle is approximately 7 8 130 ns 1 67 us If Vm is 12 V and the duty cycle is 7 8 then the lowest output is 0 94 V As an example for the maximum output voltage if Vin is 5 V fsw is 600 KHz and the minimum DH off time is 395 ns 335 ns DH off time plus approximately 60 ns total dead time then the maximum duty cycle is 76 Therefore the maximum output is approximately 3 8 V If the IR drop across the high side NMOSFET and the DCR ofthe inductor is 0 5 V then the absolute maximum output is 4 5 V 5 V 0 5 V independent of fsw and duty cycle SOFT START The soft start period is set by an external capacitor between SS1 SS2 and AGND The soft start function limits the input inrush current and prevents output overshoot When is enabled a current source of 6 5 uA starts charging the capacitor and the regulation voltage is reached when the voltage at 551 552 reaches 0 6 V The soft start period is approximated by 0 6 V 65 SS The SSx pin reaches a final voltage equal to VCCO If the output voltage is precharged prior to turn on the ADP1850 prevents reverse inductor current which discharges the output capacitor Once the voltage at SSx exceeds the regulation voltage typicall
55. y 0 6 V the reverse current is reenabled to allow the output voltage regulation to be independent of load current Furthermore in dual phase operation where 551 is shorted to 552 the current source is doubled to 13 during the soft start sequence When a controller is disabled for instance EN1 EN2 is pulled low or experiences an overcurrent limit condition the soft start capacitor is discharged through an internal 3 pull down resistor SETTING THE CURRENT LIMIT The current limit comparator measures the voltage across the low side MOSFET to determine the load current The current limit is set by an external current limit resistor between ILIMx and SWx The current sense pin ILIMx sources nominally 50 uA to this external resistor This creates an offset voltage of Rim multiplied by 50 uA When the drop across the low side MOSFET Roson is equal to or greater than this offset voltage the ADP1850 flags a current limit event Because the ILIMx current and the MOSFET Roson vary over process and temperature the minimum current limit should be set to ensure that the system can handle the maximum desired load current To do this use the peak current in the inductor which is the desired output current limit level plus ofthe ripple current the maximum Roson of the MOSFET at its highest expected temperature and the minimum ILIM current Keep in mind that the temperature coefficient of the MOSFET Roson is typi

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