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ANALOG DEVICES AD5100 English products handbook

1. i o vas TWNOIS NHYMNOHS nivis qv3n od 93009 1 WvHoOHd 19S SNOILVHNDISNOD 13S NOWE Laro anor 9 HOLVH3N35 5 00H21VM mE SaNIL v 13538 318viWWvHoOHd HOSS320H8dOHOIIN 8 1 1 i 19599 1091010 aTavisnrav E 13588 L 13538 T 1 1 Li 1 LOdlOld NM lt 4 NOWE 29 210 _ UO as ed MET ENN NS Aq 31 Ls iodoa 1031353d Avaa 24 0 r qt LOOA NIA avo7 NO 1 adio 7 x o e T 5 NOWZA 022 gt 1 lt vH HOLIMS T dod H3T1OHLNOO UNS L 5 NMOGLNHS An A ZIONS aa r Ta UNZ 8 5 1 i 23 1 TRE Lamo Lairo F 9 20 2 1 0 eH oso J3HA N3 SEPRLON 00 SHA Figure 24 Typical DSP in Car Infotainment Application AD5100 BATTERY lt laurcH 1 1 1 1 1 1 1 1 1 1 1 1 T 1 1 VnEG tvREG_ON_DELAY tvREG_OFF_DELAY 1 1 1 1 1 1 1 MICROPROCESSOR Vomon UV i FAILED i OFF SHUTDOWN SHUTDOWN SHUTDOWN SHDN 5V 3 3V WDI 1 1 1 ME MR 1 NET 1 1 i SHUTDOWN
2. RESET threshold 0x00 7 54 V Bit No Description 2 0 Three bits used to program RESET threshold 7 3 Reserved 0x07 R W Yes Vimon OV UV triggered SHDN hold tiso 0x00 200 ms Bit No Description 2 0 Three bits used to program Vimon OV UV triggered SHDN hold time 7 3 Reserved 0x08 R W Yes Vimon OV UV triggered SHDN delay tiso peu 0x00 1200 ms Bit No Description 2 0 Three bits used to program VI MON OV UV triggered SHDN delay time 7 3 Reserved Rev A Page 23 of 36 AD5100 Register Read Permanently NonOTP Power On Address Write Settable Register Name and Bit Description Default 0x09 R W Yes turn on triggered SHDN hold 0x00 10 ms Bit No Description 2 0 Three bits used to program ton triggered SHDN hold time 7 3 Reserved R W Yes turn off triggered SHDN delay 0x00 100 ms Bit No Description 2 0 Three bits used to program torr triggered SHDN delay time 7 3 Reserved R W Yes RESET hold tas 0x00 200 ms Bit No Description 2 0 Three bits used to program RESET hold time 7 3 Reserved OxOC R W Yes Watchdog timeout two 0x00 1500 ms Bit No Description 2 0 Three bits used to program watchdog timeout time 7 3 Reserved R W Yes RESET configuration 0x00 Bit No
3. On Code Threshold Threshold Threshold V2mon Off Threshold Vzmon Threshold Threshold 0000 18 00 V 8 43 V 7 47 V 6 95 V 2 93 V 7 54 V 0001 18 86V 7 92V 6 95V 747 4 65 1 67 0010 15 84V 9 43V 6 49 V 6 00 V 4 75V 2 31V 0011 17 22V 9 00 V 6 00 V 6 49 V 4 97V 3 05 V 0100 24 75 V 6 49 V 4 77V 4 00 V 2 32V 4 62 0101 28 29V 6 00V 4 00 V 4 77V 2 64V 6 51V 0110 19 80 V 7 47 V 3 50 V 3 00 V 4 36 V 7 16 V 0111 22 00 V 6 95 V 3 00 V 3 50 V 3 10 V 7 96 V 1000 9 90 V 12 38 V 24 75 V 19 80 V Reserved Reserved 1001 11 00 V 12 00 V 19 80 V Rising edge triggered Reserved Reserved wake up mode 1010 7 92 V 13 66 V 15 23 V 9 90 V Reserved Reserved 1011 9 00 V 13 20 V 9 90 V 15 23 V Reserved Reserved 1100 14 14 V 10 42 V 9 43 V 9 00 V Reserved Reserved 1101 15 23 V 9 90 V 9 00 V 9 43 V Reserved Reserved 1110 12 00 V 11 65 V 8 43 V 7 92 V Reserved Reserved 1111 13 20 V 11 00 V 7 92 V 8 43 V Reserved Reserved 1AD5100 0 default settings Contact Analog Devices if other default settings are required Rev A Page 10 of 36 Table 8 Available Programmable Hold Time and Delay AD5100 15 tisp_DELay 5 t2sD_DELAY tRs_HoLD two 0 07 ms 0 07 ms 0 07 ms 0 07 ms 0 1 ms 100 ms 20 ms 50 ms 10 ms 50 ms 115 250 ms 40 ms 100 5 20 ms 100 ms 15 ms 500 ms 60 ms 200 ms 30 ms 200 ms 30 ms 750 ms 80 5 400 ms 40 ms 400 ms 50 5 1000 ms 100 ms 800 ms 50 ms 800 ms 100 ms 1250 ms
4. input must be brought above the programmed UV threshold by 5 before the comparator becomes inactive indicating that the UV condition has gone away see Figure 11 uv 1 UV UV COMPARATOR COMPARATOR INACTIVE INACTIVE Figure 11 Vamon Hysteresis 05692 012 The Vamon comparator is used to control the pin and in conjunction with a hold timer to control the RESET pin To configure to control the RESET pin set Register 0x0D 3 to 0 Setting this bit to 1 prevents Vamon from causing RESET to activate The default setting is does not cause RESET to activate input voltage range is up to 30 V It has an 8 step programmable reset threshold Register 0x06 from 1 67 V to 7 96 V with an 8 step 0 1 ms to 200 ms reset hold time tus gt 5 5 1 PROGRAMMABLE 2 MOST APPLICATIONS USING REQUIRE DISABLING OF TRIGGERED RESET 1 1 1 RS DELAY ins DELAY 1 1 Vie The RESET and Vuour timing diagrams are shown Figure 12 The range of thresholds is shown in Table 6 and the programming code for the selected threshold is found in Table 8 The default monitoring threshold is 7 54 V Similarly the range of reset hold time is shown in Table 8 and the programming code of the selected timing is found
5. Lo MICROPROCESSOR SHUTDOWN ENABLE ENABLE RESET i RESET RESET 05692 026 WDI RESET Figure 25 Example of SHDN and RESET Responses of Circuit Shown in Figure 24 Rev A Page 31 of 36 AD5100 BATTERY MONITORING WITH FAN CONTROL BATTERY STATE OF CHARGE INDICATOR AND can be used with in tandem to form a simple PWM SHUTDOWN EARLY WARNING MONITORING control circuit For example as shown in Figure 26 when a In the automotive application the system designer may set the temperature sensor output connects to the Vamon input with battery threshold to the lowest level to allow an automobile to the proper threshold level set outputs high whenever the start at the worst case condition If the battery remains at the temperature goes above the threshold This turns on the FET low voltage level it is indeed a poor battery However there is switch which activates the fan When Vreme drops below the no way to warn the driver As a result the system designer can threshold Vsour decreases which turns off the fan use Vuour as the battery warning indicator By stepping down the battery voltage monitored at Vamon the LED is lit which gives a battery replacement warning The circuit is shown in Figure 28 BATTERY BATTERY SD IGNITION AD5100 VREG VTEMP Vaout MR RESET MR SHDNWARN WDI CLK 05692 027 VXEMPO zt a UE LS i e THRE
6. RELEASE AFTER 1s 05692 014 Figure 14 Advanced Watchdog SHDN Asserted After Three Trials of Resetting the Watchdog SHDN Released After 1 Second and the Cycle Repeats Rev A Page 17 of 36 AD5100 Floating WDI Input If the WDI pin is floating the watchdog function is disabled by default However floating watchdog can be enabled in the RESET configuration register such that a broken WDI connection or any unusual condition that makes WDI float triggers the reset e Register 0 00 3 0 floating WDI input does not activate RESET Default e Register 0 00 3 1 floating WDI input activates RESET This feature is fixed in OTP memory Enabling or disabling the floating WDI feature can be changed dynamically using the OTP overridden function is selected MANUAL RESET INPUT Manual reset MR is an active low input to the AD5100 and has an internal pull up resistor to Vmon If the input signal on the MR pin goes low RESET is activated MR can be driven from a CMOS logic signal The MR and RESET timing diagrams are shown in Figure 15 Note that RESET is activated after tun and is held for tas after the MR signal has gone high again MR has the highest priority in triggering the RESET over any other monitoring inputs lun cLiTCH gt tug pELAY La Ins 1 RESET 0569 PROGRAMMABLE Figure 15 Manual Reset MR Timing Diagram Rev A Page 18 of 36
7. MANUAL RESET INPUT MR Input Voltage Low 0 3 x Vsmon V MR Input Voltage High 0 7 V Input Current 1 uA MR Pulse Width tmr 1 us MR Deglitching 100 ns MR to RESET Delay tMR DELAY 1 us Rev A Page 5 of 36 AD5100 Parameter Symbol Conditions Min Unit MR Pull Up Resistance Internal to 37 60 82 kQ RESET Hold Time Tolerance Atrs_HoLD Ta 25 does not apply to Code 10 10 see Figure 12 and Table 8 0 6 and Code 0x7 Ta 40 C to 125 C does not 17 17 apply to Code 0x06 Code 0x7 SERIAL INTERFACES Input Logic High SCL SDA External 2 2 2 0 5 5 V Input Logic Low SCL SDA Vit External Reut ur 2 2 0 0 8 Output Logic High SDA Vea 2 V to 5 5 V 0 7 X V Output Logic Low SDA Vo lo 3 mA 0 0 4 V Input Current Viu 20V to 5 5 V 1 Input Capacitance 5 pF POWER SUPPLY Supply Voltage Range Vimon 6 0 30 V Sleep Mode Supply Current 15 OV 5 Active Mode Supply Current lpower_viMoNn 12V 2 mA edge triggered mode selected 2 mA Device Power On Threshold 2 2 V Vamon iL 0 4 V Device Power Up Vowoy Minimum Pulse Width _ 4 ms Device Power Down Delay Tvrec_orr_petay V2mon lt 0 4 V normal mode 2 sec C initiated power down 10 us 1 Represent typical values at 25 Vimo
8. 150 ms 1000 ms 100 ms 1000 ms 150 ms 1500 ms 200 ms 1200 ms 200 ms 1200 ms 200 ms 2000 ms AD5100 0 default settings Contact Analog Devices if other default settings are required Table 9 Look Up Table of Programming Code vs Typical Timings Shown in Table 8 Code tisp 150 pELAY 050 HoLp 050 pELAY tns twp 000 200 ms 1200 ms 10 ms 100 ms 200 ms 1500 ms 001 150 ms 1000 ms 20 ms 50 ms 150 ms 2000 ms 010 100 ms 800 ms 30 ms 200 ms 100 ms 1250 ms 011 80 ms 400 ms 40 ms 400 ms 50 ms 1000 ms 100 60 ms 200 ms 50 ms 800 ms 30 ms 750 ms 101 40 ms 100 ms 100 ms 1000 ms 15 ms 500 ms 110 20 ms 50 ms 200 ms 1200 ms 1ms 250 ms 111 0 07 ms 0 07 ms 0 07 ms 0 07 ms 0 1 ms 100 ms AD5100 0 default settings Contact Analog Devices if other default settings are required Rev A Page 11 of 36 AD5100 THEORY OF OPERATION The AD5100 is a programmable system management IC that has four channels of monitoring inputs Three inputs have high voltage 30 V capability For example if the AD5100 is used in an automotive application Vimon Monitoring Input 1 be connected to the battery and the can be connected to the ignition switch a rising edge trigger wake up signal or the media oriented systems transport MOST wake up signal is connected to for MOST applications Two other inputs Vamon and Vamon are designed for low voltage monitoring with programmable threshold
9. Figure 4 Recommended PCB Layout for Shielded High Voltage Inputs Rev A Page 9 of 36 AD5100 ONE TIME PROGRAMMABLE OTP OPTIONS All values are typical ratings see Table 2 for tolerances Table 6 Available Programmable Thresholds at T4 25 C Vimon OV Threshold Vimon UV Threshold On Threshold Off Threshold V3mon Threshold Vamon Threshold 7 92V 6 00V 3 00V 3 00V 2 32V 1 67V 9 00V 6 49V 3 5V 3 5V 2 64V 2 31V 9 90 V 6 95 V 4 00 V 4 00 V 2 93 V 3 05 V 11 00 V 747 477 477 3 10V 4 62V 12 00 V 7 92V 6 00V 6 00V 4 36V 6 51V 13 20V 8 43 V 6 49 V 6 49V 4 65 V 7 16V 14 14 V 9 00V 6 95V 6 95 V 4 75V 7 54 V 15 23 V 9 43 V 7 47 V 7 47 V 4 97 V 7 96 V 15 84 V 9 90 V 7 92 V 7 92 V Reserved Reserved 17 22 V 10 42 V 8 43 V 8 43 V Reserved Reserved 18 00 V 11 00 V 9 00 V 9 00 V Reserved Reserved 18 86 V 11 65 V 9 43V 9 43 V Reserved Reserved 19 80 V 12 00 V 9 90 V 9 90 V Reserved Reserved 22 00 V 12 38 V 15 23 V 15 23 V Reserved Reserved 24 75 V 13 20 V 19 80 V 19 80 V Reserved Reserved 28 29 V 13 66 V 24 75 V Rising edge triggered Reserved Reserved wake up mode 1 Vimon_ov must be gt Vimon_uv 2 Vomon_orr is ignored if gt Vzmon_on but Cannot be 3 AD5100 0 default settings Contact Analog Devices if other default settings are required Table 7 Look Up Table of Programming Code vs Typical Thresholds Shown in Table 6 Vimon Vimon UV
10. ADO 05692 001 Figure 1 Rev A Page 3 of 36 AD5100 SPECIFICATIONS ELECTRICAL SPECIFICATIONS 6 V Vimon 30 V and 3 Vomon 30 V 40 C lt Ta lt 125 C unless otherwise noted Table 2 Parameter Symbol Conditions Min Unit HIGH VOLTAGE MONITORING INPUTS Vimon Voltage Range Vimon 6 30 V Input Resistance Rin_vimon 36 55 70 kQ OV UV Threshold Tolerance AOV AUV Ta 25 1 6 11 6 96 See Figure 7 and Table 6 Ta 40 C to 85 1 8 1 8 Ta 40 C to 125 2 2 Hysteresis 1 5 Programmable Shutdown Hold Time Atisp Ta 25 does not apply to 10 10 Tolerance See Figure 7 and Table 8 Code 0x7 Programmable Shutdown Delay Tolerance Ta 25 does apply to 10 10 See Figure 7 and Table 8 Code 0 7 Ta 40 C to 125 C does not 17 17 apply to Code 0 7 Fault Detection Delay trD_DELAY 60 us Glitch Immune Time Guaranteed by evaluation 45 us Input Voltage Minimum voltage 2 2 V ensure AD5100 Vres power up Voltage Range 3 30 V Input Resistance 500 675 860 kQ On Off Threshold Tolerance AOn AOff 25 2 2 See Figure 7 and Table 6 Ta 40 C to 85 C 2 4 2 4 Ta 40 C to 125 C 2 5 2 5 Hysteresis 1 5 Turn On Programmable SHDN Hold Time Ta 25 does apply to 10 10 Tolerance
11. Description 0 0 RESET is active when SHDN is active 1 RESET is not active when SHDN is active 1 0 RESET active low 1 RESET active high 2 0 enables Vamon under threshold causing RESET 1 prevents Vamon under threshold from causing RESET for Vaour applications 3 0 floating WDI does not activate RESET 1 floating WDI activates RESET 7 4 Reserved OxOE R W Yes SHDN rail voltage configuration 0x00 Bit No Description 2 0 Reserved 3 0 SHDN rail Vimon 1 SHDN rail 7 4 Reserved R W Yes Watchdog mode 0x00 Bit No Description 2 0 Reserved 3 0 standard mode 1 advanced mode 7 4 Reserved 0x15 R W Yes Program lock inhibit further programming 0x00 Bit No Description 2 0 Reserved 3 Reserved 7 4 Reserved Rev A Page 24 of 36 AD5100 Register Read Permanently NonOTP Power On Address Write Settable Register Name and Bit Description Default 0x16 R W No Special function 1 0x00 Bit No Description 0 Reserved 1 Reserved 2 0 software assertion of SHDN pin is inactive 1 pulls SHDN pin low 3 0 override of permanent settings inactive 1 override of permanent settings active 7 4 Reserved 0x17 R W No Special function 2 0x00 Bit No Description 0 0 software power down of AD5100 inactive 1 software power down of AD5100 active 7 1 Reserved 0x18 R W No Disable special functions 0x00 Bit No Descriptio
12. See Figure 7 and Table 8 Code 0x7 Turn Off Programmable SHDN Delay Time Atosp_petay Ta 25 C does not apply to 10 10 Tolerance See Figure 7 and Table 8 Code 0x07 40 C to 125 C does not 17 17 apply to Code 0x7 Fault Detection Delay Only 60 Us Glitch Immune Time 45 us SHDN SHDN Output High Von Vreg 5 40 pA 24 V Vrait Vimon Isource 600 Vimon zd 0 5 V SHDN Output Low Vo Isink 1 6 mA 0 4 V Vimon 12 V Isk 40 mA 1 5 3 V SHDN Sink Current Isink Vimon 12 V SHDN forced to 12 V 10 13 5 mA SHDNWARN Open Drain Output SHDNWARN Inactive Leakage Current loH_sHDNWARN 0 9 pA SHDNWARN Active VoL sHDNWARN Isink 3 MA 0 4 V Rev A Page 4 of 36 AD5100 Parameter Symbol Conditions Min Unit LOW VOLTAGE MONITORING INPUTS Voltage Range V3mon 2 0 5 5 V Input Resistance 85 130 180 kQ Threshold Tolerance 25 2 5 42 5 See Figure 10 and Table 6 Ta 40 C to 85 C 2 75 2 75 Ta 40 C to 125 3 3 Hysteresis V3_HYSTERESIS 1 2 Voltage Range 0 9 30 V Input Resistance Rin_vamon 500 675 860 kQ Vamon Threshold Tolerance AVamon Ta 25 C 2 5 2 5 See Figure 12 and Table 6 Ta 40 C to 85 C 2 75 2 75 Ta 40 C to 125 C 3 3 Vamon Hysteresis V4_HY
13. active when reaches 2 2 V is used to turn AD5100 on and off with a different behavior depending on the V2mon monitoring mode selection By default the AD5100 turns on when the voltage at rises above the logic threshold When falls below the logic threshold AD5100 turns off 2 seconds after SHDN is deasserted Note that AD5100 requires 5 us to start up and that Vimon must be applied before V2mon Extension of the AD5100 turn off allows the system to complete any housekeeping tasks before the system is powered off Figure 18 shows the default and Vrec waveforms 25 1 SHDN VREG NOTES 1 6V lt Vimon lt 30V 2 PROGRAMMABLE 1 t25D_DELAY 1 1 gt _ gt 1 AD5100 Rising Edge Triggered Wake Up Mode If rising edge triggered wake up V2mon mode is selected instead the AD5100 does not turn off when returns to a logic low To configure the part into rising edge triggered mode set the Off threshold register Register 0x04 3 1 to 1001 In this mode once the part is powered on it can only be powered down by an power down instruction or by removing the supply on the Vimon pin To power down the part over the bus while in rising edge triggered mode the user must first ensure that the software power down feature is e
14. at the same time For example imagine that the user overrides Register 0x01 Register 0x02 and Register 0x03 If the user subsequently clears the override bit in Register 0x16 and writes a dummy byte to Register 0x01 Register 0x01 reverts to its default value However Register 0x02 and Register 0x03 still contain their override data To revert both registers to their default values the user must write dummy data to each register individually Power cycling the AD5100 also resets all registers to their programmed defaults Rev A Page 28 of 36 AD5100 APPLICATIONS INFORMATION CAR BATTERY AND INFOTAINMENT SYSTEM SUPPLY MONITORING The AD5100 has two high voltage monitoring inputs with shut down and reset controls over external devices For example the V1MON and V2MON can be used to monitor the signals from a car battery and an ignition key in an automobile respectively see Figure 24 The shutdown output can be connected to the shutdown pin of an external regulator to prevent false condi tions such as a weak battery or overcharging of a battery by an alternator The reset output can be used to reset the processor in the event of a hardware or software malfunction An example of the input and output responses of this circuit is shown in Figure 25 Rev A Page 29 of 36 AD5100 z0 269S0 Rev A Page 30 of 36 o Med dd T u3110H1NO9
15. can be fixed in OTP memory e Register OxOE 3 0 SHDN uses Vimon rail Default e Register OxOE 3 1 SHDN uses Vazc rail Figure 16 shows the SHDN output configuration Pull down Resistor R1 ensures that SHDN is pulled to ground when the AD5100 is not powered When AD5100 is powered M2a and M2b are both on M2a has relatively lower impedance than M2b and so the SHDN remains low at shutdown When the AD5100 settles SW1 is turned on M1 is stronger than 2 so SHDN is pulled to the rail which takes AD5100 out of the shutdown mode In some applications the AD5100 may monitor and control power regulators where the input and enable pins are next to each other in a fine pitch This may pose reliability concerns under some abnormal conditions To prevent errors from happen ing the AD5100 shutdown output features smart load detection to ensure that the shutdown responds For example if the car battery has not started for a long time a resistive dendrite may AD5100 have formed across the SHDN pin and the battery terminal Vimon The dendrite is blown immediately because M2a is designed with adequate current sinking capability and remains in the on position to offer such protection In another situation if the SHDN pin is hard shorted to the 12 V battery the short circuit detector opens SW2 and limits the current by the high impedance M2b VREG o o SHORT CIRCUIT DETECT Figure
16. gt ANALOG System Management IC with Factory Programmed DEVICES Quad Voltage Monitoring and Supervisory Functions AD5100 FEATURES Qualified for automotive applications 2 device enabling outputs with 6 factory programmed monitoring inputs see Table 1 Two 30 V monitoring inputs with shutdown control of external devices Factory programmed overvoltage undervoltage turn on and turn off thresholds and shutdown timings Shutdown warning with fault detection Reset control of external devices 5 V and 7 96 V monitoring inputs with reset control of external devices Factory programmed reset thresholds and hold time eMOST compatible inputs Diagnostic application using Vamon Two supervisory functions Watchdog reset controller with timeout and selectable floating input Manual reset control for external devices Digital interface and programmability interface OTP be overwritten for dynamic adjustments Power up by edge triggered signal Power down over bus Operating range Supply voltage 6 0 to Temperature range 40 C to 125 C Shutdown current 5 pA max Operating current 2 mA max High voltage input antimigration shielding pinouts APPLICATIONS Automotive systems Network equipment Computers controllers and embedded systems Rev Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for
17. in the level sensitive power up mode Both are designed with 1 596 hysteresis Only the turn on monitoring comparator is used if the rising edge triggered wake up mode is selected When the input goes above the programmed V2mon on threshold the comparator becomes active immediately indicat ing that an on condition has occurred Due to hysteresis the V2mon input must be brought below the programmed threshold by 1 596 before the comparator becomes inactive indicating that the on condition has gone away see Figure 8 When the V2mon input drops below the programmed threshold the comparator becomes active immediately indicating that a off condition has occurred Similarly due to hysteresis the input must be brought above the programmed threshold by 1 5 before the comparator becomes inactive indicating that the off condition has gone away 1 HYSTERESIS V2MON 1 1 1 1 1 UNIT 2 V2MON OFF Eu 1 1 I ON ON i COMPARATOR COMPARATOR A INACTIVE OFF OFF 8 COMPARATOR COMPARATOR 5 INACTIVE 5 Figure 8 Hysteresis By default V2mon is level sensitive and the on and off thresholds are both monitored The on threshold chosen must be greater than the off threshold When the SHDN output is activated by the input reaching the V2mon_orr threshold such fault condition is temporarily recorded in the fault detection regist
18. its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners GENERAL DESCRIPTION The AD5100 is a factory programmed system management IC that combines four channels of voltage monitoring and watchdog supervision The AD5100 can be used to shut down external supplies reset processors or disable any other system electronics when the system malfunctions The AD5100 can also be used to protect systems from improper device power up sequencing The AD5100 is a robust watchdog reset controller and can monitor two 30 V inputs with shutdown and reset controls one 2 3 V to 5 0 V input and one 1 6 V to 7 96 V input Most monitoring input thresholds and timing settings have a range of settings which are factory programmed by Analog Devices Inc in the one time programmable EPROM OTP memory or can be programmed on the fly over the serial interface The AD5100 is versatile for system monitoring applications where critical microprocessor DSP and embedded systems operate under harsh conditions such as automotive industrial or communications network environments The AD5100 is available in a compact 16 lead QSOP package and can operate in an extended automotive tempera
19. register there are two possibilities e Ifthe AD5100 address pointer register value is unknown or not at the desired value it is first necessary to set it to the correct value before data can be read from the desired data register This is done by performing a write to the AD5100 but only a value containing the register address is sent because data is not to be written to the register This is shown in Figure 22 A read operation is then performed consisting of the serial bus address R W bit set to 1 followed by the data byte from the data register This is shown in Figure 23 AD5100 e Ifthe address pointer is known to be already at the desired address data can be read from the corresponding data register without first writing to the address pointer register Table 14 shows the readback data byte structure Bits 6 0 con tain the data from the register just read Bit 7 is a reserved bit and should be ignored for normal read operations The majority of AD5100 registers are four bits wide with only the fault detect and status register and disable special functions register at seven bits and five bits wide respectively Table 14 Readback Data Byte Structure Bit Number Function 7 Reserved 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 DO LSB ACK BY AD5100 START BY FRAME 1 FRAME 2 MASTER SLAVE ADDRESS BYTE ADDRESS POINTER BYTE Figure 21 Writing a Register Address to the Address Pointer Register Then Writin
20. train is generated at the reset Rev A Page 33 of 36 AD5100 BATTERY CAN WAKE UP PULSE S AD5100 vo MICROPROCESSOR 1 0 RS yo 05692 030 Figure 29 Rising Edge Triggered Wake Up Mode WDI RESET SCL SCL SDA SDA WRITE SHDN NOTES 1 6V lt Vimon lt 30V 2 SELECT RISING EDGE TRIGGER CAN WAKE UP MODE 05692 031 Figure 30 Rising Edge Triggered Operation of Circuit Shown in Figure 29 Rev A Page 34 of 36 AD5100 OUTLINE DIMENSIONS 0 197 5 00 0 193 4 90 0 189 4 80 0 158 4 01 0 154 3 91 0 150 3 81 0 244 6 20 0 236 5 99 0 228 5 79 0 010 0 25 0 065 1 65 __ 0 069 1 75 0 006 0 15 gt mE 0 049 1 25 DX zd 0 053 1 35 i 1 GERRARD 24 0010 025 UNS T sory ol JL yas 4 REF 109 0 025 0 64 PLANE 0 0 050 1 27 COPLANARITY BSC 0 012 0 30 a O16 10 AM 0 004 0 10 0 008 0 20 0 016 0 41 COMPLIANT TO JEDEC STANDARDS MO 137 AB CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETERS DIMENSIONS lt IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR 3 REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 5 Figure 31 16 Lead Shrink Small Outline Package QSOP RQ 16 Dimensions shown in inches ORDERING GUIDE Model Temperature Range Package Description Package Option Ordering Quantity AD5100YRQZ 0 40 C to 125 C 16 Lead QSOP RQ 16 AD5100YRQZ 1RL7 40 C to 12
21. 0 slave address is 0101111 pulled up to 3 3 V maximum The ADO pin allows the user to connect two AD5100 devices to the same bus Table 13 and Figure 20 show an example of two AD5100 devices operating on the same serial bus independently Table 13 Slave Address Decoding Scheme ADO Programming Bit ADO Device Pin Device Addressed 0 0v Ox2E U1 1 3 3 V max Ox2F U2 Bit Number Function Reserved Address Bit 6 Address Bit 5 Address Bit 4 Address Bit 3 Address Bit 2 Address Bit 1 Address Bit O LSB NU WN SDA SCL wee T m 5V SDA SCL SDA SCL 3 3V MAX ADO ADO AD5100 AD5100 2 Figure 20 Two AD5100 Devices Bus 05692 021 Rev A Page 26 of 36 WRITING DATA AD5100 When writing data to the AD5100 the user begins by writing an address byte followed by the R W bit set to 0 The AD5100 acknowledges if the correct address byte is used by pulling the SDA line low during the ninth clock pulse The user then follows with two data bytes The first data byte is the address of the internal data register to be written to which is stored in the address pointer register The second byte is the data to be written to the internal data register After each byte the AD5100 acknowledges by pulling the SDA line low during the ninth clock pulse Figure 21 illustrates this operation READING DATA FROM AD5100 When reading data from an AD5100
22. 02 2 2 0 0 2 27 Temporary Override of Default 28 Applications Information eene 29 Car Battery and Infotainment System Supply Monitoring 29 Battery Monitoring with Fan Control sss 32 Battery State of Charge Indicator and Shutdown Early Warning Monitoring sse 32 Rising Edge Triggered Wake Up Mode 33 Outline Dimensions iacet rir e etnies 35 Ordering Guide zoe Ime meus 35 Automotive Products seen 35 Changes to Overcurrent Protection 22 Changes to ADI Register Map Section sss 23 Changes to Table 1 rre tr 23 Changes to Serial Interface Section and Table 12 26 Changes to Table 14 and Reading Data from AD5100 Section 27 Deleted Figure 25 eese bti 28 Deleted Permanent Setting ofAD5100 Registers Section 30 Changes to Ordering Guide and added Automotive Products SECLIOTI n SOOO ROUEN See eee 35 9 08 Revision 0 Initial Version Rev A Page 2 of 36 AD5100 FUNCTIONAL BLOCK DIAGRAM AD5100 6V 30 gt SHDN 55 E ON OFF 5E 3V TO 30V 5 O SHDNWARN 2 5 TO 5V V4MON 0 9V TO 30V 5 WDI DETECTION WDI AND RESET GENERATOR VorP SDA SCL 122 CONTROLLER
23. 16 Shutdown Output RESET OUTPUT RESET The reset output RESET is triggered by V3mon Vamon NOTES 1 2 SELECTABLE 2 DEFAULT 05692 016 underthreshold values RESET activation can also be the result of the processor not generating the proper watchdog signal if MR input is triggered or if SHDN is activated The reset generator asserts the RESET signal based on the following conditions e During power up e When drops below the threshold see Figure 10 e When drops below the threshold see Figure 12 When SHDN output is asserted see Figure 7 and Figure 14 RESET follows SHDN hold and delay timings if triggered by the SHDN output e When the external monitoring processor cannot issue the necessary WDI signal see Figure 13 and Figure 14 When MR is asserted see Figure 15 RESET is active low by default but can be configured for active high operation Register OxOD 1 controls the activation polarity of RESET It is possible to fix the value of this bit in OTP memory e Register OxOD 1 0 RESET is active low Default e Register OxOD 1 1 RESET is active high Rev A Page 19 of 36 AD5100 The RESET signal is asserted and maintained except when it is triggered by the WDI which is described in the Watchdog Input section The RESET signal is released after the programmable hold time tus uoi As shown in Figure 17 the RESET output is push pull con
24. 5 C 16 Lead QSOP RQ 16 1 000 AD5100YRQZ 1REEL 40 to 125 C 16 Lead QSOP RQ 16 2 500 EVAL AD5100EBZ Evaluation Board 17 RoHS Compliant Part AD5100YRQZ 0 Non OTP programmed part intended for evaluation purposes only AUTOMOTIVE PRODUCTS The AD5100 models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications Note that these automotive models may have specifications that differ from the commercial models therefore designers should review the Specifications section of this data sheet carefully Only the automotive grade products shown are available for use in automotive applications Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models Rev A Page 35 of 36 AD5100 NOTES refers to a communications protocol originally developed by Philips Semiconductors now NXP Semiconductors 2009 2010 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners TUA DEVICES Rev A Page 36 of 36 www analog com
25. N delay and hold timings when triggered by V mox The OV threshold chosen must be greater than the UV threshold When the shutdown is triggered either because the input has reached the OV or UV threshold such fault conditions are temporarily recorded in the fault detection register The SHDNWARN output transitions low for signaling before the shutdown output SHDN activates The timing of the SHDN output is dependent on how long the shutdown programmed delay tiso is set relative to the SHDNWARN propagation delay tro This feature attempts to allow the system to finish any critical housekeeping tasks before shutting down the external device The Vivon shutdown and shutdown warning timing diagrams are shown in Figure 7 The ranges of OV and UV thresholds are shown in Table 6 and the programming codes for the selected thresholds are found in Table 7 The defaulted OV threshold is 18 00 V and for UV threshold it is 8 43 V Similarly the ranges of shutdown hold and delay times are shown in Table 8 and the programming codes for the selected timings are shown in Table 9 Vimon exhibits typical input resistance of 55 that users should take into account for loading effect The voltage at Vimon provides the power for the AD5100 but a valid signal on must be present before the internal power rail starts operation Details are explained in the Power Requirements section Rev A
26. OUTPUTS SHUTDOWN OUTPUT SHDN The shutdown output SHDN is triggered by Vimon or over or underthreshold values or as the result of a failed watchdog input SHDN can also be asserted low at any time by writing to certain registers on the AD5100 The shutdown generator asserts a logic low SHDN signal based on the following conditions e During power up e When goes over or under the threshold see Figure 7 When is below the turn on threshold during the rising edge or the turn off threshold during the falling edge in level sensitive mode see Figure 7 When the external monitoring processor cannot issue the necessary WDI signal and advanced WDI mode is selected see Figure 10 and Figure 9 e programmed shutdown To activate SHDN by writing to the part the user must first enable this feature by writing to Register 0x18 4 e Register 0x18 4 0 enable software control of SHDN e Register 0x18 4 1 disable software control of SHDN Once the feature is enabled control of SHDN is achieved by writing to Register 0x16 2 e Register 0x16 2 0 SHDN output not controlled by software e Register Ox16 2 1 SHDN output is pulled low The SHDN signal is released after the programmable hold time tsp nor The SHDN output is push pull configured with an selectable rail voltage of either Vimon in default or internal Vres Register 0x0E 3 controls the voltage rail for SHDN This bit
27. Page 13 of 36 AD5100 tisp_DELAY tisp DELAY uu i i tosp_HOLD 4 SHDN AND RESET pELAv B DELAY a SHDNWARN NOTES 1 PROGRAMMABLE 2 THE DURATION OF THE tyjy MUST BE SHORTER THAN orr OR ELSE THE AD5100 WILL BE POWERED OFF Se ee bee 1 1 1 1 1 1 1 1 1 1 1 V1MON VauoN uv cose 1 pene Neat Meere seite V2MON ON ESO A ks eM Y V2MON OFF 1 1 1 1 1 1 t tosp_DELAY lt bsp pELAY DELAY ppLav r3 a 05692 006 Figure 7 Vimon and Shutdown Timing Diagrams in Level Sensitive Mode Note that RESET Follows SHDN is a high voltage monitoring input that controls the SHDN and RESET functions of the external devices monitors inputs from 3 V to 30 V It has a 16 level programmable turn on and turn off on off hysteresis thresholds Register 0x03 and Register 0x04 with an 8 step 0 07 ms to 200 ms shutdown hold time and 0 07 ms to 1200 ms shutdown delay tosp_peLay The pin is monitored by two comparators one for turn on and one for turn off detection
28. SHOLD Vaour NOTES 1 RESET DISABLED 05692 028 Figure 27 V4our with Respect to Vremp with Vamon RESET Disabled in Circuit Shown in Figure 26 IGNITION BATTERY AD5100 MICROPROCESSOR SHDNWARN K MISO MOSI 05692 029 CLK Figure 28 Battery State of Charge Indication Rev A Page 32 of 36 AD5100 RISING EDGE TRIGGERED WAKE UP MODE output if there is no watchdog activity The pulse continues until the correct watchdog signal appears at the AD5100 WDI pin The shutdown pin remains high as long as the AD5100 continues to receive the correct watchdog signal As indicated in Figure 29 the microprocessor can control its own power down sequence using the rising edge triggered wake up signal The operator must select the rising edge triggered wake up mode setting for the Vomon turn off When the microprocessor finishes its housekeeping tasks or threshold value as shown in Table 6 by setting Register powers down the software routine it stops sending a watchdog 0x04 3 1 1001 signal In response the AD5100 generates a reset The shut down pin is pulled low 2 seconds after and the regulator output drops to 0 V which shuts down the microprocessor At that point the AD5100 enters sleep mode When the rising edge wake up signal is detected the AD5100 is powered up with the SHDN pin pulled high The external regulator is turned on to supply power to the microprocessor A reset pulse
29. STERESIS 5 RESET RESET Hold Time Tolerance Atrs_HoLD Ta 25 does not apply to 10 10 See Figure 10 Figure 12 and Table 8 Code 0x6 and Code 0x7 Ta 40 C to 125 does not 17 17 apply to Code 0x6 Code 0x7 Vamon Vamon to RESET Delay trs_DELAY 60 us RESET Output Voltage High Vamon gt 4 38 V Isour 120 pA Vamon 1 5 V 2 7 V lt lt 4 38 V 0 8 V3mon V Isource 30 UA 2 3 V lt lt 2 7 V 0 8 V Isource 20 UA 1 8 V Vamon lt 2 3 V 0 8 V Isource 8 pA RESET Output Voltage Low Vo Vamon gt 4 38 V 3 2 mA 0 4 V lt 4 38 V Isink 1 2 mA 0 3 V RESET Output Short Circuit Current Isource RESET 0 5 5 V 825 UA RESET 0 3 6 V 400 Glitch Immune Time teutcH 50 us Vaour Maximum Output Vaour Open drain 5 5 V Vaour Propagation Delay tvaouT_DELAY 70 us Maximum Frequency fvaour Applies to RESET disabled only 10 kHz WDI WATCHDOG INPUT WDI Programmable Timeout Tolerance Atwo Ta 25 C 10 10 see Figure 13 and Table 8 Ta 40 C to 125 C 17 17 WDI Pulse Width 50 ns Watchdog Initiated RESET Pulse Width twor When no WDI two 50 ms Watchdog Initiated SHDN twp sHDN When activity gt 4 two 1 sec WDI Input Voltage Low Vi 0 3 x Vamon V WDI Input Voltage High 0 7 V WDI Input Current WDI V3mon 160 WDI 0 20
30. be power cycled In some cases the AD5100 can be connected to an bus with lots of activity Setting these bits is an added means of ensuring that any erroneous activity on the bus does not cause AD5100 special functions to become active Rev A Page 25 of 36 AD5100 SERIAL INTERFACE Control of the AD5100 is via serial bus The AD5100 is connected to this bus as a slave device the AD5100 has no master capabilities The 2 wire serial bus protocol operates as follows l master initiates data transfer by establishing a start condition which occurs when SDA goes from high to low while SCL is high The following byte is the slave address byte which consists of the 7 bit slave address followed by an R W bit that determines whether data is read from or written to the slave device 2 Data is transmitted over the serial bus in sequences of nine clock pulses eight data bits followed by an acknowledge bit The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL 3 When all data bits have been read or written a stop condition is established by the master A stop condition is defined as a low to high transition on the SDA line while SCL is high In write mode the master pulls the SDA line high during the 10 clock pulse to establish a stop condi tion In the read mode the master issues a no acknowledge for the ninth clock pulse tha
31. comparator becomes inactive indicating that the OV condition has gone away see Figure 6 HYSTERESIS _ V1M0N V4MON UV 1 1 1 1 1 1 1 1 1 i OV COMPARATOR COMPARATOR 1 1 UV UV COMPARATOR COMPARATOR ACTIVE INACTIVE 05692 007 Figure 6 Vimon Hysteresis When the Vivon input drops below the programmed under voltage UV threshold the comparator becomes active immediately indicating that a UV condition has occurred Similarly due to hysteresis the Vimon input must be brought above the programmed UV threshold by 1 596 before the comparator becomes inactive indicating that the UV condition has gone away Both Vimon comparators are used in conjunction with hold and delay timers to control the SHDN and RESET pins Vimon has 16 level programmable OV threshold Register 0x01 and UV threshold Register 0x02 with an 8 step 0 07 ms to 200 ms shutdown hold time tisp and 0 07 ms to 1200 ms AD5100 shutdown delay tisp The shutdown hold time means that the SHDN signal is held low for tisp after Vimon returns within its UV and OV thresholds The shutdown delay means that the SHDN signal activation is delayed until the programmed tisp has elapsed SHDN activates once the voltage on Vimon is outside the OV or UV threshold for a time longer than teurrcu RESET follows SHD
32. er The SHDNWARN output transitions low for signaling before the shutdown output SHDN activates The timing of the SHDN output is dependent on how long the shutdown programmed delay 45 is set relative to the SHDNWARN propagation delay trp This feature allows the system to finish any critical housekeeping tasks before shutting down the external device SHDN activates once the voltage on V2monis outside the threshold for a time longer than RESET follows SHDN delay and hold timings when triggered by The V2mon shutdown and shutdown warning timing diagrams are shown in Figure 7 Rev A Page 14 of 36 The ranges of on and off thresholds shown Table 6 and the programming codes for the selected thresholds are found in Table 7 The default on threshold is 7 47 V and off threshold is 6 95 V Similarly the ranges of shutdown hold and delay times are shown in Table 8 and the programming codes of the selected timings are found in Table 9 The default shutdown hold time is 10 ms and the delay time is 100 ms is ignored if orr is greater than but cannot equal If is selected with rising edge triggered wake up mode only the on threshold is monitored and the off threshold is ignored is put into rising edge triggered mode by setting V2mon off threshold Register 0x04 3 0 to 1001 The volta
33. figured with the rail voltage of itt N 05692 017 Figure 17 Reset Output SHUTDOWN WARNING SHDNWARN An early shutdown warning is available for the system processor to identify the source of failure and take appropriate action before shutting down the external devices Whenever the voltage at Vimon is detected as overvoltage or undervoltage or the voltage at falls below the threshold SHDNWARN outputs a Logic 0 If the processor sees a logic low on this pin the processor may issue an read command to identify the cause of failure reported in the fault detect status register at Address 0x19 The processor may store the information in external EEPROM as a record of failure history Vaour OUTPUT Viovr is an open drain output triggered by Vamon with mini mum propagation delay Vaour can be used as a PWM control over an external device or used as a monitoring signal Most applications using Vaour require disabling of the Vamon triggered reset function This function is disabled by writing to Register OxOD 2 and it is possible to fix the value of this bit in OTP memory Register 0x0D 2 0 enables Vamon under threshold to activate RESET e Register 0x0D 2 1 prevents Vamon under threshold from activating RESET Rev A Page 20 of 36 POWER REQUIREMENTS INTERNAL POWER V uc The AD5100 internal power is derived from Vimon and becomes
34. g Devices will create an AD5100 model with the desired default settings and factory program the AD5100 OTP memory with Some users may use the AD5100 as a set and forget device that is program some default values and never need to change these over the life of the application However some users may require on the fly flexibility that is the ability to change settings to values other than those they choose as their defaults Register writing reading OTP and override are explained in the Serial Interface section Register Read Permanently NonOTP Power On Address Write Settable Register Name and Bit Description Default 0x01 R W Yes Vimon overvoltage threshold 0x00 18 00 V Bit No Description 3 0 Four bits used to program Vimon OV threshold 7 4 Reserved 0x02 R W Yes Vimon undervoltage threshold 0x00 8 43 V Bit No Description 3 0 Four bits used to program Vimon UV threshold 7 4 Reserved 0x03 R W Yes V2mon turn on threshold 0x00 7 47 V Bit No Description 3 0 Four bits used to program on threshold 7 4 Reserved 0x04 R W Yes turn off threshold 0x00 6 95 V Bit No Description 3 0 Four bits used to program off threshold 7 4 Reserved 0x05 Yes Vamon RESET Threshold 0x00 2 93 V Bit No Description 2 0 Three bits used to program Vsmon RESET threshold 7 3 Reserved 0x06 R W Yes
35. g Data to the Selected Register ACK BY AD5100 ACK BY AD5100 FRAME 3 STOP BY DATA BYTE MASTER 05692 022 ACK BY ACK BY AD5100 AD5100 START BY FRAME 1 FRAME 2 STOP BY MASTER SLAVE ADDRESS BYTE ADDRESS POINTER BYTE MASTER Figure 22 Dummy Write to Set Proper Address Pointer SCL SDAN 0 1N0 1 1WADNRW orE peX ps D3X n2 D1X Do OK ACK BY NO ACK BY AD5100 MASTER START BY FRAME 1 FRAME 2 STOP BY MASTER SLAVE ADDRESS BYTE READ DATA BYTE MASTER Figure 23 Read Data from the Address Pointer Register Rev A Page 27 of 36 05692 023 05692 024 AD5100 TEMPORARY OVERRIDE OF DEFAULT SETTINGS Even with OTP Programmed parts it is possible to temporarily override the default values of any of the permanently program mable registers To override a permanent setting in a particular register when the lock bit is programmed the following sequence should be used 1 Set Bit 3 1 in Register 0x16 special function 1 2 Write the desired temporary data to the register of choice While the override bit Bit 3 is set in Register 0x16 the user can override any registers by simply writing to them with new data To reset an overridden register to its default setting the following sequence should be used 1 Set Bit 3 0 in Register 0x16 2 Write dummy byte to the register of choice Clearing the override bit in Register 0x16 does not cause all overridden registers to revert to their defaults
36. ge at Vimon provides the power for the AD5100 but a valid signal on must be present before the internal Vreg starts operating Details are explained in the Power Requirements section V2mon exhibits typical input resistance of 675 that users should take into account for loading effect V3mon is a low voltage monitoring input that controls the RESET function of an external device The Vsmon pin is monitored by a comparator to detect undervoltage condition It is designed with 1 596 hysteresis When the input drops below the programmed UV threshold the comparator becomes active immediately indi cating that a UV condition has occurred Due to hysteresis the Vsmon input must be brought above the programmed UV threshold by 1 596 before the comparator becomes inactive indicating that the UV condition has gone away see Figure 9 Sie 1 1 1 1 1 1 2 RS HOLD 1 gt RESET 5 1 PROGRAMMABLE tas DELAY AD5100 7 K 44 UV COMPARATOR uv INACTIVE COMPARATOR INACTIVE 05692 010 Figure 9 Hysteresis The Vsmon comparator is used in conjunction with a hold timer to control the RESET pin monitors inputs from 2 0 V to 5 5 V It has an 8 step programmable reset thres
37. he battery first conducts through the P1 body diode as soon as the voltage reaches its source terminal The voltage divider provides adequate gate to source voltage to turn on P1 and the voltage drop across the FET is negligible The resistor divider values are chosen such that the maximum of the P1 is not violated and the current drawn through the battery is only a few microamps EMI Protection For EMI protection a ferrite bead or EMC rated inductor such as DR331 7 103 can be used R3 220 R4 2 20 1 1MON SMCJ17 AD5100 V2MON D2 D4 DIGIPOT SMCJ17 MMBZ27VCL 05692 020 Figure 19 Protection Circuits Rev A Page 22 of 36 AD5100 REGISTER MAP Table 11 outlines the AD5100 register map used to configure and control all parameters and functions in the AD5100 and indicates whether registers are writable readable or permanently settable All registers have the same address for read and write operations The AD5100 ships from the factory with default power up values set in OTP memory These default values are different for each AD5100 model However nonprogrammed samples are avail able for evaluation purposes The user can experiment with different settings in the various threshold delay and configuration registers Table 11 AD5100 Register Map these defaults AD5100 Once evaluation is complete the user should contact Analog Devices with their desired OTP memory default values Analo
38. hold Register 0x05 with an 8 step 0 1 ms to 200 ms reset hold time tns uoi The reset hold time means that the RESET output remains activate when goes above its UV threshold until tas has elapsed This allows the reset of an external device to be held until the programmed time is reached The and RESET timing diagrams are shown in Figure 10 The range of thresholds is shown in Table 6 and the programming code for the selected threshold is found in Table 7 The range of reset hold times is shown in Table 8 and the programming code of the selected timing is found in Table 9 exhibits typical input resistance of 130 that users should take into account for loading effect The MR input has an internal resistor pull up toVsmon The RESET output is push pull between and GND 1 1 1 1 1 1 1 1 1 1 1 ins HOLD tns pELAY m 05692 009 Figure 10 RESET Timing Diagrams Rev A Page 15 of 36 AD5100 Vamon is a low voltage monitoring input that controls the RESET function of an external device or provides a comparator output Vaour The Vamon pin is monitored by a comparator to detect undervoltage condition It is designed with 5 hysteresis When the Vamon input drops below the programmed UV thresh old the comparator becomes active immediately indicating that a UV condition has occurred Due to hysteresis the
39. id watchdog signal a rising or falling edge signal at the WDI is received The internal watchdog timer clears whenever a reset is asserted The standard WDI and RESET timing diagrams are shown in Figure 13 1 two 1 51 WDI 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 two lt two ha 1 twor 1 twor ty lg RESET RESET PULSE twor WATCHDOG INITIATED RESET PULSE WIDTH twp WATCHDOG PULSE WIDTH twp WATCHDOG PROGRAMMABLE TIME AD5100 Advanced Watchdog Mode The AD5100 can be programmed into an advanced watchdog mode In this mode if WDI remains either high or low for longer than the timeout period twp a RESET pulse is generated as per standard mode However if the WDI input remains inactive after three such RESET pulses concurrent with the fourth RESET pulse SHDN is also asserted SHDN is released after 1 second These actions repeat indefinitely unless action is taken by the user if the processor is not responding The advanced WDI and RESET timing diagrams are shown in Figure 14 CONTINUOUS PULSES UNTIL WATCHDOG AWAKES 05692 013 Figure 13 Standard Watchdog Pulsing Reset Until Watchdog Awakes gt two SHDN r t 11 two r 11 WDI 1 1 1 1 1 1 1 two twor two e I e NET ro RESET 1 RESET PULSE 3 RESET PULSES SHUTDOWN AT 4TH RESET PULSE SHDN
40. in Table 9 V mon exhibits typical input resistance of 675 that users should take into account for loading effect WATCHDOG INPUT The watchdog input WDI circuit attempts to reset the system to a known good state if a software or hardware glitch renders the system processor inactive for a duration that is longer than the timeout period The timeout period two is programmable in eight steps from 100 ms to 2000 ms The watchdog circuit is independent of any CPU dock that the watchdog is monitoring The range of watchdog timeout is shown in Table 8 and the programming code of the selected timeout is found in Table 9 The default timeout is 1500 ms The watchdog is disabled during power up WDI starts monitor ing once RESET is high The AD5100 provides a standard or advanced watchdog monitoring function Register OxOF 3 sets the watchdog function to either standard or advanced mode This bit can be fixed in OTP memory e Register OxOF 3 0 standard watchdog mode Default e Register OxOF 3 1 advanced watchdog mode trs HOLD Mey 05692 011 Figure 12 Vamon RESET and Vsovr Timing Diagrams Rev A Page 16 of 36 Standard Watchdog Mode In the default standard watchdog mode if WDI remains either high or low for longer than the timeout period two a RESET pulse is generated in an attempt to allow the system processor to reestablish the WDI signal The RESET pulses continue indefinitely until a val
41. is derived from Vimon There must be a 10 pF electrolytic capacitor between this pin and GND placed as close as possible to the Vimon pin 2 GND Ground 3 Vore One Time Programmable Supply Voltage for EPROM A 10 uF decoupling capacitor low ESR to GND is required 4 Low Voltage Monitoring Input 5 MR Manual Reset Input Active low 6 WDI Watchdog Input 7 SCL Serial Input Register Clock Open drain input If it is driven directly from a logic driver without the pull up resistor ensure that the minimum is 3 3 V 8 SDA Serial Data Input Output Open drain input output If it is driven directly from a logic driver without the pull up resistor ensure that the minimum is 3 3 V 9 RESET Reset Push pull output with rail voltage of Vamon 10 Vaour Open Drain Output Triggered by Vamon 11 SHDNWARN Shutdown Warning Active low open drain output 12 SHDN Shutdown Output Push pull output with selectable rail voltage of Vimon the AD5100 internal power 30 V maximum 13 ADO PC Slave Address Configuration If tied high this pin can only be tied to 3 3 V maximum 14 Low Voltage Monitoring Input Capable of withstanding 30 V 15 GND NC Ground No Connect Can be grounded or left floating but do not connect to any other potentials 16 High Voltage Monitoring Input It is also the internal supply voltage enabling input GND TOP VIEW 5 Not to Scale 12 05692 004
42. le 10 AD5100 Functions and Features Monitoring Shutdown Reset Fault Input Range Control Control Detection Functions and Features If Not Used Vimon 6V to 28 29V Yes Yes Yes Overvoltage undervoltage thresholds Does not apply Vamon 3V to 24 75V Yes Yes Yes On off voltage thresholds pseudo rising edge Connect to Vimon triggered wake up selectable MOST wake up minimum input 6 V signal Vawou connected to Vamon Vamon 2 32Vto 4 97V No Yes Yes Connect to Vore and set threshold to minimum Vamon 1 67V to 7 96V No Yes Yes Additional output Connect to GND WDI OVto5V Yes Yes No Standard advance or floating watchdog Leave floating selectable MR OVto5V Yes Yes No Highest priority on RESET over other inputs Leave floating Rev A Page 12 of 36 MONITORING INPUTS Vimon Vimon is a high voltage monitoring input that controls the SHDN and RESET functions of the external devices In addition it provides a shutdown warning to the system Vimon monitors inputs from 6 V to 30 V The pin is monitored by two comparators one for overvol tage and one for undervoltage detection Both are designed with 1 5 hysteresis When the Vivon input goes above the programmed overvoltage OV threshold the comparator becomes active immediately indicating that an OV condition has occurred Due to hysteresis the Vimon input must be brought below the programmed OV threshold by 1 596 before the
43. me of both SDA and SCL signals 0 3 us to tr rise time of both SDA and SCL signals 0 3 us to tsusro setup time for stop condition 0 6 us 1 Guaranteed by design and not subject to production test 2 See Figure 2 SCL SDA Figure 2 Digital Interface Timing Diagram Rev A Page 7 of 36 05692 002 AD5100 ABSOLUTE MAXIMUM RATINGS Table 4 Parameter Rating Vimon to GND 0 3 V 33 V Vamon to GND 0 3 V 33 V V3mon to GND 0 3V 47V to GND 0 3 V 33 V Vote to GND 0 3 V 7V Digital Input Voltage to GND OV 7V MR WDI SCL SDA ADO Digital Output Voltage to GND OV 7V RESET SHDNWARN Digital Output Voltage to GND SHDN 433V Operating Temperature Range Storage Temperature Range ESD Rating HBM Maximum Junction Temperature Tmax Power Dissipation Thermal Impedance Junction to Ambient Junction to Case IR Reflow Soldering RoHS Compliant Package Peak Temperature Time at Peak Temperature Ramp Up Rate Ramp Down Rate Time from 25 to Peak Temperature 40 C to 125 65 C to 150 C 3 5 kV 150 C Timax 2 105 44 C W 38 8 C W 260 C 0 C 20 sec to 40 sec 3 C sec max 6 C sec max 8 minutes max Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these
44. n 0 0 allows override of any of the registers in memory except Register 0x16 Bit 2 0 and Register 0x17 Bit 0 1 disables override of any of the registers in memory except Register 0x16 Bit 2 0 and Register 0x17 Bit O 1 Reserved 2 Reserved 3 0 allows software power down function 1 disables software power down function 4 0 allows software assertion of SHDN pin 1 disables software assertion of SHDN pin 7 5 Reserved 0x19 Read No Fault detect and status 0x40 only Bits 3 0 are level triggered bits that indicate the current state of the comparators monitoring the Vimon and V2mon input pins Bits 6 4 are edge triggered fault detection bits that indicate what error conditions were present when a SHDN event occurred Bit No Description 0 1 input lt Vamon off threshold 1 1 input gt V2mon on threshold 2 1 Vimon input lt Vimon UV threshold 3 1 Vimon input gt Vimon OV threshold 6 4 000 none 001 Vimon UV only 010 Vimon OV only 011 never occurred 100 Vamon below off only default 101 Vimon UV and below off both occurred 110 Vimon V2mon below off both occurred 111 never occurred 7 Reserved Default settings of AD5100 0 evaluation model only 2 must be 0 V that is must be configured in edge sensitive mode for software power down 3 These register bits are set only To clear them the AD5100 must
45. n 12 V and 12 V 2 Initial turn on minimum remains as 2 2 V but the 3 V to 30 V specifications apply afterward 3 Does not apply if is a digital signal 4Vamon threshold limits see Table 6 are designed to primarily allow to monitor low voltage inputs The Vamon input pin is capable of withstanding voltages up to 30 V One application where this 30 V capability is useful is electronic media oriented systems transport eMOST diagnostic circuits 5 The RESET short circuit current is the maximum pull up current when RESET is driven low by a microprocessor bidirectional reset pin 6 It is typical for the SCL and SDA to have resistors pulled up to However care must be taken to ensure that the minimum is met when the SCL and SDA are driven directly from a low voltage logic controller without pull up resistors Rev A Page 6 of 36 AD5100 TIMING SPECIFICATIONS Table 3 Parameter Description Min Typ Max Unit INTERFACE TIMING CHARACTERISTICS 2 SCL clock frequency 400 kHz ti teur bus free time between start and stop 1 3 us t2 hold time after repeated start condition after this 0 6 us period the first clock is generated ts tiow low period of SCL clock 1 3 us t4 high period of SCL clock 0 6 50 us ts tsussta Setup time for start condition 0 6 us te tup par data hold time 0 9 Us t tsupar data setup time 0 1 HS ts te fall ti
46. nabled e Register 0x18 3 0 enable software power down feature e Register Ox18 3 1 disable software power down feature The user must then write to Register 0x17 0 to actually power down the AD5100 e Register Ox17 0 0 AD5100 not in software power down e Register 0x17 0 1 power down AD5100 This feature is for applications that use a wake up signal V2MON OFF me t2sD_DELAY pe P tosp_DELAY tvREG_OFF_DELAY 05692 018 Figure 18 Internal Power Vres vs Timing Diagrams Default Rev A Page 21 of 36 AD5100 PROTECTION For automotive applications proper external protections on the AD5100 are needed to ensure reliable operation The Vimon is likely to be used for battery monitoring The V2mon is likely to be used for ignition switch or other critical inputs As a result these inputs may need additional protections such as load dump and ESD protections In addition battery input requires reverse battery protection and short circuit fuse protection see Figure 19 Overcurrent Protection If the Vimon is shorted internally in the AD5100 to GND the short circuit protection kicks in and limits subsequent current to 150 mA in normal operation Thermal Shutdown When the AD5100 junction temperature is near the junction temperature limit it automatically shuts down and cuts out the power from The part resumes operation when the device junction temperature
47. ogrammable OTP Options 5 10 Theory of Operation eese entente netten tenentes 12 Monitoring Inputs 13 Mal ION saves 13 V MON 14 15 V MON c 16 Watchdog Input miiir eee p EIER 16 gt e ei neus 18 19 REVISION HISTORY 6 10 Rev 0 to Rev A Changed Programmable to Factory Programmed Thro g 1 Changes to Features Section and General Description Section 1 Changes to and MR Resistance Specifications Throughout sssseeeee 4 Changes torTable teda e eerie 4 Changes to Table 5 iiti ei e tei ege 9 Deleted Figure 18 Renumbered Sequentially 21 Changes to Rising Edge Triggered Wake Up Mode Section 21 Shutdown Output SHDN uu 19 Reset Output RESET M 19 Shutdown Warning SHDNWARN ee 20 Vaour Output Power Requirements Internal Power Vas Rees 21 22 AD5100 Register Map seen 23 debite ebbe 26 Writing Data to 5100 27 Reading Data from 5100 022
48. or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Values relate to the package being used a 4 layer board 2 Ta ambient temperature 3 Junction to case resistance is applicable to components featuring a preferential flow direction for example components mounted heat sink Junction to ambient resistance is more useful for air cooled PCB mounted components Rev A Page 8 of 36 AD5100 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Vimon L 16 GND 2 15 GND NC 3 14 4 05100 13 ADO I TOP VIEW MR 5 Not to Scale 12 SHDN 6 1 SHDNWARN SCL 10 Vaour spa 9 RESET NC NO CONNECT 05692 003 Figure 3 Pin Configuration Table 5 AD5100 Pin Function Descriptions Pin No Mnemonic Description 1 Vimon High Voltage Monitoring Input AD5100 internal supply
49. returns to normal ESD Protection It is common to require a contact rating of 8 kV and a contact or air rating of 15 kV ESD protection for the automotive electronics As a result an ESD rated protection device must be used such as MMBZ27VCL a dual 40 W transient voltage suppressor TVS at the Vimon and Vomon NDT2955 1 10 C1 DR331 7 103 0 5i MET E 2MO R2 1 5MQ F1 B lt L1 LI L1 VMAIN IGNITION SWITCH C2 0 1 iH Load Dump Protection A load dump is a severe overvoltage surge that occurs when the car battery is being disconnected from a spinning alternator and a resulting long duration high voltage surge is introduced into the supply line Therefore external load dump protection is recommended Typically the load dump overvoltage lasts for a few hundred milliseconds and peaks at around 40 V to 70 V while current can be as high as 1 A As a result a load dump rated TVS D1 and D2 such as SMCJ17 are used to handle the surge energy A series resistor is an inline current limiting resistor it should be adequate to limit the current without significant drop and yet small enough to not affect the input monitoring accuracy Reverse Battery Protection Reverse battery protection can be provided by a regular diode if the battery monitoring accuracy can be relaxed Otherwise a 60 V P channel power MOSFET like the NDT2955 can be used Because of the MOSFET internal diode t
50. s from 2 93 V to 7 96 V The two high voltage monitoring inputs control the SHDN 0 shutdown signal SHDN and reset signal RESET while the two low voltage monitoring inputs control the reset signal RESET SHDN and RESET are both disabling signals for external devices The differences between these two outputs are in output level and driving capabilities as described in the Outputs section The WDI watchdog and MR manual reset inputs also control the RESET output for use with an external digital processor Figure 5 shows the general flow chart and Table 10 summarizes the AD5100 functions and features YES FLOATING WDI 1 WDI DISABLED gt FLoarine Vomon RISING EDGE NO ADVANCE WDI SELECTED RESET 0 i SENSITIVE SELECTED wpiserECTEDI 7 7 i 1 LEVEL mea SENSITIVE lo SELECTED RESET 0 VALID WDI RESET 0 5 SHDN 0 hated septa 1 V3MON gt RESET 0 Vomon gt OFF THRESHOLD YES NO V NO D rer er 4MON gt BEGET _ THRESHOLD RESET 0 YES NO Vaout 0 CONTINUE MONITORING DEFAULT PATHS SEE TABLE 11 RESET CONFIGURATION REGISTER IF 0 0 THEN SHDN 0 AND RESET 0 IF 0 1 THEN SHDN 0 AND RESET 1 05692 005 Figure 5 General Flow Chart Tab
51. t is the SDA line remains high The master then brings the SDA line low before the 10 clock pulse and high during the 10 clock pulse to establish a stop condition For the AD5100 write operations contain either one or two bytes while read operations contain one byte The AD5100 makes use of an address pointer register This address pointer sets up one of the other registers for the second byte of the write operation or for a subsequent read operation Table 12 shows the structure of the address pointer register Bits 6 0 signify the address of the register that is to be written to or read from Bit 7 is a reserved bit and should be 0 for normal write read operations Table 12 Address Pointer Register Structure SCL The serial input register clock pin shifts in one bit at a time on positive clock edges An external 2 2 to 10 pull up resistor is needed The pull up resistor should be tied to Vsmon provided V wow is sub 5 V SDA The serial data input output pin shifts in one bit at a time on positive clock edges with the MSB loaded first An external 2 2 to 10 pull up resistor is needed The pull up resistor should be tied to Vsmon provided is sub 5 V ADO The AD5100 has a 7 bit slave address The six MSBs are 010111 and the LSB is determined by the state of the ADO pin When the slave address pin ADO is low the 7 bit AD5100 slave address is 0101110 When ADO is high the 7 bit AD510
52. ture range from 40 C to 125 Analog Devices provides non OTP programmed AD5100 parts for use in evaluating the desired threshold and delay settings Only factory programmed AD5100 parts are shipped in production quantities Contact Analog Devices directly to inquire about factory programmed models Table 1 AD5100 General Input and Output Information Monitoring Shutdown Reset Fault Input Range Control Control Detection Vimon 6V to 28 29V Yes Yes Yes 3V to 24 75 V Yes Yes Yes V3mon 2 32Vto 4 97V Yes Yes Vamon 1 67 0 7 96V No Yes Yes WDI OVto5V Yes Yes No MR OVto5V No Yes No 1 With programmable threshold and programmable delay One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2009 2010 Analog Devices Inc All rights reserved AD5100 TABLE OF CONTENTS Features EE 1 Applications idee nbl Ren ero e SY 1 General Descriptions ecce tti eie Red 1 Revision History carcer OPI es 2 Functional Block Diagram sse 3 t 4 Electrical Specifications rettet ttti tetris 4 Timing Specifications sees 7 Absolute Maximum Ratings eene 8 ESD Caution RISE RE 8 Pin Configuration and Function 9 One Time Pr

ANALOG DEVICES AD5100 English products handbook

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