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ANALOG DEVICES ADP7104 handbook Rev B

1. 10 100 1k 10k 100k FREQUENCY Hz 1M 10M 09507 029 Figure 34 Power Supply Rejection Ratio vs Frequency Vour 3 3 V Vn 2 4 8V Rev B Page 11 of 28 ADP7104 LOAD 500mA LOAD 500mA LOAD 300mA LOAD 300mA 10 LOAD 100mA 10 LOAD 100mA LOAD 10mA LOAD 10mA 20 LOAD 20 LOAD 1mA 20 30 30 a 40 a 40
2. 1 85 LOAD 100nA 9n 100p LOAD 100 LOAD 1mA LOAD imA LOAD 10mA 800 f _ LOAD 10mA Nim LOAD 100mA LOAD 100mA 83 300m LOAD A LOAD 500mA 5 600 1 81 E B 500 8 3 400 gt 4 79 2 O 300 tc 1 77 200 100 1 75 40 C 5 C 25 C 85 C 125 C 5 40 C 5 C 25 C 85 C 125 C Ty C E T C Figure 23 Output Voltage vs Junction Temperature Vour 1 8 V Figure 26 Ground Current vs Junction Temperature Vour 1 8 V 1 85 700 600 1 83 500 1 81 5 H 400 5 5 KS o 1 79 Q 300 2 2 5 200 1 77 100 1 75 a 0 0 1 1 10 100 1000 8 0 1 1 10 100 1000 lLoAp mA 8 lLoAp mA Figure 24 Output Voltage vs Load Current Vour 1 8 V Figure 27 Ground Current vs Load Current Vour 1 8 V 1 85 1200 LOAD 100pA LOAD 100pA LOAD 1mA LOAD 1mA LOAD 10mA LOAD 10mA LOAD 100mA 1000 LOAD 100mA 1 83 LOAD 300mA LOAD 300mA LOAD 500mA PE LOAD 500mA E a E 800 5 1 81 6 5 5 600 2 o 1 79 2 2 400 tc 8 1 77 200 1 75 g 0 2 4 6 8 10 12 14 16 18 20 8 2 4 6 8 10 12 14 16 18 20 Vin V 8 Vin V Figure 25 Output Voltage vs Input Voltage Vour 1 8 V Figure 28 Ground Current vs Input Voltage Vour 1 8 V Rev B Page 10 of 28 09507 126 09507 127 09507 024 LOAD 100pA LOAD 1m LOAD 10mA LOAD 100mA LOAD 300mA LOAD
3. Figure 73 SOIC TA 25 C 6400mm 500mm 25mm TJ MAX 0 0 2 04 0 6 0 8 1 0 1 2 1 4 1 6 1 8 145 135 125 115 105 95 85 75 65 TOTAL POWER DISSIPATION W Figure 74 SOIC Ta 50 C 6400mm 500mm 25mm TJ MAX 0 01 02 03 04 05 06 07 08 09 1 0 TOTAL POWER DISSIPATION W Figure 75 SOIC Ta 85 C 09507 068 09507 069 09507 070 ADP7104 In the case where the board temperature is known use the thermal characterization parameter Yp to estimate the junction temperature rise see Figure 76 and Figure 77 Maximum junction temperature is calculated from the board temperature and power dissipation Pp using the following formula Tat Pp x Wp 5 The typical value of jp is 15 1 C W for the 8 lead LFCSP package and 31 3 C W for the 8 lead SOIC package 140 120 100 80 60 40 JUNCTION TEMPERATURE Tj 20 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 6 5 7 0 TOTAL POWER DISSIPATION W Figure 76 LFCSP 09506 071 JUNCTION TEMPERATURE Ty 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 TOTAL POWER DISSIPATION W Figure 77 SOIC Rev B Page 22 of 28 09507 072 lat ADP7104 PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS Heat dissip
4. CH1 1V Bw 10 8 M4ps A CHA 1 56V CH1 1V 8w 10mV Bw M4ps A CH4 1 56V z 9 8 8 9 896 8 Figure 54 Line Transient Response Cin Cour 1 UF loan 500 mA Figure 57 Line Transient Response Cin Cour 1 UF loan 1 MA Vout 3 3 V Vour 3 3 V URRENT 2138 OUTPUT VOLTAGE 2 GHV 5w CH2 10mV Bw M 4yus A CHA 1 56V 1V Bw CH2 10mV M4us A CH4_ 1 56V 2 9 8 8 9 896 8 Figure 55 Line Transient Response Cour 1 UF liop 500 mA Figure 58 Line Transient Response Cin Cour 1 pF lioap 1 mA Vour 5V Vour 5V Rev B Page 15 of 28 ADP7104 THEORY OF OPERATION The ADP7104 is a low quiescent current low dropout linear regulator that operates from 3 3 V to 20 V and provides up to 500 mA of output current Drawing a low 1 mA of quiescent current typical at full load makes the ADP7104 ideal for battery operated portable equipment Typical shutdown current consumption is 40 uA at room temperature Optimized for use with small 1 uF ceramic capacitors the ADP7104 provides excellent transient performance 09507 055 SHORT CIRCUIT THERMAL PROTECT 1 22V REFERENCE 09507 056 Figure 60 Adjustable Output Voltage Internal Block Diagram Internally the ADP7104 consists of a reference an error amplifier a feedback voltage divider and a PMOS pass transistor Output cur
5. 0 8 0 6 CAPACITANCE pF 0 4 j L Lo LA 0 0 2 4 6 8 1 VOLTAGE V 09507 058 Figure 63 Capacitance vs Voltage Characteristic Use Equation 1 to determine the worst case capacitance accounting for capacitor variation over temperature component tolerance and voltage Czrr Cras x 1 TEMPCO x 1 TOL 1 where Cans is the effective capacitance at the operating voltage TEMPCO is the worst case capacitor temperature coefficient TOL is the worst case component tolerance In this example the worst case temperature coefficient TEMPCO over 40 C to 85 C is assumed to be 1596 for an X5R dielectric The tolerance of the capacitor TOL is assumed to be 1096 and is 0 94 uF at 1 8 V as shown in Figure 63 Substituting these values in Equation 1 yields Crrr 0 94 uF x 1 0 15 x 1 0 1 20 719 uF Therefore the capacitor chosen in this example meets the minimum capacitance requirement of the LDO overtemper ature and tolerance at the chosen output voltage To guarantee the performance of the ADP7104 it is imperative that the effects of dc bias temperature and tolerances on the behavior of the capacitors be evaluated for each application Rev B Page 17 of 28 ADP7104 PROGRAMABLE UNDERVOLTAGE LOCKOUT UVLO The ADP7104 uses the EN UVLO pin to enable and disable the VOUT pin under normal operating conditions As shown in Figure 64 when a rising vo
6. 40 C to 125 C Adjustable Output Voltage Vans 1 21 1 22 1 23 Accuracy lour 10 mA 1 MA lt lour lt 500 mA Vin Vout 1 V to 20 V 1 196 1 232 V Ty 40 C to 125 C LINE REGULATION AVour AVin Vin Vour 1 V to 20V T 40 C to 125 C 0 015 0 015 LOAD REGULATION lour 1 mA to 500 mA 0 2 A lour 1 mA to 500 mA T 40 C to 125 C 0 75 A ADJ INPUT BIAS CURRENT ADJr ias 1 mA lt lout lt 500 mA Vin Vout 1 V to 20V 10 nA ADJ connected to VOUT SENSE INPUT BIAS CURRENT SENSE sias 1 MA lt lour lt 500 mA Vin Vout 1 V to 20 V 1 uA SENSE connected to VOUT Vour 1 5 V DROPOUT VOLTAGE VonoPour lour 10 mA 20 mV lour 10 mA T 40 C to 125 C 40 mV lour 150 mA 100 mV lour 150 mA T 40 C to 125 C 175 mV lour 300 mA 200 mV lour 300 mA T 40 C to 125 C 325 mV lour 500 mA 350 mV lour 500 mA T 40 C to 125 C 550 mV START UP TIME tstarT uP Vout 5V 1000 us CURRENT LIMIT THRESHOLD lur 625 775 1000 mA PG OUTPUT LOGIC LEVEL PG Output Logic High PGuian lou lt 1 pA 1 0 V PG Output Logic Low PGiow lo lt 2 mA 0 4 V PG OUTPUT THRESHOLD Output Voltage Falling PGraL 9 2 96 Output Voltage Rising PGarise 6 5 96 THERMAL SHUTDOWN Thermal Shutdown Threshold TSsp rising 150 Thermal Shutdown Hysteresis TSsp nys 15 C Rev B Page 3 of 28 ADP7104 Parameter Symbol Conditions Min Typ Max Un
7. 500mA 40 C 5 C 25 C T C 85 C 125 C Figure 29 Output Voltage vs Junction Temperature Vour 5 V Adjustable 5 08 5 07 5 06 5 05 10 ILoap mA 100 1000 Figure 30 Output Voltage vs Load Current Vour 5 V Adjustable 5 08 5 07 5 06 5 05 5 04 e 5 5 03 o gt 5 02 5 01 LOAD 100pA 5 00 LOAD 1mA LOAD 10mA 4 99 LOAD 100mA 5 LOAD 300mA LOAD 500mA 4 98 6 8 10 12 14 16 18 20 Vin V Figure 31 Output Voltage vs Input Voltage Vour 5 V Adjustable lour SHUTDOWN CURRENT pA 09507 025 PSRR dB 09507 026 100 ADP7104 LOAD 500mA LOAD 300mA LOAD 10mA LOAD 1mA TEMPERATURE C Voltages on Vour 09507 054 Figure 32 Reverse Input Current vs Temperature Viv 0 V Different 10 100 1k 10k 100k FREQUENCY Hz 1M 10M 09507 028 Figure 33 Power Supply Rejection Ratio vs Frequency Vour 1 8 V Vw 3 3 V PSRR dB 09507 027 20 100 LOAD 500mA LOAD 10mA LOAD imA
8. DO NOT CONNECT TO 1 NC NO CONNECT DO NOT CONNECT TO THIS PIN THIS PIN 2 IT IS HIGHLY RECOMMENDED THAT THE 2 IT IS HIGHLY RECOMMENDED THAT THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE BE CONNECTED TO THE GROUND PLANE ON THE BOARD Figure 3 LFCSP Package Table 5 Pin Function Descriptions EXPOSED PAD ON THE BOTTOM OF THE PACKAGE BE CONNECTED TO THE GROUND PLANE ON THE BOARD 09507 003 09507 004 Figure 4 Narrow Body SOIC Package Pin No Mnemonic Description 1 VOUT Regulated Output Voltage Bypass VOUT to GND with a 1 uF or greater capacitor 2 SENSE ADJ Sense SENSE Measures the actual output voltage at the load and feeds it to the error amplifier Connect SENSE as close as possible to the load to minimize the effect of IR drop between the regulator output and the load This function applies to fixed voltages only Adjust Input ADJ An external resistor divider sets the output voltage This function applies to adjustable voltages only 3 GND Ground 4 NC Do Not Connect to this Pin 5 EN UVLO Enable Input EN Drive EN high to turn on the regulator drive EN low to turn off the regulator For automatic startup connect EN to VIN Programmable Undervoltage Lockout UVLO When the programmable UVLO function is used the upper and lower thresholds are determined by the programming resistors 6 GND Ground 7 PG Power Good This open drain output requires an external pull up resistor to VIN or VOUT If t
9. 50 0 6 8 10 12 14 16 18 20 Vin V 5 lLoAp mA E Figure 17 Output Voltage vs Input Voltage Vour 5 V Figure 20 Dropout Voltage vs Load Current Vour 5 V 1000 5 05 LOAD 100 900 LOAD 1mA LOAD 10mA M LOAD 100mA 800 LOAD 300mA 4 95 700 4 90 LE 600 4 85 r4 500 5 8 5 480 2 400 gt 4 75 2 o T 300 4 70 LOAD 5mA 200 4 65 LOAD 10mA LOAD 100mA LOAD 200mA 100 4 60 LOAD 300mA LOAD 500mA 40 C 5 C 25 C 85 C 125 C E TE 4 9 5 0 5 1 5 2 5 3 54 2 T CC E Vin V E Figure 18 Ground Current vs Junction Temperature Vour 5 V Figure 21 Output Voltage vs Input Voltage in Dropout 700 2500 600 2000 500 1500 i E 400 r1 5 S 1000 o o 300 a 3 2 9 Q 500 200 5 a LOAD 5mA LOAD 10mA 100 0 LOAD 100mA LOAD 200mA LOAD 300mA LOAD 500mA 0 500 5 0 1 1 10 100 1000 2 4 80 4 90 5 00 5 10 5 20 5 30 540 8 lLoap mA 3 Vin V 8 Figure 19 Ground Current vs Load Current Vour 5 V Figure 22 Ground Current vs Input Voltage in Dropout Vour 5 V Rev B Page 9 of 28 ADP7104
10. For automatic startup EN UVLO can be tied to VIN The ADP7104 incorporates reverse current protections circuitry that prevents current flow backwards through the pass element when the output voltage is greater than the input voltage A comparator senses the difference between the input and output voltages When the difference between the input voltage and output voltage exceeds 55 mV the body of the PFET is switched to Vour and turned off or opened In other words the gate is connected to VOUT Rev B Page 16 of 28 APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor The ADP7104 is designed for operation with small space saving ceramic capacitors but functions with most commonly used capacitors as long as care is taken with regard to the effective series resistance ESR value The ESR of the output capacitor affects the stability of the LDO control loop A minimum of 1 uF capacitance with an ESR of 1 Q or less is recommended to ensure the stability of the ADP7104 Transient response to changes in load current is also affected by output capacitance Using a larger value of output capacitance improves the transient response of the ADP7104 to large changes in load current Figure 62 shows the transient responses for an output capacitance value of 1 uF LOAD CURRENT OUTPUT VOLTAGE CH1 500mA Q 50mV M20us A CH1 270mA 10 Figure 62 Output Transient Response Vour
11. The circuit shown in Figure 69 adds two additional components to the output voltage setting resistor divider Cus and Rxr are added in parallel with Res to reduce the ac gain of the error amplifier Ryr is chosen to be equal to Rz this limits the ac gain of the error amplifier to approxi mately 6 dB The actual gain is the parallel combination of Rua and Res divided by Rr This ensures that the error amplifier always operates at greater than unity gain Cyr is chosen by setting the reactance of Cyr equal to Resi at a frequency between 50 Hz and 100 Hz This sets the frequency where the ac gain of the error amplifier is 3 dB down from its dc gain Vin 8V CIN ae ON 100ko 09507 064 Figure 69 Noise Reduction Modification to Adjustable LDO The noise ofthe LDO is approximately the noise of the fixed output LDO typically 15 uV rms times the square root of the parallel combination of Ryr and Res divided by Rr Based on the component values shown in Figure 69 the ADP7104 has the following characteristics e DC gain of 4 09 12 2 dB e 3 dB roll off frequency of 59 Hz e High frequency ac gain of 1 82 5 19 dB e Noise reduction factor of 1 35 2 59 dB e RMS noise of the adjustable LDO without noise reduction of 27 8 uV rms e RMS noise of the adjustable LDO with noise reduc tion assuming 15 uV rms for fixed voltage option of 20 25 uV rms Rev B Page 19 of 28 ADP7104 CURRENT LIMIT AND THER
12. z kJ t 50 tt 50 tc tc o o amp 60 a 60 70 70 80 80 90 90 100 s 100 8 10 100 1 10k 100k 1M 10M 5 10 100 1k 10k 100k 1M 10M FREQUENCY Hz FREQUENCY Hz E Figure 35 Power Supply Rejection Ratio vs Frequency Vour 3 3 V V 4 3 V Figure 38 Power Supply Rejection Ratio vs Frequency Vout 5 V Vn 6 V 0 LOAD 500mA LOAD 500mA LOAD 300mA LOAD 300mA 10 LOAD 100mA 10 LOAD 100mA LOAD 10mA LOAD 10mA 29 LOAD 1mA 29 LOAD 1mA 30 30 a 40 y 40 5 t 50 50 tc tc o o a 60 a 60 70 70 80 80 90 90 100 100 5 10 100 1k 10k 100k 1M 10M 5 10 100 1k 10k 100k 1M 10M FREQUENCY Hz 8 FREQUENCY Hz 8 Figure 36 Power Supply Rejection Ratio vs Frequency Vour 3 3 V Vu 2 3 8 V Figure 39 Power Supply Rejection Ratio vs Frequency Vout 5 V Vw 5 5 V LOAD 500mA LORD S00mA LOAD 300mA LOAD z 300mA 10 LOAD 100mA 10 LOAD 100mA LOAD 1omA LOAD 10mA 2 7 1m 20 7 LOAD 1mA 30 30 o 40 5 40 kJ 5 tt 50 t 50 tc o o a 60 a 60 70 70 80 80 90 90 100 m 100 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M E FREQUENCY Hz 8 FREQUENCY Hz 3 Figure 37 Power Supply Rejection Ratio vs Frequency Vour 5 V Vn 6 5 V Figure 40 Power Supply Rejection Ratio vs Frequency Vout 5 V Vn 5 3 V Rev B Page 12 of 28 PSRR dB Figure 41 Power Supply
13. 0 75 1 00 1 25 1 50 100 0 0 25 09507 039 HEADROOM VOLTAGE V Figure 44 Power Supply Rejection Ratio vs Headroom Voltage 100 Hz Vour 5 V LOAD 500mA LOAD 300mA LOAD 100mA LOAD 10mA LOAD 1mA 0 50 0 75 1 00 HEADROOM VOLTAGE V 09507 040 Figure 45 Power Supply Rejection Ratio vs Headroom Voltage 1 kHz Vour 5 V LOAD 500mA LOAD 300mA LOAD 100mA LOAD 10mA LOAD 1mA 1 00 HEADROOM VOLTAGE V 0 50 0 75 1 25 1 50 09507 041 Figure 46 Power Supply Rejection Ratio vs Headroom Voltage 10 kHz Vour 5V ADP7104 LOAD 500mA LOAD CURRENT LOAD a 1 5 c 1 rd a OUTPUT VOLTAGE CH1 500mA Q Bw 50mV By M20us A CH1_ 270mA 09507 045 0 25 0 50 0 75 1 00 1 25 1 50 3 HEADROOM VOLTAGE V 8 10 Figure 47 Power Supply Rejection Ratio vs Headroom Voltage 100 kHz Figure 50 Load Tran
14. 0mA LOAD 300mA LOAD 500mA 3 6 3 7 Figure 13 Output Voltage vs Input Voltage in Dropout 09507 012 09507 013 Rev B Page 8 of 28 1400 1200 1000 800 600 400 LOAD 5mA LOAD 10mA 200 LOAD 100mA LOAD 200mA LOAD 300mA 0 LOAD 500mA 3 1 3 2 3 3 3 4 Vin V 3 7 Figure 14 Ground Current vs Input Voltage in Dropout 5 05 5 04 5 03 LOAD 100 LOAD 1mA LOAD 10mA LOAD 100mA LOAD 300mA LOAD 500mA 40 C 5 C 25 C Ty C 85 C Figure 15 Output Voltage vs Junction Temperature Vour 5 V 5 05 5 04 5 03 Figure 16 Output Voltage vs Load Current Vour 5 V 10 lLoAp mA 100 1000 09507 014 09507 015 09507 016 ADP7104 LOAD 100pA LOAD 1mA LOAD 10mA LOAD 100mA 250 LOAD 300mA LOAD 500mA 200 z E 5 3 150 n 100
15. 1 8 V Cour 1 uF 09507 057 Input Bypass Capacitor Connecting a 1 uF capacitor from VIN to GND reduces the circuit sensitivity to printed circuit board PCB layout especially when long input traces or high source impedance are encountered If greater than 1 uF of output capacitance is required the input capacitor should be increased to match it Input and Output Capacitor Properties Any good quality ceramic capacitors can be used with the ADP7104 as long as they meet the minimum capacitance and maximum ESR requirements Ceramic capacitors are manufac tured with a variety of dielectrics each with different behavior over temperature and applied voltage Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions XSR or X7R dielectrics with a voltage rating of 6 3 V to 25 V are recommended Y5V and Z5U dielectrics are not recommended due to their poor temperature and dc bias characteristics ADP7104 Figure 63 depicts the capacitance vs voltage bias characteristic of an 0402 1 uF 10 V X5R capacitor The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating In general a capacitor in a larger package or higher voltage rating exhibits better stability The temperature variation of the X5R dielectric is 15 over the 40 C to 85 C temperature range and is not a function of package or voltage rating 1 2
16. 5 8 Lead SOIC_N_EP RD 8 2 ADP7104ARDZ 9 0 R7 40 C to 125 C 9 8 Lead SOIC_N_EP RD 8 2 ADP7104CP EVALZ 3 3 LFCSP Evaluation Board ADP7104RD EVALZ 3 3 SOIC Evaluation Board ADP7104CPZ REDYKIT LFCSP REDYKIT ADP7104RDZ REDYKIT SOIC REDYKIT 1 Z RoHS Compliant Part For additional voltage options contact a local Analog Devices Inc sales or distribution representative 3 The ADP7104CP EVALZ and ADP7104RD EVALZ evaluation boards are preconfigured with a 3 3 V ADP7104 Rev B Page 25 of 28 ADP7104 NOTES Rev B Page 26 of 28 ADP7104 NOTES Rev B Page 27 of 28 ADP7104 NOTES 2011 2012 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D09507 0 3 12 B DEVICES www analo g com Rev B Page 28 of 28
17. A 100 1000 3 33 LOAD 300mA 09507 006 Figure 8 Ground Current vs Junction Temperature GROUND CURRENT pA 0 1 1 10 100 1000 lLoAp mA Figure 9 Ground Current vs Load Current 1200 LOAD 100pA LOAD 1mA LOAD 10mA 1000 LOAD 100mA LOAD 300mA LOAD 500mA LOAD 500mA a 800 3 31 a E 600 5 3 gt a 3 29 2 400 tc 6 E 200 0 id 4 6 8 10 12 14 16 18 20 Figure 7 Output Voltage vs Input Voltage Vin V 09507 007 Vin V Figure 10 Ground Current vs Input Voltage Rev B Page 7 of 28 09507 009 09507 010 ADP7104 SHUTDOWN CURRENT pA 160 140 120 100 80 60 40 20 0 50 25 50 TEMPERATURE C 09507 011 GROUND CURRENT pA Figure 11 Shutdown Current vs Temperature at Various Input Voltages DROPOUT mV Vout V 350 300 Vout 3 3V Ta 25 C 250 200 150 100 50 ILoap mA 1000 Figure 12 Dropout Voltage vs Load Current d 32 3 4 Vin V LOAD 5mA LOAD 10mA LOAD 100mA LOAD 20
18. ANALOG DEVICES 20 V 500 mA Low Noise CMOS LDO ADP7104 FEATURES TYPICAL APPLICATION CIRCUITS Input voltage range 3 3 V to 20V Maximum output current 500 mA TuF Low noise 15 pV rms for fixed output versions i PSRR performance of 60 dB at 10 kHz Vou 3 3 V ON a4ooko Reverse current protection Low dropout voltage 350 mV at 500 mA Initial accuracy 0 8 Accuracy over line load and temperature 2 1 Low quiescent current Vin 5 V 900 pA with 500 mA load Low shutdown current 40 pA at Vin 12 V stable with small 1 pF ceramic output capacitor 7 fixed output voltage options 1 5 V 1 8 V 2 5 V 3V 3 3 V 5V and9V Adjustable output from 1 22 V to Vin Voo Foldback current limit and thermal overload protection User programmable precision UVLO enable Power good indicator 8 lead LFCSP and 8 lead SOIC packages APPLICATIONS Regulation to noise sensitive applications ADC DAC circuits precision amplifiers high frequency oscillators clocks and PLLs Communications and infrastructure Medical and healthcare Industrial and instrumentation Vin 8V Vour 5V CIN 1 09507 001 09507 002 Figure 2 ADP7104 with Adjustable Output Voltage 5 V GENERAL DESCRIPTION The ADP7104 is a CMOS low dropout linear regulator that The ADP7104 output noise voltage is 15 uV rms and is inde operates from 3 3 V to 20 V and provides up to 500 mA of pendent of the output voltage A digital
19. B Based on an end point calculation using 1 mA and 300 mA loads See Figure 6 for typical load regulation performance for loads less than 1 mA Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage This applies only for output voltages above 3 0 V 3 Start up time is defined as the time between the rising edge of EN to VOUT being at 90 of its nominal value 4 Current limit threshold is defined as the current at which the output voltage drops to 90 of the specified typical value For example the current limit for a 5 0 V output voltage is defined as the current that causes the output voltage to drop to 9096 of 5 0 V or 4 5 V INPUT AND OUTPUT CAPACITOR RECOMMENDED SPECIFICATIONS Table 2 Parameter Symbol Conditions Min Typ Max Unit Minimum Input and Output Capacitance Cmn Ta 40 C to 125 C 0 7 UF Capacitor ESR Resa Ta 40 C to 125 C 0 001 0 2 The minimum input and output capacitance should be greater than 0 7 pF over the full range of operating conditions The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met X7R and X5R type capacitors are recommended Y5V and Z5U capacitors are not recommended for use with any LDO Rev B Page 4 of 28 ABSOLUTE MAXIMUM RATINGS Table 3 Parameter Rati
20. MAL OVERLOAD PROTECTION The ADP7104 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits The ADP7104 is designed to current limit when the output load reaches 600 mA typical When the output load exceeds 600 mA the output voltage is reduced to maintain a constant current limit Thermal overload protection is included which limits the junction temperature to a maximum of 150 C typical Under extreme conditions that is high ambient temperature and or high power dissipation when the junction temperature starts to rise above 150 C the output is turned off reducing the output current to zero When the junction temperature drops below 135 C the output is turned on again and output current is restored to its operating value Consider the case where a hard short from VOUT to ground occurs At first the ADP7104 current limits so that only 600 mA is conducted into the short If self heating of the junction is great enough to cause its temperature to rise above 150 C thermal shutdown activates turning off the output and reducing the output current to zero As the junction temperature cools and drops below 135 C the output turns on and conducts 600 mA into the short again causing the junction temperature to rise above 150 C This thermal oscillation between 135 C and 150 C causes a current oscillation between 600 mA and 0 mA that continues as long as the short remai
21. PROPER CONNECTION OF THE EXPOSED PAD REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET COMPLIANT TO JEDEC STANDARDS MS 012 AA Figure 81 8 Lead Standard Small Outline Package with Exposed Pad SOIC_N_EP Narrow Body RD 8 2 Dimensions shown in millimeters Rev B Page 24 of 28 06 03 2011 B ADP7104 ORDERING GUIDE Temperature Output Package Package Model Range Voltage 2 3 Description Option Branding ADP7104ACPZ R7 40 C to 125 C Adjustable 8 Lead LFCSP_WD CP 8 5 LH1 ADP7104ACPZ 1 5 R7 40 C to 125 C 1 5 8 Lead LFCSP_WD CP 8 5 LK6 ADP7104ACPZ 1 8 R7 40 C to 125 C 1 8 8 Lead LFCSP_WD CP 8 5 LK7 ADP7104ACPZ 2 5 R7 40 C to 125 C 2 5 8 Lead LFCSP_WD CP 8 5 LKJ ADP7104ACPZ 3 0 R7 40 C to 125 C 3 0 8 Lead LFCSP_WD CP 8 5 LKK ADP7104ACPZ 3 3 R7 40 C to 125 C 3 3 8 Lead LFCSP_WD CP 8 5 LKL ADP7104ACPZ 5 0 R7 40 C to 125 C 5 8 Lead LFCSP_WD CP 8 5 LKM ADP7104ACPZ 9 0 R7 40 C to 125 C 9 8 Lead LFCSP_WD CP 8 5 LLD ADP7104ARDZ R7 40 C to 125 C Adjustable 8 Lead SOIC_N_EP RD 8 2 ADP7104ARDZ 1 5 R7 40 C to 125 C 1 5 8 Lead SOIC_N_EP RD 8 2 ADP7104ARDZ 1 8 R7 40 C to 125 C 1 8 8 Lead SOIC_N_EP RD 8 2 ADP7104ARDZ 2 5 R7 40 C to 125 C 2 5 8 Lead SOIC_N_EP RD 8 2 ADP7104ARDZ 3 0 R7 40 C to 125 C 3 0 8 Lead SOIC_N_EP RD 8 2 ADP7104ARDZ 3 3 R7 40 C to 125 C 3 3 8 Lead SOIC_N_EP RD 8 2 ADP7104ARDZ 5 0 R7 40 C to 125 C
22. Rejection Ratio vs Frequency Vour 5 V Vm 5 2 V PSRR dB Figure 42 Power Supply Rejection Ratio vs Frequency Vout 5 V Vn 6 V PSRR dB Figure 43 Power Supply Rejection Ratio vs Frequency Vout 5 V Vin 6 V 0 10 20 30 40 50 60 70 780 LOAD 500mA LOAD 300mA 90 LOAD 100mA LOAD 10mA 4100 LE LOAD imA 10 100 1k 10k 100k 1M FREQUENCY Hz 10 100 LOAD 500mA LOAD imA 10M 100 1k 10k 100k FREQUENCY Hz Adjustable LOAD 500mA LOAD 300mA LOAD 100mA LOAD 10mA LOAD 1mA 10 100 1k 10k 100k 1M FREQUENCY Hz Adjustable With Noise Reduction Circuit 10M PSRR dB 09507 036 PSRR dB 09507 037 PSRR dB 09507 038 Rev B Page 13 of 28 ADP7104 0 LOAD 500mA LOAD 300mA 10 LOAD 100mA LOAD 10mA 20 LOAD imA 30 40 50 60 70 80 90 100 0 0 25 0 50
23. ation from the package can be improved by increasing the amount of copper attached to the pins of the ADP7104 However as listed in Table 6 a point of diminishing returns is eventually reached beyond which an increase in the copper size does not yield significant heat dissipation benefits Place the input capacitor as close as possible to the VIN and GND pins Place the output capacitor as close as possible to the VOUT and GND pins Use of 0805 or 0603 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited 09507 074 Figure 79 Example SOIC PCB Layout 09507 073 Figure 78 Example LFCSP PCB Layout Rev B Page 23 of 28 ADP7104 OUTLINE DIMENSIONS 0 80 MAX 0 55 NOM 0 70 0 05 MAX Ganna 0 02 NOM F COPLANARITY SEATING E 0 08 PLANE 930 0 50 BSC 0 20 REF 0 25 18 COMPLIANT TO JEDEC STANDARDS MO 229 WEED 4 PI TOP VIEW BOTTOM VIEW INDICATOR FOR PROPER CONNECTION OF THE EXPOSED PAD REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET 112008 A Figure 80 8 Lead Lead Frame Chip Scale Package LFCSP_WD 3mm x 3 mm Body Very Very Thin Dual Lead CP 8 5 Dimensions shown in millimeters 3 098 0 356 8 COPLANARITY 0 10 FOR
24. e PCB to ensure that the junction temperature does not rise above 125 C Figure 70 to Figure 77 show junction temperature calculations for different ambient temperatures power dissipation and areas of PCB copper Rev B Page 20 of 28 JUNCTION TEMPERATURE C JUNCTION TEMPERATURE C JUNCTION TEMPERATURE C 145 135 125 115 105 95 85 75 65 55 45 6400mm 500mm 35 25 0 02 0 4 06 08 1 0 12 1 4 1 6 1 8 TOTAL POWER DISSIPATION W Figure 70 LFCSP Ta 25 C 140 25mm TJ MAX 20 22 24 130 120 110 100 0 02 04 06 08 1 0 1 2 1 TOTAL POWER DISSIPATION W Figure 71 LFCSP Ta 50 C 145 135 125 115 6400mm2 500mm 25mm TJ MAX 4 1 6 1 8 105 95 85 6400mm 75 65 0 01 02 03 04 05 06 07 TOTAL POWER DISSIPATION W Figure 72 LFCSP Ta 85 C 500mm 25mm TJ MAX 08 09 1 0 JUNCTION TEMPERATURE C 09507 065 JUNCTION TEMPERATURE C 09507 066 JUNCTION TEMPERATURE C 09507 067 Rev B Page 21 of 28 145 135 125 115 105 95 85 75 65 55 45 35 25 ADP7104 6400mm 500mm 25mm Tj MAX 0 0 2 0 4 0 6 08 1 0 12 1 4 16 1 8 20 2 2 24 TOTAL POWER DISSIPATION W
25. e device Pp and the junction to ambient thermal resistance of the package Oja Maximum junction temperature T is calculated from the ambient temperature T4 and power dissipation Pp using the formula T Ta Pp x Junction to ambient thermal resistance Oja of the package is based on modeling and calculation using a 4 layer board The junction to ambient thermal resistance is highly dependent on the application and board layout In applications where high maximum power dissipation exists close attention to thermal ADP7104 board design is required The value of 0j4 may vary depending on PCB material layout and environmental conditions The specified values of Oja are based on a 4 layer 4 in x 3 in circuit board See JESD51 7 and JESD51 9 for detailed information on the board construction For additional information see the AN 617 Application Note MicroCSP Wafer Level Chip Scale Package available at www analog com Y is the junction to board thermal characterization parameter with units of C W The packages js is based on modeling and calculation using a 4 layer board The JESD51 12 Guidelines for Reporting and Using Electronic Package Thermal Information states that thermal characterization parameters are not the same as thermal resistances Y measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance Ow Therefore Vs thermal paths include co
26. he part is in shutdown current limit thermal shutdown or falls below 9096 of the nominal output voltage PG immediately transitions low If the power good function is not used the pin may be left open or connected to ground 8 VIN Regulator Input Supply Bypass VIN to GND with a 1 pF or greater capacitor EPAD Exposed Pad Exposed paddle on the bottom of the package The EPAD enhances thermal performance and is electrically connected to GND inside the package It is highly recommended that the EPAD be connected to the ground plane on the board Rev B Page 6 of 28 ADP7104 TYPICAL PERFORMANCE CHARACTERISTICS Vin 7 5 V Vovr 5 V Iour 10 mA Cin Cour 1 pF Ta 25 C unless otherwise noted 3 35 1200 LOAD 100 LOAD 100 LOAD 1mA LOAD 1mA LOAD 10mA LOAD 10mA LOAD 100mA 1000 LOAD 100mA 3 33 LOAD 300mA LOAD 300mA LOAD 500mA z LOAD 500mA a E 800 EU E 600 3 3 3 29 2 2 O 400 tc o 3 27 200 3 25 0 40 C 5 C 25 C 85 C 125 C 8 40 C 5 C 25 C 85 C 125 C 8 T C 3 Ty C E Figure 5 Output Voltage vs Junction Temperature 3 35 3 33 3 31 Vout V 3 29 3 27 3 25 0 1 1 Figure 6 Output Voltage vs Load Current ur LOAD 100 LOAD 1mA LOAD 10mA LOAD 100mA 10 lLoAp m
27. ion in the power device and thermal resistances between the junction and ambient air Oja The Oja number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package GND pins to the PCB Table 6 shows typical Oja values of the 8 lead SOIC and 8 lead LFCSP packages for various PCB copper sizes Table 7 shows the typical Vs values of the 8 lead SOIC and 8 lead LFCSP Table 6 Typical 0 4 Values Osa C W Copper Size mm LFCSP SOIC 25 165 1 167 8 100 125 8 111 500 68 1 65 9 1000 56 4 56 1 6400 42 1 45 8 Device soldered to minimum size pin traces Table 7 Typical Y js Values Model UV C W LFCSP 15 1 SOIC 31 3 The junction temperature of the ADP7104 is calculated from the following equation T Ta Pp x Oya 2 where Ta is the ambient temperature Pp is the power dissipation in the die given by Pp Viv Vour x Troan Vin x Ienp 3 where Toa is the load current Icwp is the ground current Vin and Vour are input and output voltages respectively Power dissipation due to ground current is quite small and can be ignored Therefore the junction temperature equation simplifies to the following T Ta Viw Vour x Troan x Oya 4 As shown in Equation 4 for a given ambient temperature input to output voltage differential and continuous load current there exists a minimum copper size requirement for th
28. is prevents on off oscillations that can occur due to noise on the EN pin as it passes through the threshold points The ADP7104 uses an internal soft start to limit the inrush current when the output is enabled The start up time for the 3 3 V option is approximately 580 us from the time the EN active threshold is crossed to when the output reaches 90 of its final value As shown in Figure 66 the start up time is dependent on the output voltage setting Vout V ENABLE 0 500 1000 1500 2000 TIME ps 09507 061 Figure 66 Typical Start Up Behavior Rev B Page 18 of 28 POWER GOOD FEATURE The ADP7104 provides a power good pin PG to indicate the status of the output This open drain output requires an external pull up resistor to VIN If the part is in shutdown mode current limit mode or thermal shutdown or if it falls below 90 of the nominal output voltage the power good pin PG immediately transitions low During soft start the rising threshold of the power good signal is 93 5 of the nominal output voltage The open drain output is held low when the ADP7104 has suffi cient input voltage to turn on the internal PG transistor The PG transistor is terminated via a pull up resistor to VOUT or VIN Power good accuracy is 93 5 of the nominal regulator output voltage when this voltage is rising with a 90 trip point when this voltage is falling Regulator input voltage brownouts or glitche
29. it PROGRAMMABLE EN UVLO UVLO Threshold Rising UVLOnrise 3 3V lt Vn lt 20V T 40 C to 125 C 1 18 1 23 1 28 V UVLO Threshold Falling UVLOraL 3 3V Vw lt 20V T 40 C to 125 C 10 in 1 13 V series with the enable pin UVLO Hysteresis Current UVLOnys Ven gt 1 25 V T 40 C to 125 C 7 5 9 8 12 uA Enable Pull Down Current EN V 500 nA Start Threshold Vstart T 2 40 C to 125 C 3 2 V Shutdown Threshold VsHUTDOWN Ti 40 C to 125 C 2 45 V Hysteresis 250 mV OUTPUT NOISE OUTnoise 10 Hz to 100 kHz Vin 5 5 V Vout 1 8 V 15 rms 10 Hz to 100 kHz Vin 6 3 V Vout 3 3 V 15 rms 10 Hz to 100 kHz Vin 8 V Vour 5V 15 rms 10 Hz to 100 kHz Vin 12 V Vor 9V 15 rms 10 Hz to 100 kHz Vin 5 5 V Vout 1 5 V 18 rms adjustable mode 10 Hz to 100 kHz Vin 12 V Vout 5 V 30 rms adjustable mode 10 Hz to 100 kHz Vin 20 V Vour 15 V 65 rms adjustable mode POWER SUPPLY REJECTION RATIO PSRR 100 kHz Vin 4 3 V Vout 3 3 V 50 dB 100 kHz Vw 6 V Vout 5V 50 dB 10 kHz Vin 4 3 V Vout 3 3 V 60 dB 10 kHz Vu 6 V Vour 5V 60 dB 100 kHz Vin 3 3 V Vout 1 8V adjustable mode 50 dB 100 kHz Vin 6 V Vout 5 V adjustable mode 60 dB 100 kHz Vin 16 V Vout 15 V adjustable mode 60 dB 10 kHz Vin 3 3 V Vout 1 8 V adjustable mode 60 dB 10 kHz Vin 6 V Vout 5 V adjustable mode 80 dB 10 kHz Vin 16 V Vout 15 V adjustable mode 80 d
30. ltage on EN crosses the upper threshold VOUT turns on When a falling voltage on EN UVLO crosses the lower threshold VOUT turns off The hysteresis of the EN UVLO threshold is determined by the Thevenin equivalent resistance in series with the EN UVLO pin 2 0 1 8 1 6 1 4 1 2 Vout EN RISE 1 0 Vout EN FALL 0 8 0 6 0 4 0 2 09507 060 0 1 00 1 25 1 50 1 75 200 225 250 2 75 3 00 Figure 64 Typical VOUT Response to EN Pin Operation The upper and lower thresholds are user programmable and can be set using two resistors When the EN UVLO pin voltage is below 1 22 V the LDO is disabled When the EN UVLO pin voltage transitions above 1 22 V the LDO is enabled and 10 uA hysteresis current is sourced out the pin raising the voltage thus providing threshold hysteresis Typically two external resistors program the minimum operational voltage for the LDO The resistance values R1 and R2 can be determined from R1 Vuys 10 pA R2 1 22 V x RI Vm 1 22 V where Vw is the desired turn on voltage Vuys is the desired EN UVLO hysteresis level Hysteresis can also be achieved by connecting a resistor in series with EN UVLO pin For the example shown in Figure 65 the enable threshold is 2 44 V with a hysteresis of 1 V Vour 5V 09507 059 Figure 65 Typical EN Pin Voltage Divider Figure 64 shows the typical hysteresis of the EN UVLO pin Th
31. nalog Devices Tel 781 329 4700 www analog com Trademarks and registered trademarks are the property of their respective owners Fax 781 461 3113 2011 2012 Analog Devices Inc All rights reserved ADP7104 TABLE OF CONTENTS Features oo V ALLE ac 1 Applications cunei o oe 1 Typical Application Circuits sse 1 General D sciipti ons iirin eiir 1 2 SPECI CALI ONS 3 Input and Output Capacitor Recommended Specifications 4 Absolute Maximum Ratings seen 5 Thermal Data i seen on e E N EEEE EEEE 5 Thermal Resistance eee tentent 5 ESD Catron cioe 5 Pin Configurations and Function Descriptions 6 REVISION HISTORY 3 12 Rev A to Rev B Changes to Figure 66 sssseeeseeeeeneentetentenntententnntenns 18 11 11 Rev 0 to Rev A Changed Low Dropout Voltage from 200 mV to 350 mV 1 Changes to Dropout Voltage 3 10 11 Revision 0 Initial Version Typical Performance Characteristics see 7 Th ory ot Operationz c utes oie eB tibt 16 Applications Information eeeeeeeeeeeeteenteennntns 17 Capacitor Selection me etsi ehh 17 Programable Undervoltage Lockout UVLO 18 Power Good Feature esse
32. ng VIN to GND 0 3 V to 22 V VOUT to GND 0 3 V to 20 V EN UVLO to GND 0 3 V to VIN PG to GND 0 3 V to VIN SENSE ADJ to GND 0 3 V to VOUT Storage Temperature Range 65 C to 150 C Operating Junction Temperature Range 40 C to 125 C Operating Ambient Temperature Range 40 C to 85 C Soldering Conditions JEDEC J STD 020 Stresses above those listed under absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL DATA Absolute maximum ratings apply individually only not in combination The ADP7104 can be damaged when the junction temperature limit is exceeded Monitoring ambient temperature does not guarantee that T is within the specified temperature limits In applications with high power dissipation and poor thermal resistance the maximum ambient temperature may have to be derated In applications with moderate power dissipation and low PCB thermal resistance the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits The junction temperature Tj of the device is dependent on the ambient temperature the power dissipation of th
33. ns at the output Current and thermal limit protections are intended to protect the device against accidental overload conditions For reliable operation device power dissipation must be externally limited so the junction temperature does not exceed 125 C THERMAL CONSIDERATIONS In applications with low input to output voltage differential the ADP7104 does not dissipate much heat However in applications with high ambient temperature and or high input voltage the heat dissipated in the package may become large enough that it causes the junction temperature of the die to exceed the maximum junction temperature of 125 C When the junction temperature exceeds 150 C the converter enters thermal shutdown It recovers only after the junction temperature has decreased below 135 C to prevent any permanent damage Therefore thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions The junction temperature of the die is the sum of the ambient temperature of the environment and the tempera ture rise of the package due to the power dissipation as shown in Equation 2 To guarantee reliable operation the junction temperature of the ADP7104 must not exceed 125 C To ensure that the junction temperature stays below this maximum value the user must be aware of the parameters that contribute to junction temperature changes These parameters include ambient temperature power dissipat
34. nt 19 Noise Reduction of the Adjustable 71 4 19 Current Limit and Thermal Overload Protection 20 Thermal Considerations sente 20 Printed Circuit Board Layout Considerations 23 Outline Dimensions eene 24 Ordering Guide eerte 25 Rev B Page 2 of 28 SPECIFICATIONS Vix Vour 1 V or 3 3 V whichever is greater EN Vin Iovr 10 mA Cin Cour 1 uF Ta 25 C unless otherwise noted ADP7104 Table 1 Parameter Symbol Conditions Min Typ Max Unit INPUT VOLTAGE RANGE Vin 3 3 20 V OPERATING SUPPLY CURRENT lanp lout 100 pA Vn 10 V 400 uA lout 100 pA Vin 10 V Ty 40 C to 125 C 900 pA lour 10 mA Vn 10V 450 uA lout 10 mA Vin 10V T 40 C to 125 C 1050 uA lour 300 mA Vu 10V 750 HA lout 300 mA Vin 10V T 40 C to 125 C 1400 uA lout 500 mA Vin 10V 900 uA lout 500 mA Vin 10V T 40 C to 125 C 1600 yA SHUTDOWN CURRENT lenp sp EN GND Vn 12V 40 50 pA EN GND Vin 12V T 40 C to 125 C 75 yA INPUT REVERSE CURRENT InEv INPUT EN GND Vin OV Vout 20V 0 3 uA EN GND Vin OV Vout 20 V T 40 C to 5 uA 125 C OUTPUT VOLTAGE ACCURACY Fixed Output Voltage Accuracy Vout lour 10 MA 0 8 0 8 1 MA lt lour lt 500 mA Vin Vout 1 V to 20 V 2 1 Ty
35. nvection from the top of the package as well as radiation from the package factors that make Ys more useful in real world applications Maximum junction temperature T is calculated from the board temperature Ts and power dissipation Pp using the formula T Pp x Vg See JESD51 8 and JESD51 12 for more detailed information about Vg THERMAL RESISTANCE Oya and Ys are specified for the worst case conditions that is a device soldered in a circuit board for surface mount packages yc is a parameter for surface mount packages with top mounted heatsinks 6c is presented here for reference only Table 4 Thermal Resistance Package Type Osa Wp Unit 8 Lead LFCSP 40 1 27 1 17 2 C W 8 Lead SOIC 48 5 58 4 31 3 C W ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev B Page 5 of 28 ADP7104 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 8 VIN D VOUT 1 vais 8 VIN n M 7 PG SENSE ADJ 2 ADP7104 7 pa TOP VIEW Not to Scale 6 GND GND 3 Not to Scale 9 GND C15 EN UVLO NC 4 5 EN UVLO NOTES NOTES 1 NC NO CONNECT
36. power good output output current This high input voltage LDO is ideal for allows power system monitors to check the health of the output regulation of high performance analog and mixed signal voltage A user programmable precision undervoltage lockout circuits operating from 19 V to 1 22 V rails Using an function facilitates sequencing of multiple power supplies advanced proprietary architecture it provides high power The ADP7104 is available in 8 lead 3 mm x 3 mm LECSP supply rejection low noise and achieves excellent line and and 8 lead SOIC packages The LFCSP offers a very compact load transient response with just a small 1 uF ceramic solution and also provides excellent thermal performance for output capacitor applications requiring up to 500 mA of output current in a The ADP7104 is available in seven fixed output voltage options small low profile footprint and an adjustable version which allows output voltages that range from 1 22 V to Vix Voo via an external feedback divider Rev B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result fromits use Specifications subject to change without notice No One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A license is granted by implication or otherwise under any patent or patent rights of A
37. rent is delivered via the PMOS pass device which is controlled by the error amplifier The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference If the feedback voltage is lower than the reference voltage the gate of the PMOS device is pulled lower allowing more current to pass and increasing the output voltage If the feedback voltage is higher than the reference voltage the gate of the PMOS device is pulled higher allowing less current to pass and decreasing the output voltage The ADP7104 is available in seven fixed output voltage options ranging from 1 5 V to 9 V and in an adjustable version with an output voltage that can be set to between 1 22 V and 19 V by an external voltage divider The output voltage can be set according to the following equation Vour 1 22 V 1 R1 R2 09507 075 Figure 61 Typical Adjustable Output Voltage Application Schematic The value of R2 should be less than 200 to minimize errors in the output voltage caused by the ADJ pin input current For example when R1 and R2 each equal 200 kQ the output voltage is 2 44 V The output voltage error introduced by the ADJ pin input current is 2 mV or 0 08 assuming a typical ADJ pin input current of 10 nA at 25 C The ADP7104 uses the EN UVLO pin to enable and disable the VOUT pin under normal operating conditions When EN UVLO is high VOUT turns on when EN is low VOUT turns off
38. s trigger power no good signals if Vour falls below 90 A normal power down causes the power good signal to go low when Vour drops below 90 Figure 67 and Figure 68 show the typical power good rising and falling threshold over temperature PG 40 C PG 5 C PG 25 C PG 85 C PG 125 C PG V 0 4 2 4 9 4 4 4 5 4 6 4 7 48 4 9 5 0 Vout V 09507 062 Figure 67 Typical Power Good Threshold vs Temperature Vour Rising 5 PG 85 C PG 125 C PG V 42 43 44 45 46 47 48 49 50 Vout V Figure 68 Typical Power Good Threshold vs Temperature Vour Falling 09507 063 ADP7104 NOISE REDUCTION OF THE ADJUSTABLE ADP7104 The ultralow output noise of the fixed output ADP7104 is achieved by keeping the LDO error amplifier in unity gain and setting the reference voltage equal to the output voltage This architecture does not work for an adjustable output voltage LDO The adjustable output ADP7104 uses the more conventional architecture where the reference voltage is fixed and the error amplifier gain is a function of the output voltage The disadvantage of the conventional LDO architecture is that the output voltage noise is proportional to the output voltage The adjustable LDO circuit may be modified slightly to reduce the output voltage noise to levels close to that of the fixed output ADP7104
39. sient Response C Cour 1 UF loan 1 mA to 500 mA Vour 5V Vour 1 8 V Vn 5V 30 LOAD CURRENT 25 20 o E gt 15 ul 5 OUTPUT VOLTAGE 40 3 3 5 1 8V 5V 1 5 5Vapy NR 0 2 3 0 00001 0 0001 0 001 0 01 0 1 1 3 500mA Bw CH2 50 5 M20us A CH1 280mA LOAD CURRENT A 8 10 2 2 Figure 48 Output Noise vs Load Current and Output Voltage Figure 51 Load Transient Response Cour 1 UF loan 1 mA to 500 mA Cour 1 uF Vour 3 3 V Vw 5V 10 3 3 5V LOAD CURRENT 5VapJ 5Vapy NR 1 zc N x 5 a D o UTPUT VOLTAGE z 2 0 1 0 01 3 10 100 1k 10k 100k 500mA Q Bw CH2 50mV Bw M20us A CH1 300mA z FREQUENCY Hz 8 10 2 8 Figure 49 Output Noise Spectral Density lLoan 10 MA Cour 1 UF Figure 52 Load Transient Response Cw Cour 1 UF loan 1 mA to 500 mA Vour 5V Vin 7V Rev B Page 14 of 28 ADP7104 LOAD CURRENT OAD CURRENT 2 l OUTPUT VOLTA CH1 1V Bw 10mV Bw M4ys A 4 1 56V i CH1 1V By i mV w 4 6 A CHA 1 56V 2 9 8 8 9 8 8 Figure 53 Line Transient Response Cin Cour 1 UF loan 500 mA Figure 56 Line Transient Response Cin Cour 1 UF loan 1 mA Vour 1 8V Vour 1 8V LOAD CURRENT LOAD CURRENT 2 OUTPUT VOLTA OUTPUT VOLTAGE

ANALOG DEVICES ADP7104 handbook Rev B

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