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MICROCHIP - PIC18FXX2 Data Sheet

1. TABLE 4 2 REGISTER FILE SUMMARY File Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito Sok ton ae TOSU Top of Stack upper Byte TOS lt 20 16 gt 0 0000 37 TOSH Top of Stack High Byte TOS lt 15 8 gt 0000 0000 37 TOSL Top of Stack Low Byte TOS lt 7 0 gt 0000 0000 37 STKPTR STKFUL STKUNF Return Stack Pointer 00 0 0000 38 PCLATU Holding Register for PC lt 20 16 gt 0 0000 39 PCLATH Holding Register for PC lt 15 8 gt 0000 0000 39 PCL PC Low Byte PC lt 7 0 gt 0000 0000 39 TBLPTRU bit21 Program Memory Table Pointer Upper Byte TBLPTR lt 20 16 gt 00 0000 58 TBLPTRH Memory Table Pointer High Byte TBLPTR lt 15 8 gt 0000 0000 58 TBLPTRL Memory Table Pointer Low Byte TBLPTR lt 7 0 gt 0000 0000 58 TABLAT Program Memory Table Latch 0000 0000 58 PRODH Product Register High Byte XXXX 71 PRODL Product Register Low Byte XXXX XXXX 71 INTCON GIE GIEH RBIF 0000 000x 75 INTCON2 RBPU INTEDGO INTEDG1 INTEDG2 TMROIP RBIP 1111 1 1 76 INTCON3 INT2IP INT1IP INT2IE INT1IE INT2IF INT1lF 11 0 0 00 77 INDFO Uses contents of FSRO to address data memory value of FSRO not changed not a physical register n a 50 POSTINCO Uses contents of FSRO to address data memory value of FSRO post incremented not a physical register n a 50 POSTDECO Uses contents of FSRO to address d
2. Desired Baud Rate Fosc 64 X 1 Solving for X X Fosc Desired Baud Rate 64 1 X 16000000 9600 64 1 X 25 042 25 Calculated Baud Rate 16000000 64 25 1 9615 Error Calculated Baud Rate Desired Baud Rate Desired Baud Rate 9615 9600 9600 0 16 TABLE 16 1 BAUD RATE FORMULA SYNC BRGH 0 Low Speed BRGH 1 High Speed 0 Asynchronous Baud Rate Fosc 64 X 1 Baud Rate Fosc 16 X 1 1 Synchronous Baud Rate Fosc 4 X 1 N A Legend X value in SPBRG 0 to 255 TABLE 16 2 REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value on Name Bit7 Bit6 Bit5 Bit4 Bit2 Bitl Bito All Other 4 RESETS TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 0000 010 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 00x SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend unknown unimplemented read as 0 Shaded cells are not used by DS39564C page 168 2006 Microchip Technology Inc PIC18FXX2 TABLE 16 3 BAUD RATES FOR SYNCHRONOUS MODE Baup 1056 40 2 SpBRG 33 MHz SPBRG 25 MHz SPBRG 20 MHz SPBRG RATE value value value value Kbps KBAUD ERROR ERROR decimal KBAUD ERROR decimal ERROR decimal 0 3 N
3. RLCF Rotate Left f through Carry Syntax label f d a Operands 0 lt 1 lt 255 d e 0 1 a e 0 1 Operation f lt n gt gt dest lt n 1 gt f lt 7 gt gt dest lt 0 gt Status Affected C N Z Encoding 0011 01 Description The contents of register are rotated one bit to the left through the Carry Flag If d is 0 the result is placed in W If is 1 the result is stored back in register f default If a is 0 the Access Bank will be selected overriding the BSR value If a 2 1 then the bank will be selected as per the BSR value default C register f Words 1 Cycles 1 G Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example RLCF REG 0 0 Before Instruction REG 1110 0110 C 0 After Instruction REG 1110 0110 W 1100 1100 C gt d 2006 Microchip Technology Inc DS3 9564C page 243 PIC18FXX2 RLNCF Rotate Left f no carry Syntax label RLNCF Operands 0 lt 1 lt 255 d e 0 1 0 1 Operation f lt n gt gt dest lt n 1 gt f lt 7 gt gt dest lt 0 gt Status Affected N Z Encoding 0100 olda ffff Description The contents of register are rotated one bit to the left If d is 0 the result is placed in W If d is 1 the result is
4. 2006 Microchip Technology Inc DS39564C page 125 PIC18FXX2 15 3 1 REGISTERS The MSSP module has four registers for SPI mode operation These are e MSSP Control Register SSPCON1 MSSP Status Register SSPSTAT Serial Receive Transmit Buffer SSPBUF MSSP Shift Register SSPSR Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation The SSPCON1 regis ter is readable and writable The lower 6 bits of the SSPSTAT are read only The upper two bits of the SSPSTAT are read write SSPSR is the shift register used for shifting data in or out SSPBUF is the buffer register to which data bytes are written to or read from In receive operations SSPSR and SSPBUF together create a double buffered receiver When SSPSR receives a complete byte it is transferred to SSPBUF and the SSPIF interrupt is set During transmission the SSPBUF is not double buff ered A write to SSPBUF will write to both SSPBUF and SSPSR REGISTER 15 1 55 5 MSSP STATUS REGISTER SPI MODE R W 0 R W 0 R 0 R 0 R 0 R 0 R 0 R 0 SMP CKE D A P 5 R W UA BF bit 7 bit O bit 7 SMP Sample bit SPI Master mode 1 Input data sampled at end of data output time 0 Input data sampled at middle of data output time SPI Slave mode SMP must be cleared when SPI is used in Slave mode bit 6 CKE SPI Clock Edge Select When CKP 0 1 Data
5. TABLE 9 10 SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Val g n Value on Name Bit7 Bit 6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO POR BOR Other 2 5 5 PORTE RE2 RE1 REO 000 000 LATE LATE Data Output Register uuu TRISE IBF OBF IBOV PSPMODE PORTE Data Direction bits 0000 111 0000 111 ADCON1 ADFM ADCS2 PCFG3 PCFG2 PCFG1 PCFGO 00 0000 00 0000 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used by PORTE nl 2006 Microchip Technology Inc DS39564C page 99 PIC18FXX2 9 6 Parallel Slave Port The Parallel Slave Port is implemented on the 40 pin devices only PIC18F4X2 PORTD operates as an 8 bit wide Parallel Slave Port or microprocessor port when control bit PSPMODE TRISE lt 4 gt is set It is asynchronously readable and writable by the external world through RD control input pin REO RD and WR control input pin RE1 WR It can directly interface to an 8 bit microprocessor data bus The external microprocessor can read or write the PORTD latch as an 8 bit latch Setting bit PSPMODE enables port pin REO RD to be the RD input RE1 WR to be the WR input and RE2 CS to be the CS chip select input For this functionality the corresponding data direction bits of the TRISE register TRISE lt 2 0 gt must be configured as inputs set Th
6. FIGURE 19 3 CODE PROTECTED PROGRAM MEMORY FOR PIC18F2XX 4XX MEMORY SIZE DEVICE Block Code Protection 16 Kbytes 32 Kbytes Address Controlled By PIC 18FX42 PIC 18F X52 Range 000000h Boot Block Boot Block 0001FFh CPB WRTB EBTRB 000200h Block 0 Block 0 WRTO EBTRO 001FFFh 002000h Block 1 Block 1 CP1 WRT1 EBTR1 OO3FFFh Unimplemented ah a Block 2 CP2 WRT2 EBTR2 ES 005FFFh Unimplemented 99800081 Block 3 CP3 WRT3 EBTR3 007FFFh 008000h Unimplemented Unimplemented Read 0 5 Read 0 5 Unimplemented Memory Space 1FFFFFh TABLE 19 33 SUMMARY OF CODE PROTECTION REGISTERS File Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 3000081 CONFIG5L CP2 CP1 300009 CONFIG5H CPD CPB 30000Ah CONFIGGL WRT3 WRT2 WRT1 WRTO 30000Bh CONFIG6H WRTD WRTB WRTC 30000Ch CONFIG7L EBTR3 EBTR2 1 EBTRO 30000Dh CONFIG7H EBTRB Legend Shaded cells are unimplemented 2006 Microchip Technology Inc DS39564C page 207 PIC18FXX2 19 4 1 PROGRAM MEMORY outside of that block is not allowed to read and will CODE PROTECTION result in reading 05 Figures 19 4 through 19 6 illustrate Table Write and Table Read protection The user memory may be read to or written from any location using the Table Read and Table Write instruc
7. _ i i 2006 Microchip Technology Inc DS39564C page 309 PIC18FXX2 44 Lead Plastic Thin Quad Flatpack PT 10x10x1 mm Body 1 0 0 10 mm Lead Form TOFP Note For the most current package drawings please see the Microchip Packaging Specification located at http www microchip com packaging 4 DS39564C page 310 2006 Microchip Technology Inc PIC18FXX2 44 Lead Plastic Leaded Chip Carrier L Square PLCC Note Forthe most current package drawings please see the Microchip Packaging Specification located at http www microchip com packaging Fe E1 pu leads n1 Mes 1 1 CH2 x 45 x 45 A2 B E2 Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 44 44 Pitch p 050 1 27 Pins per Side ni 11 11 Overall Height A 165 173 180 4 19 4 39 4 57 Molded Package Thickness A2 145 153 160 3 68 3 87 4 06 Standoff 8 A1 020 028 035 0 51 0 71 0 89 Side 1 Chamfer Height 024 029 034 0 61 0 74 0 86 Corner Chamfer 1 CH1 040 045 050 1 02 1 14 1 27 Corner Chamfer others CH2 000 005 010 0 00 0 13 0 25 Overall Width E 685 690 695 17 40 17 53 17 65 Overall Length D 685 690 695 17 40 17 53 17
8. ef f pue SSeJppe 3Iq YIM Jngdss 1 pes foa f ta Xea Yra Ya cNOOdSS u LY LSMOV Mov SSeJppy 14 01 10 puooeg Jo geq Buniusuei lt 9 gt 6 094 14 1Y LSMOV 18819 eAe S 0 62 ov 2 22 2 v 0 e e S 0 SSEJPPY 184611 0 N3S uonipuoo LHYLS NAS lt 0 gt ZNOOdSS SIM 21855 705 vas 2006 Microchip Technology Inc DS39564C page 156 PIC18FXX2 12C MASTER MODE WAVEFORM RECEPTION 7 BIT ADDRESS FIGURE 15 22 1 111 116 5409955 1 198 SI AOdSS i 1 1 AOdSS 1 1 1048455 pepeojun SIUSIUCD pue HSdSS oiu 1114 1527 0 1v1SdSS 1 1 1 31485 0 spuodsej 41999 pue lt gt LVLSdSS pejee ui 719 0 vas 14 dios y i m i i di i l eouenbes 41955 JO pue AO JO DS 51455198 4 E MSS 1dnueju 41466 195 JO pue JE 44456 195 M19 10 uo ne Fo 4 6 Eki Vf BLA Vl Vf V e Vel Vj 6 e
9. VDD Rise Detect VDD Brown out Reset BOREN Power on Reset OST PWRT OST 0501 On chip 10 bit Ripple Counter Chip Reset R 10 bit Ripple Counter Enable PWRT Enable OST 2 See Table 3 1 for time out situations Note 1 Thisis a separate oscillator from the RC oscillator of the CLKI pin 2006 Microchip Technology Inc DS39564C page 25 PIC18FXX2 3 1 Power On Reset POR Power on Reset pulse is generated on chip when VDD rise is detected To take advantage of the POR cir cuitry just tie the MCLR pin directly or through a resis to This will eliminate external RC components usually needed to create a Power on Reset delay A minimum rise rate for VDD is specified parameter 0004 For a slow rise time see Figure 3 2 When the device starts normal operation i e exits the RESET condition device operating parameters volt age frequency temperature etc must be met to ensure operation If these conditions are not met the device must be held in RESET until the operating conditions are met FIGURE 3 2 EXTERNAL POWER ON RESET CIRCUIT FOR SLOW POWER UP _ AD MCLR 4 6 PIC 18 Note 1 Power on Reset circui
10. FIGURE 15 2 SPI MASTER SLAVE CONNECTION SPI Master SSPM3 SSPMO 00xxb SPI Slave SSPM3 SSPMO 010xb 500 SDI I I I I I I Serial Input Buffer Serial Input Buffer l SSPBUF SSPBUF I I I I I I I I I I I I I Shift Register SDI SDO Shift Register SSPSR SSPSR I MSb LSb MSb LSb Serial Clock SCK SCK PROCESSOR 1 PROCESSOR 2 2006 Microchip Technology Inc DS39564C page 129 PIC18FXX2 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK The master determines when the slave Processor 2 Figure 15 2 is to broadcast data by the software protocol 15 3 5 In Master mode the data is transmitted received as soon as the SSPBUF register is written to If the SPI is only going to receive the SDO output could be dis abled programmed as an input The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate As each byte is received it will be loaded into the SSPBUF register as if a normal received byte interrupts and status bits appropriately set This could be useful in receiver applications as a Line Activity Monitor mode The clock polarity is selected by appropriately program ming the bit SSPCON1 lt 4 gt This then would give waveforms for SPI communication as shown in FIGURE 15 3 SCK
11. Time Voltage Ta TB Legend Va LVD trip point VB Minimum valid device operating voltage The block diagram for the LVD module is shown in Figure 18 2 A comparator uses an internally gener ated reference voltage as the set point When the selected tap output of the device voltage crosses the set point is lower than the LVDIF bit is set Each node in the resistor divider represents a trip point voltage The trip point voltage is the minimum supply voltage level at which the device can operate before the LVD module asserts an interrupt When the supply voltage is equal to the trip point the voltage tapped off of the resistor array is equal to the 1 2V internal reference voltage generated by the voltage reference module The comparator then generates an interrupt signal setting the LVDIF bit This voltage is software programmable to any one of 16 values see Figure 18 2 The trip point is selected by programming the LVDL3 LVDLO bits LVDCON lt 3 0 gt 2006 Microchip Technology Inc DS39564C page 189 PIC18FXX2 FIGURE 18 2 LOW VOLTAGE DETECT LVD BLOCK DIAGRAM VDD LVDIN LVD Control N Register 16 to 1 MUX LVDEN Internally Generated Reference Voltage 1 2 gt LVDIF The LVD module has an additional feature that allows the user to supply the trip vol
12. _ DS39564C page 175 2006 Microchip Technology Inc PIC18FXX2 16 3 USART Synchronous Master Mode In Synchronous Master mode the data is transmitted in a half duplex manner i e transmission and reception do not occur at the same time When transmitting data the reception is inhibited and vice versa Synchronous mode is entered by setting bit SYNC TXSTA 4 In addition enable bit SPEN RCSTA 7 is set in order to configure the RC6 TX CK and RC7 RX DT 1 0 pins to CK clock and DT data lines respectively The Master mode indicates that the processor transmits the master clock on the CK line The Master mode is entered by setting bit CSRC TXSTA lt 7 gt USART SYNCHRONOUS MASTER TRANSMISSION The USART transmitter block diagram is shown in Figure 16 1 The heart of the transmitter is the Transmit serial Shift Register TSR The shift register obtains its data from the read write transmit buffer register TXREG The TXREG register is loaded with data in software The TSR register is not loaded until the last bit has been transmitted from the previous load As soon as the last bit is transmitted the TSR is loaded with new data from the TXREG if available Once the TXREG register transfers the data to the TSR register occurs in one TCYCLE the TXREG is empty and inter 16 3 1 PIE1 lt 4 gt Flag bit TXIF will be set regardless of the state of enable bit TXIE and ca
13. DS39564C page 286 2006 Microchip Technology Inc PIC18FXX2 TABLE 22 21 A D CONVERTER CHARACTERISTICS PIC18FXX2 INDUSTRIAL EXTENDED PIC18LFXX2 INDUSTRIAL 51 Symbol Characteristic Min Typ Max Units Conditions A01 NR Resolution 10 bit A03 EIL Integral linearity error lt 1 LSb VREF VDD 5 0V A04 EDL Differential linearity error lt 1 LSb VDD 5 0V A05 EG Gain error lt 1 LSb 5 0V A06 EOFF Offset error lt 1 5 150 VDD 5 0V A10 Monotonicity guaranteed Vss lt VAIN lt VREF A20 VREF Reference Voltage 1 8V V VDD lt 3 0V A20A VREFH VREFL V VpD gt 3 0V 21 VREFH Reference voltage High AVss AVDD 0 3V V A22 VREFL Reference voltage Low AVss 0 3V VREFH V A25 VAIN Analog input voltage AVss 0 3V AVDD 0 3V V VDD gt 2 5V Note 3 A30 ZAIN Recommended impedance of 2 5 Note 4 analog voltage source 50 IREF VREF input current Note 1 5 During VAIN acquisition 150 uA During A D conversion cycle Note 1 Vss lt VAIN lt VREF 2 The A D conversion result never decreases with an increase in the Input Voltage and has no missing codes 3 For VDD 2 5V VAIN should be limited to 5 VDD 4 Maximum allowed impedance for analog voltage source is 10
14. 0010 PIC18LFXX2 XT osc configuration 5 1 mA VDD 2 0 25 C Fosc 4 MHz 5 1 25 mA 2 0V 40 C to 85 C Fosc 4 MHz 1 2 2 mA VDD 4 2V 40 C to 85 C Fosc 4 MHz RC osc configuration 3 1 mA VDD 2 0 25 C Fosc 4 MHz 3 1 mA VDD 2 0 40 C to 85 C Fosc 4 MHz 1 5 3 mA VDD 4 2V 40 C to 85 C Fosc 4 MHz RCIO osc configuration 3 1 mA 2 0 25 C Fosc 4 MHz 3 1 mA VDD 2 0 40 C to 85 C Fosc 4 MHz m 75 3 mA VDD 4 2V 40 C to 85 C Fosc 4 MHz 0010 PIC18FXX2 XT osc configuration 1 2 15 mA 4 2V 25 Fosc 4 MHz 1 2 2 mA 4 2V 40 C to 85 C Fosc 4 MHz 1 2 3 MA VDD 4 2V 40 C to 125 C Fosc 4 MHz RC osc configuration 1 5 3 mA 4 2V 25 Fosc 4 MHz 1 5 4 MA VDD 4 2V 40 C to 85 C Fosc 4 MHz 1 6 4 mA VDD 4 2V 40 C to 125 C Fosc 4 MHz RCIO osc configuration 75 2 mA 4 2V 25 Fosc 4 MHz 75 3 mA 4 2V 40 C to 85 C Fosc 4 MHz 8 3 MA 4 2V 40 C to 125 C Fosc 4 MHz DO10A PIC18LFXX2 LP osc Fosc 32 kHz WDT disabled 14 30 LA 2 0V 40 C to 85 D010A PIC18FXX2 LP osc Fosc 32 kHz WDT disabled 40 70 LA VDD 4 2V 40 C to 85 C 50 100 pA 4 2 40 C to 125 C Legend Shading of rows is to assist in readability of t
15. File Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito POR DOR ns OSCCON SCS 0 21 LVDCON IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDLO 00 0101 191 WDTCON SWDTE 0 203 RCON IPEN RI TO PD POR BOR 1 11 53 28 84 1 Register High Byte XXXX XXXX 107 TMRIL Timer1 Register Low Byte XXXX XXXX 107 T1CON RD16 1 1 TICKPSO TIOSCEN TISYNC TMRICS TMR1ON 0 00 0000 107 TMR2 Timer2 Register 0000 0000 111 PR2 Timer2 Period Register 1111 1111 112 T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPSO TMR2ON T2CKPS1 T2CKPSO 000 0000 111 SSPBUF SSP Receive Buffer Transmit Register XXXX XXXX 125 SSPADD SSP Address Register in C Slave mode SSP Baud Rate Reload Register in 2 Master mode 0000 0000 134 SSPSTAT SMP CKE D A P S RW UA BF 0000 0000 126 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO 0000 0000 127 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 137 ADRESH Result Register High Byte xxxx xxxx 187 188 ADRESL A D Result Register Low Byte xxxx xxxx 187 188 ADCONO ADCS1 ADCSO CHS2 CHS1 CHSO GO DONE ADON 0000 00 0 181 ADCON1 ADFM ADCS2 PCFG3 PCFG2 PCFG1 PCFGO 00 0000 182 CCPRIH Register1 High Byte xxxx 121 123 CCPRIL Capture Compare PWM Register1 Low Byte xxxx xxxx 121 123 CCP1CON DC1B1 DC1BO CCP1M3 CCP1M
16. FIGURE 23 18 TYPICAL AND MAXIMUM AlwoT vs OVER TEMPERATURE WDT ENABLED 70 Typical statistical mean 25 C Maximum mean 30 40 C to 125 C Minimum mean 30 40 C to 125 C IPD LA Max 125 C Max 85 C V 2006 Microchip Technology Inc DS39564C page 297 PIC18FXX2 FIGURE 23 19 TYPICAL MINIMUM AND MAXIMUM WDT PERIOD vs 40 C 125 C 50 Typical statistical mean 25 C 45 Maximum mean 36 40 C to 125 C Minimum mean 36 40 C to 125 C 40 35 FIGURE 23 20 AlLVD vs OVER TEMPERATURE LVD ENABLED 4 5 4 78V 90 80 Max 125 C 70 60 Max 125 C 50 IDD 1 Typ 25 C 40 30 LVDIF can be cleared by firmware 20 LVDIF state is unknown LVDIF is set by hardware DS39564C page 298 2006 Microchip Technology Inc 2006 Microchip Technology Inc PIC18FXX2 FIGURE 23 23 TYPICAL AND MAXIMUM Vor vs lot 5V 40 C 125 Typical statistical mean 25 C Maximum mean 36 40 C to 125 C Minimum mean 40 C to 125 C VoL V lou mA FIGU
17. UBIU peyepdn si 55 pejepdn 5 qavdss 01 speeu 55 Aq Ti yey jes SI VN lt L gt 1VLSdSS Was JOU SI MOV 115 51409955 195 51 AOdSS s lt 9 gt NOOdSS AOdSS Bey 18019 HSdSS JO ANadss Jo pees si 408466 lt 0 gt 115455 48 lt gt 1 19 31955 d Jejsuen 48 SEN sng PEN PE AP EP EEE TEEN EP E zx fea Nea yea Yea Y za sov ov Yiv ew 12 Yev jov AN SV Vev X 0 X vas te Mov A 07 WH NEN o kg SseJppy jo puooes Ssseippy Jo eig 1514 ooe d USMEJ seu 30 erepdn sey 10 erepdn MOJ SI 49019 HUN MOJ SI 2012 2006 Microchip Technology Inc DS39564C page 142 PIC18FXX2 SLAVE MODE TIMING TRANSMISSION 10 BIT ADDRESS FIGURE 1
18. lt 9 gt NODdSS AOdSS lt 0 gt 1715459 48 E 41456 Fe SS SCENE U X ta X 2a X X ra X sa yao Voa Y 1a Yea Mov MOV Mol PISU 10 S 42019 geq cb play SI 22015 MOV 01198 470 909 116 Jo 18819 SI esneoeq PISU JOU SI 32019 HOV Xv X ev Ysy 0 vas 2006 Microchip Technology Inc DS39564C page 146 PIC18FXX2 SLAVE MODE TIMING SEN 1 RECEPTION 10 BIT ADDRESS FIGURE 15 14 elemyos lt b 0 USM qo gi Jes VN pue vn 109119 ou 1 eu jo 1 61 55 euijo ejepdn uy E ul Jes VN pue vn uo p y ou jo eJojeq JejsiBal gavdSSs jo uy UJUIU JO ssouppe peyepdn SI GdvdSS ques JOU SI MOV 110 119 88455 esneoeq 195 S Aedes perepdn speeu
19. Analog input D Digital I O C R of analog input channels of A D voltage references Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 1 Bit is set Bit is cleared x Bit is unknown Note Onany device RESET the port pins that are multiplexed with analog functions are forced to be an analog input DS39564C page 182 2006 Microchip Technology Inc PIC18FXX2 The analog reference voltage is software selectable to either the device s positive and negative supply voltage VDD and Vss or the voltage level on the RA3 AN3 VREF pin and RA2 AN2 VREF pin The A D converter has a unique feature of being able to operate while the device is in SLEEP mode To ate in SLEEP the A D conversion clock must be derived from the A D s internal RC oscillator The output of the sample and hold is the input into the converter which generates the result via successive approximation A device RESET forces all registers to their RESET state This forces the A D module to be turned off and any conversion is aborted Each port pin associated with the A D converter can be configured as an analog input RA3 can also be a voltage reference or as a digital I O The ADRESH and ADRESL registers contain the result of the A D conversion When the A D conversion is complete the result is loaded into the ADRESH ADRESL register
20. OSC1 CLKI r1 13 28 RD5 PSP5 OSC2 CLKO RAG lt 14 27 1 RD4 PSP4 RCO T1OSO T1CKI lt 1 15 26 RC7 RX DT 1 105 2 lt 16 25 RC6 TX CK RC2 CCP1 lt 17 24 RC5 SDO RC3 SCK SCL lt 18 23 4 RC4 SDI SDA RDO PSPO 19 22 RD3 PSP3 RD1 PSP1 lt 20 21 OD gt RD2 PSP2 MCLA Vep 91 MV 28 RAO ANO 2 27 RAV AN1 lt 3 26 RAZ AN2 VREF 4 25L RA3 AN3 VREF gt 5 24 RA4 TOCKI 6 3 23 RAS AN4 SS LVDIN 7 5 22 vss 1 8 ri 21 OSCI CLK 9 9 2011 OSC2II o 8 19 lt 11 18 lt 012 170 13 16 lt 14 15 2006 Microchip Technology Inc DS39564C page 3 PIC18FXX2 Table of Contents 110 Device OVErVI W LEES 2 0 Oscillator Configurations E 3 0 Reset its Ms a 4 0 Memory Organization desert TA 5 0 FLASH Program Memory 6 0 Data EEPROM Memory 7 0 8X8Hardware Multiplier zu 8 0 1 eT 9 0 I z TA e e AAA A HA ln 10 0 TimerO Module 11 0 Timer1 Module 12 0 Timer2 Module 13 0 Timer3 Module 14 0 Capture Compare PWM CCP Modules ii RR RR RH HRE 15 0 Master Synchronous Serial Port MSSP Module 16 0 Addressable Universal Synchronous Asynchronous Receiver Transmitter 5 165 17 0 C
21. TABLE 14 3 REGISTERS ASSOCIATED WITH CAPTURE COMPARE TIMER1 AND TIMER3 on Value on Name Bit 7 Bit6 Bit5 Bit4 Bit 3 Bit 2 Bit1 BitO POR BOR Other d RESETS INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 0000 000u PIR1 PSPIFO ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE PSPIEU ADIE RCIE TXIE SSPIE 1 TMR2IE 0000 0000 0000 0000 IPR1 5 ADIP RCIP TXIP SSPIP TMR2IP 0000 0000 0000 0000 TRISC PORTC Data Direction Register 1111 1111 1111 1111 TMRIL Holding Register for the Least Significant Byte of the 16 bit TMR1 Register XXXX uuuu uuuu TMRIH Holding Register for the Most Significant Byte of the 16 bit TMR1 Register XXXX UUUU uuuu TICON RD16 1 1 TICKPSO TIOSCEN TISYNC THR1CS TMR1ON 0000 u uu uuuu CCPRIL Capture Compare PWM Register1 LSB XXXX XXXX uuuu uuuu CCPRIH Capture Compare PWM Register1 MSB XXXX XXXX uuuu uuuu CCP1CON DC1B1 DC1BO CCP1M2 CCP1M1 00 0000 00 0000 CCPR2L Capture Compare PWM Register2 LSB XXXX uuuu uuuu CCPR2H Capture Compare PWM Register2 MSB XXXX uuuu uuuu CCP2CON DC2B1 DC2BO CCP2M3 2 2 CCP2M1 2 0 00 0000 00 0000 PIR2 EEIE BCLIF LVDIF TMRSIF CCP2IF 0 0000 0 0000 PI
22. a A MICROCHIP PIC18F442 L 0610017 2006 Microchip Technology Inc DS39564C page 306 PIC18FXX2 24 2 Package Details The following sections give the technical details of the packages 28 Lead Skinny Plastic Dual In line SP 300 mil Body PDIP Note For the most current package drawings please see the Microchip Packaging Specification located at http www microchip com packaging 1 ch CH RS RU ib ET M eeu Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch 100 2 54 Top to Seating Plane A 140 150 160 3 56 3 81 4 06 Molded Package Thickness A2 125 130 135 3 18 3 30 3 43 Base to Seating Plane A1 015 0 38 Shoulder to Shoulder Width E 300 310 325 7 62 7 87 8 26 Molded Package Width 1 275 285 295 6 99 7 24 7 49 Overall Length D 1 345 1 365 1 385 34 16 34 67 35 18 Tip to Seating Plane L 125 130 135 3 18 3 30 3 43 Lead Thickness c 008 012 015 0 20 0 29 0 38 Upper Lead Width B1 040 053 065 1 02 1 33 1 65 Lower Lead Width B 016 019 022 0 41 0 48 0 56 Overall Row Spacing 8 eB 320
23. ues jou SI MOV 108 88455 esneseq 2006 Microchip Technology Inc PIC 18FXX2 0 RECEPTION 7 BIT ADDRESS SLAVE MODE TIMING WITH SEN FIGURE 15 8 9 NOOdSS NOdSS 5021918455 48 me lt gt 5 IS If nn NV AoaX ta X za X ea va za Voa X ia Nea sa MOV Mov yov X av vas DS39564C page 140 PIC18FXX2 SLAVE MODE TIMING TRANSMISSION 7 BIT ADDRESS FIGURE 15 9 i SI 418458 USI HIdSS H paea Y 0 1v1SdSS 48 lt gt 1 19 41455 i 41855 01 spuodsej MOJ peu 19 ul ejeq ew Er EE PEN ene e e 666 8001000008 Buniusuei L sseJppy Mili DS39564C page 141 2006 Microchip Technology Inc PC SLAVE MODE TIMING WITH SEN 0 RECEPTION 10 BIT ADDRESS PIC18FXX2 FIGURE 15 10 0 NAS USYM 0 011ese jou seop perepdn 94 0 speeu qavdss eur jes SI VN ssoJppe Jo SSsoJppe Jo MOJ
24. e Boundaries Based on Operation 58 Table Pointer Boundaries 58 Table Reads and Table Writes 55 Block Diagrams Reads from FLASH Program Memory 59 Writing to sie ses ia 61 Protection Against Spurious Writes 63 Unexpected Termination E Write Verify retten G General Call Address Support GOTO e NU Re ee ee DS39564C page 318 2006 Microchip Technology Inc PIC18FXX2 VO eer its 87 MSSP Module ACK Pulsa saiia odio d re ea 139 Read Write Bit Information RW 139 SSP Module ACK Pulse aa 138 Master Mode Reception eene 155 Mode Clock Stretching see 144 Mode MSSP Module eee 134 Registers eterne ed RT 134 Module ACK Pulse 0 Acknowledge Seguence Timing Baud Rate Generator Bus Collision Repeated START Condition START Condition Clock Arbitration Effect of a RESET General Call Address Support Master Mode 2 4 02 2 Operation tot ht Repeated START Condition Timing is Master Mode START Condition
25. RBIE XXXXIF AE d INT1F XXXXIP INT1IE Additional Peripheral Interrupts INT2IF Interrupt to CPU Vector to Location 0018h O DS39564C page 74 2006 Microchip Technology Inc PIC18FXX2 8 1 INTCON Registers Note Interrupt flag bits are set when an interrupt The INTCON Registers are readable and writable reg isters which contain various enable priority and flag bits REGISTER 8 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit O condition occurs regardless of the state of its corresponding enable bit or the global enable bit User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt This feature allows for software polling INTCON REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W x bit 7 bit 0 GIE GIEH Global Interrupt Enable bit When IPEN z 0 1 Enables all unmasked interrupts Disables all interrupts When IPEN z 1 1 Enables all high priority interrupts 0 Disables all interrupts PEIE GIEL Peripheral Interrupt Enable bit When IPEN 0 1 Enables all unmasked peripheral interrupts Disables all peripheral interrupts When IPEN z 1 1 Enables all low priority peripheral interrupts Disables all low priority peripheral interrupts TMROIE TMRO Overflow Interrupt Enable
26. Y 2 N cem 1 1 i TT 1 1 1 1 1 1 1 1 805 i 1 1 OSCCON lt 0 gt 1 1 Counter 1 1 1 A 1 Note 1 Delay on internal system clock is eight oscillator cycles for synchronization The seguence of events that takes place when switch ing from the Timer1 oscillator to the main oscillator will depend on the mode of the main oscillator In addition to eight clock cycles of the main oscillator additional delays may take place FIGURE 2 9 a a If the main oscillator is configured for an external crys tal HS XT LP then the transition will take place after an oscillator start up time TOST has occurred A timing diagram indicating the transition from the Timer1 oscil lator to the main oscillator for HS XT and LP modes is shown in Figure 2 9 TIMING FOR TRANSITION BETWEEN TIMER1 AND 5 HS XT LP 6 Q1 Q2 024 Q1 Q2 93 TIP a a NN V ae Vv Tost Tscs 2 3 OSC2 APR AS AAA me i Internal System A 1 Osc Clock 1 k 1 i SCS e Y 5 lt 0 gt Program Counter PC X PC 2 X __PC 6 Note 1 1024 Tosc drawing not to scale DS39564C page 22
27. NA IA 13 13 OSC2 CLKO ito rada r 13 RAO ANO RA1 AN1 RA2 AN2 VREF RA3 AN3 VREF OCK same brand anta RAS5 AN4 SS LVDIN ere 13 RBO INT PAB te ess RB3 RB4 RB5 PGM ant esee t e ee des 14 sco EE 14 BBZ PGD LegemenesbestutU i ROI 14 RCO T1OSOP T1GKI ioco retten 15 RCT TTOSI CCP2 erret 15 En RASE 15 ROS SGK SCL ln 15 RCA SDI SDA 15 RCS SDO IN a 15 iuc Apc cR 15 RG7 RX DT tete Dette te enden a tete 15 RDO PSPO esce neni eh 16 RD1 PSP1 B 2 etie 16 RDS BSP39 lu 16 RD4 PSP4 16 RB5 PSP5 etit O RDG PSPO tee E ipee dd RD7 PSP7 5 BET WR ANG iii rr non rat nr 16 RE2 CS AN7 16 VDD 16 En ds 16 PIC18FXX2 Voltage Frequency Graph Ind strial remet recae 260 PIC18LFXX2 Voltage Frequency Graph Industrial ss erret terrre 260 PICDEM 1 Low Cost PICmicro Demonstration Board 255 PICDEM 17 Demonstration Board 256 PICDEM 2 Low Cost PIC16CXX Demonstration Board 255 PICDEM 3 Low Cost PIC1
28. TAN 1 Next Q4 cycle after 021 SSPSR to SSPBUF DS39564C page 132 2006 Microchip Technology Inc PIC18FXX2 15 3 8 SLEEP OPERATION In Master mode all module clocks are halted and the transmission reception will remain in that state until the device wakes from SLEEP After the device returns to Normal mode the module will continue to transmit receive data In Slave mode the SPI transmi receive shift register operates asynchronously to the device This allows the device to be placed in SLEEP mode and data to be shifted into the SPI transmi receive shift register When all 8 bits have been received the MSSP interrupt flag bit will be set and if enabled will wake the device from SLEEP 15 3 9 EFFECTS OF A RESET A RESET disables the MSSP module and terminates the current transfer 15 3 10 BUS MODE COMPATIBILITY Table 15 1 shows the compatibility between the standard SPI modes and the states the CKP and CKE control bits TABLE 15 1 SPIBUS MODES Standard SPI Mode Control Bits State Terminology CKP CKE 0 0 0 1 0 1 0 0 1 0 1 1 1 1 0 There is also SMP bit which controls when the data is sampled TABLE 15 2 REGISTERS ASSOCIATED WITH SPI OPERATION Value on Value on Name Bit7 Bit 6 Bit5 Bit4 Bit 2 Bit1 Bit O All Other RESETS INTCON GIE GIEH PEIE TMROIE
29. eyep Bojouuoe 1961002 LL 9L VL EL ZL 99 69 29991014 00791 AOI 8 SU esn LO 10 WOO dIYDOJOILU MMM JE 5 NYD OTSZd OWI ADI ADU uoisijoonuy ZHIN 9S ET M 5 uoisijo nuy ZHPI SZT A 5 ZHPI SZT ADI 5 w CIo42nu 353 JopuodsuejL 001 33 001333 ZI NA Did pueog uonensuoueg Nid I43GDld 17 pueog Z NA Did pueog T Did NA sLLVW 18287 Anua Snid LHVLSDId x mN212 U1 21 9 71 Jage nuu DI ADI FN 2412 UI DINI TdlA HSIQUSSSY jJASV dll gt STO 3 LTD OTSZd IW XXXdY OW 5 XXX48T 21
30. 4 2V 40 C to 85 C 00218 15 25 LA VDD 4 2V 40 C to 125 C Legend Shading of rows is to assist in readability of the table Note 1 This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET without losing RAM data 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as I O pin loading and switching rate oscillator type internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active Operation mode are OSC1 external square wave from rail to rail all I O pins tri stated pulled to VDD MCLR VDD WDT enabled disabled as specified 3 The power down current in SLEEP mode does not depend on the oscillator type Power down current is measured with the in SLEEP mode with all I O pins in hi impedance state and tied to VDD or Vss and all features that add delta current disabled such as WDT Timer1 Oscillator BOR 4 For RC osc configuration current through REXT is not included The current through the resistor can be estimated by the formula Ir VDD 2REXT mA with REXT in kOhm 5 The LVD and BOR modules share a large portion of circuitry The AIBOR and AILVD currents are not additive Once one of these modules is enabled the other may also be enabled without further penalty 2006 Microchip Technology Inc DS
31. Param No Symbol Characteristic Min Max Units Conditions 70 TssL2scH 554 to SCK or SCKT input Tcv ns TssL2scL 71 TscH SCK input high time Continuous 1 25 Tcy 30 ns 71A Slave mode Single Byte 40 ns Note 1 72 TscL SCK input low time Continuous 1 25 Tcv 30 ns 72A Slave mode Single Byte 40 ns Note1 7 TB2B Last clock edge of 1 to the first clock edge of Byte2 1 5 TCY 40 ns Note 2 TA TscH2diL Hold time of SDI data input to SCK edge 100 ns TscL2diL 75 TdoR SDO data output rise time PIC18FXXX 25 ns PIC18LFXXX 60 ns VDD 2V 76 TdoF SDO data output fall time PIC18FXXX 25 ns PIC18LFXXX 60 ns VDD 2V 77 TssH2doZ SS to 500 output hi impedance 10 50 ns 78 TscR SCK output rise time Master mode PIC18FXXX 25 ns PIC18LFXXX 60 ns VDD 2V 79 TscF SCK output fall time Master mode 25 ns PIC18LFXXX 60 ns VDD 2V 80 TscH2doV SDO data output valid after SCK PIC18FXXX 50 ns Tscl2doV edge PIC18LFXXX 150 ns Vbp 2V 82 TssL2doV SDO data output valid after SSL edge PIC18FXXX 50 ns PIC18LFXXX 150 ns VDD 2V 83 TscH2ssH 55 T after SCK edge 1 5 40 ns TscL2ssH 2006 Microchip Technology Inc DS39564C page 281 PIC18FXX2 FIGURE 22 16 PC BUS START STOP BITS TIMING SCL SDA START STOP Condition Condition Note Refer to Figure 22 4 for load condition
32. 1 Example SPI Slave Mode CKE 0 E Example SPI Slave Mode 1 External Clock All Modes except PLL First START Bit Timing Bus Data Bus START STOP Bits Master Mode Reception 7 bit Address 157 Master Mode Transmission 7 10 bit Address 156 C Slave Mode Timing 10 bit Reception 0 142 Slave Mode Timing 10 bit Transmission 143 C Slave Mode Timing 7 bit Reception SENS 0 140 Slave Mode Timing 7 bit Reception 1 146 147 Slave Mode Timing 7 bit Transmission 141 Low Voltage Detect 192 Master SSP Bus Data 284 Master SSP 12 Bus START STOP Bits 284 Parallel Slave Port PIC18F4X2 277 Parallel Slave Port Read Parallel Slave Port Write PWM Output Repeat START Condition RESET Watchdog Timer WDT Oscillator Start up Timer OST and Power up Timer PWRT 273 Slave Synchronization 131 Slaver Mode General Call Address Seguence 7 or 10 bit Address Mode
33. R W 0 R W 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 ADFM ADCS2 PCFG3 PCFG2 PCFG1 PCFGO bit 7 bit O ADFM A D Result Format Select bit 1 Right justified Six 6 Most Significant bits of ADRESH are read as 0 Left justified Six 6 Least Significant bits of ADRESL are read as V ADCS2 A D Conversion Clock Select bit ADCON bits in bold Clock Conversion lt ADCS2 gt lt ADCS1 ADCSO gt 0 00 Fosc 2 0 01 Fosc 8 0 10 Fosc 32 0 11 FRC clock derived from the internal A D RC oscillator 1 00 Fosc 4 1 01 Fosc 16 1 10 Fosc 64 1 ii FRC clock derived from the internal A D RC oscillator Unimplemented Read as 0 PCFG3 PCFGO A D Port Configuration Control bits 7 6 5 4 AN2 1 VREF VREF C R 0000 A A A A A A A A VDD Vss 8 0 0001 A A A A VREF A A A AN3 Vss 7 1 0010 D D D A A A A A VDD Vss 5 0 0011 D D D A VREF A A A AN3 Vss 4 1 0100 D D D D A D A A VDD Vss 3 0 0101 D D D D VREF D A A AN3 Vss 2 1 011x D D D D D D D D 0 0 1000 A A A A VREF VREF A A AN3 AN2 6 2 1001 D D A A A A A A VDD Vss 6 0 1010 D D A A VREF A A A AN3 Vss 5 1 1011 D D A A VREF VREF A A AN3 AN2 4 2 1100 D D D A VREF VREF A A AN3 AN2 3 2 1101 D D D D VREF VREF A A AN3 AN2 2 2 1110 D D D D D D D A VDD Vss 1 0 1111 D D D D VREF VREF D A AN3 AN2 1 2
34. 5 2 4 We A 5 Buffer Reg S SG RCREG norm 55 11777 4 OERR bit S SS SS CREN CC CC CC Note This timing diagram shows three words appearing on the RX input The RCREG receive buffer is read after the third word causing the OERR overrun bit to be set TABLE 16 7 REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION 2 Value on Value on Name Bit 7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit 1 Other RESETS GIE GIEH PEIE TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 0000 000u GIEL PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PsPIP ADIP RCIP SSPIP CCP1IP TMR2IP TMRIIP 0000 0000 0000 0000 RCSTA SPEN RX9 CREN ADDEN FERR OERR RX9D 0000 00x 0000 00x RCREG USART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 0000 010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend x unknown unimplemented locations read as 0 Shaded cells are not used for Asynchronous Reception Notel The PSPIF PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices always maintain these bits clear
35. ADIF RCIF TXIF SSPIF CCP1IF TMR2IF 0000 0000 0000 0000 PIE1 ADIE RCIE TXIE SSPIE CCP1IE TMRZIE TMR1IE 0000 0000 0000 0000 IPR1 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN JADDEN FERR OERR RX9D 0000 00x 0000 00x TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 0000 010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend x unknown unimplemented read as 0 Shaded cells are not used for Synchronous Slave Transmission Notel The PSPIF PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices always maintain these bits clear 2006 Microchip Technology Inc DS39564C page 179 PIC18FXX2 16 4 2 USART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception RECEPTION 1 Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit The operation of the Synchronous Master and Slave modes is identical except in the case of the SLEEP CSRC mode and bit SREN which is a don t care in Slave 2 If interrupts are desired set enable bit RCIE mode 3 If 9 bit reception is desired set bit RX9 If receive is enabled by setting bit CREN prior to the 4 To enable reception set enable bit CREN SLEEP instruction then a word may be received during 5 Flag bit will be set when r
36. VREFH 40 C 125 C Differential or Integral Nonlinearity LSB 2 2 5 3 3 5 4 4 5 5 5 5 VDD and V DS39564C page 302 2006 Microchip Technology Inc PIC18FXX2 FIGURE 23 29 A D NON LINEARITY vs VREFH 5V 40 C TO 125 C Max 40 C to 125 C Differential or Integral Nonlinearilty LSB 25 C VREFH V 2006 Microchip Technology Inc DS39564C page 303 PIC18FXX2 NOTES DS39564C page 304 2006 Microchip Technology Inc PIC18FXX2 24 0 PACKAGING INFORMATION 24 1 Package Marking Information 28 Lead SPDIP Example 0610017 YYWWNNN 5 O 28 Lead SOIC Example XXXXXXXXXXXXXXXXXXXX PIC18F242 E SO amp 0610017 YYWWNNN 5 40 Lead PDIP o D 2006 Microchip Technology Inc DS39564C page 305 PIC18FXX2 Package Marking Information Con d 44 Lead TOFP MICROCHIP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX O YYWWNNN 44 Lead PLCC gt 2 MICROCHIP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN MICROCHIP PIC18F452 E PT 0610017
37. MOVWF WORD ODD READ WORD TBLRD read into TABLAT and increment MOVF TABLAT W get data MOVWF WORD EVEN TBLRD read into TABLAT and increment MOVF TABLAT W get data 2006 Microchip Technology Inc DS39564C page 59 PIC18FXX2 5 4 Erasing FLASH Program memory The minimum erase block is 32 words or 64 bytes Only through the use of an external programmer or through ICSP control can larger blocks of program memory be bulk erased Word erase in the FLASH array is not supported When initiating an erase sequence from the micro controller itself a block of 64 bytes of program memory is erased The Most Significant 16 bits of the TBLPTR lt 21 6 gt point to the block being erased TBLPTR lt 5 0 gt are ignored The EECONI register commands the erase operation The EEPGD bit must be set to point to the FLASH pro gram memory The WREN bit must be set to enable write operations The FREE bit is set to select an erase operation For protection the write initiate sequence for EECON2 must be used A long write is necessary for erasing the internal FLASH Instruction execution is halted while in a long write cycle The long write will be terminated by the internal programming timer 5 4 1 FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory location is 1 Load table pointer with address of row being erased 2 Set EEPGD bit t
38. 2006 Microchip Technology Inc DS39564C page 163 PIC18FXX2 NOTES DS39564C page 164 2006 Microchip Technology Inc PIC18FXX2 16 0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER USART The Universal Synchronous Asynchronous Receiver Transmitter USART module is one of the two serial modules USART is also known as a Serial Com munications Interface or SCI The USART can be con figured as a full duplex asynchronous system that can communicate with peripheral devices such as CRT ter minals and personal computers or it can be configured as a half duplex synchronous system that can commu nicate with peripheral devices such as A D or D A integrated circuits serial EEPROMs etc The USART can be configured in the following modes Asynchronous full duplex Synchronous Master half duplex Synchronous Slave half duplex In order to configure pins RC6 TX CK and RC7 RX DT as the Universal Synchronous Asynchronous Receiver Transmitter bit SPEN RCSTA 7 must be set 1 bit TRISC 6 must be cleared 0 and bit TRISC lt 7 gt must be set 21 Register 16 1 shows the Transmit Status and Control Register TXSTA and Register 16 2 shows the Receive Status and Control Register RCSTA 2006 Microchip Technology Inc DS39564C page 165 PIC18FXX2 REGISTER 16 1 TXSTA TRANSMIT STATUS AND CONTROL REGISTER
39. instructions have an absolute pro gram memory address embedded into the instruction Since instructions are always stored on word bound aries the data contained in the instruction is a word address The word address is written to lt 20 1 gt which accesses the desired byte address in program memory Instruction 42 in Figure 4 5 shows how the instruction GOTO 000006h is encoded in the program memory Program branch instructions which encode a relative address offset operate in the same manner The offset value stored in a branch instruction repre sents the number of single word instructions that the PC will be offset by Section 20 0 provides further details of the instruction set INSTRUCTIONS IN PROGRAM MEMORY Program Memory Byte Locations Instruction 1 MOVLW 055h Instruction 2 GOTO 000006h Instruction 3 MOVFF Word p 123h 456h LSB 1 LSB 0 000000h 000002h 000004h 000006h OFh 55h 000008h EFh 03h 00000Ah 00h 00000Ch c1h 23h 00000Eh FAh 56h 000010h 000012h 000014h DS39564C page 40 2006 Microchip Technology Inc PIC18FXX2 4 7 1 TWO WORD INSTRUCTIONS The PIC18FXX2 devices have four two word instruc tions MOVFF CALL GOTO and LFSR The second word of these instructions has the 4 MSBs set to 1 5 and is a special kind of NOP instruction The lower 12 bits of the second word contain data to be used by the instr
40. 2 RB4 16 1 X RB5 PGM Decode logic H x RBe PcG Table Latch E RB7 PGD 8 ROM Latch PORTC X RCO T1OSO T1CKI 4 2 Instruction RC2 CCP1 Register 5 X RC3 SCK SCL ee 4 RC4 SDI SDA TX RC5 SDO pol 14 5 RCe TX CK Control PRODH PRODL gt X RC7 RX DT OSC2 CLKO d OSC1 CLKI Power up gt RDO PSPO T10SCI Timing Oscillator RD1 PSP1 T108CO Generation 7 Start up Timer RD2 PSP2 gt Power on RD3 PSP3 Reset RD4 PSP4 RD5 PSP5 AXPLL Watchdog RD6 PSP6 RD7 PSP7 REGE Brown out 8 recision Voltage Reference Low Voltage 2 Programming REO AN5 RD VoD x In Circuit 41 RE1 ANeANR Debugger a x 1 RE2 AN7 CS Timero 1 Timer2 Timer3 A D Converter Master CCP1 CCP2 Synchronous Addressable Parallel Slave Port Data EEPROM Serial Port USART EN EE JE ee A RT Note 1 Optional multiplexing of CCP2 inpu output with RB3 is enabled by selection of configuration bit 2 The high order bits of the Direct Address for the RAM are from the BSR register except for the MOVFF instruction 3 Many of the general purpose pins are multiplexed with one or more peripheral module functions The multiplexing combinations are device dependent 2006 Microchip Technology Inc DS39564C page 9 PIC18FXX2 TABLE 1 2 PIC18F2X2 PINOUT 1 0 DESCRIPTIONS
41. CCP2 input output is multiplexed with RB3 Legend R Readable bit Programmable bit U Unimplemented bit read as 0 Value when device is unprogrammed u Unchanged from programmed state REGISTER 19 5 CONFIGURATION REGISTER 4LOW CONFIG4L BYTE ADDRESS 300006h R P 1 U 0 U 0 U 0 U 0 R P 1 U 0 R P 1 BKBUG LVP STVREN bit 7 bit 0 bit 7 DEBUG Background Debugger Enable bit 1 Background Debugger disabled RB6 and RB configured as general purpose I O pins 0 Background Debugger enabled RB6 and RB7 are dedicated to In Circuit Debug bit6 3 Unimplemented Read as 0 bit 2 LVP Low Voltage ICSP Enable bit 1 Low Voltage ICSP enabled 0 Low Voltage ICSP disabled bit 1 Unimplemented Read as 0 bit O STVREN Stack Full Underflow Reset Enable bit 1 Stack Full Underflow will cause RESET Stack Full Underflow will not cause RESET Legend R Readable bit C Clearable bit U Unimplemented bit read as V n Value when device is unprogrammed Unchanged from programmed state DS39564C page 198 2006 Microchip Technology Inc PIC18FXX2 REGISTER 19 6 CONFIGURATION REGISTER 5 LOW CONFIG5L BYTE ADDRESS 300008h U 0 U 0 U 0 U 0 R C 1 R C4 RICH 1 cp2 0 bit 7 bit 0 bit 7 4 Unimplemented Read as bit 3 C
42. PCLATH Register PCLATU Register Program Memory Interrupt Vector Map and Stack for PIC18F 442 242 Map and Stack for PIC18F 452 252 2225 RESET a Program Verification and Code Protection Associated Registers Programming Device Instructions PSP See Parallel Slave Port Pulse Width Modulation See PWM CCP Module PUSH harran et a ates 240 PWM CCP Module Associated Registers CCPR1H CCPR1L Registers 122 Duty Gy Cle s aeree ox enero 122 Example Freguencies Resolutions 1238 Period Setup for PWM Operation Tus DS39564C page 322 2006 Microchip Technology Inc PIC18FXX2 RETFIE RETLW A Revision 313 RLCF RLNCF RRCF RRNCF S SCI See USART r AN SERI 125 SDI 125 SDO 125 Serial Clock SCK en steam 125 Serial Communication Interface See USART serial Data In SDI 125 Serial Data Out 125 Serial Peripheral Interface See SPI SETE etate na E ORO 245 Slave Select Synchronization 19 Slave Select SS 2 125 SLEEP 2 246 Software Simulator MPLAB SIM 254 Special Event Trigg
43. Pin Number pin Buffer M Pin Name Description DIP soic Type MCLR VPP 1 1 Master Clear input or high voltage ICSP programming enable pin MCLR ST Master Clear Reset input This pin is an active low RESET to the device VPP ST High voltage ICSP programming enable pin NC These pins should be left unconnected OSC1 CLKI 9 9 Oscillator crystal or external clock input OSC1 ST Oscillator crystal input or external clock source input ST buffer when configured in RC mode CMOS otherwise CLKI CMOS External clock source input Always associated with pin function OSC1 See related OSC1 CLKI OSC2 CLKO pins OSC2 CLKO RA6 10 10 Oscillator crystal or clock output OSC2 O Oscillator crystal output Connects to crystal or resonator in Crystal Oscillator mode CLKO In RC mode OSC2 pin outputs CLKO which has 1 4 the frequency of OSC1 and denotes the instruction cycle rate O TTL General Purpose I O pin PORTA is a bi directional I O port RAO ANO 2 2 RAO y o TTL Digital ANO Analog input 0 RA1 AN1 3 3 RA1 yo TTL Digital O AN1 Analog input 1 RA2 AN2 VREF 4 4 RA2 O TTL Digital I O AN2 Analog input 2 VREF A D Reference Voltage Low input RA3 AN3 VREF 5 5 RA3 O TTL Digital I O Analog input 3 VREF A D Reference Vo
44. tions The device ID may be read with Table Reads Note Code protection bits may only be written to The configuration registers may be read and written a from a 1 state It is not possible to with the Table Read and Table Write instructions write a 1 to a bit in the 0 state Code pro In User mode the CPn bits have no direct effect CPn tection bits are only set to 1 by a full chip bits inhibit external reads and writes A block of user erase or block erase function The full chip memory may be protected from Table Writes if the erase and block erase functions can only WRTn configuration bit is 0 The EBTRn bits control be initiated via ICSP or an external Table Reads For a block of user memory with the programmer EBTRN bit set to 0 a Table Read instruction that executes from within that block is allowed to read A Table Read instruction that executes from a location FIGURE 19 4 TABLE WRITE WRTn DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB EBTRB 11 0001FFh 000200h TBLPTR 000FFF WRTO EBTRO 01 001FFE TBLWT 001FFFh 002000h WRT1 EBTR1 11 003FFFh 004000h 004FFE TBLWT WRT2 EBTR2 11 OO5FFFh 006000h WRT3 EBTR3 11 007FFFh Results Table Writes disabled to Blockn whenever WRTn 0 DS39564C page 208 2006 Microchip Technology Inc PIC18FXX2 FIGURE 19 5 EXT
45. 0 Figure 15 3 Figure 15 5 and Figure 15 6 where the MSB is transmitted first In Master mode the SPI clock rate bit rate is user programmable to be one of the following Fosc 4 or Tcy Fosc 16 or 4 Tcy e Fosc 64 or 16 TCY Timer2 output 2 This allows a maximum data rate at 40 MHz of 10 00 Mbps Figure 15 3 shows the waveforms for Master mode When the bit is set the 500 data is valid before there is a clock edge on SCK The change of the input sample is shown based on the state of the SMP bit The time when the SSPBUF is loaded with the received data is shown SPI MODE WAVEFORM MASTER MODE SCK 1 SCK 0 SCK 1 SDO bit7 bit6 645 bit4 bit3 bit SDI bit7 Input Sample bito bit7 Input bito Sample DS39564C page 130 2006 Microchip Technology Inc PIC18FXX2 15 3 6 SLAVE In Slave mode the data is transmitted and received as the external clock pulses appear on SCK When the last bit is latched the SSPIF interrupt flag bit is set While in Slave mode the external clock is supplied by the external clock source on the SCK pin This external clock must meet the minimum high and low times as specified in the electrical specifications While in SLEEP mode the slave can transmit receive data When a byte
46. Bit is unknown 2006 Microchip Technology Inc DS39564C page 107 PIC18FXX2 11 1 Timer1 Operation can operate in one of these modes Asa timer As a synchronous counter As an asynchronous counter The Operating mode is determined by the clock select bit TMR1CS T1CON 1 When TMR1CS 0 Timer1 increments every instruc tion cycle When TMR1CS 1 Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator if enabled When the Timer1 oscillator is enabled TIOSCEN is set RC1 T1OSI and RCO T1OSO T1CKIl pins become inputs That is the TRISC lt 1 0 gt value is ignored and the pins are read as 0 1 also has an internal RESET input This RESET can be generated by the CCP module Section 14 0 FIGURE 11 1 TIMER1BLOCK DIAGRAM TMR1IF Synchronized r Clock Input TMRIH TMRIL td TMRION On Off TISYNC 1 Prescaler Synchronize Fosc 4 1 2 4 8 _f det Internal 0 Clock 2 SLEEP Input T1CKPS1 T1CKPSO TMR1CS FIGURE 11 2 TIMER1BLOCK DIAGRAM 16 BIT READ WRITE MODE DS39564C page 108 2006 Microchip Technology Inc PIC18FXX2 11 2 Oscillator A crystal oscillator circuit is built in between pins T1OSI input and T1OSO amplifier output It is enabled by setting control bit TT OSCEN T1CON 3 The oscilla tor is a low power oscillator rated u
47. DS39564C page 147 2006 Microchip Technology Inc PIC18FXX2 15 4 5 GENERAL CALL ADDRESS SUPPORT The addressing procedure for the bus is such that the first byte after the START condition usually deter mines which device will be the slave addressed by the master The exception is the general call address which can address all devices When this address is used all devices should in theory respond with an Acknowledge The general call address is one of eight addresses reserved for specific purposes by the protocol It consists of all 05 with R W 0 The general call address is recognized when the Gen eral Call Enable bit GCEN is enabled SSPCON2 7 set Following a START bit detect 8 bits are shifted into the SSPSR and the address is compared against the SSPADD It is also compared to the general call address and fixed in hardware FIGURE 15 15 SDA ONUS General Call Address R W Receiving data ACK If the general call address matches the SSPSR is transferred to the SSPBUF the BF flag bit is set eighth bit and on the falling edge of the ninth bit ACK bit the SSPIF interrupt flag bit is set When the interrupt is serviced the source for the inter rupt can be checked by reading the contents of the SSPBUF The value can be used to determine if the address was device specific or a general call address In 10 bit mode the SSPADD is required to be updated for the second half of
48. Legend R Readable bit W Writable bit U Unimplemented bit read as Value at POR 1 Bit is set V Bit is cleared X Bit is unknown DS39564C page 52 2006 Microchip Technology Inc PIC18FXX2 4 14 RCON Register Note 1 If the BOREN configuration bit is set The Reset Control RCON register contains flag bits that allow differentiation between the sources of a device RESET These flags include the TO PD POR BOR and Rlbits This register is readable and writable 115 recommended that the POR bit be set Brown out Reset enabled the BOR bit is 1 on a Power on Reset After a Brown out Reset has occurred the BOR bit will be cleared and must be set by firmware to indicate the occurrence of the next Brown out Reset after a Power on Reset has been detected so that subseguent Power on Resets may be detected REGISTER 4 3 RCON REGISTER R W 0 U 0 U 0 R W 1 R 1 R 1 R W 0 R W 0 IPEN RI TO PD POR BOR bit 7 bit O bit 7 IPEN Interrupt Priority Enable bit 1 Enable priority levels on interrupts 0 Disable priority levels on interrupts 16CXXX Compatibility mode bit 6 5 Unimplemented Read as 0 bit 4 RI RESET Instruction Flag bit 1 The RESET instruction was not executed 0 The RESET instruction was executed causing a device RESET must be set in software after a Brown out Reset occurs bit 3 Watchdog Time out
49. ZXX 8T Ild XXLOLTOId gt XVILTIId 6 514 XX849T Did 8 9 Id X8 297 214 XXL 297 Jld XL29T2Id 2 o N x 9 9 291 318 XS 297 318 00071214 Jld dVIdN 1001 1 6 EE SH pue DS39564C page 257 2006 Microchip Technology Inc PIC18FXX2 NOTES DS39564C page 258 2006 Microchip Technology Inc PIC18FXX2 22 0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings 0 Ambient temperature under 55 to 125 C Storage temperature 5 ote Ret tet etin de 65 C to 150 C Voltage on any pin with respect to Vss except VDD MCLR and 4 0 3V to VDD 0 3V Voltage VDD with respect to 55 0 3V to 7 5V Voltage MCLR with respect to VSS Note 2 OV to 13 25V Voltage on RA4 with respect to VSS sise OV to 8 5V Total power dissipation Note 1 1 0W Maximum current outor VSS PIN eni r i ne ed aee ede nett 300 mA Maximum current into VDD scisti neoe RR r 250 mA Input clamp current VI lt or VI gt VDD tenete tenete tenete ten
50. 0 1 a e 0 1 Operation f W dest Status Affected OV DC Z Encoding 0101 11 ffff Description Subtract W from register 25 complement method If d is 0 the result is stored in W If d is 1 the result is stored back in regis ter f default If a is 0 the Access Bank will be selected overriding the BSR value If a is 1 then the bank will be selected as per the BSR value default Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q4 Decode Read Process Write to register Data destination Example 1 SUBWF 1 0 Before Instruction REG 3 W 2 C 7 After Instruction REG 1 W 2 C 1 resultis positive 2 0 0 2 SUBWF REG 0 0 Before Instruction REG 2 W 52 C 2 After Instruction REG 52 W 0 1 s result is zero Z 1 0 Example 3 SUBWF REG 1 0 Before Instruction REG 1 W 2 C 2 After Instruction REG FFh 2 s complement W 2 C 0 resultis negative Z 0 N 1 2006 Microchip Technology Inc DS39564C page 247 PIC18FXX2 SUBWFB Subtract W from f with Borrow Syntax label SUBWFB f d a Operands 0 lt 1 lt 255 0 1 a e 0 1 Operation f W C gt dest Status Affected OV C DC Z Encoding 0101 10da Description Subtract W and the carry flag bor row from
51. 102 TR SDA and SCL rise 100 kHz mode 1000 ns time 400 kHz mode 20 0 1 CB 300 ns specified to be from 10 to 400 pF 103 TF SDA and SCL fall 100 kHz mode 1000 ns VDD gt 4 2V time 400 kHz mode 20 0 1 CB 300 ns VDD gt 4 2V 90 TSU STA START condition 100 kHz mode 4 7 us Only relevant for Repeated setup time 400 kHz mode 0 6 m us START condition 91 THD STA START condition hold 100 kHz mode 4 0 us After this period the first clock time 400 kHz mode 0 6 2 us pulse is generated 106 THD DAT Data input hold 100 kHz mode 0 ns 400 kHz mode 0 0 9 us 107 TSU DAT Data input setup time 100 kHz mode 250 ns Note 2 400 kHz mode 100 ns 92 TSU STO STOP condition 100 kHz mode 4 7 us setup time 400 kHz mode 0 6 us 109 Output valid from 100 kHz mode 3500 ns Note 1 clock 400 kHz mode ns 110 TBUF Bus free time 100 kHz mode 4 7 us Time the bus must be free 400 kHz mode 13 us before a new transmission can start D102 Bus capacitive loading 400 pF Note 1 As a transmitter the device must provide this internal minimum delay time to bridge the undefined region min 300 ns of the falling edge of SCL to avoid unintended generation of START STOP conditions 2 A Fast mode 12 bus device can be used in a Standard mode 2 bus system but the reguirement TSU DAT gt 250 ns must then be met This will automatically be the case if the device does not stretch th
52. 20 2 5 3 0 3 5 4 0 4 5 5 0 5 5 FIGURE 23 14 AVERAGE Fosc vs FOR VARIOUS VALUES OF RC MODE 300 pF 25 C 800 500 Freg MHz 200 100 V 2006 Microchip Technology lnc DS39564C page 295 PIC18FXX2 FIGURE 23 15 IPD vs 40 C TO 125 C SLEEP MODE ALL PERIPHERALS DISABLED 100 Max 40 C to 125 C 1 5 0 1 Typical statistical mean 25 C Maximum mean 30 40 C to 125 C Minimum mean 3o 40 C to 125 C 0 01 V FIGURE 23 16 AIBOR vs OVER TEMPERATURE BOR ENABLED VBOR 2 00 2 16V 90 80 70 Device 125 C Held in 60 RESET 50 85 C lt 3 a 8 40 25 30 5 20 SLEEP 10 0 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 V DS39564C page 296 2006 Microchip Technology Inc PIC18FXX2 FIGURE 23 17 TYPICAL AND MAXIMUM AlTMR1 vs OVER TEMPERATURE 10 C TO 70 C TIMER1 WITH OSCILLATOR XTAL 32 kHz AND C2 47 pF Typical statistical mean 25 C Maximum mean 86 10 C to 70 C Minimum mean 36 10 C to 70 C 70 C IPD LA
53. 55 jes SI JO Jaye jo qavdss peieel eq speeu 466 eu Y yeu jes s Jg 18910 oi 378855 Jo pees 7 peJeo o x leise sng Bey 48 18919 ANadSs Jo pee Awwing I 1v1Sdss vn lt 9 gt 09455 AOdSS 5455 10 Sjuejuoo uenum si 418485 UI Ud Y lt 0 gt 1VLSdSS 48 9JEMIJOS 1uld 21955 ej 00000010 WW 1 20 00 uu 1 M Nea Yra Xa yov VQ yea Yra Joa Xa MOV MOV esneoeq MOI PISU 10 SI eig SV Vv Yiv Xov IN vas Vev Yv Yo EK EK E geq 2110904 lt b 01188 SI 370 USMEJ Iun SI 2015 sey GdvdSs Jo eyepdn lun SI 90 2 SseJppy Jo puooes 07 MH ssalppy 10 eig 1514 eoe d USMEJ seu 5 Jo Iun moj si 49019
54. 60 ns VDD 2V 21 TioF Port output fall time PIC18FXXX 10 25 ns 21A PIC18LFXXX 60 ns VDD 2V 2211 TINP INT pin high or low time Toy x ns 2311 TRBP RB7 RB4 change INT high or low time Tcv ns 2411 TRCP RC7 RC4 change INT high or low time 20 ns Tt These parameters are asynchronous events not related to any internal clock edges Note 1 Measurements are taken in RC mode where CLKO output is 4 x TOSC FIGURE 22 7 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER AND POWER UP TIMER TIMING 5 2 m E i Internal 20 Za 5 33 PWRT Time out 3 gt OSC Time out M S Watchdog X Timer Reset Pins Note Refer to Figure 22 4 for load conditions 2006 Microchip Technology lnc DS39564C page 273 PIC18FXX2 FIGURE 22 8 BROWN OUT RESET TIMING BVDB lt ss __ VDD gt i 35 VBGAP 1 2V VIRVST Typical Enable Internal Reference Voltage Internal Reference Voltage stable 36 TABLE 22 7 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER POWER UP TIMER AND BROWN OUT RESET REOUIREMENTS da Symbol Characteristic Min Typ Max Units Conditions 30 TmeL MCLR Pulse Width low 2 us 31 TWDT Watchdog Timer Time out Period 7 18 33 ms
55. BRG decrements 02 and Q4 cycles A 0m X om X om X X 212 IX 02h 01h 00h hold off 03h 02h SCL is sampled high reload takes place and BRG starts its count BRG Reload ss DS39564C page 152 2006 Microchip Technology Inc PIC18FXX2 2 MASTER MODE START CONDITION TIMING To initiate a START condition the user sets the START condition enable bit SEN SSPCON2 lt 0 gt If the SDA and SCL pins are sampled high the baud rate genera tor is reloaded with the contents of SSPADD lt 6 0 gt and starts its count If SCL and SDA are both sampled high when the baud rate generator times out TBRG the SDA pin is driven low The action of the SDA being driven low while SCL is high is the START condition and causes the S bit SSPSTAT lt 3 gt to be set Follow ing this the baud rate generator is reloaded with the contents of SSPADD lt 6 0 gt and resumes its count When the baud rate generator times out TBRG the SEN bit SSPCON2 lt 0 gt will be automatically cleared by hardware the baud rate generator is suspended leaving the SDA line held low and the START condition is complete Note 15 4 8 If at beginning of the START condition the SDA and SCL pins are already sam pled low or if during the START condition the SCL line is sampled low before the SDA line is driven low a bus collision occurs the Bus Collision Interrupt Flag BCLIF
56. Master Mode Transmission Multi Master Communication Bus Collision and Arbitration 2 159 Multi Master Mode Operation Read Write Bit Information RW Bit 138 139 Serial Clock RCS SCK SCL 139 Slave Mode 138 Addressing 138 Reception seen 139 Transmission 139 Slave Mode Timing 10 bit Reception SEN Q cae dt bead dn itta 142 Slave Mode Timing 10 bit Reception SEN 1 sse 147 Slave Mode Timing 10 bit Transmission 1438 Slave Mode Timing 7 bit Reception SEN x esie ta Pag a tet 140 Slave Mode Timing 7 bit Reception SENS rates s 146 Slave Mode Timing 7 bit Transmission 141 SLEEP Operation af STOP Condition Timing eese 158 ICEPIC In Circuit Emulator eene 254 In Circuit Debugger ss 210 In Circuit Serial Programming ICSP 195 210 Indirect Addressing ss 51 INDF and FSR Registers 50 Indirect Addressing Operation 51 Indirect File Operand ss 42 INFSNZ inner Instruction Cycle Instruction Flow Pipelining eee 40 Instruction Format eret ene 213 2006 Microchip Technology Inc In
57. Note 1 See Register 19 12 for DEVID1 values REGISTER 19 1 bit 7 6 bit 5 bit 4 3 bit 2 0 CONFIGURATION REGISTER 1HIGH CONFIG1H BYTE ADDRESS 300001h U 0 U 0 R P 1 U 0 U 0 R P i 1 OSCSEN FOSC2 FOSC FOSCO bit 7 bit 0 Unimplemented Read as 0 OSCSEN Oscillator System Clock Switch Enable bit 1 Oscillator system clock switch option is disabled main oscillator is source 0 Oscillator system clock switch option is enabled oscillator switching is enabled Unimplemented Read as 0 FOSC2 FOSCO Oscillator Selection bits 111 RC oscillator w OSC2 configured as RA6 110 HS oscillator with PLL enabled Clock frequency 4 x Fosc 101 EC oscillator w OSC2 configured as RA6 100 EC oscillator w OSC2 configured as divide by 4 clock output 011 RC oscillator 010 HS oscillator 001 XT oscillator 000 LP oscillator Legend R Readable bit Programmable bit U Unimplemented bit read as 0 Value when device is unprogrammed u Unchanged from programmed state DS39564C page 196 2006 Microchip Technology Inc PIC18FXX2 REGISTER 19 2 CONFIGURATION REGISTER 2 LOW CONFIG2L BYTE ADDRESS 300002h U 0 U 0 U 0 U 0 R P 1 R P 1 R P 1 R P 1 BORV1 BORVO BOREN PWRTEN bit 7 bit 0 bit 7 4 Unimplemented Read as bit 3 2 BORV1 BORVO Brown out Reset Voltage bits 11 VBOR set to 2 5V 10
58. R W 0 R W 0 R W 0 R W 0 U 0 R W 0 R 1 R W 0 CSRC TX9 TXEN SYNC BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC Clock Source Select bit Asynchronous mode Don t care Synchronous mode 1 Master mode clock generated internally from BRG 0 Slave mode clock from external source bit 6 TX9 9 bit Transmit Enable bit 1 Selects 9 bit transmission 0 Selects 8 bit transmission bit 5 TXEN Transmit Enable bit 1 Transmit enabled 0 Transmit disabled Note SREN CREN overrides TXEN in SYNC mode bit 4 SYNC USART Mode Select bit 1 Synchronous mode 0 Asynchronous mode bit 3 Unimplemented Read as 0 bit 2 BRGH High Baud Rate Select bit Asynchronous mode 1 High speed 0 Low speed Synchronous mode Unused in this mode bit 1 TRMT Transmit Shift Register Status bit 1 TSR empty TSR full bit O TX9D 9th bit of Transmit Data Can be Address Data bit or a parity bit Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 7 Bit is set Bit is cleared Bit is unknown DS39564C page 166 2006 Microchip Technology Inc PIC18FXX2 REGISTER 16 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 RCSTA RECEIVE STATUS AND CONTROL REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R 0 R 0 R x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit O SPEN Serial Port Enable bit 1 Serial port enabled configu
59. is incremented before the read write FIGURE 5 3 TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL ERASE TBLPTR lt 21 6 gt WRITE TBLPTR lt 21 3 gt READ TBLPTR lt 21 0 gt DS39564C page 58 2006 Microchip Technology Inc PIC18FXX2 5 3 Reading the FLASH Program Memory The TBLRD instruction is used to retrieve data from pro gram memory and place into data RAM Table Reads from program memory are performed one byte at a time FIGURE 5 4 TBLPTR points to a byte address in program space Executing TBLRD places the byte pointed to into TABLAT In addition TBLPTR can be modified automatically for the next Table Read operation The internal program memory is typically organized by words The Least Significant bit of the address selects between the high and low bytes of the word Figure 5 4 shows the interface between the internal program memory and the TABLAT READS FROM FLASH PROGRAM MEMORY Even Byte Address Program Memory Odd Byte Address TBLPTR xxxxx1 TBLPTR Instruction Register TABLAT IR TBERD Read Register EXAMPLE 5 1 READING A FLASH PROGRAM MEMORY WORD MOVLW CODE ADDR UPPER Load TBLPTR with the base MOVWF TBLPTRU address of the word MOVLW CODE ADDR HIGH MOVWF TBLPTRH MOVLW CODE ADDR LOW MOVWF TBLPTRL
60. 14 5 2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPRIL register and to the CCP1CON lt 5 4 gt bits Up to 10 bit resolution is available The CCPR1L contains the eight MSbs and the CCP1CON lt 5 4 gt contains the two LSbs This 10 bit value is represented by CCPR1L CCP1CON 5 4 The following equation is used to calculate the PWM duty cycle in time PWM duty cycle CCPRIL CCPICON lt 5 4 gt Tosc TMR2 prescale value CCPR1L and CCP1CON lt 5 4 gt be written to at any time but the duty cycle value is not latched into CCPRIH until after a match between PR2 and TMR2 occurs i e the period is complete In PWM mode is a read only register The CCPR1H register and a 2 bit internal latch are used to double buffer the PWM duty cycle This double buffering is essential for glitchless PWM operation When the CCPR1H and 2 bit latch match TMR2 con catenated with an internal 2 bit Q clock or 2 bits of the TMR2 prescaler the 1 pin is cleared The maximum PWM resolution bits for a given PWM frequency is given by the equation Fosc log FPWM PWM Resolution max bits log 2 Note If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared DS39564C page 122 2006 Microchip Technology Inc PIC18FXX2 14 5 3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM o
61. 2006 Microchip Technology Inc PIC18FXX2 If the main oscillator is configured for HS PLL mode an oscillator start up time TosT plus an additional PLL time out TPLL will occur The PLL time out is typically 2 ms and allows the PLL to lock to the main oscillator freguency A timing diagram indicating the transition from the oscillator to the main oscillator for HS PLL mode is shown in Figure 2 10 FIGURE 2 10 TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 HS WITH PLL Q4 01 02 AZ 04 01 02 03 04 1 en IC 0561 O NERA NN ad ST tae M V Tscs idc i PA AAA AAA Internal System e LIVI VINNY Clock 1 U 1 1 1 1 1 1 1 so p Program Counter PC 2 O O X __ Note 1 Tosr 1024 Tosc drawing not to scale If the main oscillator is configured in the RC RCIO EC or ECIO modes there is no oscillator start up time out Operation will resume after eight cycles of the main oscillator have been counted A timing diagram indi cating the transition from the Timer1 oscillator to the main oscillator for RC RCIO EC and ECIO modes is shown in Figure 2 11 FIGURE 2 11 TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 RC EC a4 at Tte 02 04 at
62. 225 BRG See Baud Rate Generator Brown out Reset BOR 26 2006 Microchip Technology Inc DS39564C page 317 PIC18FXX2 C 226 Capture CCP Module Associated Registers n CCP Pin Configuration 2 222224222 119 CCPR1H CCPR1L Registers 119 Software Interrupt 2 Timer1 Timer3 Mode Selection 119 Capture Compare PWM CCP 117 Capture Mode See Capture seiten oxi EC REX EO RR Ege CCPR1H Register E CCPRIL Register 118 siia aco Eae epe 118 CCPR2H Register CCPR2L Register Compare Mode See Compare Interaction of Two CCP Modules 118 PWM Mode See PWM Timer Resources 0000000 118 Clocking Scheme lnstruction Cycle 39 227 et eet ee dent a 227 Code Examples 16 x 16 Signed Multiply Routine 72 16 x 16 Unsigned Multiply Routine 72 8 8 Signed Multiply Routine 71 8 x 8 Unsigned Multiply Routine 71 Changing Between Capture Prescalers 119 Data E
63. PEN RSEN SEN If the module is not in the IDLE mode this bit may not be set no spooling and the SSPBUF may not be written or writes to the SSPBUF are disabled Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2006 Microchip Technology Inc DS39564C page 137 PIC18FXX2 15 4 2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit SSPEN 55 lt 5 gt The SSPCONI register allows control of the 1 C oper ation Four mode selection bits SSPCON lt 3 0 gt allow one of the following 12 modes to be selected Master mode clock OSC 4 SSPADD 1 12 Slave mode 7 bit address C Slave mode 10 bit address 12 Slave mode 7 bit address with START and STOP bit interrupts enabled C Slave mode 10 bit address with START and STOP bit interrupts enabled 12 Firmware controlled master operation slave is IDLE Selection of any 1 C mode with the SSPEN bit set forces the SCL and SDA pins to be open drain pro vided these pins are programmed to inputs by setting the appropriate TRISC bits To guarantee proper oper ation of the module pull up resistors must be provided externally to the SCL and SDA pins 15 4 8 SLAVE MODE In Slave mode the SCL and SDA pins must be config ured as inputs TRISC 4 3 set The MSSP module w
64. PIC18FXX2 6 3 Reading the Data EEPROM Memory To read a data memory location the user must write the address to the EEADR register clear the EEPGD con trol bit 1 lt 7 gt clear the CFGS control bit EXAMPLE 6 1 DATA EEPROM READ DATA EE ADDR EECON1 lt 6 gt and then set control bit RD 1 lt 0 gt The data is available for the very next instruction cycle therefore the EEDATA register can be read by the next instruction EEDATA will hold this value until another read operation or until it is written to by the user during a write operation EEADR Data Memory Address to read EECON1 EEPGD EECON1 CFGS EECON1 RD EEDATA W EEPROM Read W EEDATA Point to DATA memory Access program FLASH or Data EEPROM memory 6 4 Writing to the Data EEPROM Memory To write an EEPROM data location the address must first be written to the EEADR register and the data writ ten to the EEDATA register Then the sequence in Example 6 2 must be followed to initiate the write cycle The write will not initiate if the above sequence is not exactly followed write 55h to EECON2 write to EECON2 then set WR bit for each byte It is strongly recommended that interrupts be disabled during this code segment Additionally the WREN bit in EECON1 must be set to enable writes This mechanism prevents accidental writes to data EEPROM due to unexpected code exe cution i e runaway pr
65. This requires higher acquisition times FIGURE 22 22 A D CONVERSION TIMING SAMPLE SAMPLING STOPPED Note 1 If the A D clock source is selected as RC a time of Tcv is added before the A D clock starts BSF ADCONO SoX Note 2 131 1 Q4 i FT LIL LEU LLL GO DONE This allows the SLEEP instruction to be executed 2 This is a minimal RC delay typically 100 nS which also disconnects the holding capacitor from the analog input 2006 Microchip Technology Inc DS39564C page 287 PIC18FXX2 TABLE 22 22 A D CONVERSION REQUIREMENTS re Symbol Characteristic Min Max Units Conditions 130 TaD A D clock period PIC18FXXX 1 6 204 us Tosc based PIC18FXXX 2 0 6 0 us A D RC mode 131 TCNV Conversion time 11 12 TAD not including acquisition time Note 1 132 TACQ Acquisition time Note 2 5 us VREF VDD 5 0V 10 us VREF VDD 2 5V 135 Tswc Switching Time from convert gt sample Note 3 Note 1 ADRES register may be read on the following Tcy cycle 2 The time for the holding capacitor to acguire the New input voltage when the new input value has not changed by more than 1 LSB from the last sampled voltage The source impedance Rs on the input channels is 500 See Section 17 0 for more information on acquisition time consideration 3 On the next Q4 cycle of t
66. not used for Synchronous Master Reception Note 1 The PSPIF PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices always maintain these bits clear FIGURE 16 8 SYNCHRONOUS RECEPTION MASTER MODE SREN o 04044101 4 4 4 4 RC7 RX DT pin Kr bit XT bits XK i bity XK bit5 bite X RCG TX CK pin Write to bit SREN SREN bit CREN bit 0 RCIF bit Interrupt Read RXREG Note Timing diagram demonstrates Sync Master mode with bit SREN 1 and bit BRGH 0 DS39564C page 178 2006 Microchip Technology Inc 164 USART Synchronous Slave Mode Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RCG TX CK pin instead of being supplied internally in Master mode This allows the device to transfer or receive data while in SLEEP mode Slave mode is entered by clearing bit CSRC TXSTA lt 7 gt USART SYNCHRONOUS SLAVE TRANSMIT The operation of the Synchronous Master and Slave modes are identical except in the case of the SLEEP mode If two words are written to the TXREG and then the 16 4 1 PIC18FXX2 To set up a Syn
67. ns 52 TccP CCPx input period 3 Tcv 40 ns N prescale value 1 4 or 16 53 TccR CCPx output fall time PIC18FXXX 25 ns PIC18LFXXX 60 ns VDD 2 54 TecF CCPx output fall time PIC18FXXX 25 ns PIC18LFXXX 60 ns VDD 2V DS39564C page 276 2006 Microchip Technology Inc PIC18FXX2 FIGURE 22 11 PARALLEL SLAVE PORT TIMING PIC18F4X2 RE2 CS dc REO RD N RE1 WR RD7 RDO 64 Note Refer to Figure 22 4 for load conditions TABLE 22 10 PARALLEL SLAVE PORT REQUIREMENTS PIC 18F4X2 2006 Microchip Technology Inc DS39564C page 277 PIC18FXX2 FIGURE 22 12 EXAMPLE SPI MASTER MODE TIMING 0 o SDI 173 Note Refer to Figure 22 4 for load conditions TABLE 22 11 EXAMPLE SPI MODE REQUIREMENTS MASTER MODE 0 ao Symbol Characteristic Min Max Units Conditions 70 TssL2scH SSJ to SCK or SCKT input Tcv ns TssL2scL 71 TscH SCK input high time Continuous 1 25 30 ns 71A Slave mode Single Byte 40 ns Note 1 72 TscL SCK input low time Continuous 1 25 30 ns 72A Slave mode Single Byte 40 ns Note 1 73 TdiV2scH Setup time of SDI data to SCK edge 100 ns TdiV2scL 7 TB2B Last clock edge of Byte1 to the 1st clock edge of Byte2 1 5 Tcy 40 ns Note 2 74 TscH2
68. A 2 4 NA 241 4023 185 2 40 0 181 9 6 9 62 40 16 103 9 62 016 64 9 52 0 83 46 9 60 0 32 19 2 1923 016 51 18 94 1 36 32 1945 132 22 18 64 294 16 76 8 7692 016 12 78 13 4173 7 7457 2 90 5 7920 3 13 3 96 100 417 9 8929 6 99 6 8949 678 4 105 60 10 00 2 300 33333 1111 2 31250 417 1 44744 449 15 0 316 80 45 60 0 500 500 0 1 625 2500 0 44744 10 51 0 NA HIGH 1000 0 625 0 447 44 0 316 80 0 LOW 3 91 255 2 44 255 1 75 255 1 24 2 255 BAUD FOSC 4MHz HERG 3 579545 MHZ SPBRG 1 MHz 32 768 kHz SPARG RATE value value value value Kbps KBAUD ERROR decima ERROR decima ERROR decimal ERROR decimal 0 3 NA 0 30 0 16 207 0 29 248 6 1 2 120 4046 207 120 023 185 120 016 51 102 14 67 1 24 240 016 103 241 023 92 240 016 25 205 14 67 0 9 6 9 62 40 16 25 973 4132 22 8 93 6 99 6 NA 5 3 19 2 1923 016 12 18 64 2 90 11 20 83 851 2 NA 76 8 NA 7457 2 90 2 62 50 18 62 0 NA 5 96 11186 16 52 1 NA 1 300 5 22372 25 43 0 NA 3 2 NA 500 NA 3 3 1 HIGH 250 0 55 93 0 62 50 0 2 05 0 LOW 0 98 255 0 22 255 0 24 255 0 008 255 2006 Microchip Technology Inc DS39564C page 171 PIC18FXX2 16 2 USART Asynchronous Mode In this mode the USART uses standard non return to zero NRZ format one START bit e
69. CLKO In RC mode OSC2 pin outputs CLKO which has 1 4 the frequency of OSC1 and denotes the instruction cycle rate O TTL General Purpose pin PORTA is a bi directional I O port RAO ANO 2 3 19 RAO y o TTL Digital I O ANO Analog input 0 RA1 AN1 3 4 20 RA1 y o TTL Digital I O AN1 Analog input 1 RA2 AN2 VREF 4 5 21 RA2 TTL Digital I O AN2 Analog input 2 VREF A D Reference Voltage Low input RA3 AN3 VREF 5 6 22 RA3 TTL Digital I O Analog input 3 VREF A D Reference Voltage High input RA4 TOCKI 6 7 23 RA4 O ST OD Digital I O Open drain when configured as output TOCKI ST TimerO external clock input RA5 AN4 SS LVDIN 7 8 24 5 O TTL Digital I O AN4 Analog input 4 55 ST SPI Slave Select input LVDIN Low Voltage Detect Input See the OSC2 CLKO RA6 pin Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input Output OD Open Drain diode to VDD 2006 Microchip Technology Inc DS39564C page 13 PIC18FXX2 TABLE 1 3 PIC18F4X2 PINOUT 1 0 DESCRIPTIONS CONTINUED Pin Number i Pin Name paid Description DIP PLCC YPE ype PORTB is a bi directi
70. Slow Rise Time MCLR Tied to VDD SPI Mode Master Mode SPI Mode Slave Mode with 0 SPI Mode Slave Mode with 1 Stop Condition Receive or Transmit Mode Time out Seguence on POR w PLL Enabled MCLR Tied to VDD 33 Time out Seguence on Power up MCLR Not Tied to VDD Case 1 Time out Seguence on Power up MCLR Tied to VDD 32 TimerO and Timer1 External Clock 275 Timing for Transition Between Timer1 and OSC1 HS with PLL 23 Transition Between Timer1 and O i 1 tmered 2 264 6 ed 15 2 2 6 264 6 edowit 11 h P 6 L 14 1 L TU F3 1 Tf9 255 2i4 15 2 14 1 L804 Tm a DS39564C page 324 2006 Microchip Technology Inc PIC18FXX2 W Wake up from SLEEP onen 195 205 Using Interrupts 205 Watchdog Timer WDT 195 203 Associated Registers 204 Control Register nnne ener e eee 203 Postscaler Programming Considerations 203 RG Oscillator 203 Time out Period 203 WOE 153 2006 Microchip Technology Inc DS39564C page 325 PIC18FXX2 NOTES DS39564C page 326
71. TOS PC 00345Ah 000124h After Instruction PC TOS Stack 1 level down 000126h 000126h 00345Ah N DS39564C page 240 2006 Microchip Technology Inc PIC18FXX2 RCALL Relative Call Syntax label RCALL Operands 1024 lt lt 1023 Operation 2 gt TOS PC 2 2 Status Affected None Encoding 1101 innn nnnn nnnn Description Subroutine call with a jump up to 1K from the current location First return address PC 2 is pushed onto the stack Then add the 25 complement number 2n to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is a two cycle instruction Words 1 Cycles 2 Q Cycle Activity Q1 Q2 04 Read literal Process Write to PC Data Push PC to stack No No No No operation operation operation operation HERE RCALL Jump Before Instruction Address HERE After Instruction PC Address Jump TOS Address HERE 2 RESET Reset Syntax abel RESET Operands None Operation Reset all registers and flags that are affected by a MCLR Reset Status Affected Encoding 0000 0000 1111 1111 Description This instruction provides a way to execute a MCLR Reset in software Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Start No No reset operation operation Examp
72. compiler optimized architecture instruction set Source code compatible with the PIC16 and PIC17 instruction sets Linear program memory addressing to 32 Kbytes Linear data memory addressing to 1 5 Kbytes Upto 10 MIPs operation DC 40 MHz osc clock input 4 MHz 10 MHz osc clock input with PLL active 16 bit wide instructions 8 bit wide data path Priority levels for interrupts 8 x 8 Single Cycle Hardware Multiplier Peripheral Features High current sink source 25 mA 25 mA Three external interrupt pins TimerO module 8 bit 16 bit timer counter with 8 bit programmable prescaler e Timer1 module 16 bit timer counter Timer2 module 8 bit timer counter with 8 bit period register time base for PWM Timer3 module 16 bit timer counter Secondary oscillator clock option Timer1 Timer3 Two Capture Compare PWM CCP modules CCP pins that can be configured as Capture input capture is 16 bit max resolution 6 25 ns TCY 16 Compare is 16 bit max resolution 100 ns TCY PWM output PWM resolution is 1 to 10 bit max PWM freq 8 bit resolution 156 kHz 10 bit resolution 2 39 kHz Master Synchronous Serial Port MSSP module Two modes of operation 3 wire SPITM supports all 4 SPI modes IC Master and Slave mode PIC 18FXX2 Peripheral Features Continued Addressable USART module Supports RS 485 and RS 232 Parallel Slave Port PSP module Analog Featu
73. 0 Low priority bit 3 BCLIP Bus Collision Interrupt Priority bit 1 High priority 0 Low priority bit 2 LVDIP Low Voltage Detect Interrupt Priority bit 1 High priority 0 Low priority bit 1 TMR3IP TMR3 Overflow Interrupt Priority bit 1 High priority 0 Low priority bit 0 CCP2IP CCP2 Interrupt Priority bit 1 High priority 0 Low priority Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown 2006 Microchip Technology Inc DS39564C page 83 PIC18FXX2 8 5 RCON Register The RCON register contains the bit which is used to enable prioritized interrupts REGISTER 8 10 RCON REGISTER R W 0 U 0 U 0 R W 1 R 1 R 1 R W 0 R W 0 IPEN RI TO PD POR BOR bit 7 bit O bit 7 IPEN Interrupt Priority Enable bit 1 Enable priority levels on interrupts Disable priority levels on interrupts 16CXXX Compatibility mode bit6 5 Unimplemented Read as 0 bit 4 RI RESET Instruction Flag bit For details of bit operation see Register 4 3 bit 3 TO Watchdog Time out Flag bit For details of bit operation see Register 4 3 bit 2 PD Power down Detection Flag bit For details of bit operation see Register 4 3 bit 1 POR Power on Reset Status bit For details of bit operation see Register 4 3 bit O BOR Brown out Reset Status bit For details of bit operation see
74. 0000 000u GIEH GIEL PIR1 PSPIF ADIF RCIF SSPIF CCP1IF TMR2IF 0000 0000 0000 0000 PIE 1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMRIIE 0000 0000 0000 0000 IPR1 PsPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP 0000 0000 0000 0000 PIR2 EEIF BCLIF LVDIF TMRSIF CCP2IF 0 0000 0 0000 PIE2 EEIE BCLIE LVDIE CCP2IE 0 0000 0 0000 IPR2 EEIP LVDIP CCP2IP 1 1111 1 0000 ADRESH A D Result Register uuuu ADRESL A D Result Register XXXX XXXX uuuu uuuu ADCONO ADCS1 ADCSO CHS2 CHSI CHSO GO DONE ADON 0000 00 0 0000 00 0 ADCON1 ADFM ADCS2 PCFG3 PCFG2 PCFG1 PCFGO 000 000 PORTA 5 4 RA2 RA1 RAO 0x 0000 0u 0000 TRISA PORTA Data Direction Register 11 1111 11 1111 RE2 RE1 REO 000 000 LATE LATE2 LATE1 LATEO uuu TRISE IBF OBF IBOV PSPMODE PORTE Data Direction bits 0000 111 0000 111 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used for A D conversion Note 1 The PSPIF PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices always maintain these bits clear DS39564C page 188 2006 Microchip Technology Inc PIC18FXX2 18 0 LOW VOLTAGE DETECT In many applications the ability to determ
75. 0100 m 4 GPR Access Bank 4FFh 00h 20101 00h 500h Access RAM low 5 GPR 7Fh Access RAM high 80h FFh SFR s 600h FFh T When a 0 gt Bank6 Unused A the BSR is ignored and the 1110 to M Read 00h gt Access Bank is used e Bank 14 The first 128 bytes are General Purpose RAM from Bank 0 The second 128 bytes are Special Function Registers EFFh from Bank 15 1111 00h Unused Bank 15 F80h FFh FFFh When 1 the BSR is used to specify the RAM location that the instruction uses DS39564C page 44 2006 Microchip Technology Inc PIC18FXX2 SPECIAL FUNCTION REGISTER MAP TABLE 4 1 Address Name FFFh TOSU FFEh TOSH FFDh TOSL FFCh STKPTR FFBh PCLATU FFAh PCLATH FF9h PCL FF8h TBLPTRU FF7h TBLPTRH TBLPTRL FF5h TABLAT FF4h PRODH PRODL FF2h INTCON FFih INTCON2 FFOh INTCON3 FEFh INDFOG FEEh POSTINCO FEDh POSTDECO FECh PREINCOG FEBh PLUSWoO FEAh FSROH FE9h FSROL FE8h WREG FE7h INDF1 FEeh POSTINC1 FE5h POSTDEC1 FE4h PREINC1 FE3h PLUSW16 FE2h FSR1H FSRIL FEOh BSR Address FDFh FDEh FDDh FDC FDBh FDAh FD9h FD8h FD7h FD6h FD5h FD4h FD3h FD2h FDih FDOh FCFh FCEh FCDh FCCh FCBh FCAh FC9h FC8h FC7h FC6h FC5h FC4h FC3h FC2h FC1h FCOh Name INDF2 POSTINC20
76. 1 certain registers loaded into from shadow registers Fast mode u Unused or Unchanged WREG Working register accumulator x Dont care 0 or 1 The assembler will generate code with x 0 It is the recommended form of use for compatibility with all Microchip software tools TBLPTR 21 bit Table Pointer points to a Program Memory location TABLAT 8 bit Table Latch TOS Top of Stack PC Program Counter PCL Program Counter Low Byte PCH Program Counter High Byte PCLATH Program Counter High Byte Latch PCLATU Program Counter Upper Byte Latch GIE Global Interrupt Enable bit WDT Watchdog Timer TO Time out bit PD Power down bit C DC Z OV ALU status bits Carry Digit Carry Zero Overflow Negative 11 Optional gt 5 Contents gt Assigned to lt gt Register bit field In the set of italics User defined term font is courier DS39564C page 212 2006 Microchip Technology Inc PIC18FXX2 FIGURE 20 1 GENERAL FORMAT FOR INSTRUCTIONS Byte oriented file register operations Example Instruction 15 10 9 87 0 OPCODE d a f FILE ADDWF MYREG W B d 0 for result destination to be WREG register d 1 for result destination to be file register f 0 to force Access Bank 1 for BSR to select bank f 8 bit file register address Byte to Byte move operations 2 word 15 12 11 0 OPCODE f Source FILE MOVFF MYREG1 MYREG2 15 12 11 0 1111 f D
77. 125 C 25 us LPosc 2 TCY Instruction Cycle Time 100 ns 4 Fosc 40 C to 85 C 160 ns TcY 4 Fosc 85 C to 125 C 3 TosL External Clock in OSC1 30 ns TosH High or Low Time 2 5 ps osc 10 ns 5 osc 4 TosR External Clock in OSC1 20 ns TosF Rise or Fall Time 2 50 ns ILP osc 7 5 ns 5 osc Note 1 Instruction cycle period eguals four times the input oscillator time base period for all configurations except PLL All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code Exceeding these specified limits may result in an unstable oscillator operation and or higher than expected current consumption All devices are tested to operate at min values with an external clock applied to the OSC1 CLKI pin When an external clock input is used the max cycle time limit is DC no clock for all devices 2006 Microchip Technology Inc DS39564C page 271 PIC18FXX2 TABLE 22 5 PLL CLOCK TIMING SPECIFICATIONS VoD 4 2 5 5V i Sym Characteristic Min Typt Units Conditions Fosc Oscillator Frequency Range 4 10 MHz HS mode only Fsvs VCO System Frequency 16 40 MHz HS mode only jte PLL Start up Time Lock Time 2 ms CLKO S
78. 252 452 0 0000 0 0000 u uuuu PCLATH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu PCL 242 442 252 452 0000 0000 0000 0000 PC 200 TBLPTRU 242 442 252 452 00 0000 00 0000 uu uuuu TBLPTRH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu TBLPTRL 242 442 252 452 0000 0000 0000 0000 uuuu uuuu TABLAT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu PRODH 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu PRODL 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu INTCON 242 442 252 452 0000 000x 0000 000u uuuu uuuulP INTCON2 242 442 252 452 ria ies 1111 1 1 uuuu u u INTCON3 242 442 252 452 11 0 0 00 11 0 0 00 uu u INDFO 242 442 252 452 N A N A POSTINCO 242 442 252 452 N A N A N A POSTDECO 242 442 252 452 N A N A N A PREINCO 242 442 252 452 N A N A N A PLUSWO 242 442 252 452 N A N A N A FSROH 242 442 252 452 uuuu uuuu FSROL 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu WREG 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu INDF1 242 442 252 452 N A N A N A POSTINC1 242 442 252 452 N A N A N A POSTDECI 242 442 252 452 N A N A N A PREINCI 242 442 252 452 N A N A N A PLUSW1 242 442 252 452 N A N A Legend u unchanged x unknown Shaded cells indicate conditions do not apply for the designated device Note 1 One or more bits in the
79. 2s complement It indicates whether the result was negative ALU MSB 1 1 Result was negative 0 Result was positive bit 3 OV Overflow bit This bit is used for signed arithmetic 2s complement It indicates an overflow of the 7 bit magnitude which causes the sign bit bit7 to change state 1 Overflow occurred for signed arithmetic in this arithmetic operation 0 2 No overflow occurred bit 2 Z Zero bit 1 The result of an arithmetic or logic operation is zero 0 The result of an arithmetic or logic operation is not zero bit 1 DC Digit carry borrow bit For ADDWF ADDLW SUBLW and SUBWF instructions 1 carry out from the 4th low order bit of the result occurred No carry out from the 4th low order bit of the result Note For borrow the polarity is reversed A subtraction is executed by adding the two s complement of the second operand For rotate RLF instructions this bit is loaded with either the bit 4 or bit 3 of the source register bit O C Carry borrow bit For ADDWF ADDLW SUBLW and SUBWF instructions 1 carry out from the Most Significant bit of the result occurred 0 No carry out from the Most Significant bit of the result occurred Note For borrow the polarity is reversed A subtraction is executed by adding the two s complement of the second operand For rotate RLF instructions this bit is loaded with either the high or low order bit of the source register
80. 350 430 8 18 8 89 10 92 Mold Draft Angle Top 5 10 15 5 10 15 Mold Draft Angle Bottom B 5 10 15 5 10 15 Controlling Parameter 8 Significant Characteristic Notes Dimension D and 1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Eguivalent MO 095 Drawing No 04 070 SS __ ___ 2006 Microchip Technology Inc DS39564C page 307 PIC18FXX2 28 Lead Plastic Small Outline SO Wide 300 mil Body SOIC Note For the most current package drawings please see the Microchip Packaging Specification located at http www microchip com packaging I E 1 1 1 4 D 4 2 C O L 1 Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p 050 1 27 Overall Height 093 099 104 2 36 2 50 2 64 Molded Package Thickness A2 088 091 094 2 24 2 31 2 39 Standoff 8 1 004 008 012 0 10 0 20 0 30 Overall Width 394 407 420 10 01 10 34 10 67 Molded Package Width 1 288 295 299 7 32 7 49 7 59 Overall Length D 695 704 712 17 65 17 87 18 08 Chamfer Distance h 010 020 029 0 25 0 50 0 74 Foot Length L 016 033 050 0 41 0 84 1 27 Foot Angle Top 0 4 8 0 4 8 Lead Thickness 0
81. Clearing a TRISD bit 0 will make the corresponding PORTD pin an output i e put the contents of the output latch on the selected pin The Data Latch register LATD is also memory mapped Read modify write operations on the LATD register reads and writes the latched output value for PORTD PORTD is an 8 bit port with Schmitt Trigger input buff ers Each pin is individually configurable as an input or output Note On a Power on Reset these pins are configured as digital inputs PORTD can be configured as an 8 bit wide micropro cessor port parallel slave port by setting control bit PSPMODE TRISE lt 4 gt In this mode the input buffers are TTL See Section 9 6 for additional information on the Parallel Slave Port PSP EXAMPLE 9 4 INITIALIZING PORTD CLRF PORTD Initialize PORTD by Clearing output data latches LATD Alternate method to clear output data latches Value used to initialize data MOVLW direction Set RD lt 3 0 gt as inputs RD lt 5 4 gt as outputs RD lt 7 6 gt as inputs MOVWF TRISD FIGURE 9 8 PORTD BLOCK DIAGRAM IN O PORT MODE Data RD LATD Bus 4 D a gt WR LATD opna r CK x PORTD Data Latch D WR TRISD CK X Schmitt Trigger N TRIS Latch Input Buffer lt RD TRISD a D RD PORTD gt Note 1 pins have diode protection to
82. PIC18LFXX2 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 lt TA lt 85 for industrial Standard Operating Conditions unless otherwise stated PIC18FXX2 5 Industrial Extended Operating temperature 40 C lt TA lt 85 C for industrial 40 C lt TA lt 125 for extended un Symbol Characteristic Min Typ Max Units Conditions IDD Supply Current Continued DO10C PIC18LFXX2 EC ECIO osc configurations 10 25 mA 4 2V 40 C to 85 C DO10C PIC18FXX2 EC ECIO osc configurations 10 25 mA 4 2V 40 C to 125 C 0013 PIC18LFXX2 HS osc configuration 6 2 mA Fosc 4 MHz 2 0V 10 15 mA Fosc 25 MHz VDD 5 5V HS PLL osc configurations 15 25 mA 10 MHz 5 5V 0013 PIC18FXX2 HS osc configuration 10 15 mA Fosc 25 MHz VDD 5 5V HS osc configurations 15 25 mA 10 MHz 5 5V D014 PIC18LFXX2 Timer1 osc configuration m 15 55 LA FOSC 32 kHz VDD 2 0V D014 PIC18FXX2 Timer1 osc configuration 200 uA 32 kHz VDD 4 2V 40 C to 85 250 uA Fosc 32 kHz VDD 4 2V 40 C to 125 C IPD Power down Current DO20 PIC18LFXX2 08 9 uA VDD 2 0V 25 C 1 4 VDD 2 0V 40 C to 85 C 3 10 VDD 4 2V 40 C to 85 C 0020 PIC18FXX2 4 9 VDD 4 2V 25 C 3 10
83. POSTDEC20 PREINC28 PLUSW28 FSR2H FSR2L STATUS TMROH TMROL TOCON OSCCON LVDCON WDTCON RCON TMR1H TMRIL TICON TMR2 PR2 T2CON SSPBUF SSPADD SSPSTAT SSPCONI SSPCON2 ADRESH ADRESL ADCONO ADCON1 Note 1 Unimplemented registers are read as 0 2 This register is not available on PIC18F2X2 devices 3 This is not a physical register Address FBFh FBEh FBDh FBCh FBBh FBAh FB9h FB8h FB7h FB6h FB5h FB4h FB3h FB2h FBih FBOh FAFh FAEh FADh FACh FABh FAAh FA9h FA8h FA7h FA6h FA5h FA4h FA3h FA2h FA1h FAOh Name Address CCPR1H CCPR1L CCP1CON CCPR2H CCPR2L CCP2CON TMRBL SPBRG RCREG TXREG TXSTA F8Dh F8Ch RCSTA EEADR EEDATA EECON2 1 F9Fh IPR1 F9Eh PIR1 F9Dh PIE1 F9Ch F9Bh F9Ah F99h F98h F97h F96h TRISE F95h TRISD F94h TRISC F93h TRISB F92h TRISA F91h F90h F8Fh F8Eh LATE LATD F8Bh LATC F8Ah LATB F89h LATA F88h F87h F86h F85h F84h PORTE F83h F82h PORTC F81h PORTB F80h PORTA 2006 Microchip Technology Inc DS39564C page 45 PIC18FXX2
84. RESET from CCP module special event trigger REGISTER 11 1 bit 7 bit 6 bit 5 4 bit 3 bit 2 bit 1 bit 0 TICON TIMER1 CONTROL REGISTER R W 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 RD16 1 1 50 TIOSCEN TISYNC TMR1CS TMR1ON bit 7 bit 0 RD16 16 bit Read Write Mode Enable bit 1 Enables register Read Write of in one 16 bit operation 0 Enables register Read Write of Timer1 in two 8 bit operations Unimplemented Read as 0 51 50 Timer1 Input Clock Prescale Select bits 11 1 8 Prescale value 10 1 4 Prescale value 01 1 2 Prescale value 00 1 1 Prescale value TIOSCEN Timer1 Oscillator Enable bit 1 Timer1 Oscillator is enabled 0 Timer1 Oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain TISYNC Timer1 External Clock Input Synchronization Select bit When TMR1CS z 1 1 Do not synchronize external clock input Synchronize external clock input When TMR1CS z 0 This bit is ignored Timer1 uses the internal clock when TMR1CS 0 TMR1CS Timer1 Clock Source Select bit 1 External clock from pin RCO T1OSO T13CKI on the rising edge 0 Internal clock Fosc 4 TMRION Timer1 On bit 1 Enables 0 Stops Timer1 Legend R Readable bit W Writable bit U Unimplemented bit read as Value at POR 1 Bit is set V Bit is cleared
85. SOIC PLCC and packages only EEE En 2006 Microchip Technology Inc DS39564C page 329 MICROCHIP AMERICAS Corporate Office 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 480 792 7200 Fax 480 792 7277 Technical Support http support microchip com Web Address www microchip com Atlanta Alpharetta GA Tel 770 640 0034 Fax 770 640 0307 Boston Westborough MA Tel 774 760 0087 Fax 774 760 0088 Chicago Itasca IL Tel 630 285 0071 Fax 630 285 0075 Dallas Addison TX Tel 972 818 7423 Fax 972 818 2924 Detroit Farmington Hills MI Tel 248 538 2250 Fax 248 538 2260 Kokomo Kokomo IN Tel 765 864 8360 Fax 765 864 8387 Los Angeles Mission Viejo CA Tel 949 462 9523 Fax 949 462 9608 Santa Clara Santa Clara CA Tel 408 961 6444 Fax 408 961 6445 Toronto Mississauga Ontario Canada Tel 905 673 0699 Fax 905 673 6509 ASIA PACIFIC Asia Pacific Office Suites 3707 14 37th Floor Tower 6 The Gateway Habour City Kowloon Hong Kong Tel 852 2401 1200 Fax 852 2401 3431 Australia Sydney Tel 61 2 9868 6733 Fax 61 2 9868 6755 China Beijing Tel 86 10 8528 2100 Fax 86 10 8528 2104 China Chengdu Tel 86 28 8665 5511 Fax 86 28 8665 7889 China Fuzhou Tel 86 591 8750 3506 Fax 86 591 8750 3521 China Hong Kong SAR Tel 852 2401 1200 Fax 852 2401 3431 China Qingdao Tel 86 532 8502 7355 Fax 86 532 8502 7205 China Sh
86. T2CKPS1 2 0 000 0000 000 0000 CCPRIL Capture Compare PWM Register1 LSB XXXX uuuu uuuu CCPR1H Capture Compare PWM Register1 MSB XXXX XXXx uuuu uuuu CCP1CON DC1B1 DC1BO CCP1M3 CCP1M2 CCP1M1 00 0000 00 0000 CCPR2L Capture Compare PWM Register2 LSB XXXX uuuu uuuu CCPR2H Capture Compare PWM Register2 MSB XXXX uuuu uuuu CCP2CON DC2B1 DC2BO CCP2M3 CCP2M2 CCP2M1 CCP2MO 00 0000 00 0000 Legend unknown u unchanged unimplemented read as 0 Shaded cells are not used by PWM and Timer2 Note 1 The PSPIF PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices always maintain these bits clear _ u DS39564C page 123 2006 Microchip Technology Inc PIC18FXX2 NOTES DS39564C page 124 2006 Microchip Technology Inc PIC18FXX2 15 0 MASTER SYNCHRONOUS SERIAL PORT MSSP MODULE 15 1 Master SSP MSSP Module Overview The Master Synchronous Serial Port MSSP module is a serial interface useful for communicating with other peripheral or microcontroller devices These peripheral devices may be serial EEPROMs shift registers dis play drivers A D converters etc The MSSP module can operate in one of two modes Serial Peripheral Interface SPI Inter Integrated Circuit Full Master mode Slave mode with general address call The interfac
87. Tel 39 0331 742611 Fax 39 0331 466781 Netherlands Drunen Tel 31 416 690399 Fax 31 416 690340 Spain Madrid Tel 34 91 708 08 90 Fax 34 91 708 08 91 UK Wokingham Tel 44 118 921 5869 Fax 44 118 921 5820 08 29 06 DS39564C page 330 2006 Microchip Technology Inc
88. a 2 TAD wait is required before the next acquisition is started After this 2 TAD wait acquisition on the selected channel is automatically started The GO DONE bit can then be set to start the conversion Note The GO DONE bit should NOT be set in the same instruction that turns on the A D Tcy TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD7 TAD8 TAD9 TAD10 TAD11 bo 08 b7 b6 b5 b4 Conversion Starts Holding capacitor is disconnected from analog input typically 100 ns b3 b2 bl bo bo Set GO bit Next Q4 ADRESH ADRESL is loaded GO bit is cleared ADIF bit is set holding capacitor is connected to analog input 17 4 1 A D RESULT REGISTERS The ADRESH ADRESL register pair is the location where the 10 bit A D result is loaded at the completion of the A D conversion This register pair is 16 bits wide The A D module gives the flexibility to left or right justify the 10 bit result in the 16 bit result register The A D Format Select bit ADFM controls this justification Figure 17 4 shows the operation of the A D result justi fication The extra bits are loaded with 0 s When an A D result will not overwrite these locations A D disable these registers may be used as two general purpose 8 bit registers FIGURE 17 4 A D RESULT J USTIFICATION 10 bit Result ADFM 1 ADFM 0 5 A 7 2107 0 7 0765 0 000000 0000 00 xy ho cr E
89. k lt 4095 Operation k gt FSRf Status Affected None Encoding 1110 1110 00ff k kkk 1111 0000 Description The 12 bit literal k is loaded into the file select register pointed to by Words 2 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal Process Write k MSB Data literal k MSB to FSRfH Decode Read literal Process Write literal k LSB Data k to FSRfL Example LFSR 2 After Instruction FSR2H FSR2L 0x03 Move f Syntax label Operands 0 lt lt 255 de 0 1 0 1 Operation f gt dest Status Affected N Z Encoding 0101 00da ffff Description The contents of register are moved to a destination dependent upon the status of d If d is 0 the result is placed in W If d is 1 the result is placed back in register default Location can be any where in the 256 byte bank If a is 0 the Access Bank will be selected overriding the BSR value If a 1 then the bank will be selected as per the BSR value default Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write W register f Data Example MOVF REG 0 0 Before Instruction REG 0x22 W OxFF After Instruction REG 0x22 W 0x22 2006 Microchip Technology Inc DS39564C page 235 PIC18FXX2 MOVFF Synta
90. 0 0 Before Instruction W 0 17 REG 0x02 After Instruction W OxD9 REG 0x02 2006 Microchip Technology Inc DS39564C page 217 PIC18FXX2 ADDWFC ADD W and Carry bit to f Syntax label ADDWFC fILdl a Operands 0 lt 1 lt 255 0 1 a e 0 1 Operation W f dest Status Affected DC Z Encoding 0010 00da fff Description Add W the Carry Flag and data memory location If d is 0 the result is placed in W If d is 1 the result is placed in data memory loca tion f If a is 0 the Access Bank will be selected If a is 1 the BSR will not be overridden Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example ADDWFC REG 0 Before Instruction Carry bit 1 REG 0x02 W Ox4D After Instruction Carry bit 0 REG 0x02 W 0x50 ANDLW AND literal with W Syntax label ANDIW k Operands 0 lt k lt 255 Operation W AND k gt W Status Affected 2 Encoding 0000 1011 kkkk kkkk Description The contents of W are ANDed with the 8 bit literal k The result is placed in W Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 04 Decode Read literal Process Write to W k Data Example ANDLW 0x5F Before Instruction W After Instruction W 0x03 DS39564C pag
91. 0000 0000 FA7h EECON EEPROM Control Register2 not a physical register mE FA6h EEPGD CFGS FREE WRERR WREN WR RD 0 x000 uu 0 u000 FA2h IPR2 EEIP BCLIP LVDIP TMRSIP CCP2IP 1 1111 1 1111 PIR2 EEIF LVDIF TMRSIF 0 0000 0 0000 FAOh PIE2 EEIE BCLIE LVDIE TMRSIE CCP2IE 0 0000 0 0000 Legend unknown u unchanged r reserved unimplemented read as 0 Shaded cells are not used during FLASH EEPROM access DS39564C page 69 2006 Microchip Technology Inc PIC18FXX2 NOTES DS39564C page 70 2006 Microchip Technology Inc PIC18FXX2 70 8 X 8 HARDWARE MULTIPLIER 7 1 Introduction An 8 x 8 hardware multiplier is included in the ALU of the PIC18FXX2 devices By making the multiply a hardware operation it completes in a single instruction cycle This is an unsigned multiply that gives a 16 bit result The result is stored into the 16 bit product regis ter pair PRODH PRODL The multiplier does not affect any flags in the ALUSTA register Making the 8 x 8 multiplier execute in a single cycle gives the following advantages Higher computational throughput Reduces code size requirements for multiply algorithms The performance increase allows the device to be used in applications previously reserved for Digital Signal Processors Table 7 1 shows a performance comparison between enhanced devices
92. 021 03 04 1081 MIR m i 0861 i i FAAUTA N N 7 OSC2 1 1 X A N Ye PN Internal System Clock OSCCON lt 0 gt 1 1 Tsos i Program Counter 1 PC 2 i X PC 4 Note 1 RC Oscillator mode assumed 2006 Microchip Technology Inc DS39564C page 23 PIC18FXX2 switching currents have been removed SLEEP mode achieves the lowest current consumption of the device only leakage currents Enabling any on chip feature that will operate during SLEEP will increase the current consumed during SLEEP The user can wake from SLEEP through external RESET Watchdog Timer Reset or through an interrupt 2 7 Effects of SLEEP Mode on the On Chip Oscillator When the device executes a SLEEP instruction the on chip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle Q1 state With the oscillator off the OSC1 and OSC2 signals will stop oscillating Since all the transistor TABLE 2 3 OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode 05 OSC2 Pin RC Floating external resistor At logic low should pull high RCIO Floating external resistor Configured as PORTA bit 6 should pull high ECIO Floating Configured as PORTA bit 6 EC Floating At logic low LP XT and HS Feedback inverter disabled at Feedback inverter disabled at gui
93. 2 S o lt o x o Mr 8 28 ds START bit Detect LO STOP bit Detect SCL in Write Collision Detectt Set Reset S WCOL SSPSTAT Collision Clock Arbitration State Counter for end of XMIT RCV Set SSPIF BCLIF Reset ACKSTAT PEN SSPCON2 2006 Microchip Technology Inc DS39564C page 149 PIC18FXX2 15 4 6 1 Master Mode Operation The master device generates all of the serial clock pulses and the START and STOP conditions A trans fer is ended with a STOP condition or with a Repeated START condition Since the Repeated START condi tion is also the beginning of the next serial transfer the 2 bus will not be released In Master Transmitter mode serial data is output through SDA while SCL outputs the serial clock The first byte transmitted contains the slave address of the receiving device 7 bits and the Read Write R W bit In this case the RW bit will be logic 0 Serial data is transmitted 8 bits at a time After each byte is transmit ted an Acknowledge bit is received START and STOP conditions are output to indicate the beginning and the end of a serial transfer In Master Receive mode the first byte transmitted con tains the slave address of the transmitting device 7 bits and the R W bit In this case the R W bit will be logic 1 Thus the first byte transmitted is a 7 bit slave address followe
94. 2006 Microchip Technology Inc DS39564C page 203 PIC18FXX2 19 2 2 WDT POSTSCALER The WDT has a postscaler that can extend the WDT Reset period The postscaler is selected at the time of the device programming by the value written to the CONFIG2H configuration register FIGURE 19 1 WATCHDOG TIMER BLOCK DIAGRAM Timer gt Postscaler 8 Y 8 to 1MUX WDTPS2 WDTPSO WDTEN 21 SWDTEN bit Configuration bit WDT Time out Note WDPS2 WDPSO are bits in register CONFIG2H TABLE 19 2 SUMMARY WATCHDOG TIMER REGISTERS Name Bit7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit1 CONFIG2H WDTPS2 WDTPS2 WDTPSO WDTEN RCON IPEN RI TO PD POR BOR WDTCON SWDTEN Legend Shaded cells are not used by the Watchdog Timer EE O DS39564C page 204 2006 Microchip Technology Inc 2006 Microchip Technology Inc DS39564C page 205 PIC18FXX2 FIGURE 19 2 WAKE UP FROM SLEEP THROUGH INTERRUPT 01102 03104 ail 021 03 04 ail 01 ad Q3 Q4 01 AZ 03104 01 AJ 03104 1 AZ AZ 04 NAY WP EPP NP CLKOM 1 Tost __ w INT pin INTF flag 3 INTCON lt 1 gt Interrupt Latency INTCON lt 7 gt Processor in 1 1 SLEEP 1 1 1 1 1 INSTRUCTION FLOW
95. 3 Many of the general purpose I O pins are multiplexed with one or more peripheral module functions The multiplexing combinations are device dependent M DS39564C page 8 2006 Microchip Technology Inc PIC18FXX2 FIGURE 1 2 PIC18F4X2 BLOCK DIAGRAM Data Bus lt 8 gt ag TT 1 RAO ANO 21 Table Pointer Data Latch RA1 AN1 i 8 8 18 RA2 AN2 VREF up to 4K RAS ANS VREF 21 inc dec logic address reach RA4 TOCKI 7 Address Latch 4 lt RAS ANA SSAVDIN RAG Address Latch 21 PCLATU PCLATH 129 1 Address lt 12 gt up to 2 Mbytes PCU PCH PCL PORTE Program Counter 4X 12 X 4 Data Latch BSR Banko X RBO INTO LFSRO 1 1 31 Level Stack FSR1 RB2 INT2 1 FSR2 12
96. 3 2 OPERATION When initializing the SPI several options need to be specified This is done by programming the appropriate control bits SSPCON1 lt 5 0 gt and SSPSTAT lt 7 6 gt These control bits allow the following to be specified Master mode SCK is the clock output Slave mode 5 15 the clock input Clock Polarity IDLE state of SCK Data input sample phase middle or end of data output time Clock edge output data on rising falling edge of SCK Clock Rate Master mode only Slave Select mode Slave mode only The MSSP consists of a transmit receive Shift Register SSPSR and a buffer register SSPBUF The SSPSR shifts the data in and out of the device MSb first The 55 holds the data that was written to the SSPSR until the received data is ready Once the 8 bits of data have been received that byte is moved to the SSPBUF register Then the buffer full detect bit BF SSPSTAT lt 0 gt and the interrupt flag bit SSPIF are set This double buffering of the received data SSPBUF allows the next byte to start reception before reading the data that was just received Any write to the SSPBUF register during transmission reception of data will be ignored and the write collision detect bit WCOL SSPCON 1 lt 7 gt will be set User software must clear the WCOL bit so that it can be determined if the follow ing write s to the SSPBUF register completed successfully When the ap
97. 4 3 5V 6 8 3 0V 4 2 5V 2 2 0V 0 4 6 8 10 12 14 16 18 20 22 24 26 Fosc MHz 2006 Microchip Technology Inc DS39564C page 289 PIC18FXX2 FIGURE 23 3 TYPICAL IpD vs Fosc OVER HS PLL MODE Typical statistical mean 25 C Maximum mean 30 40 C to 125 C Minimum mean 3o 40 C to 125 C IDD mA 4 5 6 74 8 9 10 Fosc MHz FIGURE 23 4 MAXIMUM vs Fosc OVER HS PLL MODE 20 18 Typical statistical mean 25 C 5 5V Maximum mean 30 40 C to 125 C Minimum mean 3o 40 C to 125 C 16 5 0V 14 4 5V 12 4 2V IDD mA 5 4 5 6 7 8 9 10 Fosc MHz DS39564C page 290 2006 Microchip Technology Inc PIC18FXX2 FIGURE 23 5 TYPICAL vs Fosc OVER XT MODE FIGURE 23 6 MAXIMUM vs Fosc OVER XT MODE 2006 Microchip Technology Inc DS39564C page 291 PIC18FXX2 FIGURE 23 7 TYPICAL vs Fosc OVER LP MODE FIGURE 23 8 MAXIMUM vs Fosc OVER LP MODE DS39564C page 292 2006 Microchip Technology Inc PIC18FXX2 FIGURE 23 9 TYPICAL vs Fosc OVER MODE 16 14 12 10 IDD mA Typical Maximum Minimum
98. DC Characteristics m Sym Characteristic Min Typt Max Units Conditions Internal Program Memory Programming Specifications D110 VPP Voltage on MCLR VPP pin 9 00 1325 V 0113 IDDP Supply Current during 10 mA Programming Data EEPROM Memory 0120 Cell Endurance 100K 1M 40 C to 85 C D121 VDRW VDD for Read Write VMIN 5 5 V Using EECON to read write VMIN Minimum operating voltage D122 TDEW Erase Write Cycle Time 4 ms 0123 TRETD Characteristic Retention 40 Year Provided no other specifications are violated 0124 TREF Number of Total Erase Write 1M 10M 40 C to 85 C Cycles before Refresh Program FLASH Memory 0130 Cell Endurance 10K 100K 40 C to 85 C 0131 VPR VDD for Read VMIN 5 5 V VMIN Minimum operating voltage 0132 VIE for Block Erase 4 5 5 5 V Using ICSP port D132A Viw for Externally Timed Erase 4 5 5 5 V Using ICSP port or Write D132B VPEW VDD Self timed Write VMIN 5 5 V VMIN Minimum operating voltage 0133 TIE ICSP Block Erase Cycle Time 4 ms gt 45 D133A ICSP Erase or Write Cycle Time 1 ms VpD gt 4 5V externally timed D133A TIW Self timed Write Cycle Time 2 ms 0134 TRETD Characteristic Retention 40 Year Provided no other specifications are violated 1 Data in Typ column is at 5 0V 25 C unless otherwise stated These parameters for design g
99. Direct Addressing 0 S Bank Select Location Select Data Memory Note 1 For register file map detail see Table 4 1 registers of the Access Bank J gt 00h 01h OEh OFh 000h 100h FOOh OFFh 1FFh EFFh FFFh Bank 0 Bank 1 Bank 14 Bank 15 2 The access bit of the instruction can be used to force an override of the selected bank BSR lt 3 0 gt to the 3 The MOVFF instruction embeds the entire 12 bit address in the instruction 2006 Microchip Technology Inc DS39564C page 49 PIC18FXX2 4 12 Indirect Addressing INDF and FSR Registers Indirect addressing is a mode of addressing data mem ory where the data memory address in the instruction is not fixed An FSR register is used as a pointer to the data memory location that is to be read or written Since this pointer is in RAM the contents can be modified by the program This can be useful for data tables in the data memory and for software stacks Figure 4 9 shows the operation of indirect addressing This shows the moving of the value to the data memory address specified by the value of the FSR register Indirect addressing is possible by using one of the INDF registers Any instruction using the INDF register actually accesses the register pointed to by the File Select Register FSR Reading the INDF register itself indirectly FSR 0 will read 00h Writing to the INDF register
100. EXAMPLE 9 3 INITIALIZING PORTC CLRF PORTC Initialize PORTC by clearing output data latches CLRF LATC Alternate method to clear output data latches MOVLW Value used to initialize data direction TRISC Set RC lt 3 0 gt as inputs RC 5 4 as outputs RC lt 7 6 gt as inputs FIGURE 9 7 PORTC BLOCK DIAGRAM PERIPHERAL OUTPUT OVERRIDE Port Peripheral 2 SV m Peripheral Data Out LATC 0 Data Data Latch ata Bus D Q P WR LATC or 1 WR PORTC CK 30 yo pin TRIS Latch x 9 0 Q WR TRISC Ck VG 04 N RD TRISC Y V Schmitt Vss Trigger Peripheral Output Enable Q D RD PORTC gt Peripheral Data In Note 1 O pins have diode protection to VDD and Vss 2 Port Peripheral Select signal selects between port data input and peripheral output 3 Peripheral Output Enable is only active if peripheral select is active 2006 Microchip Technology Inc DS39564C page 93 PIC18FXX2 TABLE 9 5 PORTC FUNCTIONS Name Bit Buffer Type Function RCO T1OSO T1CKI bito ST Input output port pin or Timer1 oscillator output Timer1 clock input RC4 T1OSI CCP2 bit1 ST Input output port pin Timer1 oscillator input or Capture2 input Compare2 output PWM output when CCP2MX configuration
101. External Clock Input Synchronization Control bit Not usable if the system clock comes from Timer1 Timer3 When TMR3CS 1 1 Do not synchronize external clock input 0 Synchronize external clock input When TMR3CS 0 This bit is ignored Timer3 uses the internal clock when TMR3CS 0 bit 1 TMR3CS Timer3 Clock Source Select bit 1 External clock input from Timer1 oscillator or T1CKI on the rising edge after the first falling edge 0 Internal clock Fosc 4 bit 0 TMR3ON Timer3 On bit 1 Enables Timer3 0 Stops Timer3 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR Bit is set Bit is cleared Bit is unknown 2006 Microchip Technology Inc DS39564C page 113 PIC18FXX2 13 1 Timer3 Operation Timer3 can operate in one of these modes Asatimer a synchronous counter As an asynchronous counter The Operating mode is determined by the clock select bit TMR3CS T3CON 1 FIGURE 13 1 TIMER3 BLOCK DIAGRAM When TMR3CS 0 Timer3 increments every instruc tion cycle When 1 Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator if enabled When the Timer1 oscillator is enabled TIOSCEN is set the RC1 T1OSI and RCO T1OSO T1CKI pins become inputs That is the TRISC lt 1 0 gt value is ignored and the pins are read as 0 Timers also has an internal RES
102. FSR2 post incremented not a physical register n a 50 POSTDEC2 Uses contents of FSR2 to address data memory value of FSR2 post decremented not a physical register n a 50 PREINC2 Uses contents of FSR2 to address data memory value of FSR2 pre incremented not a physical register n a 50 PLUSW2 Uses contents of FSR2 to address data memory value of FSR2 not a physical register n a 50 Offset by value in WREG FSR2H Indirect Data Memory Address Pointer 2 High Byte 0000 50 FSR2L Indirect Data Memory Address Pointer 2 Low Byte XXXX XXXX 50 STATUS N OV Z DC C X 52 TMROH 0 Register High Byte 0000 0000 105 TMROL TimerO Register Low Byte XXXX XXXX 105 TOCON TMROON TOBBIT TOCS TOSE PSA TOPS2 TOPS1 TOPSO 1111 1111 103 Legend unknown u unchanged unimplemented value depends on condition Note 1 RA6 and associated bits are configured as port pins in and ECIO Oscillator mode only and read 0 in all other Oscillator modes 2 Bit21 of the TBLPTRU allows access to the device configuration bits 3 These registers and bits are reserved on the PIC18F2X2 devices always maintain these clear DS39564C page 46 2006 Microchip Technology Inc PIC18FXX2 TABLE 4 2 REGISTER FILE SUMMARY CONTINUED
103. Flag bit 1 After power up CLRWDT instruction or SLE 0 AWDT time out occurred bit 2 PD Power down Detection Flag bit 1 After power up or by the CLRWDT instruction By execution of the SLEEP instruction bit 1 POR Power on Reset Status bit 1 A Power on Reset has not occurred 0 A Power on Reset occurred EP instruction must be set in software after a Power on Reset occurs bit O BOR Brown out Reset Status bit 1 A Brown out Reset has not occurred 0 A Brown out Reset occurred must be set in software after a Brown out Reset occurs Legend R Readable bit W Writable bit Value at POR 1 Bit is set U Unimplemented bit read as 0 0 Bit is cleared X Bit is unknown 2006 Microchip Technology Inc DS39564C page 53 PIC18FXX2 NOTES DS39564C page 54 2006 Microchip Technology Inc PIC18FXX2 5 0 FLASH PROGRAM MEMORY The FLASH Program Memory is readable writable and erasable during normal operation over the entire range A read from program memory is executed on one byte at a time A write to program memory is executed on blocks of 8 bytes at a time Program memory is erased in blocks of 64 bytes at a time bulk erase operation may not be issued from user code Writing or erasing program memory will cease instruc tion fetches until the operation is complete The pro gram memory cannot be accessed during the write or erase th
104. GPRs can be accessed in a single cycle regardless of the current BSR values an Access Bank is implemented A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM Section 4 10 provides a detailed description of the Access RAM 4 9 1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly or indi rectly Indirect addressing operates using a File Select Register and corresponding Indirect File Operand The operation of indirect addressing is shown in Section 4 12 Enhanced MCU devices may have banked memory in the GPR area GPRs are not initialized by a Power on Reset and are unchanged on all other RESETS Data RAM is available for use as GPR registers by all instructions The top half of Bank 15 OxF80 to OxFFF contains SFRs All other banks of data memory contain GPR registers starting with Bank O 4 9 2 SPECIAL FUNCTION REGISTERS The Special Function Registers SFRs are registers used by the CPU and Peripheral Modules for control ling the desired operation of the device These regis ters are implemented as static RAM A list of these registers is given in Table 4 1 and Table 4 2 The SFRs can be classified into two sets those asso ciated with the core function and those related to the peripheral functions Those registers related to the core are described in this section while those related to the operation of the peripheral features are described in the section of that periphe
105. High priority 0 Low priority Unimplemented Read as 0 INT2IE INT2 External Interrupt Enable bit 1 Enables the INT2 external interrupt 0 Disables the INT2 external interrupt INT1IE INT1 External Interrupt Enable bit 1 Enables the INT1 external interrupt 0 Disables the INT1 external interrupt Unimplemented Read as 0 INT2IF INT2 External Interrupt Flag bit 1 The INT2 external interrupt occurred must be cleared in software The INT2 external interrupt did not occur INT1IF INT1 External Interrupt Flag bit 1 The INT1 external interrupt occurred must be cleared in software 0 The INT1 external interrupt did not occur Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown Note Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt This feature allows for software polling 2006 Microchip Technology Inc DS39564C page 77 PIC18FXX2 8 2 PIR Registers Note 1 Interrupt flag bits are set when an interrupt The PIR registers contain the individual flag bits for the condition occurs regardless of the state of peripheral interrupts Due to the number of peripheral its corresponding enable bit or the
106. INTOIE RBIE TMROIF INTOIF 0000 000 0000 000u GIEL PIR1 PSPIFM ADIF RCIF TXIF SSPIF TMR2IF TMRIIF 0000 0000 0000 0000 PIE PSPIEU ADIE RCIE TXIE SSPIE CCPIIE TMR2IE 0000 0000 0000 0000 IPR1 lt ADIP RCIP TXIP SSPIP CCP1IP TMR2IP 0000 0000 0000 0000 TRISC PORTC Data Direction Register 1111 1111 1111 1111 SSPBUF Synchronous Serial Port Receive Buffer Transmit Register XXXX XXXX uuuu uuuu SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO 0000 0000 0000 0000 TRISA PORTA Data Direction Register 111 1111 111 1111 SSPSTAT SMP CKE D A P 5 RW UA BF 0000 0000 0000 0000 Legend x unknown u unchanged unimplemented read as Shaded cells not used by the MSSP SPI mode Note 1 The PSPIF PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices always maintain these bits clear 2006 Microchip Technology Inc DS39564C page 133 PIC18FXX2 154 Mode The MSSP module in 122 mode fully implements all DS39564C page 134 2006 Microchip Technology Inc PIC18FXX2 REGISTER 15 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit O SSPSTAT MSSP STATUS REGISTER 2 MODE R W 0 R W 0 R 0 R 0 R 0 R 0 R 0 R 0 SMP CKE D A P 5 UA BF bit 7 bit 0 SMP Slew Rate Control bit In Master or Slave mode 1 Slew rate control disabled for Sta
107. If match releases SCL line this will clear bit UA 6 Read the SSPBUF register clears bit BF and clear flag bit SSPIF 7 Receive Repeated START condition 8 Receive first high byte of Address bits SSPIF and BF are set 9 Read the SSPBUF register clears bit BF and clear flag bit SSPIF DS39564C page 138 2006 Microchip Technology Inc PIC18FXX2 15 4 3 2 Reception When the R W bit of the address byte is clear and an address match occurs the R W bit of the SSPSTAT register is cleared The received address is loaded into the SSPBUF register and the SDA line is held low ACK When the address byte overflow condition exists then the no Acknowledge ACK pulse is given An overflow condition is defined as either bit BF SSPSTAT 0 is set or bit SSPOV SSPCON1 lt 6 gt is set An MSSP interrupt is generated for each data transfer byte Flag bit SSPIF PIR1 lt 3 gt must cleared in soft ware The SSPSTAT register is used to determine the status of the byte SEN is enabled SSPCON1 lt 0 gt 1 RC3 SCK SCL will be held low clock stretch following each data trans fer The clock must be released by setting bit CKP SSPCON lt 4 gt See Section 15 4 4 Clock Stretching for more detail 15 4 3 3 Transmission When the R W bit of the incoming address byte is set and an address match occurs the RW bit of the SSPSTAT register is set The received address is loaded into tne SSPBUF register
108. In Circuit Debugger and ICSP programming clock pin RB7 PGD 28 28 RB7 O TTL Digital I O Interrupt on change pin PGD O ST In Circuit Debugger and ICSP programming data pin Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input Output Power OD Open Drain diode to VDD 2006 Microchip Technology Inc DS39564C page 11 PIC18FXX2 TABLE 1 2 PIC18F2X2 PINOUT 1 0 DESCRIPTIONS CONTINUED Pin Number Pin Name Pii cBulfer Description DIP soic Type Type PORTC is a bi directional I O port RCO T1OSO T1CKI 11 11 RCO ST Digital T10SO O 1 oscillator output T1CKI ST Timer1 Timer3 external clock input RC1 T1OSI CCP2 12 12 RC1 ST Digital T1OSI CMOS oscillator input CCP2 O ST Capture2 input Compare2 output PWM2 output RC2 CCP1 13 13 RC2 ST Digital CCP1 O ST Capture input Compare1 output PWM 1 output RC3 SCK SCL 14 14 RC3 ST Digital SOK O ST Synchronous serial clock input output for SPI mode SOL O ST Synchronous serial clock input output for 2 mode RC4 SDI SDA 15 15 RC4 ST Digital SDI ST SPI Data In SDA ST 2 Data RC5 SDO 16 16 RC5 ST Digital SDO O SPI Data Out RC6 TX CK 17 17 RC6 ST Digital TX O USART Asynchronous Transmit CK O ST USART
109. Input Schmitt Trigger Buffer CCP2MX 0 Note 1 has diode protection to and Vss 2 To enable weak pull ups set the appropriate DDR bit s and clear the RBPU bit INTCON2 lt 7 gt 3 The CCP2 input output is multiplexed with RB3 if the CCP2MX bit is enabled 0 in the configuration register 2006 Microchip Technology Inc DS39564C page 91 PIC18FXX2 TABLE 9 3 PORTB FUNCTIONS Name Bit Buffer Function RBO INTO bitO TTL STU Inpu output pin or external interrupt inputo Internal software programmable weak pull up RB1 INT1 bit1 TTL STU Input output pin or external interrupt Internal software programmable weak pull up RB2 INT2 bit2 TTL STU Inpu output pin or external interrupt input2 Internal software programmable weak pull up RB3 CCP26 bit3 TTL ST4 Inpu output pin or Capture2 input Compare2 output PWM output when CCP2MX configuration bit is enabled Internal software programmable weak pull up RB4 bit4 TTL Inpu output pin with interrupt on change Internal software programmable weak pull up RB5 PGM bits TTL ST Inpu output pin with interrupt on change Internal software programmable weak pull up Low voltage ICSP enable pin RB6 PGC bit6 TTL ST Input output pin with interrupt on change Internal software programmable weak pull up Serial programming clock RB7 PGD bit7 TTL STO Inpu output pin with interrupt on change In
110. Input output or analog input RA1 AN1 bit1 TTL Input output or analog input RA2 AN2 VREF bit2 TTL Input output or analog input or VREF RA3 AN3 VREF bit3 TTL Input output or analog input or VREF RA4 TOCKI bit4 ST Input output or external clock input for Output is open drain type RA5 SS AN4 LVDIN bit5 TTL Inpu output or slave select input for synchronous serial port analog input or low voltage detect input OSC2 CLKO RA6 bit6 TTL 5 2 or clock output pin Legend TTL TTL input ST Schmitt Trigger input TABLE 9 2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on Value on Name Bit 7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 POR Other BOR RESETS PORTA 5 4 RA2 RAO x0x 0000 uOu 0000 LATA LATA Data Output Register XXX XXXX uuu uuuu TRISA PORTA Data Direction Register 111 1111 111 1111 ADCON1 ADFM ADCS2 PCFG3 PCFG2 PCFG1 PCFGO 00 0000 00 0000 Legend x unknown u unchanged unimplemented locations read as 0 Shaded cells are not used by PORTA 2006 Microchip Technology Inc DS39564C page 89 PIC18FXX2 9 2 PORTB TRISB and LATB Registers PORTB is an 8 bit wide bi directional port The corre sponding Data Direction register is TRISB Setting a TRISB bit 1 will make the corresponding PORTB pin an input i e put the corresponding output dr
111. Microchip Technology Inc PIC18FXX2 2 0 OSCILLATOR CONFIGURATIONS 21 Oscillator Types The PIC18FXX2 can be operated in eight different Oscillator modes The user can program three configu ration bits FOSC2 FOSC1 and FOSCO to select one of these eight modes 1 LP Low Power Crystal 2 XT Crystal Resonator 3 HS High Speed Crystal Resonator 4 HS PLL High Speed Crystal Resonator with PLL enabled 5 RC External Resistor Capacitor 6 RCIO External Resistor Capacitor with O pin enabled 7 EC External Clock 8 ECIO External Clock with enabled 2 2 Crystal Oscillator Ceramic Resonators In XT LP HS or HS PLL Oscillator modes a crystal ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation Figure 2 1 shows the pin connections The PIC18FXX2 oscillator design requires the use of a parallel cut crystal Note Use of a series cut crystal may give a fre quency out of the crystal manufacturers specifications FIGURE 2 1 CRYSTAL CERAMIC RESONATOR OPERATION HS XT OR LP CONFIGURATION Internal Logic OSC1 XTAL SLEEP PIC18FXXX cat 0862 Note 1 See Table2 1 and Table2 2 for recommended values of C1 and C2 2 A series resistor RS may be required for AT strip cut crystals 3 Rr varies with the Oscillator mode chosen TABLE 2 1 CAPACITOR SEL
112. No Postscaler 32 TOST Oscillation Start up Timer Period 1024 Tosc 1024 Tosc Tosc OSCI period 33 TPWRT Power up Timer Period 28 72 132 ms 34 Hi impedance from MCLR Low 2 us or Watchdog Timer Reset 35 TBOR Brown out Reset Pulse Width 200 mE us lt BVDD see 0005 36 TIVRST Time for Internal Reference 20 500 us Voltage to become stable 37 TLVD Low Voltage Detect Pulse Width 200 us lt VLVD see D420 DS39564C page 274 2006 Microchip Technology Inc PIC18FXX2 FIGURE 22 9 TIMERO AND TIMER1 EXTERNAL CLOCK TIMINGS TOCKI 40 gt lt 41 gt lt a 42 gt T1OSO T1CKI 4 45 gt 46 E 47 48 TMRO or TMR1 Note Refer to Figure 22 4 for load conditions TABLE 22 8 TIMERO AND TIMER1 EXTERNAL CLOCK REQUIREMENTS onn Symbol Characteristic Min Max Units Conditions 40 TtOH TOCKI High Pulse Width No Prescaler 0 5TCY 20 ns With Prescaler 10 ns 41 TtOL TOCKI Low Pulse Width No Prescaler 0 5TCY 20 ns With Prescaler 10 ns 42 Period Prescaler Toy 10 ns With Prescaler Greater of ns prescale 20 ns or Toy 40 value N 1 2 4 256 45 High Synchronous prescaler 0 5T
113. OF A RESET A RESET disables the MSSP module and terminates the current transfer 15 4 16 MULTI MASTER MODE In Multi Master mode the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free The STOP P and START S bits are cleared from a RESET or when the MSSP module is disabled Control of the bus may be taken when the P bit SSPSTAT lt 4 gt is set or the bus is idle with both the S and P bits clear When the bus is busy enabling the SSP interrupt will generate the interrupt when the STOP condition occurs In multi master operation the SDA line must be moni tored for arbitration to see if the signal level is the expected output level This check is performed in hardware with the result placed in the BCLIF bit The states where arbitration can be lost are Address Transfer Data Transfer A START Condition A Repeated START Condition An Acknowledge Condition FIGURE 15 25 15 4 17 MULTI MASTER COMMUNICATION BUS COLLISION AND BUS ARBITRATION Multi Master mode support is achieved by bus arbitra tion When the master outputs address data bits onto the SDA pin arbitration takes place when the master outputs a 1 on SDA by letting SDA float high and another master asserts a 0 When the SCL pin floats high data should be stable If the expected data on SDA is a 1 and the data sampled on the SDA pin 0 then a bus collision has taken p
114. S A Analog for the Digital Age Application Maestro CodeGuard dsPICDEM dsPICDEM net dsPICworks ECAN ECONOMONITOR FanSense FlexROM fuzzyLAB In Circuit Serial Programming ICSP ICEPIC Linear Active Thermistor Mindi MiWi MPASM MPLIB MPLINK PICDEM PICDEM net PICLAB PICtail PowerCal Powerlnfo PowerMate PowerTool REAL ICE rfLAB rfPICDEM Select Mode Smart Serial SmartTel Total Endurance UNI O WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U S A and other countries SQTP is a service mark of Microchip Technology Incorporated in the U S A other trademarks mentioned herein are property of their respective companies 2006 Microchip Technology Incorporated Printed in the U S A All Rights Reserved gt Printed on recycled paper Microchip received ISO TS 16949 2002 certification for its worldwide headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona Gresham Oregon and Mountain View California The Company s quality system processes and procedures are for its 8 bit MCUs code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchip s quality system for the design and manufacture of development systems is 150 9001 2000 certified DS39564C page ii 2006 Microchip Technology Inc MICROCHIP High Performance RISC CPU
115. TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 0000 010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend x unknown unimplemented read as 0 Shaded cells are not used for Synchronous Slave Reception Notel The PSPIF PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices always maintain these bits clear DS39564C page 180 2006 Microchip Technology PIC18FXX2 17 0 COMPATIBLE 10 BIT The A D module has four registers These registers ANALOG TO DIGITAL CONVERTER A D MODULE A D Result High Register ADRESH 27 A D Result Low Register ADRESL The Analogo Digia A convener module a Ne AD Coni Register o ADCOND PIC18F4X2 devices This module has the ADCONO and ADCONI register definitions that are compatible The ADCONO register shown in Register 17 1 con with the mid range A D module trols the operation of the A D module The ADCON1 register shown in Register 17 2 configures the Th D allows conversion of an analog input signal t 1 PAD allows conversion oran anabo input signala functions of the port pins a corresponding 10 bit digital number REGISTER 17 1 ADCONO REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 U 0 R W 0 ADCS1 ADCSO CHS2 CHS1 CHSO GO DONE ADON bit 7 bit 0 bit7 6 ADCSI ADCSO A D Conversion Clock Select bits ADCONO bits in bol
116. Write AAh to EECON2 Set the WR bit This will begin the write cycle CPU will stall for duration of write approximately 2 ms using internal timer 9 Execute a 10 Re enable interrupts NOO 2006 Microchip Technology Inc DS39564C page 195 PIC18FXX2 TABLE 19 1 CONFIGURATION BITS AND DEVICE IDS Default File Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO Unprogrammed Value 300001h CONFIG1H OSCSEN FOSC2 FOSCi FOSCO 1 111 300002h CONFIG2L BORV1 BORVO BOREN PWRTEN 1111 300003h CONFIG2H WDTPS2 WDTPS1 WDTPSO WDTEN 111 300005h CONFIG3H CCP2MX 1 300006h CONFIG4L DEBUG LVP STVREN 1 1 1 300008h CONFIGSL CP3 CP2 CP1 CPO 1111 300009h CONFIG5H CPD CPB 11 30000Ah CONFIGGL WRT3 WRT2 1111 30000Bh CONFIG6H WRTD WRTB WRTC Lire 30000Ch CONFIG7L EBTR3 EBTR2 EBTR1 EBTRO 1111 30000Dh CONFIG7H EBTRB 1 SFFFFEh DEVID1 DEV2 DEV1 DEVO REV4 REV3 REV2 REV1 REVO 1 SFFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 0100 Legend x unknown u unchanged unimplemented value depends on condition Shaded cells are unimplemented read as 0
117. XOR f dest Status Affected N Z Encoding 0001 10da ffff Description Exclusive OR the contents of W with register f If d is 0 the result is stored in W If d is 1 the result is stored back in the register default If a is 0 the Access Bank will be selected overriding the BSR value If a is 1 then the bank will be selected as per the BSR value default Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register Data destination Example XORWF 1 0 Before Instruction REG OxAF W 0 5 After Instruction REG 1 W 0 5 DS39564C page 252 2006 Microchip Technology Inc PIC18FXX2 21 0 DEVELOPMENT SUPPORT The PlCmicro microcontrollers are supported with a full range of hardware and software development tools Integrated Development Environment MPLAB IDE Software Assemblers Compilers Linkers MPASM Assembler MPLAB C17 and MPLAB C18 C Compilers MPLINK Object Linker MPLIB Object Librarian Simulators MPLAB SIM Software Simulator Emulators MPLAB ICE 2000 In Circuit Emulator ICEPIC In Circuit Emulator In Circuit Debugger MPLAB ICD Device Programmers PRO MATE II Universal Device Programmer PICSTART Plus Entry Level Development Programmer Low Cost Demonstration Boards PICDEM 1 Demonstration Board PICDEM 2 Demonstration Boa
118. XXXX XXXX uuuu uuuu uuuu uuuu 242 442 252 452 00 0000 00 0000 uu uuuu CCPR2H 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu CCPR2L 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu CCP2CON 242 442 252 452 00 0000 00 0000 uu uuuu TMR3H 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu TMR3L 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu 242 442 252 452 0000 0000 uuuu uuuu uuuu uuuu SPBRG 242 442 252 452 0000 0000 0000 0000 uuuu uuuu RCREG 242 442 252 452 0000 0000 0000 0000 uuuu uuuu TXREG 242 442 252 452 0000 0000 0000 0000 uuuu uuuu TXSTA 242 442 252 452 0000 010 0000 010 uuuu uuu RCSTA 242 442 252 452 0000 000x 0000 000x uuuu uuuu EEADR 242 442 252 452 0000 0000 0000 0000 uuuu uuuu EEDATA 242 442 252 452 0000 0000 0000 0000 uuuu uuuu 1 242 442 252 452 0 000 uu 0 0000 uu 0 1000 2 242 442 252 452 Legend u unchanged x unknown unimplemented bit read as g value depends on condition Shaded cells indicate conditions do not apply for the designated device Note 1 One or more bits in the INTCONX or PIRx registers will be affected to cause wake up 2 When the wake up is due to an interrupt and the GIEL or GIEH bit is set the PC is loaded with the interrupt vector 0008h or 00185 3 When the wake up is due to an interrupt and the GIEL or GIEH b
119. a single byte the TBLWT instruction has to be executed 8 times for each programming operation All of the Table Write operations will essentially be short writes because only the holding registers are written At the end of updating 8 registers the EECON 1 register must be written to to start the programming operation with a long write The long write is necessary for programming the inter nal FLASH Instruction execution is halted while in a long write cycle The long write will be terminated by the internal programming timer The EEPROM on chip timer controls the write time The write erase voltages are generated by an on chip charge pump rated to operate over the voltage range of the device for byte or word operations FIGURE 5 5 TABLE WRITES TO FLASH PROGRAM MEMORY Write Register TABLAT TBLPTR xxxxx0 TBLPTR 1 TBLPTR xxxxx2 TBLPTR xxxxx7 Holding Register Holding Register Holding Register Holding Register IVA V Program Memory 5 5 1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be 1 Read 64 bytes into RAM Update data values in RAM as necessary Load Table Pointer with address being erased Do the row erase procedure Load Table Pointer with address of first byte being written 6 Write the first 8 bytes into the holding registe
120. all 12 bits That is when FSRnL overflows from an increment FSRnH will be incremented automatically Adding these features allows the FSRn to be used as a stack pointer in addition to its uses for table operations in data memory Each FSR has an address associated with it that per forms an indexed indirect access When a data access to this INDFn location PLUSWn occurs the FSRn is configured to add the signed value in the WREG regis ter and the value in FSR to form the address before an indirect access The FSR value is not changed If an FSR register contains a value that points to one of the INDFn an indirect read will read OOh zero bit is set while an indirect write will be equivalent to a NOP STATUS bits are not affected If an indirect addressing operation is done where the target address is an FSRnH or FSRnL register the write operation will dominate over the pre or post increment decrement functions DS39564C page 50 2006 Microchip Technology Inc PIC18FXX2 FIGURE 4 9 INDIRECT ADDRESSING OPERATION RAM on Instruction Executed Opcode Address FFFh 12 File Address access of an indirect addressing register BSR lt 3 0 gt Instruction Fetched Opcode File FSR FIGURE 4 10 INDIRECT ADDRESSING 11 FSR Register Indirect Addressing Location Select Note 1 For re
121. and SCL Interrupt cleared in software RSEN S 0 SSPIF DS39564C page 162 2006 Microchip Technology Inc PIC18FXX2 15 4 17 3 Bus Collision During a STOP Condition Bus collision occurs during a STOP condition if a After the SDA pin has been de asserted and allowed to float high SDA is sampled low after the BRG has timed out b After the SCL pin is de asserted SCL is sampled low before SDA goes high The STOP condition begins with SDA asserted low When SDA is sampled low the SCL pin is allowed to float When the pin is sampled high clock arbitration the baud rate generator is loaded with SSPADD lt 6 0 gt and counts down to 0 After the BRG times out SDA is sampled If SDA is sampled low a bus collision has occurred This is due to another master attempting to drive a data Figure 15 31 If the SCL pin is sampled low before SDA is allowed to float high a bus collision occurs This is another case of another master attempting to drive a data Figure 15 32 FIGURE 15 31 BUS COLLISION DURING A STOP CONDITION CASE 1 TBRG TBRG SDA sampled low after TBRG P Set BCLIF SDA SDA asserted low SCL PEN W Q m FIGURE 15 32 BUS COLLISION DURING A STOP CONDITION CASE 2 TBRG SDA N TBRG Assert SDA SCL goes low before SDA goes high PE BCLIF SCL PEN BCLIF P SSPIF O
122. as WDT Timer1 Oscillator BOR For RC osc configuration current through REXT is not included The current through the resistor can be estimated by the formula Ir VDD 2REXT mA with REXT in kOhm The LVD and BOR modules share a large portion of circuitry The AIBOR and AILVD currents are not additive Once one of these modules is enabled the other may also be enabled without further penalty DS39564C page 264 2006 Microchip Technology Inc PIC18FXX2 22 2 DC Characteristics PIC18FXX2 Industrial Extended PIC18LFXX2 Industrial Standard Operating Conditions unless otherwise stated DC CHARACTERISTICS Operating temperature 40 C lt TA lt 85 C for industrial 40 C lt TA lt 125 C for extended E Symbol Characteristic Min Max Units Conditions VIL Input Low Voltage ports DO30 with TTL buffer Vss 0 15 VDD V VDD lt 4 5V D030A 0 8 V 14 5 lt VDD lt 5 5 0031 with Schmitt Trigger buffer Vss 0 2 V RC3 and RC4 Vss 0 3 VDD V D032 MCLR Vss 0 2 V DO32A OSC1 in XT HS and LP modes Vss 0 3 V and T1OSI D033 OSCI in RC and EC 55 0 2 V VIH Input High Voltage ports DO40 with TTL buffer 0 25 VDD VDD V VpD lt 4 5V 0 8V DO40A 2 0 VDD V 14 5 lt VDD lt 5 5 0041 with Schmitt Trigger buffer 0 8 VDD V RC3 and RC4 0 7 VDD VDD V D042 MCLR OSC1 EC mode 0 8 VDD VDD V D042A OSC1 in XT HS and LP modes 0 7 VDD VDD V and
123. be cleared and clock stretching will not occur 2 The CKP bit can be set in software regardless of the state of the BF bit The user should be careful to clear the BF bit in the ISR before the next receive sequence in order to prevent an overflow condition 15 4 4 2 Clock Stretching for 10 bit Slave Receive Mode SEN 1 In 10 bit Slave Receive mode during the address sequence clock stretching automatically takes place but CKP is not cleared During this time if the UA bit is set after the ninth clock clock stretching is initiated The UA bit is set after receiving the upper byte of the 10 bit address and following the receive of the second byte of the 10 bit address with the R W bit cleared to 0 The release of the clock line occurs upon updating SSPADD Clock stretching will occur on each data receive sequence as described in 7 bit mode updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasn t cleared the BF bit by read ing the SSPBUF register before that time then the CKP bit will still NOT be asserted low Clock stretching on the basis of the state of the BF bit only occurs during a data sequence not an address sequence Note If the user polls the UA bit and clears it by 15 4 4 8 Clock Stretching for 7 bit Slave Transmit Mode 7 bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock i
124. before SDA is asserted low This may indicate that another master is attempting to transmit a data 1 FIGURE 15 20 REPEAT START CONDITION WAVEFORM Write to SSPCON2 Set S SSPSTAT lt 3 gt occurs here E zh At completion of START bit SDA 1 ser hardware clear RSEN bit SCL no change and set SSPIF TBRG gt k TBRG gt TBRG 1st bit SDA Falling edge of ninth clock Write to SSPBUF occurs here End of Xmit Tena SCL ITBRG gt Sr Repeated START DS39564C page 154 2006 Microchip Technology Inc PIC18FXX2 15 4 10 MASTER TRANSMISSION Transmission of a data byte a 7 bit address or the other half of a 10 bit address is accomplished by simply writing a value to the SSPBUF register This action will set the buffer full flag bit BF and allow the baud rate generator to begin counting and start the next transmis sion Each bit of address data will be shifted out onto the SDA pin after the falling edge of SCL is asserted see data hold time specification parameter 106 SCL is held low for one baud rate generator rollover count TBRG Data should be valid before SCL is released high see data setup time specification parameter 107 When the SCL pin is released high it is held that way for TBRG The data on the SDA pin must remain stable for that duration and some hold time after the next fall ing edge of SCL After the eighth bit is shifted
125. bit 1 Enables the TMRO overflow interrupt 0 Disables the TMRO overflow interrupt INTOIE INTO External Interrupt Enable bit 1 Enables the INTO external interrupt Disables the INTO external interrupt RBIE RB Port Change Interrupt Enable bit 1 Enables the RB port change interrupt 0 Disables the RB port change interrupt TMROIF TMRO Overflow Interrupt Flag bit 1 TMRO register has overflowed must be cleared in software 0 TMRO register did not overflow INTOIF INTO External Interrupt Flag bit 1 The INTO external interrupt occurred must be cleared in software The INTO external interrupt did not occur RBIF RB Port Change Interrupt Flag bit 1 At least one of the RB7 RB4 pins changed state must be cleared in software 0 None of the RB7 RB4 pins have changed state Note mismatch condition will continue to set this bit Reading PORTB will end the mismatch condition and allow the bit to be cleared Legend R Readable bit W Writable bit U Unimplemented bit read as Value at POR 1 Bitis set Bit is cleared x Bit is unknown 2006 Microchip Technology Inc DS39564C page 75 PIC18FXX2 REGISTER 8 2 INTCON2 REGISTER R W 1 R W 1 R W 1 R W 1 U 0 R W 1 U 0 R W 1 RBPU INTEDGO INTEDG1 INTEDG2 TMROIP RBIP bit 7 bit 0 bit 7 RBPU Pull up Enable bit 1 All PORTB pull ups are disabled PORTB pull ups are enabled by individual port latch
126. bit conditions Once Master mode is enabled the user has six options 1 Assert a START condition on SDA and SCL 2 Assert a Repeated START condition on SDA and SCL 3 Write to the SSPBUF transmission of data address 4 Configure the port to data 5 Generate an Acknowledge condition at the end of a received byte of data 6 Generate a STOP condition on SDA and SCL register initiating The MSSP Module when configured in Master mode does not allow queueing of events For instance the user is not allowed to initiate a START condition and immediately write the SSPBUF register to initiate transmission before the START condition is complete In this case the SSPBUF will not be written to and the WCOL bit will be set indicating that a write to the SSPBUF did not occur Note The following events will cause SSP interrupt flag bit SSPIF to be set SSP interrupt if enabled START condition STOP condition Data transfer byte transmitted received Acknowledge Transmit Repeated START FIGURE 15 16 MSSP BLOCK DIAGRAM c MASTER MODE Internal SSPM3 SSPMO Data Bus SSPADD lt 6 0 gt Read Write SSPBUF Baud Rate Generator SDA Shift o 818 Als 3 ZA 5 START bit STOP bit 5 8 g Acknowledge 15 Generate x
127. generally applicable to all mid range to enhanced device migrations This Application Note is available as Literature Number DS00716 APPENDIX F MIGRATION FROM HIGH END TO ENHANCED DEVICES A detailed discussion of the migration pathway and dif ferences between the high end MCU devices i e PIC17CXXX and the enhanced devices ie PIC18FXXX is provided in AN726 PIC17CXXX to PIC18FXXX Migration This Application Note is available as Literature Number DS00726 2006 Microchip Technology Inc DS39564C page 315 PIC18FXX2 NOTES DS39564C page 316 2006 Microchip Technology Inc PIC18FXX2 INDEX A UPC 181 A D Converter Flag ADIF Bit 183 A D Converter Interrupt Configuring 184 Acquisition Requirements m ADCONO Register sese ADCONI Register 2 42422 ADRESH Register ADRESH ADRESL Registers 183 ADRESL Register Analog Port Pins Analog Port Pins Configuring 186 Associated Registers 188 Configuring the Module 184 Conversion Clock TAD 186 Conversion Status GO DONE Bit 183 5 nnn rre nr ira e 187 Converter Characteristics 287 Eq
128. however a 1 is sampled the SDA pin the SDA pin is asserted low at the end of the BRG count The baud rate generator is then reloaded and counts down to 0 and during this time if the SCL pins are sampled as 0 a bus collision does not occur At the end of the BRG count the SCL pin is asserted low Note Thereason that bus collision is not a factor during a START condition is that no two bus masters can assert a START condition at the exact same time Therefore one master will always assert SDA before the other This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address follow ing the START condition If the address is the same arbitration must be allowed to continue into the data portion Repeated START or STOP conditions BUS COLLISION DURING START CONDITION SDA ONLY Set BCLIF SDA 0 SCL 1 SDA goes low before the SEN bit is set S bit and SSPIF set because SDA N V SEN cleared automatically because of bus collision SSP module reset into IDLE state M 55 and BCLIF are cleared in software SCL Set SEN enable START Ses condition if SDA 1 SCL 1 SEN SDA sampled low before START condition Set BCLIF S bit and SSPIF set because BCLIF SDA 0 SCL 1 S SSPIF SSPIF and BCLIF are cleared in software DS39564C page 160 2006 Mi
129. i PC X PC X PCR X X X PC 4 X 0008 X 00038 pasttuction finst PC SLEEP Ins PC 2 Inst PC 4 Inst 0008h Inst 000Ah Instruction inst PC 1 SLEEP Inst PC 2 Dummy Cycle Dummy Cycle Inst 0008h Note 1 XT HSorLP Oscillator mode assumed 2 1 assumed In this case after wake up the processor jumps to the interrupt routine If GIE execution will continue in line 3 Tost 1024 Tosc drawing not to scale This delay will not occur for RC and EC Osc modes 4 CLKO is not available in these Osc modes but shown here for timing reference DS39564C page 206 2006 Microchip Technology Inc PIC18FXX2 19 4 Program Verification and Code Protection The overall structure of the code protection on the PIC18 FLASH devices differs significantly from other PICmicro devices The user program memory is divided into five blocks One of these is a boot block of 512 bytes The remain der of the memory is divided into four blocks on binary boundaries Each of the five blocks has three code protection bits associated with them They are Code Protect bit CPn Write Protect bit WRTn External Block Table Read bit EBTRn Figure 19 3 shows the program memory organization for 16 and 32 Kbyte devices and the specific code protection bit associated with each block The actual locations of the bits are summarized in Table 19 3
130. identical to that of CCP2 with the exception of the special event trigger Therefore operation of a CCP module in the following sections is described with respect to CCP1 Table 14 2 shows the interaction of the CCP modules REGISTER 14 1 CCPICON REGISTER CCP2CON REGISTER U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 DCxB1 bit 7 bit 7 6 Unimplemented Read as 0 DCxBO CCPxM2 CCPxM1 CCPXMO bit O bit 5 4 DCxB1 DCxBO PWM Duty Cycle bit1 and bitO Capture mode Unused Compare mode Unused PWM mode These bits are the two LSbs bit1 and bitO of the 10 bit PWM duty cycle The upper eight bits DCx9 DCx2 of the duty cycle are found in CCPRxL bit 30 3 Mode Select bits 0000 Capture Compare PWM disabled resets CCPx module 0001 Reserved 0010 Compare mode toggle output on match bit is set 0011 Reserved 0100 Capture mode every falling edge 0101 Capture mode every rising edge 0110 Capture mode every 4th rising edge 0111 Capture mode every 16th rising edge 1000 Compare mode Initialize CCP pin Low on compare match force CCP pin High CCPIF bit is set 1001 Compare mode Initialize CCP pin High on compare match force CCP pin Low CCPIF bit is set 1010 Compare mode Generate software interrupt on compare match CCPIF bit is set CCP pin is unaffected 1011 Compare mode Trigger special
131. in the PIR2 register is set when the write is complete It must be cleared in software DS39564C page 56 2006 Microchip Technology Inc PIC18FXX2 REGISTER 5 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 REGISTER ADDRESS FA6h R W x R W x U 0 R W 0 R W x R W 0 R S 0 R S 0 EEPGD CFGS FREE WRERR WREN WR RD bit 7 bit 0 EEPGD FLASH Program or Data EEPROM Memory Select bit 1 Access FLASH Program memory 0 Access Data EEPROM memory CFGS FLASH Program Data EE or Configuration Select bit 1 Access Configuration registers Access FLASH Program Data EEPROM memory Unimplemented Read as FREE FLASH Row Erase Enable bit 1 Erase the program memory row addressed by TBLPTR on the next WR command cleared by completion of erase operation 0 Perform write only WRERR FLASH Program Data EE Error Flag bit 1 write operation is prematurely terminated any RESET during self timed programming in normal operation 0 The write operation completed Note When a WRERR occurs the EEPGD and CFGS bits are not cleared This allows tracing of the error condition WREN FLASH Program Data EE Write Enable bit 1 Allows write cycles 0 Inhibits write to the EEPROM WR Write Control bit 1 Initiates a data EEPROM erase write cycle or a program memory erase cycle or write cycle The operation is self timed and the bit is cleared by h
132. indirectly results in a no operation The FSR register contains a 12 bit address which is shown in Figure 4 10 The INDFn register is not a physical register Address ing INDFn actually addresses the register whose address is contained in the FSRn register FSRn is a pointer This is indirect addressing Example 4 4 shows a simple use of indirect addressing to clear the RAM in Bank1 locations 100h 1FFh in a minimum number of instructions EXAMPLE 4 4 HOW TO CLEAR RAM BANK1 USING INDIRECT ADDRESSING LFSR FSRO 0x100 NEXT CLRF POSTINCO Clear INDF register and inc pointer BTFSS FSROH 1 All done with Bank1 GOTO NEXT NO clear next CONTINUE YES continue There are three indirect addressing registers To address the entire data memory space 4096 bytes these registers are 12 bit wide To store the 12 bits of addressing information two 8 bit registers required These indirect addressing registers are 1 FSRO composed of FSROH FSROL 2 FSR1 composed of FSR1H FSR1L 3 FSR2 composed of FSR2H FSR2L In addition there are registers INDFO INDF1 and INDF2 which are not physically implemented Reading or writing to these registers activates indirect address ing with the value in the corresponding FSR register being the address of the data If an instruction writes a value to INDFO the value will be written to the address pointed to by FSROH FSROL A read from INDF1 reads the d
133. interrupt PWM Capture None PWM Compare DS39564C page 118 2006 Microchip Technology Inc PIC18FXX2 2006 Microchip Technology Inc DS39564C page 119 PIC18FXX2 144 Compare Mode In Compare mode the 16 bit CCPR1 CCPR2 register value is constantly compared against either the TMR1 register pair value or the TMRS register pair value When a match occurs the RC2 CCP1 RC1 CCP2 pin is driven High driven Low toggle output High to Low or Low to High remains unchanged The action on the pin is based on the value of control bits CCP1M3 CCP1MO CCP2M3 CCP2M0 At the same time interrupt flag bit CCP1IF CCP2IF is set 14 4 1 CCP PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the appropriate TRISC bit Note Clearing the CCP1CON register will force the RC2 CCP1 compare output latch to the default low level This is not the PORTC I O data latch FIGURE 14 2 COMPARE MODE OPERATION BLOCK DIAGRAM 14 4 2 TIMER1 TIMER3 MODE SELECTION and or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature In Asynchronous Counter mode the compare operation may not work 14 4 8 SOFTWARE INTERRUPT MODE When generate software interrupt is chosen the CCP1 pin is not affected Only a CCP interrupt is generated if enabled 14 4 4 SPECIAL EVENT TRIGGER In this mode
134. is lost Overflow can only occur in Slave mode The user must read the SSPBUF even if only transmitting data to avoid setting overflow must be cleared in software 0 No overflow Note In Master mode the overflow bit is not set since each new reception and transmission is initiated by writing to the SSPBUF register bit 5 SSPEN Synchronous Serial Port Enable bit 1 Enables serial port and configures SCK SDO SDI and SS as serial port pins Disables serial port and configures these pins as port pins Note When enabled these pins must be properly configured as input or output bit 4 CKP Clock Polarity Select bit 1 IDLE state for clock is a high level IDLE state for clock is a low level bit 3 0 SSPM3 SSPMO Synchronous Serial Port Mode Select bits 0101 SPI Slave mode clock SCK pin SS pin control disabled SS can be used as I O pin 0100 SPI Slave mode clock SCK pin SS pin control enabled 0011 SPI Master mode clock TMR2 output 2 0010 SPI Master mode clock Fosc 64 0001 SPI Master mode clock Fosc 16 0000 SPI Master mode clock Fosc 4 Note Bit combinations not specifically listed here are either reserved or implemented in mode only Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2006 Microchip Technology Inc DS39564C page 127 PIC18FXX2 15
135. or after a recovery from SLEEP mode External Clock Input In the EC Oscillator mode the oscillator frequency divided by 4 is available on the OSC2 pin This signal may be used for test purposes or to synchronize other logic Figure 2 4 shows the pin connections for the EC Oscillator mode FIGURE 2 4 EXTERNAL CLOCK INPUT OPERATION EC CONFIGURATION OSC1 PIC18FXXX OSC2 Clock from Ext System Fosc 4 The ECIO Oscillator mode functions like the EC mode except that the OSC2 pin becomes an additional gen eral purpose pin The pin becomes bit 6 of PORTA RA6 Figure 2 5 shows the pin connections for the ECIO Oscillator mode FIGURE 2 5 EXTERNAL CLOCK INPUT OPERATION ECIO CONFIGURATION Clock from OSC1 Ext System PIC18FXXX RAG OSC2 2 5 HS PLL A Phase Locked Loop circuit is provided as a program mable option for users that want to multiply the fre guency of the incoming crystal oscillator signal by 4 For an input clock frequency of 10 MHz the internal clock freguency will be multiplied to 40 MHz This is useful for customers who are concerned with EMI due to high freguency crystals The PLL can only be enabled when the oscillator con figuration bits are programmed for HS mode If they are programmed for any other mode the PLL is not enabled and the system clock will come directly from OSC1 The PLL is one of the modes of the FOSC lt 2 0 gt config uration bi
136. out the falling edge of the eighth clock the BF flag is cleared and the master releases SDA This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred or if data was received properly The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock If the master receives an Acknowledge the Acknowledge status bit ACKSTAT is cleared If not the bit is set After the ninth clock the SSPIF bit is set and the master clock baud rate generator is sus pended until the next data byte is loaded into the SSPBUF leaving SCL low and SDA unchanged Figure 15 21 After the write to the SSPBUF each bit of address will be shifted out on the falling edge of SCL until all seven address bits and the R W bit are completed On the fall ing edge of the eighth clock the master will de assert the SDA pin allowing the slave to respond with an Acknowledge On the falling edge of the ninth clock the master will sample the SDA pin to see if the address was recognized by a slave The status of the ACK bit is loaded into the ACKSTAT status bit SSPCON2 lt 6 gt Following the falling edge of the ninth clock transmis sion of the address the SSPIF is set the BF flag is cleared and the baud rate generator is turned off until another write to the SSPBUF takes place holding SCL low and allowing SDA to float 15 4 10 1 Status In Transmit mode the BF
137. placed in register default If a is 0 the Access Bank will be selected overriding the BSR value If a is 1 then the bank will be selected as per the BSR value default Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example SWAPF REG 1 0 Before Instruction REG 0x53 After Instruction REG 0x35 DS39564C page 248 2006 Microchip Technology Inc PIC18FXX2 TBLRD Table Read Syntax label TBLRD Operands None Operation if TBLRD Prog TBLPTR TBLPTR Change if TBLRD Prog TBLPTR TBLPTR 1 TBLPTR if TBLRD TBLPTR TBLPTR 1 if TBLRD TBLPTR 1 TBLPTR TBLPTR Status Affected None Encoding 0000 0000 0000 10nn Description This instruction is used to read the con tents of Program Memory P M To address the program memory a pointer called Table Pointer TBLPTR is used The TBLPTR a 21 bit pointer points to each byte in the program memory TBLPTR has a 2 Mbyte address range TBLPTR 0 0 Least Significant Byte of Program Memory Word TBLPTR 0 1 Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows no change po
138. selected overriding the BSR value If a 1 then the bank will be selected as per the BSR value default Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 04 Decode Read Process Write to register Data destination Example COMF REG 0 0 Before Instruction REG 0x13 After Instruction REG 0x13 W OxEC CPFSEO Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Compare f with W skip if f W label CPFSEQ fla 0 lt 1 lt 255 a e 0 1 f W skip if f W unsigned comparison None 0110 001a Compares the contents of data memory location to the contents of W by performing an unsigned subtraction If then the fetched instruc tion is discarded and a NOP is exe cuted instead making this a two cycle instruction If a is 0 the Access Bank will be selected over riding the BSR value If 1 then the bank will be selected as per the BSR value default 1 1 2 Note 3 cycles if skip and followed by a 2 word instruction Q1 Q2 Q3 Q4 Decode Read Process No register Data operation If skip Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2 word instruction Q1 No operation No operation Example Q2 Q3 Q4 No No No operation operation operation No No No operation operation operat
139. stored back in register default If a is 0 the Access Bank will be selected overriding the BSR value If a is 1 then the bank will be selected as per the BSR value default 1 register f 4 Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example RLNCF REG 1 0 Before Instruction REG 1010 1011 After Instruction REG 0101 0111 RRCF Rotate Right f through Carry Syntax label RRCF f d a Operands 0 lt 1 lt 255 d e 0 1 a e 0 1 Operation f lt n gt gt dest lt n 1 gt f lt O gt gt 3 dest lt 7 gt Status Affected N Z Encoding 0011 ffff Description The contents of register f are rotated one bit to the right through the Carry Flag If d is 0 the result is placed in W If d is 1 the result is placed back in register default If a is 0 the Access Bank will be selected overriding the BSR value If a is 1 then the bank will be selected as per the BSR value default Ee ds Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example RRCF REG 0 0 Before Instruction REG 1110 0110 C 0 After Instruction REG 1110 0110 W 0111 0011 C 0 DS39564C page 244 2006 Microchip Technology Inc PIC18FXX2 RRNCF Rotate Right f
140. the address to match and the UA bit is set SSPSTAT lt 1 gt If the general call address is sampled when the GCEN bit is set while the slave is configured in 10 bit Address mode then the second half of the address is not necessary the UA bit will not be set and the slave will begin receiving data after the Acknowledge Figure 15 15 SLAVE MODE GENERAL CALL ADDRESS SEQUENCE 7 OR 10 BIT ADDRESS MODE Address is compared to General Call Address after ACK set interrupt 7 Y De X D5 D4 X D3 X D2XD1 X DON SSPIF A AA AAA AAA AA AAA AAA f SSPOV SSPCON1 lt 6 gt BF SSPSTAT lt 0 gt 4L_ Cleared in software SSPBUF is read GCEN SSPCON2 lt 7 gt DS39564C page 148 2006 Microchip Technology Inc PIC18FXX2 15 4 6 MASTER MODE Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit In Master mode the SCL and SDA lines are manipulated by the MSSP hardware Master mode of operation is supported by interrupt generation on the detection of the START and STOP conditions The STOP P and START S bits are cleared from a RESET or when the MSSP module is disabled Control of the IC bus may be taken when the P bit is set or the bus is IDLE with both the 5 and P bits clear In Firmware Controlled Master mode user code con ducts all IC bus operations based on START and STOP
141. the next com mand When the buffer is read by the CPU the BF flag bit is automatically cleared The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge sequence enable bit SSPCON2 4 15 4 11 1 BF Status Flag In receive operation the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR It is cleared when the SSPBUF register is read 15 4 11 2 SSPOV Status Flag In receive operation the SSPOV bit is set when 8 bits are received into the SSPSR and the BF flag bit is already set from a previous reception 15 4 11 3 WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress i e SSPSR is still shifting in a data byte the WCOL bit is set and the contents of the buffer are unchanged the write doesn t occur 2006 Microchip Technology Inc DS39564C page 155 PIC18FXX2 12C MASTER MODE WAVEFORM TRANSMISSION 7 OR 10 BIT ADDRESS FIGURE 15 21 _ NAS uonipuoo 1HVLS Jeu ealo ui uenuM SI Jngdss TI BUNA eie jos Y 1 0 1 1 1 1 1 409955 1 N3d N3S lt 0 gt 1VLSdSS 44 ui 1 41455 spuodsei eum PISU 128 4 5 PENNE A TA
142. the prescaler count but will not change the prescaler assignment TABLE 10 1 REGISTERS ASSOCIATED WITH TIMERO Walden Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O POR BOR Other d RESETS TMROL TimerO Module Low Byte Register XXXX XXXX uuuu uuuu TMROH TimerO Module High Byte Register 0000 0000 0000 0000 INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 000x 0000 000u TOCON TMROON TOCS TOSE PSA TOPS2 TOPS1 TOPSO 1111 1111 1111 1111 TRISA PORTA Data Direction Register 111 1111 111 1111 Legend x unknown u unchanged unimplemented locations read as 0 Shaded cells are not used by 2006 Microchip Technology Inc DS39564C page 105 PIC18FXX2 NOTES DS39564C page 106 2006 Microchip Technology Inc PIC18FXX2 11 0 TIMER1 MODULE Figure 11 1 is a simplified block diagram of the Timer1 The Timer1 module timer counter has the following module Register 11 1 details the Timer1 control register This features register controls the Operating mode of the Timer1 16 bit timer counter module and contains the Timer1 oscillator enable bit two 8 bit registers TMR1H and TMRIL 105 can be enabled or disabled by Readable and writable both registers setting or clearing control bit TMR1ON 1 lt 0 gt Internal or external clock select Interrupt on overflow from FFFFh to 0000h
143. transmitted on rising edge of SCK 0 Data transmitted on falling edge of SCK When 1 1 Data transmitted on falling edge of SCK 0 Data transmitted on rising edge of SCK bit5 D A Data Address bit Used in mode only bit4 STOP bit Used mode only This bit is cleared when the MSSP module is disabled SSPEN is cleared bit 3 S START bit Used in mode only bit 2 RW Read Write bit information Used in IC mode only bit 1 UA Update Address Used in IC mode only bit O BF Buffer Full Status bit Receive mode only 1 Receive complete SSPBUF is full 0 Receive not complete SSPBUF is empty Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown DS39564C page 126 2006 Microchip Technology Inc PIC18FXX2 REGISTER 15 2 SSPCONI MSSP CONTROL REGISTER SPI MODE R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPMI SSPMO bit 7 bit O bit 7 WCOL Write Collision Detect bit Transmit mode only 1 The SSPBUF register is written while it is still transmitting the previous word must be cleared in software 0 No collision bit 6 SSPOV Receive Overflow Indicator bit SPI Slave mode 1 Anew byte is received while the SSPBUF register is still holding the previous data In case of overflow the data in SSPSR
144. using the single cycle hardware mul tiply and performing the same function without the hardware multiply TABLE 7 1 PERFORMANCE COMPARISON Program Time Routine Multiply Method Memory Words 40MHz 10 MHz 4 MHz Without hardware multiply 13 69 6 9 us 27 6 us 69 us 8 x 8 unsigned Hardware multiply 1 1 100 5 400 ns 1 us Without hardware multiply 33 91 9 1 us 36 4 us 91 us 8 x 8 signed Hardware multiply 6 6 600 ns 2 4 us 6 us Without hardware multiply 21 242 24 2 us 96 8 us 242 us 16 x 16 unsigned 24 24 2 4 US 9 6 us 24 us u Without hardware multiply 52 254 25 4 us 102 6 us 254 us 16 x 16 signed Hardware multiply 36 36 3 6 us 14 4 us 36 us 7 2 Operation EXAMPLE 7 2 8 x 8 SIGNED MULTIPLY ROUTINE Example 7 1 shows the sequence to do an 8 x 8 unsigned multiply Only one instruction is required MOVF ARG1 W when one argument of the multiply is already loaded in MULWF ARG2 ARG1 ARG2 gt the WREG register PRODH PRODL BTFSC ARG2 SB Test Sign Bit Example 7 2 shows the seguence to do an 8 x 8 signed PRODH F PRODH PRODH multiply To account for the sign bits of the arguments ARGI each argument s Most Significant bit MSb is tested MOVF ARG2 W and the appropriate subtractions are done BTFSC ARG1 SB Test Sign Bit SUBWF PRODH F PRODH PRODH EXAMPLE 7 1 8 x 8 UNSIG
145. 0 2006 Microchip Technology Inc PIC18FXX2 12 0 TIMER2 MODULE The Timer2 module timer has the following features 8 bit timer TMR2 register 8 bit period register PR2 Readable and writable both registers Software programmable prescaler 1 1 1 4 1 16 Software programmable postscaler 1 1 to 1 16 Interrupt on TMR2 match of PR2 SSP module optional use of TMR2 output to generate clock shift Timer2 has a control register shown in Register 12 1 Timer2 can be shut off by clearing control bit TMR2ON T2CON lt 2 gt to minimize power consumption Figure 12 1 is a simplified block diagram of the Timer2 module Register 12 1 shows the Timer2 control regis ter The prescaler and postscaler selection of Timer2 are controlled by this register REGISTER 12 1 12 1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module The TMR2 register is readable and writable and is cleared on any device RESET The input clock Fosc 4 has a prescale option of 1 1 1 4 or 1 16 selected by control bits T2CKPS1 T2CKPSO T2CON lt 1 0 gt The match out put of TMR2 goes through a 4 bit postscaler which gives a 1 1 to 1 16 scaling inclusive to generate a TMR2 interrupt latched in flag bit TMR2IF PIR1 12 The prescaler and postscaler counters are cleared when any of the following occurs a write to the TMR2 register a write to the T2CON register any device RES
146. 0 the result is placed in W If d is 1 the result is placed back in register f default If the result is not 0 the next instruction which is already fetched is discarded and a NOP is executed instead making it a two cycle instruction If a is O the Access Bank will be selected overriding the BSR value If a 1 then the bank will be selected as per the BSR value default 1 1 2 Note 3 cycles if skip and followed by a 2 word instruction Before Instruction TEMP After Instruction TEMP TEMP 1 Q1 Q2 Q3 Q4 Decode Read Process Write to register Data destination If skip Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example HERE DCFSNZ TEMP 1 0 ZERO NZERO Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination If skip Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example HERE DECFSZ CNT 1 1 GOTO LOOP CONTINUE Before Instruction PC Address HERE After Instruction CNT 1 IICNT 0 PC Address CONTINUE IfCNT 0 PC Address HERE 2 If T
147. 0 MHz 3Fh 100 kHz 4 MHz 8 MHz 400 kHz 4 MHz 8 MHz ODh 308 kHz 4 MHz 8 MHz 28h 100 kHz 1MHz 2 MHz 03h 333 kHz 1MHz 2 MHz OAh 100kHz 1 MHz 2 MHz 00h 1 MHz Note 1 The interface does not conform to the 400 kHz 122 specification which applies to rates greater than 100 kHz in all details but may be used with care where higher rates are required by the application 2 Actual frequency will depend on bus conditions Theoretically bus conditions will add rise time and extend low time of clock period producing the effective frequency 2006 Microchip Technology Inc DS39564C page 151 PIC18FXX2 15 4 7 1 Clock Arbitration sampled high the baud rate generator is reloaded with the contents of SSPADD lt 6 0 gt and begins counting This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device Figure 15 18 Clock arbitration occurs when the master during any receive transmit or Repeated START STOP condition de asserts the SCL pin SCL allowed to float high When the SCL pin is allowed to float high the baud rate generator BRG is suspended from counting until the SCL pin is actually sampled high When the SCL pin is FIGURE 15 18 BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX X DX 1 SCL de asserted but slave holds SCL allowed to transition high SCL low clock arbitration SCL A
148. 0 NA 2 5 5 B 96 NA 3 300 i 2 3 500 5 gt 1 HIGH 62 50 0 55 93 0 15 63 0 0 51 0 Low 0 24 255 0 22 255 0 06 255 0 002 255 DS39564C page 170 2006 Microchip Technology Inc PIC18FXX2 TABLE 16 5 BAUD RATES FOR ASYNCHRONOUS MODE BRGH 1 BAUD Fosc 40MHz SPBRG 33 MHz SPBRG 25 MHz SPBRG 20 MHz SPBRG RATE value value value value Kbps KBAUD ERROR decima ERROR decima ERROR decimal KBAUD ERROR decimal 0 3 NA 2 5 NA 5 z NA 1 2 2 3 2 4 NA NA NA 3 9 6 9 60 0 07 214 959 0 15 162 9 62 016 129 19 2 1923 016 129 19 28 0 39 106 19 30 047 80 19 23 016 64 768 7576 1 36 32 7639 0 54 26 78 13 173 19 78 13 4173 15 96 96 15 4016 25 9821 42 31 20 97 66 173 15 96 15 016 12 300 81250 417 7 294 64 179 6 312 50 417 4 312 50 417 3 500 500 0 4 51563 313 3 520 83 417 2 416 67 16 67 2 HIGH 2500 0 2062 50 0 1562 50 0 1250 3 0 Low 977 255 8 06 255 6 10 255 4 88 255 Baup FOSC 16MHz 6PBRG 10 MHz SRE 7 15909 MHz UN 5 0688 MHz pene RATE value value value value Kbps KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal 0 3 NA z NA 1 2 5
149. 0 kHz mode 20 0 1 CB 300 ns 06 gt 4 2 90 TSU STA START condition 100 kHz mode 2 Tosc BRG 1 ms Only relevant for setup time 400 kHz mode 2 Tosc BRG 1 ms Repeated START 1 MHz mode melo 91 THD STA START condition 100 kHz mode 2 Tosc BRG 1 ms After this period the first hold time 400 kHz mode 2 Tosc BRG 1 ms clock pulse is generated 1 MHz mode 2 Tosc BRG 1 ms 106 THD DAT Data input 100 kHz mode 0 ns hold time 400 kHz mode 0 0 9 ms 107 TSU DAT Data input 100 kHz mode 250 ns Note 2 setup time 400 kHz mode 100 ns 92 Tsu sTO STOP condition 100 kHz mode 2 Tosc BRG 1 ms setup time 400 kHz mode 2 Tosc BRG 1 ms 1 MHz model 2 Tosc BRG 1 ms 109 Output valid from 100 kHz mode 3500 ns clock 400 kHz mode 1000 ns 1 MHz mode mE ns 110 TBUF Bus free time 100 kHz mode 4 7 ms Time the bus must be free 400 kHz mode 1 3 ms before a new transmission can start 0102 capacitive loading 400 pF Note 1 Maximum pin capacitance 10 pF for all 2 pins 2 A Fast mode bus device can be used in a Standard mode 2 bus system but parameter 107 gt 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next dat
150. 0 lt k lt 255 Operation BSR Status Affected None Encoding 0000 0001 kkkk kkkk Description The 8 bit literal k is loaded into the Bank Select Register BSR Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal Process Write k Data literal k to BSR Example MOVLB 5 Before Instruction BSR register 0x02 After Instruction BSR register 0x05 DS39564C page 236 2006 Microchip Technology Inc PIC18FXX2 MOVLW Move literal to W Syntax label MOVLW k Operands 0 lt lt 255 Operation kW Status Affected None Encoding 0000 1110 kkkk kkkk Description The eight bit literal K is loaded into W Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to W literal k Data Example MOVLW 0x5A After Instruction W Ox5A Move to f Syntax label MOVWF f al Operands 0 lt 1 lt 255 a e 0 1 Operation W f Status Affected None Encoding 0110 lila ffff Description Move data from W to register Location f can be anywhere in the 256 byte bank If a is 0 the Access Bank will be selected over riding the BSR value If 1 then the bank will be selected as per the BSR value default Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 04 Decode Read Process Write register Data register Example MOVWF REG 0 Before Instruction W Ox4F REG OxFF A
151. 003 ADRESH ADRESL ADRESH ADRESL 5 5 10 bit Result 10 bit Result Right Justified Left Justified 2006 Microchip Technology Inc DS39564C page 187 PIC18FXX2 17 5 Use of the CCP2 Trigger An A D conversion can be started by the special event trigger of the CCP2 module This requires that the 2 2 bits CCP2CON lt 3 0 gt be pro grammed as 1011 and that the A D module is enabled ADON bit is set When the trigger occurs the GO DONE bit will be set starting the A D conversion and the Timer1 or Timer3 counter will be reset to zero or is reset to automatically repeat the A D acquisition period with minimal software overhead moving ADRESH ADRESL to the desired location The appropriate analog input channel must be selected and the minimum acquisition done before the special event trigger sets the GO DONE bit starts conversion If the A D module is not enabled ADON is cleared the special event trigger will be ignored by the A D module but will still reset the Timer1 or Timer3 counter TABLE 17 2 SUMMARY OF A D REGISTERS 2 Value on Value Name Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 POR BOR Other 5 5 INTCON GIE PEIE TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000
152. 09 011 013 0 23 0 28 0 33 Lead Width B 014 017 020 0 36 0 42 0 51 Mold Draft Angle Top 0 12 15 0 12 15 Draft Angle Bottom B 0 12 15 0 12 15 DS39564C page 308 2006 Microchip Technology Inc PIC18FXX2 40 Lead Plastic Dual In line P 600 mil Body PDIP Note For the most current package drawings please see the Microchip Packaging Specification located at http www microchip com packaging e E1 3 q 3 9 3 q q q q q q 8 8 9 2 n O 1 Y 3 ES j iW 7 B B1 eB B p Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 40 40 Pitch 100 2 54 Top to Seating Plane A 160 175 190 4 06 4 45 4 83 Molded Package Thickness A2 140 150 160 3 56 3 81 4 06 Base to Seating Plane A1 015 0 38 Shoulder to Shoulder Width 595 600 625 15 11 15 24 15 88 Molded Package Width E1 530 545 560 13 46 13 84 14 22 Overall Length D 2 045 2 058 2 065 51 94 52 26 52 45 Tip to Seating Plane L 120 130 135 3 05 3 30 3 43 Lead Thickness c 008 012 015 0 20 0 29 0 38 Upper Lead Width B1 030 050 070 0 76 1 27 1 78 Lower Lead Width B 014 018 022 0 36 0 46 0 56 Overall Row Spacing 8 eB 620 650 680 15 75 16 51 17 27 Mold Draft Angle Top 5 10 15 5 10 15 Mold Draft Angle Bottom B 5 10 15 5 10 15
153. 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example INCF CNT 1 0 Before Instruction CNT OxFF Z 0 C 7 DC 2 After Instruction CNT 0x00 2 1 C 1 DC 1 DS39564C page 232 2006 Microchip Technology Inc PIC18FXX2 INCFSZ Increment f skip if 0 INFSNZ Increment f skip if not 0 Syntax label INCFSZ Syntax label INFSNZ f df a Operands 0 lt 1 lt 255 Operands 0 lt lt 255 de 0 1 de 0 1 ae 0 1 ae 0 1 Operation f 1 5 dest Operation f 1 5 dest skip if result 0 skip if result 0 Status Affected None Status Affected None Encoding 0011 lida ffff Encoding 0100 10da ffff Description The contents of register f are Description The contents of register are incremented If is 0 the result is incremented If d is 0 the result is placed in W If d is 1 the result is placed in W If d is 1 the result is placed back in register default placed back in register f default If the result is 0 the next instruc If the result is not 0 the next tion which is already fetched is instruction which is already discarded and a NOP is executed fetched is discarded and a is instead making it a two cycle executed instead making it a two instruction If a is 0 the Access cycle instruction If a is 0 the Bank will be selected overriding Acces
154. 1 REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER C OUNTER agen Value on Name Bit7 Bit 6 Bit5 Bit4 Bit 3 Bit 2 Bit1 Bito All Other 7 RESETS INTCON GIE PEIE TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 000x 0000 000u GIEH GIEL PIR2 EEIF BCLIF LVDIF TMRGIF CCP2IF 0 0000 0 0000 PIE2 EEIE BCLIE LVDIE CCP2IE 0 0000 0 0000 IPR2 EEIP LVDIP TMRSIP CCP2IP 1 1111 1 1111 TMR3L Holding Register for the Least Significant Byte of the 16 bit TMR3 Register XXXX XXXX UUUU uuuu TMR3H Holding Register for the Most Significant Byte of the 16 bit TMR3 Register XXXX XXXX UUUU uuuu TICON RD16 T1CKPS1 TICKPSO TIOSCEN TISYNC TMR1CS TMR1ON 0 00 0000 u uu uuuu RD16 2 T3CKPS1 T3CKPSO 1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu Legend unknown u unchanged unimplemented read as 0 Shaded cells are not used by the Timer1 module EEE LE 2006 Microchip Technology Inc DS39564C page 115 PIC18FXX2 NOTES DS39564C page 116 2006 Microchip Technology Inc PIC18FXX2 14 0 CAPTURE COMPARE PWM CCP MODULES Each CCP Capture Compare PWM module contains a 16 bit register which can operate as a 16 bit Capture register as a 16 bit Compare register or as a PWM Master Slave Duty Cycle register Table 14 1 shows the timer resources of the CCP Module modes The operation of CCP1 is
155. 1 4 1 16 M Postscaler Comparator A EQ 1 1 to 1 16 T2CKPS1 T2CKPSO PR2 4 TOUTPSS TOUTPSO Note 1 TMR2 register output can be software selected by the SSP Module as a baud clock TABLE 12 1 REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER C OUNTER 5 Value on Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit 1 Other 4 5 5 INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 000 0000 000u PIR1 PSPIFO ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 0000 0000 0000 0000 PIE PSPIEU ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMRIIE 0000 0000 0000 IPR1 PSPIPU ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMRIIP 0000 0000 0000 0000 TMR2 Timer2 Module Register 0000 0000 0000 0000 T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPSO TMR2ON T2CKPS1 T2CKPSO 000 0000 000 0000 PR2 Timer2 Period Register 1111 1111 1111 1111 Legend x unknown u unchanged unimplemented read as Shaded cells are not used by the Timer2 module Note 1 The PSPIF PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices always maintain these bits clear DS39564C page 112 2006 Microchip Technology Inc PIC18FXX2 13 0 TIMER3 MODULE Figure 13 1 is a simplified block diagram of the Timer3 module The Timer3 module timer counter has the following features Register 13 1 shows the Timer3 co
156. 10 0101 nnnn nnnn None BNZ n Branch if Not Zero 2 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 2 1110 0100 nnnn nmmn None n Branch Unconditionally 1 2 1101 Onnn nnnn nnnn None BZ n Branch if Zero 1 2 1110 0000 nnnn nmmn None CALL n s Call subroutine1st word 2 1110 110s kkkk None 2nd word 1111 kkkk CLRWDT Clear Watchdog Timer 0000 0000 0000 0100 PD DAW Decimal Adjust WREG 1 0000 0000 0000 0111 GOTO n Go to addressist word 2 1110 1111 kkkk kkkk 2nd word 1111 No Operation 1 0000 0000 0000 0000 NOP No Operation 1 1111 xxxx xxxx None 4 POP Pop top of return stack TOS 1 0000 0000 0000 0110 PUSH Push top of return stack 5 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software device RESET 1 0000 0000 1111 1111 RETFIE 5 Return from interrupt enable 2 0000 0000 0001 000s GIE GIEH PEIE GIEL RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None _ SLEEP Go into Standby mode 1 0000 0000 0000 0011 TO PD Note 1 When a PORT register is modified as a function of itself e g MOVF PORTB 1 0 the value used will be that value present on the pins themselves For example if the data latch is 1 for a pin configured as input and is driven low by an externa
157. 111 1111 uuuu uuuu TRISB 242 442 252 452 1111 1111 uuuu uuuu 5 6 242 442 252 452 111 11116 111 11116 uuu uuuu LATE 242 442 252 452 XXX uuu uuu LATD 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu LATC 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu LATB 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu LATA 56 242 442 252 452 xxx uuu uuuul uuu uuu PORTE 242 442 252 452 000 000 uuu PORTD 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu PORTC 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu PORTB 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu PORTA 242 442 252 452 00009 u0u 00009 uuu uuuu Legend u unchanged x unknown unimplemented bit read as 0 g value depends on condition Shaded cells indicate conditions do not apply for the designated device Note 1 One or more bits in the INTCONXx or PIRx registers will be affected to cause wake up 2 When the wake up is due to an interrupt and the GIEL or GIEH bit is set the PC is loaded with the interrupt vector 0008h or 00185 3 When the wake up is due to an interrupt and the GIEL or GIEH bit is set the TOSU TOSH and TOSL are updated with the current value of the PC The STKPTR is modified to point to the next location in the hardware stack 4 See Table 3 2 for RESET value for specific condition 5 Bit 6 of PORTA LATA and TRIS
158. 15 pF 15 pF 8 0 MHz 15 33 pF 15 33 pF 20 0 MHz 15 33 pF 15 33 pF 25 0 MHz 15 33 pF 15 33 pF See notes following this table These values are for design guidance only Crystals Used 32 0 kHz Epson C 001R32 768K A 20 PPM 200 kHz STD XTL 200 000KHz x 20 PPM 1 0 MHz ECS ECS 10 13 1 50 PPM 4 0 MHz 5 5 40 20 1 50 PPM 8 0 MHz Epson CA 301 8 000M C 30 PPM 20 0 MHz Epson CA 301 20 000M C 30 PPM Note 1 Higher capacitance increases the stability of the oscillator but also increases the start up time 2 Rs may be reguired in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification 3 Since each resonator crystal has its own characteristics the user should consult resonator crystal manufacturer for appro priate values of external components or verify oscillator performance An external clock source may also be connected to the OSC pin in the HS XT and LP modes as shown in Figure 2 2 FIGURE 2 2 EXTERNAL CLOCK INPUT OPERATION HS XT OR LP OSC CONFIGURATION Clock from OSC1 Ext System PIC18FXXX Open OSC2 2 3 RC Oscillator For timing insensitive applications the and RCIO device options offer additional cost savings The RC oscillator frequency is a function of the supply voltage the resistor REXT and capacitor CEXT val ues and the operating tempera
159. 2 CCP1M1 CCP1MO 00 0000 117 CCPR2H Capture Compare PWM Register2 High Byte xxxx xxxx 121 123 CCPR2L Capture Compare PWM Register2 Low Byte xxxx xxxx 121 123 CCP2CON DC2B1 DC2BO CCP2MS CCP2M2 CCP2M1 CCP2MO 00 0000 117 Timer3 Register High Byte XXXX XXXX 113 TMRSL Timer3 Register Low Byte XXXX XXXX 113 T3CON RD16 T3CCP2 T3CKPS1 T3CKPSO T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 113 SPBRG USART1 Baud Rate Generator 0000 0000 168 RCREG USART1 Receive Register 0000 0000 175 178 180 TXREG USART1 Transmit Register 0000 0000 173 176 179 5 CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 166 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000 167 Data EEPROM Address Register 0000 0000 65 69 EEDATA Data EEPROM Data Register 0000 0000 69 2 Data EEPROM Control Register 2 not a physical register ne 65 69 1 EEPGD CFGS FREE WRERR WREN WR RD xx 0 x000 66 Legend unknown u unchanged unimplemented value depends on condition Note 1 RAG and associated bits are configured as port pins in and ECIO Oscillator mode only and read in all other Oscillator modes 2 Bit21 the TBLPTRU allows access to the device configuration bits 3 These registers and bits are reserved on the PIC18F2X2 devices always maintain these clear 2006 Microchip Technology Inc DS39564C page 47 PIC18FXX2 TABLE 4 2 REGISTER FILE SUMMARY CONT
160. 2006 Microchip Technology Inc PIC18FXX2 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www microchip com This web site is used as means to make files and information easily available to customers Accessible by using your favorite Internet browser the web site contains the following information e Product Support Data sheets and errata application notes and sample programs design resources users guides and hardware support documents latest software releases and archived software General Technical Support Frequently Asked Questions FAQ technical support reguests online discussion groups Microchip consultant program member listing Business of Microchip Product selector and ordering guides latest Microchip press releases listing of seminars and events listings of Microchip sales offices distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip s customer notification service helps keep customers current on Microchip products Subscribers will receive e mail notification whenever there are changes updates revisions or errata related to a specified product family or development tool of interest To register access the Microchip web site at www microchip com click on Customer Change Notification and follow the registration instructions CUSTOMER SUPPORT Users of Microchip products can receive assistance through several chann
161. 31250 417 0 500 625 25 00 0 NA 3 HIGH 625 0 515 63 0 390 63 0 312 50 0 LOW 2 44 255 2 01 255 1 53 255 122 255 Baup FOSC216MHZ 10 MHz PERE 7 15909 MHz SPERE 5 0688 MHz PERG RATE value value value value Kbps KBAUD ERROR decimal KBaup ERROR decimal KBAUD ERROR decimal ERROR decimal 0 3 NA 2 12 120 0 16 207 1 20 0 16 129 1 20 0 23 92 1 20 0 65 24 240 016 103 2 40 40 16 64 2 38 0 83 46 2 40 0 32 9 6 9 62 40 16 25 977 41 73 15 9 32 2 90 11 990 43 13 7 192 1928 40 16 12 19 53 173 7 18 64 2 90 5 19 80 43 13 3 768 8333 851 2 7843 173 1 11186 _ 4565 0 79 20 43 13 0 96 8333 13 19 2 7813 18 62 1 1 300 250 16 67 0 156 25 47 92 0 NA 500 NA 3 HIGH 250 0 156 25 0 111 86 0 79 20 0 LOW 0 98 255 0 61 255 0 44 255 0 31 255 BAUD Fosc 4MHz SppRG 3 579545 2 Tu 1MHz SPBRG 32 768 kHz value value value Kbps KBAUD ERROR decima ERROR decima kBAUD ERROR decimal ERROR decimal 0 3 0 30 0 16 207 0 30 0 23 185 0 30 0 16 51 026 1467 1 12 120 167 51 1 19 0 83 46 1 20 0 16 12 gt 2 4 240 167 25 2 43 1 32 22 2 23 6 99 6 9 6 8 93 6 99 6 9 32 2 90 5 781 18 62 1 NA 19 2 2083 851 2 18 64 2 90 2 15 63 18 62 0 NA 76 8 6250 18 62 0 5593 27 17
162. 39564C page 167 PIC18FXX2 16 1 USART Baud Rate Generator BRG The BRG supports both the Asynchronous and Syn chronous modes of the USART It is a dedicated 8 bit baud rate generator The SPBRG register controls the period of a free running 8 bit timer In Asynchronous mode bit BRGH TXSTA lt 2 gt also controls the baud rate In Synchronous mode bit BRGH 15 ignored Table 16 1 shows the formula for computation of the baud rate for different USART modes which only apply in Master mode internal clock Given the desired baud rate and Fosc the nearest inte ger value for the SPBRG register can be calculated using the formula in Table 16 1 From this the error in baud rate can be determined EXAMPLE 16 1 Example 16 1 shows the calculation of the baud rate error for the following conditions Fosc 16 MHz Desired Baud Rate 9600 BRGH 0 SYNC 0 It may be advantageous to use the high baud rate BRGH 1 even for slower baud clocks This is because the Fosc 16 X 1 equation can reduce the baud rate error in some cases Writing a new value to the SPBRG register causes the BRG timer to be reset or cleared This ensures the BRG does not wait for a timer overflow before outputting the new baud rate 16 1 1 SAMPLING The data on the RC7 RX DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin CALCULATING BAUD RATE ERROR
163. 39564C page 263 18F XX2 22 1 DC Characteristics PIC18FXX2 Industrial Extended PIC18LFXX2 Industrial Continued PIC18LFXX2 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 C lt TA lt 85 for industrial Standard Operating Conditions unless otherwise stated PIC18FXX2 i T Industrial Extended Operating temperature 40 C lt TA lt 85 C for industrial 3 40 lt lt 125 for extended Ew Symbol Characteristic Min Typ Max Units Conditions Module Differential Current 0022 Watchdog Timer 75 1 5 2 0V 25 C PIC18LFXX2 2 8 2 0 40 C to 85 C 10 25 uA 4 2V 40 C to 85 C D022 Watchdog Timer 7 15 uA 4 2V 25 C PIC18FXX2 10 25 4 2V 40 C to 85 25 40 4 2V 40 C to 125 C 00224 AIBOR Brown out Reset 29 35 uA Vop 2 0V 25 C PIC18LFXX2 29 45 VDD 2 0V 40 C to 85 C 33 50 HA VDD 4 2V 40 C to 85 DO22A Brown out Reset 36 40 uA 4 20 25 C PIC18FXX2 36 50 uA 4 2V 40 C to 85 36 65 uA 4 2V 40 C to 125 C DO22B AILVD Low Voltage Detect 29 35 uA Voo 2 0V 25 PIC18LFXX2 29 45 pA VDD 2 0V 40 C to 85 C 33 50 HA VDD 4 2
164. 5 11 19 pejeojo Ajeonewomne SI yO Ul JOS SI HO 3 peyepdn speeu 55 yey Buneorpur 19 S VN jo sseippe Jo perepdn si qavdss payepdn si 55 2 7 Aq pejeej9 speeu qavdss eui 3 V yey Buneorpur 195 SI VN 48 UOISSILUSUEJ Jo 2111 eouenbes eux Jo pue eu Je 509485 1 4 14810 si 44 4g 18819 48495 10 peai 4 Bey 4g 18919 378455 Jo pees 7 Y ueuu SI 118455 v NOOdSS 5355 10 5094000 1 1v1SdSS vn TA 1 3 ui 1 lt 0 gt 1VLSdSS 48 lt gt LHld Lr 21955 41 VENU 108 aa 39v leise sng eg 1101195 SI dO Play SI 49019 oa ra za fea Ysa sa V py Yev oy LX 3i y Hov Vv 22 Xv a Vev v Yo YY KY lt as 10
165. 500 nA Sampling Switch 1k ml CHOLD 120 pF Legend input capacitance threshold voltage various junctions LEAKAGE leakage current at the pin due to Ric interconnect resistance 55 sampling switch CHOLD sample hold capacitance from DAC fj 5 6 7 8 9 10 11 Sampling Switch DS39564C page 184 2006 Microchip Technology Inc PIC18FXX2 To calculate the minimum acquisition time Equation 17 1 may be used This equation assumes that 1 2 LSb error is used 1024 steps for the A D The 1 2 LSb error is the maximum error allowed for the A D to meet its specified resolution EQUATION 17 1 ACQUISITION TIME Amplifier Settling Time Holding Capacitor Charging Time Temperature Coefficient TAMP TC TCOFF EQUATION 17 2 A D MINIMUM CHARGING TIME VHOLD VREF VREF 2048 1 eC T CHOLPRRIC RSS R or TC 120 pF 1 Rss RS In 1 2048 Example 17 1 shows the calculation of the minimum required acquisition time TACQ This calculation is based on the following application system assump tions CHOLD 120pF Rs 2 5kQ Conversion Error lt 1 2 LSb VDD 5V gt Rss 7kQ Temperature 50 system max VHOLD OV Q time 0 EXAMPLE 17 1 CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ TC TCOF
166. 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O POR BOR Other RESETS INTCON GIE PEIE TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 0000 000u GIEH GIEL PIR1 PsPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIEU ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIPO ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 00 0000 00x TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 0000 010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend x unknown unimplemented read as 0 Shaded cells are not used for Synchronous Master Transmission Notel The PSPIF PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices always maintain these bits clear DS39564C page 176 2006 Microchip Technology Inc PIC18FXX2 FIGURE 16 6 SYNCHRONOUS TRANSMISSION ai Pes Pis age eese Q1 40 2 ado ba RC7 RX DT M x bti x bit7 X bii x ITXICK Word 1 gt wold 2 i Bn d i j 5 2 Write to c TAREG
167. 6 Microchip Technology Inc PIC18FXX2 43 Fast Register Stack fast interrupt return option is available for interrupts Fast Register Stack is provided for the STATUS WREG and BSR registers and are only one in depth The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt The values in the registers are then loaded back into the working regis ters if the FAST RETURN instruction is used to return from the interrupt A low or high priority interrupt source will push values into the stack registers If both low and high priority interrupts are enabled the stack registers cannot be used reliably for low priority interrupts If a high priority interrupt occurs while servicing a low priority interrupt the stack register values stored by the low priority inter rupt will be overwritten If high priority interrupts are not disabled during low pri ority interrupts users must save the key registers in software during a low priority interrupt If no interrupts are used the fast register stack can be used to restore the STATUS WREG and BSR registers at the end of a subroutine call To use the fast register stack for a subroutine call a FAST CALL instruction must be executed Example 4 1 shows a source code example that uses the fast register stack EXAMPLE 4 1 FAST REGISTER STACK CODE EXAMPLE CALL SUB1 FAST z STATUS WRE
168. 65 Molded Package Width 1 650 653 656 16 51 16 59 16 66 Molded Package Length D1 650 653 656 16 51 16 59 16 66 Footprint Width E2 590 620 630 14 99 15 75 16 00 Footprint Length D2 590 620 630 14 99 15 75 16 00 Lead Thickness c 008 011 013 0 20 0 27 0 33 Upper Lead Width B1 026 029 032 0 66 0 74 0 81 Lower Lead Width B 013 020 021 0 33 0 51 0 53 Mold Draft Angle Top 0 5 10 0 5 10 Mold Draft Angle Bottom B 0 5 10 0 5 10 Controlling Parameter 8 Significant Characteristic Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MO 047 Drawing No C04 048 GER EL 2006 Microchip Technology Inc DS39564C page 311 PIC18FXX2 NOTES DS39564C page 312 2006 Microchip Technology Inc APPENDIX A REVISION HISTORY Revision A J une 2001 Original data sheet for the PIC18FXX2 family Revision B August 2002 This revision includes the DC and AC Characteristics Graphs and Tables The Electrical Specifications in Section 22 0 have been updated and there have been minor corrections to the data sheet text Revision C October 2006 Packaging diagrams updated APPENDIX B The differences between the devices listed in this data PIC18FXX2 DEVICE DIFFERENCES sheet are shown in Table B 1 TABLE B 1 DEVICE DIF
169. 6CXXX Demonstration Board 256 PICSTART Plus Entry Level Development Prograimtrier ott eere erre 255 PIE Registers tshirt esse 80 81 Pinout I O Descriptions PIC18F2X2 2006 Microchip Technology Inc DS39564C page 321 PIC18FXX2 PORTE Analog Port Pins Associated Registers LATE eerte A PORTE Register nnt rear PSP Mode Select PSPMODE Bit n REO RD ANB Pin 99 100 RE1 WR ANG Pin RE2 CS ANT Pin 4 2 1 22 202 24 2 04 4108801 99 100 TRISE 97 Postscaler WDT Assignment PSA Bit 105 Rate Select TOPS2 TOPSO Bits 105 Switching Between WDT 105 Power down Mode See SLEEP Power on Reset POR Oscillator Start up Timer OST Power up Timer PWRT esee Prescaler Capture Prescaler Assignment PSA Bit m Rate Select TOPS2 TOPSO Bits Switching Between WDT Prescaler Timer2 PRO MATE II Universal Device Programmer Product Identification System Program Counter PCL
170. 85 for industrial 40 lt lt 125 for extended Operating voltage VDD range as described DC spec Section 22 1 and Section 22 2 LC parts operate for industrial temperatures only AC CHARACTERISTICS FIGURE 22 4 LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 2 RL Pin CL Vss CL Rin RL 4640 Vss CL 50pF forall pins except OSC2 CLKO and including D and E outputs as ports DS39564C page 270 2006 Microchip Technology Inc PIC18FXX2 22 3 3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 22 5 EXTERNAL CLOCK TIMING ALL MODES EXCEPT PLL 4 01 Q4 o at OSC1 CLKO TABLE 22 4 EXTERNAL CLOCK TIMING REOUIREMENTS dt Symbol Characteristic Min Max Units Conditions 1A FOSC External CLKI Frequency DC 40 MHz ECIO 40 C to 85 C Oscillator Frequency DC 25 MHz EC ECIO 85 C to 125 C DC 4 MHz osc 0 1 4 MHz osc 4 25 MHz HS osc 4 10 MHz HS PLL osc 40 C to 85 C 4 6 25 MHz HS PLL osc 85 C to 125 C 5 200 kHz LP Osc mode 1 Tosc External CLKI Period 25 ns 40 C to 85 C Oscillator Period 40 ns ECIO 85 C to 125 C 250 ns osc 250 10 000 ns XT osc 40 250 ns HS osc 100 250 ns HS PLL osc 40 C to 85 C 160 250 ns HS PLL osc 85 C to
171. 8F242 442 devices and Figure 4 2 shows the Program Memory for PIC18F 252 452 devices 2006 Microchip Technology Inc DS39564C page 35 PIC18FXX2 FIGURE 4 1 PROGRAM MEMORY MAP FIGURE 4 2 PROGRAM MEMORY MAP AND STACK FOR AND STACK FOR PIC18F 442 242 PIC18F452 252 PC lt 20 0 gt PC lt 20 0 gt CALL RCALL RETUR 21 CALL RCALL RETUR 21 RETFIE RETLW RETFIE RETLW Stack Level 1 Stack Level 1 Stack Level 31 Stack Level 31 RESET Vector 0000h RESET Vector 0000h ee ee 2 High Priority Interrupt Vector 0008h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018 Low Priority Interrupt Vector 0018h On Chip Program Memory 3FFFh 29000 On Chip 2 5 gt 24 2 I 7FFFh Read 0 n 8000h 7 Read 0 1FFFFFh 1FFFFFh 200000h gt 200000h DS39564C page 36 2006 Microchip Technology Inc PIC18FXX2 4 2 Return Address Stack The return address stack allows any combination of up to 31 program calls and interrupts to occur The PC Program Counter is pushed onto the stack when a CALL Or RCALL instruction is executed or an interrupt is acknowledged The PC value is pulled off the stack on a RETURN RETLW Or a RETFIE instruction PCLATU and PCLATH are not affected by any
172. 8F442 29 VSS CI 6 87 VDD gt 7 PIC 18F452 27 0 lt gt RBO INTO gt 8 26 lt gt RB1 INT1 lt gt 9 25 gt RB2 INT2 lt gt 10 24 2 gt 11 23 gt AS Tu V NU NO 0 O V ZZ21212120000 588 4 DUIS SSE 858555656 2 T v lt lt DD m m m m 2 RB2 INT2 RB1 INT1 RBO INTO VDD Vss RD7 PSP7 RD6 PSP6 RD5 PSP5 RD4 PSP4 RC7 RX DT NC RCO T10SO T1CKI OSC2 CLKO RA6 OSC1 CLKI Vss VDD T RE2 AN7 CS RE1 ANG WR REO AN5 RD RA5 AN4 SS LVDIN RA4 TOCKI 2006 Microchip Technology Inc PIC18FXX2 Pin Diagrams Cont d J 40 O 4 RB7 PGD 39 RB6 PGC 38 1 lt RB5 PGM 37 O gt RB4 35 RB2 INT2 34 RB1 INT1 33 RBO INTO 32 4 VDD 31 VSS O RD7 PSP7 29 4 RD6 PSP6 MCLR VPP RAO ANO 4 RA1 AN1 RA2 AN2 VREF RAS AN3 VREF lt 4 RAS AN4 SS LVDIN lt REO RD AN5 lt RE1 WR AN6 9 RE2 CS AN7 lt 10 VDD 11 Vss ___ 12 O NOU RUN 18 442
173. 914g 1514 SseJppy JO 914g PU098S eoe d USMEJ eoe d USMEJ sey 5 Jo sey qavdss 10 eyepdn HUN SI 015 Iun SI SseJppy JO 914g 1514 a DS39564C page 143 2006 Microchip Technology Inc PIC18FXX2 15 4 4 CLOCK STRETCHING Both 7 and 10 bit Slave modes implement automatic clock stretching during a transmit sequence The SEN bit SSPCON2 lt 0 gt allows clock stretching to be enabled during receives Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence 15 4 4 1 Clock Stretching for 7 bit Slave Receive Mode SEN 1 In 7 bit Slave Receive mode on the falling edge of the ninth clock at the end of the ACK sequence if the BF bit is set the bit in the SSPCONI register is auto matically cleared forcing the SCL output to be held low The being cleared to 0 will assert the SCL line low The bit must be set in the users ISR before reception is allowed to continue By holding the SCL line low the user has time to service the ISR and read the contents of the SSPBUF before the master device can initiate another receive sequence This will prevent buffer overruns from occurring see Figure 15 13 Note 1 If the user reads the contents of the SSPBUF before the falling edge of the ninth clock thus clearing the BF bit the CKP bit will not
174. 9564C page 233 2006 Microchip Technology Inc PIC18FXX2 IORLW Inclusive OR literal with W Syntax label IORLW k Operands 0 lt k lt 255 Operation W KO W Status Affected N Z Encoding 0000 1001 kkkk kkkk Description The contents of W are ORed with the eight bit literal k The result is placed in W Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to W literal k Data Example IORLW 0x35 Before Instruction W Ox9A After Instruction W OxBF IORWF Inclusive OR W with f Syntax label IORWF f d a Operands 0 lt 1 lt 255 d e 0 1 0 1 Operation W OR f dest Status Affected N 2 Encoding 0001 ooda ffff Description Inclusive OR W with register f If d is 0 the result is placed in W If d is 1 the result is placed back in register default If a is 0 the Access Bank will be selected over riding the BSR value If a 1 then the bank will be selected as per the BSR value default Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example IORWF RESULT 0 1 Before Instruction RESULT 0x13 W 0x91 After Instruction RESULT 0x13 W 0x93 DS39564C page 234 2006 Microchip Technology Inc PIC18FXX2 LFSR Load FSR Syntax label LFSR f k Operands 0 lt 1 lt 2 0 lt
175. A 5 z z NA 12 24 f NA 5 9 6 NA 3 5 NA 19 2 5 NA 3 768 7692 40 16 129 77 10 039 106 7716 047 80 76 92 40 16 64 96 96 15 0 16 103 95 93 0 07 85 96 15 016 64 96 15 0 16 51 300 30203 1 01 32 294 64 179 27 297 62 0 79 20 29412 1 96 16 500 500 0 19 485 30 2 94 16 480 77 3 85 12 500 0 9 HIGH 10000 0 8250 0 6250 0 5000 0 LOW 39 06 4 255 32 23 255 24 41 1 255 19 53 3 255 BAup FOSC 16MHz SPBRG 10 MHz REN 7 15909 MHz se 5 0688 MHz RATE value Kbps KBAUD ERROR decimal KBAUD ERROR decima ERROR decimal ERROR decimal 0 3 NA 5 z NA 12 i NA 5 24 1 NA 9 6 NA i 9 62 40 23 185 9 60 0 131 19 2 1923 3016 207 19 23 016 129 19 24 023 92 19 20 0 65 768 7692 016 51 7576 1 36 32 7782 132 22 7454 2 94 16 96 95 24 079 41 96 15 _ 0 16 25 9420 1 88 18 9748 154 12 300 30770 42 56 12 812 50 417 7 298 35 0 57 5 316 80 5 60 3 500 500 0 7 500 0 4 447 44 10 51 3 42240 15 52 2 HIGH 4000 0 2500 0 1789 80 0 126720 0 LOW 15 63 255 9 77 255 6 99 255 4 95 255 Baup FOSCZ4MHZ 3 579545 MHZ SpBRG 1 MHz S BKG 32 768 kHz RATE Kbps KBAUD
176. A N A N A PLUSW2 242 442 252 452 N A N A N A FSR2H 242 442 252 452 XXXX uuuu uuuu 25821 242 442 252 452 XXXX uuuu uuuu uuuu uuuu STATUS 242 442 252 452 XXXX u uuuu u uuuu TMROH 242 442 252 452 0000 0000 uuuu uuuu uuuu uuuu TMROL 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu TOCON 242 442 252 452 1111 1111 1111 1111 uuuu uuuu OSCCON 242 442 252 452 Q Q u LVDCON 242 442 252 452 00 0101 00 0101 uu uuuu WDTCON 242 442 252 452 Q Q ween u 242 442 252 452 0 1144 0 qquu u u qquu TMR1H 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu TMR1L 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu T1CON 242 442 252 452 0 00 0000 u uu uuuu u uu uuuu TMR2 242 442 252 452 0000 0000 0000 0000 uuuu uuuu PR2 242 442 252 452 1111 XLI 1121 LEIL ETES TIBI T2CON 242 442 252 452 000 0000 000 0000 uuu uuuu SSPBUF 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu SSPADD 242 442 252 452 0000 0000 0000 0000 uuuu uuuu SSPSTAT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu SSPCONT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu SSPCON2 242 442 252 452 0000 0000 0000 0000 uuuu uuuu Legend u unchanged x unknown o gt unimplemented bit read as 0 value depends on condition Shaded cells indi
177. A are enabled ECIO and RCIO Oscillator modes only In all other Oscillator modes they are disabled and read 0 6 Bit 6 of PORTA LATA and TRISA are not available on all devices When unimplemented they are read 0 2006 Microchip Technology Inc DS39564C page 31 PIC18FXX2 FIGURE 3 3 TIME OUT SEQUENCE ON POWER UP MCLR TIED TO INTERNAL POR PWRT TIME OUT TOST OST TIM INTERNAL RESET VDD z MCLR TPWRT E OUT FIGURE 3 4 TIME OUT SEQUENCE POWER UP MCLR NOT TIED TO CASE 1 INTERNAL POR PWRT TIM OST TIME OUT INTERNAL RESET 1 2138 MCLR 12 gt TPWT E OUT 14 TOST gt FIGURE 3 5 TIME OUT SEQUENCE POWER UP MCLR NOT TIED Vpp CASE 2 INTERNAL POR PWRT TIME OUT MCLR g lt TPWRT gt INTERNAL RESET OST TIME OUT i DS39564C page 32 2006 Microchip Technology Inc PIC18FXX2 FIGURE 3 6 SLOW RISE TIME MCLR TIED TO 5V VDD ov MCLR ta INTERNAL POR TPWRT PWRT TIME OUT TOST OST TIME OUT INTERNAL RESET FIGURE 3 7 TIME OUT SEQUENCE ON POR W PLL ENABLED MCLR TIED TO VDD MCLR T
178. ARGIH W ARGIH W ARG2L ARG2L gt MULWF ARG2L ARGIH ARG2L gt PRODH PRODL PRODH PRODL MOVF PRODL W MOVF PRODL W ADDWF RES1 F Add cross ADDWF RES1 F Add cross MOVF PRODH W products MOVF PRODH W products ADDWFC RES2 F ADDWFC RES2 CLRF WREG i CLRF WREG i ADDWFC RES3 ADDWFC RES3 BTFSS ARG2H 7 ARG2H ARG2L neg Example 7 4 shows the sequence to do a 16 x 16 BRA SIGN 1 no check ARG1 signed multiply Equation 7 2 shows the algorithm MOVE ARGIL W i used The 32 bit result is stored in four registers SUBWF RES2 RES3 RESO To account for the sign bits of the argu MOVF ments argument pairs Most Significant bit MSb SUBWFB RES3 is tested and the appropriate subtractions are done SIGN ARG1 BTFSS 7 ARG1H ARGIL neg EQUATION 7 2 16 x 16 SIGNED BRE CONT CODE Re MULTIPLICATION MOVF ARG2L W ALGORITHM SUBWF RES2 RES3 RESO MOVF ARG2H W ARGIH ARGIL ARG2H ARG2L SPANIE 16 ARGIH e ARG2H e CONT CODE ARGIH e ARG2L e 2 ARGIL ARG2H 28 ARGIL ARG2L 1 e ARG2H lt 7 gt ARGIH ARGIL e 216 1 e ARGIH lt 7 gt ARG2H ARG2L e 216 DS39564C page 72 2006 Microchip Technology Inc PIC18FXX2 8 0 INTERRUPTS The PIC18FXX2 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to
179. C see Section 4 8 1 4 5 Clocking Scheme Instruction Cycle The clock input from OSC1 is internally divided by four to generate four non overlapping quadrature clocks namely Q1 Q2 Q3 and Q4 Internally the pro gram counter PC is incremented every Q1 the instruction is fetched from the program memory and latched into the instruction register in Q4 The instruc tion is decoded and executed during the following Q1 through Q4 The clocks and instruction execution flow are shown in Figure 4 4 FIGURE 4 4 CLOCK INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q4 Q1 02 03 Q4 OSC1 Xe ak FN LINES PSN RUE DR 02 N Internal TN X Q4 X A TA TI PC PC PC 2 4 OSC2 CLKO RC mode Execute INST TPC2 Fetch INST PC xecute etc Fetch INST PC 4 2006 Microchip Technology Inc DS39564C page 39 PIC18FXX2 4 6 Instruction Flow Pipelining An Instruction Cycle consists of four cycles G1 Q2 Q3 and 04 The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle However due to the pipelining each instruction effectively executes in one cycle If an instruction causes the program counter to change GOTO then two cycles are required to complete
180. CY 20 ns Time Synchronous 10 ms with prescaler PICIBLEXXX 25 ns Asynchronous PIC18FXXX 30 ns PIC18LFXXX 50 ns 46 Low Synchronous no prescaler 0 5TCY 5 ns Time Synchronous 10 ns with prescaler PIC18LFXXX 25 ns Asynchronous PIC18FXXX 30 ns PIC18LFXXX 50 ns 47 input Synchronous Greater of ns prescale period 20 ns or Toy 40 value N 1 2 4 8 Asynchronous 60 ns Ft1 oscillator input frequency range DC 50 kHz 48 Tcke2tmrl Delay from external TICKI clock edge to timer 2 Tosc 7 Tosc increment DS39564C page 275 2006 Microchip Technology Inc PIC18FXX2 FIGURE 22 10 CAPTURE COMPARE PWM TIMINGS CCP1 AND CCP2 Capture Mode 50 lt 51 gt 52 x LS Note Refer to Figure 22 4 for load conditions TABLE 22 9 CAPTURE COMPARE PWM REQUIREMENTS CCP1 AND CCP2 Symbol Characteristic Min Max Units Conditions 50 TccL CCPx input low No Prescaler 0 5 20 ns time With PIC18FXXX 10 ns Prescaler pIC18LFXXX 20 ns 51 TccH CCPx input No Prescaler 0 5 Tcv 20 ns high time With PIC18FXXX 10 ns Prescaler 18 20
181. Duty Cycle Registers CCPRIL Tie yY CCPR1H Slave e Comparator R Q T RC2 CCP1 TMR2 Note 1 mE Comparator TRISC lt 2 gt Clear Timer 4 CCP1 and PRO latch D C Note 8 bit timer is concatenated with 2 bit internal clock or 2 bits of the prescaler to create 10 bit time base A PWM output Figure 14 4 has a time base period and a time that the output stays high duty cycle The frequency of the PWM is the inverse of the period 1 period FIGURE 14 4 PWM OUTPUT Period Duty Cycle TMR2 PR2 TMR2 Duty Cycle TMR PR2 14 5 1 PWM PERIOD The PWM period is specified by writing to the PR2 register The PWM period can be calculated using the following formula PWM period PR2 1 4 TOSC e TMR2 prescale value PWM frequency is defined as 1 PWM period When TMR2 is equal to PR2 the following three events occur on the next increment cycle e 2 is cleared The pin is set exception if PWM duty cycle 096 the CCP1 pin will not be set The PWM duty cycle is latched from CCPRIL into CCPR1H Note The Timer2 postscaler see Section 12 0 is not used in the determination of the PWM frequency The postscaler could be used to have a servo update rate at a different frequency than the PWM output
182. E Initialize PORTE by Clearing output data latches CLRF LATE Alternate method to clear output data latches MOVLW 0x07 Configure A D MOVWF ADCON1 for digital inputs MOVLW 0x05 Value used to initialize data direction MOVWF TRISE Set RE 0 as inputs RE 1 as outputs RE 2 as inputs FIGURE 9 9 PORTE BLOCK DIAGRAM IN O PORT MODE RD LATE Data Bus 05 vd pin WR LATE X PORTE Data Latch A D Q TS K Schmitt Trigger TRIS Latch Input Buffer RD TRISE RD PORTE To Analog Converter Note 1 1 0 pins have diode protection to and Vss 2006 Microchip Technology Inc DS39564C page 97 PIC18FXX2 REGISTER 9 1 TRISE REGISTER R 0 R 0 R W 0 R W 0 U 0 R W 1 R W 1 R W 1 IBF OBF IBOV PSPMODE TRISE2 TRISE1 TRISEO bit 7 bit 0 bit 7 IBF Input Buffer Full Status bit 1 word has been received and waiting to be read by the CPU 0 No word has been received bit 6 OBF Output Buffer Full Status bit 1 The output buffer still holds a previously written word 0 The output buffer has been read bit 5 IBOV Input Buffer Overflow Detect bit in Microprocessor mode 1 write occurred when a previously input word has not been read must be cleared in software 0 No overflow occurred bit 4 PSPMODE Parallel Slav
183. E2 EEIF BCLIE LVDIE TMR3IE CCP2IE 0 0000 0 0000 IPR2 EEIP BCLIP LVDIP TMR3IP CCP2IP 1 1111 1 1111 TMRSL Holding Register for the Least Significant Byte of the 16 bit TMR3 Register XXXX uuuu uuuu TMR3H Holding Register for the Most Significant Byte of the 16 bit TMR3 Register XXXX UUUU uuuu T3CON RD16 T3CCP2 T3CKPS1 T3CKPSO T3CCP1 TZSYNC TMR3CS 0000 0000 uuuu uuuu Legend x unknown u unchanged unimplemented read as 0 Shaded cells not used by Capture and Note 1 The PSPIF PSPIE and PSPIP bits are reserved on the PIC18F2x2 devices always maintain these bits clear 2006 Microchip Technology Inc DS39564C page 121 PIC18FXX2 145 PWM Mode In Pulse Width Modulation PWM mode the CCP1 pin produces up to a 10 bit resolution PWM output Since the 1 pin is multiplexed with the PORTC data latch the TRISC lt 2 gt bit must be cleared to make the CCP1 pin an output Note Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level This is not the PORTC data latch Figure 14 3 shows a simplified block diagram of the CCP module in PWM mode For a step by step procedure on how to set up the CCP module for PWM operation see Section 14 5 3 FIGURE 14 3 SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON lt 5 4 gt
184. ECTION FOR CERAMIC RESONATORS Ranges Tested Mode Freq C1 C2 XT 455 kHz 68 100 pF 68 100 pF 2 0 MHz 15 68pF 15 68pF 4 0 MHz 15 68pF 15 68pF HS 8 0 MHz 10 68 pF 10 68 pF 16 0 MHz 10 22pF 10 22 pF These values are for design guidance only See notes following this table Resonators Used 455 kHz Panasonic EFO A455K04B 0 3 2 0 MHz Murata Erie CSA2 00MG 0 5 4 0 MHz Murata Erie CSA4 00MG 0 5 8 0 MHz Murata Erie CSA8 00MT 0 5 16 0 MHz Murata CSA16 00MX 0 5 All resonators used did not have built in capacitors Note 1 When operating below 3V or when Since each resonator crystal has its own Higher capacitance increases the stability of the oscillator but also increases the start up time using certain ceramic resonators at any voltage it may be necessary to use high gain HS mode try a lower freguency resonator or switch to a crystal oscillator characteristics the user should consult resonator crystal manufacturer for appro priate values of external components or verify oscillator performance 2006 Microchip Technology Inc DS39564C page 17 PIC18FXX2 TABLE 2 2 CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Ranges Tested Mode Freq C1 C2 LP 32 0 kHz 33 pF 33 pF 200 kHz 15 pF 15 XT 200 kHz 22 68 pF 22 68 pF 1 0 MHz 15 pF 15 pF 4 0 MHz 15 pF 15 pF HS 4 0 MHz
185. EG 1 0000 1101 kkkk RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C DC Z OV N XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk 2 DATA MEMORY lt gt PROGRAM MEMORY OPERATIONS TBLRD Table Read 2 0000 0000 0000 1000 TBLRD Table Read with post increment 0000 0000 0000 1001 TBLRD Table Read with post decrement 0000 0000 0000 1010 TBLRD Table Read with pre increment 0000 0000 0000 1011 TBLWT Table Write 2 5 0000 0000 0000 1100 TBLWT Table Write with post increment 0000 0000 0000 1101 TBLWT Table Write with post decrement 0000 0000 0000 1110 TBLWT Table Write with pre increment 0000 0000 0000 1111 Note 1 When a PORT register is modified as a function of itself e g MOVF PORTB 1 0 the value used will be that value present on the pins themselves For example if the data latch is 1 for a pin configured as input and is driven low by an external device the data will be written back with a 0 If this instruction is executed on the TMRO register and where applicable d 1 the prescaler will be cleared if assigned If Program Counter PC is modified or a conditional test is true the instruction requires two cycles The second cycle is executed as Some instructions are 2 word instructions The second word of these instructions wi
186. EG register starts transmission Note TXIF is not cleared immediately upon load ing data into the transmit buffer TXREG The flag bit becomes valid in the second instruction cycle following the load instruction FIGURE 16 1 USART TRANSMIT BLOCK DIAGRAM Data Bus TXREG Register TXIE 7222 22 det 30 LSb 0 ess TSR Register 0 RC6 TX CK pin Interrupt TRMT SPEN DS39564C page 172 2006 Microchip Technology Inc PIC18FXX2 FIGURE 16 2 ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output Shift Clock L L ET RC6 TX CK ilte pin START bit 0 X BETIS Word 1 gt TXIF bit 1 Transmit Buffer Reg Empty 55 Wordi TRMT bit Qhi Transmit Shift Transmit Shift Reg Reg Empty Flag ide 2 FIGURE 16 3 ASYNCHRONOUS TRANSMISSION BACK TO BACK TABLE 16 6 REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION 2006 Microchip Technology Inc DS39564C page 173 PIC18FXX2 16 2 2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 16 4 The data is received on the RC7 RX DT pin and drives the data recovery bloc
187. EMP PC If TEMP PC Address ZERO Wow Hg oH og 0 Address NZERO 2006 Microchip Technology Inc DS39564C page 231 PIC18FXX2 GOTO Unconditional Branch Syntax label GOTO k Operands O lt k lt 1048575 Operation PC lt 20 1 gt Status Affected None Encoding 1st word k lt 7 0 gt 1110 1111 kjkkk 2nd word k lt 19 8 gt 1111 k 9kkk Description GOTO allows an unconditional branch anywhere within entire 2 Mbyte memory range The 20 bit value K is loaded into lt 20 1 gt GOTO is always a two cycle instruction Words 2 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal No Read literal k lt 7 0 gt operation K 19 85 Write to PC No No No No operation operation operation operation Example GOTO THERE After Instruction PC Address THERE INCF Increment f Syntax label INCF f d a Operands 0 lt 1 lt 255 d e 0 1 0 1 Operation f 1 gt dest Status Affected C DC N Z Encoding 0010 10da ffff Description The contents of register are incremented If d is 0 the result is placed in W If d is 1 the result is placed back in register f default If a is 0 the Access Bank will be selected overriding the BSR value If a 1 then the bank will be selected as per the BSR value default Words 1 Cycles
188. EPROM Read m Data EEPROM Refresh Routine Data EEPROM Write Erasing a FLASH Program Memory Row Fast Register How to Clear Bank1 Using Indirect Addressing 50 Initializing PORTA eene 87 Initializing PORTB 90 Initializing PORTC 93 Initializing PORTD 22295 Initializing PORTE eee 97 Loading the SSPBUF SSPSR Register 128 Reading a FLASH Program Memory Word 59 Saving STATUS WREG and BSR Registers in RAM 85 Writing to FLASH Program Memory 62 63 Code Protection ere et tret ee teer eet rne 195 Compare CCP Module 120 Associated Registers 2 4 4222122 121 CCP Pin Configuration CCPRI Register Software Interrupt Special Event Trigger 109 115 120 188 Timer1 Timer3 Mode Selection 120 Configuration Bits Context Saving During Interrupts Conversion Considerations E ote e Yo pe HI 5 a awa ba Data EEPROM Memory Associated R
189. ERNAL BLOCK TABLE READ EBTRn DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB EBTRB 11 0001FFh 000200h TBLPTR 000FFF WRTO EBTRO 10 001FFFh 002000h 002FFE TBLRD WRT1 EBTR1 11 003FFFh 004000h WRT2 EBTR2 11 005FFFh 006000h 11 007FFFh Results All Table Reads from external blocks to Blockn are disabled whenever EBTRn 0 register returns a value of 0 FIGURE 19 6 EXTERNAL BLOCK TABLE READ EBTRn ALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB EBTRB 11 0001FFh 000200h TBLPTR 000FFF WRTO EBTRO 10 001FFE TBLRD 001FFFh 002000h WRT1 EBTR1 11 003FFFh 004000h WRT2 EBTR2 11 005FFFh 006000h WRT3 EBTR3 11 007FFFh Results Table Reads permitted within Blockn even when EBTRBn 0 TABLAT register returns the value of the data at the location TBLPTR 2006 Microchip Technology Inc DS39564C page 209 PIC18FXX2 19 4 2 DATA EEPROM CODE PROTECTION The entire Data is protected from external reads and writes by two bits CPD and WRTD CPD inhibits external reads and writes of Data EEPROM WRTD inhibits external writes to Data EEPROM The CPU can continue to read and write Data EEPROM regardless of the protection bit settings 19 4 8 CONFIGURATION REGISTER PROTECTION The configuration registers can be wri
190. ERROR decimal KBAUD ERROR decima KBAUD ERROR decimal ERROR decimal 0 3 NA 1 3 030 114 26 12 NA 1 20 0 16 207 147 248 6 24 2 40 0 16 103 278 413 78 2 9 6 9 62 016 103 9 62 023 92 9 62 0 16 25 8 20 14 67 0 19 2 1923 40 16 51 19 04 083 46 19 23 4046 12 NA 768 7692 016 12 7457 290 11 83 33 851 2 NA 96 1000 417 9 9943 357 8 83 33 13 19 2 300 333 33 411 11 2 298 30 0 57 2 250 16 67 0 NA 500 500 0 1 44744 1051 1 1 3 HIGH 1000 0 894 89 0 250 0 8 20 0 LOW 3 91 5 255 3 50 255 0 98 255 0 03 255 2006 Microchip Technology Inc DS39564C page 169 PIC18FXX2 TABLE 16 4 BAUD RATES FOR ASYNCHRONOUS MODE BRGH 0 BAUD FOSsC 40MHz SpBRG 33 MHz SPBRG 25 MHz SPBRG 20 MHz SPBRG RATE value value Kbps KBAUD ERROR Kpaup ERROR decimal KBAUD ERROR decimal ERROR decimal 03 NA __ A 12 z 5 NA 24 5 2 40 0 07 214 2 40 0 15 162 240 016 129 9 6 9 62 0 16 64 9 55 0 54 53 9 53 0 76 40 947 196 32 192 1894 136 32 19 10 0 54 26 1953 173 19 19 58 173 15 768 7818 41 73 7 73 66 4 09 6 7813 173 4 7813 173 3 96 8929 699 6 103 13 4742 4 9766 173 3 10417 4851 2 31250 417 1 257 81 14 06 1 NA
191. ET Power on Reset MCLR Reset Watchdog Timer Reset or Brown out Reset TMR2 is not cleared when T2CON is written T2CON TIMER2 CONTROL REGISTER U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPSO 2 T2CKPS1 T2CKPSO bit 7 bit O bit 7 Unimplemented Read as bit 6 3 0000 1 1 Postscale 0001 1 2 Postscale 1111 1 16 Postscale bit 2 TMR2ON Timer2 On bit 1 Timer2 is on 0 Timer2 is off bit 1 0 00 Prescaler is 1 01 Prescaler is 4 1x Prescaler is 16 TOUTPS3 TOUTPSO Timer2 Output Postscale Select bits T2CKPS1 T2CKPSO Timer2 Clock Prescale Select bits Legend R Readable bit W Writable bit U Unimplemented bit read as at POR 7 Bit is set 0 Bit is cleared X z Bit is unknown 2006 Microchip Technology Inc DS39564C page 111 PIC18FXX2 12 2 Timer2 Interrupt The Timer2 module has an 8 bit period register PR2 Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle PR2 is a readable and writable register The PR2 register is initialized to FFh upon RESET 12 3 Output of TMR2 The output of TMR2 before the postscaler is fed to the Synchronous Serial Port module which optionally uses it to generate the shift clock FIGURE 12 1 TIMER2 BLOCK DIAGRAM Sets Flag u 1 bit TMR2IF A Fosc 4 Prescaler TMR2 1 1
192. ET input This RESET can be generated by the CCP module Section 14 0 TMRSIF CCP Special Trigger C Draco Overflow Interrupt Flag bit Synchronized CLR 04 Clock Input TMR3H TMR3L 1 On Off T3SYNC 1080 gt gt T13CKI i Prescaler Synchronize a TiOscen Fosc 4 1 2 4 8 4 det i Enable Internal 0 T1OSI x Oscillator Clock 2 me TMR3CS SLEEP Input Note 1 When enable bit TIOSCEN is cleared the inverter and feedback resistor are turned off This eliminates power drain TSCKPS1 T3CKPSO FIGURE 13 2 TIMER3 BLOCK DIAGRAM CONFIGURED IN 16 BIT READ WRITE MODE Data lt 7 0 gt NX C XS 8 TMR3H BNL 874 Write TMR3L Read TMR3L L Special Trigger Set TMRGIF Flag bit 8 V TMR3 V7 me a Synchronized on Overflow A Timer3 CLR Clock Input High Byte 1 To Clock Input TMR3ON pd ctt On Off T3SYNC T10S0 an T13CKI 2 Prescaler Synchronize OSCEN Fosc 4 1 2 4 8 A det Ee Internal 0 TE Oscillator T10SI Dx Clock 2 SLEEP Input T3CKPS1 T3CKPSO TMR3CS Note 1 When the TIOSCEN bit is cleared the inverter and feedback resistor are turned off This eliminates power drain DS39564C page 114 2006 Microchip Technology Inc P
193. F Temperature coefficient is only required for temperatures gt 25 C TACQ 2ys TC Temp 25 C 0 05 us C TC CHOLD RIC RSS RS In 1 2048 120 pF 1 7 2 5 In 0 0004883 120 pF 10 5 In 0 0004883 1 26 us 7 6246 9 61 us 2 us 9 61 us 50 25 C 0 05 us C 11 61 us 1 25 us 12 86 us TACO 2006 Microchip Technology Inc DS39564C page 185 PIC18FXX2 17 2 Selecting the A D Conversion Clock A D conversion time per bit is defined as TAD A D conversion requires 12 TAD per 10 bit conversion The source of the A D conversion clock is software selectable The seven possible options for TAD are 2 Tosc 4 TOSC 8 Tosc 16 Tosc 32 Tosc 64 Tosc Internal A D module RC oscillator 2 6 us For correct A D conversions the A D conversion clock TAD must be selected to ensure a minimum TAD time of 1 6 us Table 17 1 shows the resultant TAD times derived from the device operating frequencies and the A D clock Source selected 17 3 Configuring Analog Port Pins The ADCONI TRISA and TRISE registers control the operation of the A D port pins The port pins that are desired as analog inputs must have their corresponding TRIS bits set input If the TRIS bit is cleared output the digital output level or VOL will be converted The A D operation is independent of the state of the CHS2 CHSO bits and the TRIS bit
194. FERENCES Feature PIC18F242 PIC 18F 252 PIC 18F 442 PIC18F452 Program Memory Kbytes 16 32 16 32 Data Memory Bytes 768 1536 768 1536 A D Channels 5 5 8 8 Parallel Slave Port PSP No No Yes Yes des 40 pin DIP 40 pin DIP Package Types 2 44 44 P 44 pin TQFP 44 pin TQFP DS39564C page 313 2006 Microchip Technology Inc PIC18FXX2 APPENDIX C CONVERSION CONSIDERATIONS This appendix discusses the considerations for con verting from previous versions of a device to the ones listed in this data sheet Typically these changes are due to the differences in the process technology used An example of this type of conversion is from a PIC16C74A to a PIC16C74B Not Applicable APPENDIX D MIGRATION FROM BASELINE TO ENHANCED DEVICES This section discusses how to migrate from a Baseline device i e PIC16C5X to an Enhanced device i e PIC18FXXX The following are the list of modifications over the PIC16C5X microcontroller family Not Currently Available DS39564C page 314 2006 Microchip Technology Inc PIC18FXX2 APPENDIX E MIGRATION FROM MID RANGE TO ENHANCED DEVICES detailed discussion of the differences between the mid range MCU devices i e PIC16CXXX and the enhanced devices i e PIC18FXXX is provided in AN716 Migrating Designs from PIC16C74A 74B to PIC18F442 The changes discussed while device specific are
195. Figure 3 6 and Figure 3 7 depict time out seguences on Since the time outs occur from the POR pulse if MCLR is kept low long enough the time outs will expire Bringing MCLR high will begin execution immediately Figure 3 5 This is useful for testing purposes or to synchronize more than one PIC18FXXX device operat ing in parallel Table 3 2 shows the RESET conditions for some Special Function Registers while Table 3 3 shows the RESET conditions for all the registers DS39564C page 26 2006 Microchip Technology Inc PIC18FXX2 TABLE 3 1 TIME OUT IN VARIOUS SITUATIONS osdilbio Power up Wake up from Configuration 1 Brown out SLEEP or 9 PWRTE 0 1 Oscillator Switch 2 HS with PLL enabled 72 ms 1024 Tosc 1024 Tosc 72 ms 1024 Tosc 1024 Tosc 2 2ms 2 ms 2 ms HS XT LP 72 ms 1024 Tosc 1024 Tosc 72 ms 1024 Tosc 1024 Tosc EC 72 ms 72 ms External RC 72 ms 72 ms Note 1 2 ms is the nominal time required for the 4x PLL to lock 2 72 ms is the nominal power up timer delay if implemented REGISTER 3 1 RCON REGISTER BITS AND POSITIONS R W 0 U 0 U 0 RAW 1 R 1 R 1 R W 0 R W 0 IPEN RI TO PD POR BOR bit 7 bit 0 Note 1 Refer to Section 4 14 page 53 for bit definitions TABLE 3 2 STATUS BITS THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Cond
196. G BSR SAVED IN FAST REGISTER STACK SUBI RETURN FAST RESTORE VALUES SAVED IN FAST REGISTER STACK 4 4 PCL PCLATH and PCLATU The program counter PC specifies the address of the instruction to fetch for execution The PC is 21 bits wide The low byte is called the PCL register This reg ister is readable and writable The high byte is called the PCH register This register contains the lt 15 8 gt bits and is not directly readable or writable Updates to the PCH register may be performed through the PCLATH register The upper byte is called PCU This register contains the PC lt 20 16 gt bits and is not directly readable or writable Updates to the PCU register may be performed through the PCLATU register The PC addresses bytes in the program memory To prevent the PC from becoming misaligned with word instructions the LSB of PCL is fixed to a value of 0 The PC increments by 2 to address sequential instructions in the program memory The CALL RCALL GOTO and program branch instructions write to the program counter directly For these instructions the contents of PCLATH and PCLATU are not transferred to the program counter The contents of PCLATH and PCLATU will be trans ferred to the program counter by an operation that writes PCL Similarly the upper two bytes of the pro gram counter will be transferred to PCLATH and PCLATU by an operation that reads PCL This is useful for computed offsets to the P
197. GD 43 RB6 PGC 42 RB5 PGM 41 40 883 is the alternate pin for the 2 pin multiplexing DS39564C page 2 RA4 TOCKI lt gt 7 39 gt RAS AN4 SS LVDIN lt gt 8 3811 REO RD AN5 lt 19 370 lt gt RETMWR ANG6 10 PIC18F442 30 gt RE2 CS AN7 11 350 Voo 12 PIC18F452 31 Vss 13 33L lt gt OSCI CLKI 14 321 lt gt OSC2 CLKO RA6 15 310 lt gt RCO T1OSO T1CKI 16 300 To 2120210101992 gt 109111 10034 200000000 ODRVVVV OG DAGOANWOG TS T X amp N 5 5 o x x aaooooooOo0ra E 0 o00 0 0 0 OOF XO LO sr CO QN TOFP TTO st 444 CO CO RC7 RX DT 1 RD4 PSP4 lt 2 32 335220 RD5 PSP5 lt gt 0 3 31 _ RD6 PSP6 7 CIO 4 30 RD7 PSP7 C10 5 PIC1
198. IC18FXX2 13 2 Oscillator The Timer1 oscillator may be used as the clock source for Timer3 The Timer1 oscillator is enabled by setting the TIOSCEN T1CON lt 3 gt bit The oscillator is a low power oscillator rated up to 200 KHz See Section 11 0 for further details 13 3 Timer3 Interrupt The TMR3 Register pair TMR3H TMR3L increments from 0000h to FFFFh and rolls over to 0000h The TMR3 Interrupt if enabled is generated on overflow which is latched in interrupt flag bit TMRSIF PIR2 lt 1 gt This interrupt can be enabled disabled by setting clearing TMR3 interrupt enable bit TMRSIE PIE2 lt 1 gt 13 4 Resetting Timer3 Using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a special event trigger CCP1M3 CCP1MO 1011 this signal will reset Timers Note The special event triggers from the CCP module will not set interrupt flag bit TMRSIF PIR1 lt 0 gt Timer3 must be configured for either Timer or Synchro nized Counter mode to take advantage of this feature If Timer3 is running in Asynchronous Counter mode this RESET operation may not work In the event that a write to Timer3 coincides with a special event trigger from CCPI the write will take precedence In this mode of operation the CCPR1H CCPR1L registers pair effectively becomes the period register for Timer3 TABLE 13
199. IINTERNALPOR TPWRT PWRT TIME OUT la TOST OST TIME OUT lt TPLL PLL TIME OUT INTERNAL RESET Note Tosr 1024 clock cycles TPLL 2 ms max First three stages of the PWRT timer 2006 Microchip Technology Inc DS39564C page 33 PIC18FXX2 NOTES DS39564C page 34 2006 Microchip Technology Inc PIC18FXX2 4 0 MEMORY ORGANIZATION There are three memory blocks in Enhanced MCU devices These memory blocks are Program Memory Data RAM Data EEPROM Data and program memory use separate busses which allows for concurrent access of these blocks Additional detailed information for FLASH program memory and Data EEPROM is provided in Section 5 0 and Section 6 0 respectively 4 1 Program Memory Organization A 21 bit program counter is capable of addressing the 2 Mbyte program memory space Accessing a location between the physically implemented memory and the 2 Mbyte address will cause a read of all 05 a NOP instruction The PIC18F252 and PIC18F452 each have 32 Kbytes of FLASH memory while the PIC18F242 and PIC18F442 have 16 Kbytes of FLASH This means that PIC18FX52 devices can store up to 16K of single word instructions and PIC18FX42 devices can store up to 8K of single word instructions The RESET vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h Figure 4 1 shows the Program Memory Map for PIC1
200. INTCONXx or PIRx registers will be affected to cause wake up 2 When the wake up is due to an interrupt and the GIEL or GIEH bit is set the PC is loaded with the interrupt vector 0008h or 0018h 3 When the wake up is due to an interrupt and the GIEL or GIEH bit is set the TOSU TOSH and TOSL are updated with the current value of the PC The STKPTR is modified to point to the next location in the hardware stack 4 See Table 3 2 for RESET value for specific condition unimplemented bit read as 0 value depends on condition 5 Bit 6 of PORTA LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only In all other Oscillator modes they are disabled and read 0 6 Bit 6 of PORTA LATA and TRISA are not available on all devices When unimplemented they are read 0 DS39564C page 28 2006 Microchip Technology Inc PIC18FXX2 TABLE 3 3 INITIALIZATION CONDITIONS FOR ALL REGISTERS CONTINUED MCLR Resets Register Appicabiedevices ONeron eset WETRereL Wakeup va Wor Stack Resets FSR1H 242 442 252 452 uuuu uuuu FSRIL 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu BSR 242 442 252 452 0000 0000 uuuu INDF2 242 442 252 452 N A N A N A POSTINC2 242 442 252 452 N A N A N A POSTDEC2 242 442 252 452 N A N A N A PREINC2 242 442 252 452 N
201. INUED File Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito POR BOR IPR2 EEIP BCLIP LVDIP TMR3IP CCP2IP 1 1111 83 PIR2 EEIF BCLIF LVDIF TMRBIF CCP2IF 0 0000 79 PIE2 EEIE BCLIE LVDIE TMR3IE CCP2IE 0 0000 81 IPR1 PSPIPB ADIP RCIP TXIP SSPIP CCP1IP TMR2IP 1111 1111 82 PIR1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRAIF 0000 0000 78 PIE1 PSPIEU ADIE RCIE TXIE SSPIE CCP1IE TMR2IE 0000 0000 80 TRISE IBF OBF IBOV PSPMODE Data Direction bits for PORTE 0000 111 98 TRISD Data Direction Control Register for PORTD 1111 1111 96 TRISC Data Direction Control Register for PORTC 1111 1111 93 TRISB Data Direction Control Register for PORTB 1111 1111 90 TRISA TRISA6 Data Direction Control Register for PORTA 111 1111 87 LATE Read PORTE Data Latch xxx 99 Write PORTE Data Latch Read PORTD Data Latch Write PORTD Data Latch 95 Read PORTC Data Latch Write PORTC Data Latch XXXX XXXX 93 LATB Read PORTB Data Latch Write PORTB Data Latch XXXX XXXX 90 LATA Read PORTA Data Latch Write PORTA Data Latch xxxx 87 PORTE Read PORTE pins Write PORTE Data Latch 000 99 PORTD Read PORTD pins Write PORTD Data Latch xxxx xxxx 95 PORTC Read PORTC pins Write PORTC Data Latch XXXX XX
202. IZATION WAVEFORM 55 E SCK 55 0 L CKE 0 1 i 20 S Write to i 55 J i SDO L X bite X X bito X SDI 2 SMP 0 i DT lt DD gt TG 1 1 SMP 0 SSPIF Interrupt SSPSR to SSPBUF 5 Next Q4 cycle ual 092 2 2006 Microchip Technology Inc DS39564C page 131 PIC18FXX2 FIGURE 15 5 SPI MODE WAVEFORM SLAVE MODE WITH 0 Optional SCK 0 CKE 0 SCK 1 CKE 0 Write to SSPBUF SDO ax bit7 X bite x bits x X bit3 bit2 x bitt gt bito soi lt lt gt gt 0 0 SMP 0 bit gt bio 020 0 f SMP 0 po SSPIF Interrupt FI 23 Next Q4 cycle SSPSR to i i i i after 921 SSPBUF FIGURE 15 6 SPI MODE WAVEFORM SLAVE MODE WITH CKE 1 s I SCK 1 1 Write to SSPBUF 00 bit7 X Ex bit5 T EX bit2 bit o gt 55 lt gt SMP 0 bit bio M o to a E SMP 0 SSPIF Interrupt Flag
203. L 7 0 MA VDD 4 5V 40 C to 125 C 0083 OSC2 CLKO 0 6 V 101 1 6 MA VDD 4 5V RC mode 40 C to 85 C DO83A 0 6 V 101 1 2 MA VDD 4 5V 40 C to 125 C VOH Output High Voltage DO90 ports VDD 0 7 V 3 0 mA VDD 4 5V 40 C to 85 C D090A 0 7 V 2 5 mA VDD 4 5V 40 C to 125 C 0092 OSC2 CLKO VDD 0 7 V 1 3 MA VDD 4 5V RC mode 40 C to 85 C DO92A VDD 0 7 V 1 0 mA VDD 4 5V 40 C to 125 C D150 Open Drain High Voltage 8 5 V 4 Capacitive Loading Specs on Output Pins D100 OSC2 pin 15 pF In XT HS and LP modes when external clock is used to drive OSC1 0101 Clo All I O pins and OSC2 50 pF meet the AC Timing in RC mode Specifications D102 SCL SDA 400 pF PC mode Note 1 In RC oscillator configuration the OSC1 CLKI pin is Schmitt Trigger input It is not recommended that the device be driven with an external clock while in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as current sourced by the pin 4 Parameter is characterized but not tested DS39564C page 266 2006 Microchip Technology Inc PIC18F
204. MICROCHIP PICISFXX2 Data Sheet High Performance Enhanced Flash Microcontrollers with 10 Bit A D 2006 Microchip Technology Inc DS39564C Note the following details of code protection feature on Microchip devices Microchip products meet the specification contained in their particular Microchip Data Sheet Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions There dishonest and possibly methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets Most likely the person doing so is engaged in theft of intellectual property Microchip is willing to work with the customer who is concerned about the integrity of their code Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as unbreakable Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of our products Attempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright Act If such acts allow unauthorized access to your software or other copyri
205. NED ARO MULTIPLY ROUTINE Example 7 3 shows the seguence to do a 16 x 16 MOVE ARCAM unsigned multiply Equation 7 1 shows the algorithm MULWE ARG ARGl ARG2 gt that is used The 32 bit result is stored in four registers PRODH PRODL RES3 RESO EQUATION 7 1 16x 16 UNSIGNED MULTIPLICATION ALGORITHM RES3 RESO ARGIH ARGIL e ARG2H ARG2L ARGIH e ARG2H e 216 ARGIH e ARG2L 28 ARGIL e ARG2H 28 ARGIL ARG2L 2006 Microchip Technology Inc DS39564C page 71 PIC18FXX2 EXAMPLE 7 3 16 x 16 UNSIGNED EXAMPLE 7 4 16 x 16 SIGNED MULTIPLY ROUTINE MULTIPLY ROUTINE OVF ARGIL W OVF ARGIL W ULWF ARG2L ARG1L ARG2L gt ULWF ARG2L ARGIL ARG2L gt PRODH PRODL PRODH PRODL OVFF PRODH RES1 OVFF PRODH RES1 OVFF PRODL RESO OVFF PRODL RESO OVF ARG1H W OVF ARGIH W ULWF ARG2H gt ULWF ARG2H ARGIH ARG2H gt PRODH PRODL PRODH PRODL OVFF PRODH RES3 OVFF PRODH RES3 OVFF PRODL RES2 OVFF PRODL RES2 OVF ARGIL W OVF ARGIL W ULWF ARG2H ARGIL ARG2H gt ULWF ARG2H ARGIL ARG2H gt PRODH PRODL PRODH PRODL OVF PRODL W OVF PRODL W ADDWF RES1 F Add cross ADDWF RES1 Add cross PRODH W products PRODH W products ADDWFC RES2 ADDWFC RES2 CLRF WREG CLRF WREG i ADDWFC RES3 ADDWFC RES3
206. ORVO 00 4 45 PIC18FXX2 BORV1 BORVO 1x BORV1 BORVO 01 4 16 BORV1 BORVO 00 4 45 Units 5 5 V 5 5 V 0 7 V 2 14 V 2 89 V 4 5 V 4 83 V N A V 4 5 V 4 83 V Legend Shading of rows is to assist in readability of the table Note 1 This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET without losing RAM data 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as I O pin Operating temperature 40 x TA 85 for industrial 40 C x TA 125 for extended Conditions HS XT RC and LP Osc mode See Section 3 1 Power on Reset for details V ms See Section 3 1 Power on Reset for details 85 C gt T gt 25 C Not in operating voltage range of device 2006 Microchip Technology Inc DS39564C page 261 18F XX2 22 1 DC Characteristics PIC18FXX2 Industrial Extended PIC18LFXX2 Industrial Continued PIC18LFXX2 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 C lt TA lt 85 for industrial PIC18FXX2 Standard Operating Conditions unless otherwise stated Param No Industrial Extended Operating temperature 40 C lt TA lt 85 for industrial 40 C lt TA lt 125 for extended Symbol Characteristic Min Max Units Conditions IDD Supply 2
207. Protection bit 1 Configuration registers 300000 3000FFh not write protected 0 Configuration registers 300000 3000FFh write protected Note This bit is read only and cannot be changed in User mode bit4 0 Unimplemented Read Legend R Readable bit C Clearable bit U Unimplemented bit read as V n Value when device is unprogrammed u Unchanged from programmed state DS39564C page 200 2006 Microchip Technology Inc PIC18FXX2 REGISTER 19 10 CONFIGURATION REGISTER 7 LOW CONFIG7L BYTE ADDRESS 30000Ch U 0 U 0 U 0 U 0 R C 1 R C 1 R C 1 R C 1 EBTR3U EBTR2 1 EBTRO bit 7 bit O bit 7 4 Unimplemented Read as bit 3 EBTR3 Table Read Protection bit 1 Block 3 006000 007FFFh not protected from Table Reads executed in other blocks Block 3 006000 007FFFh protected from Table Reads executed in other blocks bit 2 EBTR2 Table Read Protection bit 1 Block 2 004000 005FFFh not protected from Table Reads executed in other blocks Block 2 004000 005FFFh protected from Table Reads executed in other blocks bit 1 EBTR1 Table Read Protection bit 1 Block 1 002000 003FFFh not protected from Table Reads executed in other blocks Block 1 002000 003FFFh protected from Table Reads executed in other blocks bit O EBTRO Table Read Protection bit 1 Block 0 000200h 001FFFh not protected from Table Reads executed in
208. R HIGH point to buffer MOVWF FSROH MOVLW ADDR LOW MOVWF FSROL MOVLW NEW DATA LOW update buffer word MOVWF POSTINCO MOVLW DATA HIGH MOVWF NDFO ERASE BLOCK MOVLW CODE ADDR UPPER load TBLPTR with the base MOVWF BLPTRU address of the memory block MOVLW CODE ADDR HIGH MOVLW CODE ADDR LOW BSF EECONI1 EEPGD point to FLASH program memory BCF 1 5 access FLASH program memory BSF EECON1 WREN enable write to memory BSF EECON1 FREE enable Row Erase operation BCF INTCON GIE disable interrupts MOVLW 55h MOVWF EECON2 write 55h MOVLW AAh MOVWF EECON2 write AAh BSF EECON1 WR Start erase CPU stall BSF INTCON GIE re enable interrupts TBLRD dummy read decrement WRITE BUFFER BACK MOVLW 8 number of write buffer groups of 8 bytes MOVWF COUNTER HI MOVLW BUFFER ADDR HIGH point to buffer MOVWF FSROH MOVLW BUFFER ADDR LOW MOVWF FSROL PROGRAM LOOP MOVLW 8 number of bytes in holding register MOVWF COUNTER WRITE WORD TO HREGS MOVF POSTINCO W get low byte of buffer data MOVWF TABLAT present data to table latch TBLWT write data perform a short write to internal TBLWT holding register DECFSZ COUNTER loop until buffers are full BRA WRITE WORD TO HREGS DS39564C page 62 2006 Microchip Technology Inc PIC18FXX2 EXAMPLE 5 3 WRITING TO FLASH PROGRAM MEMORY CONTINUED 5 5 2 WRITE VERIFY 2006 Micro
209. R TRANSMIT AND ACKNOWLEDGE Data changes while SCL 0 SDA SDA line pulled low by another source SDA released by master A Sample SDA While SCL is high data doesn t match what is driven by the master Bus collision has occurred BCLIF SCL Set bus collision interrupt BCLIF 2006 Microchip Technology Inc DS39564C page 159 PIC18FXX2 15 4 17 1 Bus Collision During START Condition During a START condition a bus collision occurs if a SDA or SCL are sampled low at the beginning of the START condition Figure 15 26 b SCL is sampled low before SDA is asserted low Figure 15 27 During a START condition both the SDA and the SCL pins are monitored If the SDA pin is already low or the SCL pin is already low then all of the following occur the START condition is aborted the BCLIF flag is set and the MSSP module is reset to its IDLE state Figure 15 26 The START condition begins with the SDA and SCL pins de asserted When the SDA pin is sampled high the baud rate generator is loaded from SSPADD lt 6 0 gt and counts down to 0 If the SCL pin is sampled low while SDA is high a bus collision occurs because it is assumed that another master is attempting to drive a data 1 during the START condition FIGURE 15 26 If the SDA pin is sampled low during this count the BRG is reset and the SDA line is asserted early Figure 15 28 If
210. R register occurs in one TCY the TXREG register is empty and flag bit TXIF PIR1 lt 4 gt is set This interrupt can be enabled disabled by setting clearing enable bit TXIE PIE1 lt 4 gt Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in soft ware It will reset only when new data is loaded into the TXREG register While flag bit TXIF indicated the sta tus of the TXREG register another bit TRMT TXSTA lt 1 gt shows the status of the TSR register Sta tus bit TRMT is a read only bit which is set when the TSR register is empty No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty Note 1 The TSR register is not mapped in data memory so it is not available to the user 2 Flag bit TXIF is set when enable bit is set To set up an asynchronous transmission 1 Initialize the SPBRG register for the appropriate baud rate If a high speed baud rate is desired set bit BRGH Section 16 1 2 Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN 3 If interrupts are desired set enable bit 4 f 9 bit transmission is desired set transmit bit TX9 Can be used as address data bit 5 Enable the transmission by setting bit TXEN which will also set bit TXIF 6 f 9 bit transmission is selected the ninth bit should be loaded in bit TX9D 7 Load data to the TXR
211. RE 23 24 TYPICAL AND MAXIMUM VoL vs lot 40 C 125 2 5 Typical statistical mean 25 C Maximum mean 30 40 C to 125 C Minimum mean 40 C to 125 C lo mA DS39564C page 300 2006 Microchip Technology Inc PIC18FXX2 FIGURE 23 25 MINIMUM AND MAXIMUM Vin vs ST INPUT 40 C 125 C 4 0 Typical statistical mean 25 C 35 Maximum mean 30 40 C to 125 C Minimum mean 30 40 C to 125 C 3 0 2 5 2 0 VIN V 1 5 1 0 0 5 0 0 V FIGURE 23 26 MINIMUM AND MAXIMUM VN vs TTL INPUT 40 C TO 125 C 1 6 Typical statistical mean 25 C 1 4 Maximum mean 30 40 C to 125 C Minimum mean 30 40 C to 125 C VTH Max VTH Min 0 8 V 0 6 0 4 0 2 0 0 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 V A EE OD 2006 Microchip Technology Inc DS39564C page 301 PIC18FXX2 FIGURE 23 27 MINIMUM AND MAXIMUM Vin vs I C INPUT 40 C TO 125 C 3 5 VIH Max Typical statistical mean 25 C Maximum mean 36 40 C to 125 C Minimum mean 36 40 C to 125 C Vin V V FIGURE 23 28 A D NON LINEARITY vs VREFH
212. REGISTER 6LOW CONFIG6L BYTE ADDRESS 30000Ah U 0 U 0 U 0 U 0 R C 1 R C 1 R C 1 R C 1 WRT3 WRT21 wRT1 WRTO bit 7 bit O bit7 4 Unimplemented Read as bit 3 WRT3 Write Protection bit 1 Block 3 006000 007FFFh not write protected Block 3 006000 007FFFh write protected bit 2 WRT2 Write Protection bit 1 Block 2 004000 005FFFh not write protected Block 2 004000 005FFFh write protected bit 1 WRT1 Write Protection bit 1 Block 1 002000 003FFFh not write protected Block 1 002000 003FFFh write protected bit O WRTO Write Protection bit 1 Block 0 000200h 001FFFh not write protected o Block 0 000200h 001FFFh write protected Note 1 Unimplemented PIC18FX42 devices maintain this bit set Legend R Readable bit Clearable bit U Unimplemented bit read as V Value when device is unprogrammed u Unchanged from programmed state REGISTER 19 9 CONFIGURATION REGISTER 6HIGH CONFIG 6H BYTE ADDRESS 30000B h R C 1 R C 1 C 1 U 0 U 0 U 0 U 0 U 0 WRTD WRTB WRTC bit 7 bit 0 bit 7 WRTD Data EEPROM Write Protection bit 1 gt Data EEPROM not write protected 0 Data EEPROM write protected bit 6 WRTB Boot Block Write Protection bit 1 Boot Block 000000 0001FFh not write protected 0 Boot Block 000000 0001FFh write protected bit 5 WRTC Configuration Register Write
213. Reg write Word Write Word2 5 TXIF bit NEN interrupt B a muc xs 3 s TXEN bit DL NES r E 1 Note Sync Master mode SPBRG 0 Continuous transmission of two 8 bit words FIGURE 16 7 SYNCHRONOUS TRANSMISSION THROUGH TXEN RC7 RX DT pin X bto Y X bit bite X RC6 TX CK pin M N g Write to TXREG reg TXIF bit L bit TXEN bit TN M an 2006 Microchip Technology Inc DS39564C page 177 PIC18FXX2 gt 16 3 2 USART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected reception is enabled by setting either enable bit SREN If interrupts are desired set enable bit RCIE If 9 bit reception is desired set bit RX9 6 single reception is required set bit For continuous reception set bit CREN 5 lt 5 gt enable bit CREN RCSTA lt 4 gt Data is 7 Interrupt flag bit will be set when reception sampled on the RC7 RX DT pin on the edge of is complete and an interrupt will be generated if the clock If enable bit SREN is set only a single word the enable bit RCIE was set is received If enable bit CREN is set the reception is 8 Read the RCSTA register to get the ninth bit if continuous until CREN is cleared If both bits are set enabled and determine if any error o
214. Register 4 3 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 77 Bit is set Bit is cleared Bit is unknown OX lt lt lt DS39564C page 84 2006 Microchip Technology Inc PIC18FXX2 8 6 INTO Interrupt External interrupts on the RBO INTO RB1 INT1 and RB2 INT2 pins are edge triggered either rising if the corresponding INTEDGx bit is set in the 2 reg ister or falling if the INTEDGx bit is clear When a valid edge appears on the RBX INTx pin the corresponding flag bit INTXF is set This interrupt can be disabled by clearing the corresponding enable bit INTxE Flag bit INTxF must be cleared in software in the Interrupt Ser vice Routine before re enabling the interrupt exter nal interrupts INTO INT1 and INT2 can wake up the processor from SLEEP if bit INTxE was set prior to going into SLEEP If the global interrupt enable bit GIE is set the processor will branch to the interrupt vector following wake up Interrupt priority for INT1 and INT2 is determined by the value contained in the interrupt priority bits INT1IP INTCON3 6 and INT2IP INTCON3 lt 7 gt There is no priority bit associated with INTO It is always a high priority interrupt source EXAMPLE 8 1 MOVWF W TEMP MOVFF STATUS STATUS TEMP MOVFF BSR BSR TEMP USER ISR CODE MOVFF BSR TEMP BSR MOVF W TEMP W MOVFF STATUS TEMP STATUS Restore BSR Restor
215. SCL line The value of register SSPSR 7 1 is compared to the value of the SSPADD register The address is compared on the falling edge of the eighth clock SCL pulse If the addresses match and the BF and SSPOV bits are clear the following events occur 1 The SSPSR register value is loaded into the SSPBUF register 2 The buffer full bit BF is set An ACK pulse is generated 4 MSSPinterrupt flag bit SSPIF PIR1 3 is set interrupt is generated if enabled on the falling edge of the ninth SCL pulse In 10 bit Address mode two address bytes need to be received by the slave The five Most Significant bits MSbs of the first address byte specify if this is a 10 bit address Bit R W SSPSTAT lt 2 gt must specify a write so the slave device will receive the second address byte For a 10 bit address the first byte would equal 11110 9 8 0 where AJ and are the two MSbs of the address The sequence of events for 10 bit address is as follows with steps 7 through 9 for the slave transmitter 1 Receive first high byte of Address bits SSPIF BF and bit UA SSPSTAT lt 1 gt are set 2 Update the SSPADD register with second low byte of Address clears bit UA and releases the SCL line 3 Read the SSPBUF register clears bit BF and clear flag bit SSPIF 4 Receive second low byte of Address bits SSPIF BF and UA are set 5 Update the SSPADD register with the first high byte of Address
216. SP read write interrupt Disables the PSP read write interrupt bit 6 ADIE A D Converter Interrupt Enable bit 1 Enables the A D interrupt 0 Disables the A D interrupt bit 5 RCIE USART Receive Interrupt Enable bit 1 Enables the USART receive interrupt 0 Disables the USART receive interrupt bit 4 TXIE USART Transmit Interrupt Enable bit 1 Enables the USART transmit interrupt 0 Disables the USART transmit interrupt bit 3 SSPIE Master Synchronous Serial Port Interrupt Enable bit 1 Enables the MSSP interrupt 0 Disables the MSSP interrupt bit 2 CCP1 Interrupt Enable bit 1 Enables the CCP1 interrupt 0 Disables the CCP1 interrupt bit 1 TMR2IE TMR2 to PR2 Match Interrupt Enable bit 1 Enables the TMR2 to PR2 match interrupt 0 Disables the TMR2 to PR2 match interrupt bit O TMRIIE TMR1 Overflow Interrupt Enable bit 1 Enables the TMR1 overflow interrupt Disables the TMR1 overflow interrupt Note 1 This bit is reserved on PIC18F2X2 devices always maintain this bit clear bit O Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 1 Bit is set Bit is cleared x Bit is unknown DS39564C page 80 2006 Microchip Technology Inc PIC18FXX2 REGISTER 8 7 bit 7 5 bit 4 bit 3 bit 2 bit 1 bit 0 PIE 2 PERIPHERAL INTERRUPT ENABLE REGISTER 2 U 0 U 0 U 0 R W 0 R W 0 R
217. SPBUF is empty In Receive mode 1 Data transmit in progress does not include the and STOP bits SSPBUF is full 0 Data transmit complete does not include the ACK and STOP bits SSPBUF is empty Legend R Readable bit W Writable bit U Unimplemented bit read as Value at POR 7 Bit is set 0 Bit is cleared x Bit is unknown 2006 Microchip Technology Inc DS39564C page 135 PIC18FXX2 REGISTER 15 4 55 1 MSSP CONTROL REGISTER1 PC MODE R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPMI SSPMO bit 7 bit 0 bit 7 WCOL Write Collision Detect bit In Master Transmit mode 1 A write to the SSPBUF register was attempted while the 2 conditions were not valid for a transmission to be started must be cleared in software 0 No collision In Slave Transmit mode 1 The SSPBUF register is written while it is still transmitting the previous word must be cleared in software 0 No collision In Receive mode Master or Slave modes This is a don t care bit bit 6 SSPOV Receive Overflow Indicator bit In Receive mode 1 A byte is received while the SSPBUF register is still holding the previous byte must be cleared in software 0 No overflow In Transmit mode This is a don t care bit in Transmit mode bit 5 SSPEN Synchronous Serial Port Enable bit 1 Enables the serial port and configures the SDA and SCL pins as the seri
218. Set ADIE bit Set GIE bit Set PEIE bit 3 Wait the required acquisition time 4 Start conversion Set GO DONE bit ADCONO FIGURE 17 2 ANALOG INPUT MODEL 5 Wait for A D conversion to complete by either Polling for the GO DONE bit to be cleared interrupts disabled OR Waiting for the A D interrupt 6 Read A D Result registers ADRESH ADRESL clear bit ADIF if required 7 For next conversion go to step 1 or step 2 as required The A D conversion time per bit is defined as TAD A minimum wait of 2 TAD is required before the next acquisition starts 17 1 A D Acquisition Requirements For the A D converter to meet its specified accuracy the charge holding capacitor CHOLD must be allowed to fully charge to the input channel voltage level The analog input model is shown in Figure 17 2 The source impedance Rs and the internal sampling switch Rss impedance directly affect the time required to charge the capacitor CHOLD The sampling switch Rss impedance varies over the device voltage VDD The source impedance affects the offset voltage at the analog input due to pin leakage current The maximum recommended impedance for analog sources is 2 5 After the analog input channel is selected changed this acquisition must be done before the conversion can be started When the conversion is started the hold ing capacitor is disconnected from the input pin VDD LEAKAGE
219. Synchronous Clock see related RX DT RC7 RX DT 18 18 RC7 ST Digital RX ST USART Asynchronous Receive DT O ST USART Synchronous Data see related TX CK Vss 8 19 8 19 P Ground reference for logic and I O pins VDD 20 20 P Positive supply for logic and I O pins Legend TTL TTL compatible input ST Schmitt Trigger input with CMOS levels O Output OD Open Drain no P diode to VDD DS39564C page 12 CMOS CMOS compatible input or output Input Power 2006 Microchip Technology Inc PIC18FXX2 TABLE 1 3 PIC18F4X2 PINOUT 1 0 DESCRIPTIONS Pin Number Pin Buffer cd Pin Name Description DIP PLCC Type Type MCLR VPP 1 2 18 Master Clear input or high voltage ICSP programming enable pin MCLR ST Master Clear Reset input This pin is an active low RESET to the device VPP ST High voltage ICSP programming enable pin NC These pins should be left unconnected OSC1 CLKI 13 14 30 Oscillator crystal or external clock input OSC1 ST Oscillator crystal input or external clock source input ST buffer when configured in RC mode CMOS otherwise CLKI CMOS External clock source input Always associated with pin function OSC1 See related OSC1 CLKI OSC2 CLKO pins OSC2 CLKO RA6 14 15 31 Oscillator crystal or clock output OSC2 O Oscillator crystal output Connects to crystal or resonator in Crystal Oscillator mode
220. T Xu PORTE RE2 RE1 REO 000 000 LATE LATE Data Output bits XXX uuu TRISE IBF OBF IBOV PSPMODE PORTE Data Direction bits 0000 111 0000 111 INTCON GIE PEIE TMROIF INTOIE RBIE TMROIF INTOIF RBIF 0000 000x 0000 000u GIEH GIEL PIR1 PSPIF ADIF RCIF TXIF SSPIF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE TMR2IE TMRIIE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP TMR2IP 0000 0000 0000 0000 ADCON1 ADFM ADCS2 PCFG3 PCFG2 PCFGI PCFGO 00 0000 00 0000 Legend x unknown u unchanged unimplemented read as Shaded cells are not used by the Parallel Slave Port 2006 Microchip Technology Inc DS39564C page 101 PIC18FXX2 NOTES DS39564C page 102 2006 Microchip Technology Inc PIC18FXX2 10 0 TIMERO MODULE The TimerO module has the following features Software selectable as an 8 bit or 16 bit timer counter Readable and writable Dedicated 8 bit software programmable prescaler including the prescale selection Clock source selectable to be external or internal Interrupt on overflow from FFh to 00h in 8 bit mode and FFFFh to 0000h in 16 bit mode Edge select for external clock REGISTER 10 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 0 Figure 10 1 shows a simplified block diagram of th
221. T1OSI D043 OSC1 RC 0 9 VDD VDD V liL Input Leakage Current D060 ports 02 1 uA VSS lt VPIN lt VDD Pin at hi impedance DO61 MCLR 1 Vss lt lt VDD 0063 OSC1 i1 HA Vss VPIN lt VDD IPU Weak Pull up Current 0070 IPURB PORTB weak pull up current 50 450 VDD 5V VSS Note 1 In RC oscillator configuration the OSC1 CLKI pin is a Schmitt Trigger input It is not recommended that the PICmicro device be driven with an external clock while in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as current sourced by the pin 4 Parameter is characterized but not tested i a ut 2006 Microchip Technology Inc DS39564C page 265 PIC18FXX2 22 2 DC Characteristics PIC18FXX2 Industrial Extended PIC18LFXX2 Industrial Continued DC CHARACTERISTICS Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt TA lt 85 C for industrial 40 C lt TA lt 125 C for extended Symbol Characteristic Min Max Units Conditions VOL Output Low Voltage DO80 ports 0 6 V 10 8 5 MA VDD 4 5V 40 C to 85 C DO80A 0 6 V lo
222. Tcv 30 ns 72A Single Byte 40 ns Note 1 73 TdiV2scH Setup time of SDI data input to SCK edge 100 ns TdiV2scL 73A TB2B Last clock edge of Byte1 to the first clock edge of Byte2 1 5 TCY 40 ns Note 2 74 TscH2diL Hold time of SDI data input to SCK edge 100 ns TscL2diL 75 TdoR SDO data output rise time PIC18F XXX 25 ns PIC18LFXXX 60 ns 2 76 TdoF SDO data output fall time PIC18F XXX 25 ns PIC18LFXXX 60 ns VDD 2 77 TssH2doZ SS to 500 output hi impedance 10 50 ns 78 TscR SCK output rise time Master mode 25 ns PIC18LFXXX 60 ns VDD 2V 79 TscF SCK output fall time Master mode PIC18F XXX 25 ns PIC18LFXXX 60 ns VDD 2 80 TscH2doV SDO data output valid after SCK edge PIC18F XXX 50 ns st PIC18LFXXX 150 ns 2V 83 TscH2ssH SS f after SCK edge 1 5 TCY 40 ns TscL2ssH Note 1 Reguires the use of Parameter 73A 2 Only if Parameter 71A and 72A are used DS39564C page 280 2006 Microchip Technology Inc PIC18FXX2 FIGURE 22 15 EXAMPLE SPI SLAVE MODE TIMING 1 Note 82 gt Refer to Figure 22 4 for load conditions TABLE 22 14 EXAMPLE SPISLAVE MODE REQUIREMENTS CKE 1 Note 1 Requires the use of Parameter 73A 2 Only if Parameter 71A and 72A are used
223. The ACK pulse vill be sent on the ninth bit and pin RC3 SCK SCL is held low regardless of SEN see Clock Stretching Section 15 4 4 for more detail By stretching the clock the master will be unable to assert another clock pulse until the slave is done preparing the transmit data The transmit data must be loaded into the SSPBUF register which also loads the SSPSR register Then pin RC3 SCK SCL should be enabled by setting bit CKP 55 1 lt 4 gt The eight data bits are shifted out on the falling edge of the SCL input This ensures that the SDA signal is valid during the SCL high time Figure 15 9 The ACK pulse from the master receiver is latched on the rising edge of the ninth SCL input pulse If the SDA line is high not ACK then the data transfer is com plete In this case when the ACK is latched by the slave the slave logic is reset resets SSPSTAT regis ter and the slave monitors for another occurrence of the START bit If the SDA line was low the next transmit data must be loaded into the SSPBUF register Again pin RC3 SCK SCL must be enabled by setting bit CKP An MSSP interrupt is generated for each data transfer byte The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte The SSPIF bit is set on the falling edge of the ninth clock pulse 2006 Microchip Technology Inc DS39564C page 139 0 NAS 0 0 1980 jou seop
224. V Vf W e Vel wf is jues jou SI MOV Jejse N sng lt 11 11 I I xov 04 XraXzaXeaXraYsaXoaYza ivXzvXevyrvXsvXSv 2v 4 N vas I T Load N3d LGMOV vas eouenbes eDpe wouxoy uelis NIMOY 195 1 t NADH 1xou 0 LGMOV vas J8JSEIN MOV p 129 9 NADH 5 OAEIS MOV L lt E gt ZNODASS Ag 0 lt G gt ZNOOdSS LGMOV vas eouenbes efpe wouxoy LEJS 01 Sy eNOOGSS 01 19419991 se 4 L ME SseJppy 1 LINX 5 19Y 4N9dSS 01 0 NAS uonipuo LHYLS NAS lt 0 gt ZNOOdSS DS39564C page 157 2006 Microchip Technology Inc PIC18FXX2 15 4 12 ACKNOWLEDGE SEQUENCE 15 4 13 STOP CONDITION TIMING TIMING A STOP bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive transmit by setting the STOP sequence enable Acknowledge sequence enable bit bit PEN SSPCON2 2 At the end of a receive trans SSPCON2 lt 4 gt When this bit is set the SCL p
225. V 40 C to 85 DO22B Low Voltage Detect 33 40 pA 06 4 2 25 PIC18FXX2 33 50 uA 4 2V 40 C to 85 33 65 uA VDD 4 2V 40 C to 125 C 0025 AITMR Oscillator 5 2 30 uA 2 0V 25 C PIC18LFXX2 5 2 40 pA 2 0V 40 C to 85 C 6 5 50 4 2V 40 C to 85 C 0025 Oscillator 6 5 40 LA 4 2V 25 C PIC18FXX2 6 5 50 pA 4 2V 40 C to 85 C 6 5 65 4 2V 40 C to 125 C Legend Shading of rows is to assist in of the table Note 1 This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET without losing RAM data 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as pin loading and switching rate oscillator type internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active Operation mode are OSC1 external square wave from rail to rail all I O pins tri stated pulled to VDD MCLR VDD WDT enabled disabled as specified The power down current in SLEEP mode does not depend on the oscillator type Power down current is measured with the part in SLEEP mode with all I O pins in hi impedance state and tied to VDD or Vss and all features that add delta current disabled such
226. VBOR set to 2 7 01 VBOR set to 4 2V 00 VBOR set to 4 5V bit 1 BOREN Brown out Reset Enable bit 1 Brown out Reset enabled 0 Brown out Reset disabled bit O PWRTEN Power up Timer Enable bit 1 PWRT disabled 0 z PWRT enabled Legend Readable bit Programmable bit U Unimplemented bit read as 0 Value when device is unprogrammed u Unchanged from programmed state REGISTER 19 3 CONFIGURATION REGISTER 2HIGH CONFIG2H BYTE ADDRESS 300003h 0 0 0 0 0 0 0 0 R P 1 R P 1 WDTPS2 WDTPS1 WDTPSO WDTEN bit 7 bit 0 bit 7 4 Unimplemented Read as V bit 3 1 WDTPS2 WDTPSO Watchdog Timer Postscale Select bits 111 1 128 110 1 64 101 1 32 100 1 16 011 1 8 010 1 4 001 1 2 000 1 1 bit O WDTEN Watchdog Timer Enable bit 1 gt WDT enabled WDT disabled control is placed on the SWDTEN bit Legend R Readable bit Programmable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state 2006 Microchip Technology Inc DS39564C page 197 PIC18FXX2 REGISTER 19 4 CONFIGURATION REGISTER 3 HIGH CONFIG3H BYTE ADDRESS 300005h U 0 U 0 U 0 U 0 U 0 U 0 U 0 R P 1 CCP2MX bit 7 bit 0 bit 7 1 Unimplemented Read as 0 bit O CCP2MX CCP2 Mux bit 1 CCP2 input output is multiplexed with RC1
227. VDD and Vss DS39564C page 95 2006 Microchip Technology Inc PIC18FXX2 TABLE 9 7 PORTD FUNCTIONS Name Bit Buffer Type Function RDO PSPO bito ST TTLU Input output port pin or parallel slave port bitO RD1 PSP1 bit1 ST TTLU Input output port pin or parallel slave port bit1 RD2 PSP2 bit2 ST TTLU Input output port pin or parallel slave port bit2 RD3 PSP3 bit3 ST TTLU Inpu output port pin or parallel slave port bits RD4 PSP4 bit4 ST TTLU Input output port pin or parallel slave port bit4 RD5 PSP5 bit5 sT rrL Input output port pin or parallel slave port bit5 RD6 PSP6 bite ST TTLU Input output port pin or parallel slave port 616 RD7 PSP7 bit7 ST TTLU Input output port pin or parallel slave port bit7 Legend ST Schmitt Trigger input TTL TTL input Note 1 Input buffers are Schmitt Triggers when mode and TTL buffer when in Parallel Slave Port mode TABLE 9 8 SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Value on Value on Name Bit7 Bit6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O RESETS PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RDO XXXX XXXX uuuu uuuu LATD LATD Data Output Register XXXX XXXX uuuu uuuu TRISD PORTD Data Direction Register 1111 1111 1111 1111 TRISE IBF OBF IBOV PSPMODE PORTE Data Direction bits 0000 111 0000 111 Legend x unknown u unchanged unimplemented read as Shad
228. W 0 R W 0 R W 0 EEIE BCLIE LVDIE TMRSIE CCP2IE bit 7 bit O Unimplemented Read as 0 EEIE Data EEPROM FLASH Write Operation Interrupt Enable bit 1 Enabled Disabled BCLIE Collision Interrupt Enable bit 1 Enabled Disabled LVDIE Low Voltage Detect Interrupt Enable bit 1 Enabled Disabled TMR3IE TMR3 Overflow Interrupt Enable bit 1 Enables the TMR3 overflow interrupt Disables the TMR3 overflow interrupt CCP2IE CCP2 Interrupt Enable bit 1 Enables the CCP2 interrupt Disables the CCP2 interrupt Legend R Readable bit W Writable bit n Value at POR 1 Bit is set U Unimplemented bit read as 0 Bit is cleared X Bit is unknown 2006 Microchip Technology Inc DS39564C page 81 PIC18FXX2 8 4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts Due to tne number of periph eral interrupt sources there are two Peripheral Inter rupt Priority Registers IPR1 IPR2 The operation of the priority bits reguires that the Interrupt Priority DS39564C page 82 2006 Microchip Technology Inc PIC18FXX2 REGISTER 8 9 IPR2 PERIPHERAL INTERRUPT PRIORITY REGISTER 2 U 0 U 0 U 0 R W 1 R W 1 R W 1 R W 1 R W 1 EEIP BCLIP LVDIP TMRSIP CCP2IP bit 7 bit O bit 7 5 Unimplemented Read as 0 bit 4 EEIP Data EEPROM FLASH Write Operation Interrupt Priority bit 1 High priority
229. XX Description No operation Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No No No operation operation operation Example None 2006 Microchip Technology Inc DS39564C page 239 PIC18FXX2 POP Pop Top of Return Stack Syntax label POP Operands None Operation TOS bit bucket Status Affected None Encoding 0000 0000 0000 0110 Description The TOS value is pulled off the return stack and is discarded The TOS value then becomes the previ ous value that was pushed onto the return stack This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No POP TOS No operation value operation Example POP GOTO NEW Before Instruction TOS 0031A2h Stack 1 level down 014332 After Instruction TOS 0143328 NEW PUSH Push Top of Return Stack Syntax label PUSH Operands None Operation PC 2 gt TOS Status Affected None Encoding 0000 0000 0000 0101 Description The PC 2 is pushed onto the top of the return stack The previous TOS value is pushed down on the stack This instruction allows to implement a software stack by modifying TOS and then push it onto the return stack Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode PC 2 No No Example onto return stack operation operation PUSH Before Instruction
230. XX 93 PORTB Read PORTB pins Write PORTB Data Latch XXXX XXXX 90 PORTA Read PORTA pins Write PORTA Data Latch x0x 0000 87 Legend unknown u unchanged unimplemented value depends on condition Note 1 RA6 and associated bits are configured as port pins in and ECIO Oscillator mode only and read 0 in all other Oscillator modes 2 Bit 21 of the TBLPTRU allows access to the device configuration bits 3 These registers and bits are reserved on the PIC18F2X2 devices always maintain these clear DS39564C page 48 2006 Microchip Technology Inc PIC18FXX2 4 10 Access Bank The Access Bank is an architectural enhancement which is very useful for C compiler code optimization The techniques used by the C compiler may also be useful for programs written in assembly This data memory region can be used for Intermediate computational values Local variables of subroutines Faster context saving switching of variables Common variables Faster evaluation control of SFRs no banking The Access Bank is comprised of the upper 128 bytes in Bank 15 SFRs and the lower 128 bytes in Bank 0 These two sections will be referred to as Access RAM High and Access RAM Low respectively Figure 4 6 and Figure 4 7 indicate the Access RAM areas A bit in the instruction word specifies if the operation is to occur in the bank specified by the BSR register or in the Access Bank This bit is
231. XX2 FIGURE 22 3 LOW VOLTAGE DETECT CHARACTERISTICS VDD Jia ete LVDIF can be VLVD cleared in software LVDIF set by hardware TABLE 22 1 LOW VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt TA lt 85 C for industrial 40 C lt 125 for extended Symbol Characteristic Min Typ Max Units Conditions D420 LVD Voltage on LVV 0001 1 98 2 06 2 14 gt 25 C as high to 0010 2 18 2 27 2 36 gt 25 OW LVV 0011 2 37 2 47 2 57 gt 25 C 0100 2 48 2 58 2 68 0101 2 67 2 78 2 89 0110 2 77 2 89 3 01 0111 2 98 3 1 3 22 1000 3 27 3 41 3 55 1001 3 47 3 61 3 75 1010 3 57 3 72 3 87 1011 3 76 3 92 4 08 1100 3 96 4 13 4 3 1101 4 16 4 33 4 5 1110 4 45 4 64 4 83 L lt lt lt lt lt lt lt lt lt I lt lt lt lt 2006 Microchip Technology Inc DS39564C page 267 PIC18FXX2 TABLE 22 2 MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt TA lt 85 C for industrial 40 lt lt 125 for extended
232. a RAM access bit a 0 RAM location in Access RAM BSR register is ignored 1 RAM bank is specified by BSR register bbb Bit address within an 8 bit file register 0 to 7 BSR Bank Select Register Used to select the current RAM bank d Destination select bit 0 store result in WREG d 1 store result in file register f dest Destination either the WREG register or the specified register file location f 8 bit Register file address 0x00 to OxFF fs 12 bit Register file address 0x000 to OxFFF This is the source address fd 12 bit Register file address 0x000 to OxFFF This is the destination address k Literal field constant data or label may be either an 8 bit 12 bit or a 20 bit value label Label name mm The mode of the TBLPTR register for the Table Read and Table Write instructions Only used with Table Read and Table Write instructions No Change to register such as TBLPTR with Table reads and writes Post Increment register such TBLPTR with Table reads and writes Post Decrement register such as TBLPTR with Table reads and writes Pre Increment register such as TBLPTR with Table reads and writes n The relative address 25 complement number for relative branch instructions or the direct address for Call Branch and Return instructions PRODH Product of Multiply high byte PRODL Product of Multiply low byte 8 Fast Call Return mode select bit s 0 do not update into from shadow registers s
233. a bit to the SDA line parameter 102 parameter 107 1000 250 1250 ns for 100 kHz mode before the SCL line is released 2006 Microchip Technology Inc DS39564C page 285 PIC18FXX2 FIGURE 22 20 USART SYNCHRONOUS TRANSMISSION MASTER SLAVE TIMING RCG TXICK A pin T 121 T 121 RC7 RX DT D 4 pin K i 120 lt Note Refer to Figure 22 4 for load conditions TABLE 22 19 USART SYNCHRONOUS TRANSMISSION REOUIREMENTS Symbol Characteristic Min Max Units Conditions 120 TckH2dtV SYNC XMIT MASTER 8 SLAVE Clock high to data out valid PIC18FXXX 50 ns PIC18LFXXX 150 ns VDD 2V 121 Tekr Clock out rise time and fall time PIC18FXXX 25 ns Master mode PICIBLEXXX 60 ns VDD 2V 122 Tdtr Data out rise time and fall time PIC18FXXX mE 25 ns PIC18LFXXX 60 ns VDD 2V FIGURE 22 21 USART SYNCHRONOUS RECEIVE MASTER SLAVE TIMING RC6 TX CK 125 124 5 RC7 RX DT 2 X x 126 gt Note Refer to Figure 22 4 for load conditions TABLE 22 20 USART SYNCHRONOUS RECEIVE REQUIREMENTS es Symbol Characteristic Min Units Conditions 125 TdtV2ckl SYNC MASTER 8 SLAVE Data hold before CK 4 DT hold time 10 ns 126 Data hold after J DT hold time PIC18FXXX 15 ns PIC18LFXXX 20 ns 2
234. al bank STATUS TEMP located anywhere BSR located anywhere 2006 Microchip Technology Inc DS39564C page 85 PIC18FXX2 NOTES DS39564C page 86 2006 Microchip Technology Inc PIC18FXX2 9 0 1 0 PORTS EXAMPLE 9 1 INITIALIZING PORTA Initialize PORTA by clearing output data latches CLRF PORTA Depending on the device selected there are either five ports or three ports available Some pins of the O ports are multiplexed with an alternate function from CLRF LATA Alternate method the peripheral features on the device In general when to clear output a peripheral is enabled that pin may not be used as a data latches general purpose pin MOVLW 0x07 Configure A D i MOVWF ADCON1 for digital inputs Each port has three registers for its operation These MOTEN ORCE Value a t P registers are initialize data TRIS register data direction register direction MOVWF TRISA Set RA lt 3 0 gt as inputs PORT register reads the levels on the pins of the device LAT register output latch RA 5 4 as outputs The data latch LAT register is useful for read modify write operations on the value that the I O pins driving FIGURE 9 1 BLOCK DIAGRAM OF RA3 RAOAND PINS 9 1 PORTA TRISA and LATA Registers RD LATA PORTA is a 7 bi
235. al port pins Disables serial port and configures these pins as port pins Note When enabled the SDA and SCL pins must be properly configured as input or output bit 4 CKP SCK Release Control bit In Slave mode 1 Release clock 0 Holds clock low clock stretch used to ensure data setup time In Master mode Unused in this mode bit 3 0 55 3 55 0 Synchronous Serial Port Mode Select bits 1111 Slave mode 10 bit address with START and STOP bit interrupts enabled 1110 Slave mode 7 bit address with START and STOP bit interrupts enabled 1011 2 Firmware Controlled Master mode Slave IDLE 1000 2 Master mode clock Fosc 4 SSPADD 1 0111 IPC Slave mode 10 bit address 0110 Slave mode 7 bit address Note Bit combinations not specifically listed here are either reserved or implemented in SPI mode only Legend R Readable bit W Writable bit U Unimplemented bit read as n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown DS39564C page 136 2006 Microchip Technology Inc PIC18FXX2 REGISTER 15 5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SSPCON2 MSSP CONTROL REGISTER 2 IC MODE R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 0 R W 0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 GCEN General Call Enable bit Slave mode only 1 Enable interrupt when a genera
236. an A D conversion if the A D module is enabled Note The special event triggers from the CCP1 module will not set interrupt flag bit TMR 1IF PIR1 lt 0 gt must be configured for either Timer or Synchro nized Counter mode to take advantage of this feature If Timer is running in Asynchronous Counter mode this RESET operation may not work In the event that a write to Timer1 coincides with a special event trigger from CCP1 the write will take precedence In this mode of operation the CCPR1H CCPR1L regis ters pair effectively becomes the period register for Timer1 11 5 Timer 16 Bit Read Write Mode Timer1 can be configured for 16 bit reads and writes see Figure 11 2 When the RD16 control bit TICON lt 7 gt is set the address for TMR1H is mapped to a buffer register for the high byte of Timer1 A read from TMR1L will load the contents of the high byte of Timer1 into the high byte buffer This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte followed by a read of the low byte is valid due to a rollover between reads A write to the high byte of Timer1 must also take place through the TMR1H buffer register Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMRIL This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once The high byte o
237. an internal hardware trigger is generated which may be used to initiate an action The special event trigger output of CCP1 resets the TMRI register pair This allows the CCPR1 register to effectively be a 16 bit programmable period register for The special trigger output of resets either the TMR1 or TMR3 register pair Additionally the CCP2 Special Event Trigger will start an A D conversion if the A D module is enabled Note The special event trigger from the CCP2 module will not set the Timer1 or Timer3 interrupt flag bits Special Event Trigger will and set bit GO DONE ADCONO lt 2 gt which starts an A D conversion 2 only Special Event Trigger Reset Timer1 or Timer3 but not set 1 or Timer3 interrupt flag bit Set Flag bit CCP1IF CCPRIH CCPRIL a S Qutput Comparator RC2 CCP1 pin R g TRISC lt 2 gt Output Enable CCP1CON lt 3 0 gt T3CCP2 0 1A Mode Select TMRIH TMRIL Special Event Trigger 4 Set Flag bit CCP2IF T3CCP1 T3CCP2 Fae Comparator 5 Output RC1 CCP2 pin jJ R Logic TRISC lt 1 gt 4 Output Enable CCP2CON lt 3 0 gt Mode Select CCPR2H CCPR2L DS39564C page 120 2006 Microchip Technology Inc PIC18FXX2
238. an support different subsets of PIC16C5X or PIC16CXXX products through the use of inter changeable personality modules or daughter boards The emulator is capable of emulating without target application circuitry being present DS39564C page 254 2006 Microchip Technology Inc PIC18FXX2 21 8 MPLAB ICD In Circuit Debugger Microchip s In Circuit Debugger MPLAB ICD is a pow erful low cost run time development tool This tool is based on the FLASH MCUs and can be used to develop for this and other PICmicro microcontrollers The MPLAB ICD utilizes the in circuit debugging capa bility built into the FLASH devices This feature along with Microchip s In Circuit Serial Programming proto col offers cost effective in circuit FLASH debugging from the graphical user interface of the MPLAB Integrated Development Environment This enables a designer to develop and debug source code by watch ing variables single stepping and setting break points Running at full speed enables testing hardware in real time 219 PRO MATE Il Universal Device Programmer The PRO MATE universal device programmer is a full featured programmer capable of operating in stand alone mode as well as PC hosted mode The PRO MATE II device programmer is CE compliant The PRO MATE II device programmer has program mable and VPP supplies which allow it to verify programmed memory at VDD min and max for max imum reliab
239. anghai Tel 86 21 5407 5533 Fax 86 21 5407 5066 China Shenyang Tel 86 24 2334 2829 Fax 86 24 2334 2393 China Shenzhen Tel 86 755 8203 2660 Fax 86 755 8203 1760 China Shunde Tel 86 757 2839 5507 Fax 86 757 2839 5571 China Wuhan Tel 86 27 5980 5300 Fax 86 27 5980 5118 China Xian Tel 86 29 8833 7250 Fax 86 29 8833 7256 WORLDWIDE SALES AND SERVICE ASIA PACIFIC India Bangalore Tel 91 80 4182 8400 Fax 91 80 4182 8422 India New Delhi Tel 91 11 4160 8631 Fax 91 11 4160 8632 India Pune Tel 91 20 2566 1512 Fax 91 20 2566 1513 J apan Yokohama Tel 81 45 471 6166 Fax 81 45 471 6122 Korea Gumi Tel 82 54 473 4301 Fax 82 54 473 4302 Korea Seoul Tel 82 2 554 7200 Fax 82 2 558 5932 or 82 2 558 5934 Malaysia Penang Tel 60 4 646 8870 Fax 60 4 646 5086 Philippines Manila Tel 63 2 634 9065 Fax 63 2 634 9069 Singapore Tel 65 6334 8870 Fax 65 6334 8850 Taiwan Hsin Chu Tel 886 3 572 9526 Fax 886 3 572 6459 Taiwan Kaohsiung Tel 886 7 536 4818 Fax 886 7 536 4803 Taiwan Taipei Tel 886 2 2500 6610 Fax 886 2 2508 0102 Thailand Bangkok Tel 66 2 694 1351 Fax 66 2 694 1350 EUROPE Austria Wels Tel 43 7242 2244 3910 Fax 43 7242 2244 393 Denmark Copenhagen Tel 45 4450 2828 Fax 45 4485 2829 France Paris Tel 33 1 69 53 63 20 Fax 33 1 69 30 90 79 Germany Munich Tel 49 89 627 144 0 Fax 49 89 627 144 44 Italy Milan
240. ardware once write is complete The WR bit can only be set not cleared in software Write cycle to the EEPROM is complete RD Read Control bit 1 Initiates EEPROM read Read takes one cycle RD is cleared in hardware The RD bit can only be set not cleared in software RD bit cannot be set when EEPGD 1 0 Does not initiate an EEPROM read Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 17 Bit is set 0 Bit is cleared Bit is unknown 2006 Microchip Technology Inc DS39564C page 57 PIC18FXX2 5 2 2 TABLAT TABLE LATCH REGISTER The Table Latch TABLAT is an 8 bit register mapped into the SFR space The Table Latch is used to hold 8 bit data during data transfers between program memory and data RAM 5 2 3 TBLPTR TABLE POINTER REGISTER The Table Pointer TBLPTR addresses a byte within the program memory The TBLPTR is comprised of three SFR registers Table Pointer Upper Byte Table Pointer High Byte and Table Pointer Low Byte TBLPTRU TBLPTRH TBLPTRL These three regis ters join to form a 22 bit wide pointer The low order 21 bits allow the device to address up to 2 Mbytes of pro gram memory space The 22nd bit allows access to the Device ID the User ID and the Configuration bits The table pointer TBLPTR is used by the TBLRD and TBLWT instructions These instructions can update the TBLPTR in one of four ways based on the ta
241. as 0 RA6 and RA4 are configured as digital inputs The TRISA register controls the direction of the RA pins even when they are being used as analog inputs The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs 2006 Microchip Technology Inc DS39564C page 87 PIC18FXX2 FIGURE 9 2 BLOCK DIAGRAM OF FIGURE 9 3 BLOCK DIAGRAM OF RA4 TOCKI PIN RA6 PIN lt Enable Data RD LATA Bus Data RD LATA Bus D a zt e D Q WR LATA pin PORTA Data Latch N P CK Y WR LATA or D Q Vss Data Latch WR TRISA IN in 1 4 Schmitt t D a IN Trigger TRIS Latch Input Buffer pokra Vss _ WR TRISA TRIS Latch RD TRISA TTL Q Input RD TRISA Buffer EN M RD PORTA A Enable Q D EN TMRO Clock Input RD PORTA gt Note 1 Opin has protection diode to Vss only 1 Note 1 pins have protection diodes to and Vss DS39564C page 88 2006 Microchip Technology Inc PIC18FXX2 TABLE 9 1 PORTA FUNCTIONS Name Bit Buffer Function RAO ANO bitO TTL
242. ata from the address pointed to by FSR1H FSR1L INDFn can be used in code anywhere an operand can be used If INDFO INDF1 or INDF2 are read indirectly via an FSR all 05 are read zero bit is set Similarly if INDFO INDF1 or INDF2 are written to indirectly the operation will be equivalent to a NOP instruction and the STATUS bits are not affected 4 12 1 INDIRECT ADDRESSING OPERATION Each FSR register has an INDF register associated with it plus four additional register addresses Perform ing an operation on one of these five registers deter mines how the FSR will be modified during indirect addressing When data access is done to one of the five INDFn locations the address selected will configure the FSRn register to Do nothing to FSRn after an indirect access no change INDFn Auto decrement FSRn after an indirect access post decrement POSTDECn Auto increment FSRn after an indirect access post increment POSTINCn Auto increment FSRn before an indirect access pre increment PREINCn Use the value in the WREG register as an offset to FSRn Do not modify the value of the WREG or the FSRn register after an indirect access no change PLUSWn When using the auto increment or auto decrement fea tures the effect on the FSR is not reflected in the STATUS register For example if the indirect address causes the FSR to equal 0 the Z bit will not be set Incrementing or decrementing an FSR affects
243. ata memory value of FSRO post decremented not a physical register n a 50 PREINCO Uses contents of FSRO to address data memory value of FSRO pre incremented not a physical register n a 50 PLUSWO Uses contents of FSRO to address data memory value of FSRO not a physical register n a 50 Offset by value in WREG FSROH Indirect Data Memory Address Pointer 0 High Byte 0000 50 FSROL Indirect Data Memory Address Pointer 0 Low Byte XXXX XXXX 50 WREG Working Register XXXX n a INDF1 Uses contents of FSR1 to address data memory value of FSR1 not changed not a physical register n a 50 POSTINCI Uses contents of FSR1 to address data memory value of FSR1 post incremented not a physical register n a 50 POSTDEC1 Uses contents of FSR1 to address data memory value of FSR1 post decremented not a physical register n a 50 PREINC1 Uses contents of FSR1 to address data memory value of FSR1 pre incremented not a physical register n a 50 PLUSW1 Uses contents of FSR1 to address data memory value of FSR1 not a physical register n a 50 Offset by value in WREG FSR1H Indirect Data Memory Address Pointer 1 High Byte 0000 50 FSRIL Indirect Data Memory Address Pointer 1 Low Byte XXXX XXXX 50 BSR Bank Select Register 0000 49 INDF2 Uses contents of FSR2 to address data memory value of FSR2 not changed not a physical register n a 50 POSTINC2 Uses contents of FSR2 to address data memory value of
244. ation 000h WDT Operation 000h f 000h WDT postscaler 12 1 TO Status Affected 2 TPD Encoding 0110 101a ffff Status Affected TO PD Description Clears the contents of the specified Encoding een DER register If a is 0 the Access Bank Description CLRWDT instruction resets the will be selected overriding the BSR Watchdog Timer It also resets the value If 1 then the bank will postscaler of the WDT Status bits be selected as per the BSR value TO and PD are set default Words 1 Words 1 Cycles 1 Cycles Q Cycle Activity Q Cycle Activity Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode No Process No Decode Read Process Write operation Data operation register Data register f Example CLRWDT Example CLRF FLAG REG 1 Before Instruction Before Instruction WDT Counter 7 FLAG REG Ox5A After Instruction After Instruction WDT Counter 0 00 FLAG REG 0x00 WDT Postscaler 0 TO 1 PD ze 2006 Microchip Technology Inc DS39564C page 227 PIC18FXX2 COMF Complement f Syntax label f d Operands 0 lt 1 lt 255 d e 0 1 a e 0 1 Operation f dest Status Affected N Z Encoding 0001 11 ffff Description The contents of register f are com plemented If is 0 the result is stored in W If d is 1 the result is stored back in register default If a is 0 the Access Bank will be
245. available in these 32 bits In the second word the 4 MSbs are 1 s If this second word is exe cuted as an instruction by itself it will execute as a NOP All single word instructions are executed in a single instruction cycle unless a conditional test is true or the program counter is changed as a result of the instruc tion In these cases the execution takes two instruction cycles with the additional instruction cycle s executed as a NOP The double word instructions execute in two instruction cycles One instruction cycle consists of four oscillator periods Thus for an oscillator frequency of 4 MHz the normal instruction execution time is 1 us conditional test is true or the program counter is changed as a result of an instruction the instruction execution time is 2 us Two word branch instructions if true would take 3 us Figure 20 1 shows the general formats that the instructions can have All examples use the format nnh to represent a hexadecimal number where h signifies hexadecimal digit The Instruction Set Summary shown in Table 20 2 lists the instructions recognized by the Microchip Assembler MPASM Section 20 1 provides a description of each instruction 2006 Microchip Technology Inc DS39564C page 211 PIC18FXX2 TABLE 20 1 OPCODE FIELD DESCRIPTIONS Field Description
246. be assigned a high priority level or a low priority level The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h High priority interrupt events will over ride any low priority interrupts that may be in progress There are ten registers which are used to control interrupt operation These registers are RCON INTCON INTCON2 e INTCON3 PIR1 PIR2 PIE PIE2 IPR1 IPR2 It is recommended that the Microchip header files sup plied with MPLAB IDE be used for the symbolic bit names in these registers This allows the assembler compiler to automatically take care of the placement of these bits within the specified register Each interrupt source except INTO has three bits to control its operation The functions of these bits are Flag bit to indicate that an interrupt event occurred Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit RCON lt 7 gt When interrupt priority is enabled there are two bits which enable interrupts glo bally Setting the GIEH bit INTCON lt 7 gt enables all interrupts that have the priority bit set Setting the GIEL bit INTCON lt 6 gt enables all interrupts that have the priority bit cleared When the interrupt flag enable bit and appropriate gl
247. be verified against the original value This should be used in applications where excessive writes can stress bits near the specification limit 6 6 Protection Against Spurious Write There are conditions when the device may not want to write to the data memory To protect against spurious EEPROM vwrites various mechanisms have been built in On power up the WREN bit is cleared Also the Power up Timer 72 ms duration prevents EEPROM write The write initiate sequence and the WREN bit together help prevent an accidental write during brown out power glitch or software malfunction 67 Operation During Code Protect Data EEPROM memory has its own code protect mechanism External Read and Write operations are disabled if either of these mechanisms are enabled The microcontroller itself can both read and write to the internal Data EEPROM regardless of the state of the code protect configuration bit Refer to Special Features of the CPU Section 19 0 for additional information 6 8 Using the Data EEPROM The data EEPROM is a high endurance byte address able array that has been optimized for the storage of freguently changing information e g program va i ables or other data that are updated often Freguently changing values will typically be updated more often than specification D124 If this is not the case an array refresh must be performed For this reason variables that change infreguently such as c
248. bit SSPSTAT lt 0 gt is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out 15 4 10 2 WCOL Status If the user writes the SSPBUF when a transmit is already in progress i e SSPSR is still shifting out a data byte the WCOL is set and the contents of the buffer are unchanged the write doesn t occur WCOL must be cleared in software 15 4 10 3 ACKSTAT Status In Transmit mode the ACKSTAT bit SSPCON2 6 is cleared when the slave has sent an Acknowledge ACK 0 and is set when the slave does not Acknowledge ACK 1 A slave sends an Acknowledge when it has recognized its address including a general call or when the slave has properly received its data 15 4 11 MASTER MODE RECEPTION Master mode reception is enabled by programming the receive enable bit SSPCON2 3 Note the MSSP module the bit must be set after the ACK sequence or the RCEN bit will be disregarded The baud rate generator begins counting and on each rollover the state of the SCL pin changes high to low low to high and data is shifted into the SSPSR After the falling edge of the eighth clock the receive enable flag is automatically cleared the contents of the SSPSR are loaded into the SSPBUF the BF flag bit is set the SSPIF flag bit is set and the baud rate genera tor is suspended from counting holding SCL low The MSSP is now in IDLE state awaiting
249. bit is set RC2 CCP1 bit2 ST Input output port pin or Capture1 input Compare1 output PWM1 output RC3 SCK SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and IC modes RC4 SDI SDA bit4 ST RC4 can also be the SPI Data In SPI mode Data I O mode RC5 SDO bit5 ST Input output port pin or Synchronous Serial Port data output RC6 TX CK bit6 ST Input output port pin Addressable USART Asynchronous Transmit or Addressable USART Synchronous Clock RC7 RX DT bit7 ST Input output port pin Addressable USART Asynchronous Receive or Addressable USART Synchronous Data Legend ST Schmitt Trigger input TABLE 9 6 SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on Value on Name Bit7 Bit6 Bit5 Bit 4 Bit3 Bit 2 Bit1 BitO All Other RESETS PORTC RC7 RC6 RC5 RC4 RC3 RC2 RCI RCO XXXX XXXX uuuu uuuu LATC LATC Data Output Register XXXX uuuu uuuu TRISC PORTC Data Direction Register 1111 1111 1111 1111 Legend x unknown u unchanged DS39564C page 94 2006 Microchip Technology Inc PIC18FXX2 9 4 PORTD TRISD and LATD Registers This section is applicable only to the PIC18F4X2 devices PORTD is an 8 bit wide bi directional port The corre sponding Data Direction register is TRISD Setting a TRISD bit 1 will make the corresponding PORTD pin an input i e put the corresponding output driver in a Hi Impedance mode
250. ble opera tion These operations are shown in Table 5 1 These operations on the TBLPTR only affect the low order 21 bits 5 2 4 TABLE POINTER BOUNDARIES TBLPTR is used in reads writes and erases of the FLASH program memory When a TBLRD is executed all 22 bits of the Table Pointer determine which byte is read from program memory into TABLAT When TBLWT is executed the three LSbs of the Table Pointer TBLPTR 2 0 determine which of the eight program memory holding registers is written to When the timed write to program memory long write begins the 19 MSbs of the Table Pointer TBLPTR TBLPTR lt 21 3 gt will determine which program mem ory block of 8 bytes is written to For more detail see Section 5 5 Writing to FLASH Program Memory When an erase of program memory is executed the 16 MSbs of the Table Pointer TBLPTR lt 21 6 gt point to the 64 byte block that will be erased The Least Significant bits TBLPTR lt 5 0 gt are ignored Figure 5 3 describes the relevant boundaries of TBLPTR based on FLASH program memory operations TABLE 5 1 TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TUR TBLPTR is not modified TBLWT TBLRD X S K TBLPTR is incremented after the read write TBLRD 1 Erb ra TBLPTR is decremented after the read write 21
251. cate conditions do not apply for the designated device Note 1 One or more bits in the INTCONx or PIRx registers will be affected to cause wake up 2 When the wake up is due to an interrupt and the GIEL or GIEH bit is set the PC is loaded with the interrupt vector 0008h or 0018h 3 When the wake up is due to an interrupt and the GIEL or GIEH bit is set the TOSU TOSH and TOSL are updated with the current value of the PC The STKPTR is modified to point to the next location in the hardware stack See Table 3 2 for RESET value for specific condition Bit 6 of PORTA LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only In all other Oscillator modes they are disabled and read 0 6 Bit 6 of PORTA LATA and TRISA are not available on all devices When unimplemented they are read 0 2006 Microchip Technology Inc DS39564C page 29 PIC18FXX2 TABLE 3 3 INITIALIZATION CONDITIONS FOR ALL REGISTERS CONTINUED MCLR Resets neater poerongeset WorReset Wakeup va WOT Stack Resets ADRESH 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu ADRESL 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu ADCONO 242 442 252 452 0000 00 0 0000 00 0 uuuu uu u ADCON1 242 442 252 452 00 0000 00 0000 uu uuuu CCPRIH 242 442 252 452 XXXX XXXX uuuu uuuu uuuu uuuu CCPRIL 242 442 252 452
252. ccurred then CREN takes precedence during reception To set up a Synchronous Master Reception 9 Read the 8 bit received data by reading the RCREG register 1 Initialize the SPBRG register for the appropriate 10 If any error occurred clear the error by clearing baud rate Section 16 1 bit CREN 2 Enable the synchronous master serial port by MEA setting bits SYNC SPEN and CSRC 11 3 Ensure bits CREN and SREN clear register TABLE 16 9 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value on Value on Name BIt7 BIt6 BIt5 Bit 4 Bit 3 Bit 2 Bit 1 BOR Other RESETS INTCON GIE PEIE TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 0000 000u GIEH GIEL PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF 0000 0000 0000 0000 PIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE 0000 0000 0000 0000 IPR1 ADIP RCIP SSPIP CCP1IP TMR2IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 00x 0000 00x RCREG USART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 0000 010 SPBRG Rate Generator Register 0000 0000 0000 0000 Legend x unknown unimplemented read as Shaded cells
253. chip Technology Inc DS39564C page 63 PIC18FXX2 NOTES DS39564C page 64 2006 Microchip Technology Inc PIC18FXX2 6 0 DATA EEPROM MEMORY The Data EEPROM is readable and writable during normal operation over the entire VDD range The data memory is not directly mapped in the register file space Instead it is indirectly addressed through the Special Function Registers SFR There are four SFRs used to read and write the program and data EEPROM memory These registers are e 1 EECON2 EEDATA EEADR The EEPROM data memory allows byte read and write When interfacing to the data memory block EEDATA holds the 8 bit data for read write and EEADR holds the address of the EEPROM location being accessed These devices have 256 bytes of data EEPROM with an address range from Oh to FFh The EEPROM data memory is rated for high erase write cycles A byte write automatically erases the loca tion and writes the new data erase before write The write time is controlled by an on chip timer The write time will vary with voltage and temperature as well as from chip to chip Please refer to parameter D122 Electrical Characteristics Section 22 0 for exact limits 6 1 EEADR The address register can address up to a maximum of 256 bytes of data EEPROM 6 2 and 2 Registers is the control register for EEPROM memory accesses EECON is not a physical register Rea
254. chnology Inc DS39564C page 5 PIC18FXX2 NOTES DS39564C page 6 2006 Microchip Technology Inc PIC18FXX2 1 0 the following devices PIC18F242 PIC18F252 DEVICE OVERVIEW This document contains device specific information for PIC18F442 PIC18F452 These devices come in 28 pin and 40 44 pin packages The 28 pin devices do not have a Parallel Slave Port PSP implemented and the number of Analog to Digital A D converter input channels is reduced to 5 An overview of features is shown in Table 1 1 The following two figures are device block diagrams sorted by pin count 28 pin for Figure 1 1 and 40 44 pin for Figure 1 2 The 28 pin and 40 44 pin pinouts are listed in Table 1 2 and Table 1 3 respectively TABLE 1 1 DEVICE FEATURES Features PIC18F 242 PIC18F 252 PIC18F 442 PIC18F452 Operating Freguency DC 40 MHz DC 40 MHz DC 40 MHz DC 40 MHz Program Memory Bytes 16K 32K 16K 32K Program Memory Instructions 8192 16384 8192 16384 Data Memory Bytes 768 1536 768 1536 Data EEPROM Memory Bytes 256 256 256 256 Interrupt Sources 17 17 18 18 Ports Ports A B C Ports A B C Ports D Ports D E Timers 4 4 4 4 Capture Compare PWM Modules 2 2 2 2 MSSP MSSP MSSP MSSP Serial Communications Addressable Addressable Addressable Addressable USART USART USART USART Parall
255. chronous Slave Transmission 1 Enable the synchronous slave serial port by set ting bits SYNC and SPEN and clearing bit CSRC Clear bits CREN and SREN If interrupts are desired set enable bit TXIE If 9 bit transmission is desired set bit TX9 Enable the transmission by setting enable bit TXEN 6 If 9 bit transmission is selected the ninth bit should be loaded in bit TX9D 7 Starttransmission by loading data to the TXREG register 8 lfusinginterrupts ensure that the GIE and PEIE SLEEP instruction is executed the following will occur bits in the INTCON register INTCON lt 7 6 gt a The first word will immediately transfer to the set TSR register and transmit b The second word will remain TXREG register c Flag bit TXIF will not be set d When the first word has been shifted out of TSR the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set e If enable bit TXIE is set the interrupt will wake the chip from SLEEP If the global interrupt is enabled the program will branch to the interrupt vector TABLE 16 10 REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Value on Value on Name Bit 7 Bit6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 BIto POR BOR Other d RESETS INTCON GIE PEIE TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 000x 0000 000u GIEH GIEL PIR1
256. cifies which file register is to be used by the instruction The destination designator d specifies where the result of the operation is to be placed If is zero the result is placed in the WREG register If is one the result is placed in the file register specified in the instruction All bit oriented instructions have three operands 1 The file register specified by 2 The bit in the file register specified by b 3 The accessed memory specified by a The bit field designator b selects the number of the bit affected by the operation while the file register desig nator represents the number of the file in which the bit is located The literal instructions may use some of the following operands A literal value to be loaded into a file register specified by k The desired FSR register to load the literal value into specified by f No operand required specified by The control instructions may use some of the following operands program memory address specified by n The mode of the Call or Return instructions specified by s The mode of the Table Read and Table Write instructions specified by m No operand required specified by All instructions are a single word except for three dou ble word instructions These three instructions were made double word instructions so that all the required information is
257. circuit requires time to become stable before low voltage condition can be reliably detected This time is invariant of system clock speed This start up time is specified in electrical specification parameter 36 The low voltage 2006 Microchip Technology Inc DS39564C page 193 PIC18FXX2 NOTES DS39564C page 194 2006 Microchip Technology Inc PIC18FXX2 19 0 SPECIAL FEATURES OF THE CPU There are several features intended to maximize sys tem reliability minimize cost through elimination of external components provide power saving Operating modes and offer code protection These are OSC Selection RESET Power on Reset POR Power up Timer PWRT Oscillator Start up Timer OST Brown out Reset BOR Interrupts Watchdog Timer WDT SLEEP Code Protection ID Locations In Circuit Serial Programming All PIC18FXX2 devices have a Watchdog Timer which is permanently enabled via the configuration bits or software controlled It runs off its own RC oscillator for added reliability There are two timers that offer neces sary delays on power up One is the Oscillator Start up Timer OST intended to keep the chip in RESET until the crystal oscillator is stable The other is the Power up Timer PWRT which provides a fixed delay on power up only designed to keep the part in RESET while the power supply stabilizes With these two tim ers on chip most applications need n
258. ck input RC1 T1OSI CCP2 16 18 35 RC1 ST Digital T1OSI CMOS Timer1 oscillator input CCP2 ST Capture2 input Compare2 output PWM2 output RC2 CCP1 17 19 36 RC2 ST Digital CCP1 ST Capture1 input Compare1 output PWM1 output RC3 SCK SCL 18 20 37 RC3 y o ST Digital SCK VO ST Synchronous serial clock input output for SPI mode SOL O ST Synchronous serial clock input output for mode RC4 SDI SDA 23 25 42 RCA ST Digital SDI ST SPI Data In SDA O ST 2 Data RC5 SDO 24 26 43 RC5 ST Digital SDO O SPI Data Out RCG TX CK 25 27 44 RC6 ST Digital TX USART Asynchronous Transmit CK ST USART Synchronous Clock see related RX DT RC7 RX DT 26 29 1 RC7 y o ST Digital RX ST USART Asynchronous Receive DT ST USART Synchronous Data see related TX CK Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input Output OD Open Drain diode to VDD 2006 Microchip Technology Inc DS39564C page 15 PIC18FXX2 TABLE 1 3 PIC18F4X2 PINOUT 1 0 DESCRIPTIONS CONTINUED Pin Number Pin Buffer s Pin Name M eaan T T Description DIP PLCC ype PORTD is a bi directional I O port or a Parallel Slave Port PSP for interfacing to a microproce
259. clock pin Use primary oscillator clock input pin When OSCSEN and T1OSCEN are in other states bit is forced clear Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2006 Microchip Technology Inc DS39564C page 21 PIC18FXX2 2 6 2 OSCILLATOR TRANSITIONS The PIC18FXX2 devices contain circuitry to prevent glitches when switching between oscillator sources Essentially the circuitry waits for eight rising edges of the clock source that the processor is switching to This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources FIGURE 2 8 A timing diagram indicating the transition from the main oscilator to the oscillator is shown in Figure 2 8 The Timer1 oscillator is assumed to be run ning all the time After the SCS bit is set the processor is frozen at the next occurring Q1 cycle After eight syn chronization cycles are counted from the Timer1 oscil lator operation resumes No additional delays are required after the synchronization cycles TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1OSCILLATOR 01102 az a4 01 02 03 04 01 02 M Tscs 0561 APR A ARR AAA 1556
260. crochip Technology Inc PIC18FXX2 FIGURE 15 27 BUS COLLISION DURING START CONDITION SCL 0 SDA 0 SCL 1 k TBRG TBRG I SDA SCL Set SEN enable START sequence if SDA 1 SCL 1 pact SCL 0 before SDA 0 SEN bus collision occurs set BCLIF SCL 0 before BRG time out bus collision occurs Set BCLIF BCLIF 4 Interrupt cleared L_ in software S o 0 SSPIF o FIGURE 15 28 BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA 0 SCL 1 Set S Set SSPIF Less than TBRG gt _ TBRG SDA SDA pulled low by other master EN A 1 1 5 Reset BRG and assert SDA E SCL pulled low after BRG SEN Time out Set SEN enable START sequence if SDA 1 SCL 1 SCL I I 5 SSPIF SDA 0 SCL 1 Interrupts cleared Set SSPIF in software LL ee 2006 Microchip Technology Inc DS39564C page 161 PIC18FXX2 15 4 17 2 Collision During a Repeated START Condition During a Repeated START condition a bus collision occurs A low level is sampled on SDA when SCL goes from low level to high level b SCL goes low before SDA is asserted low indi cating that another master is attempting to transmit a data 717 When the user de asserts SDA and the pin is allowed to f
261. cution may not disable this function When the WDTEN configuration bit is cleared the SWDTEN bit enables disables the operation of the WDT REGISTER 19 14 WDTCON REGISTER The WDT time out period values may be found in the Electrical Specifications Section 22 0 under parame 0031 Values for the WDT postscaler may be assigned using the configuration bits Note The CLRWDT and SLEEP instructions clear the WDT and the postscaler if assigned to the WDT and prevent it from timing out and generating a device RESET condition Note When a CLRWDT instruction is executed and the postscaler is assigned to the WDT the postscaler count will be cleared but the postscaler assignment is not changed 19 2 1 CONTROL REGISTER Register 19 14 shows the WDTCON register This is a readable and writable register which contains a control bit that allows software to override the WDT enable configuration bit only when the configuration bit has disabled the WDT U 0 U 0 U 0 U 0 U 0 U 0 U 0 R W 0 m SWDTEN bit 7 bit O bit 7 1 Unimplemented Read as bit O SWDTEN Software Controlled Watchdog Timer Enable bit 1 Watchdog Timer is on 0 Watchdog Timer is turned off if the WDTEN configuration bit in the configuration register 0 Legend R Readable bit U Unimplemented bit read as 0 W Writable bit at POR
262. d ADCONI ADCOND Clock Conversion lt ADCS2 gt lt ADCS1 ADCS0 gt 0 00 Fosc 2 0 01 Fosc 8 0 10 Fosc 32 0 11 FRc clock derived from the internal A D RC oscillator 1 00 Fosc 4 1 01 Fosc 16 10 Fosc 64 1 11 FRC clock derived from the internal A D RC oscillator bit5 3 CHS2 CHSO Analog Channel Select bits 000 channel 0 001 channel 1 AN1 010 channel 2 2 011 channel 3 AN3 100 channel 4 AN4 101 channel 5 AN5 110 channel 6 AN6 111 channel 7 7 Note The PIC18F2X2 devices do not implement the full 8 A D channels the unimplemented selections are reserved Do not select any unimplemented channel LS o bit 2 GO DONE A D Conversion Status bit When ADON 1 1 A D conversion in progress setting this bit starts the A D conversion which is automatically cleared by hardware when the A D conversion is complete 0 A D conversion not in progress bit 1 Unimplemented Read as 0 bit O ADON A D On bit 1 A D converter module is powered up 0 A D converter module is shut off and consumes no operating current Legend R Readable bit W Writable bit U Unimplemented bit read as 0 at POR 7 Bit is set Bit is cleared Bit is unknown 2006 Microchip Technology Inc DS39564C page 181 PIC18FXX2 REGISTER 17 2 ADCON1 REGISTER bit 7 bit 6 bit 5 4 bit 3 0
263. d by a 1 to indicate receive bit Serial data is received via SDA while SCL outputs the serial clock Serial data is received 8 bits at a time After each byte is received an Acknowledge bit is transmitted START and STOP conditions indicate the beginning and end of transmission The baud rate generator used for the SPI mode opera tion is used to set the SCL clock frequency for either 100 kHz 400 kHz or 1 MHz C operation See Section 15 4 7 Baud Rate Generator for more detail DS39564C page 150 A typical transmit sequence would go as follows 1 10 11 12 The user generates a START condition by set ting the START enable bit SEN SSPCON2 lt 0 gt SSPIF is set The MSSP module will wait the required start time before any other operation takes place The user loads the SSPBUF with the slave address to transmit Address is shifted out the SDA pin until all 8 bits are transmitted The MSSP Module shifts in the ACK bit from the slave device and writes its value into the SSPCON register SSPCON2 lt 6 gt The MSSP module generates interrupt end of the ninth clock cycle by setting the SSPIF bit The user loads the SSPBUF with eight bits of data Data is shifted out the SDA pin until all 8 bits are transmitted The MSSP Module shifts in the ACK bit from the slave device and writes its value into the SSPCON register SSPCON2 lt 6 gt The MSSP module generates an interrupt at the end of t
264. denoted by the a bit for access bit When forced in the Access Bank a 0 the last address in Access RAM Low is followed by the first address in Access RAM High Access RAM High maps the Special Function registers so that these registers can be accessed without any software overhead This is useful for testing status flags and modifying control bits FIGURE 4 8 DIRECT ADDRESSING 4 11 Bank Select Register BSR The need for a large general purpose memory space dictates a RAM banking scheme The data memory is partitioned into sixteen banks When using direct addressing the BSR should be configured for the desired bank BSR lt 3 0 gt holds the upper 4 bits of the 12 bit RAM address The BSR lt 7 4 gt bits will always read 705 and writes will have no effect A MOVLB instruction has been provided in the instruction set to assist in selecting banks If the currently selected bank is not implemented any read will return all 05 and all writes are ignored The STATUS register bits will be set cleared as appropriate for the instruction performed Each Bank extends up to FFh 256 bytes data memory is implemented as static RAM A MOVFF instruction ignores the BSR since the 12 bit addresses are embedded into the instruction word Section 4 12 provides a description of indirect address ing which allows linear addressing of the entire RAM space BSR lt 3 0 gt 7 From Opcode
265. diL Hold time of 50 data input to SCK edge 100 ns TscL2diL 75 TdoR SDO data output rise time PIC18FXXX 25 ns PIC18LFXXX 60 ns VDD 2V 76 TdoF SDO data output fall time PIC18FXXX 25 ns PIC18LFXXX 60 ns VDD 2V 78 TscR SCK output rise time PIC18FXXX 25 ns Master mode PIC18LFXXX 60 ns 2 79 TscF SCK output fall time Master mode PIC18F XXX 25 ns PIC18LFXXX 60 ns VDD 2V 80 TscH2doV SDO data output valid after SCK 50 ns TsoL2doV edge PIC18LFXXX 150 ns VoD 2V Note 1 Reguires the use of Parameter 73A 2 Only if Parameter 71A and 72A are used DS39564C page 278 2006 Microchip Technology Inc PIC18FXX2 FIGURE 22 13 EXAMPLE SPI MASTER MODE TIMING 1 SDO x MSb X bit6 lt 1 x LSb SDI LSb In Note Refer to Figure 22 4 for load conditions TABLE 22 12 EXAMPLE SPI MODE REQUIREMENTS MASTER MODE CKE 1 ib Symbol Characteristic Min Max Units Conditions 71 TscH SCK input high time Continuous 1 25 TcY 30 ns 71A Slave mode Single Byte 40 ns Note 1 72 TscL SCK input low time Continuous 1 25 30 ns 72A Slave mode Single Byte 40 ns Note 1 73 TdiV2scH Setup time of 501 data input to SCK edge 100 ns TdiV2scL 73A TB2B Last clock edge of Byte1 t
266. ding EECON2 will read all 05 The 2 register is used exclusively in the EEPROM write sequence Control bits RD and WR initiate read and write opera tions respectively These bits cannot be cleared only set in software They are cleared in hardware at the completion of the read or write operation The inability to clear the WR bit in software prevents the accidental or premature termination of a write operation The WREN bit when set will allow a write operation On power up the WREN bit is clear The WRERR bit is set when a write operation is interrupted by a MCLR Reset or a WDT Time out Reset during normal opera tion In these situations the user can check the WRERR bit and rewrite the location It is necessary to reload the data and address registers EEDATA and EEADR due to the RESET condition forcing the contents of the registers to zero Note Interrupt flag bit EEIF in the PIR2 register is set when write is complete It must be cleared in software 2006 Microchip Technology Inc DS39564C page 65 PIC18FXX2 REGISTER 6 1 1 REGISTER ADDRESS FA6h R W x R W x U 0 R W 0 R W x R W 0 R S 0 R S 0 EEPGD CFGS FREE WRERR WREN WR RD bit 7 bit O bit 7 EEPGD FLASH Program or Data EEPROM Memory Select bit 1 Access FLASH Program memory 0 Access Data EEPROM memory bit 6 CFGS FLASH Program Data EE or Configuration Select bit 1 Access Configuration or Calibration r
267. dress HERE 2 CALL Subroutine Call Syntax label CALL k s Operands O lt k lt 1048575 s e 0 1 Operation 4 TOS k lt 20 1 gt if s 1 W gt WS STATUS STATUSS BSR BSRS Status Affected None Encoding 1st word k lt 7 0 gt 1110 110s kkkkg 2nd word k lt 19 8 gt 1111 ki kkk Description Subroutine call of entire 2 Mbyte memory range First return address PC 4 is pushed onto the return stack If s 1 the W STATUS and BSR registers are also pushed into their respective shadow registers WS STATUSS and BSRS If s 0 no update occurs default Then the 20 bit value k is loaded into PC lt 20 1 gt CALL is a two cycle instruction Words 2 Cycles 2 Q Cycle Activity Q1 Q2 Q3 04 Decode Read literal Push PC to Read literal k lt 7 0 gt stack K 19 85 Write to PC No No No No operation operation operation operation Example HERE CALL 1 Before Instruction PC address HERE After Instruction PC address THERE TOS address HERE 4 WS W BSRS BSR STATUSS STATUS DS39564C page 226 2006 Microchip Technology Inc PIC18FXX2 CLRF Clear f CLRWDT Clear Watchdog Timer Syntax label 1 Syntax label CLRWDT Operands 0 lt 1 lt 255 Operands None ae 0 1 Oper
268. dress Latch 21 PCLATU PCLATH y 120 ASIN Program Memory Address lt 12 gt up to 2 Mbytes PCU PCH PCL Program Counter 4 12 X 41 Data Latch BSR FSRO Banko F mm FSR2 12 16 Dead inc dec gt Table Latch r lesie 8 PORTB ROM Latch 4 5 RBO INTO 1 9 X RBI INT1 Instruction 4 1 Register LI RB3 CCP2 __ X RB5 PGM Instruction 4 5 x RB6 PCG Decode s H DX RB7 PGD Control OSC2 CLKO OSC1 CLKI Power up DK gt Timer Timing Oscillator T1 7 E TI 9860 Generation Start up Timer gt 1 Power on Reset 4XPLL K Watchdog Timer ALU lt 8 gt PORTC RCO TTOSO TICKI wn OU Precision 8 1 105 20 Voltage n RC2 CCP1 Reference Low Voltage RC3 SCK SCL Programming RC4 SDI SDA 04 5 ERI RC5 SDO Vo VSS In Circuit RC6 TX CK x Debugger RC7 RX DT la E S Ni aie 51 Timero 2 Timer3 A D Converter Master Addressable CCP1 CCP2 Synchronous USART Data EEPROM Serial Port T EZ 3 Note 1 Optional multiplexing of CCP2 input output with RB3 is enabled by selection of configuration bit The high order bits of the Direct Address for the RAM are from the BSR register except for the MOVFF instruction
269. during normal operation c MCLR Reset during SLEEP d Watchdog Timer WDT Reset during normal operation e Programmable Brown out Reset BOR f RESET Instruction g Stack Full Reset h Stack Underflow Reset Most registers are unaffected by a RESET Their status is unknown on POR and unchanged by all other RESETS The other registers are forced to a RESET state on Power on Reset MCLR WDT Reset Brown out Reset MCLR Reset during SLEEP and by the RESET instruction FIGURE 3 1 Most registers are not affected by a WDT wake up since this is viewed as the resumption of normal oper ation Status bits from the RCON register RI TO PD POR and BOR are set or cleared differently in different RESET situations as indicated in Table 3 2 These bits are used in software to determine the nature of the RESET See Table 3 3 for a full description of the RESET states of all registers A simplified block diagram of the On Chip Reset Circuit is shown in Figure 3 1 The Enhanced MCU devices have a MCLR noise filter in the MCLR Reset path The filter will detect and ignore small pulses The MCLR pin is not driven low by any internal RESETS including the WDT SIMPLIFIED BLOCK DIAGRAM OF ON CHIP RESET CIRCUIT RESET Instruction Stack Pointer External Reset gt SLEEP WDT WDT N Module Time out Reset Stack Full Underflow Reset MCLR
270. e it can be changed on the fly during program execution 10 3 0 Interrupt The TMRO interrupt is generated when the TMRO reg ister overflows from FFh to OOh in 8 bit mode or FFFFh to 0000h in 16 bit mode This overflow sets the TMROIF bit The interrupt can be masked by clearing the TMROIE bit The TMROIE bit must be cleared in soft ware by the TimerO module Interrupt Service Routine before re enabling this interrupt The TMRO interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP 10 4 16 Mode Timer Reads and Writes TMROH is not the high byte of the timer counter in 16 bit mode but is actually a buffered version of the high byte of TimerO refer to Figure 10 2 The high byte of the TimerO counter timer is not directly readable nor writable TMROH is updated with the contents of the high byte of TimerO during a read of TMROL This pro vides the ability to read all 16 bits of TimerO without having to verify that the read of the high and low byte were valid due to a rollover between successive reads of the high and low byte A write to the high byte of TimerO must also take place through the TMROH buffer register TimerO high byte is updated with the contents of TMROH when a write occurs to TMROL This allows all 16 bits of TimerO to be updated at once Note Writing to TMROL when the prescaler is assigned to TimerO will clear
271. e Interrupt with flag bit RBIF lt 0 gt This interrupt can wake the device from SLEEP The user in the Interrupt Service Routine can clear the interrupt in the following manner a Any read or write of PORTB except with the MOVFF instruction This will end the mismatch condition b Clear flag bit RBIF A mismatch condition will continue to set flag bit RBIF Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared The interrupt on change feature is recommended for wake up on key depression operation and operations where PORTB is only used for the interrupt on change feature Polling of PORTB is not recommended while using the interrupt on change feature RB3 can be configured by the configuration bit CCP2MX as the alternate peripheral pin for the CCP2 module CCP2MX 0 FIGURE 9 4 BLOCK DIAGRAM OF RB7 RB4 PINS VDD RBPUU T RBPU P Weak Pull up Data Bus Data Latch D Q 9 VO pin WR LATB or CK PORTB TRIS Latch 0 Q WR TRISB TTL X Input W Buffer ST Buffer RD TRISB RD LATB Latch Q D e RD PORTB EN Q1 Set RBIF RD PORTB From other I RB7 RB4 pins I Q3 RB7 RB5 in Serial Programming mode Note 1 O pins have diode protection to VDD and Vss 2 Toenable weak pull ups set the appropriate TRIS bit s and clear the RBPU bit INTCON2 7 Note 1 While
272. e TimerO module in 8 bit mode and Figure 10 2 shows simplified block diagram of the TimerO module in 16 bit mode The TOCON register Register 10 1 is a readable and writable register that controls all the aspects of TOCON TIMERO CONTROL REGISTER R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 TMROON TOCS TOSE PSA TOPS2 TOPS1 TOPSO bit 7 TMROON On Off Control bit 1 Enables 0 Stops TOBBIT 8 bit 16 bit Control bit 1 TimerO is configured as an 8 bit timer counter 0 TimerO is configured as a 16 bit timer counter TOCS Clock Source Select bit 1 Transition on TOCKI pin 0 Internal instruction cycle clock CLKO TOSE TimerO Source Edge Select bit 1 Increment on high to low transition on TOCKI pin 0 Increment on low to high transition on TOCKI pin PSA Prescaler Assignment bit 1 prescaler is NOT assigned clock input bypasses prescaler TimerO prescaler is assigned TimerO clock input comes from prescaler output TOPS2 TOPSO TimerO Prescaler Select bits 111 1 256 prescale value 110 1 128 prescale value 101 1 64 prescale value 100 1 32 prescale value 011 1 16 prescale value 010 1 8 prescale value 001 1 4 prescale value 000 1 2 bit 0 Legend Readable bit W Writable bit U Unimpl
273. e is 1 the BSR will not be overridden If a 1 then the bank will be default selected as per the BSR value Words 1 default Cycles 1 2 Words 1 Note 3 cycles if skip and followed Cycles 1 2 by a 2 word instruction Note 3 cycles if skip and followed Q Cycle Activity by a 2 word instruction T Q1 Q2 Q3 Q4 Q Cycle Activity Decode Read Process No Q1 Q2 Q3 Q4 register f Data operation Decode Read Process No If skip register f Data operation Q1 Q4 If skip No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2 word instruction operation operation operation operation Q1 Q4 If skip and followed by 2 word instruction No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example HERE CPFSLT REG 1 NLESS Example HERE CPFSGT REG 0 LESS NGREATER Before Instruction GREATER PC Address HERE Before Instruction W ii PC Address HERE After Instruction W 7 If REG lt W After Instruction Address LESS If REG gt If REG gt W PC Address NLESS PC Address GREATER If REG lt W Address NGREATER 2006 Microchip Technology Inc DS39564C page 229 PIC18FXX2 DAW Decima
274. e 218 2006 Microchip Technology Inc PIC18FXX2 ANDWF AND W with f Syntax label ANDWF ffd a Operands 0 lt lt 255 de 0 1 0 1 Operation W f gt dest Status Affected N Z Encoding 0001 01da ffff Description The contents of W are AND ed with register If d is 0 the result is stored in W If d is 1 the result is stored back in register f default If a is 0 the Access Bank will be selected If a is 1 the BSR will not be overridden default Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example ANDWF REG 0 0 Before Instruction W 0x17 REG 0 2 After Instruction W 0x02 REG OxC2 BC Branch if Carry Syntax label 128 lt n lt 127 Operation if carry bit is 1 PC 2 2n 5 Status Affected None Encoding 1110 0010 nnnn nnnn Description If the Carry bit is 1 then the program will branch The 2 s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a two cycle instruction Words 1 Cycles 1 2 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC n Data No No No No operation operation operation operat
275. e A D port config uration bits PCFG2 PCFGO ADCON1 lt 2 0 gt must be set which will configure pins RE2 REO as digital I O A write to the PSP occurs when both the CS and WR lines are first detected low A read from the PSP occurs when both the CS and RD lines are first detected low The PORTE pins become control inputs for the microprocessor port when bit PSPMODE TRISE lt 4 gt is set In this mode the user must make sure that the TRISE lt 2 0 gt bits are set pins are configured as digital inputs and the ADCONI is configured for digital In this mode the input buffers are TTL FIGURE 9 10 PORTD AND PORTE BLOCK DIAGRAM PARALLEL SLAVE PORT Data Bus 5 5 x RDx WRLATD lt 1 FIGURE 9 11 PARALLEL SLAVE PORT WRITE WAVEFORMS DS39564C page 100 2006 Microchip Technology Inc PIC18FXX2 FIGURE 9 12 PARALLEL SLAVE PORT READ WAVEFORMS 91 92 Q3 04 a1 a2 Q3 04 7 0 IBF M E PSPIF TABLE 9 11 REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT value on Value on Name Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 RESETS PORTD Port Data Latch when written Port pins when read XXXX XXXX uuuu uuuu LATD LATD Data Output bits XXXX XXXX uuuu uuuu TRISD PORTD Data Direction bits 12114 LIT W
276. e LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line max TSU DAT 1000 250 1250 ns according to the Standard mode bus specification before the SCL line is released 2006 Microchip Technology Inc DS39564C page 283 PIC18FXX2 FIGURE 22 18 MASTER SSP BUS START STOP BITS TIMING WAVEFORMS SCL RE 22 O O START STOP Condition Condition Note Refer to Figure 22 4 for load conditions TABLE 22 17 MASTER SSP BUS START STOP BITS REOUIREMENTS FIGURE 22 19 MASTER SSP I7C BUS DATA TIMING EE SSS DS39564C page 284 2006 Microchip Technology Inc PIC18FXX2 TABLE 22 18 MASTER SSP BUS DATA REQUIREMENTS Symbol Characteristic Min Max Units Conditions 100 THIGH Clock high time 100 kHz mode 2 Tosc BRG 1 ms 400 kHz mode 2 Tosc BRG 1 ms 1 MHz model 2 Tosc BRG 1 ms 101 TLOW Clock low time 100 kHz mode 2 Tosc BRG 1 ms 400 kHz mode 2 Tosc BRG 1 ms 1 MHz mode 2 Tosc BRG 1 ms 102 TR SDA and SCL 100 kHz mode 1000 ns CBis specified to be from rise time 400 kHz mode 20 0 1 CB 300 ns 1010 400 pF 1 MHz mode 300 ns 103 TF SDA and SCL 100 kHz mode 1000 ns VDD gt 4 2V fall time 40
277. e Port Mode Select bit 1 Parallel Slave Port mode General purpose I O mode bit 3 Unimplemented Read as 0 bit 2 TRISE2 RE2 Direction Control bit 1 Input 0 Output bit 1 TRISE 1 RE1 Direction Control bit 1 Input 0 Output bit O TRISEO REO Direction Control bit 1 Input 0 Output Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 1 Bit is set 0 Bit is cleared X z Bitis unknown DS39564C page 98 2006 Microchip Technology Inc PIC18FXX2 TABLE 9 9 PORTE FUNCTIONS Name Bit Buffer Type Function REO RD AN5 bito ST TTLU Input output port pin or read control input in Parallel Slave Port mode or analog input RD 1 Not a read operation 0 Read operation Reads PORTD register if chip selected 1 6 bit ST TTL Inpu output port pin or write control input in Parallel Slave Port mode or analog input WR 1 Not a write operation 0 Write operation Writes PORTD register if chip selected RE2 CS AN7 bit2 ST TTLU Input output port pin or chip select control input in Parallel Slave Port mode or analog input CS 1 Device is not selected 0 Device is selected Legend ST Schmitt Trigger input TTL TTL input Note 1 Input buffers are Schmitt Triggers when in O mode and TTL buffers when in Parallel Slave Port mode
278. e WREG Restore STATUS 8 7 TMRO Interrupt In 8 bit mode which is the default an overflow FFh 00h in the TMRO register will set flag bit TMROIF In 16 bit mode an overflow FFFFh 0000h in the TMROH TMROL registers will set flag bit TMROIF The interrupt can be enabled disabled by setting clearing enable bit TOIE INTCON 5 Interrupt prior ity for TimerO is determined by the value contained in the interrupt priority bit TMROIP INTCON2 lt 2 gt See Section 10 0 for further details on the TimerO module 8 8 PORTB Interrupt on Change An input change on PORTB lt 7 4 gt sets flag bit RBIF INTCON lt O gt The interrupt can be enabled disabled by setting clearing enable bit RBIE INTCON lt 3 gt Interrupt priority for PORTB interrupt on change is determined by the value contained in the interrupt priority bit 2 lt 0 gt 8 9 Context Saving During Interrupts During an interrupt the return PC value is saved on the stack Additionally the WREG STATUS and BSR regis ters are saved on the fast return stack If a fast return from interrupt is not used See Section 4 3 the user may need to save the WREG STATUS and BSR regis ters in software Depending on the user s application other registers may also need to be saved Equation 8 1 saves and restores the WREG STATUS and BSR registers during an Interrupt Service Routine SAVING STATUS WREG AND BSR REGISTERS IN RAM W TEMP is in virtu
279. e supports the following modes in hardware Master mode Multi Master mode Slave mode 15 2 Control Registers The MSSP module has three associated registers These include a status register SSPSTAT and two control registers SSPCON1 and SSPCON2 The use of these registers and their individual configuration bits differ significantly depending on whether the MSSP module is operated in SPI or mode Additional details are provided under the individual sections 15 3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously All four modes of SPI are supported To accomplish communication typically three pins are used Serial Data SDO RC5 SDO Serial Data In SDI RC4 SDI SDA e Serial Clock SCK RC3 SCK SCL LVDIN Additionally a fourth pin may be used when in a Slave mode of operation Slave Select SS RA5 SS AN4 Figure 15 1 shows the block diagram of the MSSP module when operating in SPI mode FIGURE 15 1 MSSP BLOCK DIAGRAM SPI MODE Internal Data Bus Read Write SSPBUF reg RC4 SDI SDA 4 92 2 2 SSPSR reg V shift A clock RA5 SS AN4 55 Control Enable Edge 2 Clock Select SSPM3 SSPMO RC3 SCK output SCL LVDIN 1 2 Edge Select Prescaler TOSC 4 16 64 Data to TX RX in SSPSR TRIS bit
280. eception is com SLEEP On completely receiving the word the RSR plete An interrupt will be generated if enable bit register will transfer the data to the RCREG register RCIE was set and if enable bit RCIE bit is set the interrupt generated 6 Read the RCSTA register to get the ninth bit if will wake the chip from SLEEP If the global interrupt is enabled and determine if any error occurred enabled the program will branch to the interrupt vector during reception 7 Read the 8 bit received data by reading the RCREG register 8 error occurred clear the error by clearing bit CREN 9 If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON 7 6 are set TABLE 16 11 REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on Value on Name Bit7 Bit 6 Bit5 Bit4 Bit3 Bit2 Bit 1 POR BOR Other 4 RESETS INTCON GIE PEIE TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 0000 000u GIEH GIEL PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 0000 0000 0000 0000 PIE1 ADIE RCIE TXIE SSPIE CCP1IE TMRZIE TMR1IE 0000 0000 0000 IPR1 ADIP RCIP SSPIP CCP1IP 2 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 00x 0000 00x RCREG USART Receive Register 0000 0000 0000 0000
281. ed cells are not used by PORTD DS39564C page 96 2006 Microchip Technology Inc PIC18FXX2 9 5 PORTE TRISE and LATE Registers This section is only applicable to the PIC18F4X2 devices PORTE is a 3 bit wide bi directional port The corre sponding Data Direction register is TRISE Setting a TRISE bit 1 will make the corresponding PORTE pin an input i e put the corresponding output driver in a Hi Impedance mode Clearing a TRISE bit 0 will make the corresponding PORTE pin an output i e put the contents of the output latch on the selected pin The Data Latch register LATE is also memory mapped Read modify write operations on the LATE register reads and writes the latched output value for PORTE PORTE has three pins REO RD AN5 RE1 WR AN6 and RE2 CS AN7 which are individually configurable as inputs or outputs These pins have Schmitt Trigger input buffers Register 9 1 shows the TRISE register which also controls the parallel slave port operation PORTE pins are multiplexed with analog inputs When selected as an analog input these pins will read as 0 5 TRISE controls the direction of the RE pins even when they are being used as analog inputs The user must make sure to keep the pins configured as inputs when using them as analog inputs Note On a Power on Reset these pins are configured as analog inputs EXAMPLE 9 5 INITIALIZING PORTE CLRF PORT
282. egisters 0 2 Access FLASH Program or Data EEPROM memory bit 5 Unimplemented Read as 0 bit 4 FREE FLASH Row Erase Enable bit 1 Erase the program memory row addressed by TBLPTR on the next WR command cleared by completion of erase operation 0 Perform write only bit 3 WRERR FLASH Program Data EE Error Flag bit 1 write operation is prematurely terminated any MCLR or any WDT Reset during self timed programming in normal operation 0 The write operation completed Note When a WRERR occurs EEPGD or FREE bits not cleared This allows tracing of the error condition bit 2 WREN FLASH Program Data EE Write Enable bit 1 Allows write cycles 0 Inhibits write to the EEPROM bit 1 WR Write Control bit 1 Initiates data EEPROM erase write cycle or a program memory erase cycle or write cycle The operation is self timed and the bit is cleared by hardware once write is complete The WR bit can only be set not cleared in software Write cycle to the EEPROM is complete bit O RD Read Control bit 1 Initiates EEPROM read Read takes one cycle RD is cleared in hardware The RD bit can only be set not cleared in software RD bit cannot be set when EEPGD 1 0 Does not initiate an EEPROM read Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 7 Bit is set 0 Bit is cleared Bitis unknown DS39564C page 66 2006 Microchip Technology Inc
283. egisters EEADR Register EECONI Register 440242222 44010 EECON Register Operation During Code Protect 22 Protection Against Spurious Write 68 Reading PP e Ee 67 Using 68 Write Verify iunio rre ee nale 68 Writing n Data Memory ss rene General Purpose Registers Map for PIC18F242 442 Map for PIC18F252 452 Special Function Registers DAW Aeon Died ptite DC and AC Characteristics Graphs and Tables 289 DC Characteristics DCFSNZ iie DUERME DEGESZ roger Rr PUB dore lente Development Support Device Differences ss Device Overview Features bane nce egere nee etie Direct Addressing 1 Example aotenn xm eere xe eR Pn E Electrical Characteristics 259 cest 5 F Firmware Instructions 211 FLASH Program Memory eese 55 Associated Registers 63 Control Registers 24 4222222 2 Erase Sequence Erasing Operation During Code Protect 63 Reading ss TABLAT Register Table Pointer
284. el Communications m PSP PSP 10 bit Analog to Digital Module 5 input channels 5 input channels 8 input channels 8 input channels POR BOR POR BOR POR BOR POR BOR RESET Instruction RESET Instruction RESET Instruction RESET Instruction RESETS and Delays Stack Full Stack Full Stack Full Stack Full Stack Underflow Stack Underflow Stack Underflow Stack Underflow PWRT OST PWRT OST PWRT OST PWRT OST Programmable Low Voltage Yes Yes Yes Yes Detect Programmable Brown out Reset Yes Yes Yes Yes Instruction Set 75 Instructions 75 Instructions 75 Instructions 75 Instructions es E 40 pin DIP 40 pin DIP Packages 2 uin 2 S 44 pin PLCC 44 pin p 44 pin TOFP 44 pin 2006 Microchip Technology Inc DS39564C page 7 PIC18FXX2 FIGURE 1 1 PIC18F2X2 BLOCK DIAGRAM Data Bus lt 8 gt 21 Table Pointer Data Latch PORTA RAO ANO 8 8 48 Data RAM RA1 AN1 21 inc dec logic RA2 AN2 VREF 071 RAS ANS VREF Address Latch RA4 TOCKI Ad
285. elopment needs 3 Do you find the organization of this document easy to follow If not why 4 What additions to the document do you think would enhance the structure and subject 5 What deletions from the document could be made without affecting the overall usefulness 6 Is there any incorrect or misleading information what and where 7 How would you improve this document DS39564C page 328 Advance Information 2006 Microchip Technology Inc PIC18FXX2 PIC18FXX2 PRODUCT IDENTIFICATION SYSTEM To order or obtain information e g on pricing or delivery refer to the factory or the listed sales office PART NO X X XXX Device Temperature Package Pattern Range Device PIC18FXX20 PIC18FXX2T 0 VDD range 4 2V to 5 5V PIC18LFXX2 PIC18LFXX2T 0 range 2 5V to 5 5V Temperature 40 Cto 85 C Industrial Range 40 C to 125 C Extended Package Thin Quad Flatpack SO SOIC SP Skinny Plastic DIP P PDIP L PLCC Pattern QTP SQTP Code or Special Requirements blank otherwise Examples a PIC18LF452 301 Industrial temp PDIP package Extended VDD limits QTP pattern 301 b PIC18LF242 1 50 Industrial temp SOIC package Extended VDD limits PIC18F442 E P Extended temp PDIP package normal VDD limits Note 1 F LF 2 Standard Voltage range Wide Voltage Range in tape and reel
286. els Distributor or Representative Local Sales Office Field Application Engineer FAE Technical Support Development Systems Information Line Customers should contact their distributor representative or field application engineer FAE for support Local sales offices are also available to help customers A listing of sales offices and locations is included in the back of this document Technical supportis available through the web site at http support microchip com 2006 Microchip Technology Inc DS39564C page 327 PIC18FXX2 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod uct If you wish to provide your comments on organization clarity subject matter and ways in which our documentation can better serve you please FAX your comments to the Technical Publications Manager at 480 792 4150 Please list the following information and use this outline to provide us with your comments about this document To Technical Publications Manager Total Pages Sent RE Reader Response From Name Company Address City State ZIP Country Telephone FAX Application optional Would you likeareply oN Device PIC18FXX2 Literature Number DS39564C Questions 1 What are the best features of this document 2 How does this document meet your hardware and software dev
287. emented bit read as 0 at POR Bit is set Bit is cleared x Bit is unknown 2006 Microchip Technology Inc DS39564C page 103 PIC18FXX2 FIGURE 10 1 TIMERO BLOCK DIAGRAM IN 8 BIT MODE Data Bus 8 Sync with 1 Internal TMROL RA4 TOCKI pin Clocks FOSC 4 _ 0 Programmable Prescaler TOSE 2 TCY delay f 3 PSA Set Interrupt TOPS2 TOPS1 TOPSO Flag bit TMROIF TOCS on Overflow Note Upon RESET is enabled in 8 bit mode with clock input from TOCKI max prescale FIGURE 10 2 TIMERO BLOCK DIAGRAM IN 16 BIT MODE Fosc 0 1 Sync with Set Interrupt 1 _ Internal TMROL IMRO Flag bit TMROIF Clocks High Byte TOCKI pin Programmable 0 on Overflow rescaler 2 Tcv delay T 8 TOSE 2 Tcv delay 3 N neni TMROL TOPS2 TOPS1 TOPSO TOCS PSA Write TMROL na 8 TMROH 8 Data Bus lt 7 0 gt Note Upon RESET is enabled in 8 bit mode with clock input from TOCKI max prescale DS39564C page 104 2006 Microchip Technology Inc PIC18FXX2 10 1 0 Operation can operate as a timer or as a counter Timer mode is selected by clearing the TOCS bit In Timer mode the TimerO module will increment every instruction cycle without prescaler If the TMROL reg ister is writt
288. emory map is divided into as many as 16 banks that contain 256 bytes each The lower 4 bits of the Bank Select Register BSR lt 3 0 gt select which bank will be accessed The upper 4 bits for the BSR are not implemented The data memory contains Special Function Registers SFR and General Registers GPR The SFRs are used for control and status of the controller and peripheral functions while GPRs are used for data storage and scratch pad operations in the user s appli cation The SFRs start at the last location of Bank 15 OxFFF and extend downwards Any remaining space beyond the SFRs in the Bank may be implemented as GPRs GPRs start at the first location of Bank 0 and grow upwards Any read of an unimplemented location will read as 0 s The entire data memory may be accessed directly or indirectly Direct addressing may require the use of the BSR register Indirect addressing requires the use of a File Select Register FSRn and a corresponding Indi rect File Operand INDFn Each FSR holds a 12 bit address value that can be used to access any location in the Data Memory map without banking The instruction set and architecture allow operations across all banks This may be accomplished by indirect addressing or by the use of the MOVFF instruction The MOVFF instruction is a two word two cycle instruction that moves a value from one register to another To ensure that commonly used registers SFRs and select
289. en the increment is inhibited for the follow ing two instruction cycles The user can work around this by writing an adjusted value to the TMROL register Counter mode is selected by setting the TOCS bit In Counter mode Timero will increment either on every rising or falling edge of pin RA4 TOCKI The increment ing edge is determined by the TimerO Source Edge Select bit TOSE Clearing the TOSE bit selects the ris ing edge Restrictions on the external clock input are discussed below When an external clock input is used for it must meet certain reguirements The reguirements ensure the external clock can be synchronized with the internal phase clock Tosc Also there is a delay in the actual incrementing of TimerO after synchronization 10 2 Prescaler An 8 bit counter is available as prescaler for the module The prescaler is not readable or writable The PSA and TOPS2 TOPSO bits determine the prescaler assignment and prescale ratio Clearing bit PSA will assign the prescaler to the module When the prescaler is assigned to the module prescale values of 1 2 1 4 1 256 are selectable When assigned to the module all instructions writing to the TMROL register e g CLRF TMRO MOVWF TMRO BSF TMRO x etc will clear the prescaler count 10 2 1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con trol i
290. er See Compare Special Features of the CPU Configuration Registers Special Function Registers Cope SPI Master Mode Serial Clock Serial Data In EE Serial Data Out 2 4242 0 125 Slave eene ret reet 125 SPI Clock SPI Mode SPI Master Slave Connection 129 SPI Module Associated Registers Bus Mode Compatibility 51 Effects of a RESET mimi Master Slave Connection Slave Mode Slave Select Synchronization Slave Synch Timing DR SLEEP Operation eene Mode See eet ee deett 125 SPI Mode See SPI SSPBUF Register 44 130 SSPSR Register TMR2 Output for Clock Shift 111 112 SSPOV Status Flag eee 155 SSPSTAT Register ATE M aus 138 139 Status Bits Significance and the Initialization Condition for RCON Register 27 SWAR F 248 2006 Microchip Technology Inc T TABLAT Register sus 58 Table Pointer Operations table 58 TBLPTR Register us I TBLWT Time out Seguence Time out in Var
291. erefore code cannot execute An internal pro gramming timer terminates program memory writes and erases A value written to program memory does not need to be a valid instruction Executing a program memory location that forms an invalid instruction results in a FIGURE 5 1 TABLE READ OPERATION 5 1 Table Reads and Table Writes In order to read and write program memory there are two operations that allow the processor to move bytes between the program memory space and the data RAM Table Read TBLRD Table Write TBLWT The program memory space is 16 bits wide while the data RAM space is 8 bits wide Table Reads and Table Writes move data between these two memory spaces through an 8 bit register TABLAT Table Read operations retrieve data from program memory and places it into the data RAM space Figure 5 1 shows the operation of a Table Read with program memory and data RAM Table Write operations store data from the data mem ory space into holding registers in program memory The procedure to write the contents of the holding reg isters into program memory is detailed in Section 5 5 Writing to FLASH Program Memory Figure 5 2 shows the operation of a Table Write with program memory and data RAM Table operations work with byte entities A table block containing data rather than program instructions is not reguired to be word aligned Therefore a table block can start and end at any byte addre
292. es if the access will be a program or data EEPROM memory access When clear any subseguent operations will operate on the data EEPROM memory When set any subseguent operations will operate on the program memory Control bit CFGS determines if the access will be to the configuration registers or to program memory data EEPROM memory When set subseguent operations will operate on configuration registers regardless of EEPGD see Special Features of the CPU Section 19 0 When clear memory selection access is determined by EEPGD The FREE bit when set will allow a program memory erase operation When the FREE bit is set the erase operation is initiated on the next WR command When FREE is clear only writes are enabled The WREN bit when set will allow a write operation On power up the WREN bit is clear The WRERR bit is set when a write operation is interrupted by a MCLR Reset or a WDT Time out Reset during normal opera tion In these situations the user can check the WRERR bit and rewrite the location It is necessary to reload the data and address registers EEDATA and EEADR due to RESET values of zero Control bit WR initiates write operations This bit cannot be cleared only set in software It is cleared in hard ware at the completion of the write operation The inability to clear the WR bit in software prevents the accidental or premature termination of a write operation Note Interrupt flag bit EEIF
293. escent voltage level guiescent voltage level Note See Table 3 1 in the Reset section for time outs due to SLEEP and MCLR Reset 2 8 Power up Delays Power up delays are controlled by two timers so that no external RESET circuitry is reguired for most appli cations The delays ensure that the device is kept in RESET until device power supply and clock are stable For additional information on RESET operation see Section 3 0 The first timer is the Power up Timer PWRT which optionally provides a fixed delay of 72 ms nominal on power up only POR and BOR The second timer is the Oscillator Start up Timer OST intended to keep the chip in RESET until the crystal oscillator is stable With the PLL enabled HS PLL Oscillator mode the time out seguence following a Power on Reset is differ ent from other Oscillator modes The time out sequence is as follows First the PWRT time out is invoked after a POR time delay has expired Then the Oscillator Start up Timer OST is invoked However this is still not a sufficient amount of time to allow the PLL to lock at high freguencies The PWRT timer is used to provide an additional fixed 2 ms nominal time out to allow the PLL ample time to lock to the incoming clock freguency DS39564C page 24 2006 Microchip Technology Inc PIC18FXX2 30 RESET The PIC18FXXX differentiates between various kinds of RESET a Power on Reset POR b MCLR Reset
294. ess Write to register f Data destination Example DECF ONT 1 0 Before Instruction CNT 2 0 01 0 After Instruction CNT 2 0x00 1 DS39564C page 230 2006 Microchip Technology Inc PIC18FXX2 DECFSZ Syntax Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Decrement f skip if 0 label DECFSZ 0 lt 1 lt 255 d e 0 1 ae 0 1 f 1 gt dest skip if result 0 None 0010 11da EEEE The contents of register are dec remented If is 0 the result is placed in W If d is 1 the result is placed back register default If the result is 0 the next instruc tion which is already fetched is discarded and a NOP is executed instead making it a two cycle instruction If a is 0 the Access Bank will be selected overriding the BSR value If a 1 then the bank will be selected as per the BSR value default 1 1 2 Note 3 cycles if skip and followed by a 2 word instruction DCFSNZ Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Decrement f skip if not 0 label DCFSNZ 0 lt 1 lt 255 d e 0 1 a e 0 1 f 1 dest skip if result 0 None 0100 11da FEFFE The contents of register are dec remented If is
295. ess Write to register Data destination Example 1 SUBFWB REG 1 0 Before Instruction REG 3 w 2 C 1 After Instruction REG FF W 2 0 2 0 1 result is negative 2 SUBFWB REG 0 0 Before Instruction REG 2 W 5 1 After Instruction REG 42 W 3 C 1 2 0 0 resultis positive Example 3 SUBFWB REG 1 0 Before Instruction REG 1 W 2 0 After Instruction REG 0 W gt 2 1 2 1 s result is zero N 0 DS39564C page 246 2006 Microchip Technology Inc PIC18FXX2 SUBLW Subtract W from literal Syntax label SUBLW k Operands 0 lt k lt 255 Operation W gt W Status Affected N OV C DO Z Encoding 0000 1000 kkkk kkkk Description W is subtracted from the eight bit literal K The result is placed in W Words 1 Cycles 1 Q Cycle Activity Q1 Q2 04 Read Process Write to W literal K Data Example 1 SUBLW 0x02 Before Instruction W 1 C 2 After Instruction W 1 C 1 result is positive 2 0 N 0 2 SUBLW 0x02 Before Instruction W 2 C 2 After Instruction W 0 1 result is zero 2 0 Example 3 SUBLW 0x02 Before Instruction W 3 C 7 After Instruction FF 25 complement 0 result is negative 0 1 ZNOS SUBWF Subtract W from f Syntax label SUBWF f d a Operands 0 lt 1 lt 255
296. estination FILE f 12 bit file register address Bit oriented file register operations 15 12 11 9 8 7 0 b BIT f FILE BSF MYREG bit B b 3 bit position of bit in file register f 0 to force Access Bank 1 for BSR to select bank f 8 bit file register address Literal operations 15 8 7 0 k literal Ox7F k 8 bit immediate value Control operations CALL GOTO and Branch operations 15 87 0 OPCODE lt 7 0 gt literal GOTO Label 15 12 11 0 1111 lt 19 8 gt literal 20 bit mmediate value 15 8 7 0 n lt 7 0 gt literal CALL MYFUNC 15 12 11 0 n lt 19 8 gt literal S Fast bit 15 11 10 0 OPCODE n lt 10 0 gt literal BRA MYFUNC 15 87 0 n lt 7 0 gt literal BC MYFUNC 2006 Microchip Technology Inc DS39564C page 213 PIC18FXX2 TABLE 20 2 PIC18FXXX INSTRUCTION SET CONTINUED Mnemonic 16 Bit Instruction Word Status Description Cycles Notes Operands MSb LSb Affected CONTROL OPERATIONS BC n Branch if Carry 1 2 1110 0010 nnnn nnmn None n Branch if Negative 1 2 1110 0110 nnnn nmmn None BNC n Branch if Not Carry 1 2 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 2 1110 0111 nnnn nnmn None BNOV n Branch if Not Overflow 1 2 11
297. ete tenete tenente retirees tentent niente 20 mA Output clamp current IOK VO lt 0 or VO gt VDD rennes 20 mA Maximum output current sunk by any I O pin nennen nnne nnne nennen 25 mA Maximum output current sourced by any pin sise 25 mA Maximum current sunk by PORTA PORTB and PORTE Note 3 200 mA Maximum current sourced by PORTA PORTB and PORTE Note 3 200 mA Maximum current sunk by PORTC and PORTD Note 3 combined 200 mA Maximum current sourced by PORTC and PORTD Note 3 combined 200 mA Note 1 Power dissipation is calculated as follows Pdis VDD x IDD Z VDD VOH x 2 Vol x 101 2 Voltage spikes below Vss at MCLR VPP pin inducing currents greater than 80 mA may cause latchup Thus a series resistor of 50 1000 should be used when applying a low level to the MCLR VPP pin rather than pulling this pin directly to Vss 3 PORTD and PORTE not available on the PIC18F2X2 devices T NOTICE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect d
298. event CCPIF bit is set 11xx PWM mode Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 1 Bit is set Bit is cleared Bit is unknown 2006 Microchip Technology Inc DS39564C page 117 PIC18FXX2 14 1 CCP1 Module Capture Compare PWM Register 1 CCPR1 is com prised of two 8 bit registers CCPR1L low byte and CCPRIH high byte The CCP1CON register controls the operation of CCP1 All are readable and writable TABLE 14 1 CCP MODE TIMER RESOURCE CCP Mode Timer Resource Capture Timer1 or Timer3 Compare Timer1 or Timer3 PWM Timer2 14 2 2 Module Capture Compare PWM Register2 CCPR2 is com prised of two 8 bit registers CCPR2L low byte and CCPR2H high byte The CCP2CON register controls the operation of 2 All are readable and writable TABLE 14 2 INTERACTION OF TWO MODULES CCPx Mode CCPy Mode Interaction Capture Capture TMR1 or TMR3 time base Time base can be different for each CCP Capture Compare compare could be configured for the special event trigger which clears either TMR1 or TMR3 depending upon which time base is used Compare Compare compare s could be configured for the special event trigger which clears TMR1 or TMR3 depending upon which time base is used PWM PWM The PWMs will have the same frequency and update rate TMR2
299. evice reliability 2006 Microchip Technology Inc DS39564C page 259 PIC18FXX2 FIGURE 22 1 PIC18FXX2 VOLTAGE FREQUENCY GRAPH INDUSTRIAL 6 0V 5 5V 5 0V PIC18FXXX 4 5V 4 0V 3 5V T 3 0V T 2 5V 2 0V 1 4 2V Voltage 40 MHz Frequency FIGURE 22 2 PIC18LFXX2 VOLTAGE FREQUENCY GRAPH INDUSTRIAL 4 5v PIC 18LFXXX 4 2V Voltage 4 MHz 40 MHz Frequency FMAX 16 36 MHZ V VDDAPPMIN 2 0V 4 MHz Note VDDAPPMIN is the minimum voltage of the PICmicro device in the application DS39564C page 260 2006 Microchip Technology Inc PIC18FXX2 22 1 DC Characteristics PIC18FXX2 Industrial Extended PIC18LFXX2 Industrial PIC18LFXX2 Industrial PIC18FXX2 Industrial Extended Param No 0001 0001 0002 0003 0004 0005 0005 Symbol VDD VDR VPOR SVDD VBOR Standard Operating Conditions unless otherwise stated Operating temperature 40 lt TA 85 for industrial Standard Operating Conditions unless otherwise stated Characteristic Min Supply Voltage PIC18LFXX2 2 0 PIC18FXX2 4 2 RAM Data Retention 1 5 Voltage Start Voltage to ensure internal Power on Reset signal Rise Rate 0 05 to ensure internal Power on Reset signal Brown out Reset Voltage PIC18LFXX2 BORV1 BORVO 11 1 98 BORV1 BORVO 10 2 67 BORV1 BORVO 01 4 16 BORV1 B
300. f Timer1 is not directly readable or writ able in this mode reads and writes must take place through the Timer1 high byte buffer register Writes to TMR1H do not clear the Timeri prescaler The prescaler is only cleared on writes to TMRIL 2006 Microchip Technology Inc DS39564C page 109 PIC18FXX2 TABLE 11 2 REGISTERS ASSOCIATED WITH TIMER1 AS TIMER COUNTER Value o Value on Name Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O All Other i RESETS INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 000x 0000 000u PIR1 PSPIFM ADIF RCIF TXIF SSPIF TMR2IF TMR1IF 0000 0000 0000 0000 PIE PSPIEU ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 pspip ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 TMRIL Holding Register for the Least Significant Byte of the 16 bit TMR1 Register XXXX XXXX UUUU uuuu TMR1H Holding Register for the Most Significant Byte of the 16 bit TMR1 Register XXXX uuuu uuuu T1CON RD16 T1CKPS1 TICKPSO TIOSCEN TISYNC 1 5 TMR1ON 0 00 0000 u uu uuuu Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used by the Timer1 module Note 1 The PSPIF PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices always maintain these bits clear Jc DS39564C page 11
301. f the BF bit is clear This occurs regardless of the state of the SEN bit The user s ISR must set the CKP bit before transmis sion is allowed to continue By holding the SCL line low the user has time to service the ISR and load the contents of the SSPBUF before the master device can initiate another transmit sequence see Figure 15 9 Note 1 If the user loads the contents of SSPBUF setting the BF bit before the falling edge of the ninth clock the CKP bit will not be cleared and clock stretching will not occur 2 The CKP bit can be set in software regardless of the state of the BF bit 15 4 4 4 Clock Stretching for 10 bit Slave Transmit Mode In 10 bit Slave Transmit mode clock stretching is con trolled during the first two address sequences by the state of the UA bit just as it is in 10 bit Slave Receive mode The first two addresses are followed by a third address sequence which contains the high order bits of the 10 bit address and the R W bit set to 1 After the third address sequence is performed the UA bit is not set the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7 bit Slave Transmit mode see Figure 15 11 DS39564C page 144 2006 Microchip Technology Inc PIC18FXX2 15 4 4 5 Clock Synchronization and the CKP bit If a user clears the bit the SCL output is forced to 0 Setting the bit will not assert the SCL ou
302. for the LCD signals 21 14 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers including PIC17C752 PIC17C756A PIC17C762 and PIC17C766 All neces sary hardware is included to run basic demo programs which are supplied on a 3 5 inch disk A programmed sample is included and the user may erase it and program it with the other sample programs using the PRO MATE device programmer the PICSTART Plus development programmer and easily debug and test the sample code In addition the PICDEM 17 dem onstration board supports downloading of programs to and executing out of external FLASH memory on board The PICDEM 17 demonstration board is also usable with the MPLAB ICE in circuit emulator or the PICMASTER emulator and all of the sample programs can be run and modified using either emulator Addition ally a generous prototype area is available for user hardware 21 15 KEELOQ Evaluation and Programming Tools KEELOO evaluation and programming tools support Microchip s HCS Secure Data Products The 5 eval uation kit includes a LCD display to show changing codes a decoder to decode transmissions and a programming interface to program test transmitters DS39564C page 256 2006 Microchip Technology Inc PIC18FXX2 DEVELOPMENT TOOLS FROM MICROCHIP TABLE 21 1 1919 uo e qe reAe SI 00
303. fter Instruction W 0x4F REG Ox4F 2006 Microchip Technology Inc DS39564C page 237 PIC18FXX2 MULLW Multiply Literal with W Syntax label k Operands 0 lt lt 255 Operation W xk gt PRODH PRODL Status Affected None Encoding 0000 1101 kkkk kkkk Description An unsigned multiplication is car ried out between the contents of W and the 8 bit literal The 16 bit result is placed in PRODH PRODL register pair PRODH contains the high byte W is unchanged None of the status flags are affected Note that neither overflow nor carry is possible in this opera tion A zero result is possible but not detected Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write literal k Data registers PRODH PRODL Example MULLW 0xC4 Before Instruction W OxE2 PRODH 2 PRODL 2 After Instruction W OxE2 PRODH OxAD PRODL 0x08 MULWF Multiply W with f Syntax label MULWF f a Operands 0 lt 1 lt 255 ae 0 1 Operation W x f gt PRODH PRODL Status Affected None Encoding 0000 001a ffff Description An unsigned multiplication is car ried out between the contents of W and the register file location f The 16 bit result is stored in the PRODH PRODL register pair PRODH contains the high byte Both W and f are unchanged None of the status flags are affected Note tha
304. ghted work you may have a right to sue for relief under that Act Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates It is your responsibility to ensure that your application meets with your specifications MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED WRITTEN OR ORAL STATUTORY OR OTHERWISE RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ITS CONDITION QUALITY PERFORMANCE MERCHANTABILITY OR FITNESS FOR PURPOSE Microchip disclaims all liability arising from this information and its use Use of Microchip devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless Microchip from any and all damages claims Suits or expenses resulting from such use No licenses are conveyed implicitly or otherwise under any Microchip intellectual property rights Trademarks The Microchip name and logo the Microchip logo Accuron dsPIC KEELOQ microID MPLAB PIC PICmicro PICSTART PRO PowerSmart rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U S A and other countries AmpLab FilterLab Migratable Memory MXDEV MXLAB SEEVAL SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U
305. gister file map detail see Table 4 1 0000h OFFFh 2006 Microchip Technology Inc DS39564C page 51 PIC18FXX2 4 13 STATUS Register The STATUS register shown in Register 4 2 contains the arithmetic status of the ALU The STATUS register can be the destination for any instruction as with any other register If the STATUS register is the destination for an instruction that affects the 2 DC or N bits then the write to these five bits is disabled These bits are set or cleared according to the device logic There fore the result of an instruction with the STATUS register as destination may be different than intended REGISTER 4 2 STATUS REGISTER For example CLRF STATUS will clear the upper three bits and set the Z bit This leaves the STATUS register as 000u uluu where u unchanged It is recommended therefore that only BCF BSF SWAPF MOVFF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z C DC OV or N bits from the STATUS register For other instructions not affecting any status bits see Table 20 2 Note C and DC bits operate as a borrow and digit borrow bit respectively in subtraction U 0 U 0 U 0 R W x R W x R W x R W x R W x N OV Z DC bit 7 bit O bit 7 5 Unimplemented Read as 0 bit 4 N Negative bit This bit is used for signed arithmetic
306. global interrupt sources there are two Peripheral Interrupt enable bit GIE INTCON lt 7 gt Flag Registers PIR1 PIR2 2 User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt REGISTER 8 4 PIR1 PERIPHERAL INTERRUPT REQUEST FLAG REGISTER 1 R W 0 R W 0 R 0 R 0 R W 0 R W 0 R W 0 R W 0 PsPirF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 PSPIF Parallel Slave Port Read Write Interrupt Flag bit 1 read or a write operation has taken place must be cleared in software 0 No read or write has occurred bit 6 ADIF A D Converter Interrupt Flag bit 1 An A D conversion completed must be cleared in software 0 The A D conversion is not complete bit 5 RCIF USART Receive Interrupt Flag bit 1 The USART receive buffer RCREG is full cleared when RCREG is read 0 The USART receive buffer is empty bit 4 TXIF USART Transmit Interrupt Flag bit see Section 16 0 for details on TXIF functionality 1 The USART transmit buffer TXREG is empty cleared when TXREG is written 0 The USART transmit buffer is full bit 3 SSPIF Master Synchronous Serial Port Interrupt Flag bit 1 The transmission reception is complete must be cleared in software 0 Waiting to transmit receive bit 2 CCP1 Interrupt Flag bit Capture mode 1 A TMRI register capture occurred must be clea
307. he TBLPTR a 21 bit pointer points to each byte in the program memory TBLPTR has a 2 MBtye address range The LSb of the TBLPTR selects which byte of the program memory location to access TBLPTR O0 0 Least Significant Byte of Program Memory Word TBLPTR O0 1 Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows change post increment post decrement pre increment 1 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No operation No No No operation operation No No No operation operation Read Write to Holding Register or Memory TABLAT DS39564C page 250 TBLWT Table Write Continued Example TBLWT Before Instruction TABLAT 0 55 TBLPTR 0x00A 356 HOLDING REGISTER 0x00A356 OxFF After Instructions table write completion TABLAT 0x55 TBLPTR 0x00A 357 HOLDING REGISTER 0x00A356 0 55 2 TBLWT Before Instruction TABLAT 0 34 TBLPTR 0x01389A HOLDING REGISTER 0x01389A HOLDING REGISTER 0x01389B OxFF After Instruction table write completion TABLAT 0 34 TBLPTR 0 013898 HOLDING REGISTER 0x01389A OxFF HOLDING REGISTER 0x01389B 0x34 2006 Microchip Technology Inc PIC18FXX2 XORWF Exclusive OR W with f 0 lt 1 lt 255 d e 0 1 a e 0 1 Operation W
308. he device clock 4 The time of the A D clock period is dependent on the device freguency and the TAD clock divider DS39564C page 288 2006 Microchip Technology Inc PIC18FXX2 23 0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only The performance characteristics listed herein are not tested or guaranteed In some graphs or tables the data presented may be outside the specified operating range e g outside specified power supply range and therefore outside the warranted range Typical represents the mean of the distribution at 25 C Maximum or minimum represents mean 30 or mean 36 respectively where is a standard deviation over the whole temperature range FIGURE 23 1 TYPICAL 1 vs Fosc OVER HS MODE 12 Typical statistical mean 25 C 5 5V 10 Maximum mean 30 40 C to 125 C Minimum mean 40 C to 125 C 5 0V 8 4 5V 4 0V t 8 3 5V 4 3 0V 2 2 5V lt 20v 0 4 6 8 10 12 14 16 18 20 22 24 26 Fosc MHz FIGURE 23 2 MAXIMUM vs Fosc OVER HS MODE 12 5 5V Typical statistical mean 25 C 5 0V 10 Maximum mean 30 40 C to 125 C Minimum mean 3o 40 C to 125 C 4 5V 8 4 0V
309. he ninth clock cycle by setting the SSPIF bit The user generates a STOP condition by setting the STOP enable bit PEN SSPCON2 lt 2 gt Interrupt is generated once the STOP condition is complete 2006 Microchip Technology Inc PIC18FXX2 15 4 7 BAUD RATE GENERATOR In 2 Master mode the baud rate generator BRG reload value is placed in the lower 7 bits of the SSPADD register Figure 15 17 When a write occurs to SSPBUF the baud rate generator will automatically begin counting The BRG counts down to 0 and stops until another reload has taken place The BRG count is decremented twice per instruction cycle Tcy on the Q2 and 04 clocks In Master mode the BRG is reloaded automatically FIGURE 15 17 Once the given operation is complete i e transmis sion of the last data bit is followed by ACK the internal clock will automatically stop counting and the SCL pin will remain in its last state Table 15 3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3 SSPMO SCL Reload Control SSPM3 SSPMO SSPADD lt 6 0 gt Reload lt BRG Down Counter Fosc 4 TABLE 15 3 CLOCK RATE W BRG Fcy 2 Value 2 Rollovers of BRG 10 MHz 20 MHz 19h 400 kHz 10 MHz 20 MHz 20h 312 5 kHz 10 MHz 2
310. he table Note 1 This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET without losing RAM data 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as I O pin loading and switching rate oscillator type internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active Operation mode are OSC1 external square wave from rail to rail all I O pins tri stated pulled to VDD MCLR VDD WDT enabled disabled as specified 3 The power down current in SLEEP mode does not depend on the oscillator type Power down current is measured with the part in SLEEP mode with all I O pins in hi impedance state and tied to VDD or Vss and all features that add delta current disabled such as WDT Timer1 Oscillator 4 For RC osc configuration current through REXT is not included The current through the resistor can be estimated by the formula Ir VDD 2REXT mA with REXT in kOhm 5 The LVD and BOR modules share a large portion of circuitry The AIBOR and AILVD currents are not additive Once one of these modules is enabled the other may also be enabled without further penalty DS39564C page 262 2006 Microchip Technology Inc PIC18FXX2 22 1 DC Characteristics PIC18FXX2 Industrial Extended PIC18LFXX2 Industrial Continued
311. ight or nine data bits and one STOP bit The most common data format is 8 bits An on chip dedicated 8 bit baud rate genera tor can be used to derive standard baud rate frequen cies from the oscillator The USART transmits and receives the LSb first The USART s transmitter and receiver are functionally independent but use the same data format and baud rate The baud rate gener ator produces a clock either x16 or x64 of the bit shift rate depending on bit BRGH TXSTA lt 2 gt Parity is not supported by the hardware but can be implemented in software and stored as the ninth data bit Asynchronous mode is stopped during SLEEP Asynchronous mode is selected by clearing bit SYNC TXSTA lt 4 gt The USART Asynchronous module consists of the following important elements Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver 16 2 1 USART ASYNCHRONOUS TRANSMITTER The USART transmitter block diagram is shown in Figure 16 1 The heart of the transmitter is the Transmit serial Shift Register TSR The shift register obtains its data from the read write transmit buffer TXREG The TXREG register is loaded with data in software The TSR register is not loaded until the STOP bit has been transmitted from the previous load As soon as the STOP bit is transmitted the TSR is loaded with new data from the TXREG register if available Once the TXREG register transfers the data to the TS
312. ility It has an LCD display for instructions and error messages keys to enter commands and a modular detachable socket assembly to support various package types In stand alone mode the PRO MATE II device programmer can read verify or program PICmicro devices It can also set code protection in this mode 21 10 PICSTART Plus Entry Level Development Programmer The PICSTART Plus development programmer is an easy to use low cost prototype programmer It con nects to the PC via a COM RS 232 port MPLAB Integrated Development Environment software makes using the programmer simple and efficient The PICSTART Plus development programmer sup ports all PICmicro devices with up to 40 pins Larger pin count devices such as the PIC16C92X and PIC17C76X may be supported with an adapter socket The PICSTART Plus development programmer is CE compliant 21 11 PICDEM 1 Low Cost micro Demonstration Board The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip s microcontrollers The microcontrollers sup ported are PIC16C5X PIC16C54 to 16 58 PIC16C61 PIC16C62X PIC16C71 PIC16C8X PIC17C42 PIC17C43 and 17 44 necessary hardware and software is included to run basic demo programs The user can program the sample microcon trollers provided with the PICDEM 1 demonstration board on a PRO MATE II device programmer or a PICSTART Plus development programmer a
313. ill override the input state with the output data when required slave transmitter The 12 Slave mode hardware will always generate an interrupt on an address match Through the mode select bits the user can also choose to interrupt on START and STOP bits When an address is matched or the data transfer after an address match is received the hardware automati cally will generate the Acknowledge ACK pulse and load the SSPBUF register with the received value currently in the SSPSR register Any combination of the following conditions will cause the MSSP module not to give this ACK pulse The buffer full bit BF SSPSTAT lt 0 gt was set before the transfer was received The overflow bit SSPOV 55 lt 6 gt was set before the transfer was received In this case the SSPSR register value is not loaded into the SSPBUF but bit SSPIF PIR1 lt 3 gt is set The BF bit is cleared by reading the SSPBUF register while bit SSPOV is cleared through software The SCL clock input must have a minimum high and low for proper operation The high and low times of the 2 specification as well as the requirement of the MSSP module are shown in timing parameter 100 and parameter 101 15 4 3 1 Addressing Once the MSSP module has been enabled it waits for a START condition to occur Following the START con dition the 8 bits are shifted into the SSPSR register All incoming bits are sampled with the rising edge of the clock
314. in Low Voltage ICSP mode the RB5 pin can no longer be used as a gen eral purpose pin and should be held low during normal operation to protect against inadvertent ICSP mode entry 2 When using Low Voltage ICSP program ming LVP the pull up on RB5 becomes disabled If TRISB bit 5 is cleared thereby setting RB5 as an output LATB bit 5 must also be cleared for proper operation DS39564C page 90 2006 Microchip Technology Inc PIC18FXX2 FIGURE 9 5 BLOCK DIAGRAM OF RB2 RBO PINS RBPUU Weak 4 eH P Pull up Data Latch Data Bus ID a a 1 0 pin WR Port 23 TRIS Latch D a TIL JL Input CK Buffer RD TRIS DH RD Port EN RBO INT Schmitt Trigger RD Port Buffer Note 1 O pins have diode protection to VDD and Vss 2 To enable weak pull ups set the appropriate TRIS bit s and clear the RBPU bit OPTION REG lt 7 gt FIGURE 9 6 BLOCK DIAGRAM OF RB3 PIN 9750 CCP2MX __ _ _ Pull up CCP Output VoD HP Enable 0 om 55 Data Latch 3 Data Bus e D pin WR LATB or PORT B D TRIS Latch Vss D TIL 7 WR TRISB EE Input Buffer RD TRISB RD LATB RD PORTB EN RD PORTB CCP2
315. in is mit the SCL line is held low after the falling edge of the pulled low and the contents of the Acknowledge data bit ninth clock When the PEN bit is set the master will are presented on the SDA pin If the user wishes to gen assert the SDA line low When the SDA line is sampled erate an Acknowledge then the ACKDT bit should be low the baud rate generator is reloaded and counts Cleared If not the user should set the ACKDT bit before down to 0 When the baud rate generator times out the starting an Acknowledge sequence The baud rate gen SCL pin will be brought high and one TBRG baud rate erator then counts for one rollover period TBRG and the generator rollover count later the SDA pin will be SCL pin is de asserted pulled high When the SCL pin de asserted When the SDA pin is sampled high while is sampled high clock arbitration the baud rate gener SCL is high the P bit SSPSTAT 4 is set A TBRG ator counts for TBRG The SCL pin is then pulled low Fol later the PEN bit is cleared and the SSPIF bit is set lowing this the ACKEN bit is automatically cleared the Figure 15 24 baud rate generator is turned off and the MSSP module then goes into IDLE mode Figure 15 23 15 4 13 1 WCOL Status Flag If the user writes the SSPBUF when a STOP sequence 15 4 12 1 WCOL Status Flag is in progress then the WCOL bit is set and the con If the user writes the SSPBUF when an Acknowledge tents of the buffer are unchanged the write doesn t
316. ine if the device voltage is below a specified voltage level is a desirable feature window of operation for the application can be created where the application soft ware can do housekeeping tasks before the device voltage exits the valid operating range This can be done using the Low Voltage Detect module This module is a software programmable circuitry where a device voltage trip point can be specified When the voltage of the device becomes lower then the specified point an interrupt flag is set If the interrupt is enabled the program execution will branch to the inter rupt vector address and the software can then respond to that interrupt source FIGURE 18 1 The Low Voltage Detect circuitry is completely under software control This allows the circuitry to be turned off by the software which minimizes the current consumption for the device Figure 18 1 shows a possible application voltage curve typically for batteries Over time the device voltage decreases When the device voltage eguals voltage VA the LVD logic generates an interrupt This occurs at time TA The application software then has the time until the device voltage is no longer in valid operating range to shutdown the system Voltage point VB is the minimum valid operating voltage specification This occurs at time TB The difference TB TA is the total time for shutdown TYPICAL LOW VOLTAGE DETECT APPLICATION VA VB
317. ing mode can be used to program the device When using low voltage ICSP the part must be sup plied 4 5V to 5 5V if a bulk erase will be executed This includes reprogramming of the code protect bits from an on state to off state For all other cases of low volt DS39564C page 210 2006 Microchip Technology Inc PIC18FXX2 20 0 INSTRUCTION SET SUMMARY The PIC18FXXX instruction set adds many ments to the previous PICmicro instruction sets while maintaining an easy migration from these PICmicro instruction sets Most instructions are a single program memory word 16 bits but there are three instructions that require two program memory locations Each single word instruction is a 16 bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction The instruction set is highly orthogonal and is grouped into four basic categories Byte oriented operations Bit oriented operations Literal operations Control operations The PIC18FXXX instruction set summary in Table 20 2 lists byte oriented bit oriented literal and control operations Table 20 1 shows the opcode field descriptions Most byte oriented instructions have three operands 1 The file register specified by f 2 The destination of the result specified by d 3 The accessed memory specified by a The file register designator spe
318. instruction of the called routine is the ADDWF PCL instruction The next instruction executed will be one of the RETLW Oxnn instructions that returns the value 0xnn to the calling function The offset value value in WREG specifies the number of bytes that the program counter should advance In this method only one data byte may be stored in each instruction location and room on the return address stack is required Note The ADDWF PCL instruction does not update PCLATH and PCLATU A read operation on PCL must be performed to update PCLATH and PCLATU 4 8 2 TABLE READS TABLE WRITES A better method of storing data in program memory allows 2 bytes of data to be stored in each instruction location Lookup table data may be stored 2 bytes per program word by using table reads and writes The table pointer TBLPTR specifies the byte address and the table latch TABLAT contains the data that is read from or written to program memory Data is transferred to from program memory one byte at a time A description of the Table Read Table Write operation is shown in Section 3 0 2006 Microchip Technology Inc DS39564C page 41 PIC18FXX2 4 9 Data Memory Organization The data memory is implemented as static RAM Each register in the data memory has a 12 bit address allowing up to 4096 bytes of data memory Figure 4 6 and Figure 4 7 show the data memory organization for the PIC18FXX2 devices The data m
319. ion HERE CPFSEQ REG 0 NEQUAL EQUAL Before Instruction PC Address HERE Ww 7 REG 2 After Instruction If REG W PC Address EQUAL If REG W PC Address NEQUAL DS39564C page 228 2006 Microchip Technology Inc PIC18FXX2 CPFSGT Compare f with W skip if f gt W CPFSLT Compare f with W skip if f lt W Syntax label CPFSGT f a Syntax label CPFSLT Operands 0 lt 1 lt 255 Operands 0 lt lt 255 0 1 0 1 Operation f W Operation f W skip if f gt W skip if f lt W unsigned comparison unsigned comparison Status Affected None Status Affected None Encoding 0110 010a ffff Encoding 0110 000a ffff Description Compares the contents of data Description Compares the contents of data memory location f to the contents memory location f to the contents of the W by performing an of W by performing an unsigned unsigned subtraction subtraction If the contents are greater than If the contents of are less than the contents of WREG then the the contents of W then the fetched fetched instruction is discarded and instruction is discarded and a NOP a NOP is executed instead making is executed instead making this a this a two cycle instruction If a is two cycle instruction If a is 0 the 0 the Access Bank will be Access Bank will be selected If a selected overriding the BSR valu
320. ion If No Jump Q1 Q2 Q3 Q4 Decode Read literal Process No n Data operation Example HERE BC 5 Before Instruction PC address HERE After Instruction If Carry 1 address HERE 12 If Carry 0 PC address HERE 2 2006 Microchip Technology Inc DS39564C page 219 PIC18FXX2 BCF Bit Clear f Syntax label BCF f b a Operands 0 lt lt 255 O lt b lt 7 ae 0 1 Operation 0 f lt b gt Status Affected None Encoding 1001 ffff Description Bit b in register is cleared If a is 0 the Access Bank will be selected overriding the BSR value If a 1 then the bank will be selected as per the BSR value default Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write register f Data register f Example BCF FLAG REG 7 0 Before Instruction FLAG REG 0xC7 After Instruction FLAG REG 0x47 BN Syntax Operands Operation Status Affected Encoding Description Words Cycles Branch if Negative label BN n 128 lt n lt 127 if negative bit is 1 PC 2 2n PC None 1110 0110 nnnn nnnn If the Negative bit is 1 then the program will branch The 2 s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a two cycle instruction 1 12 DS39564C
321. ional pushes will not overwrite the 31st push and STKPTR will remain at 31 When the stack has been popped enough times to unload the stack the next pop will return a value of zero to the PC and sets the STKUNF bit while the stack pointer remains at 0 The STKUNF bit will remain set until cleared in software or a POR occurs Note Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the RESET vector where the stack conditions can be verified and appropriate actions can be taken 2006 Microchip Technology Inc DS39564C page 37 PIC18FXX2 REGISTER 4 1 STKPTR REGISTER R C 0 R C 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 STKOVF STKUNF SP4 SP3 SP2 SP1 SPO bit 7 bit O bit 7 STKOVF Stack Full Flag bit 1 Stack became full or overflowed Stack has not become full or overflowed bit 61 STKUNF Stack Underflow Flag bit 1 Stack underflow occurred Stack underflow did not occur bit 5 Unimplemented Read as 0 bit 4 0 SP4 SPO Stack Pointer Location bits Note 1 Bit 7 and bit 6 can only be cleared in user software or by a POR Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 1 Bitis set 0 Bit is cleared x Bit is unknown FIGURE 4 3 RETURN ADDRESS STACK AND ASSOCIATED REGISTERS TOSU TOSH TOSL 0x00 0x34 T Top of Stack Return Addres
322. ious Situations 27 eerte te e peel neve cet 1038 16 bit Mode Timer Reads and Writes 105 Associated Registers T Clock Source Edge Select TOSE Bit 105 Clock Source Select TOCS Bit 105 Operation Overflow Interrupt Prescaler See Prescaler imer t o e eure cet eise RE 107 16 bit Read Write Mode 109 Associated Registers 110 Operation ln ina 108 Oscillator 755 109 Overflow Interrupt 22 107 109 Special Event Trigger CCP 109 120 TMR1H Register eene 107 TMRIL Register 107 Tim r2 n ikon ala ve LE Associated Registers 112 Operation iier reete rere tren 111 Postscaler See Postscaler Timer2 PR2 Register 20222 2 111 122 Prescaler See Prescaler Timer2 SSP Clock Shift sss 111 112 2 Register oett tenent 111 TMR2 to PR2 Match Interrupt 111 112 122 2 2 222 sioe EH ERE 113 Associated Registers 115 Operation 00 114 Oscillator DS39564C page 323 PIC18FXX2 Example SPI Master Mode 0 Example SPI Master Mode
323. ip Technology Inc DS39564C page 255 PIC18FXX2 21 13 PICDEM 3 Low Cost PIC16C XXX Demonstration Board The PICDEM 3 demonstration board is a simple dem onstration board that supports the PIC16C923 and PIC16C924 in the PLCC package It will also support future 44 pin PLCC microcontrollers with an LCD Mod ule All the necessary hardware and software is included to run the basic demonstration programs The user can program the sample microcontrollers pro vided with the PICDEM 3 demonstration board on a PRO MATE II device programmer or a PICSTART Plus development programmer with an adapter socket and easily test firmware The MPLAB ICE in circuit emula tor may also be used with the PICDEM 3 demonstration board to test firmware A prototype area has been pro vided to the user for adding hardware and connecting it to the microcontroller socket s Some of the features include a RS 232 interface push button switches a potentiometer for simulated analog input a thermistor and separate headers for connection to an external LCD module and a keypad Also provided on the PICDEM 3 demonstration board is a LCD panel with 4 commons and 12 segments that is capable of display ing time temperature and day of the week The PICDEM 3 demonstration board provides an additional RS 232 interface and Windows software for showing the demultiplexed LCD signals on a PC A simple serial interface allows the user to construct a hardware demultiplexer
324. is received the device will wake up from sleep 15 3 7 SLAVE SELECT SYNCHRONIZATION The SS pin allows a Synchronous Slave mode The SPI must be in Slave mode with SS pin control enabled SSPCON1 lt 3 0 gt 04h The pin must not be driven low for the SS pin to function as an input The Data Latch must be high When the SS pin is low transmis sion and reception are enabled and the SDO pin is driven When the SS pin goes high SDO pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output External pull up pull down resistors may be desirable depending on the application Note 1 When the SPI is in Slave mode with SS pin control enabled SSPCON lt 3 0 gt 0100 the SPI module will reset if the SS pin is set to VDD 2 If the SPI is used in Slave mode with set then the SS pin control must be enabled When the SPI module resets the bit counter is forced to 0 This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit To emulate two wire communication the SDO pin can be connected to the SDI pin When the SPI needs to operate as a receiver the SDO pin can be configured as an input This disables transmissions from the SDO The SDI can always be left as an input SDI function since it cannot create a bus conflict FIGURE 15 4 SLAVE SYNCHRON
325. is set the START condition is aborted and the 2 module is reset into its IDLE state FIGURE 15 19 FIRST START BIT TIMING 15 4 8 1 WCOL Status the user writes the SSPBUF when a START seguence is in progress the WCOL is set and the con tents of the buffer are unchanged the write doesn t occur Note Because queueing of events is allowed writing to the lower 5 bits of SSPCON2 is disabled until the START condition is complete Write to SEN bit occurs here SDA 1 SCL 1 1st bit Set S bit SSPSTAT lt 3 gt At completion of START bit Hardware clears SEN bit and sets SSPIF bit Write to SSPBUF occurs here X 2 k TBRG gt 2006 Microchip Technology Inc DS39564C page 153 PIC18FXX2 15 4 9 2 MASTER MODE REPEATED START CONDITION TIMING A Repeated START condition occurs when the RSEN bit SSPCON2 1 is programmed high and the logic module is in the IDLE state When the RSEN bit is set the SCL pin is asserted low When the SCL pin is sampled low the baud rate generator is loaded with the contents of SSPADD lt 5 0 gt and begins counting The SDA pin is released brought high for one baud rate generator count TBRG When the baud rate generator times out if SDA is sampled high the SCL pin will be de asserted brought high When SCL is sampled high the baud rate generator is reloaded with the con te
326. it GIEH or GIEL if priority levels are used which re enables interrupts For external interrupt events such as the INT pins or the PORTB input change interrupt the interrupt latency will be three to four instruction cycles The exact latency is the same for one or two cycle instructions Individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the GIE bit Note not use the MOVFF instruction to modify any of the Interrupt control registers while any interrupt is enabled Doing so may cause erratic microcontroller behavior 2006 Microchip Technology Inc DS39564C page 73 PIC18FXX2 FIGURE 8 1 INTERRUPT LOGIC Wake up if in SLEEP mode TMRO TMRO TMRO RB RB RB INTO INTO INT1 INT1 Peripheral Interrupt Flag bit INT1 Peripheral Interrupt Enable bit 1 7 1 2 Peripheral Interrupt Priority bit TMRIIF TMRITIE 4 gt TMRIIP XL IPE XXXXIF i IPEN XXXXIE PONE S GIEL PEIE O IPEN Additional Peripheral Interrupts Interrupt to CPU Vector to location 0008h TMA TMT mm GIEH GIE Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMRIIF J RBIF
327. it is set the TOSU TOSH and TOSL are updated with the current value of the PC The STKPTR is modified to point to the next location in the hardware stack 4 See Table 3 2 for RESET value for specific condition 5 Bit 6 of PORTA LATA and TRISA are enabled ECIO and RCIO Oscillator modes only In all other Oscillator modes they are disabled and read 0 6 Bit 6 of PORTA LATA and TRISA are not available on all devices When unimplemented they are read 0 DS39564C page 30 2006 Microchip Technology Inc PIC18FXX2 TABLE 3 3 INITIALIZATION CONDITIONS FOR ALL REGISTERS CONTINUED MCLR Resets Register Applicable Devices ONeron eset WETRereL Wakeup va Wor Stack Resets IPR2 242 442 252 452 1 1111 1 1111 u uuuu PIR2 242 442 252 452 0 0000 0 0000 u uuu PIE2 242 442 252 452 0 0000 0 0000 u uuuu 242 442 252 452 1111 1111 1111 1111 uuuu uuuu 242 442 252 452 111 1111 111 1111 uuu uuuu 242 442 252 452 0000 0000 0000 0000 uuuu uuuull ii 242 442 252 452 000 0000 000 0000 uuu uuuull 242 442 252 452 0000 0000 0000 0000 uuuu uuuu 242 442 252 452 000 0000 000 0000 uuu uuuu TRISE 242 442 252 452 0000 111 0000 111 uuuu uuu TRISD 242 442 252 452 1111 1111 1111 1111 uuuu uuuu TRISC 242 442 252 452 1111 1111 1
328. ition Program RCON Ri PD BOR STKFUL STKUNF Counter Register Power on Reset 0000h 0 1 1100 1 1 1 0 0 u u MCLR Reset during normal 0000h 0 u uuuu u u u u u u u operation Software Reset during normal 0000h 0 0 uuuu 0 u u u u u u operation Stack Full Reset during normal 0000h 0 u uull u u u u u u 1 operation Stack Underflow Reset during 0000h 0 u uull u u u u u 1 u normal operation MCLR Reset during SLEEP 0000h 0 u 10uu u 1 0 u u u u WDT Reset 0000h 0 u 01uu 1 0 1 u u u u WDT Wake up PC 2 u u 00uu u 0 0 u u u u Brown out Reset 0000h 0 1 11u0 1 1 1 0 u u Interrupt wake up from SLEEP 209 u u 00uu u 1 0 u u u u Legend u unchanged x unknown unimplemented bit read as Note 1 When the wake up is due to an interrupt and the GIEH or GIEL bits are set the PC is loaded with the interrupt vector 0x000008h 0x000018h 2006 Microchip Technology Inc DS39564C page 27 PIC18FXX2 TABLE 3 3 INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets Register AppiesieDewees MO Stack Resets TOSU 242 442 252 452 0 0000 0 0000 0 uuu TOSH 242 442 252 452 0000 0000 0000 0000 uuuu TOSL 242 442 252 452 0000 0000 0000 0000 uuuu STKPTR 242 442 252 452 00 0 0000 uu 0 0000 uu u uuuuU PCLATU 242 442
329. iver in a Hi Impedance mode Clearing a TRISB bit 0 will make the corresponding PORTB pin an output i e put the contents of the output latch on the selected pin The Data Latch register LATB is also memory mapped Read modify write operations on the LATB register reads and writes the latched output value for PORTB EXAMPLE 9 2 CLRF PORTB INITIALIZING PORTB Initialize PORTB by clearing output data latches Alternate method to clear output data latches Value used to CLRF LATB MOVLW OxCF initialize data direction Set RB 3 0 as inputs RB 5 4 as outputs RB 7 6 as inputs MOVWF TRISB Each of the PORTB pins has a weak internal pull up A single control bit can turn on all the pull ups This is per formed by clearing bit RBPU INTCON2 lt 7 gt The weak pull up is automatically turned off when the port pin is configured as an output The pull ups are disabled on a Power on Reset Note On a Power on Reset these pins are configured as digital inputs Four of the PORTB pins RB7 RB4 have an interrupt on change feature Only pins configured as inputs can cause this interrupt to occur i e any RB7 RB4 pin configured as an output is excluded from the interrupt on change comparison The input pins of RB7 RB4 are compared with the old value latched on the last read of PORTB The mismatch outputs of RB7 RB4 are OR ed together to generate the RB Port Chang
330. k The data recovery block is actually a high speed shifter operating at x16 times the baud rate whereas the main receive serial shifter oper ates at the bit rate or at FOSC This mode would typically be used in RS 232 systems To set up an Asynchronous Reception 1 Initialize the SPBRG register for the appropriate baud rate If a high speed baud rate is desired set bit BRGH Section 16 1 Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN If interrupts are desired set enable bit RCIE If 9 bit reception is desired set bit RX9 Enable the reception by setting bit CREN Flag bit RCIF will be set when reception is com plete and an interrupt will be generated if enable bit RCIE was set 7 Read the register to get the ninth bit if enabled and determine if any error occurred during reception 8 Read the 8 bit received data by reading the RCREG register 9 If any error occurred clear the error by clearing enable bit CREN 10 If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON lt 7 6 gt set m FIGURE 16 4 16 2 3 SETTING UP 9 BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS 485 systems To set up an Asynchronous Reception with Address Detect Enable 1 Initialize the SPBRG register for the appropriate baud rate If a high speed baud rate is required set the BRGH bit 2 Enable the asynchrono
331. l Adjust W Register Syntax label DAW Operands None Operation If W lt 3 0 gt gt 9 or DC 1 then W lt 3 0 gt 6 W lt 3 0 gt else W lt 3 0 gt gt W lt 3 0 gt If W 7 4 gt 9 or C 1 then W lt 7 4 gt 6 gt W lt 7 4 gt else W lt 7 4 gt 2 W lt 7 4 gt Status Affected Encoding 0000 0000 0000 0111 Description DAW adjusts the eight bit value in W resulting from the earlier addi tion of two variables each in packed BCD format and produces a correct packed BCD result Words 1 Cycles 1 G Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write register W Data W Example1 DAW Before Instruction W C 0 DC 0 After Instruction W 0x05 C zu DC 0 Example 2 Before Instruction W OxCE C 0 DC 0 After Instruction W 0x34 C 1 DC 0 DECF Decrement f Syntax label DECF f df a Operands 0 lt 1 lt 255 d e 0 1 0 1 Operation f 1 gt dest Status Affected DC OV Z Encoding 0000 01da ffff Description Decrement register If d is 0 the result is stored in W If d is 1 the result is stored back in register f default If a is 0 the Access Bank will be selected overriding the BSR value If a 2 1 then the bank will be selected as per the BSR value default Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Proc
332. l call address 0000h is received in the SSPSR 0 General call address disabled ACKSTAT Acknowledge Status bit Master Transmit mode only 1 Acknowledge was not received from slave 0 Acknowledge was received from slave ACKDT Acknowledge Data bit Master Receive mode only 1 Not Acknowledge 0 Acknowledge Note Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive ACKEN Acknowledge Sequence Enable bit Master Receive mode only 1 lnitiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit Automatically cleared by hardware 0 Acknowledge sequence IDLE RCEN Receive Enable bit Master mode only 1 Enables Receive mode for 2 Receive IDLE PEN STOP Condition Enable bit Master mode only 1 Initiate STOP condition on SDA and SCL pins Automatically cleared by hardware 0 STOP condition IDLE RSEN Repeated START Condition Enabled bit Master mode only 1 lnitiate Repeated START condition on SDA and SCL pins Automatically cleared by hardware 0 Repeated START condition IDLE SEN START Condition Enabled Stretch Enabled bit In Master mode 1 Initiate START condition on SDA and SCL pins Automatically cleared by hardware 0 START condition IDLE In Slave mode 1 Clock stretching is enabled for both Slave Transmit and Slave Receive stretch enabled 0 Clock stretching is enabled for slave transmit only Legacy mode Note For bits ACKEN
333. l device the data will be written back with a O If this instruction is executed on the TMRO register and where applicable d 1 the prescaler will be cleared if assigned If Program Counter PC is modified or a conditional test is true the instruction requires two cycles The second cycle is executed as Some instructions are 2 word instructions The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits This ensures that all program memory locations have a valid instruction If the Table Write starts the write cycle to internal memory the write will continue until terminated 2006 Microchip Technology Inc DS39564C page 215 PIC18FXX2 TABLE 20 2 PIC18FXXX INSTRUCTION SET CONTINUED Mnemonic 52 16 Bit Instruction Word Status Description Cycles Notes Operands MSb LSb Affected LITERAL OPERATIONS ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C DC Z OV N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk 2 IORLW k Inelusive OR literal with WREG 1 0000 1001 kkkk kkkk 2 LFSR f k Move literal 12 bit 2nd word 2 1110 1110 00 kkkk to FSRx 151 word 1111 0000 kkkk kkkk MOVLB k Move literal to BSR lt 3 0 gt 1 0000 0001 0000 kkkk MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk MULLW k Multiply literal with WR
334. lace The master will set the Bus Collision Interrupt Flag BCLIF and reset the port to its IDLE state Figure 15 25 If transmit was in progress when the bus collision occurred the transmission is halted the BF flag is cleared the SDA and SCL lines are de asserted and the SSPBUF can be written to When the user services the bus collision Interrupt Service Routine and if the 2 bus is free the user can resume communication by asserting a START condition If a START Repeated START STOP or Acknowledge condition was in progress when the bus collision occurred the condition is aborted the SDA and SCL lines are de asserted and the respective control bits in the SSPCON2 register are cleared When the user ser vices the bus collision Interrupt Service Routine and if the 2 bus is free the user can resume communication by asserting a START condition The master will continue to monitor the SDA and SCL pins If a STOP condition occurs the SSPIF bit will be set A write to the SSPBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred In Multi Master mode the interrupt generation on the detection of START and STOP conditions allows the determination of when the bus is free Control of the 2 bus can be taken when the P bit is setin the SSPSTAT register or the bus is IDLE and the S and P bits are cleared BUS COLLISION TIMING FO
335. le RESET After Instruction Registers Reset Value Flags Reset Value 2006 Microchip Technology Inc DS39564C page 241 PIC18FXX2 RETFIE Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Q1 No operation Example After Interrupt STATUS GIE GIEH PEIE GIEL Return from Interrupt abel s S e 0 1 TOS gt PC 1 GIE GIEH or PEIE GIEL if s 1 WS 5 W STATUSS STATUS BSRS BSR PCLATU PCLATH are unchanged GIE GIEH PEIE GIEL 0000 0000 0001 000s Return from Interrupt Stack is popped and Top of Stack TOS is loaded into the PC Interrupts are enabled by setting either the high or low priority global interrupt enable bit If s 1 the contents of the shadow registers WS STATUSS and BSRS are loaded into their corresponding registers W STATUS and BSR If s 0 no update of these registers occurs default Q2 Q3 Q4 No No operation pop PC from stack Set GIEH or GIEL No No No operation operation operation operation RETFIE TOS WS BSRS STATUSS 1 RETLW Return Literal to W Syntax label RETLW k Operands 0 lt k lt 255 Operation ko TOS PC PCLATU PCLATH are unchanged Status Affected None Encoding 0000 1100 kkkk kkkk Description W is loaded with the eight bit
336. les 1 2 Q Cycle Activity Q Cycle Activity If Jump If Jump Q1 Q2 Q3 Q4 Q1 Q2 Q3 04 Decode Read literal Process Write to PC Decode Read literal Process Write to PC n Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump If No Jump Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No n Data operation n Data operation Example HERE BNOV Jump Example HERE BNZ Jump Before Instruction Before Instruction PC address HERE PC address HERE After Instruction After Instruction If Overflow 2 If Zero address Jump PC address Jump If Overflow If Zero 2 address HERE 2 PC address HERE 2 SEE SS DS39564C page 222 2006 Microchip Technology Inc PIC18FXX2 BRA Unconditional Branch BSF BitSetf Syntax abel Syntax label BSF f b a Operands 1024 lt n lt 1023 Operands O lt f lt 255 Operation PC 2 2n PC lt D 19 Status Affected None Erodi Operation 1 gt f lt b gt ncoaing 1101 Onnn nnnn nnnn 8 Status Affected None Description Add the 2 5 complement number On to the PC Since the PC will Encoding 1000 bbba have incremented to fetch the next Description Bit b in register is set If a is 0 instruction the ne
337. literal k The program counter is loaded from the top of the stack the return address The high address latch PCLATH remains unchanged Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process PC from literal k Data stack Write to W No No No No operation operation operation operation Example CALL TABLE W contains table offset value W now has table value TABLE ADDWF PCL offset RETLW Begin table RETLW k1 RETN kn End of table Before Instruction W 0x07 After Instruction Ww value of kn DS39564C page 242 2006 Microchip Technology Inc PIC18FXX2 RETURN Return from Subroutine Syntax label RETURN s Operands s e 0 1 Operation TOS PC if s 1 WS gt W STATUSS STATUS BSRS BSR PCLATU PCLATH are unchanged Status Affected None Encoding 0000 0000 0001 0018 Description Return from subroutine The stack is popped and the top of the stack TOS is loaded into the program counter If s 1 the contents of the shadow registers WS STATUSS and BSRS are loaded into their cor responding registers W STATUS and BSR 5 0 no update of these registers occurs default Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No Process PC from operation Data stack No No No No operation operation operation operation Example RETURN After Interrupt TOS
338. literal Process Write to PC n Data No No No No operation operation operation operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal Process No n Data operation Example HERE BNC Jump Before Instruction PC address HERE After Instruction If Carry PC address Jump If Carry address HERE 2 If Negative PC If Negative PC address Jump address HERE 2 2006 Microchip Technology Inc DS39564C page 221 PIC18FXX2 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax label BNOV Syntax label BNZ n Operands 128 lt lt 127 Operands 128 lt lt 127 Operation if overflow bit is O Operation if zero bit is 0 PC 2 2n PC PC 2 2 5 Status Affected None Status Affected None Encoding 1110 0101 nnnn nnnn Encoding 1110 0001 nnnn nnnn Description If the Overflow bit is 0 then the Description If the Zero bit is V then the pro program will branch gram will branch The 2 s complement number 2n is The 2 s complement number 2n is added to the PC Since the PC will added to the PC Since the PC will have incremented to fetch the next have incremented to fetch the next instruction the new address will be instruction the new address will be PC 2 2n This instruction is then PC 2 2n This instruction is then a two cycle instruction a two cycle instruction Words 1 Words 1 Cycles 1 2 Cyc
339. ll be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits This ensures that all program memory locations have a valid instruction If the Table Write starts the write cycle to internal memory the write will continue until terminated DS39564C page 216 2006 Microchip Technology Inc PIC18FXX2 20 1 Instruction Set ADDLW ADD literal to W Syntax label ADDLW k Operands 0 lt lt 255 Operation Status Affected N OV C DC Z Encoding 0000 1111 kkkk kkkk Description The contents of W are added to the 8 bit literal k and the result is placed in W Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to W literal k Data Example ADDLW 0x15 Before Instruction W 0x10 After Instruction W 0x25 ADDWF ADD W to f Syntax label ADDWF A f d a Operands 0 lt 1 lt 255 d e 0 1 0 1 Operation W f gt dest Status Affected N OV C DC Z Encoding 0010 01da ffff Description Add W to register If d is 0 the result is stored in W If d is 1 the result is stored back in register f default If a is 0 the Access Bank will be selected If a is 1 the BSR is used Words 1 Cycles 1 Q Cycle Activity Q1 Q2 04 Decode Read Process Write to register Data destination Example ADDWF REG
340. loat high the BRG is loaded with SSPADD lt 6 0 gt and counts down to 0 The SCL pin is then de asserted and when sampled high the SDA pin is sampled If SDA is low a bus collision has occurred i e another master is attempting to transmit a data 0 Figure 15 29 If SDA is sampled high the BRG is FIGURE 15 29 reloaded and begins counting If SDA goes from high to low before the BRG times out no bus collision occurs because no two masters can assert SDA at exactly the same time If SCL goes from high to low before the BRG times out and SDA has not already been asserted a bus collision occurs In this case another master is attempting to transmit a data 1 during the Repeated START condition Figure 15 30 If at the end of the BRG time out both SCL and SDA are still high the SDA pin is driven low and the BRG is reloaded and begins counting At the end of the count regardless of the status of the SCL pin the SCL pin is driven low and the Repeated START condition is complete BUS COLLISION DURING A REPEATED START CONDITION CASE 1 SDA SCL Sample SDA when SCL goes high If SDA 0 set BCLIF and release SDA and SCL RSEN BCLIF 1 Cleared in software 5 0 SSPIF FIGURE 15 30 BUS COLLISION DURING REPEATED START CONDITION CASE 2 TBRG SDA le SCL m SCL goes low before SDA BCLIF Set BCLIF Release SDA
341. ltage High input RA4 TOCKI 6 6 RA4 O ST OD Digital Open drain when configured as output TOCKI ST TimerO external clock input RA5 AN4 SS LVDIN 7 7 5 O TTL Digital O AN4 Analog input 4 55 ST SPI Slave Select input LVDIN Low Voltage Detect Input See the OSC2 CLKO RA6 Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input Output Power OD Open Drain diode to VDD DS39564C page 10 2006 Microchip Technology Inc PIC18FXX2 TABLE 1 2 PIC18F2X2 PINOUT 1 0 DESCRIPTIONS CONTINUED Pin Number Pin Name re Su Art Butter Description DIP soic Type Type PORTB is bi directional I O port PORTB can be software for internal weak pull ups on all inputs RBO INTO 21 21 RBO O TTL Digital INTO ST External Interrupt 0 RB1 INT1 22 22 RB1 y o TTL INT1 ST External Interrupt 1 RB2 INT2 23 23 RB2 O TTL Digital INT2 ST External Interrupt 2 RB3 CCP2 24 24 RB3 O TTL Digital CCP2 O ST Capture2 input Compare2 output PWM2 output RB4 25 25 O TTL Digital Interrupt on change pin RB5 PGM 26 26 RB5 O TTL Digital I O Interrupt on change pin PGM O ST Low Voltage ICSP programming enable pin RB6 PGC 27 27 RB6 O TTL Digital I O Interrupt on change pin PGC O ST
342. n REG After Instruction REG 2006 Microchip Technology Inc DS39564C page 245 PIC18FXX2 SLEEP Enter SLEEP mode Syntax label SLEEP Operands None Operation 00h WDT 0 WDT postscaler 1 TO 0 PD Status Affected TO PD Encoding 0000 0000 0000 0011 Description The power down status bit PD is cleared The time out status bit TO is set Watchdog Timer and its postscaler are cleared The processor is put into SLEEP mode with the oscillator stopped Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No Process Go to operation Data sleep Example SLEEP Before Instruction IQ PD After Instruction IO 11 PD 0 T If WDT causes wake up this bit is cleared SUBFWB Subtract f from W with borrow Syntax label SUBFWB f d a Operands 0 lt 1 lt 255 d 0 1 a e 0 1 Operation W f C gt dest Status Affected DC Z Encoding 0101 olda Description Subtract register and carry flag borrow from 25 complement method If d is 0 the result is stored in W If d is 1 the result is stored in register default If a is 0 the Access Bank will be selected overriding the BSR value If a is 1 then the bank will be selected as per the BSR value default Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Proc
343. nd easily test firmware The user can also connect the PICDEM 1 demonstration board to the MPLAB ICE in circuit emulator and download the firmware to the emu lator for testing A prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket s Some of the features include an RS 232 interface a potentiometer for simu lated analog input push button switches and eight LEDs connected to PORTB 21 12 PICDEM 2 Low Cost PIC16CXX Demonstration Board The PICDEM 2 demonstration board is a simple dem onstration board that supports the 16 62 PIC16C64 PIC16C65 PIC16C73 and PIC16C74 microcontrollers All the necessary hardware and soft ware is included to run the basic demonstration pro grams The user can program the sample microcontrollers provided with the PICDEM 2 demon stration board on a PRO MATE II device programmer or a PICSTART Plus development programmer and easily test firmware The MPLAB ICE in circuit emula tor may also be used with the PICDEM 2 demonstration board to test firmware A prototype area has been pro vided to the user for adding additional hardware and connecting it to the microcontroller socket s Some of the features include a RS 232 interface push button switches a potentiometer for simulated analog input a serial EEPROM to demonstrate usage of the I C bus and separate headers for connection to an LCD module and a keypad 2006 Microch
344. ndard Speed mode 100 kHz and 1 MHz 0 rate control enabled for High Speed mode 400 kHz CKE SMBus Select bit In Master or Slave mode 1 Enable SMBus specific inputs Disable SMBus specific inputs D A Data Address bit In Master mode Reserved In Slave mode 1 Indicates that the last byte received or transmitted was data 0 Indicates that the last byte received or transmitted was address P STOP bit 1 Indicates that a STOP bit has been detected last 0 STOP bit was not detected last Note This bit is cleared on RESET and when SSPEN is cleared S START bit 1 Indicates that a start bit has been detected last 0 2 START bit was not detected last Note This bit is cleared on RESET and when SSPEN is cleared R W Read Write bit Information mode only In Slave mode 1 Read 0 Write Note This bit holds the R W bit information following the last address match This bit is only valid from the address match to the next START bit STOP bit or not ACK bit In Master mode 1 Transmit is in progress 0 Transmit is not in progress Note ORing this bit with SEN RSEN or ACKEN will indicate if the MSSP is in IDLE mode UA Update Address 10 bit Slave mode only 1 Indicates that the user needs to update the address in the SSPADD register 0 Address does not need to be updated BF Buffer Full Status bit In Transmit mode 1 Receive complete SSPBUF is full 0 Receive not complete S
345. neral use Table 19 4 shows which features are consumed by the background debugger TABLE 19 4 DEBUGGER RESOURCES To use the In Circuit Debugger function of the micro controller the design must implement In Circuit Serial Programming connections to MCLR VPP GND RB7 and RB6 This will interface to the In Circuit Debugger module available from Microchip or one of the third party development tool companies 19 8 Low Voltage ICSP Programming The LVP bit configuration register CONFIG4L enables low voltage ICSP programming This mode allows the microcontroller to be programmed via ICSP using a VDD source in the operating voltage range This only means that VPP does not have to be brought to VIHH but can instead be left at the normal operating voltage In this mode the RB5 PGM pin is dedicated to the pro gramming function and ceases to be a general purpose O pin During programming VDD is applied to the MCLR VPP pin To enter Programming mode VDD must be applied to the RB5 PGM provided the LVP bit is set The LVP bit defaults to a 1 from the factory If Low Voltage Programming mode is not used the LVP bit can be programmed to a 0 and RB5 PGM becomes a digital I O pin However the bit may only be pro grammed when programming is entered with VIHH on MCLR VPP It should be noted that once the LVP bit is programmed to 0 only the High Voltage Programming mode is avail able and only High Voltage Programm
346. nnot be cleared in soft ware It will reset only when new data is loaded into the TXREG register While flag bit TXIF indicates the status of the TXREG register another bit TRMT TXSTA lt 1 gt shows the status of the TSR register TRMT is a read only bit which is set when the TSR is empty No inter rupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty The TSR is not mapped in data memory so it is not available to the user To set up a Synchronous Master Transmission 1 Initialize the SPBRG register for the appropriate baud rate Section 16 1 Enable the synchronous master serial port by setting bits SYNC SPEN and CSRC If interrupts are desired set enable bit TXIE If 9 bit transmission is desired set bit TX9 Enable the transmission by setting bit TXEN If 9 bit transmission is selected the ninth bit should be loaded in bit TX9D 7 Starttransmission by loading data to the TXREG register m Note TXIF is not cleared immediately upon load ing data into the transmit buffer TXREG The flag bit becomes valid in the second rupt bit TXIF PIR1 lt 4 gt is set The interrupt can be instruction cycle following the load enabled disabled by setting clearing enable bit TXIE instruction TABLE 16 8 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Value on Value on Name Bit7 Bit
347. no carry Syntax label RRNCF Operands 0 lt 1 lt 255 d e 0 1 ae 0 1 Operation f lt n gt gt dest lt n 1 gt f lt 0 gt dest lt 7 gt Status Affected N Z Encoding 0100 ffff Description The contents of register f are rotated one bit to the right If d is O the result is placed in W If d is 1 the result is placed back in register default If a is 0 the Access Bank will be selected overriding the BSR value If a is 1 then the bank will be selected as per the BSR value default register f ial Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example 1 RRNCF REG 1 0 Before Instruction REG 1101 0111 After Instruction REG 1110 1011 Example 2 RRNCF REG 0 0 Before Instruction W 2 REG 1101 0111 After Instruction W 1110 1011 REG 1101 0111 SETF Set f Syntax abel f a Operands 0 lt lt 255 0 1 Operation 5f Status Affected None Encoding 0110 100a ffff Description The contents of the specified regis ter are set to FFh If a is 0 the Access Bank will be selected over riding the BSR value If a is 1 then the bank will be selected as per the BSR value default Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 04 Decode Read Process Write register Data register Example SETF REG 1 Before Instructio
348. nsmit Complete 165 Interr pts xen etri 73 LOGIC nn T 74 Interrupts Enable Bits CCP1 Enable CCPIIE Bit 119 E DS39564C page 320 2006 Microchip Technology PIC18FXX2 Packagihg eite nue 305 Details 307 Marking Information 2 88 00 305 Parallel Slave Port PORTD a dron Ne sin Parallel Slave Port PSP iA Associated Registers sss 101 REO RD ANG RE1 WR ANG Pin RE2 CS AN7 Pin eee Select PSPMODE Bit 95 100 PIC18F2X2 Pin Functions Men OSGTIGEKL No OSC2 CLKO RAG RA1 AN1 caer oen EQ eee ert cad RA2 AN2 VREF RAS ANS VREFE ee t Cra einen ia e RAA TOGCKI iia eet eaae vere NO NEON RAS5 AN4 SS LVDIN RBO INTO RB2 INT2 RB3 CCP2 884 suis RB6 PGC RB7 PGD RCO T10SO TICKI RC1 T1OSI CCP2 RC2 CCP1 RCS SCKISGCL rite rtr teet bene RGA SDI SDA 1 a RC5 SDO RGO TXIGK 15 heim eee es A RCZ RXIDT cite een Pee oe es PIC18F4X2 Pin Functions MGER MPP
349. nterrupt Flag bit 1 A low voltage condition occurred must be cleared in software 0 The device voltage is above the Low Voltage Detect trip point TMR3IF TMR3 Overflow Interrupt Flag bit 1 TMR3 register overflowed must be cleared in software 0 register did not overflow CCP2IF CCPx Interrupt Flag bit Capture mode 1 TMRI register capture occurred must be cleared in software 0 No TMRI register capture occurred Compare mode 1 TMRI register compare match occurred must be cleared in software 0 TMR1 register compare match occurred PWM mode Unused in this mode Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2006 Microchip Technology Inc DS39564C page 79 PIC18FXX2 8 3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts Due to the number of periph eral interrupt sources there are two Peripheral Inter rupt Enable Registers PIE1 PIE2 When IPEN 0 the PEIE bit must be set to enable any of these peripheral interrupts REGISTER 8 6 PIE1 PERIPHERAL INTERRUPT ENABLE REGISTER 1 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 0 R W 0 PSPIEU ADIE RCIE TXIE SSPIE CCP1IE TMR2IE bit 7 bit 7 5 Parallel Slave Port Read Write Interrupt Enable bit 1 Enables the P
350. ntrol register This ra register controls the Operating mode of the Timer3 16 bit timer counter module and sets the CCP clock source two 8 bit registers TMR3H and TMR3L Register 11 1 shows the Timer1 control register This Readable and writable both registers register controls the Operating mode of the Timer1 Internal or external clock select module as well as contains the oscillator Interrupt on overflow from FFFFh to 0000h enable bit T1OSCEN which can be a clock source for RESET from CCP module trigger Timer3 REGISTER 13 1 T3CON TIMER3 CONTROL REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 RD16 T3CCP2 T3CKPS1 T3CKPSO T3CCP1 TZSYNC TMR3ON bit 7 bit O bit 7 RD16 16 bit Read Write Mode Enable bit 1 Enables register Read Write of Timer3 in one 16 bit operation 0 Enables register Read Write of Timer3 in two 8 bit operations bit 6 3 2 Timer3 and Timer1 to CCPx Enable bits 1x Timer3 is the clock source for compare capture CCP modules 01 Timers is the clock source for compare capture of CCP2 Timer1 is the clock source for compare capture of CCP1 00 Timer1 is the clock source for compare capture CCP modules bit 5 4 T3CKPS1 T3CKPSO Timer3 Input Clock Prescale Select bits 11 1 8 Prescale value 10 1 4 Prescale value 01 1 2 Prescale value 00 1 1 Prescale value bit 2 T3SYNC Timer3
351. nts of SSPADD lt 6 0 gt and begins counting SDA and SCL must be sampled high for one TBRG This action is then followed by assertion of the SDA pin SDA 0 for one TBRG while SCL is high Following this the RSEN bit SSPCON2 1 will be automatically cleared and the baud rate generator will not be reloaded leaving the SDA pin held low As soon as a START condition is detected on the SDA and SCL pins the S bit SSPSTAT lt 3 gt will be set The SSPIF bit will not be set until the baud rate generator has timed out Immediately following the SSPIF bit getting set the user may write the SSPBUF with the 7 bit address in 7 bit mode or the default first address in 10 bit mode After the first eight bits are transmitted and an ACK is received the user may then transmit an additional eight bits of address 10 bit mode or eight bits of data 7 bit mode 15 4 9 1 WCOL Status Flag If the user writes the SSPBUF when a Repeated START sequence is in progress the WCOL is set and the contents of the buffer are unchanged the write doesn t occur Note Because queueing of events is not allowed writing of the lower 5 bits of SSPCON is disabled until the Repeated START condition is complete Note 1 If RSEN is programmed while any other event is in progress it will not take effect 2 A bus collision during the Repeated START condition occurs if SDA is sampled low when SCL goes from low to high SCL goes low
352. o external RESET circuitry SLEEP mode is designed to offer a very low current Power down mode The user can wake up from SLEEP through external RESET Watchdog Timer Wake up or through an interrupt Several oscillator options are also made available to allow the part to fit the application The RC oscillator option saves system cost while the LP crystal option saves power A set of configuration bits are used to select various options 19 1 Configuration Bits The configuration bits can be programmed read as 0 or left unprogrammed read as 1 to select various device configurations These bits are mapped starting at program memory location 300000h The user will note that address 300000h is beyond the user program memory space In fact it belongs to the configuration memory space 300000h 3FFFFFh which can only be accessed using Table Reads and Table Writes Programming the configuration registers is done in a manner similar to programming the FLASH memory see Section 5 5 1 The only difference is the configu ration registers are written a byte at a time The sequence of events for programming configuration registers is 1 Load table pointer with address of configuration register being written 2 Write a single byte using the TBLWT instruction 3 SetEEPGD to point to program memory set the CFGS bit to access configuration registers and set WREN to enable byte writes Disable interrupts Write 55h to EECON2
353. o point to program memory clear CFGS bit to access program memory set WREN bit to enable writes and set FREE bit to enable the erase Disable interrupts Write 55h to 2 Write AAh to EECON2 Set the WR bit This will begin the row erase cycle 7 The CPU will stall for duration of the erase about 2 ms using internal timer 8 Re enable interrupts o 01 B o EXAMPLE 5 2 ERASING A FLASH PROGRAM MEMORY ROW MOVLW CODE ADDR UPPER load TBLPTR with the base MOVWF TBLPTRU address of the memory block MOVLW CODE ADDR HIGH MOVWF TBLPTRH MOVLW CODE ADDR LOW MOVWF BLPTRL ERASE ROW BSF 1 EEPGD point to FLASH program memory BCF 1 CFGS access FLASH program memory BSF EECON1 WREN enable write to memory BSF EECON1 FREE enable Row Erase operation BCF INTCON GIE disable interrupts MOVLW 55h Required MOVWF EECON2 write 55h Sequence MOVLW AAh MOVWF EECON2 write AAh BSF EECON1 WR start erase CPU stall BSF INTCON GIE re enable interrupts DS39564C page 60 2006 Microchip Technology Inc PIC18FXX2 5 5 Writing to FLASH Program Memory The minimum programming block is 4 words or 8 bytes Word or byte programming is not supported Table Writes are used internally to load the holding reg isters needed to program the FLASH memory There are 8 holding registers used by the Table Writes for programming Since the Table Latch TABLAT is only
354. o the 1st clock edge of Byte2 1 5 40 ns Note 2 74 TscH2diL Hold time of SDI data input to SCK edge 100 ns TscL2diL 75 TdoR SDO data output rise time PIC18FXXX 25 ns PIC18LFXXX 60 ns VDD 2V 76 TdoF SDO data output fall time PIC18FXXX 25 ns PIC18LFXXX 60 ns VDD 2V 78 TscR SCK output rise time Master mode PIC18F XXX 25 ns PIC18LFXXX 60 ns VDD 2V 79 TscF SCK output fall time Master mode PIC18FXXX 25 ns PIC18LFXXX 60 ns VDD 2V 80 TscH2doV SDO data output valid after SCK PIC18FXXX 50 ns TscL2doV edge PIC18LFXXX 150 ns 2 81 TdoV2scH SDO data output setup to SCK edge Tcv ns TdoV2scL Note 1 Requires the use of Parameter 73A 2 Only if Parameter 71A and 72A are used 2006 Microchip Technology Inc DS39564C page 279 PIC18FXX2 FIGURE 22 14 EXAMPLE SPI SLAVE MODE TIMING 0 SDO 150 3 PEN 777 SDI LSb In Note Refer to Figure 22 4 for load conditions TABLE 22 13 EXAMPLE SPI MODE REQUIREMENTS SLAVE MODE TIMING 0 Param No Symbol Characteristic Min Max Units Conditions 70 TssL2scH SSL to SCK or SCKT input Tcv ns TssL2scL 71 TscH SCK input high time Slave mode Continuous 1 25 Tcv 30 ns 71A Single Byte 40 ns Note 1 72 TscL SCK input low time Slave mode Continuous 1 25
355. obal interrupt enable bit are set the interrupt will vector immediately to address 000008h or 000018h depending on the priority level Individual interrupts can be disabled through their corresponding enable bits When the IPEN bit is cleared default state the inter rupt priority feature is disabled and interrupts are com patible with PlCmicro mid range devices In Compatibility mode the interrupt priority bits for each source have no effect INTCON lt 6 gt is the PEIE bit which enables disables all peripheral interrupt sources lt 7 gt is the GIE bit which enables disables all interrupt sources All interrupts branch to address 000008h in Compatibility mode When an interrupt is responded to the Global Interrupt Enable bit is cleared to disable further interrupts If the IPEN bit is cleared this is the GIE bit If interrupt priority levels are used this will be either the GIEH or GIEL bit High priority interrupt sources can interrupt a low priority interrupt The return address is pushed onto the stack and the PC is loaded with the interrupt vector address 000008h or 000018h Once in the Interrupt Service Routine the source s of the interrupt can be deter mined by polling the interrupt flag bits The interrupt flag bits must be cleared in software before re enabling interrupts to avoid recursive interrupts The return from interrupt instruction RETFIE exits the interrupt routine and sets the GIE b
356. ode Protection bit 1 Block 3 006000 007FFFh not code protected Block 3 006000 007FFFh code protected bit 2 CP2 Code Protection bit 1 Block 2 004000 005FFFh not code protected Block 2 004000 005FFFh code protected bit 1 CP1 Code Protection bit 1 Block 1 002000 003FFFh not code protected 0 Block 1 002000 003FFFh code protected bit O CPO Code Protection bit 1 Block 0 000200 001FFFh not code protected 0 Block 0 000200 001FFFh code protected Note 1 Unimplemented in PIC18FX42 devices maintain this bit set Legend R Readable bit Clearable bit U Unimplemented bit read as V Value when device is unprogrammed u Unchanged from programmed state REGISTER 19 7 CONFIGURATION REGISTER 5 HIGH CONFIG5H BYTE ADDRESS 300009h R C 1 R C 1 U 0 U 0 U 0 U 0 U 0 U 0 CPD CPB m m bit 7 bit 0 bit 7 CPD Data EEPROM Code Protection bit 1 Data EEPROM not code protected 0 Data EEPROM code protected bit 6 CPB Boot Block Code Protection bit 1 Boot Block 000000 0001FFh not code protected 0 Boot Block 000000 0001FFh code protected bit5 O Unimplemented Read as 0 Legend R Readable bit C Clearable bit U Unimplemented bit read as V n Value when device is unprogrammed u Unchanged from programmed state 2006 Microchip Technology Inc DS39564C page 199 PIC18FXX2 REGISTER 19 8 CONFIGURATION
357. of the RETURN Or CALL instructions The stack operates as a 31 word by 21 bit RAM and a 5 bit stack pointer with the stack pointer initialized to 00000b after all RESETS There is no RAM associated with stack pointer 00000b This is only a RESET value During a CALL type instruction causing a push onto the stack the stack pointer is first incremented and the RAM location pointed to by the stack pointer is written with the contents of the PC During a RETURN type instruction causing a pop from the stack the contents of the RAM location pointed to by the STKPTR are transferred to the PC and then the stack pointer is decremented The stack space is not part of either program or data space The stack pointer is readable and writable and the address on the top of the stack is readable and writ able through SFR registers Data can also be pushed to or popped from the stack using the top of stack SFRs Status bits indicate if the stack pointer is at or beyond the 31 levels provided 4 2 1 TOP OF STACK ACCESS The top of the stack is readable and writable Three register locations TOSU TOSH and TOSL hold the contents of the stack location pointed to by the STKPTR register This allows users to implement a software stack if necessary After a CALL RCALL interrupt the software can read the pushed value by reading the TOSU TOSH and TOSL registers These values can be placed on a user defined software stack At return time the
358. ograms The WREN bit should be kept clear at all times except when updating the EEPROM The WREN bit is not cleared by hardware After a write sequence has been initiated 1 EEADR and EDATA cannot be modified The WR bit will be inhibited from being set unless the WREN bit is set The WREN bit must be set on a previous instruc tion Both WR and WREN cannot be set with the same instruction At the completion of the write cycle the WR bit is cleared in hardware and the EEPROM Write Complete Interrupt Flag bit EEIF is set The user may either enable this interrupt or poll this bit EEIF must be cleared by software EXAMPLE 6 2 DATA EEPROM WRITE MOVLW DATA EE ADDR n MOVWF EEADR Data Memory Address to read MOVLW DATA EE DATA 5 MOVWF EEDATA Data Memory Value to write BCF EECON1 EEPGD Point to DATA memory BCF EECON1 CFGS Access program FLASH or Data EEPROM memory BSF EECON1 WREN Enable writes INTCON GIE Disable interrupts Required MOVLW 55h Seguence MOVWF EECON2 Write 55h MOVLW AAh 8 MOVWF EECON2 Write AAh BSF EECON1 WR Set WR bit to begin write BSF INTCON GIE Enable interrupts user code execution BCF EECON1 WREN Disable writes on write complete EEIF set 2006 Microchip Technology Inc DS39564C page 67 PIC18FXX2 6 5 Write Verify Depending on the application good programming practice may dictate that the value written to the mem ory should
359. ompatible 10 bit Analog to Digital Converter A D Module 181 18 0 Low Voltage 189 19 0 Special Features of the 244 4 4 RH 195 20 0 Instruction Set Summary 21 0 TESTI ojoTo RR 22 0 Electrical Characteristics 23 0 DC and AC Characteristics Graphs and Tables 24 0 Packaging Information Appendix A Revision History Appendix B Device Appendix C Conversion ER Appendix D Migration from Baseline to Enhanced Devices Appendix E Migration from Mid range to Enhanced Devices Appendix F Migration from High end to Enhanced Devices EA ELEC Orm Line Supportin O de ane TE der ten te Reader Response PIC18FXX2 Product Identification 1 1 RH kn DS39564C page 4 2006 Microchip Technology Inc PIC18FXX2 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products To this end we will continue to improve our publications to better suit your needs Our publications will be refined and enhanced as new volumes and updates are introduced If you have any questions or comments regarding this publication please contact the Marketing Communicati
360. onal I O port PORTB can be software programmed for internal weak pull ups on all inputs RBO INTO 33 36 8 RBO TTL Digital I O INTO ST External Interrupt 0 RB1 INT1 34 37 9 RB1 O TTL INT 1 ST External Interrupt 1 RB2 INT2 35 38 10 RB2 TTL Digital I O INT2 ST External Interrupt 2 RB3 CCP2 36 39 11 RB3 TTL Digital I O CCP2 ST Capture2 input Compare2 output PWM2 output RB4 37 41 14 TTL Digital I O Interrupt on change pin RB5 PGM 38 42 15 RB5 TTL Digital I O Interrupt on change pin PGM ST Low Voltage ICSP programming enable pin RB6 PGC 39 43 16 RB6 y o TTL Digital I O Interrupt on change pin PGC ST In Circuit Debugger and ICSP programming clock pin RB7 PGD 40 44 17 RB7 TTL Digital I O Interrupt on change pin PGD O ST In Circuit Debugger and ICSP programming data pin Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input Output OD Open Drain diode to VDD ss DS39564C page 14 2006 Microchip Technology Inc PIC18FXX2 TABLE 1 3 PIC18F4X2 PINOUT 1 0 DESCRIPTIONS CONTINUED Pin Number i Pin Name Homola Description DIP PLCC ype PORTC is a bi directional I O port RCO T1OSO T1CKI 15 16 32 RCO ST Digital T10SO O 1 oscillator output T1CKI ST Timer1 Timer3 external clo
361. ons Department via E mail at docerrors microchip com or fax the Reader Response Form in the back of this data sheet to 480 792 4150 We welcome your feedback Most Current Data Sheet To obtain the most up to date version of this data sheet please register at our Worldwide Web site at http www microchip com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page The last character of the literature number is the version number e g DS30000A is version A of document DS30000 Errata An errata sheet describing minor operational differences from the data sheet and recommended workarounds may exist for current devices As device documentation issues become known to us we will publish an errata sheet The errata will specify the revision of silicon and revision of document to which it applies To determine if an errata sheet exists for a particular device please check with one of the following e Microchip s Worldwide Web site http www microchip com e Your local Microchip sales office see last page When contacting a sales office please specify which device revision of silicon and data sheet include literature number you are using Customer Notification System Register on our web site at www microchip com to receive the most current information on all of our products _ c GS 2006 Microchip Te
362. onstants 105 cali bration etc should be stored in FLASH program memory A simple data EEPROM refresh routine is shown in Example 6 3 Note If data EEPROM is only used to store con stants and or data that changes rarely an array refresh is likely not required See specification D124 EXAMPLE 6 3 DATA EEPROM REFRESH ROUTINE CLTE EEADR Start at address 0 bcf EECON1 CFGS Set for memory bcf 1 EEPGD Set for Data bcf INTCON GIE Disable interrupts bsf 1 WREN Enable writes Loop Loop to refresh array bsf EECON1 RD Read current address movlw 55h movwf EECON2 Write 55h movwf EECON2 Write AAh bsf EECON1 WR Set WR bit to begin write btfsc EECON1 WR Wait for write to complete bra 2 incfsz EEADR F Increment address bra Loop Not zero do it again bcf 1 Disable writes bsf INTCON GIE Enable interrupts DS39564C page 68 2006 Microchip Technology Inc PIC18FXX2 TABLE 6 1 REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Value Sri Value on Address Name Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit1 BIto Other POR BOR RESETS FF2h INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000 0000 000u GIEL FA9h EEADR EEPROM Address Register 0000 0000 0000 0000 FA8h EEDATA EEPROM Data Register 0000 0000
363. or the MPLINK object linker Intel standard HEX files MAP files to detail memory usage and symbol reference an abso lute LST file that contains source lines and generated machine code and file for debugging The MPASM assembler features include Integration into MPLAB IDE projects User defined macros to streamline assembly code Conditional assembly for multi purpose source files Directives that allow complete control over the assembly process 21 3 MPLAB C17 and MPLAB C18 Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI compilers for Microchip s PIC17CXXX and PIC18CXXX family of microcontrollers respectively These compilers provide powerful integration capabilities and ease of use not found with other compilers For easier source level debugging the compilers pro vide symbol information that is compatible with the MPLAB IDE memory display 2006 Microchip Technology Inc DS39564C page 253 PIC18FXX2 214 MPLINK Object Linker MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers It can also link relocatable objects from pre compiled libraries using directives from a linker script The MPLIB object librarian is a librarian for pre compiled code to be used with the MPLINK object linker When a routine from a library is called from ano
364. other Oscillator modes A portion of the Power up Timer is used to pro vide a fixed time out that is sufficient for the PLL to lock to the main oscillator frequency This PLL lock time out TPLL is typically 2 ms and follows the oscillator start up time out OST 3 5 Brown out Reset BOR A configuration bit BOREN can disable if clear programmed or enable if set the Brown out Reset circuitry If VDD falls below parameter 0005 for greater than parameter 35 the brown out situation will reset the A RESET may not occur if falls below parameter 0005 for less than parameter 35 The chip will remain in Brown out Reset until VDD rises above BVDD If the Power up Timer is enabled it will be invoked after VDD rises above BVDD it then will keep the chip in RESET for an additional time delay parameter 33 If drops below while the Power up Timer is running the chip will go back into Brown out Reset and the Power up Timer will be initial ized Once VDD rises above the Power up Timer will execute the additional time delay 3 6 Time out Sequence On power up the time out sequence is as follows First PWRT time out is invoked after POR time delay has expired Then OST is activated The total time out will vary based on oscillator configuration and the status of the PWRT For example in RC mode with the PWRT disabled there will be no time out at all Figure 3 3 Figure 3 4 Figure 3 5
365. other blocks Block 0 000200h 001FFFh protected from Table Reads executed in other blocks Note 1 Unimplemented in PIC18FX42 devices maintain this bit set Legend R Readable bit C Clearable bit U Unimplemented bit read as V n Value when device is unprogrammed u Unchanged from programmed state REGISTER 19 11 CONFIGURATION REGISTER 7HIGH CONFIG7H BYTE ADDRESS 30000Dh U 0 R C 1 U 0 U 0 U 0 U 0 U 0 U 0 EBTRB bit 7 bit 0 bit 7 Unimplemented Read as 0 bit 6 EBTRB Boot Block Table Read Protection bit 1 Boot Block 000000 0001FFh not protected from Table Reads executed in other blocks 0 Boot Block 000000 0001FFh protected from Table Reads executed in other blocks bit5 O Unimplemented Read as 0 Legend R Readable bit C Clearable bit U Unimplemented bit read as V Value when device is unprogrammed u Unchanged from programmed state EE __ 2006 Microchip Technology Inc DS39564C page 201 PIC18FXX2 REGISTER 19 12 DEVICE IDREGISTER 1FOR PIC18FXX2 DEVID1 BYTE ADDRESS 3FFFFEh R R R R R R R R DEV2 DEV1 DEVO REV4 REV3 REV2 REV1 REVO bit 7 bit 0 bit 7 5 DEV2 DEVO Device ID bits 000 PIC18F252 001 PIC18F452 100 PIC18F242 101 PIC18F442 bit 4 0 REV4 REVO Revision ID bits These bits are used to indicate the device revision Legend R Readable bit P Programmable bit U Unimplemented bit
366. p to 200 kHz It will continue to run during SLEEP It is primarily intended for a 32 kHz crystal Table 11 1 shows the capacitor selection for the Timer1 oscillator The user must provide a software time delay to ensure proper start up of the Timer1 oscillator TABLE 11 1 CAPACITOR SELECTION FOR THE ALTERNATE OSCILLATOR Osc Type Freq C1 C2 LP 32 kHz TBD Crystal to be Tested 32 768 kHz Epson 001832 768 20 PPM Note 1 Microchip suggests 33 pF as a starting point in validating the oscillator circuit 2 Higher capacitance increases the stability of the oscillator but also increases the start up time 3 Since each resonator crystal has its own characteristics the user should consult the resonator crystal manufacturer for appropriate values of external components 4 Capacitor values are for design guidance only 11 3 Interrupt The TMR1 Register pair TMR1H TMR1L increments from 0000h to FFFFh and rolls over to 0000h The TMR1 Interrupt if enabled is generated on overflow which is latched in interrupt flag bit TMR1IF PIR1 lt 0 gt This interrupt can be enabled disabled by setting clearing TMR1 interrupt enable bit TMR1IE PIE1 lt 0 gt 114 Resetting using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a special event trigger CCP1M3 CCP1MO 1011 this signal will reset Timer and start
367. page 220 2006 Microchip Technology Inc PIC18FXX2 BNN Branch if Not Negative Syntax label BNN n 128 lt n lt 127 Operation if negative bit is O PC 2 2n 5 PC Status Affected None Encoding 1110 0111 nnnn nnnn Description If the Negative bit is 0 then the program will branch The 2 s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a two cycle instruction Words 1 Cycles 1 2 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC n Data No No No No operation operation operation operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal Process No n Data operation Example HERE BNN Jump Before Instruction PC address HERE After Instruction BNC Branch if Not Carry Syntax label BNC n Operands 128 lt n lt 127 Operation if carry bit is 0 PC 2 2n PC Status Affected None Encoding 1110 0011 nnnn nnnn Description If the Carry bit is 0 then the program will branch 2 s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a two cycle instruction Words 1 Cycles 1 2 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read
368. peration 1 Setthe PWM period by writing to the PR2 register 2 Set the PWM duty cycle by writing to the CCPRIL register and CCP1CON lt 5 4 gt bits 3 Make the CCP1 pin an output by clearing the TRISC lt 2 gt bit 4 Setthe TMR2 prescale value and enable Timer2 by writing to T2CON 5 Configure the CCP1 module for PWM operation TABLE 14 4 EXAMPLE PWM FREOUENCIES AND RESOLUTIONS AT 40 MHz PWM Freguency 2 44 kHz 9 77 kHz 39 06 kHz 156 25 kHz 312 50 kHz 416 67 kHz Timer Prescaler 1 4 16 16 4 1 1 1 1 PR2 Value OxFF OxFF OxFF Ox3F Ox1F Ox17 Maximum Resolution bits 14 12 10 8 7 6 58 TABLE 14 5 REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value Value on Name Bit7 Bit 6 Bit5 Bit4 Bit 3 Bit2 Bit1 Bit 0 BOR All Other RESETS INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 000 0000 000u PIR1 0 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF 0000 0000 0000 0000 PIE 1 PSPIEU ADIE RCIE TXIE SSPIE CCPIIE TMR2IE TMRAIE 0000 0000 0000 0000 IPR1 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP 0000 0000 0000 0000 TRISC PORTC Data Direction Register 1111 1111 1111 1111 TMR2 Timer2 Module Register 0000 0000 0000 0000 PR2 Timer2 Module Period Register 1111 1111 1111 1111 T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPSO 2
369. plication software is expecting to receive valid data SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF Buffer full bit BF SSPSTAT lt 0 gt indicates when SSPBUF has been loaded with the received data transmission is complete When the SSPBUF is read the BF bit is cleared This data may be irrelevant if the SPI is only a transmitter Generally MSSP Interrupt is used to determine when the transmission reception has com pleted The SSPBUF must be read and or written If the interrupt method is not going to be used then software polling can be done to ensure that a write collision does not occur Example 15 1 shows the loading of the SSPBUF SSPSR for data transmission The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF reg ister Additionally the MSSP status register SSPSTAT indicates the various status conditions EXAMPLE 15 1 LOADING THE SSPBUF SSPSR REGISTER LOOP BTFSS SSPSTAT BF BRA LOOP No MOVF SSPBUF W MOVWF RXDATA Save in user RAM MOVWF SSPBUF New data to xmit Has data been received transmit complete WREG reg contents of SSPBUF if data is meaningful MOVF TXDATA W reg contents of TXDATA DS39564C page 128 2006 Microchip Technology Inc PIC18FXX2 15 3 3 ENABLING SPI To enable the serial port SSP Enable bit SSPEN SSPCON1 lt 5 gt must be set To reset or reconfig
370. powers down LVD circuit LVDL3 LVDLO Low Voltage Detection Limit bits 1111 External analog input is used input comes from the LVDIN pin 1110 4 5V 4 77V 1101 4 2 4 45V 1100 4 0V 4 24V 1011 3 8V 4 03V 1010 3 6V 3 82V 1001 3 5 3 71V 1000 3 3V 3 50V 0111 3 0V 3 18 0110 2 8 2 97V 0101 2 7V 2 86V 0100 2 5V 2 65V 0011 2 4V 2 54V 0010 2 2V 2 33 0001 2 0 2 12V 0000 Reserved Note LVDL3 LVDLO modes which result in a trip point below the valid operating voltage of the device are not tested Legend R Readable bit W Writable bit U Unimplemented bit read as Value at POR T Bit is set Bit is cleared X Bit is unknown 2006 Microchip Technology Inc DS39564C page 191 PIC18FXX2 18 2 Operation Depending on the power source for the device voltage the voltage normally decreases relatively slowly This means that the LVD module does not need to be con stantly operating To decrease the current reguire ments the LVD circuitry only needs to be enabled for short periods where the voltage is checked After DS39564C page 192 2006 Microchip Technology Inc PIC18FXX2 18 2 1 REFERENCE VOLTAGE SET POINT The Internal Reference Voltage of the LVD module may be used by other internal circuitry the Programmable Brown out Reset If these circuits are disabled lower current consumption the reference voltage
371. r Capture Mode Operation Compare Mode Operation Low Voltage Detect External Reference Source 190 Internal Reference Source 190 MSSP FO Mide iE EGER 134 MSSP SPI Mode 125 On Chip Reset Circuit 25 Parallel Slave Port PORTD and PORTE 100 PIG18E2X2 s teet taedet PIC18FAXO2 nee rct aee Yee PEE us HD eset PORTC Peripheral Output Override PORTD Mode PORTE Mode PWM Operation Simplified RA3 RAO and RAS Port Pins RA4 TOCKI Pin RAG Pin RB2 RBO Port Pins ABI mt RB7 RB4 Port Pins Table Read Operation Table Write Operation Table Writes to FLASH Program Memory 61 TimerO in 16 bit Mode Timero 8 bit Mode er teet ri hee enr ni Timer1 16 bit R W Mode 108 TIME ns 112 TIMEN 114 Timer3 16 bit R W Mode 114 USART Asynchronous Receive 174 Asynchronous Transmit 172 Watchdog Timer 204 p 222 BOR See Brown out Reset BOW ANR
372. r details PIC18FXXX PAR Enable Oscillator Tosc 4 4xPLL 5 TSCLK XNW Clock Source Clock Source option for other modules DS39564C page 20 2006 Microchip Technology Inc PIC18FXX2 2 6 1 SYSTEM CLOCK SWITCH BIT The system clock source switching is performed under Note software control The system clock switch bit SCS OSCCON lt 0 gt controls the clock switching When the SCS bit is 07 the system clock source comes from the main oscillator that is selected by the FOSC configura tion bits in Configuration Register1H When the SCS bit is set the system clock source will come from the Timer1 oscillator The SCS bit is cleared on all forms of RESET The Timer1 oscillator must be enabled and operating to switch the system clock source The Timer1 oscillator is enabled by setting the TIOSCEN bit in the Timer1 control register T1CON If the oscillator is not enabled then any write to the SCS bit will be ignored SCS bit forced cleared and the main oscillator will continue to be the system clock source REGISTER 2 1 OSCCON REGISTER U 0 U 0 U 0 U 0 U 0 U 0 U 0 R W 1 m SCS bit 7 bit o bit 7 1 Unimplemented Read as 0 bit O SCS System Clock Switch bit When OSCSEN configuration bit 0 and TIOSCEN bit is set 1 Switch to Timer1 oscillator
373. ral feature The SFRs are typically distributed among the peripherals whose functions they control The unused SFR locations will be unimplemented and read as 0 5 See Table 4 1 for addresses for the SFRs DS39564C page 42 2006 Microchip Technology Inc PIC18FXX2 FIGURE 4 6 DATA MEMORY MAP FOR PIC18F242 442 BSR lt 3 0 gt Data Memory Map 000h tees 00h Access 97Fh gt BankO 4 080h GPR FFh OFFh 00h 100h RUES Bank 1 GPR FFh 1FFh 0010 00h 200h gt 2 GPR FFh 2FFh 300h Access Bank A RAM cess ow 0011 fal x Access RAM high 80 FD La Unused SFR Read 00h TEE Bank 14 gadog When a 0 the BSR is ignored and the Access Bank is used The first 128 bytes are General Purpose RAM from Bank 0 The second 128 bytes are Special Function Registers EFFh from Bank 15 FOOh 1111 pah Unused F7Fh 15 F80h FFh RH FFFh When a 1 the BSR is used to specify the RAM location that the instruction uses 2006 Microchip Technology Inc DS39564C page 43 PIC18FXX2 FIGURE 4 7 DATA MEMORY MAP FOR PIC18F252 452 BSR lt 3 0 gt Data Memory Map zo 00h Access RAM esl gt Bank0 FFh OFFh 00h 100h 0001 L Banki GER 2001 0010 00h 2 GPR 3001 2 00h 0011 GPR FFh 3FFh 400h
374. rd PICDEM 3 Demonstration Board PICDEM 17 Demonstration Board KEELOQ Demonstration Board 211 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8 bit microcon troller market The MPLAB IDE is a Windows based application that contains An interface to debugging tools simulator programmer sold separately emulator sold separately in circuit debugger sold separately A full featured editor A project manager Customizable toolbar and key mapping A status bar On line help The MPLAB IDE allows you to Edit your source files either assembly or C One touch assemble or compile and download to PICmicro emulator and simulator tools auto matically updates all project information Debug using source files absolute listing file machine code The ability to use MPLAB IDE with multiple debugging tools allows users to easily switch from the cost effective simulator to a full featured emulator with minimal retraining 21 2 Assembler The MPASM assembler is a full featured universal macro assembler for all PICmicro MCU s The MPASM assembler has a command line interface and Windows shell can be used as a stand alone application on Windows 3 x or greater system or it can be used through MPLAB IDE The MPASM assem bler generates relocatable object files f
375. read as V n Value when device is unprogrammed u Unchanged from programmed state REGISTER 19 13 DEVICE ID REGISTER 2FOR PIC18FXX2 DEVID2 BYTE ADDRESS 3FFFFFh R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 bit 7 0 DEV10 DEV3 Device ID bits These bits are used with the DEV2 DEVO bits in the Device ID Register 1 to identify the part number Legend R Readable bit P Programmable bit U Unimplemented bit read as V Value when device is unprogrammed u Unchanged from programmed state SEE SS TV DS39564C page 202 2006 Microchip Technology Inc PIC18FXX2 19 2 Watchdog Timer WDT The Watchdog Timeris a free running on chip RC oscil lator which does not require any external components This RC oscillator is separate from the RC oscillator of the OSC1 CLKI pin That means that the WDT will run even if the clock on the OSCI CLKI and OSC2 CLKO RA6 pins of the device has been stopped for example by execution of a SLEEP instruction During normal operation a WDT time out generates a device RESET Watchdog Timer Reset If the device is in SLEEP mode a WDT time out causes the device to wake up and continue with normal operation Watch dog Timer Wake up The TO bit in the RCON register will be cleared upon a WDT time out The Watchdog Timer is enabled disabled by a device configuration bit If the WDT is enabled software exe
376. red in software 0 No TMRI register capture occurred Compare mode 1 A TMRI register compare match occurred must be cleared in software 0 No TMRI register compare match occurred PWM mode Unused in this mode bit 1 TMR2IF 2 to PR2 Match Interrupt Flag bit 1 2 to PR2 match occurred must be cleared in software 0 TMR2 to PR2 match occurred bit O TMRIIF TMR1 Overflow Interrupt Flag bit 1 register overflowed must be cleared in software 0 register did not overflow Note 1 This bit is reserved on PIC18F2X2 devices always maintain this bit clear Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 1 Bit is set Bit is cleared x Bit is unknown DS39564C page 78 2006 Microchip Technology Inc PIC18FXX2 REGISTER 8 5 bit 7 5 bit 4 bit 3 bit 2 bit 1 bit 0 PIR2 PERIPHERAL INTERRUPT REOUEST FLAG REGISTER 2 U 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 EEIF BCLIF LVDIF bit 7 bit 0 Unimplemented Read as 0 EEIF Data EEPROM FLASH Write Operation Interrupt Flag bit 1 The Write operation is complete must be cleared in software 0 The Write operation is not complete or has not been started BCLIF Bus Collision Interrupt Flag bit 1 A bus collision occurred must be cleared in software 0 No bus collision occurred LVDIF Low Voltage Detect I
377. register 25 complement method If is 0 the result is stored W If d is 1 the result is stored back in register f default If a is 0 the Access Bank will be selected overriding the BSR value If a is 1 then the bank will be selected as per the BSR value default Words 1 Cycles 1 Q Cycle Activity Q1 Q2 04 Read Process Write to register Data destination Example 1 SUBWFB 1 0 Before Instruction REG 0x19 0001 1001 W 0 00 0000 1101 C 1 After Instruction REG Ox0C 0000 1011 W 0 00 0000 1101 C 1 2 0 0 result is positive Example 2 SUBWFB REG 0 0 Before Instruction REG Ox1B 0001 1011 W 0 1 0001 1010 C 0 After Instruction REG Ox1B 0001 1011 W 0x00 C 1 2 1 result is zero 0 Example 3 SUBWEB REG 1 0 Before Instruction REG 0x03 0000 0011 W OxOE 0000 1101 C 1 After Instruction REG OxF5 1111 0100 2 s comp W OxOE 0000 1101 C 0 2 0 N 1 result is negative SWAPF Swap f Syntax label SWAPF f d a 0 lt 1 lt 255 d e 0 1 a e 0 1 Operation f lt 3 0 gt gt dest lt 7 4 gt f lt 7 4 gt 3 dest lt 3 0 gt Status Affected None Encoding 0011 10da ffff Description The upper and lower nibbles of reg ister exchanged If d is 0 the result is placed in W If d is 1 the result is
378. res Compatible 10 bit Analog to Digital Converter module A D with Fast sampling rate Conversion available during SLEEP Linearity lt 1 LSb Programmable Low Voltage Detection PLVD Supports interrupt on Low Voltage Detection Programmable Brown out Reset BOR Special Microcontroller Features 100 000 erase write cycle Enhanced FLASH program memory typical 1 000 000 erase write cycle Data EEPROM memory FLASH Data EEPROM Retention 40 years Self reprogrammable under software control Power on Reset POR Power up Timer PWRT and Oscillator Start up Timer OST Watchdog Timer WDT with its own On Chip RC Oscillator for reliable operation Programmable code protection Power saving SLEEP mode Selectable oscillator options including 4X Phase Lock Loop of primary oscillator Secondary Oscillator 32 KHz clock input Single supply 5V In Circuit Serial Programming ICSPTM via two pins In Circuit Debug ICD via two pins CMOS Technology Low power high speed FLASH EEPROM technology Fully static design Wide operating voltage range 2 0V to 5 5V Industrial and Extended temperature ranges Low power cons14 333 p TJ3ri2asircy oV 2006 Microchip Technology Inc DS39564C page 1 PIC18FXX2 Pin Diagrams PLCC RA3 AN3 VREF lt RB4 NC 5 RA2 AN2 VREF 6 4 1 RA1 AN1 3 14 RAO ANO 2 4 MCLR VPP 1 NC 44 RB7 P
379. res RX DT and TX CK pins as serial port pins 0 Serial port disabled RX9 9 bit Receive Enable bit 1 Selects 9 bit reception 0 Selects 8 bit reception SREN Single Receive Enable bit Asynchronous mode Dont care Synchronous mode Master 1 Enables single receive Disables single receive This bit is cleared after reception is complete Synchronous mode Slave Dont care CREN Continuous Receive Enable bit Asynchronous mode 1 Enables receiver Disables receiver Synchronous mode 1 Enables continuous receive until enable bit CREN is cleared CREN overrides SREN Disables continuous receive ADDEN Address Detect Enable bit Asynchronous mode 9 bit RX9 1 1 Enables address detection enable interrupt and load of the receive buffer when RSR 8 is set 0 Disables address detection all bytes are received and ninth bit can be used as parity bit FERR Framing Error bit 1 Framing error can be updated by reading RCREG register and receive next valid byte 0 No framing error OERR Overrun Error bit 1 Overrun error can be cleared by clearing bit CREN 0 No overrun error RX9D 9th bit of Received Data This can be Address Data bit or a parity bit and must be calculated by user firmware Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 7 Bit is set Bit is cleared x Bit is unknown 2006 Microchip Technology Inc DS
380. rs with auto increment TBLWT or TBLWT 7 Set EEPGD bit to point to program memory clear the CFGS bit to access program memory and set WREN to enable byte writes 8 Disable interrupts 9 Write 55h to EECON2 Or mom 10 Write AAh to EECON2 11 Set the WR bit This will begin the write cycle 12 The CPU will stall for duration of the write about 2 ms using internal timer 13 Re enable interrupts 14 Repeat steps 6 14 seven times to write 64 bytes 15 Verify the memory Table Read This procedure will require about 18 ms to update one row of 64 bytes of memory An example of the required code is given in Example 5 3 Note Before setting the WR bit the table pointer address needs to be within the intended address range of the 8 bytes in the holding registers 2006 Microchip Technology Inc DS39564C page 61 PIC18FXX2 EXAMPLE 5 3 WRITING TO FLASH PROGRAM MEMORY MOVLW D 64 number of bytes in erase block MOVWF COUNTER MOVLW BUFFER ADDR HIGH point to buffer MOVWF FSROH MOVLW BUFFER ADDR LOW MOVWF FSROL MOVLW CODE ADDR UPPER Load TBLPTR with the base MOVWF BLPTRU address of the memory block MOVLW CODE ADDR HIGH MOVLW CODE ADDR LOW READ BLOCK TBLRD read into TABLAT and inc MOVF TABLAT W get data POSTINCO store data DECFSZ COUNTER done BRA READ BLOCK repeat MODIFY WORD MOVLW ADD
381. s TABLE 22 15 BUS START STOP BITS REQUIREMENTS SLAVE MODE rane Symbol Characteristic Min Max Units Conditions 90 TSU STA START condition 100 kHz mode 4700 ns Only relevant for Repeated Setup time 400 kHz mode 600 START condition 91 THD STA START condition 100 kHz mode 4000 ns After this period the first Hold time 400 kHz mode 600 clock pulse is generated 92 Tsu sTO STOP condition 100 kHz mode 4700 ns Setup time 400 kHz mode 600 93 THD STO STOP condition 100 kHz mode 4000 ns Hold time 400 kHz mode 600 FIGURE 22 17 PC BUS DATA TIMING 103 2 a 100 SCL SDA Out Note Refer to Figure 22 4 for load conditions DS39564C page 282 2006 Microchip Technology Inc PIC18FXX2 TABLE 22 16 2 BUS DATA REQUIREMENTS SLAVE MODE Symbol Characteristic Min Max Units Conditions 100 THIGH Clock high time 100 kHz mode 4 0 us must operate at a minimum of 1 5 MHz 400 kHz mode 0 6 us PIC18FXXX must operate at a minimum of 10 MHz SSP Module 1 5 Tcv 101 TLOW Clock low time 100 kHz mode 4 7 us PIC18FXXX must operate at a minimum of 1 5 MHz 400 kHz mode 1 3 us PIC18FXXX must operate at a minimum of 10 MHz SSP Module 1 5 Tcy
382. s Note 1 When reading the port register all pins con figured as analog input channels will read as cleared a low level Pins configured as digital inputs will convert an analog input Analog levels on a digitally configured input will not affect the conversion accuracy 2 Analog levels on any pin that is defined as a digital input including the AN4 ANO pins may cause the input buffer to con sume current that is out of the device s specification TABLE 17 1 vs DEVICE OPERATING FREQUENCIES AD Clock Source TAD Maximum Device Freguency Operation ADCS2 ADCSO PIC18FXX2 PIC18LFXX2 2 Tosc 000 1 25 MHz 666 kHz 4 Tosc 100 2 50 MHz 1 33 MHz 8 TOSC 001 5 00 MHz 2 67 MHz 16 Tosc 101 10 00 MHz 5 33 MHz 32 TOSC 010 20 00 MHz 10 67 MHz 64 Tosc 110 40 00 MHz 21 33 MHz RC 011 DS39564C page 186 2006 Microchip Technology Inc PIC18FXX2 17 4 A D Conversions Figure 17 3 shows the operation of the A D converter after the GO bit has been set Clearing the GO DONE bit during a conversion will abort the current conver sion The A D result register pair will NOT be updated with the partially completed A D conversion sample That is the ADRESH ADRESL registers will continue to contain the value of the last completed conversion FIGURE 17 3 A D CONVERSION Tap CYCLES or the last value written to the ADRESH ADRESL reg isters After the A D conversion is aborted
383. s GO DONE bit ADCONO 2 is cleared and A D interrupt flag bit ADIF is set The block diagram of the A D module is shown in Figure 17 1 FIGURE 17 1 A D BLOCK DIAGRAM CHS lt 2 0 gt 111 12 0 Dx 110 DX Ane 101 pres Dx AN5 100 VAIN 4 Input Voltage ui 011 010 10 bit AN2 Converter 4 Pts PCFG lt 3 0 gt 000 4X ees VREF LES Reference Voltage 2006 Microchip Technology Inc DS39564C page 183 PIC18FXX2 The value that is in the ADRESH ADRESL registers is not modified for a Power on Reset The ADRESH ADRESL registers will contain unknown data after a Power on Reset After the A D module has been configured as desired the selected channel must be acquired before the con version is started The analog input channels must have their corresponding TRIS bits selected as input To determine acguisition time see Section 17 1 After this acguisition time has elapsed the A D conver sion can be started The following steps should be followed for doing an A D conversion 1 Configure the A D module Configure analog pins voltage reference and digital ADCON1 Select A D input channel ADCONO Select A D conversion clock ADCONO on A D module ADCONO 2 Configure A D interrupt if desired Clear ADIF bit
384. s Bank will be selected over the BSR value If a 1 then the riding the BSR value If a 1 then bank will be selected as per the the bank will be selected as per the BSR value default BSR value default Words 1 Words 1 Cycles 1 2 Cycles 1 2 Note 3 cycles if skip and followed by a 2 word instruction Note 3 cycles if skip and followed by a 2 word instruction Q Cycle Activity Q Cycle Activity Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register f Data destination register f Data destination If skip If skip Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2 word instruction If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example HERE INCFSZ CNT 1 0 Example HERE NFSNZ REG 1 0 NZERO ZERO ZERO NZERO Before Instruction Before Instruction PC Address HERE PC Address HERE After Instruction After Instruction CNT CNT 1 REG REG 1 IICNT 0 0 Address ZERO PC Address NZERO IICNT 0 0 Address Address ZERO DS3
385. s Stack TILL 11110 11101 STKPTR lt 4 0 gt a 00010 000118 0x001A34 00010 0 000058 00001 00000 4 2 3 PUSH AND POP INSTRUCTIONS Since the Top of Stack TOS is readable and writable the ability to push values onto the stack and pull values off the stack without disturbing normal program execu tion is a desirable option To push the current PC value onto the stack a PUSH instruction can be executed This will increment the stack pointer and load the cur rent PC value onto the stack TOSU TOSH and TOSL can then be modified to place a return address on the stack The ability to pull the TOS value off of the stack and replace it with the value that was previously pushed onto the stack without disturbing normal execution is achieved by using the POP instruction The POP instruc tion discards the current TOS by decrementing the stack pointer The previous value pushed onto the stack then becomes the TOS value 4 2 4 STACK FULL UNDERFLOW RESETS These resets are enabled by programming the STVREN configuration bit When the STVREN bit is disabled a full or underflow condition will set the appro priate STKFUL STKUNF bit but not cause a device RESET When the STVREN bit is enabled a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device RESET The STKFUL or STKUNF bits are only cleared by the user software or a POR Reset DS39564C page 38 200
386. sequence is in progress then WCOL is set and the con occur tents of the buffer are unchanged the write doesn t occur FIGURE 15 23 ACKNOWLEDGE SEOUENCE WAVEFORM Acknowledge seguence starts here Write to SSPCON2 1 0 automatically cleared T TBRG SDA DO SCL 8 i SSPIF Cleared in Set SSPIF at the end Cleared in software of receive software Set SSPIF at the end of Acknowledge seguence Note TBRG one baud rate generator period FIGURE 15 24 STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2 SCL 1 for TBRG followed by SDA 1 for TBRG Set PEN after SDA sampled high P bit SSPSTAT lt 4 gt is set Falling edge of PEN bit SSPCON2 lt 2 gt is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL E SDA ACK 4 ey Tara gt Tara Tera gt SCL brought high after TBRG SDA asserted low before rising edge of clock to setup STOP condition Note TBRG one baud rate generator period DS39564C page 158 2006 Microchip Technology Inc PIC18FXX2 15 4 14 SLEEP OPERATION While in SLEEP mode the I C module can receive addresses or data and when an address match or complete byte transfer occurs wake the processor from SLEEP if the MSSP interrupt is enabled 15 4 15 EFFECT
387. software can replace the TOSU TOSH and TOSL and do a return The user must disable the global interrupt enable bits during this time to prevent inadvertent stack operations 4 2 2 RETURN STACK POINTER STKPTR The STKPTR register contains the stack pointer value the STKFUL stack full status bit and the STKUNF stack underflow status bits Register 4 1 shows the STKPTR register The value of the stack pointer can be 0 through 31 The stack pointer increments when val ues are pushed onto the stack and decrements when values are popped off the stack At RESET the stack pointer value will be 0 The user may read and write the stack pointer value This feature can be used by a Real Time Operating System for return stack maintenance After the PC is pushed onto the stack 31 times without popping any values off the stack the STKFUL bit is set The STKFUL bit can only be cleared in software or by a POR The action that takes place when the stack becomes full depends on the state of the STVREN Stack Over flow Reset Enable configuration bit Refer to Section 20 0 for a description of the device configura tion bits If STVREN is set default the 31st push will push the PC 2 value onto the stack set the STKFUL bit and reset the device The STKFUL bit will remain set and the stack pointer will be set to 0 If STVREN is cleared the STKFUL bit will be set on the 31st push and the stack pointer will increment to 31 Any addit
388. ss If a Table Write is being used to write executable code into program memory program instructions will need to be word aligned Table Pointer Instruction TBLRD Program Memory TBLPTRU TBLPTRH Program Memory TBLPTR Table Latch 8 bit TABLAT Note 1 Table Pointer points to a byte in program memory 2006 Microchip Technology Inc DS39564C page 55 PIC18FXX2 FIGURE 5 2 TABLE WRITE OPERATION Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory TBLPTR Instruction TBLWT Program Memory Holding Registers Table Latch 8 bit TABLAT Section 5 5 Note 1 Table Pointer actually points to one of eight holding registers the address of which is determined by TBLPTRL lt 2 0 gt The process for physically writing data to the Program Memory Array is discussed in 5 2 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions These include the EECONI register 2 register TABLAT register TBLPTR registers 5 2 1 1 AND 2 REGISTERS EECONI is the control register for memory accesses EECON is not a physical register Reading EECON2 will read all 05 EECON2 register is used exclusively in the memory write and erase seguences Control bit EEPGD determin
389. ssor port These pins have TTL input buffers when PSP module is enabled RDO PSPO 19 21 38 y o ST Digital I O TTL Parallel Slave Port Data RD1 PSP1 20 22 39 O ST Digital I O TTL Parallel Slave Port Data RD2 PSP2 21 23 40 O ST Digital I O TTL Parallel Slave Port Data RD3 PSP3 22 24 41 O ST Digital I O TTL Parallel Slave Port Data RD4 PSP4 27 30 2 O ST Digital I O TTL Parallel Slave Port Data RD5 PSP5 28 31 3 y o ST Digital I O TTL Parallel Slave Port Data RD6 PSP6 29 32 4 O ST Digital I O TTL Parallel Slave Port Data RD7 PSP7 30 33 5 O ST Digital I O TTL Parallel Slave Port Data PORTE is a bi directional port REO RD AN5 8 9 25 VO REO ST Digital I O RD TTL Read control for parallel slave port see also WR and CS pins 5 Analog input 5 RE1 WR AN6 9 10 26 110 RE1 ST Digital I O WR TTL Write control for parallel slave port see CS and RD pins AN6 Analog Analog input 6 RE2 CS AN7 10 11 27 VO RE2 ST Digital I O CS TTL Chip Select control for parallel slave port see related RD and WR 7 Analog input 7 Vss 12 31113 34 6 29 Ground reference for logic and I O pins VDD 11 32 12 35 7 28 Positive supply for logic and I O pins Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input Output OD Open Drain diode to VDD DS39564C page 16 2006
390. st increment post decrement pre increment Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation Read Program operation Write TABLAT Memory TBLRD Table Read cont d Example TBLRD Before Instruction TABLAT 0x55 TBLPTR 0x00A 356 MEMORY 0x00A356 0 34 After Instruction TABLAT 0x34 TBLPTR 0 00 57 Example2 TBLRD Before Instruction TABLAT TBLPTR 0x01A 357 MEMORY 0x01A357 0x12 MEMORY 0x01A358 0 34 After Instruction TABLAT 0 34 TBLPTR 0x01A 358 2006 Microchip Technology Inc DS39564C page 249 PIC18FXX2 TBLWT Syntax Operands Operation Table Write label TBLWT None if TBLWT TABLAT gt Holding Register TBLPTR No Change if TBLWT TABLAT gt Holding Register TBLPTR 1 TBLPTR if TBLWT TABLAT Holding Register TBLPTR 1 gt TBLPTR if TBLWT TBLPTR 1 TBLPTR TABLAT Holding Register Status Affected None Encoding Description Words Cycles 0000 0000 0000 linn This instruction uses the 3 LSbs of the TBLPTR to determine which of the 8 holding registers the TABLAT data is written to The 8 holding registers are used to program the contents of Pro gram Memory P M See Section 5 0 for information on writing to FLASH memory T
391. statistical mean 25 C mean 36 40 C to 125 C mean 40 C to 125 C 20 Fosc MHz 28 32 36 40 FIGURE 23 10 MAXIMUM vs Fosc OVER EC MODE 16 14 12 10 IDD mA Typical Maximum Minimum statistical mean 25 C mean 36 40 C to 125 C mean 36 40 C to 125 C 20 24 Fosc MHz 28 32 36 40 2006 Microchip Technology Inc DS39564C page 293 PIC18FXX2 FIGURE 23 11 TYPICAL AND MAXIMUM vs TIMER1 AS MAIN OSCILLATOR 32 768 kHz AND C2 47 pF Typical statistical mean 25 C Maximum mean 30 10 C to 70 C Minimum mean 30 10 C to 70 C IDD LA Max 70 C vob V FIGURE 23 12 AVERAGE Fosc vs FOR VARIOUS VALUES OF RC MODE 20 pF 25 C 4 500 Operation above 4 MHz is not recommended 22 un EIL ene 4 000 3 3kQ 3 500 3 000 500 DS39564C page 294 2006 Microchip Technology Inc PIC18FXX2 FIGURE 23 13 AVERAGE Fosc vs FOR VARIOUS VALUES OF RC MODE 100 pF 25 C 2 000 1 800 1 600 3 3kQ 1 400 1 200 5 1kQ 1 000 Freq kHz 600 10kQ 100kQ
392. struction Sot ADDLW CPFSEQ CPFSGT 229 CRES T nn ne eei eee 229 DAW tn tte Ea 230 DEGEF r Saba 230 DECPSZ xime nn nr nt men en eni 231 GOTO wie la Rs M 232 INCE cette ere be eq erbe reete 232 ond eet EA 242 DS39564C page 319 PIC18FXX2 D pm 249 pz 250 TSTESZ iiiter a Pur eei 251 XORLW 251 XORWF 252 Summary Table 214 Instructions in Program Memory 40 Two Word Instructions 41 INT Interrupt RBO INT See Interrupt Sources INTCON Register RBIF Bit 90 INTCON Registers 2 00 20000011 75 77 Inter Integrated Circuit See 2 Interrupt Sources sise A D Conversion Complete Capture Complete CCP Compare Complete INTO cierre ee I Interrupt on Change RB7 RB4 PORTB Interrupt on Change RBO INT Pin External TMRO TMRO Overflow TMR1 Overflow TMR2 to PR2 224404221 TMR2 to PR2 Match PWM 111 122 TMRS Overflow 113 115 USART Receive Tra
393. t making it an excellent multi project software development tool 21 66 MPLAB ICE High Performance Universal In Circuit Emulator with MPLAB IDE The MPLAB ICE universal in circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set PICmicro microcontrollers MCUs Software control of the MPLAB ICE in circuit emulator is provided by the MPLAB Integrated Development Environment IDE which allows editing building downloading and source debugging from a single environment The MPLAB ICE 2000 is full featured emulator sys tem with enhanced trace trigger and data monitoring features Interchangeable processor modules allow the system to be easily reconfigured for emulation of differ ent processors The universal architecture of the MPLAB ICE in circuit emulator allows expansion to support new PICmicro microcontrollers The MPLAB ICE in circuit emulator system has been designed as a real time emulation system with advanced features that are generally found on more expensive development tools The PC platform and Microsoft Windows environment were chosen to best make these features available to you the end user 21 7 In Circuit Emulator The ICEPIC low cost in circuit emulator is a solution for the Microchip Technology PIC16C5X PIC16C6X PIC16C7X and PIC16CXXX families of 8 bit One Time Programmable OTP microcontrollers The mod ular system c
394. t is reguired only if the VDD power up slope is too slow The diode D helps discharge the capacitor guickly when VDD powers down 2 R lt 40 ko is recommended to make sure that the voltage drop across R does not violate the device s electrical specification 3 1 1000 to 1 will limit any current flow ing into MCLR from external capacitor C in the event of MCLR VPP pin breakdown due to Electrostatic Discharge ESD or Electrical Overstress EOS 3 2 Power up Timer PWRT The Power up Timer provides a fixed nominal time out parameter 33 only on power up from the POR The Power up Timer operates on an internal RC oscillator The chip is kept in RESET as long as the PWRT is active The PWRT s time delay allows VDD to rise to an acceptable level A configuration bit is provided to enable disable the PWRT The power up time delay will vary from chip to chip due to VDD temperature and process variation See DC parameter 0033 for details 3 3 Oscillator Start up Timer OST The Oscillator Start up Timer OST provides a 1024 oscillator cycle from OSC1 input delay after the PWRT delay is over parameter 32 This ensures that the crystal oscillator or resonator has started and stabilized The OST time out is invoked only for XT LP and HS modes and only on Power on Reset or wake up from SLEEP 3 4 PLL Lock Time out With the PLL enabled the time out sequence following a Power on Reset is different from
395. t neither overflow nor carry is possible in this opera tion A zero result is possible but not detected If a is 0 the Access Bank will be selected overriding the BSR value If a 1 then the bank will be selected as per the BSR value default Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write register f Data registers PRODH PRODL Example MULWF REG 1 Before Instruction W 0 4 REG 0 5 PRODH 2 PRODL 7 After Instruction W 0 4 REG OxB5 PRODH Ox8A PRODL 0x94 DS39564C page 238 2006 Microchip Technology Inc PIC18FXX2 NEGF Negate f Syntax label 0 lt 1 lt 255 a e 0 1 Operation f 1 gt f Status Affected N OV C DC Z Encoding 0110 110a ffff Description Location 15 negated using two s complement The result is placed in the data memory location If a is 0 the Access Bank will be selected overriding the BSR value If a 1 then the bank will be selected as per the BSR value Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write register f Data register f Example NEGF REG 1 Before Instruction REG 0011 1010 0x3A After Instruction REG 1100 0110 0xC6 NOP No Operation Syntax label NOP Operands None Operation No operation Status Affected None Encoding 0000 0000 0000 0000 1111 XXXX XXXX XX
396. t wide bi directional port The corre Data sponding Data Direction register is TRISA Setting a Bus A TRISA bit 2 1 will make the corresponding PORTA pin 2 an input i e put the corresponding output driver in a WR LATA 5 Hi Impedance mode Clearing TRISA bit 0 will or Ip make the corresponding PORTA pin an output i e put PORTA Data Latch the contents of the output latch on the selected pin LT 2 N 15 80 Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch WR TRISA e Data Latch register is also memory Analog mapped Read modify write operations on the LATA TRIS tateh apui register reads and writes the latched output value for i PORTA The RA4 pin is multiplexed with the TimerO module DOM clock input to become the RA4 TOCKI pin The RA4 Q D TOCKI pin is a Schmitt Trigger input and an open drain output All other RA port pins have TTL input levels and full CMOS output drivers EN The other PORTA pins are multiplexed with analog RD PORTA inputs and the analog VREF and VREF inputs The os operation of each pin is selected by clearing setting the SS Input RAS only control bits in the ADCONI register A D Control Register1 To A D Converter and LVD Modules Note On a Power on Reset 5 and are configured as analog inputs and read Note 1 pins have protection diodes to and Vss
397. tability Jitter 2 2 T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested FIGURE 22 6 CLKO AND 1 0 TIMING OSC1 CLKO Ass els 19 418 NET Pin 2 T input 25 2 14 17 15 gt output Old Value 1 New Value Note Refer to Figure 22 4 for load conditions 0539564 272 2006 Microchip Technology PIC18FXX2 TABLE 22 6 AND I O TIMING REQUIREMENTS Symbol Characteristic Min Units Conditions 10 TosH2ckL OSC1T to CLKOL 75 200 ns Note 1 11 TosH2ckH OSC1T to CLKOT 75 200 ns Note 1 12 TckR CLKO rise time 35 100 ns Note 1 13 TckF CLKO fall time 35 100 ns Note 1 14 CLKOL to Port out valid 10 5 Tcy 20 ns Note 1 15 TioV2ckH Port in valid before CLKO 0 25 25 ns Note 1 16 TckH2iol Port in hold after 0 ns Note 1 17 TosH2ioV 05 17 Q1 cycle to Port out valid 50 150 ns 18 TosH2iol 05 17 02 cycle to Port PIC18FXXX 100 ns 18A input invalid in hold time PIC18LFXXX 200 22 E ns 19 TioV20sH Port input valid to OSC1T I O in setup time 0 ns 20 TioR Port output rise time PIC18FXXX 10 25 ns 20A PIC18LFXXX
398. tage to the module from an external source This mode is enabled when bits LVDL3 LVDLO are set to 1111 In this state the com parator input is multiplexed from the external input pin LVDIN Figure 18 3 This gives users flexibility because it allows them to configure the Low Voltage Detect interrupt to occur at any voltage in the valid operating range FIGURE 18 3 LOW VOLTAGE DETECT LVD WITH EXTERNAL INPUT BLOCK DIAGRAM VDD z n 4 LVDIN Externally Generated Trip Point VDD 16 to 1 MUX LVD Control Register LVDEN LVD DS39564C page 190 2006 Microchip Technology Inc PIC18FXX2 18 1 Control Register The Low Voltage Detect Control register controls the operation of the Low Voltage Detect circuitry REGISTER 18 1 bit 7 6 bit 5 bit 4 bit 3 0 LVDCON REGISTER U 0 U 0 R 0 R W 0 R W 0 R W 1 R W 0 R W 1 IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDLO bit 7 bit O Unimplemented Read as 0 IRVST Internal Reference Voltage Stable Flag bit 1 Indicates that the Low Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled LVDEN Low Voltage Detect Power Enable bit 1 Enables LVD powers up LVD circuit Disables LVD
399. te 3cycles if skip and followed by a 2 word instruction Q1 Q2 Q3 Q4 Decode Read Process Data No register f operation If skip Q1 Q2 Q3 04 operation operation operation operation If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example HERE BTFSC FLAG 1 0 FALSE TRUE Before Instruction BTFSS Bit TestFile Skip if Set Syntax label BTFSS 66 Operands 0 lt 1 lt 255 O lt b lt 7 ae 0 1 Operation skip if lt b gt 1 Status Affected None Encoding 1010 bbba ffff ffff Description If bit b in register is 1 then the next instruction is skipped If bit b is 1 then the next instruction fetched during the current instruc tion execution is discarded and a NOP is executed instead making this a two cycle instruction If a is 0 the Access Bank will be selected over riding the BSR value If 1 then the bank will be selected as per the BSR value default Words 1 Cycles 1 2 Note 3 cycles if skip and followed by a 2 word instruction Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Data No register f operation If skip Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No opera
400. te protected The WRTC bit controls protection of the configuration regis ters In User mode the WRTC bit is readable only WRTC can only be written via ICSP or an external programmer 19 5 ID Locations Eight memory locations 200000h 200007h are des ignated as ID locations where the user can store checksum or other code identification numbers These locations are accessible during normal execution through the TBLRD and TBLWT instructions or during program verify The ID locations can be read when the device is code protected The sequence for programming the ID locations is sim ilar to programming the FLASH memory see Section 5 5 1 19 6 In Circuit Serial Programming PIC18FXXX microcontrollers can be serially pro grammed while in the end application circuit This is simply done with two lines for clock and data and three other lines for power ground and the programming voltage This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product This also allows the most recent firmware or a custom firmware to be programmed 19 7 In Circuit Debugger When the DEBUG bit in configuration register CONFIG4L is programmed to a the In Circuit Debugger functionality is enabled This function allows simple debugging functions when used with MPLAB9 IDE When the microcontroller has this feature enabled some of the resources are not available for ge
401. ternal software programmable weak pull up Serial programming data Legend TTL TTL input ST Schmitt Trigger input Note 1 This buffer is a Schmitt Trigger input when configured as the external interrupt This buffer is a Schmitt Trigger input when used in Serial Programming mode A device configuration bit selects which I O pin the CCP2 pin is multiplexed on This buffer is a Schmitt Trigger input when configured as the CCP2 input Low Voltage ICSP Programming LVP is enabled by default which disables the RB5 1 0 function must be disabled to enable RB5 as an I O pin and allow maximum compatibility to the other 28 pin and 40 pin mid range devices um Bow TABLE 9 4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on Value on Name Bit7 Bit 6 Bit5 Bit 4 Bit 3 Bit2 Bit1 Bito POR BOR Other 4 5 5 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO XXXX uuuu uuuu LATB LATB Data Output Register XXXX uuuu uuuu TRISB PORTB Data Direction Register XIII T111 1111 1111 INTCON GIE PEIE TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 000x 0000 000u GIEH GIEL INTCON2 RBPU INTEDGO INTEDG1 INTEDG2 TMROIP RBIP 1111 1 1 1111 1 1 INTCON3 INT2IP INT2IE INT1IE INT2IF INT1IF 11 0 0 00 11 0 0 00 Legend x unknown u unchanged Shaded cells are not used by PORTB DS39564C page 92 2006 Microchip Technolog
402. the instruction Example 4 2 A fetch cycle begins with the program counter PC incrementing in Q1 In the execution cycle the fetched instruction is latched into the Instruction Register IR in cycle Q1 This instruction is then decoded and executed during the Q2 and Q4 cycles Data memory is read during Q2 operand read and written during Q4 destination write EXAMPLE 4 2 INSTRUCTION PIPELINE FLOW TcvO Tcv1 Tcv2 Tcy3 Tcv4 Tcv5 1 MOVLW 55h Fetch 1 Execute 1 2 MOVWF PORTB Fetch 2 Execute 2 3 BRA SUB 1 Fetch 3 Execute 3 4 BSF PORTA BIT3 Forced NOP Fetch 4 Flush NOP 5 Instruction address SUB 1 Fetch SUB 1 Execute SUB 1 All instructions are single cycle except for any program branches These take two cycles since the fetch instruction is flushed from the pipeline while the new instruction is being fetched and then executed 4 7 Instructions in Program Memory The program memory is addressed in bytes Instruc tions are stored as two bytes or four bytes in program memory The Least Significant Byte of an instruction word is always stored in a program memory location with an even address LSB 0 Figure 4 5 shows example of how instruction words are stored in the pro gram memory To maintain alignment with instruction boundaries the PC increments in steps of 2 and the LSB will always read 0 see Section 4 4 FIGURE 4 5 The CALL and
403. ther source file only the modules that contain that routine will be linked in with the application This allows large libraries to be used efficiently in many different applications The MPLIB object librarian manages the creation and modification of library files The MPLINK object linker features include Integration with MPASM assembler and MPLAB C17 and MPLAB C18 C compilers Allows all memory areas to be defined as sections to provide link time flexibility The MPLIB object librarian features include Easier linking because single libraries can be included instead of many smaller files Helps keep code maintainable by grouping related modules together Allows libraries to be created and modules to be added listed replaced deleted or extracted 215 MPLAB SIM Software Simulator The MPLAB SIM software simulator allows code devel opment in a PC hosted environment by simulating the PICmicro series microcontrollers on an instruction level On any given instruction the data areas can be examined or modified and stimuli can be applied from a file or user defined key press to any of the pins The execution can be performed in single step execute until break or trace mode The MPLAB SIM simulator fully supports symbolic debug ging using the MPLAB C17 and the MPLAB C18 C com pilers and the MPASM assembler The software simulator offers the flexibility to develop and debug code outside of the laboratory environmen
404. tion operation operation operation No No No No operation operation operation operation Example HERE BTFSS FLAG 1 0 FALSE TRUE Before Instruction PC address HERE After Instruction If FLAG lt 1 gt 0 PC address TRUE If FLAG lt 1 gt 1 PC address FALSE PC address HERE After Instruction If FLAG lt 1 gt address FALSE If FLAG lt 1 gt 1 PC address TRUE DS39564C page 224 2006 Microchip Technology Inc PIC18FXX2 BTG Bit Toggle f BOV Branch if Overflow Syntax label BTG f b a Syntax label BOV n Operands 0 lt 1 lt 255 Operands 128 lt lt 127 05657 Operation if overflow bit is 1 a 0 1 PC 2 2n PC Operation b f lt b gt Status Affected None Status Affected None Encoding 1110 0100 nnnn nnnn Encoding ERE FEFE Description If the Overflow bit is 1 then the Description Bit b in data memory location f is program will branch inverted If a is 0 the Access Bank The 2s complement number 2n is will be selected overriding the BSR added to the PC Since the PC will value If a 1 then the bank will be have incremented to fetch the next selected as per the BSR value instruction the new address will be default PC 2 2n This instruction is then Words 4 a two cycle instruction Cycles 1 Words 1 Q Cycle Activity Cycles 1 2 Q1 Q2 Q C
405. tput low until the SCL output is already sampled low If the user attempts to drive SCL low the CKP bit will not assert the SCL line until an external IC master device has already asserted the SCL line The SCL output will remain low until the CKP bit is set and all other devices on 12 bus have de asserted SCL This ensures that a write to the CKP bit will not violate the minimum high time reguirement for SCL see Figure 15 12 FIGURE 15 12 CLOCK SYNCHRONIZATION TIMING 01102 031 04101102 03104101102 03104101102 03 04101102 03041 011 02 03 24 01 02 03 34 1 5 SDA DX b DX 1 55 2 SCL Len Master device asserts clock K Master device de asserts clock WR O OA SSPCON 55 2006 Microchip Technology Inc DS39564C page 145 PIC18FXX2 SLAVE MODE TIMING WITH SEN 1 RECEPTION 7 BIT ADDRESS FIGURE 15 13 ul k OF 341990 ButuojeJis 0 430 446 eu jo 19 SI 4g ou pue 0 0 eq JOU IM 416 jo Jo ud S Jg m dMo 3095 JOU SI MOV IIn 115 8409955 9esneoeq
406. ts The Oscillator mode is specified during device programming A PLL lock timer is used to ensure that the PLL has locked before device execution starts The PLL lock timer has a time out that is called TPLL PLL BLOCK DIAGRAM Loop Filter VCO FIGURE 2 6 from Configuration HS Osce bit Register PLL Enable 5 Phase 0562 Comparator x FIN Crystal c Osc FOUT SYSCLK MUX Divide by 4 2006 Microchip Technology Inc DS39564C page 19 PIC18FXX2 2 6 Oscillator Switching Feature The PIC18FXX2 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source For the PIC18FXX2 devices this alternate clock source is the Timer1 oscillator If a low frequency crystal 32 kHz for example has been attached to the Timer1 oscillator pins and the Timer1 oscillator has been enabled the device can switch to a Low Power Execu FIGURE 2 7 DEVICE CLOCK SOURCES tion mode Figure 2 7 shows a block diagram of the system clock sources The clock switching feature is enabled by programming the Oscillator Switching Enable OSCSEN bit in Configuration Register1H to a 0 Clock switching is disabled in an erased device See Section 11 0 for further details of the Timer1 oscil lator See Section 19 0 for Configuration Registe
407. ture In addition to this the oscillator frequency will vary from unit to unit due to normal process parameter variation Furthermore the difference in lead frame capacitance between package types will also affect the oscillation frequency espe cially for low CEXT values The user also needs to take into account variation due to tolerance of external R and C components used Figure 2 3 shows how the R C combination is connected In the RC Oscillator mode the oscillator frequency divided by 4 is available on the OSC2 pin This signal may be used for test purposes or to synchronize other logic Note If the oscillator frequency divided by 4 sig nal is not required in the application it is recommended to use RCIO mode to save current FIGURE 2 3 RC OSCILLATOR MODE Internal Clock PIC18FXXX OSC2 CLKO Fosc 4 Recommended values 3 lt REXT lt 100 CEXT gt 20pF The RCIO Oscillator mode functions like the RC mode except that OSC2 pin becomes additional gen eral purpose I O pin The I O pin becomes bit 6 of PORTA DS39564C page 18 2006 Microchip Technology Inc PIC18FXX2 24 The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin The feedback device between OSC1 and OSC2 is turned off in these modes to save current There is no oscilla tor start up time required after a Power on Reset
408. uations Acquisition 2 000 185 Minimum Charging Time 185 Examples Calculating the Minimum Required Acquisition Time Result Registers eene Special Event Trigger CCP TAD vs Device Operating Frequencies Use of the CCP2 Trigger Absolute Maximum Ratings eene AC Timing Characteristics Load Conditions for Device Timing Specifications Parameter Symbology Temperature and Voltage Specifications AC 270 Timing Conditions 2 0202011 270 ACKSTAT Status Flag 155 ADCONO Register 181 GO DONE Bit 183 ADCON Register ss 181 ADDLEW 217 ADDWEQ ere eee ei 218 ADRESH Register 0 0 181 ADRESH ADRESL Registers 183 ADRESL Register 01 4 181 Analog to Digital Converter See A D ANDEM AL la 218 ANDWE 3 5 TE En 219 Assembler MPASM Assembler 253 B Baud Rate Generator 151 BG es 219 uen E 220 Status n 155 Block Diagrams AD Converter 5 3 a Analog Input Baud Rate Generato
409. uction If the first word of the instruction is exe cuted the data in the second word is accessed If the second word of the instruction is executed by itself first word was skipped it will execute as a NOP This action is necessary when the two word instruction is preceded by a conditional instruction that changes the PC A pro gram example that demonstrates this concept is shown in Example 4 3 Refer to Section 20 0 for further details of the instruction set EXAMPLE 4 3 TWO WORD INSTRUCTIONS CASE 1 Object Code Source Code 0110 0110 0000 0000 TSTFSZ is RAM location 0 1100 0001 0010 0011 MOVFF REG1 REG2 No execute 2 word instruction 1111 0100 0101 0110 2nd operand holds address of REG2 0010 0100 0000 0000 ADDWF REG3 continue code CASE 2 Object Code Source Code 0110 0110 0000 0000 TSTFSZ is RAM location 0 1100 0001 0010 0011 MOVFF REG1 REG2 Yes 1111 0100 0101 0110 2nd operand becomes NOP 0010 0100 0000 0000 ADDWF REG3 continue code 4 8 Lookup Tables Lookup tables are implemented two ways These are Computed GOTO Table Reads 4 8 1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter ADDWF PCL A lookup table can be formed with an ADDWF PCL instruction and a group of RETLW Oxnn instructions WREG is loaded with an offset into the table before executing a call to that table The first
410. uidance only and are not tested Note 1 Refer to Section 6 8 for a more detailed discussion on data EEPROM endurance DS39564C page 268 2006 Microchip Technology Inc PIC18FXX2 22 3 AC Timing Characteristics 22 3 1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats 1 TppS2ppS 3 TCC ST specifications only 2 TppS 4 Ts specifications only T F Frequency T Time Lowercase letters pp and their meanings pp cc CCP1 osc OSC1 ck CLKO rd RD cs cs rw RD or WR di SDI sc SCK do SDO 55 55 dt Data in to TOCKI io port t Wr WR Uppercase letters and their meanings S F Fall P Period H High R Rise Invalid Hi impedance V Valid L Low Z Hi impedance only AA output access High High BUF Bus free Low Low 8 specifications only CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition 2006 Microchip Technology Inc DS39564C page 269 PIC18FXX2 22 3 2 TIMING CONDITIONS The temperature and voltages specified in Table 22 3 apply to all timing specifications unless otherwise noted Figure 22 4 specifies the load conditions for the timing specifications TABLE 22 3 TEMPERATURE AND VOLTAGE SPECIFICATIONS AC Standard Operating Conditions unless otherwise stated Operating temperature 40 lt TA
411. ure SPI mode clear the SSPEN bit re initialize the SSPCON registers and then set the SSPEN bit This configures the SDI SDO SCK and SS pins as serial port pins For the pins to behave as the serial port func tion some must have their data direction bits in the TRIS register appropriately programmed That is SDI is automatically controlled by the SPI module SDO must TRISC 5 bit cleared SCK Master mode must have TRISC lt 3 gt bit cleared SCK Slave mode must have TRISC lt 3 gt bit set SS must have TRISC 4 bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction TRIS register to the opposite value 15 3 4 TYPICAL CONNECTION Figure 15 2 shows a typical connection between two microcontrollers The master controller Processor 1 initiates the data transfer by sending the SCK signal Data is shifted out of both shift registers on their pro grammed clock edge and latched on the opposite edge of the clock Both processors should be pro grammed to the same Clock Polarity CKP then both controllers would send and receive data at the same time Whether the data is meaningful or dummy data depends on the application software This leads to three scenarios for data transmission Master sends data Slave sends dummy data Master sends data Slave sends data Master sends dummy data Slave sends data
412. us serial port by clearing the SYNC bit and setting the SPEN bit 3 If interrupts are required set the bit and select the desired priority level with the RCIP bit Set the RX9 bit to enable 9 bit reception Set the ADDEN bit to enable address detect Enable reception by setting the CREN bit The RCIF bit will be set when reception is com plete The interrupt will be acknowledged if the RCIE and GIE bits are set 8 Read the RCSTA register to determine if any error occurred during reception as well as read bit 9 of data if applicable 9 Read RCREG to determine if the device is being addressed 10 If any error occurred clear the CREN bit 11 If the device has been addressed clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU USART BLOCK DIAGRAM x64 Baud Rate CLK CREN 64 SPBRG or 16 Baud Rate Generator RC7 RX DT Pin Buffer Data x and Control Recovery SPEN RX9 RX9D RCREG Register FIFO 8 Interrupt C RCIF Data Bus RCIE DS39564C page 174 2006 Microchip Technology Inc PIC18FXX2 FIGURE 16 5 ASYNCHRONOUS RECEPTION START bio Y X SS BiTre STOF bi Y SS 78 it GS ya STOP I I i I Rev Shift Reg gt C
413. values bit 6 INTEDGO External InterruptO Edge Select bit 1 Interrupt on rising edge 0 Interrupt on falling edge bit 5 INTEDG1 External Interrupt1 Edge Select bit 1 Interrupt on rising edge 0 Interrupt on falling edge bit 4 INTEDG2 External Interrupt2 Edge Select bit 1 Interrupt on rising edge 0 Interrupt on falling edge bit 3 Unimplemented Read as 0 bit 2 TMROIP TMRO Overflow Interrupt Priority bit 1 High priority 0 Low priority bit 1 Unimplemented Read as 0 bit O RBIP RB Port Change Interrupt Priority bit 1 priority 0 Low priority Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 1 Bit is set Bit is cleared Bit is unknown Note Interrupt bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt This feature allows for software polling DS39564C page 76 2006 Microchip Technology Inc PIC18FXX2 REGISTER 8 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 INTCON3 REGISTER R W 1 R W 1 U 0 R W 0 R W 0 U 0 R W 0 R W 0 INT2IP INT1IP INT2IE INT1IE INT2IF INT1IF bit 7 bit O INT2IP INT2 External Interrupt Priority bit 1 High priority 0 Low priority INT1IP INT1 External Interrupt Priority bit 1
414. w address will be Access Bank will be selected over PC 2 2n This instruction is a riding the BSR value If 1 then two cycle instruction the bank will be selected as per the Words 1 BSR value Cycles 2 Words 1 Q Cycle Activity 1 Q1 Q2 Q3 Q4 Q Cycle Activity Decode Read literal Process Write to PC Q1 Q2 Q3 04 Data Decode Read Process Write No No No No register Data register operation operation operation operation Example BSF FLAG REG 7 1 Example HERE BRA Jump Before Instruction FLAG REG 0x0A Before Instruction address HERE After Instruction FLAG REG 0x8A After Instruction PC address Jump 2006 Microchip Technology Inc DS39564C page 223 PIC18FXX2 BTFSC Syntax Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Bit Test File Skip if Clear label BTFSC f b a 0 lt 1 lt 255 O lt b lt 7 ae 0 1 skip if lt b gt 0 None 1011 bbba ffff ffff If bit b in register is 0 then the next instruction is skipped If bit b is O then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead making this a two cycle instruction If a is 0 the Access Bank will be selected over riding the BSR value If 1 then the bank will be selected as per the BSR value default 1 1 2 No
415. x Operation Status Affected Encoding 1st word source 2nd word destin Description Words Cycles Q Cycle Activity Q1 Move f to f label MOVFF ff 0 lt 1 lt 4095 0 lt fg lt 4095 fs gt fa None 1100 ffff ffff 1111 ffff ffff ffffg The contents of source register f are moved to destination register Location of source can be anywhere in the 4096 byte data space 000h to FFFh and location of destination 14 can also be any where from 000h to FFFh Either source or destination can be W a useful special situation MOVFF is particularly useful for transferring a data memory location to a peripheral register such as the transmit buffer or an I O port The MOVFF instruction cannot use the PCL TOSU TOSH or TOSL as the destination register Note The MOVFF instruction should not be used to mod ify interrupt settings while any interrupt is enabled See Section 8 0 for more information 2 3 Q2 Q4 Decode Read register src Process Data No operation Decode No operation No dummy read No operation Write register dest Example MOVFF RE Before Instruction REG1 REG2 0 33 0x11 After Instruction REG1 REG2 0 33 0 33 G1 REG2 MOVLB Move literal to low nibble in BSR Syntax label MOVLB k Operands
416. y Inc PIC18FXX2 9 3 PORTC TRISC and LATC Registers is 8 bit wide bi directional port The corre sponding Data Direction register is TRISC Setting a TRISC bit 1 will make the corresponding PORTC pin an input i e put the corresponding output driver in a Hi Impedance mode Clearing a TRISC bit O will make the corresponding PORTC pin an output i e put the contents of the output latch on the selected pin The Data Latch register LATC is also memory mapped Read modify write operations on the LATC register reads and writes the latched output value for PORTC PORTC is multiplexed with several peripheral functions Table 9 5 PORTC pins have Schmitt Trigger input buffers When enabling peripheral functions care should be taken in defining TRIS bits for each PORTC pin Some peripherals override the TRIS bit to make a pin an out put while other peripherals override the TRIS bit to make a pin an input The user should refer to the corre sponding peripheral section for the correct TRIS bit settings Note On a Power on Reset these pins are configured as digital inputs The pin override value is not loaded into the TRIS reg ister This allows read modify write of the TRIS register without concern due to peripheral overrides RC1 is normally configured by configuration bit as the default peripheral pin of the CCP2 module default erased state CCP2MX 1
417. ycle Activity Decode Read Process If Jump register f Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Example BTG PORTC n Data ae No No No No Before Instruction operation operation operation operation PORTC 0111 0101 0x75 After Instruction If No Jump PORTC 0110 0101 0x65 Q1 Q2 Q3 Q4 Decode Read literal Process No n Data operation Example HERE BOV Jump Before Instruction PC address HERE After Instruction If Overflow 1 address Jump If Overflow PC address HERE 2 2006 Microchip Technology Inc DS39564C page 225 PIC18FXX2 BZ Branch if Zero Syntax label BZ n 128 lt n lt 127 Operation if Zero bit is 1 PC 2 2n Status Affected None Encoding 1110 0000 nnnn nnnn Description If the Zero bit is 1 then the pro gram will branch The 2 s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a two cycle instruction Words 1 Cycles 1 2 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Data No No No No operation operation operation operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal Process No Data operation Example HERE BZ Jump Before Instruction PC address HERE After Instruction If Zero 1 address Jump If Zero 0 ad

MICROCHIP - PIC18FXX2 Data Sheet

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