ANALOG DEVICES ADM4210 English products handbook Rev 0
Contents
1. SUPPLY VOLTAGE V Figure 26 vs Supply Voltage 05132 041 05132 047 ADM4210 toFF ONLOw HS 50 49 TEMPERATURE C Figure 27 torrionow vs Temperature mV 6 8 10 12 SUPPLY VOLTAGE V 14 16 Figure 28 Cct Breaker Voltage vs Supply Voltage 18 05132 048 05132 049 Rev 0 Page 10 of 16 25 50 75 TEMPERATURE C 100 125 Figure 29 Cct Breaker Voltage vs Temperature 150 05132 021 ADM4210 THEORY OF OPERATION Many systems require the insertion or removal of circuit boards to live backplanes During this event the supply bypass and hold up capacitors can require substantial transient currents from the backplane power supply as they charge These currents can cause permanent damage to connector pins or undesirable glitches and resets to the system ADM4210 is intended to control the powering of a system on and off in a controlled manner allowing the board to be removed from or inserted into a live backplane by protecting it from excess currents The ADM4210 can reside either on the backplane or on the removable board OVERVIEW ADM4210 operates over a supply range of 2 7 V to 16 5 V As the supply voltage is coming up an undervoltage lockout circuit checks if sufficient s2. operates with a supply voltage ranging from 2 7 V to 16 5 V The ADM4210 is available in two options the ADM4210 1 with automatic retry for overcurrent fault and the ADM4210 2 with latch off for an overcurrent fault Toggling the ON ON CLR pin resets a latched fault The ADM4210 is packaged in a 6 lead TSOT Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM RsENSE 5V LONG 0 010 Q Vout 5 05132 001 Figure 1 Croan 470 VoN 2VIDIV VTIMER 1VIDIV Vour 5VIDIV l lout 0 5A DIV 10ms DIV 05132 050 Figure 2 Start Up Sequence One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2006 Analog Devices Inc All rights reserved ADM4210 TABLE OF CONTENTS Features a aaa aus 1 Suwaqa 11 1 naqha 1
3. the external FET This minimizes the bus supply voltage drop caused by the fault and protects neighboring cards As the voltage across the sense resistor approaches the current limit a timer activates This timer resets again if the sense voltage returns below this level If the sense voltage is any voltage below 44 mV the timer is guaranteed to be off Should the current continue to increase the ADM4210 tries to regulate the gate of the FET to achieve a limit of 50 mV across the sense resistor However if the device is unable to regulate the fault current and the sense voltage further increases a larger pull down in the order of milliamperes is enabled to compensate for fast current surges If the sense voltage is any voltage greater than 56 m V this pull down is guaranteed to be on When the timer expires the GATE pin shuts down TIMER FUNCTION The TIMER pin is responsible for several key functions on the ADM4210 A capacitor controls the initial power on reset time and the amount of time an overcurrent condition lasts before the FET shuts down On the ADM4210 1 the timer pin also controls the time between auto retry pulses There are pull up and pull down currents internally available to control the timer functions The voltage on the TIMER pin is compared with two threshold voltages 1 0 2 V and COMP2 1 3 V The four timing currents are listed in Table 5 Table 5 Timing Current Level Pull up 5 Pull
4. up 60 Pull down 2 Pull down 100 POWER UP TIMING CYCLE The ADM4210 is in reset when the ON ON CLR pin is held low The GATE pin is pulled low and the TIMER pin is pulled low with a 100 uA pull down At Time Point 2 in Figure 30 the ON ON CLR pin is pulled high For the device to startup correctly the supply voltage must be above UVLO the ON ON CLR pin must be above 1 3 V and the TIMER pin voltage must be less than 0 2 V The initial timing cycle begins when these three conditions are met and the TIMER pin is pulled high with 5 At Time Point 3 the TIMER reaches the COMP2 threshold This is the end of the first section of the initial cycle The 100 current source then pulls down the TIMER pin until it reaches 0 2 V at Time Point 4 The initial cycle delay Time Point 2 to Time Point 4 relates to Crimer by equation 1 3 x Crimer 5 4 When the initial cycle ends a start up cycle activates and the GATE pin is pulled high the TIMER pin continues to pull down I I I T Vour INITIAL NORMAL MODE CYCLE 11 CYCLE START UP CYCLE RESET INITIAL START UP NORMAL MODE CYCLE CYCLE CYCLE 05126 003 Figure 31 Power Up into Capacitor Rev 0 Page 12 of 16 CIRCUIT BREAKER TIMING CYCLE When the voltage across the sense resistor exceeds the circuit breaker trip voltage the 60 uA timer pull
5. 1 General Descriptio nsss Qu aq ss 1 O 11 Functional Block Diagram ananas 1 Current Limit 11 Revision 2 Calculating the Current 11 Specifications naa e E 3 Circuit Breaker Function a aaaaassasssaaas 12 Absolute Maximum Ratings 4 Timer Pui ction u aaa e ei ias 12 Thermal Characteristics 4 Power Up Timing 12 BSD Caution 4 Circuit Breaker Timing 13 Pin Configurations and Function Descriptions 5 Automatic Retry or Latched 13 Typical Performance Characteristics 6 Outline 31015 14 Theory of Operation a a uu 11 Ordering Guide asus ainiin 14 ON AETA ETETETT T T cess sseadeasbanss 11 REVISION HISTORY 7 06 Revision 0 Initial Version Rev 0 2 of 16 ADM4210 SPECGIFICATIONS Vcc 2 7 V to 16 5 V Ta 40 C to 85 C typical values at Ta 25 C unless otherwise noted Table 1 Parameter Symbol Min Typ Max Unit Conditions Vcc PIN Operating Voltage Range Vcc 2 7 16 5 V Supply Current 0 65 3 5 mA Undervoltage Lockout Vuvio 2 2 2 5 2 65 V Vcc rising Undervoltage Lockout Hysteresis Vuvioryys 100 mV ON ON CLR PIN Input Current linon 10 0 10 Threshold
6. ANALOG DEVICES Hot Swap Controller in 6 Lead TSOT Package ADM4210 FEATURES Controls supply rails from 2 7 V to 16 5 V Allows protected board removal and insertion to a live backplane External sense resistor provides adjustable analog current limit with circuit breaker Peak fault current limited with fast response Charge pumped gate drive for external N FET switch Automatic retry or latch off during current fault Undervoltage lockout Low profile 1 mm 6 lead TSOT package Pin compatible with LTC4210 1 and LTC4210 2 APPLICATIONS Hot swap board insertion line cards raid systems Industrial high side switches circuit breakers Electronic circuit breakers GENERAL DESCRIPTION The ADM4210 is a hot swap controller that safely enables a printed circuit board to be removed and inserted to a live backplane This is achieved using an external N channel power MOSFET with a current control loop that monitors the load current through a sense resistor An internal charge pump is used to enhance the gate of the N channel FET When an overcurrent condition is detected the gate voltage of the FET is reduced to limit the current flowing through the sense resistor During an overcurrent condition the TIMER cap determines the amount of time the FET remains at a current limiting mode of operation until it is shut down The ON ON CLR pin is the enable input for the device and can be used to monitor the input supply voltage The ADM4210
7. Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device This is a stress Pin 0 3 V to 20V rating only functional operation of the device at these or any SENSE Pin 0 3V to 20V other conditions above those indicated in the operational Vcc SENSE 5V section of this specification is not implied Exposure to absolute TIMER Pin 0 3 V to Vcc 0 3 V maximum rating conditions for extended periods may affect ON ON CLR Pin 0 3 V to 20 V device reliability GATE Pin 0 3 V to Vcc 11 V Storage Temperature Range 65 C to 125 C THERMAL CHARACTERISTICS Operating Temperature Range 40 C to 85 C is specified for the worst case conditions that is a device Lead Temperature 10 sec 300 C soldered in a circuit board for surface mount packages Junction Temperature BUC Table 3 Thermal Resistance Package Type Osa Unit 6 Lead TSOT 169 5 C W ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection Although this product features PAV AIT lt proprietary ESD protection permanent damage may occur devices subjected to high energy Ag electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE Rev 0 Page 4 of 16 ADM4210 PIN CONFIGURATI
8. E pins In an overcurrent condition the gate of the FET is controlled to maintain the SENSE voltage at 50 mV When this limit is reached the TIMER circuit breaker mode is activated The circuit breaker limit can be disabled by connecting the Vcc pin and SENSE pin together Positive Supply Input Pin The ADM4210 operates between 2 7 V to 16 5 V An undervoltage lockout UVLO circuit with a glitch filter resets the ADM4210 when the supply voltage drops below the specified UVLO limit Rev 0 Page 5 of 16 ADM4210 TYPICAL PERFORMANCE CHARACTERISTICS SUPPLY CURRENT mA SUPPLY CURRENT mA UVLO THRESHOLD V Ta 25 C 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE V Figure 5 Supply Current vs Supply Voltage 50 25 0 25 50 75 100 125 150 TEMPERATURE C Figure 6 Supply Current vs Temperature RISING Vec FALLING 50 25 0 25 50 75 100 125 150 TEMPERATURE C Figure 7 UVLO Threshold vs Temperature 05132 032 05132 033 05132 046 Rev 0 6 of 16 GATE VOLTAGE V GATE VOLTAGE V GATE CURRENT pA SUPPLY VOLTAGE V Figure 8 GATE Voltage vs Supply Voltage TEMPERATURE C Figure 9 GATE Voltage vs Temperature SUPPLY VOLTAGE V Figure 10 GATE Current up vs Supply Volta
9. ONS AND FUNCTION DESCRIPTIONS ADM4210 1AUJ ADM4210 2AUJ Table 4 P 6 Vcc TIMER 6 Vcc VIEW SENSE GND Not to Scale 5 GATE VIEW SENSE 12 Not to Scale 5 ON CLR 3 4 GATE 05132 006 05132 007 Figure 3 Pin Configuration 1AUJ Model Figure 4 Pin Configuration 2AUJ Model in Function Descriptions Pin No Mnemonic Description 1 TIMER GND ON ON CLR GATE SENSE Vcc Timer Input Pin The initial and circuit breaker timing cycles are set by this external capacitor The initial timing delay is 272 9 ms uF and 21 7 5 for a circuit breaker delay When the TIMER pin is pulled beyond the upper threshold the GATE turns off Chip Ground Pin Input Pin The ON ON CLR pin is an input to a comparator that has a low to high threshold of 1 3 V with 80 mV hysteresis and a glitch filter The ADM4210 is reset when the ON ON CLR pin is low When the ON ON CLR pin is high the ADM4210 is enabled A rising edge on this pin has the added function of clearing a fault and restarting the device on the latched off model the ADM4210 2 Gate Output Pin An internal charge pump provides 12 pull up current to drive the gate of an N channel MOSFET In an overcurrent condition the ADM4210 controls the external FET to maintain a constant load current Current Limit Sense Input Pin The current limit is set via a sense resistor between the Vcc and SENS
10. VoN 1 22 1 3 1 38 V ON rising Threshold Hysteresis 80 mV SENSE PIN Input Current INSENSE 10 5 10 Vsense Vcc Circuit Breaker Limit Voltage Vcs 44 50 56 mV Vcs Vcc Vsense GATE PIN Pull Up Current GATEUP 5 10 15 Pull Down Current IGATEDN 25 mA Vimer 1 5 V Veate 3 V or Von 0 V Veate 3 V or Vsense 100 mV Veate 3 V Gate Drive Voltage Vaate 4 5 7 5 10 Vaate Vec 3 V 5 0 8 5 12 Vaate Vcc 3 3 8 75 12 16 Vaate Vcc Vcc 5 7 6 12 16 Vaate Vcc Vec 12 V 6 0 11 18 Vaate 15 Pull Up Current TIMERUP 2 5 8 5 Initial cycle 1 V 25 60 100 During current fault 1 V Pull Down Current TIMERDN 2 3 5 After current fault 1 V 100 Normal operation Vimer 1 V Threshold High 1 22 133 1 38 V TIMER rising Threshold Low VTIMERL 015 02 0 25 V TIMER falling Turn Off Time TIMER Rise to GATE Fall toFF TMRHIGH 1 us Vimer OV to 2 V step Vcc Von 5 V Turn Off Time ON ON CLR Fall to GATE Fall ToFF ONLOW 30 us Von 5 V to OV step Vc 5 V Turn Off Time Vcc Rise to IC Reset toFF vccLow 30 us Vcc 0 V to 2V step 5 V Rev 0 Page 3 of 16 ADM4210 ABSOLUTE MAXIMUM RATINGS Table 2 Stresses above those listed under
11. anding ADM4210 1AUJZ RL7 40 C to 85 C 6 Lead TSOT UJ 6 M2P ADM4210 2AUJZ RL7 40 C to 85 C 6 Lead TSOT UJ 6 M2Q 1 Z Pb free part Rev 0 14 of 16 ADM4210 NOTES Rev 0 Page 15 of 16 ADM4210 NOTES 2006 Analog Devices Inc All rights reserved Trademarks and ANALOQ registered trademarks are the property of their respective owners D05132 0 7 06 0 DEVICES www analo g com Rev 0 Page 16 of 16
12. c Retry During Overcurrent Fault ADM4210 AUTOMATIC RETRY OR LATCHED OFF The ADM4210 is available in two models The ADM4210 1 has an automatic retry system whereby when a current fault is detected the FET is shut down after a time determined by the timer capacitor and it is switched on again in a controlled con tinuous cycle to determine if the fault remains see Figure 32 for details The period of this cycle is determined by the timer capacitor at a duty cycle of 3 8 on and 96 2 off The ADM4210 2 model has a latch off system whereby when a current fault is detected the GATE is switched off after a time determined by the timer capacitor see Figure 33 for details Toggling the ON CLR pin or pulling the TIMER pin to GND for a brief period resets this condition 05126 005 Figure 33 ADM4210 2 Latch Off After Overcurrent Fault Rev 0 Page 13 of 16 ADM4210 OUTLINE DIMENSIONS ORDERING GUIDE 2 90 BSC 1 60 BsC 2 80 5 PIN 1 INDICATOR 0 95 1 90 0 90 BSC 087 0 84 amp oeo a SEATING A 0 45 0 10 Max 0 50 l o 030 COMPLIANT JEDEC STANDARDS 193 WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS Figure 34 6 Lead Thin Small Outline Transistor Package TSOT UJ 6 Dimensions shown in millimeters Model Temperature Range Package Description Package Option Br
13. ce Care must be taken not to load the GATE pin resistively because this reduces the gate drive capability CURRENT LIMIT FUNCTION The ADM4210 features a fast response current control loop that actively limits the current by reducing the gate voltage of the external FET This current is measured by monitoring the voltage drop across an external sense resistor The ADM4210 tries to regulate the gate of the FET to achieve a 50 mV voltage drop across the sense resistor CALCULATING THE CURRENT LIMIT The sense resistor connected between Vcc and the SENSE pin is used to determine the nominal fault current limit This is given by the following equation ILIMIT wom VCBwom 5 5 1 The minimum load current is given by Equation 2 ILIMIT mw 2 The maximum load current is given by Equation 3 ILIMITmax VCBmax RSENSEmm 3 For proper operation the minimum current limit must exceed the circuit maximum operating load current with margin The sense resistor power rating must exceed Rev 0 11 of 16 ADM4210 CIRCUIT BREAKER FUNCTION When the supply experiences a sudden current surge such as a low impedance fault on load the bus supply voltage can drop significantly to a point where the power to an adjacent card is affected potentially causing system malfunctions The ADM4210 limits the current drawn by the fault by reducing the gate voltage of
14. ge 05132 013 05132 015 05132 009 0 4210 11 0 11 2 11 4 1 11 8 NT uA ITIMERUP GATE CURRE N gt N 50 25 0 25 50 75 100 125 150 TEMPERATURE C 05132 017 05132 035 SUPPLY VOLTAGE V Figure 11 GATE Current up vs Temperature Figure 14 in Initial Cycle vs Supply Voltage 10 0 Voc 5V DELTA GATE VOLTAGE V wo gt m ItimeRup Pay a 0 2 4 6 10 12 14 16 48 50 25 0 25 50 75 100 125 1508 SUPPLY VOLTAGE V 8 8 Figure 12 Delta GATE Voltage vs Supply Voltage Figure 15 Initial Cycle vs Temperature ItimeRup DELTA GATE VOLTAGE V 0 2 4 6 8 10 12 14 16 48 SUPPLY VOLTAGE V 05132 016 05132 036 TEMPERATURE C Figure 13 Delta GATE Voltage vs Temperature Figure 16 During Cct Breaker Delay vs Supply Voltage Rev 0 Page 7 of 16 ADM4210 ItimeRuP TEMPERATURE C Figure 17 During Cct Breaker Delay vs Temperature ITIMERDN HA SUPPLY VOLTAGE V Figure 18 in Cool Off Cyc
15. he ADM4210 2 A low input on the ON ON CLR pin turns off the external FET by pulling the GATE pin to ground and resets the timer An external resistor divider at the ON ON CLR pin can be used to program an undervoltage lockout value higher than the internal UVLO circuit There is a glitch filter delay of approximately 3 on rising allowing the addition of an RC filter at the ON ON CLR pin to increase the delay time at card insertion If using a short pin system to enable the device a pull down resistor should be used to hold the device prior to insertion GATE Gate drive for the external N channel MOSFET is achieved using an internal charge pump The gate driver consists of a 12 uA pull up from the internal charge pump There are various pull down devices on this pin At a hot swap condition the board is hot inserted to the supply bus During this event it is possible for the external FET GATE capacitance to be charged up by the sudden presence of the supply voltage This can cause uncontrolled inrush currents An internal strong pull down circuit holds GATE low while in UVLO This reduces current surges at inser tion After the initial timing cycle the GATE is then pulled high During an overcurrent condition the ADM4210 servos the GATE pin in an attempt to maintain a constant current to the load until the circuit breaker timeout completes In the event of a timeout the GATE pin abruptly shuts down using the 4 mA pull down devi
16. le vs Supply Voltage ITIMERDN HA TEMPERATURE C Figure 19 in Cool Off Cycle vs Temperature 05132 039 05132 034 05132 037 Rev 0 Page 8 of 16 TIMER HIGH THRESHOLD V 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE V Figure 20 TIMER High Threshold vs Supply Voltage Voc 5V TIMER HIGH THRESHOLD V 50 25 0 25 50 75 100 125 150 TEMPERATURE C Figure 21 TIMER High Threshold vs Temperature TIMER LOW THRESHOLD V 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE V Figure 22 TIMER Low Threshold vs Supply Voltage 05132 042 05132 044 05132 043 TIMER LOW THRESHOLD V ON ON CLR PIN THRESHOLD V 50 25 0 25 50 75 100 125 150 TEMPERATURE C Figure 23 TIMER Low Threshold vs Temperature THRESHOLD LOW THRESHOLD 1 05 2 4 6 8 10 12 14 16 0 18 SUPPLY VOLTAGE V Figure 24 ON ON CLR Pin Threshold vs Supply Voltage 05132 045 05132 040 Rev 0 9 of 16 ON ON CLR PIN THRESHOLD V torF onLow HS ADM4210 1 45 1 40 1 35 HIGH THRESHOLD 1 25 LOW THRESHOLD 50 25 0 25 50 75 100 125 150 TEMPERATURE C Figure 25 ON ON CLR Pin Threshold vs Temperature
17. up current is activated If the sense voltage falls below this level before the TIMER pin reaches 1 3 V the 60 uA pull up is disabled and the 2 uA pull down is enabled This is likely to happen if the overcurrent fault is only transient such as an inrush current This is shown in Figure 31 However if the overcurrent condition is continuous and the sense voltage remains above the circuit breaker trip voltage the 60 uA pull up remains active This allows the TIMER pin to reach the high trip point of 1 3 V and initiate the GATE shutdown On the ADM4210 2 the TIMER pin continues pulling up but switches to the 5 uA pull up when it reaches the 1 3 threshold The device can be reset by toggling the ON CLR pin or by manually pulling the TIMER pin low On the ADM4210 1 the TIMER pin activates the 2 pull down once the 1 3 V threshold is reached and continues to pull down until it reaches the 0 2 V threshold At this point the 100 uA pull down is activated and the GATE pin is enabled The device keeps retrying in the manner as shown in Figure 32 The duty cycle of this automatic retry cycle is set to the ratio of 2 uA 60 uA which approximates 3 8 The value of the timer capacitor determines the on time of this cycle This time is calculated as follows ton 1 3 x 60 tore 1 1 x 2 I sl I IRsense 1 I I Y 5126 004 FAULT CYCLE CYCLE Figure 32 ADM4210 1 Automati
18. upply voltage is present for proper operation During this period the FET is held off by the GATE pin being held to GND When the supply voltage reaches a level above UVLO and the ON ON CLR pin is high an initial timing cycle ensures that the board is fully inserted in the backplane before turning on the FET The TIMER pin capacitor sets the periods for all of the TIMER pin functions After the initial timing cycle the ADM4210 monitors the inrush current through an external sense resistor Overcurrent conditions are actively limited to 50 m V Rs ssz for the circuit breaker timer limit The ADM4210 1 automatically retries after a current limit fault and the ADM4210 2 latches off The retry duty cycle on the ADM4210 1 timer function is limited to 3 8 for FET cooling UVLO If the Vcc supply is too low for normal operation an under voltage lockout circuit holds the ADM4210 in reset The GATE pin is held to GND during this period When the supply reaches this UVLO voltage the ADM4210 starts when the ON ON CLR pin condition is satisfied ON ON CLR PIN The ON ON CLR pin is the enable pin It is connected to a comparator that has a low to high threshold of 1 3 V with 80 mV hysteresis and a glitch filter The ADM4210 is reset when the ON ON CLR pin is low When the ON ON CLR pin is high the ADM4210 is enabled A rising edge on this pin has the added function of clearing a fault and restarting the device on the latched off model t
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ANALOG DEVICES ADM4210 English products handbook Rev 0