MOTOROLA MC34016 Data Sheet
Contents
1. i MSETO ROLA ANALOG IC DEVICE DATA Go to www freescale com Freescale Stsi nductor Inc 2i MC34016 4H AV fg PIN FUNCTION DESCRIPTION Pin Symbol Description 1 Serial bus clock input 2 Data Serial bus data input 3 Out2 Logic output 2 4 Stab Line driver compensation 5 Gnd Ground 6 HKSW Logic output for the hook switch 7 Outi Logic output 1 8 Vcc Supply input 5 0 V Coe R mmessmensdn MOTOROLA ANALOG IC DEVICE D mere Information On This Product 5 Go to www freescale com Freescale St i i nductor Inc DESCRIPTION OF THE CIRCUIT SAU ifo e refer to the typical application of Figure 10 The data given in this chapter refers to typical data of the characteristics DC OPERATION For dc the MC34016 incorporates four different masks which can be selected via the serial bus interface Bit 4 Reg 1 Bit 5 Reg 1 Bit 1 Reg 2 Mask DC Mode AGC Ratio 0 0 X DC Mask Selected Voltage Regula tion Mask Current Regula tion Mask with AGC Ratio 1 2 Current Regula tion Mask with AGC Ratio 3 5 X don t care Voltage Regulation Mask The voltage regulation mask is the default setting of the MC34016 after power up In this mode the circuit behaves as a zener with a series resistor The line voltage can be expressed as Viine VBG IBG X RDC1 RS with VBG 1 3 V IBG 5 2 pA2. Serial Bus Logic a Inputs Outputs e e e This device contains 610 active transistors 242 gates MAXIMUM RATINGS Rating Symbol Value Unit Operation Supply Voltage 0 5 6 5 V All Other Inputs Vin 0 5 V Vcc 0 5 Operating Ambient Temperature TA 20 to 70 Junction Temperature TJ 150 NOTE ESD data available upon request C or More information Un Go to www freescale com IS Pro ROLA ANALOG IC DEVICE DATA Freescale Stsi i nductor Inc DC GHARACTERISTIGS M parameters are das with Bit 0 of Register 1 set to 1 the rest of the VOLTAGE REGULATION Line Voltage Vline lline 5 0 mA 15 lline 60 CURRENT REGULATION Bit 4 Reg 1 1 Bit 1 Reg 2 1 47 Line Voltage Vline Line Current 10 V Vline 35V Line Current in Protection Mode 70 V DC BIASING Operating Supply Voltage Vcc Current Consumption from Voc Voc 3 0 V all Bits to 0 Vcc 5 0 V all Bits to 0 Source Capabiltiy Pin LAO in Speech Mode VLAO 20 7 V Source Capability Pin LAO in Dialing Mode Bit 5 Reg 1 1 Internal Pull Down Resistor at Pin LAO Bias Voltage at Pins and Ry2 1 3 V LOGIC INPUTS Logic Low Level Pins Clk Data BEN 0 6 V Logic High Level Pins CIk Data BEN 2 2 B V LOGIC OUTPUTS Source Capability from Pins HKSW Out1 Out2 Output
3. 0dB registers are set to 0 This RESET function enables smooth 1 AGC Range 0 dB Switched power up of the device The registers are as follows 1 Voltage Current i E Regulation Regulation Register 1 Bit 7 0 Bit 4 Bit 4 Reg 1 0 Reg 1 1 0 Ratio 1 3 0 Ratio 1 2 0 HKSW is Low 1 Ratio 1 2 1 Ratio 3 5 1 HKSW is High 0 Out1 is Low 1 Out1 is High Output 0 Out2 is Low Out2 1 Out2 is High Not Used 1 DC Mask 0 Voltage Regulation Mask 5 Receive Receive Channel Gain 0 dB 1 Current Regulation Mask for Gain Receive Channel Gain 6 0 dB France 6 Normal Mode PABX Mode only Input HYS Selected 2 Transmit Transmit Channel Active Mute Transmit Channel Muted 3 Receive Receive Channel Active Mute Receive Channel Muted 4 Transmit Transmit Channel Gain 0 dB Gain Transmit Channel Gain 6 0 dB DC Mode 0 Speech Mode Normal Operation 1 Dialing Mode for Low Voltage Drop Figure 1 Line Voltage versus Line Current Figure 2 Line Voltage versus Line Current Voltage Regulation Mask Pulse Dial Mask 6 0 1 680 5 0 g 40 E 9 30 2 2 Rer a 20 20 40 0 0 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 line LINE CURRENT mA line LINE CURRENT m
4. D MILLIMETERS INCHES MIN MAX 0 010 0 25 g 12 65 12 95 0 499 0 510 740 7 60 0 292 0 299 2 35 2 65 0 093 0 104 0 35 0 49 0 014 0 019 0 50 0 90 0 020 0 035 1 27 BSC 0 050 BSC 0 25 0 32 0 010 0 012 0 10 0 25 0 004 0 009 0 1 0 7 10 05 10 55 0 395 0 415 0 25 0 75 0 010 0 029 lt _ SEATING PLANE 14 Or MOFO chan Sn 1 MSETO ROLA ANALOG IC DEVICE DATA Go to www freescale com Freescale Stsi nductor Inc NOTES A M 34016 4H Av Fs MOTOROLA ANALOG IC DEVICE D mere Information On This Product 15 Go to www freescale com Freescale Stsi i nductor Inc A M 34016 4H Av Fs For More Information On This Product Go to www freescale comH tee wii
5. Voltage at Vcc 1 3 V 1 0 mA Sink Capability into Pins HKSW Out1 Out2 Output Voltage at 0 5 V 5 0 AC ELECTRICAL CHARACTERISTICS All parameters are specified with Bit 0 of Register 1 set to 1 the rest of the bits in both registers set to 0 TA 25 C Vcc 5 0 V lige 15 mA f 1 0 kHz Test Circuit in Figure 9 unless otherwise noted Parameter Condition Min Typ Max Unit TRANSMIT CHANNEL Transmit Gain from VTy to Vline MC34016P MC34016DW VTx 0 1 Vrms Gain Variation with Line Current Referred to lline 70 mA lline 15 mA with the AGC Function Switched Off Bit 0 Reg 2 1 Gain Increase in 6 0 dB Mode Bit 4 Reg 2 1 Gain Reduction in Mute Condition Bit 2 Reg 2 1 Maximum Input Swing for THD lt 2 THD at the Line Psophometrically Weighted Noise Level at the Line 200 Q Between Tx2 79 dBmp Vine RECEIVE CHANNEL Receive Gain from to VRy 0 1 Vrms 1 0 0 1 0 dB Gain Variation with Line Current Referred to lline 70 mA 0 7 0 7 dB lline 15 mA with the AGC Function Switched Off Bit 0 Reg 2 1 re Inrormation IS Proauct 3 o MOTOROLA ANALOG IC DEVICE DA Freescale Stsi nductor Inc AC ELECTRICAL CHARACTERISTICS continued All parameters are specified with Bit 0 of Register 1 set to 1 the rest of the Ais n egege s sid pia 25
6. current of 29 mA With the AGC ratio set to 1 2 the knee occurs at 20 mA Above these line currents it can be derived that the dc slope of the circuit changes to DC1 AGC With the component values mentioned a slope of 1300 will occur Figures and 4 shows Vine versus in the two current regulation masks for different values of When reaches 62 uA for AGC ratio 3 5 or 52 uA in case of AGC ratio 1 2 the MC34016 will enter protection mode after about 800 ms In practice this mode occurs only under overload conditions In protection mode the MC34016 decreases the power dissipation in Q1 by drastically increasing the dc slope starting from Iknee This results in a reduced line current which remains practically constant over line voltage With the equation for lagc it can be derived that xR 2 5 Rslope Te R Rg Line Current to Enter Line Current in AGC ratio Protection Mode Protection Mode 3 5 58 mA 29 mA 1 2 49 mA 20 mA Once the MC34016 enters protection mode it remains there until the output HKSW is toggled via 0 of Register 1 off hook Supply Voltage Vcc The MC34016 operates from an external supply within a voltage range of 3 0 to 5 5 V The current consumption with all bits set to 0 equals 3 0 mA at 3 0 V and 3 5 mA at 5 5 V AC SET IMPEDANCE The MC34016 offers two possibilities for the adjustment of the ac set impedance Either a passive
7. 047 Receive Outputs CRyo 0 047 Vine Line x MC34016 pe Transmit 4 0 047 BG Inputs _ i Gnd amp 4 D2 CTy2 0 047 1N4004 B Ring Serial Bus Interface AGC A Tip Data BEN Outt a m R RAGC Rs _LCseT L Supply Re 100 0 Toi e e e e gt From MPU gt Shunt gt Earth gt NOTE Sidetone Networks not adapted to country specific telephone lines Opt Or MOTE THOSE EISE TUM ROLA ANALOG IC DEVICE DATA 12 Go to www freescale com Freescale Stsi i nductor Inc Figure 11 Typical Application with Active Impedance and Current Regulation ZS i8 M CAOL HMR no uc C d bd Cstab 100 p RINT 1 8k lt Receive Outputs 0 Vine lt Q1 1 gt MC34016 Driver Fa MJE340 Transmit cr VBG Inputs _ ve Gnd e 4 D2 0 047 1N4004 B Ring Serial Bus Interface AGC A Tip Data BEN Out Out2 K Q3 MPSA42 R RAGC Rs LCM L Supply Re 100 0 501 Y Ld remm pm gt Shunt x Earth gt Optional NOTE Sidetone Networks not adapted to country specific telephone lines MOTOROLA ANALOG Ic DEVICE kore Information On This Produc i35 M
8. 1 DC setting resistor of 470 in the typical application Line current Rs Slope resistor of 50 in the typical application thus Vline 3 75 50 x line By choosing different values of the zener voltage can be adjusted to fit country specific requirements In Figure 1 a curve shows Vine versus for different Rp C1 values Pulse Dial Mask In this mask the circuit is forced into a very low voltage drop mode meant for pulse dialing e g make period during pulse dialing Pin LAO of the MC34016 sources a current of 5 0 mA in this mode saturating output transistor Q1 The line voltage Vline is now determined by the saturation voltage of Q1 and the dc slope resistor Rs VCE sat Q1 RS X lline 0 1 50 line Figure 2 shows versus lline Current Regulation Masks These masks are equal to the voltage regulation mask up to a knee current Above this current the dc slope changes to a higher value fulfilling requirements such as those in France 3 75 RS lline forlAGC lt IBG 2 5 x laGC Iknee RDC1 VBG Rs lline for IAGC gt lknee 6 or More Information On is Pro Go to www freescale com with X Ln AGC line RAGC 21 for AGC ratio 1 2 31 for AGC ratio 3 5 With Rs 50 Q and 47 and the AGC ratio set 103 5 laGC will equal Iknee ata line
9. 5 0 V line 15 mA f 1 0 kHz Test Circuit in T 9 unless otherwise noted RECEIVE CHANNEL Gain Increase in 6 0 dB Mode Bit 5 Reg 2 1 Input Impedance at HYL or HYS Ep Du Maximum Input Swing at HYL or HYS for THD lt 2 mVpp Maximum Output Swing 0 for THD x 10 a Total Harmonic Distortion at Total Harmonie Distorion at WRx o AUTOMATIC GAIN CONTROL Gain Reduction in Transmit and Receive Channel with line 70 mA Respect to line 15 mA Highest Line Current for Maximum Gain 23 Gain Reduction in Transmit and Receive Channel with lline 85 mA Respect to line 35 mA Bit 1 Reg 2 1 Highest Line Current for Maximum Gain Bit 1 Reg 2 1 40 Lowest Line Current for Minimum Gain Bit 1 2 1 8 m BALANCE RETURN LOSS Balance Return Loss with Respect to 6000 f 1 0 kHz 20 d SIDETONE Voltage Gain from VTy to VRx lline 15 mA 20 dB Bit 0 Reg 2 1 SERIAL BUS Clock Frequency BEN Rising Edge Setup Time Before First Rising See t1 in Timing Diagram ILI Edge Data Setup Time Before CIk Rising Edge See t2 in Timing Diagram Data Hold Time After CIk Rising Edge See 13 in Timing Diagram BEN Falling Edge Delay Time After Last Rising See t4 in Timing Diagram Edge BEN Rising Edge Delay Time After Last BEN Falling See t5 in Timing Diagram Edge Power Supply Reset Voltage Vcc 4
10. A MOTOROLA ANALOG IC DEVICE DA more Information On This Product 9 Go to www freescale com AGC WEIGHTING FACTOR LINE VOLTAGE V AGC WEIGHTING FACTOR 10 Freescale Stsi i nductor Inc ie j i age versus Line Current Mask 60 Rago 47k 50 AGC Ratio 3 5 1 680 40 30 20 10 0 0 10 20 30 40 50 60 line LINE CURRENT mA Figure 5 AGC Weighting Factor versus Voltage Regulation Mask 1 0 0 8 0 6 Rage 100 k Gain AGC Ratio 1 2 0 4 HYS HYL 0 2 0 0 10 20 30 40 50 60 70 80 90 100 line LINE CURRENT mA Figure 7 AGC Weighting Factor versus Current Regulation Mask Rago 47k AGC Ratio 3 5 0 0 20 30 40 50 60 70 80 90 100 line LINE CURRENT mA or More Information On Go to www freescale com AGC WEIGHTING FACTOR LINE VOLTAGE V AGC WEIGHTING FACTOR Figure 4 Line Voltage versus Line Current Current Regulation Mask 60 Rago 47k 90 AGG Ratio 1 2 680 40 1 470 30 20 10 1 220k 0 0 10 20 30 40 50 60 line LINE CURRENT mA Figure 6 AGC Weighting Factor versus Voltage Retulation Mask 1 0 0 8 RAG
11. B Sidetone Switchover Enabled No AGC Gain Range Sidetone Switchover Enabled AGC Range of 6 0 dB only HYS Input Active HYL Muted No AGC Gain Range only HYS Input Active HYL Muted The ratio between start and stop current for the AGC curves is programmable for both voltage and current regulation mode AGC Ratio lAGCstart Selected uA uA Voltage Regu lation AGC Ratio 1 3 Voltage Regu lation AGC Ratio 1 2 The relation between line current and lstart and lstop is given by _ PAGC linestart Rg AGCstart l _ PAGC linestop AGCstop Figures 5 6 7 and 8 show the AGC curves for both voltage regulation and current regulation In current regulation the start point for the AGC curves is coupled to the knee point of the dc characteristic or knee lAGCstart LOGIC OUTPUT DRIVERS The MC34016 is equipped with three logic outputs meant to interface to the front end of a telephone The outputs can be controlled via the serial bus interface As shown in the characteristics the logic outputs are capable of sourcing at least 1 0 mA and sinking at least 5 0 mA Output HKSW Output HKSW is dedicated to drive the hookswitch With HKSW low the line is opened via Q2 and Q3 and automatically switches off the line driver transistor Q1 This feature guarantees fast dc settling after line breaks occurring during pulse dialing Outputs Out1 and Out2 Outputs
12. C 100 k 0 6 Ratio 1 3 Gain 0 4 HYS 0 2 0 0 10 20 30 40 50 60 70 80 90 100 line LINE CURRENT mA Figure 8 AGC Weighting Factor versus Currrent Regulation Mask RAGC 47 AGC Ratio 1 2 0 0 20 30 40 50 60 70 80 90 100 line LINE CURRENT mA STO ROLA ANALOG IC DEVICE DATA Freescale Stsi i nductor Inc Figure 9 Test Diagram 8 MC34016e Ev RHS1 ER RDC1 L OStab RSET 18k 18k 470k 100 p 600 52 RHL2 A A A eVWV 3 0k 3 0k RR 10k Qt MC34016 8 i Ka MJE340 BG VTx l Serial Bus Interface Out Out2 4 R R C lj Pre AAA IW 29 CM ESSET 4 ine CD vac Viine From MPU MOTOROLA ANALOG IC DEVICE S Inrormation 1 ns p 11 Freescale Stsi i nductor Inc Figure 10 Typical Application with Passive Impedance and Voltage Regulation 28 MC34016 ER MESES bd rum RSET 100p 600 RINT CRyq 0
13. Freescale Semiconductor Inc order this document by MC34016 D 2 i8 M 340164 Av Fs Cordless Universal Telephone Interface The MC34016 is a telephone line interface meant for use in cordless telephone base stations for CTO CT1 CT2 and DECT The circuit forms the interface towards the telephone line and performs all speech and line interface functions like dc and ac line termination 2 4 wire conversion automatic gain control and hookswitch control Adjustment of transmission parameters is accomplished by two 8 bit registers accessible via the integrated serial bus interface and by external components DC Masks for Voltage and Current Regulation Supports Passive or Active AC Set Impedance Applications Double Wheatstone Bridge Sidetone Architecture Symmetrical Inputs and Outputs with Large Signal Swing Capability Gain Setting and Mute Function for and Rx Amplifiers Very Low Noise Performance Serial Bus Interface SPI Compatible Operation from 3 0 to 5 5 V FEATURES Line Driver Architecture Two DC Masks for Voltage Regulation Two DC Masks for Current Regulation Passive or Active Set Impedance Adjustment Double Wheatstone Bridge Architecture Automatic Gain Control Function Transmit Channel Symmetrical Inputs Capable of Handling Large Voltage Swing Gain Select Option via Serial Bus Interface Transmit Mute Function Programmable via Bus Large Voltage Swing Capability at the Telephone Line Recei
14. OTOROLA ANALOG IC DEVICE DATA Go tos www freescale com Freescale St amp et nductor Inc 3401641 hy OUTLINE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 738 03 ISSUE E NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 2 CONTROLLING DIMENSION INCH 3 DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL DIMENSION B DOES NOT INCLUDE MOLD IL FLASH INCHES MILLIMETERS MIN MIN 1 010 1 070 25 66 27 17 0 240 0 260 6 10 6 60 0 150 0 180 3 81 4 57 0 015 0 022 0 39 0 55 BSC 1 27 BSC 0 070 177 BSC 54 BSC 0 015 0 38 0 140 J 3 55 BSC 62 BSC 15 15 0 040 1 01 g TS SEATING PLANE el 22 M H4 J 20 PL D 20 PL lt gt 0 25 0 010 0 25 0 010 gt lt 9 DW SUFFIX PLASTIC PACKAGE CASE 751D 04 ISSUE E NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 20 CONTROLLING DIMENSION MILLIMETER DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION MAXIMUM MOLD PROTRUSION 0 150 0 006 PER SIDE DIMENSION D DOES NOT INCLUDE e 0 010 0 25 DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 13 0 005 TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION 1 bits 20x
15. Outi and Out2 may be used for any logic function such as control of an earth switch and or a shunt wire SERIAL BUS INTERFACE The serial interface of the MC34016 enables a simple three wire connection to a micro controller Timing Times t1 t2 t3 t4 and t5 are specified in the electrical characteristics With BEN high data can be clocked into the serial port by using Data and lines On the rising edge of the CIk the data enters the MC34016 The last 8 bits of data entered are shifted into the registers when BEN is forced low With BEN low the serial port of the MC34016 is disabled BEN must be kept low until the next register update is needed Data should be written by entering the most significant bit first Bit 7 and the least significant bit Bit last 1 0 Current Regu 21 42 lation AGC With BEN low the Data lines may be used to Ratio 1 2 control other devices in the application 1 1 Current Regu 31 52 lation AGC Ratio 3 5 8 REESE TUM ROLA ANALOG IC DEVICE DATA Go to www freescale com Freescale Stsi i nductor Inc Timing Diagram A M 34016 4H Av Fs t2 t3 t4 t5 Registers Register 2 Bit 7 1 The MC34016 is equipped with two 8 bit registers which Bit Function Operation Default are selected by the value of the most significant bit Bit 7 If the supply voltage of the MC34016 drops below 2 5 V all 0 0 AGC Range 6
16. et impedance RDpC1 can be made complex In such case the dc mask can be adjusted with the dc value of and the set impedance can be adjusted with the ac value of RDC1 An application with an active set impedance is interesting particularly in countries like France where with the dc current regulation mask rather high line voltages can be reached With a passive set impedance this would result in a high cost for capacitor CSET TRANSMIT CHANNEL Inputs The inputs 2 are designed to handle large signal levels of up to 3 0 dBm The input impedance for both 1 and equals 30 The inputs are designed for symmetrical as well as asymmetrical use In asymmetrical drive one input can be tied to Gnd via an external capacitor Gain The gain from inputs and Ty to the line is dependent on the set impedance the line load impedance and dc slope resistor Rg in the following way xZ 1__ SET EZ TX 6x Rg 25 line line With ZSET 600 600 Q and Rs 50 Q the gain equals 0 dB By setting Bit 4 of Register 2 to 1 the gain is raised by 6 0 dB Outputs In order to transmit signals to the line the output stage of the MC34016 line driver modulates the zener previously described To guarantee stability of the output stage capacitor CSTB of 100 pF is required SIDETONE The MC34016 is equipped with a double Wheatstone bridge architecture to optimize sidetone One s
17. he line to the outputs and 2 for short lines and passive impedance equals R14 Apy 7 6 x RX R14 Zuys For active impedance it follows R1xZ R14 HYS Apy 7 6 x x 1 5 RX R14 Zuys R14 x In these relations R14 is the resistor R14 in parallel with the input impedance at HYS of 30 kO The gain for long lines can be derived by replacing ZHYs and R14 by ZHyL MOTOROLA ANALOG IC DEVICE DA mere Information On This Product 7 Go to www freescale com Freescale St i nductor Inc and R17 With R14 3 0 and ZHys 18 the receive in equal Bf e ive impedance application SEC MEG A010 Ga Outputs The outputs Ry4 and Ry of the receive channel have an output impedance of 150 Q and are designed to drive a 10 KQ resistive load or a 47 nF capacitive load with a 3 5 Vpp swing AUTOMATIC GAIN CONTROL The automatic gain control function AGC controls the transmit and receive gains and the switchover for the sidetone networks for short and long lines according to the line current which represents line length The effect of AGC on the transmit and receive amplifiers is 6 0 dB at default and it can be disabled via the serial bus The switchover for the sidetone networks tracks the AGC curves for the transmit and receive amplifier gain This feature can also be disabled via the serial bus Bit 0 Reg 2 AGC Range Description AGC Gain Range of 6 0 d
18. idetone network is used for short lines and one for long lines Switchover between both networks is dependent on line current and is described in the automatic gain control section Different sidetone equations apply depending on whether a passive or an active set impedance is set Sidetone Cancellation with Passive Set Impedance In a passive set impedance application the set impedance is a part of the equations for optimum sidetone For short lines optimum cancellation occurs if _ Pus2 ser 2 HS1 Rs ZsEr Zlineshort with Zlineshort impedance of a short telephone line and for long lines _ SET ZSET linelong with Zlinelong impedance of a long telephone line Z lineshort xZ Z Z linelong Sidetone Cancellation with Active Set Impedance In the active set impedance application the set impedance does not appear in the equations for optimum sidetone cancellation as it does in the passive application For short lines optimum cancellation occurs if R _ _ HS2 2 51 Rg X Z neshort and for long lines R HL2 ZUL Rs Zlinelong RECEIVE CHANNEL Inputs The inputs HYS and HYL have an input resistance of 30 and can handle signals up to 800 mVpp This corresponds to a signal at the telephone line of about 8 0 dBm in the typical application The switchover from HYS to HYL is dependent on line current and described in the automatic gain control section Gain The overall gain from t
19. or an active set impedance can be obtained Passive Set Impedance In this application the set impedance is formed by the ac impedance of the circuit itself in parallel with resistor RSET and capacitor CSET An equivalent network equals Rpct E RSET Rpc1 x ey x Rs 2 n CMT T CSET ROLA ANALOG IC DEVICE DATA Freescale Stsi i nductor Inc With the component values of the typical application the es 3416 Gtatogig2 4 and RDC1 equals 470 ir the audio range ot 300 3400 Hz these components form a fairly large parallel impedance to RSET and CSET Therefore the set impedance is mainly determined by the passive network RSET and CsET In the typical application RSET is 600 but it can easily be replaced by a complex network to obtain a complex set impedance Active Set Impedance An active set impedance can be obtained by placing a resistor between LAI and SRF as shown in Figure 11 By doing so the 34016 itself generates the ac set impedance and RSET and can be omitted An equivalent network now equals Rpc1 x Re RsRF Rs Rpc1 x CM x Rg cman Rs Ignoring the effect of the inductor and the parallel path RSRF again for audio frequencies the set impedance is now determined by Raa Poci SRF With Rs 250 Q and RpC1 470 kQ Rspr should be 43 kQ to obtain a 600 Q set impedance To obtain a complex s
20. ve Channel Double Sidetone Architecture for Optimum Line Matching Symmetrical Outputs Capable of Producing High Voltage Swing Gain Select Option via Serial Bus Interface Receive Mute Function Programmable via Serial Bus Serial Bus Interface 3 Wire Connection to Microcontroller One Programmable Output Meant for Driving a Hookswitch Two Programmable Outputs Capable of Driving Low Ohmic Loads Two 8 Bit Registers for Parameter Adjustment MC34016 CORDLESS UNIVERSAL TELEPHONE INTERFACE SEMICONDUCTOR TECHNICAL DATA P SUFFIX PLASTIC PACKAGE CASE 738 1 DW SUFFIX PLASTIC PACKAGE CASE 751D Clk Data Out2 Stab Gnd HKSW Outi HYL PIN CONNECTIONS BEN LAO LAI SRF AGC Tx2 Ry2 HYS Top View ORDERING INFORMATION Operating Device Temperature Range Package MC34016P TA 20 to 70 C MC34016DW 50 20 Motorola Inc 1996 Rev 1 For More Information On This Product Go to www freescale com Freescale Stsi i nductor Inc Representative Block Diagram zril MC34016 BEI S TW VV OF Rx Outputs Line MC34016 Driver Hook Ty gt 00 Inputs Tyo Switch Serial Bus Interface B Ring 5 0 V
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MOTOROLA MC34016 Data Sheet