NATIONAL SEMICONDUCTOR LP38691-ADJ/LP38693-ADJ Manual
Contents
1. EE po Serial Digital Interface SDI www national com sdi Temperature Sensors www national com tempsensors Wireless PLL VCO www national com wireless THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION NATIONAL PRODUCTS NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE NO LICENSE WHETHER EXPRESS IMPLIED ARISING BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL S PRODUCT WARRANTY EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS BUYERS SHOULD PROVIDE ADEQUATE DESIGN TESTING AND OPERATING SAFEGUARDS EXCEPT AS PROVIDED IN NATIONAL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS NATIONAL ASSUMES NO LIABILITY WHATSOEVER AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY2. 5 1 0 0 5 0 0 00 05 10 15 20 25 30 20126858 MIN V y VS lour 20126856 Vout V Vororour mV Vour VS Vin Vour 1 80V 1000 T 25 C Vin V 20126859 Dropout Voltage vs loy Vour 1 8V 20126857 www national com av 698Ed1 AV 1698 d1 LP38691 ADJ LP38693 ADJ Application Hints EXTERNAL CAPACITORS Like any low dropout regulator external capacitors are re quired to assure stability These capacitors must be correctly selected for proper performance INPUT CAPACITOR An input capacitor of at least 1uF is re quired ceramic recommended The capacitor must be lo cated not more than one centimeter from the input pin and returned to a clean analog ground OUTPUT CAPACITOR An output capacitor is required for loop stability It must be located less than 1 centimeter from the device and connected directly to the output and ground pins using traces which have no other currents flowing through them The minimum amount of output capacitance that can be used for stable operation is 1uF Ceramic capacitors are recom mended the LP38691 3 ADJ was designed for use with ultra low ESR capacitors The LP38691 3 ADJ is stable with any output capacitor ESR between zero and 100 Ohms SETTING THE OUTPUT VOLTAGE The output voltage is set using the external resistors R1 and
3. Cy Cour 10 pF enable pin is tied to Vy LP38693 ADJ only Vo 1 25V Vn 2 7V 10mA Noise vs Frequency S 27 o 2 10 100 1k 10k 100k FREQUENCY Hz 20126835 Noise vs Frequency N Lu a 2 10k 100k FREQUENCY Hz 20126837 Ripple Rejection T Q H O LLI T ra E rz Em 10 100 1k 10k 100k FREQUENCY Hz 20126819 NOISE uV VHz RIPPLE REJECTION dB RIPPLE REJECTION dB 1 0 0 8 0 6 0 4 0 2 0 0 Noise vs Frequency Cour 10 10 100 1k 10k FREQUENCY Hz Ripple Rejection 100k 20126836 L 1 Vy DC 3 25V AC 1V p p 100 1k 10k FREQUENCY Hz Ripple Rejection 100k 20126817 in DC 3 25V in AC 1V p p 10k FREQUENCY Hz 20126821 www national com Veer V
4. R2 see Typical Ap plication Circuit The output voltage will be given by the equation Vout X 1 R1 R2 Because the part has a minimum load current requirement of 100 pA it is recommended that R2 always be 12k Ohms or less to provide adequate loading Even if a minimum load is always provided by other means it is not recommended that very high value resistors be used for R1 and R2 because it can make the ADJ node susceptible to noise pickup A max imum Ohmic value of 100k is recommended for R2 to prevent this from occurring ENABLE PIN LP38693 ADJ only The LP38693 ADJ has an enable pin which turns the regulator output on and off Pulling the enable pin down to a logic low will turn the part off The voltage the pin has to be pulled up to in order to assure the part is on depends on input voltage refer to Electrical Characteristics section This pin should be tied to Viv if the enable function is not used FOLDBACK CURRENT LIMITING Foldback current limiting is built into the LP38691 3 ADJ which reduces the amount of output current the part can deliver as the output voltage is reduced The amount of load current is dependent on the dif ferential voltage between Vi and Typically when this differential voltage exceeds 5V the load current will limit at about 350 mA When the Vi Voyr differential is reduced be low 4V load current is limited to about 850 mA SELECTING A CAPACITOR Itis important to note
5. disspation causes the junction temperature to exceed specified limits the device will go into thermal shutdown Note 3 ESD is tested using the human body model which is a 100pF capacitor discharged through a 1 5k resistor into each pin Note 4 Typical numbers represent the most likely parametric norm for 25 C operation Note 5 If used in a dual supply system where the regulator load is returned to a negative supply the output pin must be diode clamped to ground Note 6 Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage Note 7 Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1mA to full load Note 8 Dropout voltage is defined as the minimum input to output differential required to maintain the output within 100mV of nominal value www national com 4 Block Diagrams Vin MOSFET ENABLE NC o LOGIC FOLDBACK CURRENT O Vout LIMITING THERMAL 1 25 SHUTDOWN REFERENCE O ADJ GND O 20126806 FIGURE 1 LP38691 ADJ Functional Diagram LLP MOSFET DRIVER ENABLE FOLDBACK CURRENT LIMITING THERMAL 1 25 SHUTDOWN REFERENCE FIGURE 2 LP38693 ADJ Functional Diagram SOT 223 LLP 20126807 www national com av 698Ed1 AV 1698 d1 LP38691 ADJ LP38693 ADJ Typical Performance Characteristics unless otherwise specified T 25 C
6. pins so there is no voltage drop in series with the input and output capacitors RFI EMI SUSCEPTIBILITY RFI radio frequency interference and EMI electromagnetic interference can degrade any integrated circuit s perfor mance because of the small dimensions of the geometries inside the device In applications where circuit sources are present which generate signals with significant high frequen cy energy content 1 MHz care must be taken to ensure that this does not affect the IC regulator If RFI EMI noise is present on the input side of the regulator such as applications where the input source comes from the output of a switching regulator good ceramic bypass capac itors must be used at the input pin of the IC If a load is connected to the IC output which switches at high speed such as a clock the high frequency current pulses required by the load must be supplied by the capacitors on the IC output Since the bandwidth of the regulator loop is less than 100 kHz the control circuitry cannot respond to load changes above that frequency This means the effective out put impedance of the IC at frequencies above 100 kHz is determined only by the output capacitor s www national com 10 In applications where the load is switching at high speed the output of the IC may need RF isolation from the load It is recommended that some inductance be placed between the output capacitor and the load and good RF bypass cap
7. that capacitance tolerance and variation with temperature must be taken into consideration when se lecting a capacitor so that the minimum required amount of capacitance is provided over the full operating temperature range Capacitor Characteristics CERAMIC For values of capacitance in the 10 to 100 uF range ceramics are usually larger and more costly than tan talums but give superior AC performance for bypassing high frequency noise because of very low ESR typically less than 10 mQ However some dielectric types do not have good capacitance characteristics as a function of voltage and tem perature Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage A typical Z5U or Y5V capacitor can lose 60 of its rated capacitance with half of the rated voltage applied to it The Z5U and Y5V also exhibit a severe temperature effect losing more than 50 of nominal capac itance at high and low limits of the temperature range X7R and X5R dielectric ceramic capacitors are strongly rec ommended if ceramics are used as they typically maintain a capacitance range within 20 of nominal over full operating ratings of temperature and voltage Of course they are typi cally larger and more costly than Z5U Y5U types for a given voltage and capacitance TANTALUM Solid Tantalum capacitors have good temper ature stability a high quality Tantalum will typically show a capacitance value that varies less than
8. 10 1596 across the full temperature range of 40 C to 125 C ESR will vary only about 2X going from the high to low temperature limits The increasing ESR at lower temperatures can cause oscil lations when marginal quality capacitors are used if the ESR of the capacitor is near the upper limit of the stability range at room temperature PCB LAYOUT Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops The in put and output capacitors must be directly connected to the input output and ground pins of the regulator using traces which do not have other currents flowing in them Kelvin con nect The best way to do this is to lay out CiN and Cour near the device with short traces to the Vy and ground pins The regulator ground pin should be connected to the external cir cuit ground so that the regulator and its capacitors have a single point ground It should be noted that stability problems have been seen in applications where vias to an internal ground plane were used at the ground points of the IC and the input and output capacitors This was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane Using a single point ground technique for the regulator and it s capacitors fixed the problem Since high current flows through the traces going into Vy and coming from Kelvin connect the capacitor leads to these
9. 38693 ADJ Applications m Hard Disk Drives m Notebook Computers m Battery Powered Devices m Portable Instrumentation 20126801 Vour 20126802 X 1 R1 R2 2008 National Semiconductor Corporation 201268 www national com sJ0312ede 3ndin Q lqesSsinhno a1qeqsnipy siojzeinbay 1 SOIND 3nodouq MOT av eeoased 1 aV T698Ed1 LP38691 ADJ LP38693 ADJ Connection Diagrams GND Ven ADJ Vin 20126803 SOT 223 Top View LP38693MP ADJ 20126804 20126805 6 Lead LLP Bottom View 6 Lead LLP Bottom View LP38691SD ADJ LP38693SD ADJ Pin Descriptions Description This is the input supply voltage to the regulator For LLP package devices both Vi pins must be tied together for full current operation 250mA maximum per pin as the heat sink when the large ground pad is soldered down to a copper plane Regulated output voltage The enable pin allows the part to be turned ON and OFF by pulling this pin high or low The adjust pin is used to set the regulated output voltage by connecting it to the external resistors R1 and R2 see Typical Application Circuit Ordering Information 6 Lead LLP SDEO6A 4500 Units Tape and Reel SOT 223 MP05A 2000 Units Tape and Reel www national com 2 Absolute Maximum Ratings Note 1 V max All pins with respect to GND 0 3V to 12V lour Internally Limited If Mili
10. National Semiconductor LP38691 ADJ LP38693 AD Adjustable Output General Description The LP38691 3 ADJ low dropout CMOS linear regulators pro vide 2 0 precision reference voltage extremely low dropout voltage 250mV 500mA load current Vour 5V and ex cellent AC performance utilizing ultra low ESR ceramic output capacitors The low thermal resistance of the LLP and SOT 223 pack ages allow the full operating current to be used even in high ambient temperature environments The use of a PMOS power transistor means that no DC base drive current is required to bias it allowing ground pin current to remain below 100 regardless of load current input volt age or operating temperature Dropout Voltage 250 mV typ 500 typ 5V out Ground Pin Current 55 yA typ at full load Adjust Pin Voltage 2 0 25 C accuracy Typical Application Circuits Note Minimum value required for stability LP38691 ADJ October 24 2008 500mA Low Dropout CMOS Linear Regulators with Stable with Ceramic Output Capacitors Features Output voltage range of 1 25V 9V 2 0 adjust pin voltage accuracy 25 C Low dropout voltage 250mV 500mA typ 5V out Wide input voltage range 2 7V to 10V Precision trimmed bandgap reference Guaranteed specs for 40 C to 125 C 1pA off state quiescent current Thermal overload protection Foldback current limiting SOT 223 and 6 Lead LLP packages Enable pin LP
11. OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein Life support devices or systems are devices which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation All other brand or product names may be trademarks or registered trademarks of their respective holders Copyright 2008 National Semiconductor Corporation For the most current product information visit us at www national com National Semiconductor National Semiconductor Europe National Semiconductor Asia National Semiconductor J apan Americas Technical Technical Su
12. S Temperature 0 4 0 2 DEVIATION TEMPERATURE C 20126830 Line Transient Response AVour mV z gt 200 us DIV 20126824 Line Transient Response AVour mV 100 us DIV 20126826 Line Transient Response AVoyr mV 200 us DIV Line Transient Response AVour mV 200 us DIV Line Transient Response AVoyr mV 40 us DIV 20126823 20126825 20126827 www national com A V 698 d1 AV 1698 d1 LP38691 ADJ LP38693 ADJ Line Transient Response AVour mV 100 us DIV 20126828 Load Transient Response AV aur mV 10 us DIV 20126844 Load Regulation vs Temperature 1 0 15 lt gt 20 2 _ lt E 25 gt lt 3 0 3 5 50 25 0 25 50 75 100 125 TEMPERATURE C 20126854 Load Transient Response 40 us DIV 20126842 Enable Voltage vs Temperature 2 3 2 1 Ven 50 25 0 25 50 75 100 125 TEMPERATURE C 20126853 Line Regulation vs Temperature AV gy AV y V TEMPERATURE C 20126855 www national com Vout V MIN Vy V Vour VS Vin Vor 1 25V 3 0 1000 T 25 C 2 5 2 0 1
13. acitors be placed directly across the load PCB layout is also critical in high noise environments since RFI EMI is easily radiated directly into PC traces Noisy cir cuitry should be isolated from clean circuits where possible and grounded through a separate path At MHz frequencies ground planes begin to look inductive and RFI EMI can cause ground bounce across the ground plane In multi layer PCB applications care should be taken in layout so that noisy power and ground planes do not radiate directly into adjacent layers which carry analog power and ground OUTPUT NOISE Noise is specified in two ways Spot Noise or Output Noise density is the RMS sum of all noise sources measured at the regulator output at a specific frequency measured with 1Hz bandwidth This type of noise is usually plotted on a curve as a function of frequency Total Output Noise or Broad Band Noise is the RMS sum of spot noise over a specified bandwidth usually several decades of frequencies Attention should be paid to the units of measurement Spot noise is measured in units uV root Hz or nV root Hz and total output noise is measured pV rms The primary source of noise in low dropout regulators is the internal reference Noise can be reduced in two ways by in creasing the transistor area or by increasing the current drawn by the internal reference Increasing the area will decrease the chance of fitting the die into a smaller package Inc
14. n a 3 www national com A V 698 d1 AV 1698 d1 LP38691 ADJ LP38693 ADJ Parameter Comdions min ive Noea Max unis Output Noise BW 10Hz to 10kHz Vo 3 3V Output Leakage Current Vo Vo NOM 1V 10V H Enable Voltage LP38693 ADJ Output OFF a ee E ON Vin 10V Enable Pin Leakage LP38693 Vey OV or 10V Vin 10V 001 ADJ Only Note 1 Absolute maximum ratings indicate limits beyond which damage to the component may occur Operating ratings indicate conditions for which the device is intended to be functional but do not guarantee specific performance limits For guaranteed specifications see Electrical Characteristics Specifications do not apply when operating the device outside of its rated operating conditions Note 2 At elevated temperatures device power dissipation must be derated based on package thermal resistance and heatsink values if a heatsink is used The junction to ambient thermal resistance 0 4 for the SOT 223 is approximately 125 C W for a PC board mounting with the device soldered down to minimum copper area less than 0 1 square inch If one square inch of copper is used as heat dissipator for the SOT 223 the drops to approximately 70 C W The 0 4 values for the LLP package are also dependent on trace area copper thickness and the number of thermal vias used refer to application note AN 1187 If power
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16. reasing the current drawn by the internal reference increases the total supply current ground pin current 11 www national com A V 698 d1 AV 1698 d1 LP38691 ADJ LP38693 ADJ Physical Dimensions inches millimeters unless otherwise noted DIMENSIONS ARE IN MILLIMETERS DIMENSION IN FOR REFERENCE ONLY 6X 0 6 IL x 0 95 RECOMMENDED LAND PATTERN PIN 1 INDEX AREA x A 1 3 45 X 0 25 LI udo mm quo 6X 0 420 1 y rra 6 9 3540 05 be 350 4 P La 0 1 lt 49 86 9 95 94 SDE06A Rev 6 lead LLP Package NS Package Number SDEO6A 3 040 1 SYMM fo i 5 a I 1 6 3 1 6 9613 33 1 ES 1 5 TYP E SYMM gt i 1 TYP 1 1 4 mt LAND PATTERN RECOMMENDATION A 6 540 2 R0 1520 05 TYP a 1 25 SOT 223 Package NS Package Number MP05A www national com 12 LP38691 ADJ LP38693 ADJ Notes www national com 13 p 5 8 A t t ear Regulators wi OutputStable with Ceramic Output Ca LP38691 ADJ LP38693 ADJ 500mA Low Dropout CMOS L Notes For more National Semiconductor product information and proven design tools visit the following Web sites at www national com amplifiers cond 7
17. tary Aerospace specified devices are required o please contactthe National Semiconductor Sales Office Junction Temperature 40 C to 150 C Distributors for availability and specifications Operating Ratings Storage Temperature Range 65 to 150 C Lead Temp Soldering 5 seconds 260 C Vin Supply Voltage 2 7V to 10V ESD Rating Note 3 2kV Operating Junction 40 to 125 C Power Dissipation Note 2 Internally Limited Temperature Range Electrical Characteristics Limits in standard typeface are for T 25 C and limits in boldface type apply over the full operating temperature range Unless otherwise specified Vin Voyr 1V Cin Cour 10 pF 10mA Min Max limits are guaranteed through testing statistical correlation or design symbol Canarsie Wer Unis VApJ ADJ Pin Voltage 3 2V lt Vy S 10V 100 pA lt l lt 0 5A in Output Voltage Line Regulation 0 5 lt V lt 10V SIN Note 6 25mA AV Al Output Voltage Load Regulation 1 mA lt lt 0 5A SUN Note 7 Vin Vo 1V B 80 430 65 Vn Dropout Voltage Note 8 330 mV 45 250 I 0 la Quiescent Current 10V 100 HA 05A r lt 0 001 1 LP38693 ADJ Only I MIN Minimum Load Current lt 4V o lad les Foldback Current Limit Vin Vo gt 5V v la l 850 m 120Hz Ripple Junction Temp C Junction Temp ERE Ee
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NATIONAL SEMICONDUCTOR LP38691 ADJ/LP38693 ADJ Manual