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MICROCHIP PIC12C5XX Manual

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1. INT x ml A p Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Pitch 0 050 1 27 Number of Pins n 8 8 Overall Pack Height A 0 054 0 061 0 069 1 37 1 56 1 75 Shoulder Height A1 0 027 0 035 0 044 0 69 0 90 1 11 Standoff A2 0 004 0 007 0 010 0 10 0 18 0 25 Molded Package Length pt 0 189 0 193 0 196 4 80 4 89 4 98 Molded Package Width Et 0 150 0 154 0 157 3 81 3 90 3 99 Outside Dimension E1 0 229 0 237 0 244 5 82 6 01 6 20 Chamfer Distance X 0 010 0 015 0 020 0 25 0 38 0 51 Shoulder Radius R1 0 005 0 005 0 010 0 13 0 13 0 25 Gull Wing Radius R2 0 005 0 005 0 010 0 13 0 13 0 25 Foot Length L 0 011 0 016 0 021 0 28 0 41 0 53 Foot Angle 0 4 8 0 4 8 Radius Centerline L1 0 000 0 005 0 010 0 00 0 13 0 25 Lead Thickness c 0 008 0 009 0 010 0 19 0 22 0 25 Lower Lead Width Bt 0 014 0 017 0 020 0 36 0 43 0 51 Mold Draft Angle Top a 0 12 15 0 12 15 Mold Draft Angle Bottom B 0 12 15 0 12 15 i Controlling Parameter Dimension B does not include dam bar protrusions Dam bar protrusions shall not exceed 0 003 0 076 mm per side or 0 006 0 152 mm more than dimension B Dimensions D and E do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0 010 0 254 mm p
2. TABLE 5 1 SUMMARY OF PORT REGISTERS Value on Power On Value on Address Name Bit 7 Bit 6 Bit 5 6114 Bit3 Bit2 Bit1 6110 Reset All Other Resets N A TRIS I O control registers 11 1111 11 1111 N A OPTION GPWU GPPU TOCS TOSE PSA PS2 PS1 PSO 1111 1111 1111 1111 03H STATUS GPWUF PAO TO Z DC C 0001 1xxx q00q quuu 1 06h GPIO GP5 GP4 GP3 GP2 GP1 GPO xx xxxx uu uuuu Legend Shaded cells not used by Port Registers read as 0 unimplemented read as x unknown u unchanged g see tables in Section 7 7 for possible values Note 1 If reset was due to wake up on change then bit 7 1 All other resets will cause bit 7 0 1998 Microchip Technology Inc DS40139D page 21 PIC12C5XX 5 4 O Programming Considerations 5 4 1 BI DIRECTIONAL I O PORTS Some instructions operate internally as read followed by write operations The BCF and BSF instructions for example read the entire port into the CPU execute the bit operation and re write the result Caution must be used when these instructions are applied to a port where one or more pins are used as input outputs For example a BSF operation on 0115 of GPIO will cause all eight bits of GPIO to be read into the CPU bit5 to be set and the GPIO value to be written to the output latches If another bit of GPIO is used as a bi directional I O pin say bitO and it is defined as
3. 400 300 DS40139D page 92 Preliminary m Typ 25 C Max 125 C x 85 C 200 R Min 40 C 100 2 4 5 6 7 VDD Volts 1998 Microchip Technolooy Inc PIC12C5XX FIGURE 13 5 loH vs VOH VDD 2 5 V 0 IOH mA 20 25 1 5 2 0 FIGURE 13 6 2 5 VOH Volts 3 0 IOH vs VOH VDD 3 5 V 3 5 FIGURE 13 7 loL vs VOL VDD 2 5 V IOL mA 0 N oh 1 5 2 0 2 5 VOH Volts 3 0 3 5 loL mA 35 30 25 780 2 15 V 0 FIGURE 13 8 35 500 0m 750 0m 1 0 VoL Volts loL vs VOL VDD 3 5 V 30 25 20 15 10 500 0m 750 0m 1 0 VoL Volts 1998 Microchip Technology Inc Preliminary DS40139D page 93 PIC12C5XX NP S A E E k E E h r 1 C I i EE DS40139D page 94 Preliminary 1998 Microchip Technology Inc PIC12C5XX 14 0 PACKAGING INFORMATION 14 1 Package Marking Information 8 Lead PDIP 300 mil Example XXXXXXXX 12C508A XXXXXCDE 041 PSAZ A AABB AN 9825 8 Lead SOIC 150 mil Example XXXXXXX C508A QN XXXX Q 9825 8 Lead SOIC 208 mil
4. 1998 Microchip Technology Inc DS40139D page 39 PIC12C5XX TABLE 8 2 INSTRUCTION SET SUMMARY Mnemonic 12 Bit Opcode Status Operands Description Cycles MSb LSb Affected Notes ADDWF f d Add W and f 1 0001 114f ffff 0002 1 2 4 ANDWF f d AND W with f 1 0001 01df ffff Z 2 4 CLRF f Clear f 1 0000 O11f ffff Z 4 CLRW Clear W 1 0000 0100 0000 Z COMF f d Complement f 1 0010 01df ffff 2 DECF f d Decrement f 1 0000 11df ffff Z 2 4 DECFSZ 10 Decrement f Skip if 0 1 2 0010 11d ffff None 2 4 INCF f d Increment f 1 0010 10df ffff 2 2 4 INCFSZ 10 Increment f Skip if 0 1 2 0011 1iidf ffff None 2 4 IORWF f d Inclusive OR W with f 1 0001 00df ffff Z 24 MOVF f d Move f 1 0010 00df ffff Z 24 MOVWF f Move W to f 1 0000 001 ffff None 1 4 NOP No Operation 1 0000 0000 0000 None RLF f d Rotate left f through Carry 1 0011 01df ffff C 2 4 RRF f d Rotate right f through Carry 1 0011 00df ffff C 2 4 SUBWF f d Subtract W from f 1 0000 104f ffff 0002 1 2 4 SWAPF f d Swap f 1 0011 10df ffff None 2 4 XORWF f d Exclusive ORW with f 1 0001 10df ffff Z 2 4 BIT ORIENTED FILE REGISTER OPERATIONS BCF f b Bit Clear f 1 0100 bbbf ffff None 2 4 BSF f b Bit Set f 1 0101 bbbf ffff None 2 4 BTFSC fb Bit Test f Skip if Clear 1 2 0110 bbbf ffff None BTFSS f b Bit Test f Skip if Set 1 2 0111 bbbf ffff None LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL k Cal
5. Dimensions D and E do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0 010 0 254 mm per side or 0 020 0 508 mm more than dimensions D or E DS40139D page 98 1998 Microchip Technology lnc PIC12C5XX Package Type K04 084 8 Lead Ceramic Side Brazed Dual In line with Window JW 300 mil i T n Y U i i ci Li A2 i c B1 p r eB B Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX PCB Row Spacing 0 300 7 62 Number of Pins n 8 8 Pitch p 0 098 0 100 0 102 2 49 2 54 2 59 Lower Lead Width B 0 016 0 018 0 020 0 41 0 46 0 51 Upper Lead Width B1 0 050 0 055 0 060 1 27 1 40 1 52 Lead Thickness c 0 008 0 010 0 012 0 20 0 25 0 30 Top to Seating Plane A 0 145 0 165 4 19 Top of Body to Seating Plane Base to Seating Plane 0 045 0 64 0 89 1 14 Tip to Seating Plane 0 150 3 30 3 56 3 81 Package Length 0 530 12 95 13 21 13 46 Package Width 0 300 7 11 7 37 7 62 Overall Row Spacing 0 365 7 87 8 57 9 27 Window Diameter 0 171 4 09 4 22 4 34 Lid Length 0 460 11 18 11 43 11 68 Lid Width 0 280 6 60 6 86 7 11 Controlling Parameter ES OSO 1998 Microchip Technology Inc DS40139D pag
6. 11 E _ I i D L J 2 a d OI 1 R L c I B B1 4 p eB B m a Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX PCB Row Spacing 0 300 7 62 Number of Pins n 8 8 Pitch 0 100 2 54 Lower Lead Width 0 018 0 022 0 36 0 46 0 56 Upper Lead Width 0 060 0 065 1 40 1 52 1 65 Shoulder Radius 0 005 0 010 0 00 0 13 0 25 Lead Thickness 0 012 0 015 0 20 0 29 0 38 Top to Seating Plane 0 150 0 160 3 56 3 81 4 06 Top of Lead to Seating Plane 0 080 0 100 1 52 2 03 2 54 Base to Seating Plane 0 020 0 035 0 13 0 51 0 89 Tip to Seating Plane 0 130 0 140 3 05 3 30 3 56 Package Length 0 370 0 385 9 02 9 40 9 78 Molded Package Width 0 250 0 260 6 22 6 35 6 60 Radius to Radius Width 0 280 0 292 6 78 7 10 7 42 Overall Row Spacing 0 342 0 380 7 87 8 67 9 65 Mold Draft Angle Top 10 15 5 10 15 Mold Draft Angle Bottom 10 15 5 10 15 Controlling Parameter Dimension B1 does not include dam bar protrusions Dam bar protrusions shall not exceed 0 003 0 076 mm per side or 0 006 0 152 mm more than dimension B1 Dimensions D and E do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0 010 0 254 mm per side or 0 020 0 508 mm more than dimensions D or E DS40139D page 96 1998 Microchip Technology Inc PIC12C5XX Package Type K04 057 8 Lead Plastic Small Outline SN Narrow 150 mil
7. 32 kHz VDD 2 5V WDT disabled AIWDT VDD 2 5V Commercial VDD 2 5V Industrial IPD xD TBD These parameters are characterized but novtested Note 1 Data in the Typical Typ column is basetXor charasterization results at 25 C This data is for design guid loading oscillator type bus rate interna the current consumptic a The test condit OSC1 exte in SLEEP mode does not depend on the oscillator type Power down current is mea LEEP mode with all O pins in hi impedance state and tied to VDD or Vss 1998 Microchip Technology lnc Preliminary DS40139D page 79 PIC12C5XX 12 3 DC CHARACTERISTICS PIC12C508A 509A Commercial Industrial Extended Standard Operating Conditions unless otherwise specified Operating temperature 0 C lt TA lt 70 C commerd 40 C x TA x 85 C industria 40 C lt TA 125 C extended DC CHARACTERISTICS Section 12 2 Param Characteristic Sym Min onditions No Input Low Voltage I O ports VIL D030 with TTL buffer D031 with Schmitt Trigger buffer D032 MCLR GP2 TOCKI AN2 INT in EXTRC mode 0033 OSC1 in XT HS and LP Input High Voltage I O ports VIH D040 with TTL buffer 4 5 lt VDD lt 5 5V DO40A For VDD gt 5 5V or VDD lt 4 5V DO41 with Schmitt Trigger buffer For entire VDD range D042 MCLR GP2 TOCKI AN2 INT D042A OSC1 XT HS and LP 0043 OSC1
8. FIGURE 11 3 WDT TIMER TIME OUT PERIOD vs VDD 50 45 40 35 a 8 Max 125 C 2 25 5 Max 85 C z 20 25 85 Typ 25 C Temperature Deg C 1 5 TABLE 11 1 DYNAMIC IpD TYPICAL Min 40 C WDT ENABLED 25 C 5 3 4 5 6 7 Frequency VDD 2 5V VDD 5 5V VD Volts 4 MHz 250 NA 620 pA 4 MHz 420 LA 1 1 mA 4 MHz 251 uA 775 pA 32 KHz 7 uA 37 uA Does not include current through external R amp C i ssms2 O n qri DS40139D page 74 1998 Microchip Technology Inc PIC12C5XX FIGURE 11 4 SHORT DRT PERIOD VS VDD FIGURE 11 6 IOH vs VOH VDD 5 5 V 1000 900 O1 o o WDT period us 400 800 700 600 Max 125 C Max 85 C 300 Tul 12506 71 Min 40 C 100 2 3 4 5 6 7 VDD Volts FIGURE 11 5 loHvs VOH VDD 2 5 V 0 IOH mA 1 0 1 5 2 0 2 5 VOH Volts 10 T E zk 9 3 5 4 0 4 5 5 0 5 5 VOH Volts FIGURE 11 7 loL vs VoL VDD 2 5 V 25 20 Max 40 C 15 T E ER 9 Min 125 C 0 250 0m VoL Volts 500 0m 1 0 1998 Microchip Technol
9. The STATUS register can be the destination for any instruction as with any other register If the STATUS register is the destination for an instruction that affects the Z DC or C bits then the write to these three bits is disabled These bits are set or cleared according to the device logic Furthermore the TO and PD bits are not writable Therefore the result of an instruction with the STATUS register as destination may be different than intended For example CLRF STATUS will clear the upper three bits and set the Z bit This leaves the STATUS register as 000u uluu where u unchanged It is recommended therefore that only BCF BSF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z DC or C bits from the STATUS register For other instructions which do affect STATUS bits see Instruction Set Summary FIGURE 4 4 STATUS REGISTER ADDRESS 03h R W 0 R W 0 R W 0 R 1 R 1 R W x R W x R W x GPWUF PAO TO PD Z DC C R Readable bit bit7 6 5 4 3 2 1 bito W Writable bit n Value at POR reset bit 7 GPWUF GPIO reset bit 1 Reset due to wake up from SLEEP on pin change 0 After power up or other reset bit 6 Unimplemented bit 5 PAO Program page preselect bits 1 gt Page 1 200h 3FFh PIC12C509 A 0 Page 0 000h 1FFh PIC12C508 A and PIC12C509 A Each page is 512 bytes Using the PAO bit as a general purpos
10. 4 MHz XT osc mode DC 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 ns EXTRC osc mode 250 ns XT osc mode 5 ms LP osc mode Oscillator Period 250 ns EXTRC osc mode 250 110 000 ns XT osc mode 5 ms LP osc mode 2 Tcy Instruction Cycle Time 4Fosc 3 TosL TosH Clock in OSC1 Low or High Time 50 ns XT oscillator 2 ms LP oscillator 4 TosR TosF Clock in OSC1 Rise or Fall Time 25 ns XT oscillator 50 ns LP oscillator These parameters are characterized but not tested Note 1 Data in the Typical Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 2 All specified values are based on characterization data for that particular oscillator type under standard oper ating conditions with the device executing code Exceeding these specified limits may result in an unstable oscillator operation and or higher than expected current consumption When an external clock input is used the max cycle time limit is DC no clock for all devices 3 Instruction cycle period 10 equals four times the input oscillator time base period LE a SSS gt SS DS40139D page 66 1998 Microchip Technology Inc PIC12C5XX TABLE 10 3 CALIBRATED INTERNAL RC FREQUENCIES PIC12C508 C509 AC Characteristics Standard Operating Conditions
11. The PIC12C5XX devices have a 12 bit Program Counter PC capable of addressing a 2K x 12 program memory space Only the first 512 x 12 0000h 01FFh for the PIC12C508 A and 1K x 12 0000h 03FFh for the PIC12C509 A are physically implemented Refer to Figure 4 1 Accessing a location above these boundaries will cause a wrap around within the first 512 x 12 space PIC12C508 A or 1K x 12 space PIC12C509 A The effective reset vector is at 000h see Figure 4 1 Location 01FFh PIC12C508 A or location O3FFh PIC12C509 A contains the internal clock oscillator calibration value This value should never be overwritten FIGURE 4 1 PROGRAM MEMORY MAP User Memory Space Note 1 AND STACK FOR THE PIC12C5XX PC lt 11 0 gt CALL RETLW is Stack Level 1 Stack Level 2 Reset Vector note 1 On chip Program Memory 512 Word PIC12C508 A On chip Program Memory 1024 Word PIC12C509 A 7FFh Address 0000h becomes the effective reset vector Location 01FFh PIC12C508 A or location O3FFh PIC12C509 A contains the MoVLW XX INTERNAL RC oscil lator calibration value 1998 Microchip Technology Inc DS40139D page 13 PIC12C5XX 4 2 Data Memory Organization FIGURE 4 2 PIC12C508 A REGISTER FILE Data memory is composed of registers or bytes of MAP RAM Therefore data memory for a device is specified File Address by its register file The regist
12. column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 In EXTRC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC12C5XX be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as coming out of the pin 4 Extended operating range is Advance Information for this device 5 When configured as external reset the input leakage current is the weak pulll up current of 10mA minimum This pull up is weaker than the standard I O pull up EE DE a a muis UNE a as 1998 Microchip Technology Inc DS40139D page 63 PIC12C5XX TABLE 10 1 PULL UP RESISTOR RANGES PIC12C508 C509 VDD Volts Temperature C Min Typ Max Units GPO GP1 2 5 40 38K 42K 63K Q 25 42K 48K 63K Q 85 42K 49K 63K Q 125 50K 55K 63K Q 5 5 40 15K 17K 20K Q 25 18K 20K 23K Q 85 19K 22K 25K Q 125 22K 24K 28K Q GP3 2 5 40 285K 346K 417K Q 25 343K 414K 532K Q 85 368K 457K 532K Q 125 431K 504K 593K Q 5 5 40 247K 292K 360K Q 25 288K 341K 437K Q 85 306K 371K 448K Q 125 351K 407K 500K Q These parameters are characterized
13. MICROCHIP PIC12C5XX 8 Pin 8 Bit CMOS Microcontroller Devices included in this Data Sheet PIC12C508 PIC12C508A PIC12C509 PIC12C509A Note Throughout this data sheet PIC12C508 A refers to the PIC12C508 and PIC12C508A PIC12C509 A refers to the PIC12C509 and PIC12C509A PIC12C5XX refers to the PIC12C508 PIC12C508A PIC12C509 and PIC12C509A High Performance RISC CPU Only 33 single word instructions to learn All instructions are single cycle 1 us except for program branches which are two cycle Operating speed DC 4 MHz clock input DC 1 us instruction cycle Device EPROM RAM PIC12C508 512 x 12 25 PIC12C508A 512 x 12 25 PIC12C509 1024 x 12 41 PIC12C509A 1024 x 12 41 12 bit wide instructions 8 bit wide data path Seven special function hardware registers Two level deep hardware stack Direct indirect and relative addressing modes for data and instructions Internal 4 MHz RC oscillator with programmable calibration In circuit serial programming Peripheral Features 8 bit real time clock counter TMRO with 8 bit programmable prescaler Power On Reset POR Device Reset Timer DRT Watchdog Timer WDT with its own on chip RC oscillator for reliable operation Programmable code protection Power saving SLEEP mode Wake up from SLEEP on pin change Internal weak pull ups on I O pins Internal pull up on MCLR pin Selectable oscillator op
14. Words 1 Cycles 1 Example BCF FLAG REG 7 Before Instruction FLAG REG 0xC7 After Instruction FLAG REG 0x47 1998 Microchip Technology Inc DS40139D page 41 PIC12C5XX BSF Bit Set f Syntax label BSF fb Operands 0 lt f lt 31 O lt b lt 7 Operation 1 gt f lt b gt Status Affected None Encoding 0101 bbbf ffff Description Bit b in register f is set Words 1 Cycles 1 Example BSF FLAG REG 7 Before Instruction FLAG REG 0x0A After Instruction FLAG REG 0x8A BTFSC Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Bit Test f Skip if Clear abel BTFSC fb 0 lt f lt 31 O lt b lt 7 skip if lt b gt 0 None 0110 If bit b in register f is 0 then the next instruction is skipped If bit b is O then the next instruction fetched during the current instruction execution is discarded and an NOP is executed instead making this a 2 cycle instruction bbbf EEEE HERE BTFSC FLAG 1 FALSE GOTO PROCESS CODE TRUE Before Instruction PC address HERE After Instruction if FLAG lt 1 gt 0 PC address TRUE if FLAG lt 1 gt 1 PC address FALSE BTFSS Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Bit Test f Skip if Set label BTFSS f b 0 lt f lt 31 0 lt b lt 7 skip if lt b gt 1 None 0111 bbbf ffff
15. Bank 0 Bank 1 Note 1 Nota physical register See Section 4 8 DS40139D page 14 1998 Microchip Technology Inc PIC12C5XX 4 2 2 SPECIAL FUNCTION REGISTERS The special registers can be classified into two sets The Special Function Registers SFRs are registers used by the CPU and peripheral functions to control the operation of the device Table 4 1 TABLE 4 1 Address Name N A TRIS N A OPTION 00h INDF 01h TMRO 02h PCL 03h STATUS The special function registers associated with the core functions are described in this section Those related to the operation of the peripheral features are described in the section for each peripheral feature SPECIAL FUNCTION REGISTER SFR SUMMARY Value on Value on Power On All Other Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Biti Bito Reset Resets O control registers uli UEL 11 1111 Contains control bits to configure Timer0 Timer0 WDT prescaler wake up on change and weak pull ups LTIT TL 1111 1111 Uses contents of FSR to address data memory not a physical register XXXX XXXX uuuu uuuu 8 bit real time clock counter XXXX XXXX uuuu uuuu Low order 8 bits of PC TELE TIDL 1111 1111 GPWUF PAO TO PD 2 DC C 0001 1xxx q00q quuu 2 1998 Microchip Technology Inc DS40139D page 15 PIC12C5XX 4 3 STATUS Register This register contains the arithmetic status of the ALU the RESET status and the page preselect bit for program memories larger than 512 words
16. DRT OSC Start Up Timer Im CHIP RESET FIGURE 7 9 TIME OUT SEQUENCE ON POWER UP MCLR PULLED LOW VDD mm MCLR INTERNAL POR DRT TIME OUT INTERNAL RESET VDD MCLR INTERNAL POR DRT TIME OUT INTERNAL RESET 1998 Microchip Technology 100 DS40139D page 33 PIC12C5XX FIGURE 7 11 TIME OUT SEQUENCE ON POWER UP MCLR TIED TO VDD SLOW Vpp RISE TIME VDD MCLR INTERNAL POR DRT TIME OUT INTERNAL RESET When VDD rises slowly the TDRT time out expires long before VDD has reached its final value In this example the chip will reset properly if and only if V gt VDD min 7 5 Device Reset Timer DRT In the PIC12C5XX DRT runs from RESET and varies based on oscillator selection see Table 7 5 The DRT operates on an internal RC oscillator The processor is kept in RESET as long as the DRT is active The DRT delay allows VDD to rise above VDD min and for the oscillator to stabilize Oscillator circuits based on crystals or ceramic resonators require a certain time after power up to establish a stable oscillation The on chip DRT keeps the device in a RESET condition for approximately 18 ms after MCLR has reached a logic high VIHMCLR level Thus programming GP3 MCLR VPP as MCLR and using an external RC network connected to the MCLR input is not required in most cases allowing for savings
17. Example XXXXXXX 12C508A XXXXXXX 041 SM AABBCDE 9824SAZ S S 8 Lead Windowed Ceramic Side Brazed 300 mil Example Q XXX Q IW XXXXXX 12C508A Legend MM M Microchip part number information XX X Customer specific information AA Year code last 2 digits of calendar year BB Week code week of January 1 is week 01 C Facility code of the plant at which wafer is manufactured O Outside Vendor C 5 Line S 6 Line H 8 Line D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note In the event the full Microchip part number cannot be marked on one line it will be carried over to the next line thus limiting the number of available characters for customer specific information x Standard OTP marking consists of Microchip part number year code week code facility code mask rev and assembly code For OTP marking beyond this certain price adders apply Please check with your Microchip Sales Office For QTP devices any special marking adders are included in QTP price 1998 Microchip Technology Inc DS40139D page 95 PIC12C5XX Package Type K04 018 8 Lead Plastic Dual In line P 300 mil
18. Figure 4 8 For a CALL instruction or any instruction where the PCL is the destination bits 7 0 of the PC again are provided by the instruction word However PC lt 8 gt does not come from the instruction word but is always cleared Figure 4 8 Instructions where the PCL is the destination or Modify PCL instructions include MOVWF PC ADDWF PC and BSF PC 5 Note Because PC lt 8 gt is cleared in the CALL instruction or any Modify PCL instruction all subroutine calls or computed jumps are limited to the first 256 locations of any pro gram memory page 512 words long FIGURE 4 8 LOADING OF PC BRANCH INSTRUCTIONS PIC12C5XX GOTO Instruction 1110 9 87 STATUS CALL or Modify PCL Instruction 1110 9 8 7 PC PCL li Instruction Word Reset to 0 STATUS 4 6 1 EFFECTS OF RESET The Program Counter is set upon a RESET which means that the PC addresses the last location in the last page i e the oscillator calibration instruction After executing MOVLW XX the PC will roll over to location 00h and begin executing user code The STATUS register page preselect bits are cleared upon a RESET which means that page 0 is pre selected Therefore upon a RESET a coro instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered 4 7 Stack PIC12C5XX devices have a
19. If bit b in register f is 1 then the next instruction is skipped If bit b is 1 then the next instruction fetched during the current instruction execution is discarded and an NOP is executed instead making this a 2 cycle instruction 1 1 2 HERE BTFSS FLAG 1 FALSE GOTO PROCESS CODE TRUE Before Instruction PC address HERE After Instruction If FLAG lt 1 gt 0 PC address FALSE if FLAG lt 1 gt 1 PC address TRUE DS40139D page 42 1998 Microchip Technology Inc PIC12C5XX CALL Subroutine Call Syntax label CALL k Operands 0 lt k lt 255 Operation PC 1 Top of Stack k gt PC lt 7 0 gt STATUS lt 6 5 gt gt PC lt 10 9 gt 0 PC lt 8 gt Status Affected None Encoding 1001 kkkk kkkk Description Subroutine call First return address PC 1 is pushed onto the stack The eight bit immediate address is loaded into PC bits lt 7 0 gt The upper bits PC lt 10 9 gt are loaded from STA TUS lt 6 5 gt PC lt 8 gt is cleared CALLis a two cycle instruction Words 1 Cycles 2 Example HERE CALL THERE Before Instruction PC address HERE After Instruction PC address THERE TOS address HERE 1 CLRF Clear f Syntax abel CLRF f Operands 0 lt f lt 31 Operation 00h f 12Z Status Affected Z Encoding 0000 011f ffff Description The contents of register f are cleared and the Z bit is set Words 1 Cycles 1 Exampl
20. Internal Calibrated RC Frequency TBD 4 00 TBD M EN 2 5V These parameters are characterized but not tested de Note 1 Data in the Typical Typ column is at 5V 25 C unless otherwise stated Th se par m or design guidance only and are not tested SS d 1998 Microchip Technology Inc Preliminary DS40139D page 87 PIC12C5XX FIGURE 12 3 1 0 TIMING PIC12C508A C509A a4 1 ai VO Pin input i Old Value TABLE 12 4 TIMING REQUIREMENTS AC Characteristics Parameter No Sym Characteristic i Typ Max Units 17 TosH2ioV C 1 Q1 yole to Port out valid 100 ns 18 TosH2i Q24ycle to Port input invalid TBD ns O in hole time 19 TioV2osM ringut valid to 05017 TBD ns setup time 6rt output rise time 9 Port output fall time ter are design targets and are not tested No characterization data available at this time 4 uidance only and are not tested 2 lt Measurements are taken in EXTRC mode 3 Sse Figure 12 1 for loading conditions DS40139D page 88 Preliminary 1998 Microchip Technology Inc PIC12C5XX FIGURE 12 4 RESET WATCHDOG TIMER AND DEVICE RESET TIMER TIMING PIC12C508A C509A Internal POR DRT Timeout Note 2 Internal RESET Watchdog Timer RESET I O pin
21. Standard Operating Conditions unless otherwise specified Operating temperature 0 C lt TA lt 70 C commercial 40 C TA lt 85 C industrial DE CHARACTERISTICS 40 C x TA lt ose ion Operating voltage VDD range as described in DC spec Section 10 1 and Section 10 2 Param Characteristic Sym Min Typ Max Units Conditions No Input Low Voltage I O ports VIL D030 with TTL buffer Vss 0 5V V D031 with Schmitt Trigger buffer Vss 0 2VDD V D032 MCLR GP2 TOCKI AN2 INT Vss 0 2Vpp V in EXTRC mode D033 OSC1 in XT HS and LP Vss 0 8Vpp V Note1 Input High Voltage I O ports VIH D040 with TTL buffer 2 0 VDD V 4 5 lt VDp lt 5 5V D040A 0 8VDD VDD V For VDD gt 5 5V or VDD lt 4 5V D041 with Schmitt Trigger buffer 0 8VDD VDD V For entire VDD range D042 MCLR GP2 TOCKI AN2 INT 0 8VDD VDD V D042A OSC1 XT HS and LP 0 7VDD VDD V Note 0043 OSC1 in EXTRC mode 0 9VDD VDD V D070 GPIO weak pull up current IPUR 50 250 400 uA VDD 5V VPIN VSS Input Leakage Current Notes 2 3 0060 I O ports liL 1 uA Vss lt VPIN VDD Pin at hi impedance D061 MCLR GP2 TOCKI 4506 pA Vss x VPIN lt VDD D063 JOSC1 5 uA Vss lt VPIN lt VDD XT HS and LP osc configuration Output Low Voltage D080 l O ports CLKOUT VoL 0 6 V oL 8 5 mA VDD 4 5V 40 C to 85 C DO80A 0 6 V IoL 7 0 mA VDD 4 5V 40 C to 125 C D083 jOSC2 0 6 V loi 1 6 mA
22. VDD 3 0V Industrial 2 18 HA VDD 3 0V Extended These parameters are characterized but not tested Note 1 Data in the Typical Typ column is based on characterization results at 25 C This data is for design guid ance only and is not tested 2 This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data 3 The supply current is mainly a function of the operating voltage and frequency Other factors such as bus loading oscillator type bus rate internal code execution pattern and temperature also have an impact on the current consumption a The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all I O pins tristated pulled to Vss TOCKI VoD MCLR VDD WDT enabled disabled as specified b For standby current measurements the conditions are the same except that the device is in SLEEP mode 4 Does not include current through Rext The current through the resistor can be estimated by the formula IR VDD 2Rext mA with Rext in kOhm 5 The power down current in SLEEP mode does not depend on the oscillator type Power down current is mea sured with the part in SLEEP mode with all I O pins in hi impedance state and tied to VDD or Vss DS40139D page 58 1998 Microchip Technology Inc PIC12C5XX 10 2 DC CHARACTERISTICS PIC12C508 509 Commercial Industrial Extended
23. in EXTRC mode D070 GPIO weak pull up current Input Leakage Current Notes 2 3 D060 I O ports li Note1 VDD 5V VPIN VSS Vss lt VPIN VDD Pin at hi impedance Vss lt VPIN lt VDD Vss VPIN VDD XT HS and LP osc configuration D061 MCLR GP2 TOCKI D063 OSC1 Output Low Voltage D080 I O ports CLK VoL IOL 8 5 mA VDD 4 5V 40 C to 85 C DO80A loL 7 0 mA VDD 4 5V 40 C to 125 C IOL 1 6 mA VDD 4 5V 40 C to 85 C IOL 1 2 mA VDD 4 5V 40 C to 125 C Scillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that e PIC12C5XX be driven with external clock in RC mode 3 Ne ative current is defined as coming out of the pin 4 Extended operating range is Advance Information for this device 5 When configured as external reset the input leakage current is the weak pulll up current of 10mA minimum This pull up is weaker than the standard 1 2 pull up DS40139D page 80 Preliminary 1998 Microchip Technology Inc PIC12C5XX Standard Operating Conditions unless otherwise specified Operating temperature 0 C lt TA lt 70 C commercial 40 C lt TA lt 85 C industrial DC CHARACTERISTICS 40 C lt TA lt 125 C extended Operating voltage VDD range as described in DC spec Section 12 1 and Section 12 2 Param Cha
24. supports the PIC16C923 and PIC16C924 in the PLCC package It will also support future 44 pin PLCC microcontrollers with a LCD Module All the neces sary hardware and software is included to run the basic demonstration programs The user can pro gram the sample microcontrollers provided with the PICDEM 3 board on a PRO MATE II program mer or PICSTART Plus with an adapter socket and easily test firmware The MPLAB ICE emulator may also be used with the PICDEM 3 board to test firm ware Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket s Some of the features include an RS 232 interface push button switches a potenti ometer for simulated analog input a thermistor and separate headers for connection to an external LCD module and a keypad Also provided on the PICDEM 3 board is an LCD panel with 4 commons and 12 seg ments that is capable of displaying time temperature and day of the week The PICDEM 3 provides an addi tional RS 232 interface and Windows 3 1 software for showing the demultiplexed LCD signals on a PC A sim ple serial interface allows the user to construct a hard ware demultiplexer for the LCD signals DS40139D page 52 1998 Microchip Technology Inc PIC12C5XX 9 10 MPLAB Integrated Development Environment Software The MPLAB IDE Software brings an ease of software development previously unseen in the 8 bit microcon troller
25. 1 Bits TOCS TOSE PSA PS2 PS1 and PSO are located in the OPTION register 2 The prescaler is shared with the Watchdog Timer Figure 6 5 1998 Microchip Technology Inc DS40139D page 23 PIC12C5XX FIGURE 6 2 PC Program Counter Instruction Fetch TimerO Instruction Executed FIGURE 6 3 PC Program Counter Instruction Fetch TimerO Instruction Execute TIMERO TIMING INTERNAL CLOCK NO PRESCALE Q1 02 03 04 a1 az az a4 at1 az azl a4 a1 az a3 04 01 az a3 a4 Q1 a2 aZ a4 a1 02 103 04 Q1 a2 03 a4 PC PCH Y PC 2 Y PC 3 X PC 4 Y MOVWF TMRO MOVF TMRO W MOVF TMRO W MOVF TMRO W MOVF TMRO W MOVF TMRO W NTO 1 X NTO 2 X CFE Write TMRO executed t Read TMRO reads NTO t Read TMRO reads NTO t Read TMRO reads NTO TIMERO TIMING INTERNAL CLOCK PRESCALE 1 2 t Read TMRO reads NTO 1 PC 5 SE Q1 a2 03 04 a1 a2 a3 24 91 az az a4 a1 o2 03 a4 a1 AZ az a4 a1 az 03 04 at az 3 04 Q1 G2 a3 a4 t Read TMRO reads NTO 2 PC 6 1 1 1 1 1 PC PCH Y PC 3 PC 4 y PC 5 X PC 6 MOVWF TMRO MOVF TMRO W MOVF TMRO W MOVF TMRO W MOVF TMRO W MOVF TMRO W TO X NTO 1 X PC 1 t Write TMRO executed t X PC 2 Read TMRO reads NTO Read TMRO reads NTO t Read TMRO reads NTO t Read TMRO
26. EXAMPLE 4 1 INDIRECT ADDRESSING Register file 07 contains the value 10h Register file 08 contains the value OAh Load the value 07 into the FSR register Aread of the INDF register will return the value of 10h Increment the value of the FSR register by one FSR 08 Aread of the INDR register now will return the value of OAh Reading INDF itself indirectly FSR 0 will produce 00h Writing to the INDF register indirectly results in a no operation although STATUS bits may be affected A simple program to clear RAM locations 10h 1Fh using indirect addressing is shown in Example 4 2 FIGURE 4 9 DIRECT INDIRECT ADDRESSING Direct Addressing FSR 6 5 4 opcode bank select location select X EXAMPLE 4 2 HOW TO CLEAR RAM USING INDIRECT ADDRESSING moviw 0x10 initialize pointer movwf FSR to RAM NEXT CIE INDF clear INDF register incf FSR F inc pointer btfsc FSR 4 all done goto NEXT NO clear next CONTINUE YES continue The FSR is a 5 bit wide register It is used in conjunction with the INDF register to indirectly address the data memory area The FSR lt 4 0 gt bits are used to select data memory addresses 00h to 1Fh PIC12C508 A Does not use banking FSR lt 7 5 gt are unimplemented and read as 1 s PIC12C509 A Uses FSR lt 5 gt Selects between bank 0 and bank 1 FSR lt 7 6 gt is unimplemented read as 1 Indirect Addressi
27. Inclusive OR literal with W Syntax label IORLW k Operands 0 lt k lt 255 Operation W OR k gt W Status Affected Z Encoding 1101 kkkk kkkk Description The contents of the W register are OR ed with the eight bit literal K The result is placed in the W register Words 1 Cycles 1 Example IORLW 0x35 Before Instruction W Ox9A After Instruction W OxBF Z 0 IORWF Inclusive ORW with f Syntax label IORWF fd Operands 0 lt f lt 31 de 0 1 Operation W OR f gt dest Status Affected Z Encoding 0001 00df ffff Description Inclusive OR the W register with regis ter f If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f Words 1 Cycles 1 Example IORWF RESULT 0 Before Instruction RESULT 0x13 W 0x91 After Instruction RESULT 0x13 W 0x93 Z 0 1998 Microchip Technology lnc DS40139D page 45 PIC12C5XX MOVF Move f Syntax label MOVF fd Operands 0 lt f lt 31 de 0 1 Operation f gt dest Status Affected Z Encoding 0010 00df ffff Description The contents of register f is moved to destination d If d is 0 destination is the W register If d is 1 the destination is file register f is 1 is useful to test a file register since status flag Z is affected Words 1 Cycles 1 Example MOVF FSR 0 After Instruction W value in FSR register MOVLW Move Literal to W Syntax
28. MCLR reset during SLEEP d e WDT time out reset during SLEEP WDT time out reset during normal operation f Wake up from SLEEP on pin change Some registers are not reset in any way they are unknown on POR and unchanged in any other reset Most other registers are reset to reset state on power on reset POR MCLR WDT or wake up on pin change reset during normal operation They are not affected by a WDT reset during SLEEP or MCLR reset during SLEEP since these resets are viewed as resumption of normal operation The exceptions to this are TO PD and GPWUF bits They are set or cleared differently in different reset situations These bits are used in software to determine the nature of reset See Table 7 3 for a full description of reset states of all registers DS40139D page 30 1998 Microchip Technology Inc PIC12C5XX TABLE 7 3 RESET CONDITIONS FOR REGISTERS MCLR Reset Register Address Power on Reset WDT time out Wake up on Pin Change W PIC12C508 509 gaga xxxx 1 0999 uuuu 1 W PIC12C508A 509A qqqq qqxx 1 qqqq gguu 1 uuuu uuuu uuuu uuuu 1111 1111 STATUS FSR 12C508 12C508A FSR 12C509 12C509A OSCCAL 12C 508 509 OSCCAL 12C508A 509A GPIO OPTION TRIS Legend u unchanged x unknown unimplemented bit read as 0 q value depends on condition Note 1 Bits lt 7 2 gt of W register contai
29. MCUs Serial EEPROMs related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization ISO All rights reserved 1998 Microchip Technology Incorporated USA 9 98 d Printed on recycled paper um ee KENE OI E a EE IU a a ee ee ee eee Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates No representation or warranty is 01087 and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information or infringement of patents or other intellectual property rights arising from such use or otherwise Use of Microchip s products as critical components in life support systems is not authorized except with express written approval by Microchip No licenses are conveyed implicitly or otherwise under any intellectual property rights The Microchip logo and name are registered trademarks of Microchip Technology Inc in the U S A and other countries All rights reserved All other trademarks mentioned herein are the property of their respective companies DS40139D page 108 1998 Microchip Technology Inc
30. Operation W f dest Status Affected C DC Z Encoding 0001 11df EEEE Description Add the contents of the W register and register f If d is 0 the result is stored in the W register If is 1 the result is stored back in register f Words 1 Cycles 1 Example ADDWF FSR 0 Before Instruction W 0x17 FSR 0x02 After Instruction W 0xD9 FSR 0x02 ANDLW And literal with W Syntax label ANDLW k Operands 0 lt k lt 255 Operation W AND k W Status Affected Z Encoding 1110 kkkk kkkk Description The contents of the W register are AND ed with the eight bit literal k The result is placed in the W register Words 1 Cycles 1 Example ANDLW Ox5F Before Instruction W 0xA3 After Instruction W 0x03 ANDWF AND W with f Syntax label ANDWF fd Operands 0 lt f lt 31 de 0 1 Operation W AND f dest Status Affected Z Encoding 0001 01df ffff Description The contents of the W register are AND ed with register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in register Words 1 Cycles 1 Example ANDWF FSR 1 Before Instruction W 0x17 FSR 0x02 After Instruction W 0x17 FSR 0x02 BCF Bit Clear f Syntax label BCF fb Operands 0 lt f lt 31 O lt b lt 7 Operation 0 f lt b gt Status Affected None Encoding 0100 bbbf ffff Description Bit b in register f is cleared
31. PIC12C5XX configuration word consists of 12 bits Configuration bits can be programmed to select various device configurations Two bits are for the selection of the oscillator type one bit is the Watchdog Timer enable bit and one bit is the MCLR enable bit FIGURE 7 1 CONFIGURATION WORD FOR PIC12C5XX MCLRE CP WDTE FOSC1 FOSCO Register CONFIG bit11 10 9 8 7 6 5 bit 11 5 Unimplemented bit 4 MCLRE MCLR enable bit 1 MCLR pin enabled 0 MCLR tied to VDD Internally bit 3 CP Code protection bit 1 Code protection off 0 Code protection on bit 2 WDTE Watchdog timer enable bit 1 WDT enabled 0 WDT disabled bit 1 0 FOSC1 FOSCO Oscillator selection bits 11 EXTRC external RC oscillator 10 INTRC internal RC oscillator 01 XT oscillator 00 LP oscillator 3 2 1 bito Address FFFh Note 1 Refer to the PIC12C5XX Programming Specifications to determine how to access the configuration word This register is not user addressable during device operation 1998 Microchip Technology Inc DS40139D page 27 PIC12C5XX 7 2 Oscillator Configurations 7 2 1 OSCILLATOR TYPES The PIC12C5XX can be operated in four different oscillator modes The user can program two configuration bits FOSC1 FOSCO to select one of these four modes e LP Low Power Crystal XT Crystal Resonator INTRC Internal 4 MHz Oscillator EXTRC External Resistor Capacitor 7 2
32. ROM based CMOS microcontrollers It employs a RISC architecture with only 33 single word single cycle instructions All instructions are single cycle 1 us except for program branches which take two cycles The PIC12C5XX delivers performance an order of magnitude higher than its competitors in the same price category The 12 bit wide instructions are highly symmetrical resulting in 2 1 code compression over other 8 bit microcontrollers in its class The easy to use and easy to remember instruction set reduces development time significantly The PIC12C5XX products are equipped with special features that reduce system cost and power require ments The Power On Reset POR and Device Reset Timer DRT eliminate the need for external reset cir cuitry There are four oscillator configurations to choose from including INTRC internal oscillator mode and the power saving LP Low Power oscillator mode Power saving SLEEP mode Watchdog Timer and code protection features also improve system cost power and reliability The PIC12C5XX are available in the cost effective One Time Programmable OTP versions which are suitable for production in any volume The customer can take full advantage of Microchip s price leadership in OTP microcontrollers while benefiting from the OTP s flexibility The PIC12C5XX products are supported by a full fea tured macro assembler a software simulator an in cir cuit emulator a C compiler fuzzy logic support
33. STATUS lt 4 gt is set the PD bit STATUS lt 3 gt is cleared and the oscillator driver is turned off The O ports maintain the status they had before the SLEEP instruction was executed driving high driving low or hi impedance It should be noted that a RESET generated by a WDT time out does not drive the MCLR pin low For lowest current consumption while powered down the TOCKI input should be at VDD or Vss and the GP3 MCLR VPP pin must be at a logic high level VIHMC if MCLR is enabled 7 9 2 WAKE UP FROM SLEEP The device can wake up from SLEEP through one of the following events 1 An external reset input on GP3 MCLR VPP pin when configured as MCLR 2 A Watchdog Timer time out reset if WDT was enabled 3 A change on input pin GPO GP1 or GP3 MCLR VPP when wake up on change is enabled These events cause a device reset The TO PD and GPWUF bits can be used to determine the cause of device reset The TO bit is cleared if a WDT time out occurred and caused wake up The PD bit which is set on power up is cleared when SLEEP is invoked The GPWUF bit indicates a change in state while in SLEEP at pins GPO GP1 or GP3 since the last time there was a file or bit operation on GP port Caution Right before entering SLEEP read the input pins When in SLEEP wake up occurs when the values at the pins change from the state they were in at the last reading If a wake up on chang
34. Temperature 4 acit an i a ha nn id ddd 65 C to 150C Voltage on VDD with respct to VSS its see eee ti eret ee ote Eu ree ede ved ere iS 0to 47 5 V Voltage on MCLR with respect to VSS nenene ene Oto 14 V Voltage on all other pins with respect to VSS ssssee emen 0 6 V to VDD 0 6 V Total Power Dissipation EE ey rey D MINE IM D Oe aT eee TO E UM Tee 700 mW Max GUrrent OUTOT VSS pili ie deor eek tied ad esee ec erepti dete dee ret aero fn ore 200 mA MaxeGurrent into VDD Bites r ia la ni EDR RERO URRO 150 mA Input Clamp Current IK VI lt 0 or VI gt VDD riniti A E EERE E R 20 mA Output Clamp Current IOK VO lt 0 or VO gt VDD een 20 mA Max Output Current sunk by any I O pin RR RR 25 mA Max Output Current sourced by any I O pin RR 25 mA Max Output Current sourced by I O port GPIO non osn rn RR 100 mA Max Output Current sunk by I O port GPIO iii 100 mA Note 1 Power Dissipation is calculated as follows PDIS VDD x IDD Y loH X VbD VoH x lOH Z VoL x IOL TNOTICE Stresses above those listed under Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may aff
35. an input at this time the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin overwriting the previous content As long as the pin stays in the input mode no problem occurs However if bitO is switched into output mode later on the content of the data latch may now be unknown Example 5 1 shows the effect of two sequential read modify write instructions e g BCF BSF etc on an O port A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin wired or wired and The resulting high output currents may damage the chip FIGURE 5 2 SUCCESSIVE 1 0 OPERATION 01 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Qt Q2 03 Q4 Q2 Q3 Q4 EXAMPLE 5 1 READ MODIFY WRITE INSTRUCTIONS ON AN 110 PORT lnitial GPIO Settings GPIO lt 5 3 gt Inputs GPIO 2 0 Outputs GPIO latch GPIO pins Se Ne Ne BCF GPIO 5 01 ppp 11 pppp BCF GPIO 4 10 ppp 11 pppp MOVLW 007h TRIS GPIO 10 ppp 11 pppp Note that the user may have expected the pin values to be 00 pppp The 2nd BCF caused GP5 to be latched as the pin value High 5 448 SUCCESSIVE OPERATIONS ON I O PORTS The actual write to an I O port happens at the end of an instruction cycle whereas for reading the data must be valid at the beginning of the instruction cycle Figure
36. are trademarks and SQTP is a service mark of Micro chip in the U S A All other trademarks mentioned herein are the property of their respective companies 1998 Microchip Technology lnc DS40139D page 103 PIC12C5XX READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod uct If you wish to provide your comments on organization clarity subject matter and ways in which our documentation can better serve you please FAX your comments to the Technical Publications Manager at 602 786 7578 Please list the following information and use this outline to provide us with your comments about this Data Sheet To Technical Publications Manager Total Pages Sent RE Reader Response From Name Company Address City State ZIP Country Telephone FAX E Application optional Would you like a reply Y N Device PIC12C5XX Literature Number DS40139D Ouestions 1 What are the best features of this document 2 How does this document meet your hardware and software development needs 3 Do you find the organization of this data sheet easy to follow If not why 4 What additions to the data sheet do you think would enhance the structure and subject 5 What deletions from the data sheet could be made without affecting the overall usefulness 6 Is there any incorrect
37. but not tested DS40139D page 64 1998 Microchip Technology Inc PIC12C5XX 10 5 Timing Parameter Symbology and Load Conditions PIC12C508 C509 The timing parameter symbols have been created following one of the following formats 1 TppS2ppS 2 TppS T F Frequency T Time Lowercase subscripts pp and their meanings to MCLR CLKOUT oscillator cycle time OSC1 device reset timer TOCKI I O port watchdog timer F Fall P Period H High R Rise Invalid Hi impedance V Valid L Low Z Hi impedance FIGURE 10 1 LOAD CONDITIONS PIC12C508 C509 Pin XI CL 50 for all pins except OSC2 CL 15 pF for OSC2 in XT HS or LP v modes when external clock is used to drive OSC1 1998 Microchip Technology 100 DS40139D page 65 PIC12C5XX 10 6 Timing Diagrams and Specifications FIGURE 10 2 EXTERNAL CLOCK TIMING PIC12C508 C509 TABLE 10 2 EXTERNAL CLOCK TIMING REQUIREMENTS PIC12C508 C509 AC Characteristics Standard Operating Conditions unless otherwise specified Operating Temperature 0 C lt TA 70 C commercial 40 C lt TA lt 85 C industrial 40 C lt TA lt 125 C extended Operating Voltage VDD range is described in Section 10 1 eee Sym Characteristic Min Typ Max Units Conditions FOSC External CLKIN Frequency DC 4 MHz XT osc mode DC 200 kHz LP osc mode Oscillator Frequency 0 1
38. lt f lt 31 de 0 1 Operation W XOR f 5 dest Status Affected Z Encoding 0001 10df ffff Description Exclusive OR the contents of the W register with register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f Words 1 Cycles 1 Example XORWF REG 1 Before Instruction REG OxAF W 0xB5 After Instruction REG 0014 W 0xB5 1998 Microchip Technology lnc DS40139D page 49 PIC12C5XX NOTES DS40139D page 50 1998 Microchip Technology Inc PIC12C5XX 9 0 DEVELOPMENT SUPPORT 9 1 Development Tools The PlCmicro microcontrollers are supported with a full range of hardware and software development tools e MPLAB ICE Real Time In Circuit Emulator ICEPIC Low Cost PIC16C5X and PIC16CXXX In Circuit Emulator PRO MATE II Universal Programmer PICSTART Plus Entry Level Prototype Programmer SIMICE PICDEM 1 Low Cost Demonstration Board PICDEM 2 Low Cost Demonstration Board PICDEM 3 Low Cost Demonstration Board MPASM Assembler MPLAB SIM Software Simulator MPLAB C17 C Compiler Fuzzy Logic Development System fuzzyYTECH MP KEELoc Evaluation Kits and Programmer 9 2 MPLAB ICE High Performance Universal In Circuit Emulator with MPLAB IDE The MPLAB ICE Universal In Circuit Emulator is intended to provide the product development engineer with a complete microcontroller des
39. mA VDD 4 5V 40 C to 85 C D090A VDD 0 7 V IOH 2 5 mA VDD 4 5V 40 C to 125 C D092 OSC2 00 0 7 V lOH 1 3 mA VDD 4 5V 40 C to 85 C DO92A VDD 0 7 V IOH 1 0 mA VDD 4 5V 40 C to 125 C Capacitive Loading Specs on Output Pins D100 OSC2 pin Cosc2 15 pF In XT HS and LP modes when external clock is used to drive OSC1 D101 m All I O pins and OSC2 Clo 50 pF Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 In EXTRC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC12C5XX be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as coming out of the pin 4 Extended operating range is Advance Information for this device 5 When configured as external reset the input leakage current is the weak pulll up current of 10mA minimum This pull up is weaker than the standard I O pull up OOOO a eel DS40139D page 60 1998 Microchip Technology Inc PIC12C5XX 1998 Microchip Technology Inc DS40139D page 61 PIC12C5XX 10 4 DC CHARACTERISTICS PI
40. market MPLAB is a windows based application which contains A full featured editor Three operating modes editor emulator simulator A project manager Customizable tool bar and key mapping A status bar with project information Extensive on line help MPLAB allows you to Edit your source files either assembly or C One touch assemble or compile and download to PICmicro tools automatically updates all project information Debug using source files absolute listing file The ability to use MPLAB with Microchip s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools 9 11 Assembler MPASM The MPASM Universal Macro Assembler is a PC hosted symbolic assembler It supports all microcon troller series including the PIC12C5XX PIC14000 PIC16C5X PIC16CXXX and PIC17CXX families MPASM offers full featured Macro capabilities condi tional assembly and several source and listing formats It generates various object code formats to support Microchip s development tools as well as third party programmers MPASM allows full symbolic debugging from MPLAB ICE Microchip s Universal Emulator System MPASM has the following features to assist in develop ing software for specific use applications Provides translation of Assembler source code to object c
41. of the desired device FIGURE 6 4 011 Q21 Q3I Q4 AA External Clock Input or 011 Q21 Q31 Q4 When a prescaler is used the external clock input is divided by the asynchronous ripple counter type prescaler so that the prescaler output is symmetrical For the external clock to meet the sampling requirement the ripple counter must be taken into account Therefore it is necessary for TOCKI to have a period of at least 4Tosc and a small RC delay of 40 ns divided by the prescaler value The only requirement on TOCKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns Refer to parameters 40 41 and 42 in the electrical specification of the desired device 6 1 2 TIMERO INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks there is a small delay from the time the external clock edge occurs to the time the TimerO module is actually incremented Figure 6 4 shows the delay from the external clock edge to the timer incrementing 6 1 3 OPTION REGISTER EFFECT ON GP2 TRIS If the option register is set to read TIMERO from the pin the port is forced to an input regardless of the TRIS reg ister setting TIMERO TIMING WITH EXTERNAL CLOCK 011 A21 AZI Q4 Q1 Q21 Q3I Q4 Small pulse X misses sampling Prescaler Output 2 1 External Clock Prescaler Mal i A Output After Sampling A A i Increment Timer0 Q4 Ti
42. of the CPU 327 Special Function Registers 15 Stack 19 STATUS ooo rot onno nn 9 STATUS Register islo zial eret siet 16 T TimerO Switching Prescaler Assignment 26 Burm TimerO TMRO Module eene TMRO with External Clock Timing Diagrams and Specifications 66 86 Timing Parameter Symbology and Load Conditions 65 85 TRIS Registers 0 cett eec teh cea 21 W Wake up from SLEEP ss 37 Watchdog Timer WDT 27 34 Period Programming Considerations ssssss 35 WWW On Line Support 3 2 ZOVO DIS PERCIPIT 9 1998 Microchip Technology lnc DS40139D page 101 PIC12C5XX NOTES DS40139D page 102 1998 Microchip Technology Inc PIC12C5XX ON LINE SUPPORT Microchip provides on line support on the Microchip World Wide Web WWW site The web site is used by Microchip as a means to make files and information easily available to customers To view the site the user must have access to the Internet and a web browser such as Netscape or Microsoft Explorer Files are also available for FTP download from our FTP site Connecting to the Microchip InternetWeb Site The Microchip web site is available by using your favorite Internet browser to attach to www microchip com The file transfer site is available by using an FTP ser vice to connect t
43. or misleading information what and where 7 How would you improve this document 8 How would you improve our software systems and silicon products DS40139D page 104 1998 Microchip Technolooy Inc PIC12C5XX PIC12C5XX Product Identification System PART NO XX X XX XXX Examples EH Pattern Special Requirements a PIC12C508A 04 P Commercial Temp 150 mil SOIC PDIP Package 4 MHz 208 mil SOIC normal VDD limits 300 mil PDIP 300 mil Windowed Ceramic Side Brazed P PIC12C508A 04 SM Industrial Temp SOIC 0 C to 70 C 40 C to 85 C package 4 MHz normal 40 C to 125 C VDD limits 4 MHz PIC12C509 041 P Industrial Temp PDIP package 4 MHz normal VDD limits Package SN SM P JW Temperature Range E Frequency 04 Range Device PIC12C508 PIC12C509 PIC12C508T Tape amp reel for SOIC only PIC12C509T Tape amp reel for SOIC only PIC12C508A PIC12C509A PIC12C508AT Tape amp reel for SOIC only PIC12C509AT Tape amp reel for SOIC only PIC12LC508A PIC12LC509A PIC12LC508AT Tape amp reel for SOIC only PIC12LC509AT Tape amp reel for SOIC only Please contact your local sales office for exact ordering procedures Sales and Support Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds To determine if an errata sheet exists for a particular device ple
44. program execution To avoid an unintended device RESET the following instruction sequence Example 6 1 must be executed when changing the prescaler assignment from TimerO to the WDT EXAMPLE 6 1 CHANGING PRESCALER TIMERO gt WDT CLRWDT Clear WDT CLRF TMRO Clear TMRO 4 Prescaler MOVLW 00xx1111 b These 3 lines 5 6 7 OPTION are required only if desired 5 CLRWDT PS 2 0 are 000 or 001 6 MOVLW 00xx1xxx b Set Postscaler to 7 OPTION desired WDT rate To change prescaler from the WDT to the TimerO module use the sequence shown in Example 6 2 This sequence must be used even if the WDT is disabled A CLRWDT instruction should be executed before switching the prescaler EXAMPLE 6 2 CHANGING PRESCALER WDT TIMERO CLRWDT Clear WDT and prescaler Select TMRO new prescale value and MOVLW XXXXOxxx clock source OPTION FIGURE 6 5 BLOCK DIAGRAM OF THE TIMERO WDT PRESCALER Tcv Fosc 4 GP2 TOCKI Pin Data Bus 8 TMRO reg 4 PS2 PSO WDT Enable bit Time Out Note TOCS TOSE PSA PS2 PSO are bits in the OPTION register DS40139D page 26 1998 Microchip Technology Inc PIC12C5XX 7 0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits to deal with the needs of real time applications The P
45. reads NTO Mo t Read TMRO reads NTO amp 1 TABLE 6 1 REGISTERS ASSOCIATED WITH TIMERO Value on Value on Power On All Other Address Name Bit 7 Bit 6 Bit5 Bit4 Bit 3 6112 Bit1 BitO Reset Resets 01h TMRO TimerO 8 bit real time clock counter XXXX XXXX uuuu uuuu N A OPTION GPWU GPPU TOCS TOSE PSA PS2 PS1 PSO 1111 1111 1111 1111 N A TRIS GP5 GP4 GP3 GP2 GP1 GPO 11 1111 11 1111 Legend Shaded cells not used by TimerO unimplemented x unknown u unchanged DS40139D page 24 1998 Microchip Technology Inc PIC12C5XX 6 1 Using TimerO with an External Clock When an external clock input is used for TimerO it must meet certain requirements The external clock requirement is due to internal phase clock Tosc synchronization Also there is a delay in the actual incrementing of TimerO after synchronization 6 1 1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used the external clock input is the same as the prescaler output The synchronization of TOCKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks Figure 6 4 Therefore it is necessary for TOCKI to be high for at least 2Tosc and a small RC delay of 20 ns and low for at least 2Tosc and a small RC delay of 20 ns Refer to the electrical specification
46. result is negative DS40139D page 48 1998 Microchip Technology Inc PIC12C5XX SWAPF Swap Nibbles in f Syntax label SWAPF f d Operands 0 lt f lt 31 de 0 1 Operation f lt 3 0 gt dest lt 7 4 gt f lt 7 4 gt dest lt 3 0 gt Status Affected None Encoding 0011 10df ffff Description The upper and lower nibbles of register are exchanged If d is 0 the result is placed in W register If d is 1 the result is placed in register f Words 1 Cycles 1 Example SWAPF REG1 0 Before Instruction REG1 0xA5 After Instruction REG1 0xA5 W OX5A TRIS Load TRIS Register Syntax label TRIS f Operands f 6 Operation W TRIS register f Status Affected None Encoding 0000 0000 Offf Description TRIS register f f 6 is loaded with the contents of the W register Words 1 Cycles 1 Example TRIS GPIO Before Instruction W OXAS After Instruction TRIS Note O0XA5 f 6 for PIC12C5XX only XORLW Exclusive OR literal with W Syntax label XORLW k Operands 0 lt k lt 255 Operation W XOR k gt W Status Affected Z Encoding 1111 kkkk kkkk Description The contents of the W register are XOR ed with the eight bit literal k The result is placed in the W register Words 1 Cycles 1 Example XORLW OxAF Before Instruction W OxB5 After Instruction W OxlA XORWF Exclusive OR W with f Syntax label XORWF f d Operands 0
47. unless otherwise specified Operating Temperature 0 C lt TA x 70 C commercial 40 C lt TA 85 C industrial 40 C lt TA 125 C extended Operating Voltage VDD range is described in Section 10 1 Parameter No Sym Characteristic Min Typ Max Units Conditions Internal Calibrated RC Freguency 3 64 4 00 4 32 MHz VDD 5 0V Internal Calibrated RC Frequency 3 51 4 00 4 26 MHz VDD 2 5V These parameters are characterized but not tested Note 1 Data in the Typical Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested FIGURE 10 3 1 0 TIMING PIC12C508 C509 VO Pin input Sati Old Value Y New Value Note All tests must be done with specified capacitive loads see data sheet 50 pF on I O pins and CLKOUT 1998 Microchip Technology Inc DS40139D page 67 PIC12C5XX TABLE 10 4 TIMING REQUIREMENTS PIC12C508 C509 AC Characteristics Standard Operating Conditions unless otherwise specified Operating Temperature 0 C lt TA 70 C commercial 40 C lt TA lt 85 C industrial 40 C lt TA 125 C extended Operating Voltage VDD range is described in Section 10 1 Parameter No Sym Characteristic Min Typ Max Units TosH2ioV DSC17 Q1 cycle to Port out valid TosH2iol OSC1T Q2 cycle to Port input invalid I O in hold t
48. 12 bit wide L I F O hardware push pop stack A CALL instruction will push the current value of stack 1 into stack 2 and then push the current program counter value incremented by one into stack level 1 If more than two sequential CALLS are executed only the most recent two return addresses are stored A RETLW instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1 If more than two sequential RETLWS are executed the stack will be filled with the address previously stored in level 2 Note that the W register will be loaded with the literal value specified in the instruction This is particularly useful for the implementation of data look up tables within the program memory Upon any reset the contents of the stack remain unchanged however the program counter PCL will also be reset to 0 Note 1 There are no STATUS bits to indicate stack overflows or stack underflow condi tions Note 2 There are no instructions mnemonics called PUSH or POP These are actions that occur from the execution of the CALL and RETLW instructions 1998 Microchip Technology Inc DS40139D page 19 PIC12C5XX 4 8 Indirect Data Addressing INDF and FSR Registers The INDF register is not a physical register Addressing INDF actually addresses the register whose address is contained in the FSR register FSR is a pointer This is indirect addressing
49. 2 CRYSTAL OSCILLATOR CERAMIC RESONATORS In XT or LP modes a crystal or ceramic resonator is connected to the GP5 OSC1 CLKIN and GP4 OSC2 pins to establish oscillation Figure 7 2 The PIC12C5XX oscillator design requires the use of a parallel cut crystal Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications When in XT or LP modes the device can have an external clock source drive the GP5 OSC1 CLKIN pin Figure 7 3 FIGURE 7 2 CRYSTAL OPERATION OR CERAMIC RESONATOR XT OR LP OSC CONFIGURATION PIC12C5XX SLEEP i RF To internal ogic See Capacitor Selection tables for recommended values of C1 and C2 A series resistor RS may be required for AT strip cut crystals RF approximate value 10 MQ FIGURE 7 3 EXTERNAL CLOCK INPUT OPERATION XT OR LP OSC CONFIGURATION Clock from J gt OSC1 ext system PIC12C5XX OSC2 Open TABLE 7 1 CAPACITOR SELECTION FOR CERAMIC RESONATORS PIC12C5XX Osc Resonator Cap Range Cap Range Type Freg 01 C2 XT 4 0 MHz 30 pF 30 pF These values are for design guidance only Since each resonator has its own characteristics the user should consult the resonator manufacturer for appropriate values of external components TABLE 7 2 CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR PIC12C5XX Osc Resonator Cap Range Cap Range Type Freq C1
50. 2ppS 2 TppS T F Freguency T Time Za Lowercase subscripts pp and their meanings to MCLR CLKOUT oscillator cycle time OSC1 device reset timer TOCKI I O port watchdog timer E Fall P Period H High Invalid Hi impedance Low FIGURE 12 1 LOAD CONDITIONS PIC12C508A C5Q for all pins except OSC2 for OSC2 in XT HS or LP modes when external clock is used to drive OSC1 1998 Microchip Technology Inc Preliminary DS40139D page 85 PIC12C5XX 12 6 Timing Diagrams and Specifications FIGURE 12 2 EXTERNAL CLOCK TIMING PIC12C508A C509A C TABLE 12 2 EXTERNAL CLOCK TIMING REGUIREMENTS a 509A AC Characteristics Standard Operating Conditions unless otherwise specified Operating Temperature 0 C TA amp 782C commersial 40 C lt TA x 4285 C industrial 40 C lt lt 1258C extended Operating Voltage VDD range is described in Section 2 1 ue Sym Characteristic Min Typ Max Units Conditions Fosc External CLKIN Frequent DC 4 MHz XT osc mode C 200 kHz LP osc mode Oscillator Frequency DC 4 MHz EXTRC osc mode 0 1 4 MHz XT osc mode DC 200 kHz LP osc mode 1 TOSC External CLKIN Perio 250 ns XT osc mode 5 ms LP osc mode d 250 ns EXTRC osc mode 250 110 000 ns XT osc mode 5 ms LP osc mode on Cycle Time 4 Fosc E in OSC1 Low o
51. 34 Tioz I O Hi impedance from MCLR Low 2000 ns These parameters are characterized but not tested Note 1 Data in the Typical Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested TABLE 10 6 DRT DEVICE RESET TIMER PERIOD PIC12C508 C509 Oscillator Configuration POR Reset Subsequent Resets IntRC amp ExtRC 18 ms typical 300 us typical XT amp LP 18 ms typical 18 ms typical SEE EE EE aa ee SEI IE MUN t 1998 Microchip Technology Inc DS40139D page 69 PIC12C5XX FIGURE 10 5 TIMERO CLOCK TIMINGS PIC12C508 C509 TABLE 10 7 TIMERO CLOCK REQUIREMENTS PIC12C508 C509 AC Characteristics Standard Operating Conditions unless otherwise specified Operating Temperature 0 C lt TA lt 70 C commercial 40 C lt TA lt 85 C industrial 40 C lt TA 125 C extended Operating Voltage VDD range is described in Section 10 1 Parameter No Sym Characteristic Min Typ Max Units Conditions TOCKI High Pulse Width No Prescaler 0 5 Tcv 20 With Prescaler 10 ns TtOL TOCKI Low Pulse Width No Prescaler 0 5 Tcv 20 LES S ns With Prescaler 10 E ns TtOP TOCKI Period 20 or Toy 40 ns Whichever is greater N N Prescale Value 1 2 4 256 These par
52. 5 2 Therefore care must be exercised if a write followed by a read operation is carried out on the same l O port The sequence of instructions should allow the pin voltage to stabilize load dependent before the next instruction which causes that file to be read into the CPU is executed Otherwise the previous state of that pin may be read into the CPU rather than the new state When in doubt it is better to separate these instructions with a NOP or another instruction not accessing this I O port PC Y PC 1 X PC 2 PC 3 This example shows a write to GPIO followed Instruction fetched MOVWF GPIO MOVFGPIOW by a read from GPIO Data setup time 0 25 Tcy TPD where Tcy instruction cycle NOP i NOP GP5 GPO i X Port pin sampled here 1 Port pin written here P Instruction sacia MOVWF GPIO Write to GPIO MOVF GPIOW Read GPIO TPD propagation delay Therefore at higher clock freguencies a write followed by a read may be problematic DS40139D page 22 1998 Microchip Technolooy Inc PIC12C5XX 6 0 TIMERO MODULE AND TMRO REGISTER The TimerO module has the following features 8 bit timer counter register TMRO Readable and writable 8 bit software programmable prescaler Internal or external clock select Edge select for external clock Figure 6 1 is a simplified block diagram of the TimerO module Timer mode is selected by cleari
53. C12LC508 509 Commercial Industrial Standard Operating Conditions unless otherwise specified Operating temperature 0 C lt TA lt 70 C commercial DC CHARACTERISTICS 40 C lt TA x 85 C industrial Operating voltage VDD range as described in DC spec Section 10 1 and Section 10 2 Characteristic Sym Min Typ Max Units Conditions Input Low Voltage I O ports with TTL buffer V with Schmitt Trigger buffer V MCLR GP2 TOCKI AN2 INT V in EXTRC mode OSC1 in XT HS and LP i V Note1 Input High Voltage I O ports with TTL buffer V 45 lt VpD lt 5 5V V For VDD gt 5 5V or VDD lt 4 5V with Schmitt Trigger buffer V For entire VDD range MCLR GP2 TOCKI AN2 INT V XT HS and LP V Note in EXTRC mode V GPIO weak pull up current uA VDD 5V VPIN VSS Input Leakage Current Notes 2 3 I O ports uA Vss VPIN VDD Pin at hi impedance MCLR GP2 TOCKI HA Vss VPIN lt VDD OSC1 uA Vss lt VPIN VDD XT HS and LP osc configuration Output Low Voltage D080 1 O ports CLKOUT VoL 0 6 V oi 8 5 mA VDD 4 5V 40 C to 85 C D080A 0 6 V IoL 7 0 mA VDD 4 5V 40 C to 125 C D083 jOSC2 0 6 V loi 1 6 mA VDD 4 5V 40 C to 85 C D083A 0 6 V oi 1 2 mA VDD 4 5V 40 C to 125 C Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 In EXTRC oscillator configuration t
54. C2 LP 32 kHz 15 pF 15 pF XT 200 kHz 47 68 pF 47 68 pF 1MHz 15 pF 15 pF 4 MHz 15 pF 15 pF Note 1 For VDD gt 4 5V C1 C2 30 pF is recommended These values are for design guidance only Rs may be required to avoid overdriving crystals with low drive level specification Since each crystal has its own characteristics the user should consult the crys tal manufacturer for appropriate values of external components DS40139D page 28 1998 Microchip Technology Inc PIC12C5XX 7 2 3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit Prepackaged oscillators provide a wide operating range and better stability A well designed crystal oscillator will provide good performance with TTL gates Two types of crystal oscillator circuits can be used one with parallel resonance or one with series resonance Figure 7 4 shows implementation of a parallel resonant oscillator circuit The circuit is designed to use the fundamental freguency of the crystal The 74AS04 inverter performs the 180 degree phase shift that a parallel oscillator requires The 4 7 kQ resistor provides the negative feedback for stability The 10 kQ potentiometers bias the 74AS04 in the linear region This circuit could be used for external oscillator designs FIGURE 7 4 EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT
55. CS PIC12C508A PIC12C509A PIC12LC508A PIC12LC509A The graphs and tables provided in this section are for design guidance and are not tested In some graphs or tables the data presented are outside specified operating range e g outside specified VDD range This is f r information only and devices will operate properly only within the specified range The data presented in this section is a statistical summary of data collected on units from different 6ts ovar a period of time Typical represents the mean of the distribution while max or min represents mean 36 and meam 36 respectively where o is standard deviation FIGURE 13 1 CALIBRATED INTERNAL RC FREQUENCY RANGE VS TEMPERATURE VDD 5 0V INTERNAL RC IS CALIBRATED TO 25 C 5 0V Not available at this time S7 FIGURE 13 2 CALIBRATED i Te e RANGE VS TEMPERATURE VDD 2 5V INTERNAL RC IS CALIBRA Not available at this time 1998 Microchip Technology Inc Preliminary DS40139D page 91 PIC12C5XX TABLE 13 1 DYNAMIC IDD TYPICAL WDT ENABLED 25 C Oscillator Frequency VDD 3 0V VDD 5 5V External RC 4 MHz 300 LA 620 uA Internal RC 4 MHz 520 uA 1 1 mA XT 4 MHz 300 uA 775 LA LP 32 KHz 10 pA 37 uA Does not include current through external R amp C FIGURE 13 3 WDT TIMER TIME OUT PERIOD vs VDD 50 45 40 35 30 25 Max 125 C WDT period mS Max 85 C Typ 25 C
56. DECF 10 Operands 0 lt f lt 31 de 0 1 Operation f 1 gt dest Status Affected Z Encoding 0000 11df FECE Description Decrement register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f Words 1 Cycles 1 Example DECF CNT 1 Before Instruction CNT 0x01 Z 0 After Instruction CNT 0x00 Z E 1 DECFSZ Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Decrement f Skip if 0 abel DECFSZ 10 0 lt f lt 31 d e 0 1 1 gt d skipif result 0 None 0010 11df ffff The contents of register f are decre mented If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f If the result is 0 the next instruction which is already fetched is discarded and an NOP is executed instead mak ing it a two cycle instruction 1 1 2 HERE DECFSZ CNT 1 GOTO LOOP CONTINUE Before Instruction PC address HERE After Instruction CNT CNT 1 ii CNT 0 PC address CONTINUE ifCNT 0 PC address HERE 1 GOTO Unconditional Branch Syntax label GOTO k Operands O lt k lt 511 Operation k gt PC lt 8 0 gt STATUS lt 6 5 gt PC lt 10 9 gt Status Affected None Encoding 101k kkkk kkkk Description GOTO is an unconditional branch The 9 bit immediate value is loaded into PC bits lt 8 0 gt The upper bits o
57. IC12C5XX family of microcontrollers has a host of such features intended to maximize system reliability minimize cost through elimination of external components provide power saving operating modes and offer code protection These features are Oscillator selection Reset Power On Reset POR Device Reset Timer DRT Wake up from SLEEP on pin change Watchdog Timer WDT SLEEP Code protection ID locations In circuit Serial Programming The PIC12C5XX has a Watchdog Timer which can be shut off only through configuration bit WDTE It runs off of its own RC oscillator for added reliability If using XT or LP selectable oscillator options there is always an 18 ms nominal delay provided by the Device Reset Timer DRT intended to keep the chip in reset until the crystal oscillator is stable If using INTRC or EXTRC there is an 18 ms delay only on VDD power up With this timer on chip most applications need no external reset circuitry The SLEEP mode is designed to offer a very low current power down mode The user can wake up from SLEEP through a change on input pins or through a Watchdog Timer time out Several oscillator options are also made available to allow the part to fit the application including an internal 4 MHz oscillator The EXTRC oscillator option saves system cost while the LP crystal option saves power A set of configuration bits are used to select various options 7 1 Configuration Bits The
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59. NTS tO General Description 2 000 s TH VVO KNN A 4 2 0 PIGT2G5XX Device Varieti s Aisne ccs see SR ona Zoo Evu 7 3 0 Architectural Overview M 40 Memory Organization 4 ertet ente te dne i ee a bid ie n re PH re e re eh f e Ee ne der irre ere THEE eo oH RU RN Leo er rb ori rana v r 6 0 TimerO Module and TMRO Register zu 7 0 Special Features of the CPU HR 8 0 Instruction Set Summ ry cce enc ata pace DER TEE e Pe EHE e UEM ehe see E aeree qe eed 9 0 Development Support Pii 10 0 Electrical Characteristics PIC12C508 PIC12C509 PIC12LC508 PIC12L C509 Ve 11 0 DC and AC Characteristics PIC12C508 PIC12C509 PIC12LC508 PIC12LC509 12 0 Electrical Characteristics PIC12C508A PIC12C509A PIC12L C508A PIC12LC509A B 13 0 DC and AC Characteristics PIC12C508A PIC12C509A PIC12LC508A PIC12LC509A esee 91 T4 07 Packaging Information asaan Pr te n RAI RUE QU Fe SERO ARM ar ee LM IR exter a A 95 To Our Valued Customers Most Current Data Sheet To obtain the most up to date version of this data sheet please check our Worldwide Web site at http Awww microchip com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page The last character of the literature number is the version number e g DS30000A is version A of document DS30000 Errata An errata sheet may exi
60. Note 1 A TABLE 12 5 RESET WATCHDOG TIMER ANQ DEVI AC Characteristics Parameter No Min Typ Max Units Conditions 30 2000 ns VDD 5V 31 9 18 30 ms VDD 5 V Commercial 9 18 30 ms VDD 5 V Commercial m 2000 ns Typ column is at 5V 25 C unless otherwise stated These parameters are for design nly and are not tested 1998 Microchip Technology Inc Preliminary DS40139D page 89 PIC12C5XX TABLE 12 6 DRT DEVICE RESET TIMER PERIOD PIC12C508A C509A Oscillator Configuration POR Reset Subsequent Resets IntRC amp ExtRC 18 ms typical 300 us typical XT amp LP 18 ms typical 18 ms typical FIGURE 12 5 TIMERO CLOCK TIMINGS PIC12C508A C509A TOCKI a TABLE 12 7 TIMERO CLOCK REQUIREMENTS PI AC Characteristics ess otherwise specified Q C STA lt 70 C commercial G lt TA 85 C industrial lt TA lt 125 C extended ge is described in Section 12 1 aha Min Typ Max Units Conditions 0 5 Tcv 20 ns 10 mE ns Ise Width No Pre aler 0 5 Tcv 20 ns 10 ns 20 or TCY 40 ns Whichever is greater N N Prescale Value 1 2 4 256 DS40139D page 90 Preliminary 1998 Microchip Technology Inc PIC12C5XX 13 0 DC AND AC CHARACTERISTI
61. To Other Devices 4 7k 74AS04 PIC12C5XX 74AS04 CLKIN Figure 7 5 shows a series resonant oscillator circuit This circuit is also designed to use the fundamental frequency of the crystal The inverter performs a 180 degree phase shift in a series resonant oscillator circuit The 330 Q resistors provide the negative feedback to bias the inverters in their linear region FIGURE 7 5 EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT To Other Devices 330 PIC12C5XX 74AS04 74AS04 e CLKIN 7 2 4 EXTERNAL RC OSCILLATOR For timing insensitive applications the RC device option offers additional cost savings The RC oscillator frequency is a function of the supply voltage the resistor Rext and capacitor Cext values and the operating temperature In addition to this the oscillator frequency will vary from unit to unit due to normal process parameter variation Furthermore the difference in lead frame capacitance between package types will also affect the oscillation frequency especially for low Cext values The user also needs to take into account variation due to tolerance of external R and C components used Figure 7 6 shows how the R C combination is connected to the PIC12C5XX For Rext values below 2 2 KQ the oscillator operation may become unstable or stop completely For very high Rext values e g 1 MQ the oscillator becomes sensitive to noise humidity and
62. VDD 4 5V 40 C to 85 C D083A 0 6 V oi 1 2 mA VDD 4 5V 40 C to 125 C Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 In EXTRC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC12C5XX be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as coming out of the pin 4 Extended operating range is Advance Information for this device 5 When configured as external reset the input leakage current is the weak pulll up current of 10mA minimum This pull up is weaker than the standard I O pull up 1998 Microchip Technology Inc DS40139D page 59 PIC12C5XX Standard Operating Conditions unless otherwise specified Operating temperature OC amp TA lt 70 C commercial 40 C lt TA lt 85 C industrial 40 C lt TA 125 C extended Operating voltage VDD range as described in DC spec Section 10 1 and DC CHARACTERISTICS Section 10 2 Param Characteristic Sym Min Typ Max Units Conditions No utput High Voltage D090 I O ports CLKOUT Note 3 VoH VDD 0 7 V JIOH 3 0
63. ameters are characterized but not tested Note 1 Data in the Typical Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Oe TOO Oe o U aei DS40139D page 70 1998 Microchip Technology Inc PIC12C5XX NOTES 1998 Microchip Technology Inc DS40139D page 71 PIC12C5XX DS40139D page 72 1998 Microchip Technology Inc PIC12C5XX 11 0 DC AND AC CHARACTERISTICS PIC12C508 PIC12C509 PIC12LC508 PIC12LC509 The graphs and tables provided in this section are for design guidance and are not tested In some graphs or tables the data presented are outside specified operating range e g outside specified VDD range This is for information only and devices will operate properly only within the specified range The data presented in this section is a statistical summary of data collected on units from different lots over a period of time Typical represents the mean of the distribution while max or min represents mean 3o and mean 30 respectively where o is standard deviation FIGURE 11 1 CALIBRATED INTERNAL RC FREQUENCY RANGE VS TEMPERATURE VDD 2 5V gt o a gt 3 85 D c 2 E e o a Temperature Deg C 1998 Microchip Technology Inc DS40139D page 73 kautia EIE PIC12C5XX FIGURE 11 2 CALIBRATED INTERNAL RC FREQUENCY RANGE VS TEMPERATURE VDD 5 0V
64. and represents a destination designator The file register designator is used to specify which one of the 32 file registers is to be used by the instruction The destination designator specifies where the result of the operation is to be placed If is 0 the result is placed in the W register If is 1 the result is placed in the file register specified in the instruction For bit oriented instructions b represents a bit field designator which selects the number of the bit affected by the operation while f represents the number of the file in which the bit is located For literal and control operations k represents an 8 or 9 bit constant or literal value TABLE 8 1 OPCODE FIELD DESCRIPTIONS Field Description Register file address 0x00 to Ox7F Working register accumulator f W b Bit address within an 8 bit file register k Literal field constant data or label Don t care location 0 or 1 The assembler will generate code with x 0 It is the recommended form of use for compatibility with all Microchip software tools Destination select d 0 store result in W d 1 store result in file register f Default is d 1 label Label name TOS Top of Stack PC Program Counter Watchdog Timer Counter WDT TO Time Out bit PD Power Down bit Destination either the W register or the specified register file location Options Conten
65. ase contact one of the following 1 Your local Microchip sales office see below 2 The Microchip Corporate Literature Center U S FAX 602 786 7277 Please specify which device revision of silicon and Data Sheet include Literature you are using For latest version information and upgrade kits for Microchip Development Tools please call 1 800 755 2345 or 1 602 786 7302 1998 Microchip Technology Inc Preliminary DS40139D page 105 PIC12C5XX NOTES Z ET DS40139D page 106 Preliminary 1998 Microchip Technology Inc PIC12C5XX NOTES D 1998 Microchip Technology Inc Preliminary DS40139D page 107 MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office Microchip Technology Inc 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 602 786 7200 Fax 602 786 7277 Technical Support 602 786 7627 Web http www microchip com Atlanta Microchip Technology Inc 500 Sugar Mill Road Suite 200B Atlanta GA 30350 Tel 770 640 0034 Fax 770 640 0307 Boston Microchip Technology Inc 5 Mount Royal Avenue Marlborough MA 01752 Tel 508 480 9990 Fax 508 480 8575 Chicago Microchip Technology Inc 333 Pierce Road Suite 180 Itasca IL 60143 Tel 630 285 0071 Fax 630 285 0075 Dallas Microchip Technology Inc 14651 Dallas Parkway Suite 816 Dallas TX 75240 8809 Tel 972 991 7177 Fax 972 991 8588 Dayton Microchip Technology Inc Two Prestige Place Suite 150
66. ation value for the internal RC oscillator This location is never code protected regardless of the code protect settings This value is programmed as a MOVLW Xx instruction where XX is the calibration value and is placed at the reset vector This will load the W register with the calibration value upon reset and the PC will then roll over to the users program at address 0x000 The user then has the option of writing the value to the OSCCAL Register 05h or ignoring it OSCCAL when written to with the calibration value will trim the internal oscillator to remove process variation from the oscillator frequency Note Please note that erasing the device will also erase the pre programmed internal calibration value for the internal oscillator The calibration value must be read prior to erasing the part so it can be repro grammed correctly later For the PIC12C508A and PIC12C509A bits lt 7 2 gt CAL5 CALO are used for calibration Adjusting CAL5 0 from 000000 to 111111 yields a higher clock speed Note that bits 1 and 0 of OSCCAL are unimplemented and should be written as 0 when modifying OSCCAL for compatibility with future devices For the PIC12C508 and PIC12C509 the lower 4 bits of the register are used Writing a larger value in this loca tion yields a higher clock speed 7 3 RESET The device differentiates between various kinds of reset a Power on reset POR b MCLR reset during normal operation c
67. chip Technology Inc DS40139D page 51 PIC12C5XX 9 6 SIMICE Entry Level Hardware Simulator SIMICE is an entry level hardware development sys tem designed to operate in a PC based environment with Microchip s simulator MPLAB SIM Both SIM ICE and MPLAB SIM run under Microchip Technol ogys MPLAB Integrated Development Environment IDE software Specifically SIMICE provides hardware simulation for Microchip s PIC12C5XX PIC12CE5XX and PIC16C5X families of PICmicroTM 8 bit microcon trollers SIMICE works in conjunction with MPLAB SIM to provide non real time O port emulation SIMICE enables a developer to run simulator code for driving the target system In addition the target system can provide input to the simulator code This capability allows for simple and interactive debugging without having to manually generate MPLAB SIM stimulus files SIMICE is a valuable debugging tool for entry level system development 9 7 PICDEM 1 Low Cost PlCmicro Demonstration Board The PICDEM 1 is a simple board which demonstrates the capabilities of several of Microchip s microcontrol lers The microcontrollers supported are PIC16C5X PIC16C54 to PIC16C58A PIC16C61 PIC16C62X PIC16C71 PIC16C8X PIC17C42 PIC17C43 and PIC17C44 All necessary hardware and software is included to run basic demo programs The users can program the sample microcontrollers provided with the PICDEM 1 board on a PROMATE Il or PICSTART Plus prog
68. coder to decode transmissions and a pro gramming interface to program test transmitters DU SSE SSS DS40139D page 54 1998 Microchip Technology Inc ou ABojouyoe 4001 866 gg 0060 06810760 HCS200 PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX 25CXX HCS300 HCS301 MPLABTM ICE v v Y Y Y v v Y Y Y ICEPIC Low Cost In Circuit Emulator MPLAB Integrated Development Environment MPLAB C17 Compiler fuzzyTECH MP Explorer Edition Fuzzy Logic Dev Tool Total Endurance Software Model PICSTART Plus Low Cost v P4 Y Y Y v P4 Y P4 Y Universal Dev Kit PRO MATE II Universal 4 Y Y Y Y 4 v Y Y Y Y 4 Programmer KEELOQ Programmer SEEVAL Designers Kit o 2 5 3 o 3 a LJ 2 S 5 W Software Tools Programmers SIMICE Y Y PICDEM 14A Y PICDEM 1 Y Y Y Y PICDEM 2 Y Y PICDEM 3 Y KEELOQ Evaluation Kit KEELOQ Transponder Kit Demo Boards 6 414VL dIHOOYDIIN INOH3 STOOL LN3INdO 1434430 9001210 PIC12C5XX NOTES DS40139D page 56 1998 Microchip Technology Inc PIC12C5XX 10 0 ELECTRICAL CHARACTERISTICS PIC12C508 PIC12C509 PIC12LC508 PIC12LC509 Absolute Maximum Ratingst Ambient Temperature under bias sise 40 C to 125 C Storage
69. de VDD 1 P Positive supply for logic and I O pins Vss 8 8 P Ground reference for logic and I O pins Legend input O output I O input output P power not used TTL TTL input ST Schmitt Trigger input 1998 Microchip Technology Inc DS40139D page 11 PIC12C5XX 3 1 Clocking Scheme Instruction Cycle The clock input OSC1 CLKIN pin is internally divided by four to generate four non overlapping quadrature clocks namely Q1 Q2 Q3 and Q4 Internally the program counter is incremented every Q1 and the instruction is fetched from program memory and latched into instruction register in Q4 It is decoded and executed during the following Q1 through Q4 The clocks and instruction execution flow is shown in Figure 3 2 and Example 3 1 FIGURE 3 2 CLOCK INSTRUCTION CYCLE Q2 Q3 Q4 3 2 Instruction Flow Pipelining An Instruction Cycle consists of four Q cycles 01 Q2 Q3 and Q4 The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle However due to the pipelining each instruction effectively executes in one cycle If an instruction causes the program counter to change e g GOTO then two cycles are required to complete the instruction Example 3 1 A fetch cycle begins with the program counter PC incrementing in Q1 In the execution cycle the
70. dependent on the applied voltage level The specified levels ended operating range is Advance Information for this device 5 When configured as external reset the input leakage current is the weak pulll up current of 10mA minimum This pull up is weaker than the standard 1 2 pull up DS40139D page 82 Preliminary 1998 Microchip Technology Inc PIC12C5XX Stan Dat Loatemperln X5 5483 70 Datureandar 502 111 0 0C o 85 DC CHARACTERISTICS Output High Voltage D090 O ports CLKOUT Note 3 VoH VDD 0 7 D090A VDD 0 7 D092 OSC2 VDD 0 7 D092A VDD 0 7 Capacitive Loading Specs on Output Pins D100 OSC2 pin Cosc2 D101 A All I O pins and OSC2 Clo IOH 3 0 mA VOD 4 5V 40 C to 85 C 1998 Microchip Technology Inc Preliminary DS40139D page 83 PIC12C5XX TABLE 12 1 PULL UP RESISTOR RANGES PIC12C508A C509A VDD Volts Temperature C Min Typ Max lt units GPO GP1 z 2 5 40 38K 42K 63K Q 25 42K 48K 85 42K 49K Qv 125 50K 55K m Q 5 5 40 15K 17K Q 25 18K 20K Q 85 19K 22K Q 125 22K 24K Q 2 5 5 5 OO DO O Oo p OO DS40139D page 84 Preliminary 1998 Microchip Technology Inc PIC12C5XX 12 5 Timing Parameter Symbology and Load Conditions PIC12C508A C509A The timing parameter symbols have been created following one of the following formats 1 TppS
71. e CLRF FLAG REG Before Instruction FLAG REG 0x5A After Instruction FLAG REG 0x00 2 1 CLRW Clear W Syntax label CLRW Operands None Operation 00h W 1 Z Status Affected Z Encoding 0000 0100 0000 Description The W register is cleared Zero bit Z is set Words 1 Cycles 1 Example CLRW Before Instruction W Ox5A After Instruction W 0x00 Z v 1 CLRWDT Clear Watchdog Timer Syntax label CLRWDT Operands None Operation 00h gt WDT 0 WDT prescaler if assigned 1 TO 1 PD Status Affected TO PD Encoding 0000 0000 0100 Description The CLRWDT instruction resets the WDT It also resets the prescaler if the prescaler is assigned to the WDT and not Timer Status bits TO and PD are set Words 1 Cycles 1 Example CLRWDT Before Instruction WDT counter After Instruction WDT counter 0x00 WDT prescale 0 TO 1 PD 1 1998 Microchip Technology Inc DS40139D page 43 PIC12C5XX COMF Complement f Syntax label COMF fd Operands 0 lt f lt 31 de 0 1 Operation f dest Status Affected Z Encoding 0010 01df ffff Description The contents of register f are comple mented If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f Words 1 Cycles 1 Example COMF REG1 0 Before Instruction REG1 0x13 After Instruction REG1 Ox13 W OxEC DECF Decrement f Syntax label
72. e 99 PIC12C5XX DS40139D page 100 1998 Microchip Technology Inc PIC12C5XX INDEX A ALU i O Eee E 9 AppliGatiOns us ertet trente rre ne eni Dei 4 Architectural Overview 9 Assembler MPASM Assembler 53 B Block Diagram On Chip Reset Circuit 33 TIMETO EE 23 TMRO WDT Prescaler Watchdog Timer ttn trennt 35 Brown Out Protection Circuit eeeeeese 36 C CALO bit E 18 CAL Dit MM 18 CAL2 bit ic TR man a A auras 18 CALS bits iris 18 GAEEST DIL iret bi peer A te ea 18 CALSLW bites asd ree rettet eee tne 18 ET oe E ed ede eere EN 9 Clocking Scheme 12 Code Protection 27 37 Configuration Bits oir hne k ra tatran 27 Configuration Word 27 D DC and AC Characteristics 73 91 Development Support 51 Development Tools 51 Device Varieties T Digit Galty c oco tip eee E Errata i 3 F Family of Devices eio na 5 Features eeeeeeeeeeeneneenernnne rnnt there nnne nn 1 ESR siae IN NAN n 20 Fuzzy Logic Dev System fuzzyTECH MP 53 l VO Interfacing 2 ion nnm tnn 21 VO POMS wer rente dent cate tee ie tpe tee erp Decet pdt 21 I O Programming Considerations ICEPIC Low Cost PIC16CXXX In Circuit Emulator 51 ID Location
73. e occurs and the pins are not read before reentering SLEEP a wake up will occur immediately even if no pins change while in SLEEP mode The WDT is cleared when the device wakes from sleep regardless of the wake up source 7 10 Program Verification Code Protection If the code protection bit has not been programmed the on chip program memory can be read out for verification purposes The first 64 locations and the last location can be read regardless of the code protection bit setting 7 11 ID Locations Four memory locations are designated as ID locations where the user can store checksum or other code identification numbers These locations are not accessible during normal execution but are readable and writable during program verify Use only the lower 4 bits of the ID locations and always program the upper 8 bits as 0 s 1998 Microchip Technology Inc DS40139D page 37 PIC12C5XX 7 12 In Circuit Serial Programming FIGURE 7 15 TYPICAL IN CIRCUIT SERIAL PROGRAMMING The PIC12C5XX microcontrollers can be serially CONNECTION programmed while in the end application circuit This is simply done with two lines for clock and data and three other lines for power ground and the programming To Normal voltage This allows customers to manufacture boards External Connections with unprogrammed devices and then program the Connector PIC12C5XX microcontroller just before shippin
74. e read write bit in devices which do not use it for program page preselect is not recommended since this may affect upward compatibility with future products bit 4 TO Time out bit 1 After power up CLRWDT instruction or SLEEP instruction 0 AWDT time out occurred bit 3 PD Power down bit 1 After power up or by the CLRWDT instruction 0 By execution of the SLEEP instruction bit 2 Z Zero bit 1 The result of an arithmetic or logic operation is zero 0 The result of an arithmetic or logic operation is not zero bit 1 DC Digit carry borrow bit for ADDWF and SUBWF instructions ADDWF 1 A carry from the 4th low order bit of the result occurred 0 A carry from the 4th low order bit of the result did not occur SUBWF 1 A borrow from the 4th low order bit of the result did not occur 0 A borrow from the 4th low order bit of the result occurred bit 0 C Carry borrow bit for ADDWF SUBWF and RRF RLF instructions ADDWF 1 carry occurred 0 A carry did not occur SUBWF 1 A borrow did not occur 0 A borrow occurred RRF or RLF Load bit with LSB or MSB respectively DS40139D page 16 1998 Microchip Technology lnc PIC12C5XX 4 4 OPTION Register Note If TRIS bit is set to 0 the wake up on The OPTION register is a 8 bit wide write only SE EE po ere oilselsilee register which contains various control bits to for that pin i e note that TRIS overrides configure the Timer0 WDT prescaler and Ti
75. ect device reliability 1998 Microchip Technology Inc DS40139D page 57 PIC12C5XX 10 1 DC CHARACTERISTICS PIC12C508 509 Commercial Industrial Extended Standard Operating Conditions unless otherwise specified DC Characteristics Operating Temperature 0 C TA 70 C commercial Power Supply Pins 40 C lt TA lt 85 C industrial 40 C lt TA 125 C extended Characteristic Sym Min Typ Max Units Conditions Supply Voltage VDD 2 5 5 5 V Fosc DC to 4 MHz Commercial Industrial 3 0 5 5 V Fosc DC to 4 MHz Extended RAM Data Retention VDR 1 5 V Device in SLEEP mode Voltage VDD Start Voltage to ensure VPOR Vss V See section on Power on Reset for details Power on Reset VDD Rise Rate to ensure Svpp 0 05 V ms See section on Power on Reset for details Power on Reset Supply Current IDD 1 8 2 4 mA XT and EXTRC options Note 4 Fosc 4 MHz VDD 5 5V 1 8 2 4 mA INTRC Option Fosc 4 MHz VDD 5 5V 15 27 HA LP OPTION Commercial Temperature Fosc 32 kHz VDD 3 0V WDT disabled 19 35 uA LP OPTION Industrial Temperature Fosc 32 kHz VDD 3 0V WDT disabled 19 35 uA LP OPTION Extended Temperature Fosc 32 kHz VDD 3 0V WDT disabled AIWDT 3 75 8 uA VDD 3 0V Commercial UE 3 75 9 uA VDD 3 0V Industrial 3 75 4 uA VDD 3 0V Extended Power Down Current 5 IPD 0 25 4 uA VDD 3 0V Commercial 0 25 5 uA
76. er file is divided into two a functional groups special function registers and 00h INDF general purpose registers 01h TMRO The special function registers include the TMRO 02h PCL register the Program Counter PC the Status 03h STATUS Register the I O registers ports and the File Select Register FSR In addition special purpose registers 04h FSR are used to control the I O port configuration and 05h OSCCAL prescaler options 06h GPO The general purpose registers are used for data and 07h control information under command of the instructions For the PIC12C508 A the register file is composed of 7 special function registers and 25 general purpose General registers Figure 4 2 Purpose es Registers For the PIC12C509 A the register file is composed of 7 special function registers 25 general purpose registers and 16 general purpose registers that may be addressed using a banking scheme Figure 4 3 1Fh 4 2 1 GENERAL PURPOSE REGISTER FILE Note 1 Not a physical register See Section 4 8 The general purpose register file is accessed either directly or indirectly through the file select register FSR Section 4 8 FIGURE 4 3 PIC12C509 A REGISTER FILE MAP FSR 6 5 00 File Address 00h INDF 01h 02h 03h STATUS Addresses map back to 04h addresses 05h OSCCAL in Bank 0 06h 07h General Purpose Registers 30h General General Purpose Purpose Registers Registers 3Fh
77. er side or 0 020 0 508 mm more than dimensions D or E 1998 Microchip Technology Inc DS40139D page 97 PIC12C5XX Package Type K04 056 8 Lead Plastic Small Outline SM Medium 208 mil B Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Pitch p 0 050 1 27 Number of Pins n 8 8 Overall Pack Height A 0 070 0 074 0 079 1 78 1 89 2 00 Shoulder Height Al 0 037 0 042 0 048 0 94 1 08 1 21 Standoff A2 0 002 0 005 0 009 0 05 0 14 0 22 Molded Package Length D 0 200 0 205 0 210 5 08 5 21 5 33 Molded Package Width Et 0 203 0 208 0 213 5 16 5 28 5 41 Outside Dimension E1 0 300 0 313 0 325 7 62 7 94 8 26 Shoulder Radius R1 0 005 0 005 0 010 0 13 0 13 0 25 Gull Wing Radius R2 0 005 0 005 0 010 0 13 0 13 0 25 Foot Length L 0 011 0 016 0 021 0 28 0 41 0 53 Foot Angle 0 4 0 4 8 Radius Centerline L1 0 010 0 015 0 020 0 25 0 38 0 51 Lead Thickness c 0 008 0 009 0 010 0 19 0 22 0 25 Lower Lead Width B 0 014 0 017 0 020 0 36 0 43 0 51 Mold Draft Angle Top a 0 12 15 0 12 15 Mold Draft Angle Bottom B 0 12 15 0 12 15 Controlling Parameter Dimension B does not include dam bar protrusions Dam bar protrusions shall not exceed 0 003 0 076 mm per side or 0 006 0 152 mm more than dimension B
78. f PC are loaded from STATUS lt 6 5 gt GOTO is a two cycle instruction Words 1 Cycles 2 Example GOTO THERE After Instruction PC address THERE DS40139D page 44 1998 Microchip Technology Inc PIC12C5XX INCF Increment f Syntax label INCF fd Operands 0 lt f lt 31 de 0 1 Operation f 1 dest Status Affected Z Encoding 0010 10df ffff Description The contents of register f are incre mented If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f Words 1 Cycles 1 Example INCF CNT 1 Before Instruction CNT OxFF 2 0 After Instruction CNT 0x00 Z 1 INCFSZ Increment f Skip if 0 Syntax label INCFSZ fd Operands 0 lt f lt 31 d e 0 1 Operation f 1 dest skip if result 0 Status Affected None Encoding 0011 11df ffff Description The contents of register f are incre mented If d is 0 the result is placed in the W register If is 1 the result is placed back in register If the result is 0 then the next instruc tion which is already fetched is dis carded and an NOP is executed instead making it a two cycle instruc tion Words 1 Cycles 1 2 Example HERE INCFSZ CNT GOTO LOOP CONTINUE Before Instruction PC address HERE After Instruction CNT if CNT PC if CNT PC CNT 1 0 address CONTINUE 0 address HERE 1 Hoc I IORLW
79. fetched instruction is latched into the Instruction Register IR in cycle Q1 This instruction is then decoded and executed during the Q2 Q3 and Q4 cycles Data memory is read during Q2 operand read and written during Q4 destination write f Vf X Internal phase clock Fetch INST PC Execute INST PC 1 Fetch INST PC 1 Execute INST PC Fetch INST PC 2 EXAMPLE 3 1 MOVLW 03H Fetch 1 Execute 1 Execute INST PC 1 INSTRUCTION PIPELINE FLOW MOVWF GPIO Fetch 2 Execute 2 1 25 3 CALL SUB 1 4 BSF GPIO BIT1 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB 1 Execute SUB 1 All instructions are single cycle except for any program branches These take two cycles since the fetch instruction is flushed from the pipeline while the new instruction is being fetched and then executed DS40139D page 12 1998 Microchip Technology Inc PIC12C5XX 4 0 MEMORY ORGANIZATION PIC12C5XX memory is organized into program mem ory and data memory For devices with more than 512 bytes of program memory a paging scheme is used Program memory pages are accessed using one STA TUS register bit For the PIC12C509 A with a data memory register file of more than 32 registers a bank ing scheme is used Data memory banks are accessed using the File Select Register FSR 4 1 Program Memory Organization
80. g the product This Signals also allows the most recent firmware or a custom 45V VDD firmware to be programmed ov Vss The device is placed into a program verify mode by VPP MCLR VPP holding the GP1 and GPO pins low while raising the i MCLR VPP pin from VIL to VIHH see programming CLK GP1 specification GP1 becomes the programming clock and GPO becomes the programming data Both GP1 and GPO are Schmitt Trigger inputs in this mode Data O GPO After reset a 6 bit command is then supplied to the i VDD device Depending on the command 14 bits of pro gram data are then supplied to or from the device To Normal depending if the command was a load or a read For Connections complete details of serial programming please refer to the PIC12C5XX Programming Specifications A typical in circuit serial programming connection is shown in Figure 7 15 DS40139D page 38 1998 Microchip Technolooy Inc PIC12C5XX 8 0 INSTRUCTION SET SUMMARY Each PIC12C5XX instruction is a 12 bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction The PIC12C5XX instruction set summary in Table 8 2 groups the instructions into byte oriented bit oriented and literal and control operations Table 8 1 shows the opcode field descriptions For byte oriented instructions represents a file register designator
81. h enough level for proper opera tion To take advantage of the internal POR program the GP3 MCLR VPP pin as MCLR and tie thru a resis tor to VDD or program the pin as GP3 An internal weak pull up resistor is implemented using a transistor Refer to Table 10 1 for the pull up resistor ranges This will eliminate external RC components usually needed to create a Power on Reset A maximum rise time for VDD is specified See Electrical Specifications for details When the device starts normal operation exits the reset condition device operating parameters voltage frequency temperature must be met to ensure operation If these conditions are not met the device must be held in reset until the operating parameters are met A simplified block diagram of the on chip Power On Reset circuit is shown in Figure 7 8 The Power On Reset circuit and the Device Reset Timer Section 7 5 circuit are closely related On power up the reset latch is set and the DRT is reset The DRT timer begins counting once it detects MCLR to be high After the time out period which is typically 18 ms it will reset the reset latch and thus end the on chip reset signal A power up example where MCLR is held low is shown in Figure 7 9 VpD is allowed to rise and stabilize before bringing MCLR high The chip will actually come out of reset TDRT msec after MCLR goes high In Figure 7 10 the on chip Power On Reset feature is being used MCLR a
82. he OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC12C5XX be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as coming out of the pin 4 Extended operating range is Advance Information for this device 5 When configured as external reset the input leakage current is the weak pulll up current of 10mA minimum This pull up is weaker than the standard 1 2 pull up DS40139D page 62 1998 Microchip Technology Inc PIC12C5XX Standard Operating Conditions unless otherwise specified Operating temperature 0 C lt TA lt 70 C commercial DC CHARACTERISTICS 40 C lt TA lt 85 C industrial Operating voltage VDD range as described in DC spec Section 10 1 and Section 10 2 Characteristic Sym Min Max Units Conditions Output High Voltage I O ports CLKOUT Note 3 V lOH 3 0 mA VDD 4 5V 40 C to 85 C V IOH 2 5 mA VDD 4 5V 40 C to 125 C V IOH 1 3 mA VDD 4 5V 40 C to 85 C V IOH 1 0 mA VDD 4 5V 40 C to 125 C Capacitive Loading Specs on Output Pins OSC2 pin pF ln XT HS and LP modes when external clock is used to drive OSC1 All I O pins and OSC2 pF Data in Typ
83. he W register or a file register The W register is an 8 bit working register used for ALU operations It is not an addressable register Depending on the instruction executed the ALU may affect the values of the Carry C Digit Carry DC and Zero Z bits in the STATUS register The C and DC bits operate as a borrow and digit borrow out bit respectively in subtraction See the SUBWF and ADDWF instructions for examples A simplified block diagram is shown in Figure 3 1 with the corresponding device pins described in Table 3 1 1998 Microchip Technology Inc DS40139D page 9 PIC12C5XX FIGURE 3 1 PIC12C5XX BLOCK DIAGRAM 12 Data Bus EPROM Program Counte 512 x 12 or 1024 x 12 GPO GP1 GP2 TOCKI Program RANI Memory STACK VA GP3 MCLR Vpp STACK2 File GP4 OSC2 P Registers GP5 OSC1 CLKIN rogram Bus RAM Addr 7 9 Addr MUX Instruction reg Direct Addr 5 FSR reg STATUS regk Device Reset Timer EU Vu Deren r Reset 8 U eg A Timin BRUHN lain Wah w Internal RC OSC Timer0 Vdd Vss DS40139D page 10 1998 Microchip Technolooy Inc PIC12C5XX TABLE 3 1 PIC12C5XX PINOUT DESCRIPTION Name DIP Pin SOIC Pin l O P Type Buffer Type Descri
84. ign tool set for PICmicro microcontrollers MCUs MPLAB ICE is sup plied with the MPLAB Integrated Development Environ ment IDE which allows editing make and download and source debugging from a single envi ronment Interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro cessors The universal architecture of the MPLAB ICE allows expansion to support all new Microchip micro controllers The MPLAB ICE Emulator System has been designed as a real time emulation system with advanced fea tures that are generally found on more expensive development tools The PC compatible 386 and higher machine platform and Microsoft Windows 3 x or Windows 95 environment were chosen to best make these features available to you the end user MPLAB ICE is available in two versions MPLAB ICE 1000 is a basic low cost emulator system with simple trace capabilities It shares processor mod ules with the MPLAB ICE 2000 This is a full featured emulator system with enhanced trace trigger and data monitoring features Both systems will operate across the entire operating speed reange of the PICmicro MCU 9 3 ICEPIC Low Cost PICmicroTM In Circuit Emulator ICEPIC is a low cost in circuit emulator solution for the Microchip PIC12CXXX PIC16C5X and PIC16CXXX families of 8 bit OTP microcontrollers ICEPIC is designed to operate on PC compatible machines ranging from 386 through Penti
85. ime 19 TioV20sH Port input valid to OSC1T TBD ns I O in setup time 20 TioR Port output rise time E 10 25 ns 21 TioF Port output fall time 9 10 25 ns These parameters are characterized but not tested These parameters are design targets and are not tested No characterization data available at this time Note 1 Data in the Typical Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 2 Measurements are taken in EXTRC mode 3 See Figure 10 1 for loading conditions FIGURE 10 4 RESET WATCHDOG TIMER AND DEVICE RESET TIMER TIMING PIC12C508 C509 SESE E ADI DS40139D page 68 1998 Microchip Technology Inc PIC12C5XX TABLE 10 5 RESET WATCHDOG TIMER AND DEVICE RESET TIMER PIC12C508 C509 AC Characteristics Standard Operating Conditions unless otherwise specified Operating Temperature 0 C lt TA 70 C commercial 40 C lt TA lt 85 C industrial 40 C lt TA 125 C extended Operating Voltage VDD range is described in Section 10 1 Parameter No Sym Characteristic Min Typ Max Units Conditions 30 TmeL MCLR Pulse Width low 2000 ns VDD 5V 31 Twdt Watchdog Timer Time out Period 9 18 30 ms VDD 5V Commercial No Prescaler 32 TorT Device Reset Timer Period 9 18 30 ms Vpp 5 V Commercial
86. in cost sensitive and or space restricted applications as well as allowing the use of the GP3 MCLR VPP pin as a general purpose input The Device Reset time delay will vary from chip to chip due to VDD temperature and process variation See AC parameters for details The DRT will also be triggered upon a Watchdog Timer time out This is particularly important for applications using the WDT to wake from SLEEP mode automatically 7 6 Watchdog Timer WDT The Watchdog Timer WDT is a free running on chip RC oscillator which does not require any external components This RC oscillator is separate from the external RC oscillator of the GP5 OSC1 CLKIN pin and the internal 4 MHz oscillator That means that the WDT will run even if the main processor clock has been stopped for example by execution of a SLEEP instruction During normal operation or SLEEP a WDT reset or wake up reset generates a device RESET The TO bit STATUS lt 4 gt will be cleared upon a Watchdog Timer reset The WDT can be permanently disabled by programming the configuration bit WDTE as a Section 7 1 Refer to the PIC12C5XX Programming Specifications to determine how to access the configuration word TABLE 7 5 DRT DEVICE RESET TIMER PERIOD Oscillator POR Reset Subsequent Configuration Resets IntRC amp 18 ms typical 300 us typical ExtRC XT amp LP 18 ms typical 18 ms typical DS40139D
87. ithout losing RAM data 3 mainly a function of the operating voltage and frequency Other factors such as bus OSC1 external square wave from rail to rail all I O pins tristated pulled to Vss TOCKI VoD MCLR 400 WDT enabled disabled as specified b For standby current measurements the conditions are the same except that the device is in SLEEP mode B es not include current through Rext The current through the resistor can be estimated by the formula IR VDD 2Rext mA with Rext in kOhm 5 The power down current in SLEEP mode does not depend on the oscillator type Power down current is mea sured with the part in SLEEP mode with all I O pins in hi impedance state and tied to VDD or Vss DS40139D page 78 Preliminary 1998 Microchip Technology Inc PIC12C5XX 12 2 DC CHARACTERISTICS PIC12LC508A 509A Commercial Industrial DC Characteristics Power Supply Pins Standard Operating Conditions unless otherwise specified Operating Temperature 0 C TA lt 70 C commercial 40 C lt TA lt 85 C industrial Characteristic Sym Min Typ Max Units Conditions Supply Voltage VDD 2 5 5 5 V Fosc DC to 4 MHz Comm cial Industrial RAM Data Retention VDR 1 5 V Device in SLEEP mod Voltage VDD Start Voltage to ensure VPOR Vss V See section on Pewer an Reset fo ails Power on Reset To Vpp Rise Rate to ensure SVDD 0 05 Rowgf i Power on Reset Supply Current IDD
88. l subroutine 2 1001 kkkk kkkk None 1 CLRWDT k Clear Watchdog Timer 1 0000 0000 0100 TOPD GOTO k Unconditional branch 2 101k kkkk kkkk None IORLW k Inclusive OR Literal with W 1 1101 kkkk kkkk Z MOVLW k Move Literal to W 1 1100 kkkk kkkk None OPTION Load OPTION register 1 0000 0000 0010 None RETLW k Return place Literal in W 2 1000 kkkk kkkk None SLEEP Go into standby mode 1 0000 0000 0011 TOPD TRIS f Load TRIS register 1 0000 0000 Offf None 3 XORLW k Exclusive OR Literal to W 1 1111 kkkk kkkk Z Note 1 The 9th bit of the program counter will be forced to a by any instruction that writes to the PC except for GOTO Section 4 6 When an I O register is modified as a function of itself e g MOVF GPIO 1 the value used will be that value present on the pins themselves For example if the data latch is 1 for a pin configured as input and is driven low by an external device the data will be written back with a 0 The instruction TRIS f where f 6 causes the contents of the W register to be written to the tristate latches of GPIO A 1 forces the pin to a hi impedance state and disables the output buffers If this instruction is executed on the TMRO register and where applicable d 1 the prescaler will be cleared if assigned to TMRO 2 3 4 DS40139D page 40 1998 Microchip Technology Inc PIC12C5XX ADDWF Add W and f Syntax label ADDWF fd Operands 0 lt f lt 31 de 0 1
89. label MOVLW k Operands 0 lt k lt 255 Operation k gt W Status Affected None Encoding 1100 kkkk kkkk Description The eight bit literal k is loaded into the W register The don t cares will assem ble as Os Words 1 Cycles 1 Example MOVLW 0x5A After Instruction W 0x5A MOVWF Move W to f Syntax label MOVWF f Operands 0 lt f lt 31 Operation W f Status Affected None Encoding 0000 001 ES Description Move data from the W register to regis ter Words 1 Cycles 1 Example MOVWF TEMP REG Before Instruction TEMP REG OxFF W Ox4F After Instruction TEMP REG 0x4F w 0 NOP No Operation Syntax label NOP Operands None Operation No operation Status Affected None Encoding 0000 0000 0000 Description No operation Words 1 Cycles 1 Example NOP DS40139D page 46 1998 Microchip Technology Inc PIC12C5XX OPTION Load OPTION Register Syntax label OPTION Operands None Operation W gt OPTION Status Affected None Encoding 0000 0000 0010 Description The content of the W register is loaded into the OPTION register Words 1 Cycles 1 Example OPTION Before Instruction W 0x07 After Instruction OPTION 0x07 RETLW Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Return with Literal in W label RETLW k 0 lt k lt 255 k g
90. leakage Thus we recommend keeping Rext between 3 kQ and 100 kQ Although the oscillator will operate with no external capacitor Cext 0 pF we recommend using values above 20 pF for noise and stability reasons With no or small external capacitance the oscillation frequency can vary dramatically due to changes in external capacitances such as PCB trace capacitance or package lead frame capacitance The Electrical Specifications sections show RC frequency variation from part to part due to normal process variation The variation is larger for larger R since leakage current variation will affect RC frequency more for large R and for smaller C since variation of input capacitance will affect RC frequency more Also see the Electrical Specifications sections for variation of oscillator frequency due to VDD for given Rext Cext values as well as frequency variation due to operating temperature for given R C and VDD values FIGURE 7 6 EXTERNAL RC OSCILLATOR MODE Internal OSC1 clock vas N 1 PIC12C5XX 1998 Microchip Technology lnc DS40139D page 29 PIC12C5XX 7 2 5 INTERNAL 4 MHz RC OSCILLATOR The internal RC oscillator provides a fixed 4 MHz nom inal system clock at VDD 5V and 25 C see Electri cal Specifications section for information on variation over voltage and temperature In addition a calibration instruction is programmed into the top of memory which contains the calibr
91. ll Other Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit3 Bit2 Bit1 Bito Reset Resets N A OPTION GPWU GPPU TOCS TOSE PSA PS2 PS1 PSO 1111 1111 ox Bt Fae Be Ba E Legend Shaded boxes Not used by Watchdog Timer unimplemented read as u unchanged 1998 Microchip Technology Inc DS40139D page 35 PIC12C5XX 7 7 Time Out Sequence Power Down and Wake up from SLEEP Status Bits TO PD GPWUF The TO PD and GPWUF bits in the STATUS register can be tested to determine if a RESET condition has been caused by a power up condition a MCLR or Watchdog Timer WDT reset TABLE 7 7 TO PD GPWUF STATUS AFTER RESET GPWUF T P RESET caused by 0 0 0 WDT wake up from SLEEP 0 0 u WDT time out not from SLEEP 0 1 0 MCLR wake up from SLEEP 0 1 1 Power up 0 4 u MCLR not during SLEEP 1 0 Wake up from SLEEP on pin change Legend Legend u unchanged Note 1 The TO PD and GPWUF bits main tain their status u until a reset occurs A low pulse on the MCLR input does not change the TO PD and GPWUF status bits u DS40139D page 36 1998 Microchip Technology Inc PIC12C5XX 7 9 Power Down Mode SLEEP A device may be powered down SLEEP and later powered up Wake up from SLEEP 7 9 1 SLEEP The Power Down mode is entered by executing a SLEEP instruction If enabled the Watchdog Timer will be cleared but keeps running the TO bit
92. merO TO TO 1 Delay from clock input change to TimerO increment is 3Tosc to 7Tosc Duration of Q 1050 Therefore the error in measuring the interval between two edges on TimerO input 41060 max External clock if no prescaler selected Prescaler output otherwise The arrows indicate the points in time where sampling occurs 1998 Microchip Technology Inc DS40139D page 25 PIC12C5XX 6 2 Prescaler An 8 bit counter is available as a prescaler for the TimerO module or as a postscaler for the Watchdog Timer WDT respectively Section 7 6 For simplicity this counter is being referred to as prescaler throughout this data sheet Note that the prescaler may be used by either the TimerO module or the WDT but not both Thus a prescaler assignment for the TimerO module means that there is no prescaler for the WDT and vice versa The PSA and PS2 PSO bits OPTION lt 3 0 gt determine prescaler assignment and prescale ratio When assigned to the TimerO module all instructions writing to the TMRO register e g CLRF 1 MOVWF 1 BSF 1 x etc will clear the prescaler When assigned to WDT a CLRWDT instruction will clear the prescaler along with the WDT The prescaler is neither readable nor writable On a RESET the prescaler contains all O s 6 2 1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control i e it can be changed on the fly during
93. merO OPTION control of GPPU and GPWU By executing the OPTION instruction the contents of Note If the TOCS bit is set to 1 GP2 is forced to the W register will be transferred to the OPTION be an input even if TRIS GP2 0 register A RESET sets the OPTION lt 7 0 gt bits FIGURE 4 5 OPTION REGISTER W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 GPWU GPPU TOCS TOSE PSA PS2 PS1 PSO W Writable bit bit7 6 5 4 3 2 1 bito U Unimplemented bit n Value at POR reset Reference Table 4 1 for other resets bit 7 GPWU Enable wake up on pin change GPO GP1 GP3 1 Disabled 0 Enabled bit 6 GPPU Enable weak pull ups GPO GP1 GP3 1 Disabled 0 Enabled bit 5 TOCS TimerO clock source select bit 1 Transition on TOCKI pin 0 Transition on internal instruction cycle clock Fosc 4 bit 4 TOSE TimerO source edge select bit 1 Increment on high to low transition on the TOCKI pin 0 Increment on low to high transition on the TOCKI pin bit 3 PSA Prescaler assignment bit 1 Prescaler assigned to the WDT 0 Prescaler assigned to TimerO bit 2 0 PS2 PSO Prescaler rate select bits Bit Value TimerO Rate WDT Rate 000 1 2 1 1 001 1 4 1 2 010 1 8 1 4 011 1 16 1 8 100 1 32 1 16 101 1 64 1 32 110 1 128 1 64 dd 1 256 1 128 1998 Microchip Technology Inc DS40139D page 17 PIC12C5XX 4 5 OSCCAL Register The Oscillator Calibration OSCCAL register is used t
94. mory bytes 16 16 Timer Peripherals Module s TMRO TMRO TMRO TMRO TMRO TMRO TMRO TMRO A D Con verter 8 bit Channels Wake up from SLEEP on pin change Yes Yes Yes Yes Yes Yes Yes Interrupt Sources 1 0 Pins Features Input Pins Internal Pull ups In Circuit Serial Programming Yes Yes Yes Yes Yes Number of Instructions 33 33 33 33 35 35 35 35 Packages 8 pin DIP JW SOIC 8 pin DIP JW SOIC 8 pin DIP JW SOIC 8 pin DIP JW SOIC 8 pin DIP JW SOIC 8 pin DIP JW SOIC 8 pin DIP JW 8 pin DIP JW All PIC12CXXX amp PIC12CEXXX devices have Power on Reset selectable Watchdog Timer selectable code protect and high I O current capability All PIC12CXXX amp PIC12CEXXX devices use serial programming with data pin GPO and clock pin GP1 SOI EE EE BEE a 2 1998 Microchip Technology Inc DS40139D page 5 PIC12C5XX NOTES DS40139D page 6 1998 Microchip Technology Inc PIC12C5XX 2 0 PIC12C5XX DEVICE VARIETIES A variety of packaging options are available Depending on application and production reguirements the proper device option can be selected using the information in this section When placing orders please use the PIC12C5XX Product Identification System at the back of this data sheet to specify
95. n an Road West Hong Qiao District Shanghai PRC 200335 Tel 86 21 6275 5700 Fax 86 21 6275 5060 DNV Certification Inc DNV MSC The Netherlands Accredited by the RvA ED o gt v q 9 ANSI RAB g DIN 151 Iso 9001 REGISTERED FIRM bu d ASIA PACIFIC continued Singapore Microchip Technology Singapore Pte Ltd 200 Middle Road 3107 02 Prime Centre Singapore 188980 Tel 65 334 8870 Fax 665 334 8850 Taiwan R O C Microchip Technology Taiwan 10F 1C 207 Tung Hua North Road Taipei Taiwan ROC Tel 886 2 2717 7175 Fax 886 2 2545 0139 EUROPE United Kingdom Arizona Microchip Technology Ltd 505 Eskdale Road Winnersh Triangle Wokingham Berkshire England RG41 5TU Tel 44 1189 21 5858 Fax 44 1189 21 5835 France Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy France Tel 33 1 69 53 63 20 Fax 33 1 69 30 90 79 Germany Arizona Microchip Technology GmbH Gustav Heinemann Ring 125 D 81739 M chen Germany Tel 49 89 627 144 0 Fax 49 89 627 144 44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V Le Colleoni 1 20041 Agrate Brianza Milan Italy Tel 39 39 689 9939 Fax 39 39 6899883 7 7 98 Microchip received ISO 9001 Quality System certification for its worldwide headquarters design and wafer fabrication facilities in January 1997 Our field programmable PICmicro TM 8 bit
96. n oscillator calibration values due to MOVLW xx instruction at top of memory Note 2 See Table 7 7 for reset value for specific conditions Note 3 If reset was due to wake up on pin change then bit 7 1 All other resets will cause bit 7 0 TABLE 7 4 RESET CONDITION FOR SPECIAL REGISTERS STATUS Addr 03h PCL Addr 02h Power on reset 0001 1xxx 1111 1111 MCLR reset during normal operation 000u uuuu 1111 1111 MCLR reset during SLEEP 0001 Ouuu 1111 1111 WDT reset during SLEEP 0000 Ouuu 1111 1111 WDT reset normal operation 0000 uuuu 1111 1111 Wake up from SLEEP on pin change 1001 Ouuu 1111 1114 Legend u unchanged x unknown unimplemented bit read as 0 1998 Microchip Technology Inc DS40139D page 31 PIC12C5XX 7 3 1 MCLR ENABLE This configuration bit when unprogrammed left in the 1 state enables the external MCLR function When programmed the MCLR function is tied to the internal VDD and the pin is assigned to be a GPIO See Figure 7 7 When pin GP3 MCLR VPP is configured as MCLR the internal pull up is always on FIGURE 7 7 MCLR SELECT L WEAK PULL UP D q INTERNAL MCLR GP3 MCLR VPP 7 4 Power On Reset POR The PIC12C5XX family incorporates on chip Power On Reset POR circuitry which provides an internal chip reset for most power up situations The on chip POR circuit holds the chip in reset until VDD has reached a hig
97. nd VDD are tied together or the pin is programmed to be GP3 The Vpp is stable before the start up timer times out and there is no problem in getting a proper reset However Figure 7 11 depicts a problem situation where Vpp rises too slowly The time between when the DRT senses that MCLR is high and when MCLR and VDD actually reach their full value is too long In this situation when the start up timer times out VDD has not reached the VpD min value and the chip is therefore not guaranteed to function correctly For such situations we recommend that external RC circuits be used to achieve longer POR delay times Figure 7 10 Note When the device starts normal operation exits the reset condition device operat ing parameters voltage frequency tem perature etc must be meet to ensure operation If these conditions are not met the device must be held in reset until the operating conditions are met For additional information refer to Application Notes Power Up Considerations AN522 and Power up Trouble Shooting AN607 DS40139D page 32 1998 Microchip Technology Inc PIC12C5XX FIGURE 7 8 SIMPLIFIED BLOCK DIAGRAM OF ON CHIP RESET CIRCUIT Power Up Detect VDD POR Power On Reset Pin Change Wake up on pin change SLEEP Z Be WDT Time out MCLRE GP3 MCLR VPP 8 bit Asynch On Chip Ripple Counter
98. ng FSR I location select Data OFh Addresses map back to addresses in Bank 0 Memory 10h 1Fh 3Fh BankO Bank 1 2 Note 1 For register map detail see Section 4 2 Note 2 PIC12C509 A only DS40139D page 20 1998 Microchip Technology Inc PIC12C5XX 5 0 I O PORT As with any other register the I O register can be written and read under program control However read instructions e g MOVF GPIO W always read the I O pins independent of the pin s input output modes On RESET all I O ports are defined as input inputs are at hi impedance since the I O control registers are all set 5 1 GPIO GPIO is an 8 bit I O register Only the low order 6 bits are used GP5 GP0 Bits 7 and 6 are unimplemented and read as Os Please note that GP3 is an input only pin The configuration word can set several l O s to alternate functions When acting as alternate functions the pins will read as 0 during port read Pins GPO GP1 and GP3 can be configured with weak pull ups and also with wake up on change The wake up on change and weak pull up functions are not pin selectable If pin 4 is configured as MCLR weak pull up is always on and wake up on change for this pin is not enabled 5 2 TRIS Register The output driver control register is loaded with the contents of the W register by executing the TRIS f instruction A 1 from a TRIS register bit puts the cor
99. ng the TOCS bit OPTION lt 5 gt In timer mode the TimerO module will increment every instruction cycle without prescaler If TMRO register is written the increment is inhibited for the following two instruction cycles Figure 6 2 and Figure 6 3 The user can work around this by writing an adjusted value to the TMRO register FIGURE 6 1 TIMERO BLOCK DIAGRAM GP2 TOCKI Fosc 4 Pin Programm Prescale 3 PS2 PS1 PSO 70060 Counter mode is selected by setting the TOCS bit OPTION lt 5 gt In this mode TimerO will increment either on every rising or falling edge of pin TOCKI The TOSE bit OPTION lt 4 gt determines the source edge Clearing the TOSE bit selects the rising edge Restrictions on the external clock input are discussed in detail in Section 6 1 The prescaler may be used by either the TimerO module or the Watchdog Timer but not both The prescaler assignment is controlled in software by the control bit PSA OPTION lt 3 gt Clearing the PSA bit will assign the prescaler to TimerO The prescaler is not readable or writable When the prescaler is assigned to the TimerO module prescale values of 1 2 1 4 1 256 are selectable Section 6 2 details the operation of the prescaler A summary of registers associated with the TimerO module is found in Table 6 1 Data bus 8 Sync with Internal TMRO reg Clocks PSout 2 Tcv delay Syne PSA Note
100. o ftp ftp futureone com pub microchip The web site and file transfer site provide a variety of services Users may download files for the latest Development Tools Data Sheets Application Notes User s Guides Articles and Sample Programs A vari ety of Microchip specific business information is also available including listings of Microchip sales offices distributors and factory representatives Other data available for consideration is Latest Microchip Press Releases Technical Support Section with Frequently Asked Questions Design Tips Device Errata Job Postings Microchip Consultant Program Member Listing Links to other useful web sites related to Microchip Products Conferences for products Development Systems technical information and more Listing of seminars and events Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides System users a listing of the latest versions of all of Microchip s development systems software products Plus this line provides information on how customers can receive any currently available upgrade kits The Hot Line Numbers are 1 800 755 2345 for U S and most of Canada and 1 602 786 7302 for the rest of the world 980106 Trademarks The Microchip name logo PIC PICSTART PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U S A and other countries PICmicro FlexROM MPLAB and fuzzy LAB
101. o calibrate the internal 4 MHz oscillator It contains four to six bits for calibration Increasing the cal value increases the frequency See Section 7 2 5 for more information on the internal oscillator FIGURE 4 6 OSCCAL REGISTER ADDRESS 8Fh R W 0 R W 1 R W 1 R W 1 R W 0 R W 0 U 0 U 0 CAL3 CAL2 cas CALO R Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 4 CAL lt 3 0 gt Calibration bit 3 0 Unimplemented Read as 0 FIGURE 4 7 OSCCAL REGISTER ADDRESS 8Fh PIC12C508A C509A R W 1 R W 0 R W 0 R W 0 R W 0 R W 0 U 0 U 0 CAL5 CAL4 CAL3 CAL2 CAL1 CALO R Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 2 CAL lt 5 0 gt Calibration bit 1 0 Unimplemented Read as DS40139D page 18 1998 Microchip Technology Inc PIC12C5XX 4 6 Program Counter As a program instruction is executed the Program Counter PC will contain the address of the next program instruction to be executed The PC value is increased by one every instruction cycle unless an instruction changes the PC For a GOTO instruction bits 8 0 of the PC are provided by the GoTo instruction word The PC Latch PCL is mapped to PC lt 7 0 gt Bit 5 of the STATUS register provides page information to bit 9 of the PC
102. ode for all Microchip microcontrollers Macro assembly capability Produces all the files Object Listing Symbol and special required for symbolic debug with Microchip s emulator systems Supports Hex default Decimal and Octal source and listing formats MPASM provides a rich directive language to support programming of the PICmicro Directives are helpful in making the development of your assemble source code shorter and more maintainable 9 12 Software Simulator MPLAB SIM The MPLAB SIM Software Simulator allows code development in a PC host environment It allows the user to simulate the PlCmicro series microcontrollers on an instruction level On any given instruction the user may examine or modify any of the data areas or provide external stimulus to any of the pins The input output radix can be set by the user and the execution can be performed in single step execute until break or in a trace mode MPLAB SIM fully supports symbolic debugging using MPLAB C17 and MPASM The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi project software development tool 9 13 MPLAB C17 Compiler The MPLAB C17 Code Development System is a complete ANSI C compiler and integrated develop ment environment for Microchip s PIC17CXXX family of microcontrollers The compiler provides powerful inte gration capabilities and ease
103. of use not found with other compilers For easier source level debugging the compiler pro vides symbol information that is compatible with the MPLAB IDE memory display 9 14 Fuzzy Logic Development System fuzzyTECH MP fuzzyTECH MP fuzzy logic development tool is avail able in two versions a low cost introductory version MP Explorer for designers to gain a comprehensive working knowledge of fuzzy logic system design and a full featured version fuzzyTECH MP Edition for imple menting more complex systems Both versions include Microchip s fuzzyLABM demon stration board for hands on experience with fuzzy logic Systems implementation 9 15 SEEVAL Evaluation and Programming System The SEEVAL SEEPROM Designers Kit supports all Microchip 2 wire and 3 wire Serial EEPROMs The kit includes everything necessary to read write erase or program special features of any Microchip SEEPROM product including Smart SerialsTM and secure serials The Total Endurance Disk is included to aid in trade off analysis and reliability calculations The total kit can significantly reduce time to market and result in an optimized system 1998 Microchip Technology Inc DS40139D page 53 PIC12C5XX 9 16 KEELOG Evaluation and Programming Tools KEELOO evaluation and programming tools support Microchips HCS Secure Data Products The HCS eval uation kit includes an LCD display to show changing codes a de
104. ogy Inc DS40139D page 75 PIC12C5XX FIGURE 11 8 loL vs VOL VDD 5 5 V 50 Max 40 C 40 30 T E a UR 20 Min 85 C Min 125 C 10 0 250 0m 500 0m 750 0m 1 0 VoL Volts NOTES LE 2 DS40139D page 76 1998 Microchip Technology lnc PIC12C5XX 12 0 ELECTRICAL CHARACTERISTICS PIC12C508A PIC12C509A PIC12LC508A PIC12LC509A Absolute Maximum Ratingst Ambient Temperature under bias sise 40 C to 125 C Storage Temperature 4 acit dite ce ec ted ha nn sf dece diu din a gt 65 C to 4150 C Voltage on VDD with resp ctto VSS ii see eee a ae Se oe cut a gies 0 to 47 0 V Voltage on MCLR with respect to VSS ran s ra 0 to 414 V Voltage on all other pins with respect to VSS sssee eene eene Total Power Dissipation E Max G rrent oUt of VSS pili ie deci ie adea terne annee case id Bee ee renege a Max Output Current sourced by any I O pin Ned Max Output Current sourced by I O port GPIO NA This is a stress rating only and functional operation of the device al indicated in the operation listings of this specification ig notimplis extended periods may affect device reliability hose orany other conditions above those Exposure to maximum rating conditions for 1998 Microchip Techn
105. ology Inc Preliminary DS40139D page 77 PIC12C5XX 12 1 DC CHARACTERISTICS PIC12C508A 509A Commercial PIC12C508A 509A Industrial PIC12C508A 509A Extended Standard Operating Conditions unless otherwise sp d DC Characteristics Operating Temperature 0 C lt TA lt 70 C commercial Power Supply Pins 40 C lt TA lt 85 C in ial 40 C TA 125 C Characteristic Sym Min Typ Max Units Supply Voltage VDD 3 0 5 5 V Fosc DC to 4 ommercial Industrial Extende RAM Data Retention VDR 1 5 V DewWicev Voltage VDD Start Voltage to ensure VPOR Vss V See settio on Power on Reset for details Power on Reset VDD Rise Rate to ensure Svpp 0 05 S ee section on Power on Reset for details Power on Reset XT and EXTRC options Note 4 SC 4 MHz VDD 5 5V TRC Option Fosc 4 MHz VDD 5 5V LP OPTION Commercial Temperature Fosc 32 kHz VDD 3 0V WDT disabled LP OPTION Industrial Temperature Fosc 32 kHz VDD 3 0V WDT disabled LP OPTION Extended Temperature Fosc 32 kHz VDD 3 0V WDT disabled VDD 3 0V Commercial VDD 3 0V Industrial VDD 3 0V Extended VDD 3 0V Commercial VDD 3 0V Industrial VDD 3 0V Extended Supply Current IDD These parameters raeterizgtNbut not tested Note 1 lumn is based on characterization results at 25 C This data is for design guid ed 2 VDD can be lowered in SLEEP mode w
106. ons Consequently all instructions 33 execute in a single cycle 1116 4MHz except for program branches The table below lists program memory EPROM and data memory RAM for each PIC12C5XX device Device EPROM RAM PIC12C508 512 x 12 25 PIC12C508A 512 x 12 25 PIC12C509 1024 x 12 41 PIC12C509A 1024 x 12 41 The PIC12C5XX can directly or indirectly address its register files and data memory All special function registers including the program counter are mapped in the data memory The PIC12C5XX has a highly orthogonal symmetrical instruction set that makes it possible to carry out any operation on any register using any addressing mode This symmetrical nature and lack of special optimal situations make programming with the PIC12C5XX simple yet efficient In addition the learning curve is reduced significantly The PIC12C5XX device contains an 8 bit ALU and working register The ALU is a general purpose arithmetic unit It performs arithmetic and Boolean functions between data in the working register and any register file The ALU is 8 bits wide and capable of addition subtraction shift and logical operations Unless otherwise mentioned arithmetic operations are two s complement in nature In two operand instructions typically one operand is the W working register The other operand is either a file register or an immediate constant In single operand instructions the operand is either t
107. page 34 1998 Microchip Technology Inc PIC12C5XX 7 6 1 WDT PERIOD The WDT has a nominal time out period of 18 ms with no prescaler If a longer time out period is desired a prescaler with a division ratio of up to 1 128 can be assigned to the WDT under software control by writing to the OPTION register Thus a time out period of a nominal 2 3 seconds can be realized These periods vary with temperature VDD and part to part process variations see DC specs Under worst case conditions VDD Min Temperature Max max WDT prescaler it may take several seconds before a WDT time out occurs 7 6 2 WDT PROGRAMMING CONSIDERATIONS The CLRWDT instruction clears the WDT and the postscaler if assigned to the WDT and prevents it from timing out and generating a device RESET The SLEEP instruction resets the WDT and the postscaler if assigned to the WDT This gives the maximum SLEEP time before a WDT wake up reset FIGURE 7 12 WATCHDOG TIMER BLOCK DIAGRAM From TimerO Clock Source Figure 6 5 F Watchdog 1 F Timer E U xc WDT Enable PSA Configuration Bit I Postscaler 8 to MUX PS2 PSO To Timer 0 Figure 6 4 MUX PSA WDT Time out TABLE 7 6 SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Value on Value on Power On A
108. ption GPO 7 7 O TTL ST Bi directional I O port serial programming data Can be software programmed for internal weak pull up and wake up from SLEEP on pin change This buffer is a Schmitt Trigger input when used in serial programming mode GP1 O TTL ST Bi directional I O port serial programming clock Can be software programmed for internal weak pull up and wake up from SLEEP on pin change This buffer is a Schmitt Trigger input when used in serial programming mode GP2 TOCKI O ST Bi directional I O port Can be configured as TOCKI GP3 MCLR VPP TTL ST Input port master clear reset input programming volt age input When configured as MCLR this pin is an active low reset to the device Voltage on MCLR VPP must not exceed VDD during normal device operation or the device will enter programming mode Can be software programmed for internal weak pull up and wake up from SLEEP on pin change Weak pull up always on if configured as MCLR ST when in MCLR mode GP4 OSC2 O TTL Bi directional I O port oscillator crystal output Con nections to crystal or resonator in crystal oscillator mode XT and LP modes only GPIO in other modes GP5 OSC1 CLKIN O TTL ST Bidirectional IO port oscillator crystal input external clock source input GPIO in Internal RC mode only OSC1 in all other oscillator modes TTL input when GPIO ST input in external RC oscillator mo
109. r High Time 50 ns XT oscillator 2 ms LP oscillator Clock in OSC1 Rise or Fall Time 25 ns XT oscillator 50 ns LP oscillator lt b e parameters are characterized but not tested te Data in the Typical Typ column is at 5V 25 C unless otherwise stated These parameters are for design idance only and are not tested Zx Al specified values are based on characterization data for that particular oscillator type under standard oper ating conditions with the device executing code Exceeding these specified limits may result in an unstable oscillator operation and or higher than expected current consumption When an external clock input is used the max cycle time limit is DC no clock for all devices 3 Instruction cycle period 10 equals four times the input oscillator time base period DS40139D page 86 Preliminary 1998 Microchip Technology Inc PIC12C5XX TABLE 12 3 CALIBRATED INTERNAL RC FREQUENCIES PIC12C508A C509A AC Characteristics Standard Operating Conditions unless otherwise specified Operating Temperature 0 C lt TA x 70 C commercial 40 C lt TA 85 C industrial 40 C lt TA 125 C extended Operating Voltage VDD range is described in Section 10 1 Parameter No Sym Characteristic Min Typ Max Units Conditions Internal Calibrated RC Frequency TBD 4 00 TBD MHz V D 58V
110. r f Words 1 Cycles 1 Example RRF REG1 0 Before Instruction REGI 1110 0110 C 0 After Instruction REGI 1110 0110 W 0111 0011 C 0 1998 Microchip Technology Inc DS40139D page 47 PIC12C5XX SLEEP Enter SLEEP Mode Syntax labe SLEEP Operands None Operation 00h 2 WDT 0 WDT prescaler 1 TO 0 PD Status Affected TO PD GPWUF Encoding 0000 0000 0011 Description Time out status bit TO is set The power down status bit PD is cleared GPWUF is unaffected The WDT and its prescaler are cleared The processor is put into SLEEP mode with the oscillator stopped See sec tion on SLEEP for more details Words 1 Cycles 1 Example SLEEP SUBWF Subtract W from f Syntax labe SUBWF fd Operands 0 lt f lt 31 d e 0 1 Operation f W dest Status Affected C DC Z Encoding 0000 10df fft Description Subtract 2 s complement method the W register from register f If d is 0 the result is stored in the W register If is 1 the result is stored back in register f Words 1 Cycles 1 Example 1 SUBWF REG1 1 Before Instruction REG1 3 W 2 6 After Instruction REG1 1 W 2 C 1 result is positive Example 2 Before Instruction REG1 2 W B 2 6 After Instruction REG1 M 0 W 2 C result is zero Example 3 Before Instruction REG1 1 W 2 6 After Instruction REG1 FF W 2 C 0
111. racteristic Sym Min Typ Max Units Conditions No T utput High Voltage DO90 I O ports CLKOUT Note 3 VoH VDD 0 7 IOH 3 0 mA VOD 4 5V DO90A VDD 0 7 D092 JOSC2 VDD 0 7 DO92A VDD 0 7 Capacitive Loading Specs on Output Pins D100 OSC2 pin Cosc2 and LP modes when clock is used to drive D101 m All I O pins and OSC2 Clo Data in Typ column is at 5V 25 C unless otherwise stated 3 ameters are for design guidance only and are not tested Note 1 In EXTRC oscillator configuration the OSC1 CLKIN pi gger input It is not recommended that the PIC12C5XX be driven with external clock in RC A 2 The leakage current on the MCLR pin is stro g applied voltage level The specified levels represent normal operating conditions Higher te nt may be measured at different input voltages 3 4 Extended operating range is Advance Informe 5 When configured as external reset Me inputlggk ge cujrent is the weak pulll up current of 10mA minimum W 1998 Microchip Technology Inc Preliminary DS40139D page 81 PIC12C5XX 12 4 DC CHARACTERISTICS PIC12LC508A 509A Commercial Industrial Standard Operating Conditions unless otherwise specified Operating temperature OC lt TA 70 C commercia DC CHARACTERISTICS 40 C lt TA lt 85 C indyste Operating voltage VDD range as described in DC tich 12 1 and Section 12 2 Param Characteristic Sym Min Typ Max Units nditions No Input Low Vol
112. rammer and easily test firm ware The user can also connect the PICDEM 1 board to the MPLAB ICE emulator and download the firmware to the emulator for testing Additional proto type area is available for the user to build some addi tional hardware and connect it to the microcontroller socket s Some of the features include an RS 232 interface a potentiometer for simulated analog input push button switches and eight LEDs connected to PORTB 9 8 PICDEM 2 Low Cost PIC16CXX Demonstration Board The PICDEM 2 is a simple demonstration board that supports the PIC16C62 PIC16C64 PIC16C65 PIC16C73 and PIC16C74 microcontrollers All the necessary hardware and software is included to run the basic demonstration programs The user can program the sample microcontrollers provided with the PICDEM 2 board on a PRO MATE II pro grammer or PICSTART Plus and easily test firmware The MPLAB ICE emulator may also be used with the PICDEM 2 board to test firmware Additional prototype area has been provided to the user for adding addi tional hardware and connecting it to the microcontroller socket s Some of the features include a RS 232 inter face push button switches a potentiometer for simu lated analog input a Serial EEPROM to demonstrate usage of the 12C bus and separate headers for connec tion to an LCD module and a keypad 9 9 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 is a simple demonstration board that
113. responding output driver in a hi impedance mode A 0 puts the contents of the output data latch on the selected pins enabling the output buffer The exceptions are GP3 which is input only and GP2 which may be controlled by the option register see Figure 4 5 Note Aread of the ports reads the pins not the output data latches That is if an output driver on a pin is enabled and driven high but the external system is holding it low a read of the port will indicate that the pin is low The TRIS registers are write only and are set output drivers disabled upon RESET 5 3 I O Interfacing The equivalent circuit for an I O port pin is shown in Figure 5 1 All port pins except GP3 which is input only may be used for both input and output operations For input operations these ports are non latching Any input must be present until read by an input instruction e g MOVF GPIO W The outputs are latched and remain unchanged until the output latch is rewritten To use a port pin 86 output the corresponding direction control bit in TRIS must be cleared 0 For use as an input the corresponding TRIS bit must be set Any I O pin except GP3 can be programmed individually as input or output FIGURE 5 1 EQUIVALENT CIRCUIT FOR A SINGLE I O PIN RD Port Note 1 O pins have protection diodes to VDD and Vss 2 See Table 3 1 for buffer type
114. s 5 oer tH te einn INDE RR Indirect Data Addressing Instruction Cycle Instruction Flow Pipelining Instruction Set Summary K KeeLoq Evaluation and Programming Tools 54 L Loading of PC mieten toner teen 19 M Memory Organization 13 Data Memory Program Memory 13 MPLAB Integrated Development Environment Software 53 0 OPTION Register nre te etg OSG selection erre rini OSCCAL Register Oscillator Configurations Oscillator Types Package Marking Information 95 Packaging Information 95 PICDEM 1 Low Cost PICmicro Demo Board a PICDEM 2 Low Cost PIC16CXX Demo Board 52 PICDEM 3 Low Cost PIC16CXXX Demo Board 2452 PICSTART Plus Entry Level Development System 51 POR Prescaler me PRO MATES II Universal Programmer 51 Program Counter eire her iret i Hte 19 Q A 12 R RC Oscillator essen 29 Read Modify Write 22 Register File Map isiseeereereesreerresrrereesreertesrsrressseesssass 14 Registers Special Function sse 15 Reset Reset on Brown Out S SEEVAL Evaluation and Programming System 53 SLEEP EE 27 37 Software Simulator MPLAB SIM DD Special Features
115. st for current devices describing minor operational differences from the data sheet and recommended workarounds As device documentation issues become known to us we will publish an errata sheet The errata will specify the revi sion of silicon and revision of document to which it applies To determine if an errata sheet exists for a particular device please check with one of the following e Microchip s Worldwide Web site http Awww microchip com Your local Microchip sales office see last page The Microchip Corporate Literature Center U S FAX 602 786 7277 When contacting a sales office or the literature center please specify which device revision of silicon and data sheet include lit erature number you are using Corrections to this Data Sheet We constantly strive to improve the quality of all our products and documentation We have spent a great deal of time to ensure that this document is correct However we realize that we may have missed a few things If you find any information that is missing or appears in error please Fill out and mail in the reader response form in the back of this data sheet E mail us at webmaster microchip com We appreciate your assistance in making this a better document 1998 Microchip Technology Inc DS40139D page 3 PIC12C5XX 1 0 GENERAL DESCRIPTION The PIC12C5XX from Microchip Technology is a family of low cost high performance 8 bit fully static EPROM
116. t W TOS 3 PC None 1000 ES ES The W register is loaded with the eight bit literal k The program counter is loaded from the top of the stack the return address This is a two cycle instruction 1 2 CALL TABLE W contains table offset value W now has table value ADDWF PC W offset RETLW k1 Begin table RETLW k2 RETLW kn End of table Before Instruction W 0x07 After Instruction W value of k8 RLF Rotate Left f through Carry Syntax label RLF fd Operands 0 lt f lt 31 de 0 1 Operation See description below Status Affected C Encoding 0011 01df ffff Description The contents of register f are rotated one bit to the left through the Carry Flag If d is 0 the result is placed in the W register If d is 1 the result is stored back in register f C register f j Words 1 Cycles 1 Example RLF REG1 0 Before Instruction REGI 1110 0110 C 0 After Instruction REGI 1110 0110 W 1100 1100 C 3L RRF Rotate Right f through Carry Syntax label RRF fd Operands 0 lt f lt 31 de 0 1 Operation See description below Status Affected C Encoding 0011 00df ffff Description The contents of register are rotated one bit to the right through the Carry Flag If d is O the result is placed in the W register If d is 1 the result is placed back in register f C I registe
117. tage I O ports VIL D030 with TTL buffer Vss 0 5V V D031 with Schmitt Trigger buffer Vss 0 2VD D032 MCLR GP2 TOCKI AN2 INT Vss 0 2VD in EXTRC mode 0033 OSC1 in XT HS and LP Vss A 3VDD V ote1 Input High Voltage I O ports VIH D040 with TTL buffer 4 5 lt VDD 5 5V D040A For VDD 5 5V or VDD 4 5V D041 with Schmitt Trigger buffer For entire VDD range D042 MCLR GP2 TOCKI AN2 INT D042A OSC1 XT HS and LP 0043 OSC1 in EXTRC mode Note1 D070 GPIO weak pull up current uA VDD 5V VPIN VSS Input Leakage Current Notes 2 0060 1 2 ports IL BD TBD TBD LA Vss lt VPIN VDD Pin at hi impedance D061 MCLR GP2 TOCKI D TBD TBD uA Vss x VPIN lt VDD D063 OSC1 TBD TBD TBD pA Vss lt VPIN lt VDD XT HS and LP osc configuration Output Low Voltag D080 I O ports CLKOU OL TBD V loi 8 5 mA VDD 4 5V 40 C to 85 C DO80A 0 6 V oi 7 0 mA VDD 4 5V 40 C to 125 C 0083 OSC2 0 6 V oi 1 6 mA VDD 4 5V 40 C to 85 C D083A 0 6 V_jloL 1 2 mA VDD 4 5V 2 40 C to 125 C T air is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Ca XTRG ossillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that PIC12C67X be driven with external clock in RC mode e leakage current on the MCLR pin is strongly
118. the correct part number 2 1 UV Erasable Devices The UV erasable version offered in ceramic side brazed package is optimal for prototype development and pilot programs The UV erasable version can be erased and reprogrammed to any of the configuration modes Note Please note that erasing the device will also erase the pre programmed internal calibration value for the internal oscillator The calibration value must be saved prior to erasing the part Microchip s PICSTART PLUS and PRO MATE pro grammers all support programming of the PIC12C5XX Third party programmers also are available refer to the Microchip Third Party Guide for a list of sources 2 2 One Time Programmable OTP Devices The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates or small volume applications The OTP devices packaged in plastic packages permit the user to program them once In addition to the program memory the configuration bits must also be programmed 2 3 Quick Turnaround Production QTP Devices Microchip offers a QTP Programming Service for factory production orders This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized The devices are identical to the OTP devices but with all EPROM locations and fuse options already programmed by the factory Certain code and protot
119. tions INTRC Internal 4 MHz RC oscillator EXTRC External low cost RC oscillator XT Standard crystal resonator LP Power saving low frequency crystal CMOS Technology Low power high speed CMOS EPROM technology Fully static design Wide operating voltage range Wide temperature range Commercial 0 C to 70 C Industrial 40 C to 85 C Extended 40 C to 125 C Low power consumption 2mA 5V 4 MHz 15 uA typical 3V 32 KHZ lt 1 uA typical standby current Pin Diagram PDIP SOIC Windowed Ceramic Side Brazed VDD GP5 OSC1 CLKIN a GP4 OSC2 GP3 MCLR VPP gt lt GP2 TOCKI W 60SOZLOld v 80S0Z19Id 1998 Microchip Technology Inc DS40139D page 1 PIC12C5XX Device Differences VOR Oscillator Process Device age Oscillator Calibration Technology ange Bits Microns PIC12C508A 3 0 5 5 See Note 1 6 0 7 PIC12LC508A 2 5 5 5 See Note 1 6 0 7 PIC12C508 2 5 5 5 See Note 1 4 0 9 PIC12C509A 3 0 5 5 See Note 1 6 0 7 PIC12LC509A 2 5 5 5 See Note 1 6 0 7 PIC12C509 2 5 5 5 See Note 1 4 0 9 Note 1 If you change from the PIC12C50X to the PIC12C50XA please verify oscillator characteristics in your appli cation Note 2 See Section 7 2 5 for OSCCAL implementation differences ee ee CO Ol E ely DS40139D page 2 1998 Microchip Technology Inc PIC12C5XX TABLE OF CONTE
120. tools a low cost development programmer and a full fea tured programmer All the tools are supported on IBM PC and compatible machines 1 1 Applications The PIC12C5XX series fits perfectly in applications ranging from personal care appliances and security Systems to low power remote transmitters receivers The EPROM technology makes customizing applica tion programs transmitter codes appliance settings receiver frequencies etc extremely fast and conve nient The small footprint packages for through hole or surface mounting make this microcontroller series per fect for applications with space limitations Low cost low power high performance ease of use and O flex ibility make the PIC12C5XX series very versatile even in areas where no microcontroller use has been considered before e g timer functions replacement of glue logic and PLD s in larger systems coproces sor applications DS40139D page 4 1998 Microchip Technology Inc PIC12C5XX TABLE 1 1 Maximum Frequency of Operation MHz PIC12CXXX amp PIC12CEXXX FAMILY OF DEVICES PIC12C508 A PIC12C509 A PIC12CE518 PIC12CE519 PIC12C671 10 PIC12C672 10 PIC12CE673 10 PIC12CE674 10 EPROM Program Memory 512 x 12 1024 x 12 512x 12 1024 x 12 1024 x 14 2048 x 14 1024 x 14 2048 x 14 RAM Data Memory bytes 41 25 41 128 128 128 128 EEPROM Data Me
121. ts Assigned to lt gt Register bit field In the set of italics User defined term font is courier All instructions are executed within a single instruction cycle unless a conditional test is true or the program counter is changed as a result of an instruction In this case the execution takes two instruction cycles One instruction cycle consists of four oscillator periods Thus for an oscillator frequency of 4 MHz the normal instruction execution time is 1 116 If a conditional test is true or the program counter is changed as a result of an instruction the instruction execution time is 2 Lis Figure 8 1 shows the three general formats that the instructions can have All examples in the figure use the following format to represent a hexadecimal number Oxhhh where h signifies a hexadecimal digit FIGURE 8 1 GENERAL FORMAT FOR INSTRUCTIONS Byte oriented file register operations 11 6 5 4 OPCODE d f FILE d 0 for destination W d 1 for destination f f 5 bit file register address Bit oriented file register operations 11 87 54 OPCODE b BIT FILE bit bit address bit file register address Literal and control operations except GOTO 11 8 7 OPCODE k literal k 8 bit immediate value Literal and control operations GOTO instruction 11 9 8 0 OPCODE k literal k 9 bit immediate value
122. um based machines under Windows 3 x Windows 95 or Win dows NT environment ICEPIC features real time non intrusive emulation 9 4 PRO MATE II Universal Programmer The PRO MATE II Universal Programmer is a full fea tured programmer capable of operating in stand alone mode as well as PC hosted mode PRO MATE Il is CE compliant The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability It has an LCD display for displaying error messages keys to enter commands and a modular detachable socket assembly to support various package types In stand alone mode the PRO MATE 11 can read verify or pro gram PIC12CXXX PIC14C000 PIC16C5X PIC16CXXX and PIC17CXX devices It can also set configuration and code protect bits in this mode 9 5 PICSTART Plus Entry Level Development System The PICSTART programmer is an easy to use low cost prototype programmer It connects to the PC via one of the COM RS 232 ports MPLAB Integrated Development Environment software makes using the programmer simple and efficient PICSTART Plus is not recommended for production programming PICSTART Plus supports all PIC12CXXX PIC14C000 PIC16C5X PIC16CXXX and PIC17CXX devices with up to 40 pins Larger pin count devices such as the PIC16C923 PIC16C924 and PIC17C756 may be sup ported with an adapter socket PICSTART Plus is CE compliant 1998 Micro
123. ype verification procedures do apply before production shipments are available Please con tact your local Microchip Technology sales office for more details 2 4 Serialized Quick Turnaround Production SQTP Devices Microchip offers a unique programming service where a few user defined locations in each device are programmed with different serial numbers The serial numbers may be random pseudo random or seguential Serial programming allows each device to have a unigue number which can serve as an entry code password or ID number 1998 Microchip Technology lnc DS40139D page 7 PIC12C5XX NOTES DS40139D page 8 1998 Microchip Technology Inc PIC12C5XX 3 0 ARCHITECTURAL OVERVIEW The high performance of the PIC12C5XX family can be attributed to a number of architectural features commonly found in RISC microprocessors To begin with the PIC12C5XX uses a Harvard architecture in which program and data are accessed on separate buses This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus Separating program and data memory further allows instructions to be sized differently than the 8 bit wide data word Instruction opcodes are 12 bits wide making it possible to have all single word instructions A 12 bit wide program memory access bus fetches a 12 bit instruction in a single cycle A two stage pipeline overlaps fetch and execution of instructi

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