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MICROCHIP PIC16C64X PIC16C66X handbook

1. dd NY TOWN U r o gt RAS AN3 Bs Lu fr 22 lt lt lt lt co 5 4 w RAO ANO L 4 MCLR VPP PIC16C66X 18 19 20 21 2223 242526 27 28 0dSd 0QH lt lt gt dSd EQu gt gt LL 2 gt lt _ lt NC RCO OSC2 CLKOUT OSC1 CLKIN Vss 2 5 RE1 WR REO RD RA5 RA4 TOCKI RB3 RB2 RB1 RBO INT VDD Vss RD7 PSP7 RD6 PSP6 RD5 PSP5 RD4 PSP4 RC7 DS30559A page 2 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X Table of Contents 1 0 General Description A 5 2 0 PIC16C64X 8 PIC16C66X Device Varieties sise 7 3 0 Architectural OVerVieW seeded agde ated u horia ah 9 4 0 Memory Orgahizalion dade Ho ede epe ieee de a eth 17 5 0 Meyer MR ENS 29 6 0 Timer tres 41 7 0 Comparator Mod le sc ooi A na deren 47 8 0 Voltage 6 ennemie ln 53 9 0 Special Feat
2. 87 On chip Reset Circuit 59 Device Drawings Parallel Slave Port PORTD PORTE 39 28 Lead Ceramic CERDIP Dual In line with Win M M 10 dow 300 mil 107 PIC160642 ac on ent 10 28 Lead Ceramic Dual In Line with Window JW PIC 16 C661 Re D atin 11 300 mil e 107 OD BER ko do sos O t 11 28 Lead Plastic Small Outline 50 Wide 300 mil PORTC In Port Mode 34 Body 106 PORTD In I O Port Mode 35 28 Lead Skinny Plastic Dual In Line SP PORTE In Port Mode 37 300 mil 105 PINS 5 A UE 29 40 Lead Ceramic Dual In Line with Window pin JW 600 108 RM pin 40 Lead Plastic Dual In Line P 600 mil 109 RB3 RB ds 32 44 Lead Plastic Leaded Chip Carrier L RB7 RB4 DIS castae em 32 s x ire Rh 110 Oscillator 58 44 Lead Plastic Quad Flatpack PQ 10x10x2 Single Comparator oss eaa asas 49 mm Body 1 6 0 15 mm Lead Form 111 Dur amsn onen 41 TimerO WDT Prescaler 44 Voltage Reference 53 Famil
3. 35 Summary of Registers Associated with PORTD 35 PORTE F nctions dunes 37 Summary of Registers Associated with PORTE tak m s 37 Registers Associated with Parallel Slave Port39 Registers Associated with Timer 45 Registers Associated with Comparator 52 Registers Associated with Voltage Reference54 Capacitor Selection for Ceramic Resonators Preliminary eene 57 Capacitor Selection for Crystal Oscillator Preliminary sisi Time out in Various Situations Status Bits and Their Significance Initialization Condition for Special Registers 62 Initialization Condition for Registers 63 Opcode Field Descriptions 25178 Instruction Set 75 Development Tools From Microchip 90 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation Commercial Devices Comparator Voltage Reference Specifications External Clock Timing Requirements 98 CLKOUT and I O Timing Requirements 99 Reset Watchdog Timer Oscillator Start up Tim er Power up Timer and Brown out Reset Re quirements eee eee eee 100 0 Clock Requirements
4. RD PORT gt Note 1 O pins have protection diodes to VDD and Vss TABLE 5 7 PORTD FUNCTIONS Name Bit Buffer Type Function RDO PSPO bitO ST TTL Input output port pin or parallel slave port bitO RD1 PSP1 ST TTLO Input output port pin or parallel slave port bit RD2 PSP2 bit2 ST TTL Input output port pin or parallel slave port bit2 RD3 PSP3 bit3 ST TTLO Input output port pin or parallel slave port bit3 RD4 PSP4 bit4 ST TTL Input output port pin or parallel slave port bit4 RD5 PSP5 bit5 ST TTL Input output port pin or parallel slave port bit5 RD6 PSP6 bit6 ST TTLO Input output port pin or parallel slave port bit6 RD7 PSP7 bit7 ST TTLO Input output port pin or parallel slave port bit7 Legend ST Schmitt Trigger input TTL TTL input Note 1 Input buffers are Schmitt Triggers when in mode and TTL buffers when in Parallel Slave Port Mode TABLE 5 8 SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR other resets BOR 08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RDO xxxx xxxx uuuu uuuu 88h TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISDO 1111 1111 1111 1111 89h TRISE IBF OBF PSPMODE TRISE2 TRISE1 TRISEO 0000 111 0000 111 Legend x unknown u unchanged unim
5. 56 Figure 9 2 Crystal Operation or Ceramic Resonator HS XT or LP Osc Configuration 57 Figure 9 3 External Clock Input Operation HS XT or LP Osc 57 Figure 9 4 External Parallel Resonant Crystal Oscillator Cirt 58 Figure 9 5 External Series Resonant Crystal Oscillator al Gee Figure 9 6 RC Oscillator Mode Figure 9 7 Simplified Block Diagram of On chip Reset nece 59 Figure 9 8 Brown out Situations 60 Figure 9 9 Time out Sequence on Power up MCLR not tied to VDD Case 1 64 Figure 9 10 Time out Sequence on Power up MCLR not tied to VDD Case 2 64 Figure 9 11 Time out Sequence on Power up MCLR tied to VDD n 64 Figure 9 12 External Power on Reset Circuit For Slow VDD o te erepta idiei 65 Figure 9 13 External Brown out Protection Circuit 1 65 Figure 9 14 External Brown out Protection Circuit 2 65 Figure 9 15 Interrupt Logic 66 Figure 9 16 RBO INT Pin Interrupt Timing 67 Figure 9 17 Watchdog Timer Block Diagram 69 Figure 9 18 Summary of Watchdog Timer Registers 69 Figure 9 19 Wake up from Sleep Through Interrupt 70 Figure 9 20 Typical In Circui
6. Watchdog Timer WDT Enable bit WDT Time out Note TOCS TOSE PSA PS2 PS0 OPTION lt 5 0 gt DS30559A page 44 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 6 3 1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con To change prescaler from the WDT to the TimerO mod ule use the sequence shown in Example 6 2 trol i e it can be changed on the fly during program execution EXAMPLE 6 2 CHANGING PRESCALER WDT TIMERO Note To avoid an unintended device RESET the following instruction sequence shown in CLRWDT iClear WDT and Example 6 1 must be executed when iprescaler changing the prescaler assignment from BSE lc ME TimerO to the WDT This precaution must rprescale value be followed even if the WDT is disabled OPTION REG clock source BCF STATUS Bank 0 EXAMPLE 6 1 PRESCALER TIMERO WDT BCF STATUS Bank 0 CLRF TMRO Clear 6 Prescaler BSF STATUS RPO Bank 1 CLRWDT Clears WDT MOVLW 1 Select new prescale MOVWF OPTION REG value amp WDT BCF STATUS RPO Bank 0 TABLE 6 1 REGISTERS ASSOCIATED WITH TIMERO value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B
7. R Readable bit bit7 bitO W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit7 PSPIF Parallel Slave Port Interrupt Flag bit 1 A read or write operation has taken place must be cleared in software 0 No read or write operation has taken place bit 6 CMIF Comparator Interrupt Flag bit 1 Comparator input has changed must be cleared in software 0 Comparator input has not changed bit 5 0 Unimplemented Read as 0 Note 1 Bit PSPIF is reserved on the PIC16C641 642 always maintain this bit clear 1996 Microchip Technology Inc Preliminary DS30559A page 25 PIC16C64X amp PIC16C66X 4 2 2 6 PCON REGISTER The PCON register contains flag bits to differentiate Note BOR is unknown on Power on Reset It between a Power on Reset POR an external MCLR must then be set by the user and checked reset WDT reset Brown out Reset BOR and Parity on subsequent resets to see if BOH is Error Reset PER The PCON register also contains a cleared indicating a brown out has status bit MPEEN which reflects the value of the occurred The BOR status bit is a don t MPEEN bit in Configuration Word See Table 9 4 for care and is not necessarily predictable if status of these bits on various resets the brown out circuit is disabled by programming the BODEN bit in the Configuration word FIGURE 4 10 PCON REGISTER ADDRESS 8Eh R U U 0 U 0 U
8. I 9 8 2 WAKE UP USING INTERRUPTS When global interrupts are disabled GIE cleared and any interrupt source has both its interrupt enable bit and interrupt flag set one of the following events will If the interrupt occurs before the execution of a SLEEP instruction the SLEEP instruction will com plete as an Therefore the WDT and WDT postscaler will not be cleared the TO bit will not be set and PD bit will not be cleared Ifthe interrupt occurs during or after the execution of a SLEEP instruction the device will immediately wake up from sleep The SLEEP instruction will be completely executed before the wake up There fore the WDT and WDT postscaler will be cleared the TO bit will be set and the PD bit will be cleared Even if the flag bits were checked before executing a SLEEP instruction it may be possible for flag bits to become set before the SLEEP instruction completes To determine whether a SLEEP instruction executed test the PD bit If the PD bit is set the SLEEP instruction was executed as an NOP T To ensure that the WDT is clear a CLRWDT instruction should be executed before a SLEEP instruction FIGURE 9 19 WAKE UP FROM SLEEP THROUGH INTERRUPT 011 021 a3 a4 ail 021 asl 04 ail i ail aal a4 ai 021 03104 ail a2 03 04 011 021 031 04
9. Instruction Decode amp Control Timing Generation Timer Oscillator Start up Timer Power on Reset Power up Watchdog Timer Brown out Reset Parity Error Reset MCLR VDD 55 REO RD I RE1 WR gt RE2 CS 1996 Microchip Technology Inc Parallel Slave Port Preliminary FE 1 Comparator X RAO ANO lt x RA1 AN1 DT RA2 AN2 VREF lt A 0 x RA4 TOCKI RBO INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 RDO PSPO RD1 PSP1 RD2 PSP2 RD3 PSP3 RD4 PSP4 RD5 PSP5 RD6 PSP6 RD7 PSP7 DS30559A page 11 PIC16C64X amp PIC16C66X TABLE 3 1 PIC16C641 642 PINOUT DESCRIPTION Name Pin es pos Description OSC1 CLKIN 9 ST CMOS Oscillator crystal input or external clock source input OSC2 CLKOUT 10 O Oscillator crystal output Connects to crystal or resonator in crystal oscillator mode In RC mode OSC2 pin outputs CLKOUT which has 1 4 the frequency of OSC1 and denotes the instruction cycle rate MCLR VPP 1 ST Master clear reset input or programming voltage input This pin is
10. To Normal Connections 1996 Microchip Technology Inc Preliminary DS30559A page 71 PIC16C64X amp PIC16C66X NOTES F R _ ___ _ _ _ _ _ _ _ DS30559A page 72 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 10 0 INSTRUCTION SET SUMMARY Each PIC16CXX instruction is a 14 bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction The PIC16CXX instruction set summary in Table 10 2 lists byte oriented bit ori ented and literal and control operations Table 10 1 shows the opcode field descriptions For byte oriented instructions f represents a file reg ister designator and d represents a destination desig nator The file register designator specifies which file register is to be used by the instruction The destination designator specifies where the result of the operation is to be placed If d is zero the result is placed in the W register If d is one the result is placed in the file register specified in the instruction For bit oriented instructions b represents a bit field designator which selects the number of the bit affected by the operation while f represents the number of the file in which the bit is located For literal and control operations K represents an eigh
11. Indicator DI eB gt Area gt D gt Base Plane Seatin a A AAA AE seje 2 Le D1 Package Group Plastic Dual In Line PLA Millimeters Inches Symbol Min Max Notes Min Max Notes A 5 080 0 200 A1 0 381 0 015 A2 3 175 4 064 0 125 0 160 B 0 355 0 559 0 014 0 022 B1 1 270 1 778 Typical 0 050 0 070 Typical C 0 203 0 381 Typical 0 008 0 015 Typical Typical Typical BSC BSC O 1996 Microchip Technology Inc Preliminary DS30559A page 109 PIC16C64X amp PIC16C66X Package Type 44 Lead Plastic Leaded Chip Carrier L Square D 2 gt D g 0 812 0 661 p TI 127 0321026 Pies el DEG 50 0177 eee gt Ai 2 Sides LA i Ds Es 0 101 Seating DE D 004 Plano AX te lt E2 gt 0 38 2015 lt JA AET E gt z 0 812 0 661 0 254 Soe Max AK rr I 032 026 0 508 0 508 NEE 7020 420 H lis ue 1 co 1 651 1 651 064 wi 0 533 0 UR 5 B ne R
12. are ovis A ee 2 A INT pin 1 flag INTCON lt 1 gt Interrupt Latency Note 2 X NTOON lt 7 gt Processor in SLEEP INSTRUCTION FLOW Instruction fetched Instruction executed Inst PC SLEEP Inst PC 1 Inst PC 2 Inst PC 1 SLEEP Inst PC 1 Dummy cycle Note 1 HS or LP oscillator mode assumed 2 Tosr 1024Tosc drawing not to scale This delay will not be there for RC osc mode 3 GIE 1 assumed In this case after wake up the processor jumps to the interrupt routine If GIE 0 execution will continue in line 4 CLKOUT is not available in these osc modes but shown here for timing reference DS30559A page 70 Preliminary O 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 9 9 Code Protection If the code protection bit s have not been programmed the on chip program memory can be read out for verification purposes Note Microchip does not recommend code protecting windowed devices 9 10 ID Locations Four memory locations 2000h 2003h are designated as ID locations where the user can store checksum or other code identification numbers These locations are not accessible during normal execution but are readable and writable during program verify Only the least significant 4 bits of the ID locations are used 9 11 In Circuit Serial Programming
13. m TMPO Figure 7 6 Note PSA and PS2 PSO are bits in the OPTION register oY MUX WDT Time out FIGURE 9 18 SUMMARY OF WATCHDOG TIMER REGISTERS Address Bit 7 Bit 6 Bit5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Config bits BODEN CP1 CPO PWRTE WDTE FOSC FOSCO 81h OPTION RBPU INTEDG TOCS TOSE PSA PS2 PS1 PSO Legend Shaded cells are not used by the Watchdog Timer Note 1 See Figure 9 1 for details of the operation of these bits O 1996 Microchip Technology Inc Preliminary DS30559A page 69 PIC16C64X amp PIC16C66X 9 8 Power Down Mode SLEEP Power down mode is entered by executing SLEEP instruction If enabled the Watchdog Timer will be cleared but keeps running the PD bit in the STATUS register is cleared the TO bit is set and the oscillator driver is turned off The O ports maintain the status they had before the SLEEP instruction was executed driving high low or hi impedance I For lowest current consumption in this mode all I O pins should be either at VDD or 55 with no external circuitry drawing current from the pin and the com parators and VREF module should be disabled I O pins that are hi impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs The TOCKI input should also be at VDD or VsS
14. 101 Parallel Slave Port Requirements PIC16C661 and 16 662 102 Pin Compatible 125 DS30559A page 130 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X ON LINE SUPPORT Microchip provides two methods of on line support These are the Microchip BBS and the Microchip World Wide Web WWW site Use Microchip s Bulletin Board Service BBS to get current information and help about Microchip products Microchip provides the BBS communication channel for you to use in extending your technical staff with micro controller and memory experts To provide you with the most responsive service possible the Microchip systems team monitors the BBS posts the latest component data and software tool updates provides technical help and embedded systems insights and discusses how Microchip products pro vide project solutions The web site like the BBS is used by Microchip as a means to make files and information easily available to customers To view the site the user must have access to the Internet and a web browser such as Netscape or Microsoft Explorer Files are also available for FTP download from our FTP site Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to www microchip com The file transfer site is availa
15. PIC16CXX microcontrollers can be serially programmed while in the end application circuit This is simply done with two lines for clock and data and three other lines for power ground and the programming voltage This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product This also allows the most recent firmware or a custom firmware to be programmed The device is placed into a program verify mode by holding the RB6 and RB7 pins low while raising the MCLR VPP pin from VIL to ViHH see programming specification RB6 becomes the programming clock and RB7 becomes the programming data Both RB6 and RB7 are Schmitt Trigger inputs in this mode After reset to place the device into programming verify mode the program counter PC is at location 00h 6 bit command is then supplied to the device Depending on the command 14 bits of program data are then supplied to or from the device depending if the command was a load or a read For complete details of serial programming please refer to the PIC16C6X 7X Programming Specifications Literature DS30228 A typical in circuit serial programming connection is shown in Figure 9 20 FIGURE 9 20 TYPICAL IN CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal External Connections Connector Signals PIC16CXX 5V VDD ov Vss Ver MGLR VPP CLKH RB6 Data RB7
16. x unknown u unchanged unimplemented locations read as 0 Shaded cells are not used by the PSP These bits are reserved on the PIC16C641 642 always maintain these bits clear 1996 Microchip Technology Inc Preliminary DS30559A page 39 PIC16C64X amp PIC16C66X NOTES P DS30559A page 40 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 6 0 TIMERO MODULE OPTION lt 4 gt Clearing bit TOSE selects the rising edge Restrictions on the external clock input are dis The TimerO module has the following features cussed in detail in Section 6 2 8 bit timer counter register The prescaler is mutually exclusively shared between Read and write capability the 0 module and the Watchdog Timer The pres Interrupt on overflow from FFh to 00h caler assignment is controlled in software by control bit 8 bit software programmable prescaler PSA OPTION lt 3 gt Clearing bit PSA will assign the prescaler to the TimerO module The prescaler is not readable or writable When the prescaler is assigned to the module prescale values of 1 2 1 4 Internal or external clock select Edge select for external clock Figure 6 1 is a simplified block diagram of the 1 256 are selectable Section 6 3 details the operation module of the prescaler Timer mode is selected by clearing bit TOCS OPTION lt 5 gt In timer mode ihe Timer
17. X9999191d Four user programmable ID locations Program Memory Parity Error checking circuitry with Parity Error Reset PER CMOS Technology Low power high speed CMOS EPROM technology Fully static design Wide operating voltage range 3 0V to 6 0V Commercial Industrial and Automotive temperature ranges Low power consumption lt 2 0 5 0 4 0 MHz 15 uA typical 3 0V 32 kHz lt 1 0 uA typical standby current 3 0V 1996 Microchip Technology Inc DS30559A page 1 1 AMA PIC16C64X amp PIC16C66X Pin Diagrams Cont d lt RC6 5 gt RCA o Tu RD3 PSP3 gt RD2 PSP2 RD1 PSP1 RDO PSPO gt RC2 lt RCI NC RC7 RD4 PSP4 4 RD5 PSP5 gt RD6 PSP6 RD7 PSP7 lt gt Vss gt gt Voo gt RBO INT lt RB1 RB2 lt gt 40 39 38 3736 35 34 RA4 TOCKI RA5 REO RD lt RET WR gt RE2 CS Vss OSC1 CLKIN OSC2 CLKOUT RCO lt NC
18. The PRO MATE II has programmable and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability It has an LCD display for displaying error messages keys to enter commands and a modular detachable socket assembly to support various package types In stand alone mode the PRO MATE II can read verify or pro gram PIC16C5X PIC16CXX PIC17CXX PIC14000 devices It can also set configuration and code protect bits in this mode 11 5 PICSTART Plus Eniry Level Development System The PICSTART programmer is an easy to use low cost prototype programmer It connects to the PC via one of the COM RS 232 ports MPLAB Integrated Development Environment software makes using the programmer simple and efficient PICSTART Plus is not recommended for production programming PICSTART Plus supports all PIC12C5XX PIC14000 PIC16C5X PIC16CXX and PIC17CXX devices with up to 40 pins Larger pin count devices such as the PIC16C923 and PIC16C924 may be supported with an adapter socket 1996 Microchip Technology Inc Preliminary DS30559A page 87 1 AMA PIC16C64X amp PIC16C66X 11 6 PICDEM 1 Low Cost 16 17 Demonstration Board The PICDEM 1 is a simple board which demonstrates the capabilities of several of Microchip s microcontrol lers The microcontrollers supported are PIC16C5X PIC16C54 to PIC16C58A PIC16C61 PIC16C62X PIC16C71 PIC16C8X
19. wil 6 1 Hmer interrupt increment every instruction cycle without prescaler If The TMRO interrupt is generated when the register TMRO register is written the increment is inhibited for TMRO overflows from FFh to 00h This overflow sets the following two instruction cycles Figure 6 2 and interrupt flag bit TOIF INTCON lt 2 gt The interrupt can Figure 6 3 The user can work around this by writing be masked by clearing enable bit TOIE lt 5 gt an adjusted value to the TMRO register Flag bit TOIF must be cleared in software by the TimerO interrupt service routine before re enabling this inter rupt The TMRO interrupt cannot wake the processor from SLEEP since the timer is shut off during SLEEP Figure 6 4 displays the TimerO interrupt timing Counter mode is selected by setting bit TOCS In this mode TimerO will increment either on every rising or falling edge of pin RA4 TOCKI The incrementing edge is determined by the source edge select bit TOSE FIGURE 6 1 TIMERO BLOCK DIAGRAM Data bus RA4 TOCKI Fosc 4 M 8 Sync with Internal TMRO reg 7 Programmable Clocks PSout Prescaler TOSE 2 cycle delay 3 Set bit TOIF PS2 PS1 PSO PSA on overflow TOCS Note 1 Bits TOCS TOSE PSA and PS2 PS1 PSO lt 5 0 2 The prescaler is shared with Watchdog Timer refer to Figure 6 6 for detailed diagram
20. 17 42 PIC17C43 and PIC17C44 All necessary hardware and software is included to run basic demo programs The users can program the sample microcontrollers provided with the PICDEM 1 board on PRO MATE Il or PICSTART 16B programmer and easily test firm ware The user can also connect the PICDEM 1 board to the PICMASTER emulator and download the firmware to the emulator for testing Additional pro totype area is available for the user to build some addi tional hardware and connect it to the microcontroller socket s Some of the features include an RS 232 interface a potentiometer for simulated analog input push button switches and eight LEDs connected to PORTB 11 7 PICDEM 2 Low Cost PIC16CXX Demonstration Board The PICDEM 2 is a simple demonstration board that supports the PIC16C62 PIC16C64 PIC16C65 PIC16C73 and PIC16C74 microcontrollers the necessary hardware and software is included to run the basic demonstration programs The user can program the sample microcontrollers provided with the PICDEM 2 board on a PRO MATE II pro grammer or PICSTART 16C and easily test firmware The PICMASTER emulator may also be used with the PICDEM 2 board to test firmware Additional prototype area has been provided to the user for adding addi tional hardware and connecting it to the microcontroller socket s Some of the features include a RS 232 inter face push button switches a potentiometer for simu lated analog input a Se
21. e x RAO ANO Registers e X RA1 AN1 RA2 AN2 VREF RAM Bank 54 Addr 14 Instruction reg Indirect Addr Direct Addr 7 FSR reg STATUS reg DX RA4 TOCKI Power up Timer Instruction D Oscillator eae Start up Timer Power on Timin Reset 9 DK Generation Watchdo OSC1 CLKIN Timer OSC2 CLKOUT Brown out RA5 Reset LLL Parity Error Reset RBO INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 DS30559A page 10 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X FIGURE 3 2 Program Bus PIC16C661 662 BLOCK DIAGRAM PIC16C661 has 2K x 14 Program Memory and 128 x 8 RAM PIC16C662 has 4K x 14 Program Memory and 176 x 8 RAM 13 EPROM Program Memory Data Bus Voltage Reference Program Counter lt 8 Level Stack 13 bit 14 RAM File Registers RAM Bank Instruction reg Select OSC1 CLKIN OSC2 CLKOUT Direct Addr 7 Indirect FSR reg STATUS reg
22. 0 No overflow occurred bit 4 PSPMODE Parallel Slave Port Mode Select bit 1 Parallel slave port mode 0 General purpose mode bit 3 Unimplemented Read as 0 bit 2 TRISE2 Direction control bit for pin RE2 CS 1 Input 0 Output bit 1 TRISE1 Direction control bit for pin RE1 WR 1 2 Input 0 Output bit 0 TRISEO Direction control bit for pin REO RD 1 Input 0 Output DS30559A page 36 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X FIGURE 5 10 PORTE BLOCK DIAGRAM IN 1 0 PORT MODE Data Bus D a Dx pin WR PORT beka Data Latch D Q Schmitt WR TRIS ck G Trigger input TRIS Latch buffer N RD TRIS RD PORT o Note I O pins have protection diodes to VDD and Vss TABLE 5 9 PORTE FUNCTIONS Name Bit Buffer Type Function REO RD bitO ST TTLO Input output port pin or read control input in parallel slave port mode RD 1 Notaread operation 0 Read operation Reads PORTD register if chip selected RE1 WR bit ST TTL Input output port pin or write control input in parallel slave port mode WR 1 Nota write operation 0 Write operation Writes PORTD register if chip selected RE2 CS bit2 ST TTLO Inpu output port pin or chip select control input in parallel slave port mode CS 1 Device is not selected 0 Device is selected Legend ST Schmi
23. 1 enables weak pull up if 0 OPTION lt 7 gt 1996 Microchip Technology lnc PIC16C64X amp PIC16C66X EXAMPLE 5 2 INITIALIZING PORTB Initialize PORTB by clearing output data latches Select Bank 1 Value used to BSF STATUS RPO MOVLW 0xCF initialize data direction Set RB 3 0 as inputs RB 5 4 as outputs RB 7 6 as inputs MOVWF TRISB 54054054044 44 Ne Ne Ne Ne ve TABLE 5 3 PORTB FUNCTIONS Name Bit Buffer Type Function RBO INT bitO TTL ST Input output or external interrupt input Internal software programmable weak pull up RB1 bit TTL Input output pin Internal software programmable weak pull up RB2 bit2 TTL Input output pin Internal software programmable weak pull up RB3 bit3 Input output pin Internal software programmable weak pull up RB4 bit4 TTL Input output pin with interrupt on change Internal software programmable weak pull up RB5 bit5 TTL Input output pin with interrupt on change Internal software programmable weak pull up RB6 bit6 TTL ST Input output pin with interrupt on change Internal software programmable weak pull up Serial programming clock pin RB7 bit7 TTL ST Input output pin with interrupt on change Internal software programmable weak pull up Serial programming data pin Legend ST Schmitt Trigger input TTL TTL input Note 1 This buffer is a Schmitt Trigger
24. 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 5 7 Parallel Slave Port PIC16C661 and PIC16C662 only PORTD operates as an 8 bit wide parallel slave port or as a microprocessor port when control bit PSPMODE TRISE 4 is set In slave mode it is asynchronously readable and writable by the external world through RD control input pin REO RD and WR control input pin RE1 WR It can directly interface to an 8 bit microprocessor data bus The external microprocessor can read or write the PORTD latch as an 8 bit latch Setting PSPMODE enables port pin REO RD to be the RD input RE1 WR to be the WR input and RE2 CS to be the CS chip select input For this functionality the corresponding data direction bits of the TRISE register TRISE lt 2 0 gt must be configured as inputs set There are actually two 8 bit latches one for data out from the PIC16 17 and one for data input The user writes 8 bit data to PORTD data latch and reads data from the port pin latch note that they have the same address In this mode the TRISD register is ignored since the microprocessor is controlling the direction of data flow Input Buffer Full Status Flag bit IBF TRISE lt 7 gt is set if a received word is waiting to be read by the CPU Once the PORTD input latch is read bit IBF is cleared IBF is a read only status bit Output Buffer Full Status Flag bit OBF TRISE lt 6 gt is set if a word written to PORTD latch is waiting
25. C DC Z TL 110x kkkk kkkk W register is subtracted 2s com plement method from the eight bit literal K The result is placed in the W register 1 1 SUBLW 0x02 Before Instruction W 1 After Instruction W 1 C 1 result is positive Before Instruction W 2 2 After Instruction W 0 C 1 result is zero Before Instruction W 3 C After Instruction W OxFF C O result is nega tive SUBWF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example 1 Example 2 Example 3 Subtract W from f label SUBWF 5 0 lt 1 lt 127 de 0 1 f W dest C DC Z 00 0010 dfff ffff Subtract 2 s complement method W reg ister from register f If d is O the result is stored in the W register If d is 1 the result is stored back in register f 1 1 SUBWF REG1 1 Before Instruction REG1 19 W 72 C 2 After Instruction REGI Se ed W 2 C 1 result is positive Before Instruction REG 42 W 2 C 2 After Instruction REG1 0 W zc C 1 result is zero Before Instruction REG1 1 W 2 C 2 After Instruction REG1 OxFF W 2 C 0 result is negative DS30559A page 84 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X SWAPF S
26. PIC16C66X use a Harvard architecture in which pro gram and data are accessed from separate memories using separate buses This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory Separat ing program and data memory further allows instruc tions to be sized differently than an 8 bit wide data word Instruction opcodes are 14 bits wide making it possible to have all single word instructions A 14 bit wide program memory access bus fetches a 14 bit instruction in a single cycle A two stage pipeline over laps fetch and execution of instructions Consequently all instructions 35 execute in a single cycle 200 ns 20 MHz except for program branches which require two cycles The PIC16C641 and PIC16C661 both address 2K x 14 on chip program memory while the PIC16C642 and PIC16C662 address 4K x 14 All program memory is internal PIC16C64X amp PIC16C66X devices can directly or indi rectly address their register files or data memory All special function registers including the program counter are mapped in the data memory These devices have an orthogonal symmetrical instruction set that makes it possible to carry out any operation on any register using any addressing mode This symmet rical nature and lack of special optimal situations make programming with the PIC16C64X amp PIC16C66X simple yet efficient In addition the learning curve is reduced significantly
27. ified in Table 12 1 Characteristics Sym Min Typ Max Units Comments Input offset voltage 5 0 10 mV Input common mode voltage 0 1 5 V CMRR 35 db Response 150 400 ns 16 64 66 600 ns PIC16LC64X 66 Comparator Mode Change to 10 us Output Valid These parameters are characterized but not tested Note 1 Response time measured with one comparator input at 1 5 2 while the other ahsitions fro VSS to VDD TABLE 12 3 VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions 3 0V lt VDD lt 6 0V 40 C lt TA lt 125 C unless otherwise s a r ent co sumption is spec ified in Table 12 1 Characteristics Sym Min Comments Resolution 24 Absolute Low Range VRR 1 High Range VRR 0 Figure 8 2 Unit Resistor Value R E Settling Time J R These parameters are characterized but not t d Note 1 Settling time measured while VRR lt 3 DS30559A page 96 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 12 4 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats 1 TppS2ppS 2 TppS T F Frequency T Time Lowercase subscripts pp and their meanings pp ck CLKOUT osc OSC1 io O port 10 MCLR Uppercase letters and their meanings 5 F Fall H High R Rise I
28. ports D030 with TTL buffer Vss 0 15VDD Vss 0 8V 0031 with Schmitt Trigger input Vss 0 2 0032 RA4 TOCKI OSC1 in Vss 0 2VDD RC mode 0033 OSC1 and HS modes 0 3VDD OSC1 LP modes VIH Input High Voltage ports D040 with TTL buffer 0041 with Schmitt Trigger input 0042 RA4 TOCKI D043 OSC1 XT HS LP modes D043A OSC1 RC mode 1 D070 IPURB PORTB weak pull up curren VDD 5 0 VPIN VSS liL Input Leakage Current 2 3 ports Except 1 0 55 lt lt pin at hi impedance 0060 PORTA 0 5 Vss VPIN lt VDD pin at hi impedance 0061 RA4 TOCKI 1 0 Vss VPIN lt VDD D063 2 5 0 HA Vss lt VPIN lt VDD XT HS and LP configuration VoL D080 0 6 V 10 8 5 mA VDD 4 5V 40 to 85 C lt 0 6 V loL 7 0 MA VDD 4 5V 125 C D083 OSC2 CLKOUT 0 6 V loL 1 6 mA VDD 4 5V 40 to 85 C RC only 0 6 V loL 1 2 mA VDD 4 5V 125 C These parameters are characterized but not tested T Data in Typ column is at 5 0V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 In RC oscillator configuration the OSC1 pin is a Schmitt Trigger input It is not recommended that the PIC16C64X amp PIC16C66X be driven with external clock in RC mode 2 The leakage c
29. 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 14 0 PACKAGING INFORMATION Package Type 28 Lead Skinny Plastic Dual In Line SP 300 mil Or 177 1 Indicator DILILILC Le eB gt Area gt gt B2 B1 D gt S pare 2 ane N Seating k Plane LA Detail A gt el A1A2A D1 gt B3 B Detail A Package Group Plastic Dual In Line PLA Millimeters Inches Symbol Min Max Notes Min Max Notes A 3 632 4 572 0 143 0 180 A1 0 381 0 015 A2 3 175 3 556 0 125 0 140 B 0 406 0 559 0 016 0 022 B1 1 016 1 651 Typical 0 040 0 065 Typical B2 0 762 1 016 4 places 0 030 0 040 4 places 4 places 4 places Typical Typical BSC BSC el 2 540 2 540 Typical 0 100 0 100 Typical eA 7 874 7 874 BSC 0 310 0 310 BSC eB 8 128 9 906 0 320 0 390 L 3 175 3 683 0 125 0 145 S 0 584 1 220 0 023 0 048 1996 Microchip Technology Inc rm oc Preliminary tn DS30559A page 105 PIC16C64X amp PIC16C66X Package Type 28 Lead Plastic Small Outline SO Wide 300 mil Body h x 45 Pin No 1 Indicator H Area Chamfe
30. 1996 Microchip Technology Inc Preliminary DS30559A page 27 PIC16C64X amp PIC16C66X 4 5 Indirect Addressing INDF and FSR A simple program to clear RAM location 20h 2Fh using Registers indirect addressing is shown in Example 4 1 The INDF register is not a physical register Addressing EXAMPLE 4 1 INDIRECT ADDRESSING the INDF register will cause indirect addressing movlw 0x20 initialize pointer Indirect addressing is possible by using the INDF reg movwf FSR to RAM ister Any instruction using the INDF register actually NEXT clrf INDF clear INDF register accesses data pointed to by the file select register incf FSR inc pointer FSR Reading INDF itself indirectly will produce OOh btfss FSR 4 all done Writing to the INDF register indirectly results in a no goto NEXT goto next operation although status bits may be affected An yes continue effective 9 bit address is obtained by concatenating the CONTINUE 8 bit FSR register and the IRP bit STATUS lt 7 gt as shown in Figure 4 12 However bit IRP is not used in the PIC16C64X amp PIC16C66X FIGURE 4 12 DIRECT INDIRECT ADDRESSING Direct Addressing Indirect Addressing RP1 RPO 6 from opcode IRPO 7 FSR register bank select location select bank select location select M 00 P 00h 00h Bank 0 Bank 1 2 Bank 3 For memory map deta
31. FIGURE 6 2 TIMERO TIMING INTERNAL CLOCK NO PRESCALER PC 01 02 03104 a1 a2 a3 a4 a1 a2 a3 a4 01102 03 04 03 02103 04 011 021 031 04 011 02 03 04 1 1 1 1 1 1 1 Counter 1 Y PC X PC 1 PC 2 Y PC 3 PC 4 y PC 5 X PC 6 2 MOVWF TMRO TMRO W TMRO W TMRO W TMRO W MOVF TMRO W Instruction Executed ME NO2 X Write TMRO Read TMRO ReadTMRO ReadTMRO Read TMRO Read TMRO executed reads NTO reads NTO reads NTO reads NTO 1 reads NTO 2 TMRO 1 1 1 1 t t 1996 Microchip Technology Inc Preliminary DS30559A page 41 1 am Rad AMA PIC16C64X amp PIC16C66X FIGURE 6 3 TIMERO TIMING INTERNAL CLOCK PRESCALE 1 2 02 03 04 011 az 04 01 02 03 031 a4 01 02 03 24 011 02 03 04 MOVWF TMRO MOVF TMRO W TMRO W TMRO W MOVF TMRO W Instruction MOVF TMRO W Fetch TMRO TO TO 1 t t D ed WriteTMRO ReadTMRO ReadTMRO ReadTMRO ReadTMRO ReadTMRO executed reads NTO reads NTO reads NTO reads NTO reads NTO 1 Instruction Execute Counter POH y PCr y Y PC 4 y PC FIGURE 6 4 TIMERO INTERRUPT TIMING 04 21 az 0
32. For external interrupt events such as the or Port RB change interrupt the interrupt latency will be three or four instruction cycles The exact latency depends when the interrupt event occurs Figure 9 16 The latency is the same for one or two cycle instructions Once in the interrupt service routine the source s of the interrupt can be determined by polling the interrupt flag bits The interrupt flag bit s must be cleared in software before re enabling interrupts to avoid multiple interrupt reguests Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit Note 1 Individual interrupt flag bits are set regard less of the status of their corresponding mask bit or the GIE bit Note 2 When an instruction that clears the GIE bit is executed any interrupts that were pending for execution in the next cycle are ignored The CPU will execute a NOP in the cycle immediately following the instruction which clears the GIE bit The interrupts which were ignored are still pending to be serviced when the GIE bit is set again Wake up If in SLEEP mode Interrupt to CPU Note 1 The Parallel Slave Port is implemented on the PIC16C661 and PIC16C662 only DS30559A page 66 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 9 5 1 RBO INT INTERRUPT 9 5 3 PORTB INTERRUPT The external interrupt on the RBO INT pin is edge tr
33. Freg 4 0 MHz max HS 4 5V to 5 5V 4 5V to 5 5V Do not use in HS mode 4 5V to 5 5V IDD 30 MA max 5 5V IDD 30 mA max 5 5V IDD 30 mA max 5 5V IPD 1 5 uA typ 4 5V IPD 1 5 LA typ 4 5V IPD 1 5 LA typ 4 5V Freg 10 MHz max Freg 20 MHz max Freg 10 MHz max LP AW to 6 0V Do not use in LP mode Do not use in LP mode VDD 3 0V to 6 0V VDD 3 0V to 6 0V IDD 52 5 LA typ IDD 48 LA max IDD 48 uA max 32 kHz 4 0V 32 kHz 3 0V 32 kHz 3 0V IPD 0 9 LA typ 4 0V IPD 5 0 LA max 3 0V IPD 5 0 LA max 3 0V Freg 200 kHz max Freg 200 kHz max Freg 200 kHz max The shaded sections indicate oscillator selections which are tested for functionality but not for MIN MAX specifications It is recommended that the user select the device type that ensures the specifications reguired 1996 Microchip Technology Inc Preliminary 1 am ax DS30559A page 91 PIC16C64X amp PIC16C66X 12 1 DC Characteristics PIC16C641 642 661 662 04 Commercial Industrial Automotive PIC16C641 642 661 662 10 Commercial Industrial Automotive PIC16C641 642 661 662 20 Commercial Industrial Automotive Standard Operating Conditions unless otherwise stated Operating temperature 409 lt TA lt 85 C for industrial 0 C lt TA lt 70 C commercial and 40 C lt TA lt 125 C automotive
34. PIC16C64X amp PIC16C66X devices contain an 8 bit ALU and working register The ALU is a general pur pose arithmetic unit It performs arithmetic and Bool ean functions between data in the working register and any register file The ALU is 8 bits wide and capable of addition subtraction shift and logical operations Unless otherwise mentioned arithmetic operations are two s complement in nature In two operand instructions typically one is the working register W register The other operand is a file register or an immediate constant In single operand instructions the operand is either the W register or a file register The W register is an 8 bit working register used for ALU operations It is not an addressable register Depending on the instruction executed the ALU may affect the values of the Carry C Digit Carry DC and Zero Z bits in the STATUS register The C and DC bits operate as a Borrow and Digit Borrow out bit respectively bit in subtraction See the sUBLW and SUBWF instructions for examples 1996 Microchip Technology Inc Preliminary DS30559A page 9 1 ana PIC16C64X amp PIC16C66X FIGURE 3 1 16 641 642 BLOCK DIAGRAM PIC16C641 has 2K x 14 Program Memory and 128 x 8 RAM PIC16C642 has 4K x 14 Program Memory and 176 x 8 RAM Voltage 13 Data Bus Reference Program Counter lt EPROM Program RAM Memory 8 Level Stack ei Comparator 13 bit
35. a en 42 IORLW Instruction ener 80 IORWF Instruction 81 M MOVFEF Instr ction siennes MOVLW Instruction sss MOVWF Instruction senes MPASM Assembler MPLAB C C Compiler MPLAB SIM Software Simulator 87 89 N NOP IAStrUCtION 82 One Time Programmable OTP Devices 7 73 OPTION InsStr ctior cie ttes 82 OPTION Register sss 22 Oscillator Configurations 22 57 Oscillator Start up Timer OST 60 P Package Marking Information 112 113 Packaging Information eee 105 Parallel Slave Port 35 DECNOM s e ce Pc bcm Ten ge int 39 Error Reset PER 60 61 POL te ihe etie E eile 74 PGLiand PCLATH prep ic 27 PCON Register sss 26 61 PICDEM 1 Low Cost PIC16 17 Demo Board 87 88 PICDEM 2 Low Cost PIC16CXX Demo Board 87 88 PICDEM 3 Low Cost PIC16C9XX Demo Board 88 PICDEM 3 PIC16C9XX Low Cost Demonstration Board serie Mau e 87 PICMASTER High Performance In Circuit Emulator eee 87 PICSTART Plus Entry Level Development NATI MTM dan sn Ram ne 87 PICSTART Plus Entrvel Prototype Programmer 87 PIE1 i
36. an active low reset to the device PORTA is a bi directional I O port RAO ANO 2 ST Analog comparator input RA1 AN1 3 ST Analog comparator input RA2 AN2 VREF 4 ST Analog comparator input or VREF output RA3 AN3 5 VO ST Analog comparator input or comparator output RA4 TOCKI 6 ST Can be selected to be the clock input to the TimerO timer counter or a comparator output Output is open drain type RA5 7 ST PORTB is a bi directional I O port PORTB can be software pro grammed for internal weak pull ups on all inputs RBO INT 21 TTL ST RBO can also be selected as an external interrupt pin RB1 22 VO TTL RB2 23 VO TTL RB3 24 VO TTL RB4 25 VO TTL Interrupt on change pin RB5 26 TTL Interrupt on change pin RB6 27 TTL ST2 Interrupt on change pin Serial programming clock RB7 28 TTL ST Interrupt on change pin Serial programming data PORTC is a bi directional I O port RCO 11 ST 12 VO ST RC2 13 VO ST RC3 14 VO ST RC4 15 VO ST RC5 16 VO ST RC6 17 ST RC7 18 VO ST Vss 8 19 P Ground reference for logic and I O pins VDD 20 P Positive supply for logic and I O pins Legend O output input output P power input not used ST Schmitt Trigger input TTL TTL input Note 1 This buffer is a Schmitt Trigger input when configured as the external interrupt 2 This buffer is a Schmitt Trigger input when used in serial programming mode DS30559A p
37. res of the i debe HO tte bed nite nid rire des 55 10 0 Instr ctiori Set SUMMA eite ER ER fed inei tote BP ln 73 11 0 Dev lopmient tone teen Ness ere COE one RU EP ERR ERR FERA DAR RR EFL MERO 87 12 0 Electrical Specifications sir semblaient intense eee os Eo petere east eoe RI eu ten pires De reden ee tuse T dang ded 91 13 0 Device Characterization Information sise 103 14 0 Packaging Informations rent A ett ord dae ah edere eee 105 Appendix A Enhancements te Eee Hee i UR ede crei pedi Dept ens 115 Appendix Bi Compatibility tac tete ine Go Pire edet o eo as 115 Appendix What s New eer etes intimement byvaly yh 116 Appendix D Whats Changed uoa aee dei ident arrete ne 116 Appendix E PIC16 17 Microcontrollers 3 3 NI ded Ec p ce eet ee 117 Pin Goripatibilily 2 5 e tet E ee eaten bent itai ies 125 a NE AR 127 List ot Examples uir RR EHE TRAE trader mages RB ORO RESET GER RETE REN re ERR aie te ira 129 L 129 List of Tables tti eoe t er eiit od En RE te 130 On Line SUPPON awit EE 131 Reade
38. teinte eie ERE 76 ANDW EP iine tire rip dv 76 NI ea eb 77 BSP ete ca loda M le eda 77 BTESG noni pen EE Ha 77 BTESS x cbe cere Rene 78 1 uiii O HER evene 78 GERF 2 n 78 CERW une tab eda e 78 CLRWDT es 79 inita ctia e e bestie t 79 acetate eee er 79 DEGESZ tae e ced 79 BONO iie nn L ai mn ns 80 INGE ALORE EE E 80 INGESZ i e te dE E HS 80 IOREW 80 IORWF ER 81 eT 81 i eter 81 MQONME eit re Rr edd 81 NOP 82 OPTION divin rete Gere 82 tote et e d 82 oe Sn 82 RETURN iniret neben tg ce tle ees 83 cete here inten ial 83 RRE ica miedo tees ten s 83 SLEEP P O O 83 SUBEW 84 SUBWE sancti ie MARS 84 eee etta 85 TRIS HO 85 pe plu 85 ice Waihi a RATE 85 inem Mann 73 Summary Table 75 IN T ssec ette ec 67 INTCON Register eee eee eee eee 23 Interrupts i robert 66 Comparator er tO 51 PORTB Change 32 PSPRead Wiite 5 de nes 39 RBO ING breed ee 66 SOCOM PE EE 66 ree HER 41 Timer
39. 0 12 0 5 0 472 0 0472 5 D1 10 0 10 0 BSC 0 394 0 394 BSC E 12 0 12 0 BSC 0 472 0 472 BSC E1 10 0 10 0 BSC 0 394 0 394 BSC e 0 8 0 8 BSC 0 031 0 031 BSC L 0 450 0 750 0 018 0 030 1996 Microchip Technology Inc Preliminary DS30559A page 111 PIC16C64X amp PIC16C66X 14 1 Package Marking Information 28 Lead PDIP Skinny DIP Example PIC16C642 10 SP XXXXXXXXXXXXXXX D AABBCDE D e AABBCDE O Q MICROCHIP MICROCHIP 28 Lead SOIC Example PIC16C642 10 SO XXXXXXXXXXXXXXXXXXXX AN AABBCDE AN 945 28 Lead Side Brazed Skinny Windowed Example XXXXXXXXXXX PIC16C642 JW D XXXXXXXXXXX C MICROCHIP AABBCDE E 951 7CAT Legend MM MMicrochip part number information XX X Customer specific information AA Year code last 2 digits of calendar year BB Week code week of January 1 is week 01 C Facility code of the plant at which wafer is manufactured C Chandler Arizona U S A D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note ln the event the full Microchip part number cannot be marked on one line it will be carried over to the next line thus limiting the number of available characters for customer specific information Standard OTP marking consists of Microchip part number year cod
40. 0 U 0 R W 1 R W 0 R W u MPEEN PER POR BOR R Readable bit bit7 bitO W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 MPEEN Memory Parity Error Circuitry Status bit Reflects the value of Configuration Word bit MPEEN bit 6 3 Unimplemented Read as 0 bit2 PER Memory Parity Error Reset Status bit 1 No error occurred 0 Program memory fetch parity error occurred must be set in software after a Parity Error Reset occurs bit 1 Power on Reset Status bit 1 No Power on Reset occurred 0 A Power on Reset occurred must be set in software after a Power on Reset occurs BOR Brown out Reset Status bit 1 No Brown out Reset occurred 0 A Brown out Reset occurred must be set in software after a Brown out Reset occurs DS30559A page 26 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 4 3 PCL and PCLATH The program counter PC is 13 bits wide The low byte comes from the PCL register which is readable and writable The high byte PC lt 12 8 gt is not directly read able or writable and comes from PCLATH On any reset the PC is cleared Figure 4 11 shows the two situations for the loading of the PC The upper example in the figure shows how the PC is loaded on a write to PCL PCLATH lt 4 0 gt PCH The lower example in the figure shows how the PC is loaded during a CALL GOTO instruction PCLATH lt 4 3 gt
41. 1 14 0 64 1 14 0 64 0457 025 045 025 917 AlFGB DE Package Group Plastic Leaded Chip Carrier PLCC Millimeters Inches Symbol Min Max Notes Min Max Notes A 4 191 4 572 0 165 0 180 1 2 413 2 921 0 095 0 115 D 17 399 17 653 0 685 0 695 D1 16 510 16 663 0 650 0 656 D2 15 494 16 002 0 610 0 630 D3 12 700 12 700 BSC 0 500 0 500 BSC 17 399 17 653 0 685 0 695 1 16 510 16 663 0 650 0 656 E2 15 494 16 002 0 610 0 630 E3 12 700 12 700 BSC 0 500 0 500 5 0 102 0 004 LT 0 203 0 381 0 008 0 015 DS30559A page 110 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X Package Type 44 Lead Thin Plastic Quad Flatpack PT TQ 10x10x1 mm Body 1 0 0 10 mm Lead Form Dt gt D D 2 PinNo 1 Indicator Area Et NN E 2 i Y 8 Places A _ 11 139 gt nn 0 min ETS Ni not 2 7 A Datum Play 2 2 A ie 0 25 7 b AM 0 08 L d 1 with Lead Finish R min 0 7 odpo 0 20 min X 1 00 ref lt gt Ner cod ee Base Metal DETAIL B Package Group Plastic TQFP Millimeters Inches Symbol Min Max Notes Min Max Notes 09 7 0 7 A 1 200 0 047 1 0 050 0 150 0 002 0 006 2 0 950 1 050 0 037 0 041 b 0 300 0 450 0 012 0 018 bi 0 300 0 400 0 012 0 016 D 12
42. 5 PC None 11 01 kkkk kkkk The W register is loaded with the eight bit literal k The program counter is loaded from the top of the stack the return address This is a two cycle instruction 1 2 CALL TABLE W contains table offset value W now has table value ADDWF PC W offset RETLW k1 Begin table RETLW k2 RETLW kn End of table Before Instruction W 0 07 After Instruction W valueofk8 DS30559A page 82 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X RETURN Return from Subroutine Syntax label RETURN Operands None Operation TOS PC Status Affected None Encoding 00 0000 0000 1000 Description Return from subroutine The stack is POPed and the top of the stack TOS is loaded into the program counter This is a two cycle instruction Words 1 Cycles 2 Example RETURN After Interrupt PC TOS RLF Rotate Left f through Carry Syntax label RLF fd Operands 0 lt 1 lt 127 de 0 1 Operation See description below Status Affected C Encoding 00 1101 dfff fff Description The contents of register f are rotated one bit to the left through the Carry Flag If d is O the result is placed in the W register If is 1 the result is stored back in register f r Register f K_ Words 1 Cycles 1 Example 1 0 Before Instruction
43. 7 8 Effects of a RESET device reset forces the CMCON register to its reset state This forces the comparator module to be in the comparator reset mode CM2 CMO 000 This ensures that all potential inputs are analog inputs Device current is minimized when analog inputs are present at reset time The comparators will be powered down during the reset interval 7 9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 7 5 Since the analog pins are connected to a digital output they have reverse biased diodes to and Vss The analog input therefore must be between Vss If the input voltage deviates from this range by more than 0 6 in either direction one of the diodes is forward biased and a latch up may occur A maximum source impedance of 10kQ is recommended for the analog sources Any external component connected to an analog input pin such as a capacitor or a Zener diode should have very little leakage current Rc 10k ANN JE LEAKAGE NMT 0 6V 1 500 nA CPIN Input Capacitance Threshold Voltage ILEAKAGE Leakage Current at the pin due to various junctions Ric Interconnect Resistance Rs Source Impedance VA Analog Voltage 1996 Microchip Technology Inc Preliminary DS30559A page 51 PIC16C64X amp PIC16C66X TABLE 7 1 REGISTERS ASSOCIATED WITH THE COMPARATOR MODULE Valu
44. Before Instruction W 0x17 FSR 0xC2 After Instruction W 0x17 FSR 0 02 DS30559A page 76 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X BCF Bit Clear f BTFSC Bit Test Skip if Clear Syntax label fb Syntax label BTFSC Operands 0 lt 1 lt 127 Operands 0 lt 1 lt 127 0 lt 0 lt 7 0 lt 0 lt 7 Operation 0 f lt b gt Operation skip if f lt b gt 0 Status Affected None Status Affected None Encoding 01 00bb bfff ffff Encoding 01 10bb bfff ffff Description Bit b in register f is cleared Description If bit b in register f is O then the next Words 1 instruction is skipped If bit b is V then the next instruction Cycles 1 fetched during the current instruction execution is discarded and a NOP is Example BOE ah executed instead making this a 2 cycle Before Instruction instruction FLAG REG 0x07 Words 1 After Instruction FLAG_REG 0x47 Cycles 1 2 BTFSC 1 FALSE PROCESS CODE TRUE Before Instruction PC address HERE After Instruction if FLAG 1 0 PC address TRUE if FLAG lt 1 gt 1 PC address FALSE BSF Bit Set f Syntax label BSF fb Operands 0 lt 1 lt 127 0 lt 0 lt 7 Operation 1 gt f lt b gt Status Affected None Encoding 01 0155 bfff Description Bit b in register f is set Words 1 Cycles 1 Example BSF FLAG REG 7 Befo
45. Block Diagram of RB7 RB4 Pins Figure 5 6 Block Diagram of RB3 RBO Pins Figure 5 7 PORTC Block Diagram in I O port Mode 34 Figure 5 8 PORTD Block Diagram in I O Port Mode 35 Figure 5 9 TRISE Register Address 89h 36 Figure 5 10 PORTE Block Diagram in I O Port Mode 37 Figure 5 11 Successive I O 38 Figure 5 12 PORTD and PORTE as a Parallel Slave Port 39 Figure 6 1 Block Diagram eects 41 Figure 6 2 0 Timing Internal Clock No Prescaler 41 Figure 6 3 TimerO Timing Internal Clock Prescale 1 2 42 1996 Microchip Technology Inc Preliminary DS30559A page 129 PIC16C64X amp PIC16C66X Figure 6 4 Interrupt 42 Figure 6 5 0 Timing With External Clock 43 Figure 6 6 Block Diagram of the TimerO WDT Prescaler 44 Figure 7 1 CMCON Register Address 1Fh 47 Figure 7 2 Comparator I O Operating Modes 48 Figure 7 3 Single Comparator ET Figure 7 4 Comparator Output Block Diagram 50 Figure 7 5 Analog Input Figure 8 1 VRCON Register Address 9Fh EN Figure 8 2 Voltage Reference Block Diagram 53 Figure 8 3 Voltage Reference Output Buffer Example 54 Figure 9 1 Configuration
46. C2 HS 8 MHz 15 30 pF 15 30 pF 10 MHz 15 30 pF 15 30 pF Note A series resistor may be required for 20 MHz 15 30 pF 15 30 pF AT strip cut crystals FIGURE 9 3 EXTERNAL CLOCK INPUT OPERATION HS XT OR LP OSC CONFIGURATION clock from ext system OSC1 6 OSC2 Open Higher capacitance increases the stability of the oscillator but also increases the start up time These values are for design guidance only Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level spec ification Since each crystal has its own characteristics the user should consult the crystal manufacturer for appropriate values of external components Crystals used 32 768 kHz Epson C 001R32 768K A 20 PPM 100 kHz Epson 2 100 00 KC P 20 PPM 200 kHz STD XTL 200 000 kHz 20 PPM 2 0 MHz ECS ECS 20 S 2 50 PPM 4 0 MHz ECS ECS 40 S 4 50 PPM 10 0 MHz ECS ECS 100 S 4 50 PPM 20 0 MHz ECS ECS 200 S 4 50 PPM 1996 Microchip Technology Inc Preliminary DS30559A page 57 PIC16C64X amp PIC16C66X 9 2 3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built Prepack aged oscillators provide a wide operating range and better stability well designed crystal oscillator will provide good performance with TTL gates T
47. DS30559A page 98 Preliminary O 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X FIGURE 12 3 CLKOUT AND I O TIMING CLKOUT Pin input Pin output old value Note See Figure 12 1 for load conditions TABLE 12 5 CLKOUT AND I O TIMING REQUIREME S SM V Parameter Sym Characteristic N Min Art Max Units Conditions No 10 TosH2ckL OSC1T to CLKOUTL 75 200 ns Note 1 11 TosH2ckH OSC1T to CLKOUTT 75 200 ns Note 1 12 TckR CLKOUT rise time 35 100 ns Note 1 13 TckF CLKOUT fall time 35 100 ns Note 1 14 TckL2ioV C O5TcY 20 ns Note 1 15 TioV2ckH Port in valid before CLKOUT K N gt Tosc 200 ns Note 1 16 TckH2iol Port in hold after DUNS 0 ns Note 1 17 TosH2ioV 50 150 ns 18 TosH2iol PIC16C64X 66X 100 ns PIC16LC64X 66X 200 ns 19 TioV29 i 2 I O in setup time 0 ns 20 Ti i PIC16C64X 66X 10 40 ns PIC16LC64X 66X 80 ns Port output fall time PIC16C64X 66X 10 40 ns PIC16LC64X 66X 80 ns p INT pin high or low time Tcv ns rbp RB7 RB4 change INT high or low time TCY ns ese parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters for design guidance only and are not tested tt These parameters are asynchronous events not related to any
48. Interrupt on change pin RB6 39 16 43 VO TTL ST Interrupt on change pin Serial programming clock RB7 40 17 44 TTL sT Interrupt on change pin Serial programming data PORTC is a bi directional I O port RCO 15 32 16 ST 16 35 18 VO ST RC2 17 36 19 VO ST RC3 18 37 20 VO ST RC4 23 42 25 VO ST RC5 24 43 26 VO ST RC6 25 44 27 VO ST RC7 26 1 29 VO ST Legend O output input output P power input not used ST Schmitt Trigger input TTL TTL input Note 1 This buffer is a Schmitt Trigger input when configured as the external interrupt 2 This buffer is a Schmitt Trigger input when used in serial programming mode 3 This buffer is a Schmitt Trigger input when configured as a general purpose I O and a TTL input when used in the Parallel Slave Port Mode for interfacing to a microprocessor port 1996 Microchip Technology Inc Preliminary DS30559A page 13 PIC16C64X amp PIC16C66X TR DIP QFP Buffer mee Pin Pin Pin Type Type p PORTD can be bi directional I O port or parallel slave port for interfacing to a microprocessor bus RDO PSPO 19 38 21 VO ST TTL RD1 PSP1 20 39 22 VO ST TTL RD2 PSP2 21 40 23 VO ST TTL RD3 PSP3 22 41 24 VO ST TTL RD4 PSP4 27 2 30 VO ST TTL RD5 PSP5 28 3 31 Vo ST TTL RD6 PSP6 29 4 32 VO ST TTL RD7 PSP7 30 5 33 VO ST TTL PORTE is a
49. OxCO Mask Comp bits IORWF FLAG REG F Bits to Flag Reg MOVLW 0x03 lnit Comp Mode MOVWF CMCON CM2 CMO 011 BSF STATUS RPO Select Bank 1 MOVLW 0x07 Init Data direction MOVWE TRISA RA lt 2 0 gt to inputs lt 4 3 gt to outputs TRISA lt 7 5 gt read 0 BCF STATUS RPO Select Bank 0 CALL DELAY 10us 10 Hs delay MOVF CMCON F Read CMCON to end change condition BCF PIR1 CMIF Clear Pending Ints BSF STATUS RPO Select Bank 1 BSF PIE1 CMIE Enable Comp Ints BCF STATUS RPO Select Bank O0 BSF INTCON PEIE Enable Periph Ints BSF INTCON GIE Global Int enable 7 2 Comparator Operation single comparator is shown in Figure 7 3 along with the relationship between the analog input levels and the digital output When the analog input at Vin is less than the analog input Vin the output of the comparator is a digital low level When the analog input at Vin is greater than the analog input Vin the output of the comparator is a digital high level The shaded areas of the output of the comparator in Figure 7 3 represents the uncertainty due to input offsets and response time 7 3 Comparator Reference An external or internal reference signal may be used depending on the comparator operating mode The analog signal that is present at VIN is compared to the signal at and the digital output of the comparator is adjusted accordingly Figure 7 3 FIGURE 7 3 SINGLE COMPARATOR 7 8 1 EXTERNAL REF
50. PCH FIGURE 4 11 LOADING OF PC IN DIFFERENT SITUATIONS Instruction with PCL as Destination PCLATH lt 4 0 gt ALU result PCLATH PCH 12 11 10 8 7 GOTO CALL PCLATH lt 4 3 gt Opcode lt 10 0 gt PCLATH 4 3 1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter ADDWF PCL When doing a table read using a computed GOTO method care should be exercised if the table location crosses a PCL memory boundary each 256 byte block Refer to the application note Implementing a Table Read AN556 4 3 2 STACK PIC16C64X amp PIC16C66X devices have an 8 level deep x 13 bit wide hardware stack Figure 4 2 The stack space is not part of either program or data space and the stack pointer is not readable or writable The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch The stack is POPed in the event RETURN RETLWOr instruction execution PCLATH is not affected by a PUSH or POP operation The stack operates as a circular buffer This means that after the stack has been PUSHed eight times the ninth push overwrites the value that was stored from the first push The tenth push overwrites the second push and So on Note 1 There are no status bi
51. REGI 1110 0110 C 0 After Instruction REGI 1110 0110 W 1100 1100 C EE RRF Rotate Right f through Carry Syntax label RRF fd Operands 0 lt 1 lt 127 0 1 Operation See description below Status Affected Encoding 00 1100 dfff Description The contents of register f are rotated one bit to the right through the Carry Flag If d is O the result is placed in the W register If d is 1 the result is placed back in register f Register f gt Words 1 Cycles 1 Example RRF REG1 0 Before Instruction REGI 1110 0110 C 0 After Instruction REGI 1110 0110 W 0111 0011 C 0 SLEEP Syntax label SLEEP Operands None Operation 00h gt WDT 0 gt prescaler 12 TO 0 PD Status Affected PD Encoding 00 0000 0110 0011 Description The power down status bit PD is cleared Time out status bit TO is set Watchdog Timer and its pres caler are cleared The processor is put into SLEEP mode with the oscillator stopped See Power Down Mode SLEEP for more details Words 1 Cycles 1 Example SLEEP 1996 Microchip Technology Inc DS30559A page 83 PIC16C64X amp PIC16C66X SUBLW Syntax Operands Operation Status Affected Encoding Description Words Cycles Example 1 Example 2 Example 3 Subtract W from Literal label SUBLW k 0 lt k lt 255 k W gt W
52. Table 9 5 for reset value for specific condition 4 These registers are associated with the Parallel Slave Port and are not implemented on the PIC16C641 642 1996 Microchip Technology Inc Preliminary DS30559A page 63 PIC16C64X amp PIC16C66X FIGURE 9 9 TIME OUT SEQUENCE POWER UP MCLR NOT TIED VDD CASE 1 VDD MCLR INTERNAL POR PWRT TIME OUT OST TIME OUT INTERNAL RESET FIGURE 9 10 TIME OUT SEQUENCE ON POWER UP MCLR NOT TIED TO CASE 2 VDD UT MCLR INTERNAL POR ES PWRT TIME OUT OST TIME OUT INTERNAL RESET FIGURE 9 11 TIME OUT SEQUENCE ON POWER UP MCLR TIED TO VDD MCLR INTERNAL POR PWRT TIME OUT OST TIME OUT INTERNAL RESET DS30559A page 64 Preliminary 1996 Microchip Technology Inc FIGURE 9 12 EXTERNAL POWER ON RESET CIRCUIT FOR SLOW POWER UP MCLR 6 Note 1 External power on reset circuit is required only if VDD power up slope is too slow The diode D helps discharge the capaci tor quickly when VDD powers down R lt 40 is recommended to make sure that voltage drop across R does not vio late the device s electrical specification R12 1000 to 1 kO will limit any current flowing into MCLR from external capaci tor C in the event of MCLR VPP pin b
53. and must be defined at the same offset from the bank base address i e W TEMP is defined at Ox70 Ox7F in Bank 0 The user register STATUS TEMP must be defined in Bank 0 EXAMPLE 9 1 SAVING THE STATUS AND W REGISTERS IN RAM MOVWF W TEMP SWAPF STATUS W BCF STATUS RPO MOVWF STATUS TEMP Copy W to a Temporary Register regardless of current bank Swap STATUS nibbles and place into W register Change to Bank 0 regardless of current bank Save STATUS to a Temporary register in Bank 0 Interrupt Service Routine SWAPF STATUS TEMP W Swap original STATUS register value into W restores original bank MOVWE STATUS Restore STATUS register from W register SWAPF W_TEMP F Swap Temp nibbles and return value to W Temp r SWAPF W_TEMP W Swap W_Temp to W to restore original W value without affecting STATUS DS30559A page 68 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 9 7 Watchdog Timer WDT The Watchdog Timer WDT is a free running on chip RC oscillator which does not require any external com ponents The block diagram is shown in Figure 9 17 This RC oscillator is separate from the RC oscillator of the OSC1 CLKIN pin This means that the WDT will run even if the clock on the OSC1 and OSC2 pins has been stopped for example by execution of a SLEEP instruction During normal operation a WDT time out generates a device RESET If the device is in SLEEP mode a WDT time out causes the
54. any status bits see the Instruction Set Summary Note 1 The IRP and bits STATUS lt 7 6 gt are reserved on the PIC16C64X amp PIC16C66X and should be maintained clear Use of these bits as general pur pose R W bits is NOT recommended since this may affect upward compatibility with future products Note 2 The C and DC bits operate as a Borrow and Digit Borrow out bit respectively in subtraction See the SUBLW and SUBWF instructions for examples FIGURE 4 5 STATUS REGISTER ADDRESS 03h 83h R W 0 R W 0 R W 0 R 1 R 1 R W x R W x R W x IRP RPO TO PD 2 DC C R Readable bit bit7 bitO W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 IRP Register Bank Select bit used for indirect addressing 1 Bank 2 3 100h 1FFh 0 Bank 0 1 00h FFh Bit IRP is reserved on the PIC16C64X amp PIC16C66X always maintain this bit clear bit 6 5 11 Bank 3 180h 1FFh 10 Bank 2 100h 17Fh 01 Bank 1 80h FFh 00 Bank 0 00h 7Fh RP1 RPO Register Bank Select bits used for direct addressing Each bank is 128 bytes Bit RP1 is reserved on the PIC16C64X amp PIC16C66X always maintain this bit DC Digit carry borrow bit ADDWF ADDLW SUBLW SUBWF instructions for borrow the polarity is reversed clear bit 4 TO Time out bit 1 After power up CLRWDT instruction or SLE
55. bi directional I O port REO RD 8 25 9 VO ST TTL REO RD read control for parallel slave port RE1 WR 9 26 10 VO ST TTL RE1 WR write control for parallel slave port RE2 CS 10 27 11 Vo ST TTL RE2 CS select control for parallel slave port Vss 12 31 6 29 13 34 P Ground reference for logic and I O pins VDD 11 32 7 28 12 35 P Positive supply for logic and I O pins NC 12 13 1 17 Not Connected 33 34 28 40 Legend O output I O input output P power input not used ST Schmitt Trigger input TTL TTL input Note 1 This buffer is a Schmitt Trigger input when configured as the external interrupt 2 This buffer is a Schmitt Trigger input when used in serial programming mode 3 This buffer is a Schmitt Trigger input when configured as a general purpose and a TTL input when used in the Parallel Slave Port Mode for interfacing to a microprocessor port DS30559A page 14 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 3 1 Clocking Scheme lnstruction Cycle The clock input from OSC1 is internally divided by four to generate four non overlapping quadrature clocks namely Q1 Q2 and Q4 Internally the program counter PC is incremented every Q1 the instruction is fetched from the program memory and latched into the instruction register in Q4 The instruction is decoded and executed during the following Q1 through Q4 The clocks and instruction
56. branches which require two cycles A total of 35 instructions reduced instruc tion set are available Additionally a large register set gives some of the architectural innovations used to achieve a very high performance PIC16CXXX microcontrollers typically achieve a 2 1 code compression and a 4 1 speed improvement over other 8 bit microcontrollers in its class The PIC16C641 has 128 bytes of RAM and the PIC16C642 has 176 bytes of RAM Both devices have 22 I O pins and an 8 bit timer counter with an 8 bit pro grammable prescaler In addition they have two analog comparators with a programmable on chip voltage ref erence module Program Memory has internal parity error detection circuitry with a Parity Error Reset The comparator module is ideally suited for applications requiring a low cost analog interface e g battery chargers threshold detectors white goods controllers etc The PIC16C661 has 128 bytes of RAM and the PIC16C662 has 176 bytes of RAM Both devices have 33 I O pins and an 8 bit timer counter with an 8 bit pro grammable prescaler They also have an 8 bit Parallel Slave Port In addition the devices have two analog comparators with a programmable on chip voltage ref erence module Program Memory has internal parity error detection circuitry with a Parity Error Reset The comparator module is ideally suited for applications requiring a low cost analog interface e g battery chargers threshold detectors w
57. current sourced by PORTC and PORTD combined Nete Note 1 Power dissipation is calculated as follows Pois VDD M 40 to 125 C LEE RR O Danone ette a 65 to 150 C en MORE 0 3V to VDD 0 3V E 0 to 7 5V Oto 14V indicated i in the operation listings of this specifi extended periods may affect device reliability may cause permanent damage to the e at those or any other conditions above those TABLE 12 1 PIC16C641 04 PIC16C642 04 PIC16C641 20 PIC16C642 20 PIC16LC641 04 PIC16LC642 04 05 JW Devices PIC16C661 04 PIC16C661 20 PIC16LC661 04 PIC16C662 04 PIC16C662 20 PIC16LC662 04 4 0V to 6 4 5V to 5 5V 3 0V to 6 0V 4 0V 10 6 0V IDD 2 7 mA typ 5 5V 2 0 mAtyp 3 0V IDD 5 max 5 5V IPD 1 5 uAtyp 4 0V IPb 0 9 LA typ 3 0V IPb 21 LA max 4 0V Freg 4 0 4 0 MHz max Freq 4 0 MHz max Freq 4 0 MHz Max XT BD 4 5V to 5 5V DD 4 5V to 5 5V 3 0V to 6 0V VDD 4 0V to 6 0V 2 7 mAtyp 5 5V 2 7 mAtyp 5 5V 100 2 0 mAtyp 3 0V 5 mA max 5 5V IPD 1 5 nA typ 4 0V IPb 1 5 LA typ 4 0V 0 9 LA typ 3 0V IPb 21 LA max 4 0V Freg 4 0 MHz max Freg 4 0 MHz max Freg 4 0 MHz max
58. cycles with the second cycle executed as a NOP One instruc tion cycle consists of four oscillator periods Thus for an oscillator frequency of 4 MHz the normal instruction execution time is 1 us If a conditional test is true or the program counter is changed as a result of an instruc tion the instruction execution time is 2 us Table 10 2 lists the instructions recognized by the MPASM assembler Figure 10 1 shows the three general formats that the instructions can have Note To maintain upward compatibility with future PIC16CXX products do not use the OPTION and TRIS instructions All examples use the following format to represent a hexadecimal number Oxhh where h signifies a hexadecimal digit FIGURE 10 1 GENERAL FORMAT FOR INSTRUCTIONS Byte oriented file register operations 13 8 7 6 OPCODE d f FILE 0 for destination W d 1 for destination f f 7 bit file register address Bit oriented file register operations 13 10 9 7 6 OPCODE b BIT 8 f FILE b 3 bit bit address f 7 bit file register address Literal and control operations General 13 8 7 k literal k 8 bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE k literal k 11 bit immediate value 1996 Microchip Technology Inc 1 DS30559A page 73 PIC16C64X amp PIC16C66X 10 1 Special Function Registers as Source Destination The PIC16C6
59. device to wake up and continue with normal operation this is known as a WDT wake up The WDT can be permanently disabled by clearing configuration bit WDTE Section 9 1 9 7 1 WDT PERIOD The WDT has a nominal time out period of 18 ms with no prescaler The time out period varies with temper ature VDD and process variations from part to part see DC specs If longer time outs are desired a prescaler with a division ratio of up to 1 128 can be assigned to the WDT under software control by writing to the OPTION register Thus time out periods of up to 2 3 seconds can be realized The and SLEEP instructions clear the WDT and the postscaler if assigned to the WDT and prevent it from timing out and generating a device RESET The TO bit in the STATUS register will be cleared upon a Watchdog Timer time out WDT Reset and WDT wake up 9 7 2 WDT PROGRAMMING CONSIDERATIONS It should also be taken in account that under worst case conditions VbD Min Temperature Max max WDT prescaler it may take several seconds before a WDT time out occurs Note When the prescaler is assigned to the WDT always execute a CLRWDT instruction before changing the prescale value other wise a WDT reset may occur FIGURE 9 17 WATCHDOG TIMER BLOCK DIAGRAM From TMRO Clock Source Figure 7 6 WDT Timer WDT Enable Bit Postscaler 8 1 52 50
60. epoo ejqeioejes ow SIJEIISIES J9S9H BABY ULY L 9 LOld 9105 did uid 8 p 8899L Old did 8491018 DIOS did 9 8 1 0789091019 DIOS did uid 8 7849101d 2105 did 9 81 v899191d seunjeeJ 1996 Microchip Technology Inc DS30559A page 122 PIC16C64X amp PIC16C66X PIC16C9XX Family Of Devices 7 si JO Ai iqejreAe diyo 220 INO 1221000 SION pue BUILULUEJBOJJ jenas asn JILUEJ Xx29LOld uano uBiu pue 199 0Jd SPOJ e qei 9jes 9 ge199 9s S991A9P 7 L 9 LOId IIV uld g9 3 CHILL LHL d3OL yydlds ud p9 9 0 OHNLL 26 910 ald 0974 uid g9 ZHAL 3301 dias 9 9 0 2609L0ld sounyeo4 DS30559A page 123 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X PIC17CXX Family of Devices 8 dAON 1 Ud py did uid or HIAL ZHIALL Auqedeo pue 199101d SPOJ 1 5 aw 24219818 71 9 LOId vr921
61. execution flow is shown in Figure 3 3 FIGURE 3 3 CLOCK INSTRUCTION CYCLE 02 03 04 3 2 Instruction Flow Pipelining An Instruction Cycle consists of four Q cycles 1 Q2 Q3 and Q4 The instruction fetch and execute pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle However due to the pipelining each instruction effectively executes in one cycle If an instruction causes the program counter to change e g GOTO then two cycles are required to complete the instruction Example 3 1 A fetch cycle begins with the program counter PC incrementing in Q1 In the execution cycle the fetched instruction is latched into the Instruction Register IR in cycle Q1 This instruction is then decoded and executed during the Q2 Q3 and Q4 cycles Data memory is read during Q2 operand read and written during Q4 destination write XH X Internal phase clock OSC2 CLKOUT RC mode Fetch INST PC Execute INST PC 1 Fetch INST PC 1 Execute INST PC Fetch INST PC 2 EXAMPLE 3 1 INSTRUCTION PIPELINE FLOW TcyO Tcy1 MOVLW 55h MOVWF PORTB Fetch 2 Execute INST PC 1 Tcy2 Tcy3 Fetch 1 Execute 1 Execute 2 CALL SUB 1 BSF PORTA BIT3 Forced NOP Instruction address SUB 1 Fetch 3 Execute 3 Fetch 4 Flush
62. for lowest current consumption The contribu tion from on chip pull ups on PORTB should be consid ered The MCLR pin must be at a logic high level VIHMC 9 8 1 WAKE UP FROM SLEEP The device can wake up from SLEEP through one of the following events 1 Any device reset 2 Watchdog Timer Wake up if WDT was enabled 3 Interrupt from RBO INT pin RB Port change or the Comparator The first event will reset the device upon wake up However the latter two events will wake the device and then resume program execution The TO and PD bits in the STATUS register can be used to determine the cause of device reset The PD bit which is set on power up is cleared when SLEEP is invoked The TO bit is cleared if WDT wake up occurred I When the SLEEP instruction is being executed the next instruction PC 1 is pre fetched For the device to wake up through an interrupt event the correspond ing interrupt enable bit must be set enabled Wake up is regardless of the state of the GIE bit If the GIE bit is clear disabled the device continues execution at the instruction after the SLEEP instruction If the GIE bit is set enabled the device executes the instruction after the SLEEP instruction and then branches to the inter rupt address 0004h In cases where the execution of the instruction following SLEEP is not desirable the user should have an NOP after the SLEEP instruction I I
63. inputs RD PORT Note 1 1 pins have protection diodes to 55 TABLE 5 5 PORTC FUNCTIONS Name Bit Buffer Type Function RCO ST Input output RC1 bit1 ST Input output RC2 bit2 ST Input output RC3 bit3 ST Input output RCA bit4 ST Input output RC5 bit5 ST Input output RC6 bit6 ST Input output RC7 bit7 ST Input output Legend ST Schmitt Trigger input TABLE 5 6 SUMMARY OF REGISTERS ASSOCIATED WITH Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR other resets BOR 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RCO XXXX XXXX uuuu uuuu 87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISCO 1111 1111 1111 1111 Legend x unknown u unchanged DS30559A page 34 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 5 4 PORTD and TRISD Registers FIGURE 5 8 PORTD BLOCK DIAGRAM IN 16 661 and PIC16C662 only 1 0 PORT MODE PORTD is an 8 bit port with Schmitt Trigger input buff ers Each pin is individually configurable as an input or Q output PORTD can be configured as an 8 bit wide micropro RE cessor port parallel slave port by setting control bit PSPMODE TRISE lt 4 gt In this mode the input buffers Data Latch are TTL De Schmitt Trigger N input buffer TRIS Latch RD TRIS
64. internal clock edges Note 1 Measurements are taken in RC Mode where CLKOUT output is 4 x Tosc O 1996 Microchip Technology Inc Preliminary DS30559A page 99 PIC16C64X amp PIC16C66X FIGURE 12 4 RESET WATCHDOG TIMER OSCILLATOR START UP AND POWER UP TIMER TIMING VDD 4 MCLR P Internal POR 33 PWRT Timeout OSC Timeout Internal RESET Parity Error Reset Watchdog Timer RESET Pins TABLE 12 6 RESET WATCHDOG TI WEF OSCILLATOR START UP TIMER POWER UP TIMER AND BRO OUT RESET REQUIREMENTS Parameter espe 5 Typt Max Units Conditions No Muf PS x a m o o 30 Tm T idth low 2 us VDD 5V 40 C to 125 C 31 vt dog Timer Time out Period 7 18 33 ms VDD 5 40 C to 125 C 4 P escaler 32 ost Oscillation Start up Timer Period 1024Tosc Tosc OSC1 period 33 pwrt Power up Timer Period 28 72 132 ms VDD 5V 40 C to 125C 34 O Hi impedance from MCLR Low 2 1 us or Watchdog Timer Reset 35 TBOR Brown out Reset pulse width 100 us VDD lt 0005 36 TPER Parity Error Reset TBD us These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested
65. is accessed either directly or indirectly through PORTE TRISE 89h the File Select Register FSR Section 4 5 PCLATH PCLATH 8Ah INTCON INTCON 8Bh PIR1 PIE1 8Ch 8Dh PCON 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh CMCON VRCON 9Fh AOh General General Purpose Purpose Regi Regi egister egister BFh COh EFh Mapped FOh in Page 0 7Fh FFh Bank 0 Bank 1 Unimplemented data memory locations read as 0 Note 1 Not a physical register 2 Not implemented on the PIC16C641 DS30559A page 18 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X FIGURE 4 4 16 642 662 DATA 4 2 2 SPECIAL FUNCTION REGISTERS MEMORY MAP 9 The special function registers are registers used by the File File CPU and Peripheral Modules for controlling the desired Address Address operation of the device Table 4 1 These registers are static RAM The special function registers can be classified into two OM 81h sets core and m The special function regis POL POL 82h ters associated with the core functions are described STATUS STATUS 83h in this section Those related to the operation of the FSR FSR 84h peripheral features are described in the section of that PORTA TRISA 85h peripheral feature PORTB TRISB 86h PORTC TRISC PORTD TRISD PORTE TRISE PCLATH PCLA
66. register is TRISB Setting a bit in the TRISB register puts the corresponding out put driver in a hi impedance mode Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin s Reading PORTB register reads the status of the pins whereas writing to it will write to the port latch All write operations are read modify write operations There fore a write to a port implies that the port pins are read this value is modified and then written to the port data latch Each of the PORTB pins has a weak internal pull up A single control bit can turn on all the pull ups This is done by clearing the RBPU lt 7 gt bit The weak pull up is automatically turned off when the port pin is configured as an output The pull ups are dis abled on a Power on Reset Four of PORTB s pins RB7 RB4 have an interrupt on change feature Only pins configured as inputs can cause this interrupt to occur i e any RB7 RB4 pin configured as an output is excluded from the interrupt on change comparison The input pins of RB7 RB4 are compared with the old value latched on the last read of PORTB The mismatch outputs of RB7 RB4 are OR ed together to generate the RBIF interrupt flag latched lt 0 gt FIGURE 5 5 BLOCK DIAGRAM OF RB7 RB4 PINS REPU Data Latch D Q Data bus WR Port TRIS Latch D Q WR TRIS RD TRIS RD
67. to be read by the external bus Once the PORTD output latch is read by the micropro cessor bit OBF is cleared Input Buffer Overflow Status flag bit IBOV TRISE 5 is set if a second write to the microprocessor port is attempted when the previous word has not been read by the CPU the first word is retained in the buffer When not in Parallel Slave Port mode bits IBF and OBF are held clear However if flag bit IBOV was pre viously set it must be cleared in software An interrupt is generated and latched into flag bit PSPIF PIR1 lt 7 gt when a read or a write operation is completed Flag bit PSPIF must be cleared by user software The interrupt can be disabled by clearing the interrupt enable bit PSPIE 1 lt 7 gt FIGURE 5 12 PORTD AND PORTE AS A PARALLEL SLAVE PORT Data bus WR PORT LR L One bit of PORTD Set interrupt flag PSPIF PIR1 lt 7 gt Read fr L Chip S Note I O pins have protection diodes to VDD and Vss TABLE 5 11 REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on all Address Name Bit 7 Bit6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR other resets 08h PORTD PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSPO xxxx xxxx uuuu uuuu RE2 1 REO PSPMODE PSPIF TRISE2 TRISE1 TRISEO PSPIE Legend Note 1
68. ways in which our documentation can better serve you please FAX your comments to the Technical Publications Manager at 602 786 7578 Please list the following information and use this outline to provide us with your comments about this Data Sheet To Technical Publications Manager Total Pages Sent RE Reader Response From Name Company Address City State ZIP Country Telephone FAX Application optional Would you like a reply Y N PIC16C64X 4 PIC16C66X Questions Device Literature Number DS30559A 1 What are the best features of this document 2 How does this document meet your hardware and software development needs 3 Do you find the organization of this data sheet easy to follow not why 4 What additions to the data sheet do you think would enhance the structure and subject 5 What deletions from the data sheet could be made without affecting the overall usefulness 6 Isthere any incorrect or misleading information what and where 7 How would you improve this document 8 How would you improve our software systems and silicon products DS30559A page 132 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X NOTES lt TT 1996 Technology Inc DS30559A page 133 PIC16C64X amp PIC16C66X NOTES DS30559A page 134 1996 Microchip Tec
69. 00 0110 0100 GOTO k Go to address 2 10 kkk kkkk kkkk IORLW k Inelusive OR literal with W 1 11 000 Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN Return from Subroutine 2 00 0000 0000 1000 SLEEP Go into standby mode 1 00 0000 0110 0011 TOPD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C DC Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1 When an I O register is modified as a function of itself e g MOVF PORTB 1 the value used will be that value present on the pins themselves For example if the data latch is 1 for a pin configured as input and is driven low by an external device the data will be written back with a 0 2 If this instruction is executed on the TMRO register and where applicable d 1 the prescaler will be cleared if assigned to the TimerO Module 3 If Program Counter PC is modified or a conditional test is true the instruction requires two cycles The second cycle is executed as a NOP 1996 Microchip Technology Inc DS30559A page 75 PIC16C64X amp PIC16C66X 10 2 Instruction Descriptions ADDLW Add Literal and W Syntax label ADDLW k Operands 0 lt k lt 255 Operation W k gt W Status Affected DC Z Encoding 11 111x kkkk kkkk Description The content
70. 1 Typical 0 048 0 052 C 0 228 0 305 Typical 0 009 0 012 D 35 204 35 916 1 386 1 414 D1 32 893 33 147 BSC 1 295 1 305 E 7 620 8 128 0 300 0 320 E1 7 366 7 620 0 290 0 300 el 2 413 2 667 Typical 0 095 0 105 eA 7 366 7 874 BSC 0 290 0 310 eB 7 594 8 179 0 299 0 322 L 3 302 4 064 0 130 0 160 5 1 143 1 397 0 045 0 055 51 0 533 0 737 0 021 0 029 1996 Microchip Technology Inc Preliminary DS30559A page 107 PIC16C64X amp PIC16C66X Package Type 40 Lead Ceramic Dual In Line with Window JW 600 mil Pin No 1 Sk 1 Indicator eB Area D gt Base gt Se See Plane T eating Plne B1 1 lt elle A1A3 A2 B Package Group Ceramic CERDIP Dual In Line Millimeters Inches Typical Typical Typical Typical BSC BSC BSC BSC Typical Typical Si 0 381 1 778 0 015 0 070 DS30559A page 108 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X Package Type 40 Lead Plastic Dual In Line P 600 mil Pin No 1
71. 1019 seinyee4 DS30559A page 119 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X PIC16C6X Family of Devices E 4 S90IN9P 9599 JO 10 9911 0 SEJES 200 Jno 198 U09 L SION pue 94H uid 400 9 eues esn sadap X929 LOld Ajjigedeo uano UBIU pue 199 01d SPOJ Jaw 1 seori ep AIIWE L 9LOId IY d4OL dJOW 291d Javsn ZHNL did uld o7 9a Ozl IdS 02 139499191d dA10L 440W 001d 0 14 5 CULL did Uid 0 5 pVS9D9LIId dAON 091d Ud py lHVSn CHIL HHL did uid 0 Od ldS 59091014 4401 Ud py ZHL FHL did uid op 5 OHL 0799091018 3301 440W 001d 0 COWL did uid op 5 OHNL 92912014 dAON 907d uld py ZHNL did uid op 24 45 v999191d 1HvSn ZHNL 2108 9105 uid gz Od ldS OHNL 0899091014 luvsn DIOS dias uld gz 999191d dOSS 2105 dlas uid 8z 24 45 094291214 dOSS 2105 dlas uid 8z 79 4 24 45 ZHNL dOSS 2106 dids u
72. 4 2105 didd uld gz 929214 2 4 lt o LO LO o ep PIC16C64X amp PIC16C66X 2 0 PIC16C64X 8 16 66 DEVICE VARIETIES A variety of frequency ranges and packaging options are available Depending on application and production requirements the proper device option can be selected using the information in the Product Identification Sys tem page at the end of this data sheet When placing orders please use that page of the data sheet to spec ify the correct part number 2 1 UV Erasable Devices The UV erasable version offered in CERDIP package is optimal for prototype development and pilot programs This version can be erased and reprogrammed to any of the oscillator modes Microchip s PICSTART Plus and PRO MATE II programmers both support programming of the PIC16C64X amp PIC16C66X 2 2 One Time Programmable OTP Devices The availability of OTP devices is especially useful for customers who need flexibility for frequent code updates and small volume applications In addition to the program memory the configuration bits must also be programmed 2 3 Quick Turnaround Production QTP Devices Microchip offers a QTP Programming Service for factory production orders This service is made available for users who choose not to program a medium to high quantity of units and whose code pat terns have stabilized The devic
73. 4 04 ai a az ANS CLKOUT 3 0 TOIF bit INTCON lt 2 gt GIE bit INTCON lt 7 gt INSTRUCTION FLOW Inst PC Inst PC 1 Inst 0004h Inst 0005h Instruction fetched Inst PC 1 Inst PC Dummy cycle Dummy cycle Inst 0004h executed PC 4 PC PC 1 X Instruction Note 1 Interrupt flag bit TOIF is sampled here every 1 2 Interrupt latency 4Tcy where Tcy instruction cycle time 3 CLKOUT is available only in RC oscillator mode DS30559A page 42 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 6 2 Using 0 with External Clock When an external clock input is used for 0 it must meet certain requirements The requirements ensure the external clock can be synchronized with the internal phase clock Tosc Also there is a delay in the actual incrementing of TimerO after synchronization 6 2 1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used the external clock input is the same as the prescaler output The synchronization of TOCKI with the internal phase clocks is accom plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks Figure 6 5 Therefore it is necessary for TOCKI to be high for at least 2Tosc and a small RC delay of 20 ns and low for at least 2Tosc and a small R
74. 4X amp PIC16C66X s orthogonal instruction set allows read and write of all file registers including special function registers There are some special situ ations the user should be aware of 10 1 1 STATUS AS DESTINATION If an instruction writes to STATUS the Z C and DC bits may be set or cleared as a result of the instruction and overwrite the original data bits written For example executing CLRF STATUS Will clear register STATUS and then set the Z bit leaving 0000 0100b in the reg ister 10 1 2 PCL AS SOURCE OR DESTINATION Read write or read modify write on PCL may have the following results Read PC PCL dest Write PCL PCLATH PCH 8 bit destination value PCL Read Modify Write PCL ALU operand PCLATH PCH 8 bit result gt PCL Where PCH program counter high byte not an addressable register PCLATH Program counter high holding latch dest destination WREG or f 10 1 3 BIT MANIPULATION All bit manipulation instructions are done by first read ing the entire register operating on the selected bit and writing the result back read modify write The user should keep this in mind when operating on special function registers such as ports DS30559A page 74 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X TABLE 10 2 INSTRUCTION SET Mnemonic Description Cycles 14 Bit Opcode Status Notes Operands MSb LSb Affec
75. 5 5700 Fax 86 21 6275 5060 DNV MSC USA The Netherlands Accredited by the RvA DNY ISO 9001 QS 9000 REGISTERED FIRM gt A m o m e ASIA PACIFIC continued Singapore Microchip Technology Singapore Pte Ltd 200 Middle Road 07 02 Prime Centre Singapore 188980 Tel 65 334 8870 Fax 65 334 8850 Taiwan R O C Microchip Technology Taiwan 10F 1C 207 Tung Hua North Road Taipei Taiwan ROC Tel 886 2 2717 7175 Fax 886 2 2545 0139 EUROPE United Kingdom Arizona Microchip Technology Ltd 505 Eskdale Road Winnersh Triangle Wokingham Berkshire England RG41 5TU Tel 44 118 921 5858 Fax 44 118 921 5835 Denmark Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1 3 Ballerup DK 2750 Denmark Tel 45 4420 9895 Fax 45 4420 9910 France Arizona Microchip Technology SARL Parc Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A ler Etage 91300 Massy France Tel 33 1 69 53 63 20 Fax 33 1 69 30 90 79 Germany Arizona Microchip Technology GmbH Gustav Heinemann Ring 125 D 81739 M nchen Germany Tel 49 89 627 144 0 Fax 49 89 627 144 44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V Le Colleoni 1 20041 Agrate Brianza Milan ltaly Tel 39 039 65791 1 Fax 39 039 6899883 11 15 99 Microchip received QS 9000 quality system certification for its worldwide headquarters design and wafer fabrication fa
76. 631 273 5305 Fax 631 273 5335 San Jose Microchip Technology Inc 2107 North First Street Suite 590 San Jose CA 95131 Tel 408 436 7950 Fax 408 436 7955 All rights reserved 1999 Microchip Technology Incorporated Printed in the USA 11 99 DNV Certification Inc ANSI AMERICAS continued Toronto Microchip Technology Inc 5925 Airport Road Suite 200 Mississauga Ontario L4V 1W1 Canada Tel 905 405 6279 Fax 905 405 6253 ASIA PACIFIC Hong Kong Microchip Asia Pacific Unit 2101 Tower 2 Metroplaza 223 Hing Fong Road Kwai Fong N T Hong Kong Tel 852 2 401 1200 Fax 852 2 401 3431 Beijing Microchip Technology Beijing Unit 915 6 Chaoyangmen Bei Dajie Dong Erhuan Road Dongcheng District New China Hong Kong Manhattan Building Beijing 100027 PRC Tel 86 10 85282100 Fax 86 10 85282104 India Microchip Technology Inc India Liaison Office No 6 Legacy Convent Road Bangalore 560 025 India Tel 91 80 229 0061 Fax 91 80 229 0062 Japan Microchip Technology Intl Inc Benex S 1 6F 3 18 20 Shinyokohama Kohoku Ku Yokohama shi Kanagawa 222 0033 Japan Tel 81 45 471 6166 Fax 81 45 471 6122 Korea Microchip Technology Korea 168 1 Youngbo Bldg 3 Floor Samsung Dong Kangnam Ku Seoul Korea Tel 82 2 554 7200 Fax 82 2 558 5934 Shanghai Microchip Technology RM 406 Shanghai Golden Bridge Bldg 2077 Yan an Road West Hong Qiao District Shanghai PRC 200335 Tel 86 21 627
77. 8 pin PIC16CR54A 20 pin PIC16C56 PIC16C58A PIC16CR58A PIC16C61 PIC16C554 PIC16C556 PIC16C558 PIC16C620 PIC16C621 PIC16C622 PIC16C710 PIC16C71 PIC16C711 PIC16F83 PIC16CR83 PIC16C84 PIC16F84A PIC16CR84 PIC16C55 28 pin PIC16C57 PIC16CR57B PIC16C62 PIC16CR62 16 62 PIC16C63 28 pin PIC16C72 PIC16C73 PIC16C73A PIC16C64 PIC16CR64 PIC16C64A 40 pin PIC16C65 PIC16C65A PIC16C74 PIC16C74A 17 42 PIC17CR42 17 42 40 17 43 PIC17CR43 PIC17C44 PIC16C923 PIC16C924 64 68 pin 1996 Microchip Technology Inc DS30559A page 125 PIC16C64X amp PIC16C66X NOTES AE DS30559A page 126 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X INDEX Code Examples Changing Prescaler to WDT 45 A Changing Prescaler WDT to TO 45 ADDLW Instruction 76 Indirect Addressing eee 28 ADDWF Instruction rio eto e iere 76 Initializing Comparator Module 49 ANDLW INStrUCHON uses canines 76 Initializing PORTA 29 ANDWF Instruction 76 Initializing PORTO zen 34 Architectural Overview ttt 9 Read Modify Write Instructions on an 1 Port 38 Assemblar M en eis re 88 Saving the STATUS and W Registers in RAM 68 Voltage Reference Configuration 54 B Code Pr
78. 91d dAON ddO L 091d did EHAL THNL eryoZLOld dAON ddO L 091d Uld py did EHAL THNL EvOLLOld d4OW ddOL 091d Uld pr did EHAL THNL 219 dAON ddOL 091d Uld pr did EHAL THNL VevoZLlold 99714 did EHAL THNL HHIAL OHIALL SoJnjeeJ evOLlold 1996 Microchip Technology Inc DS30559A page 124 PIC16C64X amp PIC16C66X PIN COMPATIBILITY Devices that have the same package type and 55 and locations are said to be pin compatible This allows these different devices to operate in the same socket Compatible devices may only requires minor software modification to allow proper operation in the application socket PIC16C56 PIC16C61 devices Not all devices in the same package size are pin compatible for example the PIC16C62 is compatible with the PIC16C63 but not the PIC16C55 Pin compatibility does not mean that the devices offer the same features As an example the PIC16C54 is pin compatible with the PIC16C71 but does not have an A D converter weak pull ups on PORTB or interrupts TABLE E 1 PIN COMPATIBLE DEVICES Pin Compatible Devices Package PIC12C508 PIC12C509 8 pin PIC16C54 PIC16C54A 1
79. 9A page 89 PIC16C64X amp PIC16C66X DEVELOPMENT TOOLS FROM MICROCHIP TABLE 11 1 LOO OEWQ 10090 Dd VIN 106 00 00250 VIN VIN VIN LOOVLLAG 80021111 sNOHdHd 1295 00 SIM ny junoes ny Ayin99S BuiddoH WM susubiseg G1VA33S ny 1ueuidojo eg 639nvoans 1onpoid ped 10 SU9 S S ees SEJNPOLU 19206 31VIA 5 NSVdIN 31VIN siequinu Jed JO HALSVWOId HALSVWOId IV pue NIS AVIdIN Sapnu JUSLUUOJIAUJ paeau ayep 10 Bojouuoe 1901002 20124 vv Ov Ver LO0800Ad 200200 12004219 LOOSOOAGC 900900MS S00900MS 200Z00MS LEEZ9 200200 19029 LNE L00G00Ad 900900MS 400900MS 200Z00MS EZ6O9LOld ZOLZOLWA 20029 200200 62049LIN3 LOOSOOAGC 900900MS GO0900MS 200 00 5 8491014 20129 8 200G00AG LO0800Ad 20029 200200 90229 LINA 620291WN3 L00S00Ad 900900
80. C delay of 20 ns Refer to the electrical specification of the desired device When a prescaler is used the external clock input is divided by the asynchronous ripple counter type pres caler so that the prescaler output is symmetrical For the external clock to meet the sampling requirement the ripple counter must be taken into account There fore it is necessary for TOCKI to have a period of at least 4Tosc and a small RC delay of 40 ns divided by the prescaler value The only requirement on TOCKI high and low time is that they do not violate the mini mum pulse width requirement of 10 ns Refer to param eters 40 41 and 42 in the electrical specification of the desired device 6 2 2 TIMERO INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks there is a small delay from the time the external clock edge occurs to the time the TimerO mod ule is actually incremented Figure 6 5 shows the delay from the external clock edge to the timer incrementing FIGURE 6 5 TIMERO TIMING WITH EXTERNAL CLOCK 011 Q21 03104 21 03104 Q1I Q21 03104 Q11 021 031 Q4 External Clock Inpyt or Prescaler output 1 3 External Clock Prescaler Output after sampling Small pulse PX misses sampling Increment 0 04 0 0 1 Note 1 Delay from clock input change to is 3Tosc to 7 Duration of There
81. D 1 Complement f label 0 lt 1 lt 127 d e 0 1 f 2 dest Z 00 1001 dfff ffff The contents of register are comple mented If is 0 the result is stored in W If is 1 the result is stored back in register f 1 1 COMF REG1 0 Before Instruction REG1 0 13 After Instruction REG1 0 13 W OxEC DECF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example DECFSZ Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Decrement f label DECF f d 0 lt 1 lt 127 de 0 1 f 1 dest Z 00 0011 ffff Decrement register f If d is O the result is stored in the W register If d is 1 the result is stored back in register 1 1 DECF CNT 1 Before Instruction CNT 0x01 Z 0 After Instruction CNT 0x00 Z 1 Decrement f Skip if 0 label DECFSZ f d 0 lt 1 lt 127 de 0 1 f 1 gt dest skip if result 0 None 00 1011 ffff The contents of register are decre mented If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f If the result is 0 the next instruction which is already fetched is discarded A NOP is executed instead making it a two cycle instruction 1 1 2 HERE DECFSZ CNT 1 GOTO LOOP CONTINUE Before I
82. DS30559A page 100 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X FIGURE 12 6 TIMERO CLOCK TIMING RA4 TOCKI TABLE 12 7 TIMERO REQUIREMENTS Characteristic Conditions TOCKI High Pulse Width Prescaler With Prescaler No Prescaler With Presca TOCKI Low Pulse Width TOCKI Period ns value 1 2 4 256 These parameters characteriz t T Data Typ column is at 5 0V 25 C S o and are not tested V YY 5 stated These parameters are for design guidance only 1996 Microchip Technology Inc Preliminary DS30559A page 101 PIC16C64X amp PIC16C66X FIGURE 12 7 PARALLEL SLAVE PORT TIMING PIC16C661 AND PIC16C662 RE2 CS REO RD RR 4 RE1 WR RD7 RDO Parameter Sym i Conditions No 62 TdtV2wrH 63 TwrH2dtl 64 TrdL2dtV 65 TrdH2dtl t Data in Typ column is at 5V tested DS30559A page 102 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 13 0 DEVICE CHARACTERIZATION INFORMATION NOT AVAILABLE AT THIS TIME ee ON 1996 Microchip Technology Inc Preliminary DS30559A page 103 1 am AMA PIC16C64X amp PIC16C66X NOTES DS30559A page 104 Preliminary
83. E ADDLW and SUBLW Two instructions TRIS and opTION being phased out although they are kept for compatibility with PIC16C5X OPTION and TRIS registers are made addressable Interrupt capability is added Interrupt vector is at 0004h Stack size is increased to 8 deep Reset vector is changed to 0000h Reset of all registers is revisited Six different reset and wake up types are recognized Registers are reset differently Wake up from SLEEP through interrupt is added Two separate timers Oscillator Start up Timer OST and Power up Timer PWRT are included for more reliable power up These timers can be invoked selectively to avoid unnecessary delays on power up and wake up PORTB has weak pull ups and interrupt on change feature TimerO clock input TOCKI pin is also port pin RA4 TOCKI and has a TRIS bit FSR is made a full 8 bit register In circuit programming is made possible The user can program PIC 16CXX devices using only five pins VDD Vss VPP RB6 clock and RB7 data in out PCON status register is added with a Power on Reset status bit POR a Brown out Reset sta tus bit BOR a Parity Error Reset PER and a Memory Parity Enable MPEEN bit Code protection scheme is enhanced such that portions of the program memory can be protected while the remainder is unprotected PORTA inputs are now Schmitt Trigger inputs Brown out Reset circuitry has been added the user should t
84. EP instruction 0 A WDT time out occurred bit 3 PD Power down bit 1 After power up or by the CLRWDT instruction 0 By execution of the SLEEP instruction bit 2 Z Zero bit 1 The result of an arithmetic or logic operation is zero 0 The result of an arithmetic or logic operation is not zero bit 1 1 carry out from the 4th low order bit of the result occurred 0 No carry out from the 4th low order bit of the result bit 0 Carry borrow bit ADDWF ADDLW SUBLW SUBWF instructions 1 Acarry out from the most significant bit of the result occurred 0 No carry out from the most significant bit of the result occurred Note For borrow the polarity is reversed A subtraction is executed by adding the two s complement of the second operand For rotate RRF RLF instructions this bit is loaded with either the high or low order bit of the source register 1996 Microchip Technology Inc Preliminary DS30559A page 21 PIC16C64X amp PIC16C66X 4 2 2 2 OPTION REGISTER The OPTION register is a readable and writable register which contains various control bits to configure the TMRO WDT prescaler the external RBO INT interrupt TMRO and the weak pull ups on PORTB Note To achieve a 1 1 prescaler assignment for TMRO assign the prescaler to the WDT FIGURE 4 6 OPTION REGISTER ADDRESS 81h R W 1 R W 1 RMW 1 R W 1 R i R W 1 R W 1 1 RBPU INTEDG TOCS TOSE PSA PS2 PS1 PSO R Reada
85. ERENCE SIGNAL When external voltage references are used the comparator module can be configured to have the com parators operate from the same or different reference sources However threshold detector applications may require the same reference The reference signal must be between Vss and and can be applied to either pin of the comparator s 7 3 2 INTERNAL REFERENCE SIGNAL The comparator module also allows the selection of an internally generated voltage reference for the comparators Section 8 0 contains a detailed descrip tion of the Voltage Reference Module that provides this signal The internal reference signal is used when the comparators are 2 010 Figure 7 2 In this mode the internal voltage refer ence is applied to the Vin pin of both comparators 1996 Microchip Technology Inc Preliminary DS30559A page 49 PIC16C64X amp PIC16C66X 7 4 Comparator Response Time Response time is the minimum time after selecting a new reference voltage or input source before the comparator output is guaranteed to have a valid level If the internal reference is changed the maximum delay of the internal voltage reference must be considered when using the comparator outputs Otherwise the maximum delay of the comparators should be used Table 12 2 and Table 12 3 7 5 Comparator Outputs The comparator outputs are read through the CMCON register These bits are read only The
86. Fetch SUB 1 Execute SUB 1 All instructions are single cycle except for any program branches These take two cycles since the fetch instruction is flushed from the pipeline while the new instruction is being fetched and then executed 1996 Microchip Technology Inc Preliminary DS30559A page 15 PIC16C64X amp PIC16C66X NOTES EE DS30559A page 16 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 4 0 MEMORY ORGANIZATION FIGURE 4 2 PIC16C642 662 PROGRAM MEMORY MAP AND STACK 4 1 Program Memory Organization The PIC16C64X amp PIC16C66X have a 13 bit program counter capable of addressing an 8K x 14 program memory space For PIC16C641 and PIC16C661 CALL RETURN 13 only the first 2K x 14 0000h 07FFh is physically PR DETEN 7 implemented For the PIC16C642 and PIC16C662 only the first 4K x 14 0000h OFFh is physically imple Stack Level 1 mented Accessing a location above the 2K or 4K Stack Level 2 boundary will cause a wrap around The reset vector is at 0000h and the interrupt vector is at 0004h Figure 4 2 1 and Figure 4 2 See Section 4 4 for Program b ory paging Stack Level 8 FIGURE 4 1 16 641 661 PROGRAM MEMORY MAP AND STACK Reset Vector PC lt 12 0 gt CALL RETURN 13 RETFIE RETLW Interrupt Vector Stack Level 1 Stack Level 2 Stack Level 8 On
87. IC16C64X amp PIC16C66X 4 2 2 4 PIE1 REGISTER This register contains the individual enable bits for the comparator and Parallel Slave Port interrupts FIGURE 4 8 PIE1 REGISTER ADDRESS 8Ch R W 0 R W 0 U 0 U 0 U 0 U 0 U 0 U 0 PSPIE R Readable bit bit7 bitO W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit7 X PSPIE Parallel Slave Port Read Write Interrupt Enable bit 1 Enables the PSP read write interrupt 0 Disables the PSP read write interrupt bit 6 CMIE Comparator Interrupt Enable bit 1 Enables the Comparator interrupt 0 Disables the Comparator interrupt bit 5 0 Unimplemented Read as 0 Note 1 Bit PSPIE is reserved on the PIC16C641 642 always maintain this bit clear DS30559A page 24 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 4 2 2 5 PIR1 REGISTER Note Interrupt flag bits get set when an interrupt This register contains the individual flag bits for the condition occurs regardless of the state of comparator and Parallel Slave Port interrupts its corresponding enable bit or the global enable bit GIE INTCON lt 7 gt User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt FIGURE 4 9 PIR1 REGISTER ADDRESS 0Ch R W 0 R W 0 U 0 U 0 U 0 U 0 U 0 U 0 PsPIF
88. IC16C64X amp PIC16C66X devices have on chip Brown out Reset circuitry A configuration bit BODEN can disable if clear programmed or enable if set the Brown out Reset circuitry If VDD falls below 4 0V Parameter 0005 in ES section for greater than parameter 35 in Table 12 6 the brown out situation will reset the chip A reset is not guaranteed to occur if VDD falls below 4 0V for less than parameter 35 The chip will remain in Brown out Reset until VDD rises above BVDD The Power up Timer will now be invoked and will keep the chip in reset an additional 72 ms If VDD drops below BVDD while the Power up Timer is running the chip will go back into a Brown out Reset and the Power up Timer will be initialized Once VDD rises above the Power up Timer will execute a 72 ms time delay The Power up Timer should always be enabled when Brown out Reset is enabled Figure 9 8 shows typical Brown out situations Internal Reset VDD BVDD Max 77 BVDD Min BVDD Min Internal 272 ms Reset 72 ms BVDD Max Internal Reset 7 BVop Min DS30559A page 60 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 9 45 PARITY ERROR RESET PER PIC16C64X amp PIC16C66X devices have on chip parity bits that can be used to verify the contents of program memory Parity bits may be useful in applications in order to increase overall r
89. ING PORTA CLRF PORTA Initialize PORTA by clearing output latches MOVLW 0x07 Turn comparators off MOVWF enable pins for I O BSF STATUS RPO Select bankl MOVLW 0x1F Value to initialize data direction Set RA 4 0 as inputs TRISA lt 7 5 gt are clear MOVWF TRISA 1996 Microchip Technology Inc Preliminary DS30559A page 29 1 AMA PIC16C64X amp PIC16C66X FIGURE 5 2 DIAGRAM OF RA2 PIN Q D CK 7 H Data Latch D a N RA2 Pin IRIS Y TRIS Latch Vss Analog Input Mode Schmitt Trigger Input Buffer RD PORT To Comparator VROE VREF s e Note I O pin has protection diodes to VDD and Vss FIGURE 5 3 BLOCK DIAGRAM OF PIN Comparator Mode 110 Comparator Output pos OT ci G Data Latch D Q gt lt RAS Pin CK G En y TRIS Latch Vss Analog Input Mode Schmitt Trigger Input Buffer RD TRIS RD PORT gt To Comparator DS30559A page 30 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X FIGURE 5 4 BLOCK DIAGRAM PIN Comparator Mode 110 Comparator Output p OT pok Data Latch D Q IRIS G D TRIS L
90. IOUS SITUATIONS Power up Oscillator Configuration Brown out Reset ne PWRTE 0 PWRTE 1 XT HS LP 72 ms 1024 Tosc 1024 Tosc 72 ms 1024 Tosc 1024 Tosc RC 72 ms 72 ms 1996 Microchip Technology Inc Preliminary DS30559A page 61 PIC16C64X amp PIC16C66X TABLE 9 4 STATUS BITS AND THEIR SIGNIFICANCE PER POR BOR TO PD 1 0 x 1 1 Reset x 0 x 0 x Illegal TO is set on POR x 0 x x 0 Illegal PD is set on POR 1 0 1 1 Brown out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake up 1 1 u u reset during normal operation 1 1 1 0 reset during SLEEP 0 1 1 1 1 Parity Error Reset 0 0 x x x Illegal PER is set on POR 0 x 0 x x Illegal PER is set on BOR TABLE 9 5 INITIALIZATION CONDITION FOR SPECIAL REGISTERS Condition Program STATUS PCON Counter Register Register Power on Reset 000h 0001 1xxx u 10x MCLR reset during normal operation 000h 000u uuuu u uuu MCLR reset during SLEEP 000h 0001 Ouuu u uuu WDT reset 000h 0000 1uuu u uuu WDT Wake up PC 1 uuu0 Ouuu u uuu Brown out Reset 000h 0001 luuu u uu0 Parity Error Reset 000h 0001 1uuu 1 0uu Interrupt Wake up from SLEEP PC 10 uuul Ouuu u uuu Legend u unchanged x unknown unimplemented bit reads as 0 Note 1 When the wake up is due to an interrupt and global enable bit GIE is set the PC is
91. LEEP through external reset Watchdog Timer wake up or through an interrupt Several oscillator options are also made available to allow the part to fit the application The RC oscillator option saves system cost while the LP crystal option saves power A set of configuration bits are used to select various options 1996 Microchip Technology Inc Preliminary DS30559A page 55 1 AMA PIC16C64X amp PIC16C66X 9 1 Configuration Bits The configuration bits can be programmed read as 0 or left unprogrammed read as 1 to select various device configurations These bits are mapped in program memory location 2007h The user will note that address 2007h is beyond the user program memory space In fact it belongs to the special test configuration memory space 2000h 3FFFh which be accessed only during programming FIGURE 9 1 CONFIGURATION WORD CP1 CP1 CP1 CPO MPEEN BODEN CP1 PWRTE WDTE FOSC1 FOSCO CONFIG Address REGISTER 2007h bit13 bito bit 13 8 CP1 CPO Code protection bits 5 4 11 Code protection off 10 Upper half of program memory code protected 01 Upper 3 4th of program memory code protected 00 All memory is code protected MPEEN Memory Parity Error Enable 1 Memory Parity Checking is enabled 0 Memory Parity Checking is disabled BODEN Brown out Reset Enable bi
92. MICROCHIP PIC16C64X amp PIC16C66X 8 Bit EPROM Microcontrollers with Analog Comparators Devices included in this data sheet PIC16C641 PIC16C642 PIC16C661 PIC16C662 High Performance RISC CPU Only 35 instructions to learn All single cycle instructions 200 ns except for program branches which are two cycle Operating speed DC 20 MHz clock input DC 200 ns instruction cycle Device Program Data Memory x14 Memory x8 PIC16C641 2K 128 PIC16C642 4 176 PIC16C661 2K 128 PIC16C662 4K 176 Interrupt capability 8 level deep hardware stack Direct Indirect and Relative addressing modes Peripheral Features Up to 33 I O pins with individual direction control High current sink source for direct LED drive Analog comparator module with Two analog comparators Programmable on chip voltage reference VREF module Programmable input multiplexing from device inputs and internal voltage reference Comparator outputs can be output signals e TimerO 8 bit timer counter with 8 bit programmable prescaler Special Microcontroller Features Power on Reset POR Power up Timer PWRT and Oscillator Start up Timer OST Brown out Reset Watchdog Timer WDT with its own on chip RC oscillator for reliable operation Programmable code protection Power saving SLEEP mode Selectable oscillator options Serial in circuit programming v
93. MS S00900MS 200700MS 899191d 20129 8 200 lt 00 20029 200200 62049LIN3 LOOSOOAGC 900900MS GO0900MS 200 00 5 68 904 01Z9LIN3 LO0800Ad 20029LAG 200200 SZOZ9LINA 900900MS 400900MS 200Z00MS 22991014 90129 200G00AG 20029 00Z00AC 12201919 L00G00Ad 900900MS S00900MS 200700MS 147012291214 0129 1 20029 200200 90229 22029 4 L00800AG 900900MS 400900MS 200 00 5 42509214 90129 099 LOOEOOAG 0029 200200 GEO0Z9LWA S00900MS 200Z00MS 499 279 179091014 20149 200 lt 00 Vel pl VEL EL 20029 200200 v0249LIN3 82049 LIN3 LOOSOOAGC 900900MS GO0900MS 200 00 5 4 69 G9 29091019 60129 43 LOOEOOAG 20029 200200 20229 2029LN3 L00S800AG 900900MS 400900MS 200Z00MS 229 29 029091014 20129 V9 9 LOOEOOAG 20029 200200 20249 GZOL9LWA L00SO0AQG 900900MS S00900MS 200Z00MS 729 29291014 VIN LO0800Ad 20029 200200 902 9 LZ0Z9LIWA LOOSOOAG 900900MS S00900MS 200Z00MS 1999191d LLZ9LINJ 200G00AG LOOEOOAG 200200 S 0291WN3 L00S00Ad 400900MS 200Z00MS 899 966 GGD9LOId LOLZOLWA 200 lt 00 v8S 76 9G GG 20029 200200 10229 LWA 81049 48 LOOSOOAGC 900900MS S00900MS 200200MS 2609214 LOOEOOAG
94. ORTD Data Latch when written PORTD pins when read xxxx uuuu uuuu 06h PORTEO RE2 RE1 xxx uuu 0Ah PCLATH Write buffer for upper 5 bits of program counter 0000 0 0000 OBh INTCON INTE RBIE TOIF INTF 000x 0000 000u 0Ch PIR1 5 MM 00 ODh 1Eh Unimplemented 1Fh CMCON C20UT 0000 00 0000 INDF Addressing this location uses contents of FSR to address data memory not a physical register RBPU INTEDG TOCS TOSE PSA PS2 PS1 PSO 111 1111 1111 PCL Program Counter s PC Least Significant Byte 0000 0000 0000 STATUS IRP 1 TO PD DC C xxx 000g quuu FSR Indirect data memory address pointer XXXX uuuu uuuu TRISA PORTA Data Direction Register 111 11 1111 TRISB PORTB Data Direction Register 111 1111 1111 TRISC PORTC Data Direction Register 111 2111 1111 TRISD PORTD Data Direction Register 111 1111 1111 TRISE IBF IBOV PSPMODE TRISE2 TRISE1 TRISEO 111 0000 111 PCLATH Write buffer for upper 5 bits of program counter 0000 0 0000 INTCON GIE TOIE INTE RBIE TOIF INTF RBIF 000 0000 000 8Ch PIE1 PSPIE 00 00 8Dh Unimplemented 8Eh PCON MPEEN PER POR BOR u qqq u uuu 8Fh 9Eh Unimplemented 9Fh VRCON VREN VROE VRR VR3 VR2 VR1 VRO 000 0000 000 0000 Legend unimplemented locations read as 0 u unchanged x unknown value depends on condition shaded unim
95. PIC16C66X NOP No Operation Syntax label Operands None Operation No operation Status Affected None Encoding 00 0000 OxxO 0000 Description No operation Words 1 Cycles 1 Example NOP OPTION Load Option Register Syntax abel OPTION Operands None Operation W gt OPTION Status Affected None Encoding 00 0000 0110 0010 Description The contents of the W register are loaded in the OPTION register This instruction is supported for code com patibility with PIC16C5X products Since OPTION a readable writable register the user can directly address it Words 1 Cycles 1 maintain upward compatibility with future PIC16CXX products do not use this instruction RETFIE Syntax Operands Operation Status Affected Encoding Description Words Cycles Example RETLW Syntax Operands Operation Status Affected Encoding Description Words Cycles Example TABLE Return from Interrupt label RETFIE None TOS PC 1 GIE None 00 0000 0000 1001 Return from Interrupt Stack is POPed and Top of Stack TOS is loaded in the PC Interrupts are enabled by set ting Global Interrupt Enable bit GIE lt 7 gt This is a two cycle instruction 1 2 RETFIE After Interrupt PC TOS GIE 1 Return with Literal W label RETLW k 0 lt k lt 255 2 W TOS
96. Param Sym Characteristic Min TypT Max Units Conditions No D001 VDD Supply Voltage XT RC and LP osc config 1 D001A HS osc configuration D002 VDR RAM Data Retention Voltage Device in SLEEP m de 0003 VPOR VDD start voltage to See section on Power or ReseNor ensure internal Power on details Reset signal D004 SVDD VDD rise rate to ensure internal V ms See sectio Power on Reset signal 0005 Brown out Reset Voltage V D010 IDD Supply Current XT 2086 disabled 4 D010A sc configuration PIC16C64X amp PIC16C66X 04 only Fosc 32 kHz 4 0 WDT disabled D013 HS osc configuration Fosc 20 MHz VDD 5 5V WDT disabled Module Differential Gare 0015 AIBOR Brown out Reset Current BODEN bit is clear VDD 5 0V D016 Comparator VDD 4 0V each Compa 0017 AIVREF VDD 4 0V D021 AlwoT WD VDD 4 0V Automotive 0021 IPD Power 4 0V WDT disabled These pa TU Data Typ golugn is t 5 0V 25 C unless otherwise stated These parameters are for design guidance only loading and switching rate oscillator type internal code execution pattern and temperature also have an impast o the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all I O pins tri stated pulled to VDD MCLR VDD WDT enabled disabled as specified T
97. Port Set RBIF From other 545 zA __ RB7 RB4 pins Q P EN RD Port RB7 RB6 in serial programming mode Note 1 O pins have diode protection to VDD and Vss 2 TRISB 1 enables weak pull up if 0 OPTION lt 7 gt DS30559A page 32 Preliminary This interrupt can wake the device from SLEEP The user in the interrupt service routine can clear the interrupt in the following manner a Any read or write of PORTB This will end the mismatch condition b Clear flag bit RBIF A mismatch condition will continue to set flag bit RBIF Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared This interrupt on mismatch feature together with software configurable pull ups on these four pins allow easy interface to a keypad and make it possible for wake up on key depression See AN552 in the Microchip Embedded Control Handbook The interrupt on change feature is recommended for wake up on key depression operation and operations where PORTB is only used for the interrupt on change feature Polling of PORTB is not recommended while using the interrupt on change feature FIGURE 5 6 BLOCK DIAGRAM OF RB3 RBO PINS REPU Data Latch Data bus WR Port WR TRIS RBO INT RD Port Note 1 O pins have diode protection to and Vss 2 TRISB
98. TB to be read m mI into the CPU Then the BsF operation takes place on BCF STATUS RP1 bitb and PORTB is written to the output latches If BSF STATUS RPO another bit of PORTB is used as a bi directional I O pin BCF TRISB 7 10pp 11 e g bit0 and it is defined as an input at this time the BCF TRISB 6 10 10 input signal present on the pin itself would be read into Note that the user may have expected the pin values to be 00pp ppp The 2nd BCF the CPU and rewritten to the data latch of this particular pin overwriting the previous content As long as the pin stays in the input mode no problem occurs However if bitO is switched into output mode later on the content of the data latch may now be unknown 5 6 2 caused RB7 to be latched as the pin value high SUCCESSIVE OPERATIONS ON 1 0 Reading the port register reads the values of the port PORTS pins Writing to the port register writes the value to the port latch When using read modify write instructions 0 BSF etc on a port the value of the port pins is read the desired operation is done to this value and this value is then written to the port latch The actual write to an O port happens at the end of an instruction cycle whereas for reading the data must be valid at the beginning of the instruction cycle Figure 5 11 Therefore care must be exercised if a write followed by a read operati
99. TH INTCON INTCON PIR1 PIE1 INDF 80h PCON VRCON General Purpose General Register Purpose Register Mapped in Bank 0 FFh Bank 0 Bank 1 Unimplemented data memory loca tions read as Note 1 Not a physical register 2 Not implemented on the PIC16C642 1996 Microchip Technology Inc Preliminary DS30559A page 19 PIC16C64X amp PIC16C66X TABLE 4 1 SPECIAL FUNCTION REGISTERS on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BOR all other PER resets Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory not a physical register xxxx 01h TMRO TimerO Module s Register XXXX xxxx uuuu uuuu 02h PCL Program Counter s PC Least Significant Byte 0000 0000 0000 0000 STATUS PD 1xxx 000g quuu FSR Indirect data memory address pointer XXXX uuuu uuuu PORTA PORTA Data Latch when written PORTA pins when read 0000 xu 0000 PORTB PORTB Data Latch when written PORTB pins when read XXXX uuuu uuuu PORTC PORTC Data Latch when written PORTC pins when read XXXX uuuu uuuu PORTD P
100. URE 4 7 REGISTER ADDRESS OBh 8Bh R W 0O R W 0 HR W 0 R W 0 R W 0 R W 0 R W 0 R W x GIE PEIE TOIE INTE RBIE TOIF INTF RBIF R Readable bit bit7 bitO W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 GIE Global Interrupt Enable bit 1 Enables all un masked interrupts 0 Disables all interrupts bit 6 PEIE Peripheral Interrupt Enable bit 1 Enables all un masked peripheral interrupts 0 Disables all peripheral interrupts bit 5 TOIE TMRO Overflow Interrupt Enable bit 1 Enables the TMRO interrupt 0 Disables the TMRO interrupt bit 4 INTE RBO INT External Interrupt Enable bit 1 Enables the RBO INT external interrupt 0 Disables the external interrupt bit 3 RBIE RB Port Change Interrupt Enable bit 1 Enables the RB port change interrupt 0 Disables the RB port change interrupt bit 2 TOIF TMRO Overflow Interrupt Flag bit 1 TMRO register overflowed must be cleared in software 0 TMRO register did not overflow bit 1 RBO INT External Interrupt Flag bit 1 The RBO INT external interrupt occurred must be cleared in software 0 The RBO INT external interrupt did not occur bit 0 RBIF RB Port Change Interrupt Flag bit 1 When at least one of the RB7 RB4 pins changed state See Section 5 2 to clear interrupt 0 None of the RB7 RB4 pins have changed state O 1996 Microchip Technology Inc Preliminary DS30559A page 23 P
101. age 12 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X TABLE 3 2 PIC16C661 662 PINOUT DESCRIPTION DIP QFP PLCC Buffer Description Pin Pin Type Type OSC1 CLKIN 13 30 14 ST CMOS Oscillator crystal input or external clock source input OSC2 CLKOUT 14 31 15 O Oscillator crystal output Connects to crystal or reso nator in crystal oscillator mode In RC mode OSC2 pin outputs CLKOUT which has 1 4 the frequency of OSC1 and denotes the instruction cycle rate MCLR VPP 1 18 2 ST Master clear reset input or programming voltage input This pin is an active low reset to the device PORTA is bi directional I O port RAO ANO 2 19 3 ST Analog comparator input RA1 AN1 3 20 4 ST Analog comparator input RA2 AN2 VREF 4 21 5 ST Analog comparator input or VREF output RA3 AN3 5 22 6 ST Analog comparator input or comparator output RA4 TOCKI 6 23 7 ST Can be selected to be the clock input to the 0 timer counter or a comparator output Output is open drain type RA5 7 24 8 VO ST PORTB is a bi directional I O port PORTB can be software programmed for internal weak pull ups on all inputs RBO INT 33 8 36 VO TTL sT RBO can also be selected as an external interrupt pin RB1 34 9 37 VO TTL RB2 35 10 38 VO TTL RB3 36 11 39 VO TTL RB4 37 14 41 VO TTL Interrupt on change pin RB5 38 15 42 VO TTL
102. ake the following steps 1 Preliminary 1 Remove any program memory page select operations PA2 1 PAO bits for CALL Revisit any computed jump operations write to PC or add to PC etc to make sure page bits are set properly under the new scheme Eliminate any data memory page switching Redefine data variables to reallocate them Verify all writes to STATUS OPTION and FSR registers since these have changed Change reset vector to 0000h DS30559A page 115 PIC16C64X amp PIC16C66X APPENDIX WHAT S NEW APPENDIX D WHAT S CHANGED New Data Sheet New Data Sheet ER DS30559A page 116 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X PIC16 17 MICROCONTROLLERS PIC14000 Devices APPENDIX E 2 siojeseduuo 9 1 9315 10 99 9q Mv 02 00071014 10 924 UOIJEJII EJ josueg JOJEJ IDSO EUJ91U 00 dOSS 0105 did uid gz SseJnjee DS30559A page 117 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X PIC16C5X Family of Devices E 2 Auiqedeo ufu pue 199101d SPOD ajqejoajes eiqeioejes seoiep 7 L 9 LO dOSS uid 02 910S did uid 81 79 4 V8S499191d dOSS
103. apacitor Cext values and the operat ing temperature In addition to this the oscillator frequency will vary from unit to unit due to normal pro cess parameter variation Furthermore the difference in lead frame capacitance between package types will also affect the oscillation frequency especially for low Cext values The user also needs to take into account variation due to tolerance of external R and C compo nents used Figure 9 6 shows how the R C combina tion is connected to the PIC16CXXX For Rext values below 2 2 kQ the oscillator operation may become unstable or stop completely For very high Rext values e g 1 MQ the oscillator becomes sensitive to noise humidity and leakage Thus we recommend to keep Rext between 3 and 100 Although the oscillator will operate with no external capacitor Cext 0 pF we recommend using values above 20 pF for noise and stability reasons With no or small external capacitance the oscillation frequency can vary dramatically due to changes in external capacitances such as PCB trace capacitance or pack age lead frame capacitance See characterization data for desired device for RC fre quency variation from part to part due to normal pro cess variation The variation is larger for larger R since leakage current variation will affect RC frequency more for large R and for smaller C since variation of input capacitance will affect RC frequency more See characterization da
104. at this is an enhanced version of the PIC16C5X architecture Please refer to Appendix A for a detailed list of enhancements Code written for PIC16C5X can be easily ported to the PIC16C64X amp PIC16C66X Appendix B 1 2 Development Support PIC16C64X amp PIC16C66X devices are supported by the complete line of Microchip Development tools including MPLAB Integrated Development Environment including MPLAB Simulator MPASM Universal Assembler and MPLAB C Uni versal C compiler PRO MATE Il and PICSTART Plus device pro grammers PICMASTER In circuit Emulator System e fuzzyTECH MP Fuzzy Logic Development Tools DriveWay Visual Programming Tool Please refer to Section 11 0 for more details about these and other Microchip development tools 1996 Microchip Technology Inc Preliminary DS30559A page 5 1 ana 1996 Microchip Technology Inc pue yoojo Buruurej604d ESS asn sadap XXX99L91d IV Auigedeo 1ueuno UBIU pue Joajoud epoo ejqejoejes WWI 6opuoieM 9 ge199 9s 7 L 9 LOJ IY PIC16C64X amp PIC16C66X PIC16C64X amp PIC16C66X DEVICE FEATURES TABLE 1 1 d3OL 991d Ud py dl uid op 299991918 d3OL 991d uld py dlG9 dla 2105 did uid gz 2909101
105. atch s E Schmitt Trigger Input Buffer RD TRIS EN RD PORT TMRO Clock Input TABLE 5 1 PORTA FUNCTIONS Name Butler Function Type RAO ANO ST Input output or comparator input RA1 AN1 ST Input output or comparator input RA2 AN2 VREF bit2 ST Input output or comparator input or VREF output RA3 AN3 bit3 ST Input output or comparator input output RA4 TOCKI bit4 ST Input output or external clock input for TMRO or comparator output Out put is open drain type RA5 bit5 ST Input output Legend ST Schmitt Trigger input TABLE 5 2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 POR all other BOR resets 05h PORTA RA5 RA4 RA3 RA2 RA1 RAO 0000 uu 0000 85h TRISA TRISAS5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 11 1111 11 1111 1Fh CMCON C2OUT CIOUT CIS CM2 1 00 0000 00 0000 9Fh VRCON VREN VROE VRR VR3 VR2 VR1 VRO 000 0000 000 0000 Legend x unknown u unchanged unimplemented locations read as 0 Shaded cells are not used by PORTA O 1996 Microchip Technology Inc Preliminary DS30559A page 31 PIC16C64X amp PIC16C66X 5 2 PORTB and TRISB Registers PORTB is 8 bit wide bi directional port The corresponding data direction
106. ble bit bit7 bitO W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 RBPU PORTB Pull up Enable bit 1 PORTB pull ups are disabled 0 PORTB pull ups are enabled by individual port latch values bit 6 INTEDG Interrupt Edge Select bit 1 2 Interrupt on rising edge of RBO INT pin 0 Interrupt on falling edge of RBO INT pin bit 5 TOCS TMRO Clock Source Select bit 1 Transition on RA4 TOCKI pin 0 Internal instruction cycle clock CLKOUT bit 4 TOSE TMRO Source Edge Select bit 1 Increment on high to low transition on RA4 TOCKI pin 0 Increment on low to high transition on RA4 TOCKI pin bit 3 PSA Prescaler Assignment bit 1 Prescaler is assigned to the WDT 0 Prescaler is assigned to the TimerO module bit 2 0 PS2 PSO Prescaler Rate Select bits Bit Value TMRO Rate WDT Rate 000 1 2 1 1 001 1 4 1 2 010 1 8 1 4 011 1 16 1 8 100 1 32 1 16 101 1 64 1 32 110 1 128 1 64 111 1 256 1 128 DS30559A page 22 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 4 2 2 3 INTCON REGISTER Note Interrupt flag bits get set when interrupt The INTCON register is a readable and writable condition occurs regardless of the state of register which contains the various enable and flag bits its corresponding enable bit or the global for all non peripheral interrupt sources enable bit GIE INTCON lt 7 gt FIG
107. ble by using an FTP ser vice to connect to ftp mchip com biz mchip The web site and file transfer site provide a variety of services Users may download files for the latest Development Tools Data Sheets Application Notes User s Guides Articles and Sample Programs A vari ety of Microchip specific business information is also available including listings of Microchip sales offices distributors and factory representatives Other data available for consideration is Latest Microchip Press Releases Technical Support Section with Frequently Asked Questions Design Tips Device Errata Job Postings Microchip Consultant Program Member Listing Links to other useful web sites related to Microchip Products Connecting to the Microchip BBS Connect worldwide to the Microchip BBS using either the Internet or the CompuServe communications net Work Internet You can telnet or ftp to the Microchip BBS at the address mchipbbs microchip com CompuServe Communications Network When using the BBS via the Compuserve Network in most cases a local call is your only expense The Microchip BBS connection does not use CompuServe membership services therefore you do not need CompuServe membership to join Microchip s BBS There is no charge for connecting to the Microchip BBS The procedure to connect will vary slightly from country to country Please check with your local CompuServe agent for details if you have a pr
108. chip Program Memory 0 Es ao e o E W 2 On chip Program Memory Reset Vector 1 Interrupt Vector TEST Configuration Word Es ao o E W D On chip Program Memory TEST TEST Configuration Word TEST 1996 Microchip Technology Inc Preliminary DS30559A page 17 1 am AMA PIC16C64X amp PIC16C66X 4 2 Data Memory Organization FIGURE 4 3 16 641 661 DATA MEMORY The data memory Figure 4 4 is partitioned into two banks which contain the general purpose registers and File File the special function registers Bank 0 is selected when Address Address bit RPO STATUS lt 5 gt is cleared Bank 1 is selected 00h INDF INDF 1 80h when the bit is set The Special Function Regis oth TMRO OPTION 81h ters are located in the first 32 locations of each Bank 2 02h PCL PCL 82h Register locations AOh EFh Bank 1 are general pur pose registers implemented as static RAM Some spe 03h STATUS STATUS 83h cial function registers are mapped in Bank 1 04h FSR FSR 84h 05h PORTA TRISA 85h 4 2 1 GENERAL PURPOSE REGISTER FILE PORTB TRISB 86h The register file is organized as 176 x 8 for the PORTC TRISC 87h PIC16C642 662 and 128 x8 for the PIC16C641 661 PORTD TRISD 88h Each
109. chip reset circuit is shown in Figure 9 7 The MCLR reset path has a noise filter to detect and ignore small pulses See Table 12 6 for pulse width specification FIGURE 9 7 SIMPLIFIED BLOCK DIAGRAM OF ON CHIP RESET CIRCUIT External Reset X Program Memory gt Parity WDT SLEEP Module WDT Time out VDD rise detect Power on Reset Brown out Reset OST PWRT OST Chip_Reset r gt 10 bit Ripple counter gt OJ PWRT R Bo D gt 10 bit Ripple counter Enable PWRT See Table 9 3 for time out situations Enable OST Note 1 This is a separate oscillator from the RC oscillator of the CLKIN pin 1996 Microchip Technology Inc Preliminary DS30559A page 59 PIC16C64X amp PIC16C66X 9 4 Power on Reset Power up Timer Oscillator Start up Timer OST Brown out Reset BOR and Parity Error Reset PER 9 4 1 POWER ON RESET POR A Power on Reset pulse is generated on chip when VDD rise is detected in the range of 1 6V to 1 8V To take advantage of the POR just tie the MCLR pin directly or through a resistor to This will eliminate external RC components usually needed to create a Power on Reset A maximum rise time for VDD is requi
110. cilities in Chandler and Tempe Arizona in July 1999 The Company s quality system processes and procedures are QS 9000 compliant for its 8 bit MCUs KEELOG code hopping devices Serial EEPROMs microperipheral products In addition Microchip s quality system for the design and manufacture of development systems is ISO 9001 certified Printed on recycled paper Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information or infringement of patents or other intellectual property rights arising from such use or otherwise Use of Microchip s products as critical components in life support systems is not authorized except with express written approval by Microchip No licenses are conveyed implicitly or otherwise under any intellectual property rights The Microchip logo and name are registered trademarks of Microchip Technology Inc in the U S A and other countries All rights reserved All other trademarks mentioned herein are the property of their respective companies 1999 Microchip Technology Inc
111. comparator outputs also be directly output to the RA3 and RA4 pins When CM2 CMO 110 multiplexors in the output path of the RA3 and RA4 pins will switch and the output of each pin will be the unsynchronized output of the comparator The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications Figure 7 4 shows the comparator output block diagram The TRISA bits will still function as an output enable disable for the RA3 and RA4 pins while in this mode Note 1 When reading the PORTA register all pins configured as analog inputs will read as a 0 Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification Note 2 Analog levels on any pin that is defined as a digital input may cause the input buffer to consume more current than is speci fied FIGURE 7 4 COMPARATOR OUTPUT BLOCK DIAGRAM Port Pins MULTIPLEX To or RAA pin To Data Bus RD CMCON Set OMIF bit From other Comparator EN lt e RD CMCON CL NRESET DS30559A page 50 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 7 6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator User software will need to maintain inf
112. d Upgrade Hot Line The Systems Information and Upgrade Line provides System users a listing of the latest versions of all of Microchip s development systems software products Plus this line provides information on how customers can receive any currently available upgrade kits The Hot Line Numbers are 1 800 755 2345 for U S and most of Canada and 1 602 786 7302 for the rest of the world Trademarks The Microchip name logo PIC PICSTART PICMASTER and are registered trademarks of Microchip Technology Incorporated in the U S A and other countries FlexROM MPLAB PRO MATE and fuzzyLAB are trade marks and SQTP is a service mark of Microchip in the U S A fuzzyTECH is a registered trademark of Inform Software Corporation IBM IBM PC AT are registered trademarks of International Business Machines Corp Pentium is a trade mark of Intel Corporation Windows is a trademark and MS DOS Microsoft Windows are registered trademarks of Microsoft Corporation CompuServe is a registered trademark of CompuServe Incorporated All other trademarks mentioned herein are the property of their respective companies 1996 Microchip Technology Inc 1 DS30559A page 131 PIC16C64X amp PIC16C66X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product If you wish to provide your comments on organization clarity subject matter and
113. e week code facility code mask rev and assembly code For OTP marking beyond this certain price adders apply Please check with your Microchip Sales Office For QTP devices any special marking adders are included in QTP price DS30559A page 112 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 14 2 Package Marking Information 40 Lead PDIP Example MMMMMMMMMMMMMM PIC16C662 04 P XXXXXXXXXXXXXXXXXX AABBCDE D 9512CAA CA O MICROCHIP MICROCHIP 40 Lead CERDIP Windowed Example PIC16C662 JW AN XXXXXXXXXXX AN E ere AABBCDE TI AABBCDE 44 Lead PLCC Example MICROCHIP MICROCHIP MMMMMMMM PIC16C662 XXXXXXXXXX O 20 L XXXXXXXXXX AABBCDE AABBCDE 44 Lead TQFP Example PIC16C662 XXXXXXXXXX 20 TQ XXXXXXXXXX AABBCDE Legend MM MMicrochip part number information XX X Customer specific information AA Year code last 2 digits of calendar year BB Week code week of January 1 is week 01 C Facility code of the plant at which wafer is manufactured C Chandler Arizona U S A D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note ln the event the Microchip part number cannot be marked on one line it will be carried over to the next line thus limiti
114. e on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR all other BOR resets 1Fh CMCON C2OUT C1OUT CIS CM2 CM1 CMO 00 0000 00 0000 9Fh VRCON VREN VROE VRR VR3 VR2 VR1 VRO 000 0000 000 0000 OBh 8Bh INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000 0000 000u 0Ch PIR1 PsPIF CMIF 00 00 8Ch PIE1 PSPIEU 00 00 85h TRISA TRISAS TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 11 1111 11 1111 Note 1 These bits are reserved on the PIC16C641 642 always maintain these bits clear DS30559A page 52 Preliminary O 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 8 0 VOLTAGE REFERENCE The VRCON register shown in Figure 8 1 controls the MODULE operation of the Voltage Reference Module The block diagram is given in Figure 8 2 The Voltage Reference is a 16 tap resistor ladder network that provides a selectable voltage reference The resistor ladder is segmented to provide two ranges of VREF values and has a power down function to conserve power when the reference module is not being used FIGURE 8 1 REGISTER ADDRESS 9Fh RW 0 R W 0 R W 0 0 0 RWO _ R W 0 R W 0 VREN VROE VRR VR3 VR2 VR1 VRO R Readable bit bit7 bitO W Writable bit U Unimplemented bit read as 0 n Value at POR r
115. eliability of a system There are two parity bits for each word of Program Memory The parity bits are computed on alternating bits of the program word One computation is per formed using even parity the other using odd parity As a program executes the parity is verified The even parity bit is XOR d with the even bits in the program memory word The odd parity bit is negated and XOR d with the odd bits in the program memory word When an error is detected a reset is generated and the PER flag bit in the PCON register is set This indication can allow software to act on a failure However there is no indication of the program memory location of the failure of the Program Memory This flag can only be cleared in software or by a POR The parity array is user selectable during programming Bit7 of the configuration word located at address 2007h can be programmed read as 0 to disable parity checking If left unprogrammed read as 1 parity checking is enabled 9 4 6 TIME OUT SEQUENCE On power up the time out sequence is as follows First PWRT time out is invoked after POR has expired Then the OST is activated The total time out will vary based on oscillator configuration and PWRTE bit status For example in RC mode with the PWRTE bit set PWRT disabled there will be no time out at all Figure 9 9 Figure 9 10 Figure 9 11 depict time out sequences Since the time outs occur from the POR pulse if MCLR is kept low l
116. er can directly register with register f If d is 0 the address them result is stored in the W register If d is 1 the result is stored back in register Words 1 f Cycles 1 Words 1 Exame Cycles 1 To maintain upward compatibility with future PIC16CXX products do Example XORWF REG 1 not use this instruction Before Instruction REG OxAF W 0xB5 After Instruction REG Ox1A W OxB5 1996 Microchip Technology Inc DS30559A page 85 PIC16C64X amp PIC16C66X NOTES F DS30559A page 86 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 11 0 DEVELOPMENT SUPPORT 11 1 Development Tools The PIC16 17 microcontrollers are supported with a full range of hardware and software development tools PICMASTER PICMASTER CE Real Time In Circuit Emulator Low Cost PIC16C5X and PIC16CXX In Circuit Emulator PRO MATE II Universal Programmer PICSTART Plus Entry Level Prototype Programmer PICDEM 1 Low Cost Demonstration Board PICDEM 2 Low Cost Demonstration Board PICDEM 3 Low Cost Demonstration Board MPASM Assembler MPLAB SIM Software Simulator MPLAB C C Compiler Fuzzy logic development system fuzzyTECH MP 11 2 PICMASTER High Performance Universal In Circuit Emulator with MPLAB IDE The PICMASTER Universal In Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microco
117. es are identical to the OTP devices but with all EPROM locations and config uration options already programmed by the factory Certain code and prototype verification procedures apply before production shipments are available Please contact your Microchip Technology sales office for more details 2 4 Serialized Quick Turnaround Production SQTP v Devices Microchip offers a unique programming service where a few user defined locations in each device are programmed with different serial numbers The serial numbers may be random pseudo random sequential Serial programming allows each device to have a unique number which can serve as an entry code password or ID number 1996 Microchip Technology Inc Preliminary DS30559A page 7 1 ana PIC16C64X amp PIC16C66X NOTES e CELL LLELc2rr rrLC rrrropZ i inL L ELLCLLLIIULLTBQQ RIG ILLLLOCLULECCOOLLO LCIQOLLELEIELLLEECOLGEOLELULCLIHCLLELEZIESOGLG C ZQCIDILC TIZ G COLOLEL ILLELLBL LLUL AG COOLB CCI LLUIOCOILOOLOECIQUSSOCGCLLLULLLUA LLLLLLINLOCSCLSI BSB O SCLLU L LLLLLEELLLOXCGIOOLLLLZLEEOLL LU SSCOLOROG OUG DS30559A page 8 Preliminary O 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 3 0 ARCHITECTURAL OVERVIEW The high performance of the PIC16C64X 4 PIC16C66X devices can be attributed to a number of architectural features commonly found in RISC micro processors To begin with the 16 64 amp
118. es the stability of the oscillator but also increases the start up time These values are for design guidance only Since each resonator has its own characteristics the user should consult the resonator manufacturer for appropriate values of external components In XT LP or HS modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation Figure 9 2 PIC16CXXX oscillator design requires the use of a parallel cut crystal Use of a series cut crystal may give a frequency out of the Resonators used crystal manufacturers specifications When in XT LP or 455 kHz Panasonic EFO A455K04B 0 3 HS modes the device can have an external clock 2 0 MHz Murata CSA2 00MG 0 5 source to drive the OSC1 pin Figure 9 3 4 0 MHz Murata CSA4 00MG 0 5 8 0 MHz Murata Erie CSA8 00MT 0 5 FIGURE 9 2 CRYSTAL OPERATION 16 0 MHz Murata Erie 16 00 0 5 OR CERAMIC RESONATOR HS XT OR LP OSC All resonators used did not have built in capacitors CONFIGURATION TABLE 9 2 CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR PRELIMINARY Mode Freq OSC1 OSC2 SLEEP LP 32 kHz 68 100 pF 68 100 pF 200 2 15 30 pF 15 30 pF XT 100 kHz 68 150 pF 150 200 pF iid addu 2MHz 15 30pF 15 30pF See Table 9 1 or Table 9 2 for recommended val TMb Ise 19 ues of C1 and
119. eset bit 7 VREN VREF Enable 1 VREF circuit powered up 0 VREF circuit powered down no IDD drain bit 6 VROE VREF Output Enable 1 VREF is output on RA2 pin 0 VREF is disconnected from RA2 pin bit 5 VRR VREF Range selection 1 Low Range 0 High Range bit 4 Unimplemented Read as bit 3 0 VR3 VRO VREF value selection 0 VR3 VRO x 15 When VRR 1 Then VREF VR3 VRO0 24 VDD When VRR 0 Then VREF 1 4 VDD VR3 VRO 32 VDD FIGURE 8 2 VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 16 1 Analog Mux Note Ris defined in Table 12 3 1996 Microchip Technology Inc Preliminary DS30559A page 53 1 am AMA PIC16C64X amp PIC16C66X 8 1 Configuring the Voltage Reference The Voltage Reference Module can output 16 distinct voltage levels for each range The equations used to calculate the output of the Voltage Reference are as follows If VRR 1 Then VREF VR3 VRO 24 VDD If VRR 0 Then VREF VDD 1 4 VR3 VRO 32 VDD The settling time of the Voltage Reference must be considered when changing the VREF output Table 12 2 Example 8 1 shows an example of how to configure the Voltage Reference for an output voltage of 1 25V with VDD 5 0V EXAMPLE 8 1 VOLTAGE REFERENCE CONFIGURATION MOVLW 0x02 4 inputs muxed MOVWF CMCON to 2 comparators BSF STATUS RPO Selec
120. f 0 label INCFSZ 1 0 lt 1 lt 127 de 0 1 f 1 gt dest skip if result 0 None 00 1111 dfff ffff The contents of register are incre mented If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f If the result is 0 the next instruction which is already fetched is discarded is executed instead making it a two cycle instruction 1 1 2 HERE INCFSZ CNT 1 GOTO LOOP CONTINUE Before Instruction PC address HERE After Instruction CNT CNT 1 if CNT 0 PC address CONTINUE if CNT 0 PC address HERE 1 Inclusive OR Literal with W label IORLW k 0 lt k lt 255 W OR k gt W Z EL 1000 kkkk kkkk The contents of the W register is OR ed with the eight bit literal k The result is placed in the W register 1 1 IORLW 0x35 Before Instruction W 0x9A After Instruction W OxBF Z 1 DS30559A page 80 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X IORWF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example MOVLW Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Inclusive OR W with f label IORWF fd 0 lt 1 lt 127 de 0 1 W f gt dest 2 00 0100 dfff ffff Inclusive OR the W register with regis ter f If d is O the result i
121. flexibility to develop and debug code out side of the laboratory environment making it an excel lent multi project software development tool 11 12 C Compiler MPLAB C The MPLAB C Code Development System is a com plete C compiler and integrated development environ ment for Microchip s 16 17 family of microcontrollers The compiler provides powerful inte gration capabilities and ease of use not found with other compilers For easier source level debugging the compiler pro vides symbol information that is compatible with the MPLAB IDE memory display PICMASTER emulator software versions 1 13 and later 11 13 Fuzzy Logic Development System fuzzyTECH MP fuzzyTECH MP fuzzy logic development tool is avail able in two versions a low cost introductory version MP Explorer for designers to gain a comprehensive working knowledge of fuzzy logic system design and a full featured version fuzzyTECH MP edition for imple menting more complex systems Both versions include Microchip s fuzzyLABM demon stration board for hands on experience with fuzzy logic Systems implementation 11 14 MP DriveWay Application Code Generator MP DriveWay is an easy to use Windows based Appli cation Code Generator With MP DriveWay you can visually configure all the peripherals in a PIC16 17 device and with a click of the mouse generate all the initialization and many functional code modules in C language The output is fully c
122. fore the error in measuring the interval between two edges input 4Tosc max 2 External clock if no prescaler selected prescaler output otherwise 8 The arrows indicate the points in time where sampling occurs 1996 Microchip Technology Inc Preliminary DS30559A page 43 PIC16C64X amp PIC16C66X 6 3 Prescaler An 8 bit counter is available as a prescaler for the 0 module or as a postscaler for the Watchdog Timer WDT respectively Figure 6 6 For simplicity this counter is being referred to as prescaler through out this data sheet Note that the prescaler may be used by either the TimerO module the Watchdog Timer but not both Thus a prescaler assignment for the 0 module means that there is no prescaler for the Watchdog Timer and vice versa The PSA 52 50 bits OPTION lt 3 0 gt determine the prescaler assignment and prescale ratio When assigned to the 0 module all instructions writing to the TMRO register e g CLRF 1 MOVWF 1 BSF 1 x will clear the prescaler count When assigned to Watchdog Timer a CLRWDT instruction will clear the prescaler count along with the Watchdog Timer The prescaler is not readable or writable FIGURE 6 6 BLOCK DIAGRAM OF THE TIMERO WDT PRESCALER CLKOUT Fosc 4 Data Bus RA4 TOCKI pin m TMRO reg n Set flag bit TOIF on Overflow
123. he power down current in SLEEP mode does not depend on the oscillator type Power down current is measured with the part in SLEEP mode with all pins in hi impedance state and tied to VDD or Vss For RC osc configuration current through Rext is not included The current through the resistor can be estimated by the formula Ir VDD 2Rext mA with Rext in The A current is the additional current consumed when this peripheral is enabled This current should be added to the base IDD or IPD measurement DS30559A page 92 Preliminary O 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 12 2 DC Characteristics PIC16LC641 642 661 662 04 Commercial Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt TA lt 85 C for industrial and 0 C lt TA lt 70 C commercial Param Sym Characteristic Min Max Units Conditions No 0001 Supply Voltage 3 0 6 0 V RC and LP osc configuration D002 VDR RAM Data Retention 1 5 V Device in SLEEP mode Voltage 1 D003 VPOR start voltage to Vss V See section Pow amp r n Reset for ensure internal Power on details Reset signal 0004 5 VDD rise rate to ensure internal 0 05 Power on Reset signal 0005 VBOR Brown out Reset Voltage 3 7 4 0 D010A Module Differential Current 9 0015 AlBOR Brown o
124. hite goods controllers etc PIC16CXXX devices have special features to reduce external components thus reducing cost enhancing system reliability and reducing power consumption There are four oscillator options of which the single pin RC oscillator provides a low cost solution the LP oscillator minimizes power consumption XT is a standard crystal and the HS is for High Speed crystals The SLEEP power down mode offers power saving The user can wake up the chip from SLEEP through several external and internal interrupts and resets A highly reliable Watchdog Timer WDT with its own on chip RC oscillator provides protection against soft ware lock up A UV erasable CERDIP packaged version is ideal for code development while the cost effective One Time Programmable OTP version is suitable for production in any volume The PIC16CXXX series fit perfectly in applications ranging from battery chargers to low power remote sensors EPROM technology makes customization of application programs detection levels pulse generation timers etc extremely fast and convenient The small footprint packages make this microcontroller series perfect for all applications with space limitations Low cost low power high performance ease of use and I O flexibility make the PIC16C64X amp PIC16C66X very versatile 1 1 Family and Upward Compatibility Those users familiar with the PIC16C5X family of microcontrollers will realize th
125. hnology Inc PIC16C64X amp PIC16C66X PIC16C64X amp PIC16C66X PRODUCT IDENTIFICATION SYSTEM PART NO XX X XX XXX EH Pattern Package Temperature Range Frequency Range Device Special Requirements SOIC PLCC PDIP TQFP Skinny DIP Windowed DIP 0 C to 70 C 40 C to 85 C 40 C to 125 C 4 MHz 10 2 20 2 Please contact your local sales office for exact ordering procedures Examples a PIC16C662 04 P Commercial PDIP Package 4 MHz normal limits 16 662 041 5 Industrial SOIC package 4 MHz normal VDD limits PIC16C662 04E P Automotive Temp PDIP package 4 MHz normal VDD limits JW devices are UV erasable and can be programmed to any device configuration JW devices meet the electrical requirements of each oscillator type including LC devices Sales and Support Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds To determine if an errata sheet exists for a particular device please contact one of the following 1 Your local Microchip sales office see below 2 The Microchip Corporate Literature Center U S FAX 602 786 7277 3 The Microchip s Bulletin Board via your local CompuServe number CompuServe membership NOT required Please specify which device revision of silicon and Data Sheet include Literature you are usi
126. ia two pins Pin Diagrams PDIP SOIC Windowed CERDIP MCLR VPP RAO ANO RA1 AN1 RA2 AN2 VREF lt gt RA3 AN3 gt RA4 TOCKI lt RAS Vss gt OSC1 CLKIN OSC2 CLKOUT RCO gt RC7 lt lt gt RC6 RC2 gt 5 O0 lt gt RC4 4 887 lt 886 lt 885 lt 884 RB3 4 RB2 RB1 4 RBO INT 4 VDD 4 Vss O1 X 999191d PDIP Windowed CERDIP 40 _ lt RB7 lt gt RB6 lt gt RB5 lt RB4 RB3 lt RB2 1 5 RB1 lt RBO INT VoD 4 Vss lt RD7 PSP7 lt RD6 PSP6 OSC1 CLKIN RD5 PSP5 OSC2 CLKOUT lt lt RD4 PSP4 RCO RC7 RCI gt lt RC6 RC2 RC5 RC4 RDO PSPO lt gt lt RD3 PSP3 RD1 PSP1 4 RD2 PSP2 MCLR VPP gt RAO ANO RA1 AN1 lt gt RA2 AN2 VREF RA3 AN3 RA4 TOCKI lt gt RAS REO RD lt RE1 WR gt RE2 CS gt gt Vss gt O1
127. id 8z 90 Oal IdS some s ejoudueg 1996 Microchip Technology Inc DS30559A page 120 pue 94H 909 eues esn sadap 2919214 IIV Aujiqedeo jueuno UBIU pue 19e104d epoo Aaw DopuoreM ejqejoejes 19S9H UO IBMOJ AJEJ 7 L 9 LOld IV DS30559A page 121 PIC16C64X amp PIC16C66X PIC16C7X Family of Devices E 5 d401 dJOIN 001d Ud py dig uld or Javsn 5 COWL OHNL V 299191d 0914 Ud py did 1uvsn 5 V299L9ld 9105 uld gz 14vsn Oal IdS COWL OHNL VEZ99191d 9105 dids uld gz 14vsn Dal ldS CHL OHNL 6729014 40585 2105 dlas uld gz 4 5 CHL 22291014 dOSS uld 0z OIOS uld g 1 14091014 2105 did uld g 1 7291214 dOSS 4 02 OIOS uld g SeJnjee4 0 5924 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X PIC16C8X Family of Devices E 6 9Seu JO 10 BDO INO 1224000 SION pue 909 penas asn XZIILOId Ayjigedeo UBIU pue joejoud
128. ig An input change on any bit of PORTB lt 7 4 gt sets flag bit gered either rising if bit INTEDG OPTION lt 6 gt is set RBIF lt 0 gt The interrupt can be enabled dis or falling if bit INTEDG is clear When a valid edge abled by setting clearing enable bit RBIE appears on the RBO INT pin flag bit INTF INTCON lt 4 gt For operation of PORTB Section 5 2 INTCON lt 1 gt is set This interrupt be enabled dis abled by setting clearing enable bit INTE INTCON lt 4 gt The INTF bit must be cleared in soft ware in the interrupt service routine before re enabling this interrupt The RBO INT interrupt can wake up the processor from SLEEP if bit INTE was set prior to going into SLEEP The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake up See Section 9 8 for details on SLEEP and Figure 9 19 for timing of wake up from SLEEP through RBO INT interrupt 9 5 4 COMPARATOR INTERRUPT See Section 7 6 for complete description of the com parator interrupt 9 5 2 TMRO INTERRUPT An overflow FFh 00h in the TMRO register will set the TOIF INTCON lt 2 gt bit The interrupt can be enabled disabled by setting clearing TOIE lt 5 gt bit For operation of the 0 module see Section 6 0 FIGURE 9 16 RBO INT PIN INTERRUPT TIMING Q1 AZ 031 Q4 Q1 021 031 AA Q1 021 Q4 021 AZ 04 A1 AZ Q3 Q4 OSC1 Xu ube
129. il see Figure 4 3 and Figure 4 4 Note 1 Bits RP1 and IRP are reserved always maintain these bits clear DS30559A page 28 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 5 0 1 0 PORTS The PIC16C641 and PIC16C642 have three ports PORTA PORTB and PORTC PIC16C661 and PIC16C662 devices have five ports PORTA through PORTE Some pins for these ports multiplexed with alternate functions for the peripheral features on the device In general when peripheral is enabled that pin may not be used as a general purpose pin 5 1 PORTA and TRISA Registers PORTA is a 6 bit wide latch RA4 is a Schmitt Trigger input and an open drain output Pin 4 is multiplexed with the TOCKI clock input All other RA port pins have Schmitt Trigger input levels and full CMOS output driv ers All pins have data direction bits TRIS registers which can configure these pins as input or output Setting a bit in the TRISA register puts the correspond ing output driver in a hi impedance mode Clearing a bit in the TRISA register puts the contents of the output latch on the selected pin Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch write operations are read modify write operations Therefore a write to a port implies that the port pins are read this value is modified and then written to the port data latch The PORTA pins are multi
130. input when configured as the external interrupt 2 This buffer is a Schmitt Trigger input when used in serial programming mode TABLE 5 4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit2 Bit 1 Bit 0 POR all other BOR resets 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO xxxx uuuu uuuu 86h TRISB TRISB7 TRISB6 TRISB5 5 4 TRISB3 TRISB2 TRISB1 TRISBO 1111 1111 1111 1111 81h OPTION INTEDG TOCS TOSE PSA PS2 PS1 PSO 1111 1111 1111 1111 Legend x unknown u unchanged shaded cells are not used by PORTB O 1996 Microchip Technology Inc Preliminary DS30559A page 33 PIC16C64X amp PIC16C66X FIGURE 5 7 PORTC BLOCK DIAGRAM IN 1 0 PORT MODE 5 3 PORTC and TRISC Registers PORTO is an 8 bit bi directional port Each pin is indi vidually configurable as an input or output through the TRISC register PORTC pins have Schmitt Trigger 2 Dx input buffers EXAMPLE 5 3 INITIALIZING PORTC Data Latch CLRF PORTC Initialize PORTC by Clearing output M data latches BSF STATUS RPO Select Bank 1 Schmitt MOVLW OxCF Value used to WA V initialize data TRIS Latch buffer direction MOVWF TRISC Set RC 3 0 as inputs RC lt 5 4 gt as outputs RD TRIS RC lt 7 6 gt as
131. ion PC Address THERE TOS Address HERE 1 CLRF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example CLRW Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Clear f abel CLRF f 0 lt 1 lt 127 00h f 12 2 00 0001 lfff ffff The contents of register are cleared and the Z bit is set 1 1 CLRF FLAG REG Before Instruction FLAG REG 0 5 After Instruction FLAG REG 0x00 2 1 Clear W label CLRW None 00h gt W 12 Z 00 0001 0000 0011 W register is cleared Zero bit Z is set 1 1 CLRW Before Instruction W After Instruction W 0x00 Z 1 DS30559A page 78 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X CLRWDT Syntax Operands Operation Status Affected Encoding Description Words Cycles Example COMF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Clear Watchdog Timer label CLRWDT None 00h gt WDT 0 gt WDT prescaler 1 gt 1 gt PD TO PD 00 0000 0110 0100 CLRWDT instruction resets the Watch dog Timer It also resets the prescaler of the WDT Status bits TO and PD are set 1 1 CLRWDT Before Instruction WDT counter 2 After Instruction WDT counter 0x00 WDT prescaler 0 TO d P
132. it 2 Bit 1 Bit 0 POR other resets BOR 01h TMRO TimerO module s register XXXX XXXX uuuu uuuu OBh 8Bh INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u 81h OPTION RBPU INTEDG TOCS TOSE PSA PS2 PS1 PSO 1111 1111 1111 1111 85h TRISA TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 11 1111 11 1111 Legend x unknown u unchanged unimplemented locations read as 0 Shaded cells are not used by 1996 Microchip Technology Inc Preliminary DS30559A page 45 PIC16C64X amp PIC16C66X NOTES T DS30559A page 46 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 7 0 COMPARATOR MODULE The CMCON register shown in Figure 7 1 controls the comparator input and output multiplexers A block The comparator module contains two analog diagram of the comparator is shown in Figure 7 2 comparators The inputs to the comparators are multiplexed with pins RAO through RA4 The on chip Voltage Reference Section 8 0 can also be an input to the comparators FIGURE 7 1 CMCON REGISTER ADDRESS 1Fh R 0 R 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 C2OUT CIOUT CIS CM2 CM1 CMO R Readable bit bit7 bitO W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 C2OUT Comparator 2 output 1 C2 Vin gt C2 VN 0 C2 lt C2 VN bit 6 C1OUT Comparator 1 output 1 gt C1 Vine 0 C1 l
133. le in the 3rd quarter of 1996 11 9 MPLAB Integrated Development Environment Software The MPLAB IDE Software brings an ease of software development previously unseen in the 8 bit microcon troller market MPLAB is a windows based application which contains Afull featured editor Three operating modes editor emulator simulator A project manager Customizable tool bar and key mapping A status bar with project information Extensive on line help MPLAB allows you to Edit your source files either assembly or One touch assemble or compile and download to PIC16 17 tools automatically updates all project information Debug using source files absolute listing file Transfer data dynamically via DDE soon to be replaced by OLE Run up to four emulators on the same PC The ability to use MPLAB with Microchip s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools 11 10 Assembler MPASM The MPASM Universal Macro Assembler is a PC hosted symbolic assembler It supports all microcon troller series including the PIC12C5XX PIC14000 PIC16C5X PIC16CXX and PIC17CXX families MPASM offers full featured Macro capabilities condi tional assembly and several source and listing formats It generates various object code formats to support Microchip s development t
134. loaded with the inter rupt vector 0004h after execution of PC 1 DS30559A page 62 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X TABLE 9 6 INITIALIZATION CONDITION FOR REGISTERS MCLR Reset during Wake up from SLEEP Power on Reset 5 Register Address Brown out Reset rore operation through 9 Parity Error Reset SLEEP or interrupt WDT Reset WDT time out W e uuuu uuuu uuuu uuuu XXXX XXXX uuuu uuuu uuuu uuuu 0000 0000 0000 0000 10 STATUS 000q guuu uuug guuu FSR uuuu uuuu uuuu uuuu PORTA xu 0000 uu uuuu PORTB uuuu uuuu uuuu uuuu PORTC uuuu uuuu uuuu uuuu PORTD uuuu uuuu uuuu uuuu PORTE uuu uuu CMCON 00 0000 uu uuuu PCLATH 0 0000 u uuuu INTCON 0000 000u o rov n PIR1 00 PENES 1 OPTION 1111 11 uuuu uuuu 11 11 uu uuuu 1111 11 uuuu uuuu 1111 11 uuuu uuuu TRISD 4 1111 11 uuuu uuuu TRISE 0000 1 uuuu uuu PIE1 00 UE EST PCON 8Eh u ggg u uuu u uuu VRCON 9Fh 000 0000 000 0000 uuu uuuu Legend u unchanged x unknown unimplemented bit reads as 0 value depends on condition Note 1 One or more bits in INTCON and or PIR1 will be affected to cause wake up 2 When the wake up is due to an interrupt and the GIE bit is set the PC is loaded with the interrupt vector 0004h 3 See
135. m 200200 LOOZY 400900MS 200Z00MS 000 191Id L0LZ9LIA3 200200 GLOZOLWA GO0900MS 200 00 6 60S 806221214 Wy 19G 100 J0jeJouot jueuiuoJIAu3 19G diu20421A yno4i2 uJ yn2J12 UJ 91601 zzn4 epo9 1S09 M07 1509 M07 1S09 M07 39 HALSVWOId suoneotjddy Snid LYVLSOld 911 LHVLSOId wALVIN 01939 IOHALSVNOId dN HDAL ZZNY emeaug dn 9 x yONPOld 1996 Microchip Technology Inc Iminary Prel DS30559A page 90 PIC16C64X amp PIC16C66X 12 0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings 1 Ambient Temperature under bias Storage Temperature Voltage on any pin with respect to Vss except and MCLR Voltage on VDD with respect to 55 Voltage on MCLR with respect to Vss Note 2 Total power Dissipation Note 1 Maximum Current out of VSS pin Maximum Current into VDD pin Input Clamp Current lik lt 0 or Vi VDD Output Clamp Current IOK Vo 0 or Vo VDD sin Maximum Output Current sunk by any I O pin Maximum Output Current sourced by any I O pin Maximum current sunk by PORTA PORTB and PORTE combined Note 2 Maximum current sunk by PORTC and PORTD combined Note 2 Maximum
136. n tes 24 Pin Compatible Devices 125 Pin Functions RD7 PSP7 RDO PSPO 14 REO RD iiio iter 14 39 exea heri RS 14 39 RE2 CS esee ee etre 14 39 PIR1 Register eene 25 Port RB Interr pt aite pt 67 PORTA i nete enin SR 29 PORTE 32 Register sees 34 PORTD Register u senes 35 DS30559A page 128 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X PORTE Register uere UE UR 36 Ports Power Control Status Register PCON 61 Power down Mode SLEEP 70 Power on Reset POR 60 Power up Timer PWRT eee 60 Prescaler eee nent 44 PRO MATE Universal Programmer 87 Program Memory Organization 17 PSPMOBDBE biE 5 2 nosmet 35 36 Q Quick Turnaround Production ATP Devices 7 R 2 pr tt tiec teg att boe Reset occident e ee b t EP RETFIE Instruction 22 RETLW Instruction 2 22 RETURN Instruction RLF Instruction 6 25 ter trece rci S Serialized Quick Turnaround Production SQTP Devices SERGE SFR As Source Desti
137. nation 74 SLEEP Instruction ia ene nere 83 Software Simulator MPLAB SIM 89 Special Features of the CPU 55 Special Function Registers STATUS Register SUBLW Instruction SUBWE Instruction SWAPF Instruction sss Switching Prescalers eee T Timer Modules 0 Block Diagram Counter Mode External Clock Interrupt ice tege ces Prescaler n in DECNHOM oos nn Timer Mode Timing Diagram ve TMRO register Timing Diagrams and Specifications TMRO Interrupt TRIS Instruction TRISA ih r RUD 29 TRISB RENNES aie 32 TRISG R edgislel I v d neska dd ine 34 TRISD Register eter pe hb Pte 35 TRISE R6gISIOr oie he erede 36 V Voltage Reference Module 53 VRCON Register 2 53 W Watchdog Timer WDT 69 X XORLW Instruction sse 85 XORWF Instruction sse 85 LIST OF EXAMPLES Example 3 1 Instruction Pipeline Flow Example 4 1 Indirect Addressing Example 5 1 Initializing PORTA Example 5 2 Initializing Example 5 3 Read Modify Wri
138. ng For latest version information and upgrade kits for Microchip Development Tools please call 1 800 755 2345 or 1 602 786 7302 1996 Microchip Technology Inc DS30559A page 135 MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office Microchip Technology Inc 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 480 786 7200 Fax 480 786 7277 Technical Support 480 786 7627 Web Address http www microchip com Atlanta Microchip Technology Inc 500 Sugar Mill Road Suite 200B Atlanta 30350 Tel 770 640 0034 Fax 770 640 0307 Boston Microchip Technology Inc 5 Mount Royal Avenue Marlborough MA 01752 Tel 508 480 9990 Fax 508 480 8575 Chicago Microchip Technology Inc 333 Pierce Road Suite 180 Itasca IL 60143 Tel 630 285 0071 Fax 630 285 0075 Dallas Microchip Technology Inc 4570 Westgrove Drive Suite 160 Addison TX 75248 Tel 972 818 7423 Fax 972 818 2924 Dayton Microchip Technology Inc Two Prestige Place Suite 150 Miamisburg OH 45342 Tel 937 291 1654 Fax 937 291 9175 Detroit Microchip Technology Inc Tri Atria Office Building 32255 Northwestern Highway Suite 190 Farmington Hills MI 48334 Tel 248 538 2250 Fax 248 538 2260 Los Angeles Microchip Technology Inc 18201 Von Karman Suite 1090 Irvine CA 92612 Tel 949 263 1888 Fax 949 263 1338 New York Microchip Technology Inc 150 Motor Parkway Suite 202 Hauppauge NY 11788 Tel
139. ng the number of available characters for customer specific information Standard OTP marking consists of Microchip part number year code week code facility code mask rev and assembly code For OTP marking beyond this certain price adders apply Please check with your Microchip Sales Office For QTP devices any special marking adders are included in QTP price 1996 Microchip Technology Inc Preliminary DS30559A page 113 PIC16C64X amp PIC16C66X NOTES F R _ _ _ _ _ _ _ _ _ _ _ _ _ DS30559A page 114 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X APPENDIX A ENHANCEMENTS The following are the list of enhancements over the APPENDIX B COMPATIBILITY To convert code written for 16 5 to PIC16CXX PIC16C5X microcontroller family 1 10 11 12 13 14 15 16 17 18 19 1996 Microchip Technology Inc Instruction word length is increased to 14 bits This allows larger page sizes both in program memory 4K now as opposed to 512 before and register file up to 176 bytes now versus 32 bytes before high latch register PCLATH is added to handle program memory paging PA2 PAT PAO bits are removed from STATUS register Data memory paging is slightly redefined STATUS register is modified Four new instructions have been added RETURN RETFI
140. nstruction PC address HERE After Instruction CNT CNT 1 if CNT 0 PC address CONTINUE if CNT 0 PC address HERE 1 1996 Microchip Technology lnc DS30559A page 79 PIC16C64X amp PIC16C66X GOTO Syntax Operands Operation Status Affected Encoding Description Words Cycles Example INCF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Unconditional Branch label GOTO k 0 lt k lt 2047 k lt 10 0 gt PCLATH lt 4 3 gt gt PC lt 12 11 gt None 10 lkkk kkkk kkkk GOTO is an unconditional branch The eleven bit immediate value is loaded into PC bits lt 10 0 gt The upper bits of PC are loaded from PCLATH lt 4 3 gt GOTO is a two cycle instruction 1 2 GOTO THERE After Instruction PC Address THERE Increment f label INCF 0 lt 1 lt 127 de 0 1 f 1 dest Z 00 1010 ffff The contents of register f are incre mented If d is O the result is placed in the W register If d is 1 the result is placed back in register f 1 1 INCF CNT 1 Before Instruction CNT OxFF Z 0 After Instruction CNT 0x00 Z 1 INCFSZ Syntax Operands Operation Status Affected Encoding Description Words Cycles Example IORLW Syntax Operands Operation Status Affected Encoding Description Words Cycles Increment f Skip i
141. ntrollers in the PIC12C5XX PIC14000 PIC16C5X PIC16CXX and PIC17CXX families PICMASTER is supplied with the MPLAB Integrated Development Environment IDE which allows editing make and download and source debugging from a single environment Interchangeable target probes allow the system to be easily reconfigured for emulation of different proces sors The universal architecture of the PICMASTER allows expansion to support all new Microchip micro controllers The PICMASTER Emulator System has been designed as a real time emulation system with advanced fea tures that are generally found on more expensive devel opment tools The PC compatible 386 and higher machine platform and Microsoft Windows 3 x environ ment were chosen to best make these features avail able to you the end user A CE compliant version of PICMASTER is available for European Union EU countries 11 3 ICEPIC Low cost PIC16CXX In Circuit Emulator ICEPIC is a low cost in circuit emulator solution for the Microchip PIC16C5X and PIC16CXX families of 8 bit OTP microcontrollers ICEPIC is designed to operate on PC compatible machines ranging from 286 through Pentium based machines under Windows 3 x environment ICEPIC features real time non intrusive emulation 11 4 PRO MATE Il Universal Programmer The PRO II Universal Programmer is a full fea tured programmer capable of operating in stand alone mode as well as PC hosted mode
142. nvalid Hi impedance V Valid L Low Z Hi Impedanc gt FIGURE 12 1 LOAD CONDITIONS N Load condition 1 d 1996 Microchip Technology Inc Preliminary DS30559A page 97 PIC16C64X amp PIC16C66X 12 5 Timing Diagrams and Specifications FIGURE 12 2 EXTERNAL CLOCK TIMING CLKOUT TABLE 12 4 EXTERNAL CLOCK TIMING REQUIREMENTS Param No Characteristic External CLKIN Frequency HC osc mode VDD 5 0V XT osc mode HS osc mode LP osc mode XT and RC osc mode HS osc mode LP osc mode RC osc mode XT osc mode HS osc mode LP osc mode Toy Fosc 4 XT osc mode LP osc mode HS osc mode XT osc mode LP osc mode HS osc mode Oscillator Frequency 1 External CLKIN Period Oscillator Period 9 4 andre got tested Note 1 Instr ction cycle period TCY equals four times the input oscillator time base period All specified values are based characterization data for that particular oscillator type under standard operating conditions with the device executing code Exceeding these specified limits may result in an unstable oscillator operation and or higher than expected current consumption All devices are tested to operate at min values with an external clock applied to the OSCI pin When an external clock input is used the Max cycle time limit is DC no clock for all devices
143. oblem CompuServe service allow multiple users various baud rates depending on the local point of access The following connect procedure applies in most loca tions 1 Set your modem to 8 bit No parity and One stop 8N1 This is not the normal CompuServe setting which is 7E1 2 Dial your local CompuServe access number 3 Depress the Enter key and a garbage string will appear because CompuServe is expecting a 7E1 setting 4 Type depress the Enter key and Host Name will appear 5 Type MCHIPBBS depress the Enter key and you will be connected to the Microchip BBS In the United States to find the CompuServe phone number closest to you set your modem to 7E1 and dial 800 848 4480 for 300 2400 baud or 800 331 7166 for 9600 14400 baud connection After the system responds with Host Name type NETWORK depress the Enter key and follow CompuServe s directions For voice information or calling from overseas you may call 614 723 1550 for your local CompuServe number Microchip regularly uses the Microchip BBS to distribute technical information application notes source code errata sheets bug reports and interim patches for Microchip systems software products For each SIG a moderator monitors scans and approves or disap proves files submitted to the SIG No executable files are accepted from the user community in general to limit the spread of computer viruses Systems Information an
144. of real time applications The PIC16C64X amp PIC16C66X families have a host of such features intended to max imize system reliability minimize cost through elimina tion of external components provide power saving operating modes and offer code protection These are 1 Oscillator selection 2 Resets Power on Reset POR Power up Timer PWRT Oscillator Start up Timer OST Brown out Reset BOR Parity Error Reset PER Interrupts Watchdog Timer WDT SLEEP Code protection ID Locations In circuit serial programming 04001 The PIC16C64X amp PIC16C66X has a Watchdog Timer which is enabled by a configuration bit WDTE It runs off its own RC oscillator for added reliability There are two timers that offer necessary delays on power up One is the Oscillator Start up Timer OST intended to keep the chip in reset until the crystal oscillator is sta ble The other is the Power up Timer PWRT which provides a fixed delay of 72 ms nominal on power up only designed to keep the part in reset while the power supply stabilizes Circuitry has been provided for checking program memory parity with a reset when an error is indicated There is also circuitry to reset the device if a brown out occurs which provides at least a 72 ms reset With these three functions on chip most applications need no external reset circuitry SLEEP mode is designed to offer a very low current power down mode The user can wake up from S
145. ompatible with Micro chips MPLAB C C compiler The code produced is highly modular and allows easy integration of your own code MP DriveWay is intelligent enough to maintain your code through subsequent code generation 11 15 SEEVAL Evaluation and Programming System The SEEVAL SEEPROM Designer s Kit supports all Microchip 2 wire and 3 wire Serial EEPROMs The kit includes everything necessary to read write erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials The Total Endurance Disk is included to aid in trade off analysis and reliability calculations The total kit can significantly reduce time to market and result in an optimized system 11 16 TrueGauge Intelligent Battery Management The TrueGauge development tool supports system development with the MTA11200B TrueGauge Intelli gent Battery Management IC System design verifica tion can be accomplished before hardware prototypes are built User interface is graphically oriented and measured data can be saved in a file for exporting to Microsoft Excel 11 17 KEELoa Evaluation and Programming Tools KEELOO evaluation and programming tools support Microchips HCS Secure Data Products The HCS eval uation kit includes an LCD display to show changing codes a decoder to decode transmissions and a pro gramming interface to program test transmitters 1996 Microchip Technology Inc Preliminary DS3055
146. on is carried out on the Example 5 4 shows the effect of two sequential read modify write instructions on an I O port A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin wired or wired and The resulting high output currents may damage same port The sequence of instructions should be such to allow the pin voltage to stabilize load dependent before the next instruction which causes that file to be read into the CPU is executed Otherwise the previous state of that pin may be read into the CPU rather than the new state When in doubt it is better to separate these instructions with an NOP or another instruction not accessing this I O port the chip FIGURE 5 11 SUCCESSIVE 1 0 OPERATION Q1 02 031 04 01 021 Q3 04 Q1 021 03104 01 02 Q3 04 Note __ 013 X PC 2 X PC 3 This example shows a write to PORTB followed by a read from PORTB Note that data setup time 0 25TCY TPD Instruction 1 fetched MOVWF PORTB MOVF PORTB W write to i PORTB NOP RB7 RBO X 5 where TCY instruction cycle pon pin TPD propagation delay sampled here Therefore at higher clock frequencies a write followed by a read may be problematic Instruction executed f MOVWF PORTB MOVF PORTB W write to 1 PORTB DS30559A page 38
147. ong enough the time outs will expire Then bringing MCLR high will begin execution immediately Figure 9 10 This is useful for testing purposes or to synchronize more than one device operating in parallel Table 9 5 shows the reset conditions for some special registers while Table 9 6 shows the reset conditions for all the registers 9 4 7 POWER CONTROL STATUS REGISTER PCON The power control status register PCON address has four bits See Figure 4 10 for register Bito is BOR Brown out Reset BOR is unknown on a Power on reset It must initially be set by the user and checked on subsequent resets to see if BOR 0 indicating that a Brown out Reset has occurred The BOR status bit is a don t care bit and is not necessar ily predictable if the brown out circuit is disabled by clearing the BODEN bit in the Configuration word Bit is POR Power on Reset It is cleared on a Power on Reset and is unaffected otherwise The user set this bit following a Power on Reset On subsequent resets if POR is 0 it will indicate that a Power on Reset must have occurred Bit2 is PER Parity Error Reset It is cleared on a Parity Error Reset and must be set by user software It will also be set on a Power on Reset Bit7 is MPEEN Memory Parity Error Enable This bit reflects the status of the MPEEN bit in configuration word It is unaffected by any reset or interrupt TABLE 9 3 TIME OUT IN VAR
148. ools as well as third party programmers DS30559A page 88 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X MPASM allows full symbolic debugging from the Microchip Universal Emulator System PICMASTER MPASM has the following features to assist in develop ing software for specific use applications Provides translation of Assembler source code to object code for all Microchip microcontrollers Macro assembly capability Produces all the files Object Listing Symbol and special required for symbolic debug with Microchip s emulator systems Supports Hex default Decimal and Octal source and listing formats MPASM provides a rich directive language to support programming of the PIC16 17 Directives are helpful in making the development of your assemble source code shorter and more maintainable 11 11 Software Simulator MPLAB SIM The MPLAB SIM Software Simulator allows code development in a PC host environment It allows the user to simulate the PIC16 17 series microcontrollers on an instruction level On any given instruction the user may examine or modify any of the data areas or provide external stimulus to any of the pins The input output radix can be set by the user and the execution can be performed in single step execute until break or in a trace mode MPLAB SIM fully supports symbolic debugging using MPLAB C and MPASM The Software Simulator offers the low cost
149. ormation about the status of the output bits as read from lt 7 6 gt to determine the actual change that has occurred The CMIF bit PIR1 lt 6 gt is the comparator interrupt flag and must be cleared in user software To enable the Comparator interrupt the following bits must be set PIE1 lt 6 gt PEIE INTCON lt 6 gt GIE INTCON lt 7 gt The user in the interrupt service routine can clear the interrupt in the following manner a Any read or write of CMCON This will end the mismatch condition b Clear flag bit CMIF A mismatch condition will continue to set flag bit CMIF Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared 7 7 Comparator Operation During SLEEP When a comparator is active and the device is placed in SLEEP mode the comparator remains active and the interrupt is functional if enabled This interrupt will wake up the device from SLEEP mode when enabled While the comparator is powered up higher sleep currents than shown in the power down current specification will occur Each comparator that is operational will consume additional current as shown in the comparator specifications To minimize power consumption while in SLEEP mode turn off the FIGURE 7 5 ANALOG INPUT MODEL Von Avr 0 6V comparators CM2 CMO 111 before entering sleep If the device wakes up from sleep the contents of the CMCON register are not affected
150. otection esses 71 BCF Instruction 77 Instruction 79 Bit Manipulation eee 74 Comparator Configuration 48 Block 30 Comparator Interrupt sess 51 Comparator Analog Input Mode 51 Comparator Module sss 47 Comparator I O Operating Modes 48 Comparator Operation 49 Comparator Output 50 Comparator Reference 49 Crystal Operation 57 Configuration Bits u sse 56 External Brown out Protection 1 65 Configuring the Voltage Reference 54 External Brown out Protection 2 65 D External Clock Input Operation 57 External Parallel Cystal Oscillator 58 Data Memory Organization we 18 External Power on Reset Circuit 22222222 65 DECF Instruction sssssssseee 79 External Series Crystal Oscillator 58 DECFSZ Instruction s 79 In circuit Serial Programming 71 Development Support eee 87 Interrupt LOg C ccm cit 66 Development Tools
151. pendent Comparators CM2 CM0 100 RAO ANO Vi RA3 AN3 A RA1 AN1 RA2 AN2 A Four Inputs Multiplexed to Two Comparators CM2 CM0 010 RAO ANO RAS AN3 RA1 AN1 RA2 AN2 C2 C2OUT 314 From VREF Module Two Common Reference Comparators CM2 CMO 011 RAO ANO Vi RA3 AN3 P RA1 AN1 RA2 AN2 A Two Common Reference Comparators with Outputs CM2 CMO 110 RAO ANO VX RAZ AN3 D Vu RA1 AN1 Vi RA2 AN2 A Vint RA4 Open Drain One Independent Comparator 2 0 101 VIN RAO ANO RA3 AN3 PD pul Off Read 0 RA1 AN1 RA2 AN2 A Analog Input port reads zeros always D Digital Input CIS CMCON lt 3 gt is the Comparator Input Switch DS30559A page 48 Preliminary Three Inputs Multiplexed to Two Comparators CM2 CMO 001 A RAOJANO Gis 0 RA3 AN3 Ao CIS 1 VIN RA1 AN1 RA2 AN2 A 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X The code example in Example 7 1 depicts the steps required to configure the comparator module RA3 and RA4 are configured as digital outputs RAO and RA1 are configured as the V inputs and RA2 as the V input to both comparators EXAMPLE 7 1 INITIALIZING THE COMPARATOR MODULE FLAG REG EQU 0x20 CLRF FLAG REG Init Flag Register init PORTA ANDLW
152. plemented Note 1 Other non power up resets include Reset and Watchdog Timer Reset during normal operation 2 The IRP and bits are reserved always maintain these bits clear 3 The PORTD PORTE TRISD and TRISE registers are not implemented on the PIC16C641 642 4 Bits PSPIE and PSPIF are reserved on the PIC16C641 642 always maintain these bits clear DS30559A page 20 Preliminary O 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 4 2 2 1 STATUS REGISTER The STATUS register shown in Figure 4 5 contains the arithmetic status of the ALU the RESET status and the bank select bits for data memory The STATUS register can be the destination for any instruction like any other register If the STATUS register is the destination for an instruction that affects the Z DC or C bits then the write to these three bits is disabled These bits are set or cleared according to the device logic Furthermore the TO and PD bits are not writable Therefore the result of an instruction with the STATUS register as destination may be different than intended For example CLRF STATUS Will clear the upper three bits and set the Z bit This leaves the STATUS register as O00uuluu where u unchanged It is recommended therefore that only BSF SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect any status bit For other instructions not affecting
153. plemented read as 0 Shaded cells are not used by PORTD O 1996 Microchip Technology Inc Preliminary DS30559A page 35 PIC16C64X amp PIC16C66X 5 5 PORTE and TRISE Register Figure 5 9 shows the TRISE register which also con 16 661 and PIC16C662 only trols the parallel slave port operation PORTE has three pins REO RD RE1 WR and RE2 CS which are individually configurable as inputs or outputs These pins have Schmitt Trigger input buffers PORTE becomes control inputs for the micropro cessor port when bit PSPMODE TRISE lt 4 gt is set In this mode the user must make sure that the TRISE lt 2 0 gt bits are set pins are configured as digital inputs In this mode the input buffers are TTL FIGURE 5 9 TRISE REGISTER ADDRESS 89h R 0 R 0 R W 0 R W 0 U 0 R W 1 R W 1 R W 1 IBF OBF IBOV PSPMODE TRISE2 TRISE1 TRISEO R Readable bit bit7 bito W Writable bit bit 7 IBF Input Buffer Full Status bit 1 A word has been received and waiting to be read by the CPU 0 No word has been received bit 6 Output Buffer Full Status bit 1 The output buffer still holds a previously written word 0 The output buffer has been read bit 5 IBOV Input Buffer Overflow Detect bit in microprocessor mode U Unimplemented bit read as 0 n Value at POR reset 1 A write occurred when a previously input word has not been read must be cleared in software
154. plexed with comparator and voltage reference functions The operation of these pins are selected by control bits in the CMCON comparator control register register and the VRCON voltage reference control register When selected as comparator inputs these pins will read as 0 5 FIGURE 5 1 BLOCK DIAGRAM OF RA1 RAO PINS Q ck G Data Latch D Q VO Pin Y Analog Input Mode Schmitt Trigger Input Buffer TRIS pek G TRIS Latch RD TRIS RD PORT gt E To Comparator Note I O pins have protection diodes to VDD and Vss Note On reset the TRISA register is set to all inputs The digital inputs are disabled and the comparator inputs are forced to ground to reduce excess current consumption TRISA controls the direction of the RA pins even when they are being used as comparator inputs The user must make sure to keep the pins configured as inputs when using them as comparator inputs The RA2 pin will also function as the output for the voltage reference When in this mode the VREF pin is a very hi impedance output The user must set the TRISA lt 2 gt bit and use hi impedance loads In one of the comparator modes defined by the CMCON register pins RA3 and RA4 become outputs of the comparators The TRISA lt 4 3 gt bits must be cleared to enable outputs to use this function EXAMPLE 5 1 INITIALIZ
155. r 1 h x 45 9 ja lt D gt Base Seating up HH Plane Plane 1 Package Group Plastic SOIC SO Millimeters Inches Symbol Min Max Notes Min Max Notes 0 8 0 8 A 2 362 2 642 0 093 0 104 1 0 101 0 300 0 004 0 012 0 355 0 483 0 014 0 019 C 0 241 0 318 0 009 0 013 D 17 703 18 085 0 697 0 712 7 416 7 595 0 292 0 299 1 270 1 270 5 0 050 0 050 5 H 10 007 10 643 0 394 0 419 h 0 381 0 762 0 015 0 030 L 0 406 1 143 0 016 0 045 CP 0 102 0 004 DS30559A page 106 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X Package Type 28 Lead Ceramic Side Brazed Dual In Line with Window JW 300 mil C HH CHM C1 C1 C1 L T p eB gt Pin No 1 Indicator Area D gt Ste Base t Plane Seating A3 A2 Plane At B f a Em Le D1 gt Package Group Ceramic Side Brazed Dual In Line CER Millimeters Inches Symbol Min Max Notes Min Max Notes a 0 10 0 10 A 3 937 5 030 0 155 0 198 1 1 016 1 524 0 040 0 060 A2 2 921 3 506 0 115 0 138 1 930 2 388 0 076 0 094 B 0 406 0 508 0 016 0 020 1 1 219 1 32
156. r Response RR ARR een RE eet Rr petet apt tuto Ds 132 PIC16C64X amp PIC16C66X Product Identification System ss 135 To Our Valued Customers We constantly strive to improve the quality of all our products and documentation We have spent an exceptional amount of time to ensure that these documents are correct However we realize that we may have missed a few things If you find any information that is missing or appears in error please use the reader response form in the back of this data sheet to inform us We appreciate your assistance in making this a better document O 1996 Microchip Technology Inc Preliminary DS30559A page 3 PIC16C64X amp PIC16C66X NOTES T DS30559A page 4 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 1 0 GENERAL DESCRIPTION PIC16C64X amp 16 66 devices 28 40 pin EPROM based members of the versatile PIC16CXXX family of low cost high performance CMOS fully static 8 bit microcontrollers All PIC16 17 microcontrollers employ an advanced RISC architecture The PIC16CXXX family has enhanced core features eight level deep stack and multiple internal and external interrupt sources The separate instruction and data buses of the Harvard architecture allow a 14 bit wide instruction word with the separate 8 bit wide data The two stage instruction pipeline allows all instructions to execute in a sin gle cycle except for program
157. r eua VPN NE nr VAN PNA V RN vcn SE CLKOUT INT pin INTCON 1 GIE bit INTCON lt 7 gt INSTRUCTION FLOW i PC PCH 0004 00055 Instruction i INTF flag Interrupt Latency 2 fetched Inst PC Inst PC 1 Inst 0004h Inst 0005h ented Inst 1 Inst PC Dummy Cycle Inst 0004h Note 1 INTF flag is sampled here every Q1 2 Interrupt latency 3 4 Tcy where Tcy instruction cycle time Latency is the same whether Inst PC is a single cycle or a 2 cycle instruction 3 CLKOUT is available only in RC oscillator mode 4 For minimum width of INT pulse refer to AC specs 5 INTF is enabled to be set anytime during the Q4 Q1 cycles O 1996 Microchip Technology Inc Preliminary DS30559A page 67 PIC16C64X amp PIC16C66X 9 6 Context Saving During Interrupts Example 9 1 During an interrupt only the return PC value is saved Storesth W register regardless of current bank on the stack Typically users may wish to save key reg Stores the STATUS register in Bank 0 isters during an interrupt e g W register and STATUS Executes the ISR code register This will have to be implemented in software Restores the STATUS and bank select bit Example 9 1 stores and restores the STATUS and W register registers The user register W TEMP must be defined Restores the W register in both banks
158. re Instruction FLAG REG 0x0A After Instruction FLAG REG 0x8A 1996 Microchip Technology Inc DS30559A page 77 PIC16C64X amp PIC16C66X BTFSS Syntax Operands Operation Status Affected Encoding Description Words Cycles Example CALL Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Bit Test f Skip if Set label BTFSS fb 0 lt 1 lt 127 0 lt b lt 7 skip if lt b gt 1 None 01 11bb bfff ffff If bit b in register f is 1 then the next instruction is skipped If bit b is 1 then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead making this a 2 cycle instruction 1 1 2 HERE FLAG 1 FALSE GOTO PROCESS CODE TRUE Before Instruction PC address HERE After Instruction if FLAG lt 1 gt 0 PC address FALSE if FLAG lt 1 gt 1 PC address TRUE Call Subroutine label CALL k 0 lt k lt 2047 PC 1 TOS k PC lt 10 0 gt PCLATH lt 4 3 gt gt lt 12 11 gt None 10 Okkk kkkk kkkk Call Subroutine First return address PC 1 is pushed onto the stack The eleven bit immediate address is loaded into PC bits lt 10 0 gt The upper bits of the PC are loaded from PCLATH CALL is a two cycle instruction 1 2 CALL THERE Before Instruction PC Address HERE After Instruct
159. reakdown due to Electrostatic Dis charge ESD or Electrical Overstress EOS FIGURE 9 13 EXTERNAL BROWN OUT PROTECTION CIRCUIT 1 Note 1 This circuit will activate reset when VDD goes below Vz 0 7V where Vz Zener voltage Internal Brown out Reset circuitry should be disabled when using this cir cuit Resistors should be adjusted for the characteristics of the transistor 1996 Microchip Technology Inc Preliminary PIC16C64X amp PIC16C66X FIGURE 9 14 EXTERNAL BROWN OUT PROTECTION CIRCUIT 2 This brown out circuit is less expensive albeit less accurate Transistor Q1 turns off when VDD is below a certain level such that P1 ps o NY VDD RTF Internal Brown out Reset circuitry should be disabled when using this cir cuit Resistors should be adjusted for the characteristics of the transistor DS30559A page 65 PIC16C64X amp PIC16C66X 9 5 Interrupts The PIC16C641 and PIC16C642 have four sources of interrupt while the PIC16C661 and PIC16C662 have five sources External interrupt RBO INT TMRO overflow interrupt PORTB change interrupts pins RB7 RB4 Comparator interrupt Parallel Slave Port interrupt PIC16C661 662 The interrupt control register INTCON records individual core interrupt requests in flag bits It also has various individual enable bits and the global interrupt enable bit The global interrupt enable bit GIE INTCON l
160. red See Electrical Specifications for details When the device starts normal operation exits the reset condition device operating parameters voltage frequency temperature etc must be met to ensure operation If these conditions are not met the device must be held in reset until the operating conditions are met For additional information refer to Application Note AN607 Power up Trouble Shooting 9 4 POWER UP TIMER The Power up Timer provides a fixed 72 ms nominal delay on power up only from POR or BOR The Power up Timer operates on an internal RC oscillator The chip is kept in reset as long as PWRT is active The PWRT delay allows to rise to an acceptable level A configuration bit PWRTE can disable if set or enable if cleared or programmed the Power up Timer The Power up Timer should always be enabled when Brown out Reset is enabled FIGURE 9 8 BROWN OUT SITUATIONS The power up time delay will vary from chip to chip due to VDD temperature and process variations See DC parameters for details 9 4 8 OSCILLATOR START UP TIMER OST The Oscillator Start Up Timer OST provides a 1024 oscillator cycle from OSC1 input delay after the PWRT delay is over This ensures that the crystal oscillator or resonator has started and stabilized The OST time out is invoked only for XT LP and HS modes and only on Power on Reset or wake up from SLEEP 9 4 4 BROWN OUT RESET BOR P
161. rial EEPROM to demonstrate usage of the 2 bus and separate headers for connec tion to an LCD module and a keypad 11 8 PICDEM 3 Low Cost PIC16CXX Demonstration Board The PICDEM 3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package It will also support future 44 pin PLCC microcontrollers with a LCD Module All the neces sary hardware and software is included to run the basic demonstration programs The user can pro gram the sample microcontrollers provided with the PICDEM 3 board on a PRO MATE program mer or PICSTART Plus with an adapter socket and easily test firmware The PICMASTER emulator may also be used with the PICDEM 3 board to test firm ware Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket s Some of the features include an RS 232 interface push button switches a potenti ometer for simulated analog input a thermistor and separate headers for connection to an external LCD module and a keypad Also provided on the PICDEM 3 board is an LCD panel with 4 commons and 12 seg ments that is capable of displaying time temperature and day of the week The PICDEM 3 provides an addi tional RS 232 interface and Windows 3 1 software for showing the demultiplexed LCD signals on a PC A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals PICDEM 3 will be availab
162. s of the W register are added to the eight bit literal k and the result is placed in the W register Words 1 Cycles 1 Example ADDLW 0x15 Before Instruction W 0x10 After Instruction W 0x25 ADDWF Add W and f Syntax label ADDWF f d Operands 0 lt 1 lt 127 de 0 1 Operation W f dest Status Affected DC Z Encoding 00 0111 dfff ffff Description Add the contents of the W register with register f If d is O the result is stored in the W register If d is 1 the result is stored back in register f Words 1 Cycles 1 Example ADDWF FSR 0 Before Instruction W 0x17 FSR 0xC2 After Instruction W OxD9 FSR 0xC2 ANDLW And Literal with W Syntax label ANDLW k Operands 0 lt k lt 255 Operation W k W Status Affected Z Encoding 11 1001 kkkk kkkk Description The contents of W register are AND ed with the eight bit literal k The result is placed in the W register Words 1 Cycles 1 Example ANDLW 0x5F Before Instruction W AA After Instruction W 0x03 ANDWF ANDW with f Syntax label ANDWF fd Operands 0 lt f lt 127 de 0 1 Operation W AND f dest Status Affected 2 Encoding 00 0101 dfff ffff Description AND the W register with register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f Words 1 Cycles 1 Example ANDWF FSR 1
163. s placed in the W register If d is 1 the result is placed back in register f 1 1 IORWF RESULT 0 Before Instruction RESULT 0x13 W 0x91 After Instruction RESULT 0x13 W 0x93 Z 1 Move Literal to W label MOVLW k 0 lt k lt 255 k None 11 00 kkkk kkkk The eight bit literal K is loaded into W register The don t cares will assemble as 0s 1 1 MOVLW 0x5A After Instruction W Operands Operation Status Affected Encoding Description Words Cycles Example Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Move f label fd 0 lt 1 lt 127 de 0 1 f dest Z 00 1000 ffff The contents of register f is moved to a destination dependant upon the sta tus of d If d 0 destination is W reg ister If d 1 the destination is file register f itself d 1 is useful to test a file register since status flag Z is affected 1 1 MOVF FSR 0 After Instruction W value in FSR register Z 1 Move W to f label MOVWF f 0 lt 1 lt 127 W 2 f None 00 0000 lfff ffff Move data from W register to register 1 1 MOVWF OPTION Before Instruction OPTION OxFF W Ox4F After Instruction OPTION Ox4F W Ox4F 1996 Microchip Technology Inc DS30559A page 81 PIC16C64X amp
164. t 1 1 BOR enabled 0 BOR disabled PWRTE Power up Timer Enable bit 1 1 PWRT disabled 0 PWRT enabled WDTE Watchdog Timer Enable bit 1 2 WDT enabled 0 WDT disabled FOSC1 FOSCO Oscillator Selection bits 11 RC oscillator 10 HS oscillator 01 XT oscillator 00 LP oscillator bit 7 bit 6 bit 3 bit 2 bit 1 0 Note 1 Enabling Brown out Reset automatically enables the Power up Timer PWRT regardless of the value of bit PWRTE Ensure the Power up Timer is enabled anytime Brown out Reset is enabled All of the CP1 CPO pairs have to be given the same value to enable the code protection scheme listed DS30559A page 56 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 9 2 Oscillator Configurations TABLE 9 1 CAPACITOR SELECTION FOR CERAMIC RESONATORS 9 2 1 OSCILLATOR TYPES PRELIMINARY The PIC16CXXX can be operated four different oscillator modes The user can program two Ranges tested configuration bits FOSC1 and FOSCO to select one of Mode Freq OSC1 these four modes XT 455 kHz 22 100 pF e LP Low Power Crystal 2 0 MHz 15 68 pF XT Crystal Resonator 4 0 MHz 15 68 pF HS High Speed Crystal Resonator HS 8 0 MHz 10 68 pF RC Resistor Capacitor 16 0 MHZ 10 22pF Note Recommended values of C1 and C2 are identical 9 2 2 CRYSTAL OSCILLATOR CERAMIC to the ranges tested table RESONATORS Higher capacitance increas
165. t C1 VN bit 5 4 Unimplemented Read as bit 3 CIS Comparator Input Switch When 2 0 001 Then 1 C1 Vn connects to 0 C1 connects to RAO When CM2 CMO 010 Then 1 C1 Vn connects to C2 Vin connects to RA2 0 C1 Vm connects to RAO C2 Vin connects to RA1 bit 2 0 CM2 CMO Comparator mode Figure 7 2 shows the comparator modes and CM2 CMO bit settings 1996 Microchip Technology Inc Preliminary DS30559A page 47 1 am AMA PIC16C64X amp PIC16C66X 7 1 Comparator Configuration There are eight modes of operation for the comparators The CMCON register is used to select the mode Figure 7 2 shows the eight possible modes The TRISA register controls the data direction of the comparator pins for each mode If the comparator FIGURE 7 2 Comparators Reset POR Default Value CM2 CMO 000 RAO ANO Vi ff R o A Off Read as 0 RA1 AN1 Read 0 RA2 AN2 mode is changed the comparator output level may not be valid for the specified mode change delay shown in Table 12 2 Note Comparator interrupts should be disabled during comparator mode change other wise a false interrupt may occur COMPARATOR I O OPERATING MODES Comparators Off CM2 CMO 111 D RAO ANO ff R 0 D_ Mur RA1 AN1 D Off Read as 0 RA2 AN2 Two Inde
166. t 7 gt enables if set all un masked interrupts or disables if cleared all interrupts Individual interrupts can be disabled through their corresponding enable bits in INTCON register GIE is cleared on reset The return from interrupt instruction RETF IE exits the interrupt routine as well as sets the GIE bit which allows any pending interrupt to execute Those interrupts associated with the core have their flag and enable bits in the INTCON register The core interrupts are RBO INT pin interrupt the RB port change interrupt and the TMRO overflow interrupt The INTCON register also contains the Peripheral Interrupt Enable bit PEIE Bit PEIE will enable mask the periph eral interrupts CM and PSP from vectoring when bit PEIE is set cleared Flag bits PSPIF and CMIF are contained in special function register PIR1 The corresponding interrupt enable bits PSPIE and CMIE are contained in special function register PIE1 FIGURE 9 15 INTERRUPT LOGIC CMIF PSPIF PSPIEU 3 mo SE DY When an interrupt is responded to the GIE is cleared to disable any further interrupt the return address is pushed into the stack and the PC is loaded with 0004h Once in the interrupt service routine the source s of the interrupt can be determined by polling the interrupt flag bits The interrupt flag bit s must be cleared in software before re enabling interrupts to avoid recur sive interrupts
167. t Bank 1 MOVLW 0x07 RA3 RAO to outputs MOVWF TRISA MOVLW 0 6 enable Vref low MOVWF VRCON range VR3 VRO 6 BCF STATUS RPO Select Bank 0 CALL DELAY 10ps 10 Us delay 8 2 Voltage Reference Accuracy Error The full range of Vss to VDD cannot be realized due to the construction of the module The transistors on the top and bottom of the resistor ladder network Figure 8 2 keep VREF from approaching VSS or VDD The Voltage Reference is derived and therefore FIGURE 8 3 PIC16C662 RO VREF the VREF output changes with fluctuations in absolute accuracy of the Voltage Reference can be found in Table 12 3 8 3 Operation During Sleep When the device wakes up from sleep through an interrupt or a Watchdog Timer time out the contents of the VRCON register are not affected To minimize current consumption in SLEEP mode the Voltage Reference Module should be disabled 8 4 Effects of a Reset A device reset disables the Voltage Reference by clear ing bit VREN VRCON lt 7 gt This reset also disconnects the reference from the RA2 pin by clearing bit VROE VRCON lt 6 gt and selects the high voltage range by clearing bit VRR VRCON 5 The VREF value select bits VRCON lt 3 0 gt are also cleared 8 5 Connection Considerations The Voltage Reference Module operates independently of the comparator module The output of the reference generator may be connected to the RA2 pin if
168. t Serial Programming Connection set en doen dents 71 Figure 10 1 General Format for Instructions 73 Figure 12 1 Load Conditions 97 Figure 12 2 External Clock Timing 2 98 Figure 12 3 CLKOUT and I O Timing 99 Figure 12 4 Reset Watchdog Timer Oscillator Start Up Tim er and Timing 100 Figure 12 5 Brown out Reset Timing 100 Figure 12 6 0 Clock Timing 101 Figure 12 7 Parallel Slave Port Timing PIC16C661 and PlO166662 innen e tons 102 LIST OF TABLES Table 1 1 PIC16C64X amp PIC16C66X Device Features 6 Table 3 1 PIC16C641 642 Pinout Description 12 Table 3 2 16 661 662 Pinout Description 2 13 Table 4 1 Special Function Registers 2 20 Table 5 1 PORTA Functions eee 31 Table 5 2 Summary of Registers Associated With Table 5 3 Table 5 4 Table 5 5 Table 5 6 Table 5 7 Table 5 8 Table 5 9 Table 5 10 Table 5 11 Table 6 1 Table 7 1 Table 8 1 Table 9 1 Table 9 2 Table 9 3 Table 9 4 Table 9 5 Table 9 6 Table 10 1 Table 10 2 Table 11 1 Table 12 1 Table 12 2 Table 12 3 Table 12 4 Table 12 5 Table 12 6 Table 12 7 Table 12 8 Table E 1 Summary of Registers Associated with PORTE 34 PORTD
169. t or eleven bit constant or literal value TABLE 10 1 FIELD DESCRIPTIONS Field Description t Register file address 0x00 to Ox7F Working register accumulator Literal field constant data or label W b Bit address within an 8 bit file register k Don t care location 0 or 1 The assembler will generate code with x 0 It is the recommended form of use for compatibility with all Microchip software tools d Destination select 0 store result in W d 1 store result in file register f Default is d 1 label Label name TOS Top of Stack PC Program Counter PCLATH Program Counter High Latch GIE Global Interrupt Enable bit WDT Watchdog Timer Counter TO Time out bit PD Power down bit dest Destination either the W register or the specified register file location Options Contents Assigned to lt gt Register bit field In the set of italics User defined term font is courier The instruction set is highly orthogonal and is grouped into three basic categories Byte oriented operations Bit oriented operations Literal and control operations All instructions are executed within one single instruc tion cycle unless a conditional test is true or the pro gram counter is changed as a result of an instruction In this case the execution takes two instruction
170. ta for desired device for varia tion of oscillator frequency due to VDD for given Rext Cext values as well as frequency variation due to oper ating temperature for given R C and VDD values The oscillator frequency divided by 4 is available on the OSC2 CLKOUT pin and can be used for test pur poses or to synchronize other logic see Figure 3 3 for waveform FIGURE 9 6 _RC OSCILLATOR MODE Internal wm clock PIC16CXXX OSC2 CLKOUT 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 9 3 Reset The PIC16CXXX differentiates between various kinds of reset a Power on reset POR b MCLR reset during normal operation c MCLR reset during SLEEP d WDT reset normal operation e Brown out Reset BOR f Parity Error Reset PER Some registers are not affected in any reset condition their status is unknown on POR and unchanged in any other reset Most other registers are reset to a reset state on Power on reset MCLR WDT reset Brown out Reset Parity Error Reset and on MCLR reset during SLEEP They are not affected by a WDT wake up since this is viewed as the resumption of nor mal operation TO and PD bits are set or cleared differ ently in different reset situations as indicated in Table 9 4 These bits are used in software to determine the nature of the reset See Table 9 6 for a full descrip tion of reset states of all registers A simplified block diagram of the on
171. te Instructions on an VO RON ree retro Example 6 1 Changing Prescaler Timer0 WDT Example 6 2 Changing Prescaler WDT TimeroO Example 7 1 lnitializing Comparator Module Example 8 1 Voltage Reference Configuration Example 9 1 Saving the STATUS and W Registers in LIST OF FIGURES Figure 3 1 PIC16C641 642 Block Diagram 10 Figure 3 2 16 661 662 Block Diagram ET Figure 3 3 Clock Instruction Cycle Figure 4 1 PIC16C641 661 Program Memory Map and Figure 4 2 PIC16C642 662 Program Memory Map and Figure 4 3 16 641 661 Data Memory Map Figure 4 4 PIC16C642 662 Data Memory Map Figure 4 5 STATUS Register Address 03h 83h Figure 4 6 OPTION Register address 81h Figure 4 7 INTCON Register address OBh 8Bh 23 Figure 4 8 PIE1 Register address 8Ch 24 Figure 4 9 PIR1 Register address OCh 25 Figure 4 10 PCON Register Address 8Eh 26 Figure 4 11 Loading Of PC In Different Situations 27 Figure 4 12 Direct indirect Addressing 28 Figure 5 1 Block Diagram of RA1 RAO Pins Figure 5 2 Block Diagram of RA2 jt Figure 5 3 Block Diagram of RAS Pin Figure 5 4 Block Diagram of Pin Figure 5 5
172. ted BYTE ORIENTED FILE REGISTER OPERATIONS ADDWF Add W andf 1 00 0111 dfff 00 2 1 2 ANDWF fid AND W with f 1 00 0101 afff ffff Z 1 2 CLRF f Clear f 1 00 0001 1fff 7 2 CLRW Clear W 1 00 000 0000 0011 Z COMF f d Complement f 1 00 001 dfff ffff 2Z 1 2 DECF f d Decrement f 1 00 0011 dfff ffff Z 1 2 DECFSZ fd Decrement f Skip if O 1 2 00 011 dfff ffff 1 2 3 INCF fd Increment f 1 00 010 dfff ffff Z 1 2 INCFSZ fd Increment f Skip if 0 1 2 00 111 dfff 1 2 3 IORWF fd Inclusive OR W with f 1 00 0100 afff ffff Z 1 2 MOVF fd Movef 1 00 000 dfff ffffZ 1 2 MOVWF f Move W to f 1 00 0000 1fff ffff NOP No Operation 1 00 0000 OxxO 0000 RLF f d Rotate Left f through Carry 1 00 01 dfff ffff C 1 2 RRF f d Rotate Right f through Carry 1 00 00 dfff ffff C 1 2 SUBWF fid Subtract W from f 1 00 0010 afff ffff C DCZ 1 2 SWAPF fd Swap nibbles in f 1 00 10 dfff ffff 1 2 XORWF fd Exclusive OR W with f 1 00 0110 dfff 2 1 2 BIT ORIENTED FILE REGISTER OPERATIONS BCF f b Bit Clear f 1 01 00bb ffff 1 2 BSF fb BitSetf 1 01 01bb bfff ffff 1 2 BTFSC fb Bit Test f Skip if Clear 1 2 01 Obb bfff ffff 3 BTFSS fb Bit Test f Skip if Set 1 2 01 bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 1x kkkk kkkk C DCZ ANDLW k AND literal with W 1 11 001 kkkk kkkk Z CALL k Call subroutine 2 10 Okkk kkkk kkkk CLRWDT Clear Watchdog Timer 1 00 00
173. the TRISA lt 2 gt bit is set and bit VROE is set Enabling the Voltage Reference output onto the RA2 pin with an input signal present will increase current consumption Connecting RA2 as a digital output with VREF enabled will also increase current consumption The RA2 pin can be used as a simple D A output with limited drive capability Due to the limited drive capability a buffer must be used in conjunction with the Voltage Reference output for external connections to VREF Figure 8 3 shows an example buffering technique VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE Module Voltage Reference Output Impedance VREF output Note 1 Ris dependent upon the Voltage Reference Configuration VRCON lt 3 0 gt VRCON lt 5 gt TABLE 8 1 REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE Value On Value on Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit 2 Bit 1 Bit 0 POR all other BOR resets 9Fh VRCON VREN VROE VRR VR3 VR2 VR1 VRO 000 0000 000 0000 1Fh CMCON C2OUT C1OUT CIS CM2 CM1 00 0000 00 0000 85h TRISA 5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 11 1111 11 1111 DS30559A page 54 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X 9 0 SPECIAL FEATURES OF THE CPU What sets apart a microcontroller from other processors are special circuits to deal with the needs
174. ts to indicate stack overflow or stack underflow conditions Note 2 There are no instructions mnemonics called PUSH or POP These are actions that occur from the execution of the CALL RETURN RETLW and RETFIE instruc tions or the vectoring to an interrupt address 4 4 Program Memory Paging PIC16C642 and PIC16C662 devices have 4K of pro gram memory but the CALL and GOTO instructions only have an 11 bit address range This 11 bit address range allows a branch within a 2K program memory page size To allow CALL and GOTO instructions to address the entire 4K program memory address range there must be another bit to specify the program mem ory page This paging bit comes from the PCLATH lt 3 gt bit Figure 4 11 When doing a CALL or GOTO instruc tion the user must ensure that this page select bit PCLATH lt 3 gt is programmed so that the desired pro gram memory page is addressed If a return from a CALL instruction or interrupt is executed the entire 13 bit PC is pushed onto the stack Therefore manipu lation of the PCLATH lt 3 gt bit is not required for the return instructions which POPs the address from the stack Note The PIC16C64X amp PIC16C66X ignore the PCLATH lt 4 gt bit which is used for program memory pages 2 and 3 1000h 1FFFh The use of PCLATH lt 4 gt as a general pur pose read write bit is not recommended since this may affect upward compatibility with future products
175. tt Trigger input TTL TTL input Note 1 Input buffers are Schmitt Triggers when in mode and TTL buffers when in Parallel Slave Port Mode TABLE 5 10 SUMMARY OF REGISTERS ASSOCIATED WITH PORTE value Value on all Address Bit7 Bit6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR other resets BOR 09h PORTE RE2 RE1 REO uuu 89h TRISE IBF IBOV PSPMODE TRISE2 TRISE1 TRISEO 0000 111 0000 111 Legend unknown u unchanged unimplemented read as 0 Shaded cells are not used by PORTE 1996 Microchip Technology Inc Preliminary DS30559A page 37 PIC16C64X amp PIC16C66X 5 6 Programming Considerations EXAMPLE 5 4 READ MODIFY WRITE INSTRUCTIONS ON AN 5 6 1 BI DIRECTIONAL I O PORTS PORT Any instruction which writes operates internally as a Initial PORT settings PORTB lt 7 4 gt Inputs read followed by a write operation The BCF and BSF PORTB lt 3 0 gt Outputs instructions for example read the register into the lt 7 6 gt have external pull ups and are CPU execute the bit operation and write the result inot connected to other circuitry back to the register Caution must be used when these instructions are applied to a port with both inputs and outputs defined For example a BSF operation on bit5 PORT latch PORT pins of PORTE will cause all eight bits of POR
176. uld 02 2105 did uid 8 9 0 8909101 4085 0105 did uid 8z 9 6 A SHD9LOId dOSS 105 did uid gz 9 4 28291014 dOSS uld 02 O1OS did uid 8 9 6 98091018 4055 010S did uid 8z 9 6 99091014 dOSS 4 0 20105 did 81 9 0 VvrSHO9LOld dOSS uid 02 2105 did uid 8 9 0 909101 4055 9 08 2105 did 9 81 9 6 509104 2105 uid 81 9 4 04291014 seine 5 1996 Microchip Technology Inc DS30559A page 118 PIC16C64X amp PIC16C66X of Devices PIC16CXXX Famil E 3 uid pue 94H jenas esn Ajlwe4 XXX999L91d upiqedeo jue uno Oll uDiu pue 109101d BOPYJEM 9 JEII9 9S Josey Ale LL 9LOld Ud py 299091014 Ud py 9 0 19909214 PSMOPUIM 2105 uid 8z 9 0 07929214 PSMOPUIM 2105 uid 8z 9 0 199291014 dOSS uid 02 2105 did uld g 9 8 22909014 dOSS uid 02 20105 did uid 81 9 4 129291014 dOSS uld 02 2105 did 9 8 1 9 5 029091014 dOSS uid 02 2105 did 19 8 1 9 8 899091019 dOSS utd oz 20105 did uid 81 OG 99909 919 4055 uld 02 2105 9 8 1 9 5 79999
177. urrent on the MCLR pin is strongly dependent on applied voltage level The specified levels repre sent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as coming out of the pin DS30559A page 94 Preliminary 1996 Microchip Technology Inc PIC16C64X amp PIC16C66X Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt TA lt 85 C for industrial 0 C lt TA lt 70 C commercial and 40 C lt TA lt 125 C automotive Operating voltage VDD range as described in DC spec Section 12 1 and 12 2 Param Sym Characteristic Min Typ Max Unit Conditions No t Output High Voltage 9 D090 ports Except RA4 VDD 0 7 V loH 3 0 mA VDD 4 5V 40 to 85 C loH 2 5 mA 0092 OSC2 CLKOUT VDD 0 7 V RC only Capacitive Loading Specs on Output Pins D100 Coscz 5 2 pin 15 HS and LP modes when al clock used to drive OSC1 All I O pins OSC2 in RC mode Note 1 2 3 Negative current is defined as coming S NS 1996 Microchip Technology Inc Preliminary DS30559A page 95 PIC16C64X amp PIC16C66X TABLE 12 2 COMPARATOR SPECIFICATIONS Operating Conditions 3 0V lt VDD lt 6 0V 40 C lt lt 125 C unless otherwise stated Current consumption is spec
178. ut Reset Current BODEN bit is clear VDD 5 0V D016 Comparator Current for VDD 3 0V each Comparator D017 AIVREF VREF Current VDD 3 0V D021 AIWDT WDT Current VDD 3 0V D021 IPD Power down Current 3 0V WDT disabled These parameters are characterized T Data in column is at 5 0V 25 C u and are not tested Note 1 This is the limit to which abled disabled as specified ent in SLEEP mode does not depend on the oscillator type Power down current is 4 XC o c configuration current through Rext is not included The current through the resistor can be 5 A current is the additional current when this peripheral is enabled This current should be adsled to the base IDD or IPD measurement 1996 Microchip Technology Inc Preliminary DS30559A page 93 PIC16C64X amp PIC16C66X 12 3 DC Characteristics 16 641 661 Commercial Industrial Automotive PIC16C642 662 Commercial Industrial Automotive PIC16LC641 661 Commercial Industrial PIC16LC642 662 Commercial Industrial Standard Operating Conditions unless otherwise stated Operating temperature 409 lt TA lt 85 C for industrial 0 C lt TA lt 70 C commercial and 40 C lt TA lt 125 C automotive Operating voltage VDD range as described in DC spec Section 12 1 and 12 2 Param Sym Characteristic Min Typ Max Unit Condit No t VIL Input Low Voltage
179. wap Nibbles in f XORLW Exclusive OR Literal with W Syntax abel Syntax label XORLW k Operands 0 lt 1 lt 127 Operands 0 lt k lt 255 de 0 1 0 11 Operation W XOR k gt W Operation lt 3 0 gt dest lt 7 4 gt S Aitacied 7 f lt 7 4 gt gt dest lt 3 0 gt tatus Affected Status Affected None Encoding 11 1010 kkkk kkkk ERE Description The contents of the W register are Encoding B XOR ed with the eight bit literal k Description The upper and lower nibbles of regis The result is placed in the W regis ter f are exchanged If d is 0 the ter result is placed in W register If d is 1 the result is placed in register Words 1 Words 1 1 1 Example XORLW OxAF Example SWAPF REG 0 Before Instruction Before Instruction Mc REGI OxA5 After Instruction After Instruction 0xA5 W Ox5A TRIS Load TRIS Register XORWF Exclusive OR W with f Syntax label TRIS f Syntax label XORWF 1 Operands Operands 0 lt lt 127 Operation W gt TRIS register f de 0 1 Status Affected None Operation W XOR f gt dest Encoding 00 0000 0110 Status Affected 7 Description The instruction is supported for code Encoding 00 0110 ffff compatibility with the PIC16C5X prod M ucts Since TRIS registers are read Description Exclusive OR the contents ol the W able and writable the us
180. wo types of crystal oscillator circuits can be used one with series resonance or one with parallel resonance Figure 9 4 shows implementation of a parallel resonant oscillator circuit The circuit is designed to use the fun damental frequency of the crystal The 74 504 inverter performs the 180 degree phase shift that a parallel oscillator requires The 4 7 resistor provides the negative feedback for stability The 10 potentiome ter biases the 74AS04 in the linear region This could be used for external oscillator designs FIGURE 9 4 EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT To Other Devices 4 7k 74AS04 PIC16CXXX 74AS04 CLKIN Figure 9 5 shows a series resonant oscillator circuit This circuit is also designed to use the fundamental fre quency of the crystal The inverter performs a 180 degree phase shift in a series resonant oscillator circuit The 330 resistors provide the negative feed back to bias the inverters in their linear region FIGURE 9 5 EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT To Other 330 330 Devices W ANN p CLKIN 74AS04 74AS04 74AS04 PIC16CXXX 0 X DS30559A page 58 Preliminary 9 2 4 RC OSCILLATOR For timing insensitive applications the RC device option offers additional cost savings The RC oscillator frequency is a function of the supply voltage the resis tor Rext and c
181. y of Devices Voltage Reference Output Buffer 54 VO M V Ne S e Watchdog Timer eee AN OS SOA Nov ARE EE Brown out Reset BOR ue 60 PIC16G64X pace eee recette ideni 6 BSF Instruction 77 ate teens inte 6 BIFSC Instructions ein 77 5 NES NE PS 151 BTFSS Instruction sss 78 en I a 195 e 123 C Compiler MPLAB C PIC TSC o r A r DRM 119 CALE INSTRICHON en cta apa diuo tam PICT7CXX nn 124 Clocking Scheme Instruction Cycle 15 Fuzzy Logic Dev System fuzzyTECHG MP 87 89 CERF Instruction 78 G CLRWDT Instruction Purpose Register Fe iss CMCON Register eee nenene 47 GOTO Instruction 2 4 0 9 099 0 0 0 0 0 7 4 80 1996 Microchip Technology Inc Preliminary DS30559A page 127 1 Rad AMA PIC16C64X amp PIC16C66X Programming Considerations 38 ICEPIC In Circuit Emulator ID LOCATIONS UTE INCF Instruction INCFSZ Instruction sen In Circuit Serial Programming Indirect Addressing INDF and FSR Registers 28 Instruction Flow Pipelining eee 15 Instruction Format eee 73 Instruction Set ADDEW 76 76 ANDEW

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