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TEXAS INSTRUMENTS TSD41AB1 handbook

1. Top View NOTE All linear dimensions are in millimeters Exposed Thermal Pad Dimensions 4206329 2 0 he thermal pad be for the device or alternatively optimizes the heat transfer its heat dissipating ruments Literature 02 08 LAND PATTERN PHP R PDSO G48 PowerPAD NOTES Example Board Layout 0 127mm Thick Stencil Design Example Via pattern and copper pad size Reference table below for other may vary depending on layout constraints solder stencil thicknesses Note E 44x0 5 r 48x1 55 4x 48 0 25 Non Solder Mask Defined Pad Example Solder Mask Opening Note F Center Power Pad Solder Stencil Opening Pad Geometry 0 05 Note C All Around 4207626 2 B 03 06 All linear dimensions are in millimeters This drawing is subject to change without notice Publication 7351 is recommended for alternate designs This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMAO02 SLMAO004 and also the Product Data Sheets for specific thermal information via requirements and recommended board layout These documents are available at www ti com http www ti com Laser cutting apertures with trap
2. NC NC4 NC4 NC4 INC NEC 2 Neco SH NEC D7 PD TPA 2 2 INC3 NC3 VJ NM NS ir Ms D6 TPBIAS p aa 10 NC2 Nc2 Nc2 Nc2 NC1 Lu 2 7 1 4 4 M D4 RO 1 7 AGND D PEN PEN NC2 Net D2 AVDD D1 R1 DO CTL1 AGND CTLO AGND SYSCLK or aa 5 aa az z x za zu 50 29 9 95 tc ad ad NOTES A NC not connected For latch up considerations it is recommended that the TESTM terminal have a pullup resistor 48 5 INSTRUMENTS 6 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 ZQE package terminal diagram NC connections top view ZQE PACKAGE TERMINAL DIAGRAM TOP VIEW a a a a z a On Zo o gt gt Q oo lt lt 0 o C LKON TPB LPS TPA D7 PD TPA 2020 NC NC2 NC3 NC3 22 4 1 lt 2 N idc MEM N Mag 2 BE NX D6 TPBIAS EDEN Ps 2 2 NCI EN 5 x D4 RO s D3 AGND p p 4L PEN p NC2 1 2 AVDD D1 R1
3. required for normal network operation regardless of the state of the PHY LLC interface When the interface is in the reset or disabled state and LPS is again observed active the PHY initializes the interface and returns it to normal operation When the PHY LLC interface is in the low power disabled state the TSB41AB1 automatically enters a low power mode if the port is inactive disconnected disabled or suspended In this low power mode the TSB41AB1 disables its internal clock generators and also disables various voltage and current reference circuits depending on the state of the port some reference circuitry must remain active in order to detect new cable connections disconnections or incoming TPBIAS for example The lowest power consumption the ultralow power sleep mode is attained when the port is either disconnected or disabled with the port interrupt enable bit cleared The TSB41AB1 exits the low power mode when the LPS input is asserted high or when a port event occurs which requires that the TSB41AB1 become active in order to respond to the event or to notify the LLC of the event for example incoming bias is detected on a suspended port a disconnection is detected on a suspended port a new connection is detected on a nondisabled port etc The SYSCLK output becomes active and the PHY LLC interface is initialized and becomes operative within 7 3 ms after LPS is asserted high when the TSB41AB1 is in the low power mode The P
4. 150 0 1 939 NDGND 4 8 sc C 2 F DVDD VDD Power Class 3 C PG Programming LREQ SYSCLK 3 a 2 olo o RIZ CNA OUT POWER DOWN See Figure 10 Figure 11 and Figure 12 See Figure 13 and Figure 14 See Terminal Functions Table 1 See crystal selection section for more details Figure 8 External Component Connections ZQE 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION component connection continued ZQE Package Terminal Diagram TOP VIEW 2 8 E 8 o o N T e Ss u 58 99 a0 86 9 amp C LKON TPB LPS TPA D7 PD TPA D5 D6 TPBIAS D4 RO D3 AGND D2 AVDD D1 R1 DO CTL1 AGND CTLO AGND SYSCLK 82 2 8 28 564 202 58 9 04 t ad Add zi a 4 aa NOTE connected Figure 9 Recommended Application Board Layout for ZQE Package 4 EXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 27 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 511154231 JUNE 2000 REVISED
5. Generator Transmit Data PD Encoder RESET T CNA output is only available in the 64 pin PAP package 49 5 INSTRUMENTS 10 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 ET A Crystal Oscillator PLL System and Clock Generator TPA TPA TPB TPB Xl XO FILTERO FILTER1 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 Terminal Functions TERMINAL PHP AQ B9 Supply D9 J8 25 35 B8 C8 Supply H7 J1 CMOS I O Bus manager contender programming input and link on output On hardware reset this terminal is used to set the default value of the contender status indicated during self ID Programming is done by tying the terminal through a 10 resistor to a high contender or low not contender The resistor allows the link on output to override the input However it is recommended that this terminal should be programmed low and that the contender status be set via the C register bit If the TSB41AB1 is used with an LLC that has a dedicated terminal for monitoring LKON and also setting the contender status then a 1 kQ series resistor should be placed on the LKON line between the PHY and LLC to prevent bus contention Following hardware reset this terminal is the link on output which is used to notify the LLC to power up and beco
6. TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 Fully Supports Provisions of IEEE Failsafe Circuitry Senses Sudden Loss of 1394 1995 Standard for High Performance Power to the Device and Disables the Port Serial Bust and IEEE 1394a 2000 to Ensure That the Device Does Not Load i LINK Implementation of IEEE Std 1394 Blocks Any Leakage Path From the Port Back to the Device Power Plane Software Device Reset SWR Industry Leading Low Power Consumption Ultralow Power Sleep Mode Fully Compliant With OpenHCl Requirements Provides One IEEE 1394a 2000 Fully Compliant Cable Port at 100 200 400 Megabits Per Second Mbits s Cable Power Presence Monitoring 9 Full IEEE 1394a 2000 Support Includes Cable Ports Monitor Line Conditions for Connection Debounce Arbitrated Short Active Connection to Remote Node Reset Multispeed Concatenation 2 Arbitration Acceleration Fly By Data Interface to Link Layer Controller Through 2 4 8 Parallel Lines at 49 152 MHz Concatenation Port Disable Suspend Resume Interface to Link Layer Controller Supports Low Cost TI Bus Holder Isolation and Optional Annex J Electrical Isolation Register Bits Give Software Control of Contender Bit Power Class Bits Link Active Control Bit and IEEE 1394a 2000 Interoperable With Link Layer Controllers Features Using 3 3 V 1394a 2000 Compliant Common Mode
7. www ti com gt E Falls within JEDEC 5 026 PowerPAD is a trademark of Texas Instruments 48 5 INSTRUMENTS www ti com 3 TEXAS INSTRUMENTS www ti com 2 external h attached can be a from the For additi abilities refer to Technical Brief PowerPA No SLMAO02 and Application Brief Power ERMAL INFORMA TION This PowerPAD package incorporates an exposed thermal pad that is designed to be attached directly to an eatsink The thermal pad must be soldered directly to the printed circuit board PCB After soldering the PCB can be used as a heatsink In addition through the use of thermal vias directly to the appropriate copper plane shown in the electrical schematic ucture designed into the PCB This design integrated circuit IC tached to a special heatsink str Both documents are available at www ti com The exposed thermal pad dimensions for THERMAL PAD MECHANICAL DATA information on the PowerPAD package and how to take advantage o D Thermally Enhanced Package Texas Ins PAD Made Easy Texas Instruments Literature No 51 004 25 37 PHP S 048 his package are shown in the following illustration 24 48
8. DO CTL1 AGND CTLO AGND SYSCLK aa a ul 2 2 2 za 2 g 202 38 8 596 a2 J oa NOTES A NC not connected B For latch up considerations it is recommended that the TESTM terminal have a pullup resistor 49 5 POST OFFICE BOX 655303 DALLAS TEXAS 75265 7 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 GQE package terminal diagram NC connections bottom view GQE PACKAGE TERMINAL DIAGRAM BOTTOM VIEW a z a a a a 2 oz os 0 sa a 98 amp 92 EO 22 C LKON LPS NC4 NC4 NC4 D7 PD NC3 NC3 NC2 NC2 NC D5 7 27 2 e D6 ETN 2 2 2 2 5 1 lt NCI NCI NCI D2 MP D1 DO CTL1 CTLO SYSCLK aa za e ro 0 gt 9 gt za cr ua 56 g 8 45 KE H a ad aa a a a NOTES A NC not connected For latch up considerations it is recommended that the TESTM terminal have a pullup resistor 49 5 INSTRUMENTS 8 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TPB TPB TPA TPA TPBIAS RO AGND AVDD R1 AGND AGND
9. TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 ZQE package terminal diagram NC connections bottom view ZQE PACKAGE TERMINAL DIAGRAM BOTTOM VIEW AGND TPB C LKON TPB LPS TPA D7 PD TPA A NC3 NC3 2 NC A j D5 MPO NEU UE pu D6 1 os TPBIAS NCI 2 2 D4 Ne CINE A D3 RO AS AS ET AGND J NC2 D2 D1 AVDD R1 DO CTL1 AGND CTLO AGND SYSCLK zn a x as Q 22 za rc 5 gt 5 gt Eu gt d dd 55 amp oa NOTES A NC not connected B For latch up considerations it is recommended that the TESTM terminal have a pullup resistor 5 POST OFFICE BOX 655303 DALLAS TEXAS 75265 9 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 94231 JUNE 2000 REVISED MARCH 2005 functional block diagram V D Cable Port CPS LPS Received Data ISO Link Decoder Retimer CNAT Interface y o SYSCLK LREQ CTLO CTL1 DO D1 9 2 D3 D4 Arbitration D5 and Control D6 State Machine D7 Logic PCO PC1 PC2 C LKON RO Bias Voltage R1 and Current TPBIAS
10. synchronized with data transfers to the LLC 46 Test control input This input is used manufacturing test of the TSB41AB1 For normal use this terminal should be tied to Vpp through a 1 kQ resistor m gt N oj o A F9 Twisted pair cable A differential signal terminals Board traces from the pair of positive and negative differential signal terminals should be kept matched and as G9 short as possible to the external load resistors and to the cable connector Twisted pair cable B differential signal terminals Board traces from the pair of positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector TPBIAS 38 E9 Cable I O Twisted pair bias output This provides the 1 86 V nominal bias voltage needed for proper operation of the twisted pair cable drivers and receivers and for signaling to the remote nodes that there is an active cable connection XI 59 42 A5 Crystal Crystal oscillator inputs These terminals connect to a 24 576 MHz parallel resonant XO 60 43 A4 fundamental mode crystal The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used see crystal selection in the Application Information section When an external clock source is used should be the input and XO should be left open and the clock must be supplied befo
11. the PHY ignores any fair or priority requests if receive is asserted while the LLC is sending the request The LLC may then reissue the request one clock after the next interface idle The cycle master node uses a priority bus request PriReq to send a cycle start message After receiving or transmitting a cycle start message the LLC can issue isochronous bus request IsoReq The PHY clears an isochronous request only when the serial bus has been won To send an acknowledge packet the LLC must issue an immediate bus request ImmReq during the reception of the packet addressed to it This is required in order to minimize the idle gap between the end of the received packet and the start of the transmitted acknowledge packet As soon as the receive packet ends the PHY immediately grants control of the bus to the LLC The LLC sends an acknowledgment to the sender unless the header CRC of the received packet is corrupted In this case the LLC does not transmit an acknowledge but instead cancels the transmit operation and releases the interface immediately the LLC must not use this grant to send another type of packet After the interface is released the LLC may proceed with another request 49 5 INSTRUMENTS 46 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF O
12. 1 Root This bit indicates that this node is the root node The R bit is reset to 0 by bus reset and is set to 1 during tree ID if this node becomes root FIELD Physical ID Cable power status This bit indicates the state of the CPS input terminal The CPS terminal is normally tied to serial bus cable power through a 400 kQ resistor A 0 in this bit indicates that the cable power voltage has dropped below its threshold for reliable operation Rd Wr Root holdoff bit This bit instructs the PHY to attempt to become root after the next bus reset The RHB is reset to 0 by hardware reset and is unaffected by bus reset Rd Wr Initiate bus reset This bit instructs the PHY to initiate a long 166 us bus reset at the next opportunity Any receive or transmit operation in progress when this bit is set completes before the bus reset is initiated The IBR bit is reset to 0 by hardware reset or bus reset Gap_Count Rd Wr Arbitration gap count This value is used to set the subaction fair gap arb reset gap and arb delay times The gap count may be set either by a write to this register or by reception or transmission of a CONFIG packet The gap count is set to 3Fh by hardware reset or after two consecutive bus resets without an intervening write to the gap count register either by a write to the PHY register or by a CONFIG packet pe EM register definition For the TSB41AB 1 this field is 111b indicating that the extended
13. Drawing Qty TSB41AB1GQE ACTIVE BGA MI GQE 80 360 TBD SNPB Level 2A 235C 4 WKS CROSTA R JUNI OR TSB41AB1PAP ACTIVE HTQFP PAP 64 160 Green RoHS amp CUNIPDAU Level 3 260C 168 HR no Sb Br TSB41AB1PAPG4 ACTIVE 64 160 Green RoHS amp CUNIPDAU Level 3 260C 168 HR no Sb Br TSB41AB1PHP ACTIVE HTQFP PHP 48 250 Green RoHS amp CU NIPDAU Level 3 260C 168 HR no Sb Br TSB41AB1PHPG4 ACTIVE HTQFP PHP 48 250 Green RoHS amp CU NIPDAU Level 3 260C 168 HR no Sb Br TSB41AB1ZQE 64 ACTIVE BGA MI ZQE 64 360 Green RoHS amp SNAGCU Level 3 260C 168 HR CROSTA no Sb Br R JUNI OR The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free ROHS Pb Free ROHS Exempt or Green RoHS amp no Sb Br please check http Awww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s t
14. Single 3 3 V Supply Operation Noise Filter on Incoming TPBIAS Low Cost 24 576 MHz Crystal Provides Extended Resume Signaling for Transmit Receive Data at 100 200 400 Compatibility With Legacy DV Devices and Mbits s and Link Layer Controller Clock at Terminal and Register Compatibility With 49 152 MHz TSB41LV01 Allow Direct Isochronous Low Cost High Performance 48 64 Pin Transmit to Legacy DV Devices With Any TQFP PHP PAP Thermally Enhanced Link Layer Even When Root Packages Increase Thermal Performance Power Down Features to Conserve Energy by up to 210 in Battery Powered Applications Include Meets Intel Mobile Power Guideline 2000 Automatic Device Power Down During Available in 80 Ball MicroStar Junior Suspend Device Power Down Terminal BGA GQE Package Link Interface Disable via LPS and Inactive 4 Ports Powered Down Available in 64 Ball Pb Free MicroStar Junior BGA ZQE Package Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet t Implements technology covered by one or more patents of Apple Computer Incorporated and SGS Thompson Limited FireWire is a trademark of Apple Computer Incorporated i LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation Intel is a trademark of Intel Corporation Other
15. TEXAS 75265 31 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION designing with the PowerPad package continued Other requirements for thermal lands and thermal vias are detailed in the PowerPAD Thermally Enhanced Package technical brief TI literature number SLMAO02 available via the Web pages beginning at URL http www ti com Figure 17 Example of a Thermal Land for the TSB41AB1PAP PHY For the TSB41AB1 this thermal land should be grounded to the low impedance ground plane of the device This improves not only thermal performance but also the electrical grounding of the device It is also recommended that the device ground terminal landing pads be connected directly to the grounded thermal land The land size should be as large as possible without shorting device signal terminals The thermal land may be soldered to the exposed PowerPAD using standard reflow soldering techniques While the thermal land may be electrically floated and configured to remove heat to an external heat sink it is recommended that the thermal land be connected to the low impedance ground plane for the device More information be obtained from the application report Recommendations for PHY Layout literature number SLLAO20 internal register configuration There are 16 accessible internal registers i
16. between the and XO terminals to provide the reference for an internal oscillator circuit This oscillator in turn drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data at the S100 through S400 media data rates A variation of less than 100 ppm from nominal for the media data rates is required by IEEE Std 1394 1995 Adjacent PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks and PHYs must be able to compensate for this difference over the maximum packet length Larger clock variations may cause resynchronization overflows or underflows resulting in corrupted packet data For the TSB41AB1 the SYSCLK output may be used to measure the frequency accuracy and stability of the internal oscillator and PLL from which it is derived The frequency of the SYSCLK output must be within 100 ppm of the nominal frequency of 49 152 MHz 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 29 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION crystal selection continued The following are some typical specifications for crystals used with the physical layers from TI in order to achieve the required frequency accuracy and stability Crystal mode of operation Fundamental Frequency toleranc
17. continued The PHY may initiate a status transfer either autonomously or in response to a register read request from the LLC The PHY initiates a receive operation whenever a packet is received from the serial bus The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the LLC The transmit operation is initiated when the PHY grants control of the interface to the LLC The encoding of the CTLO CTL1 bus is shown in Table 10 and Table 11 Table 10 CTL Encoding When PHY Has Control of the Bus crLo crL1 NAME DESCRIPTION o o de No activity this is the default mode o 1 Status Status information is being sent from the PHY to the LLC 1 0 Receive An incoming packet is being sent from the PHY to the LLC The LLC has been given control of the bus to send an outgoing packet Table 11 CTL Encoding When LLC Has Control of the Bus Ceno oni name 0 de The LLC releases the bus transmission has been completed An outgoing packet is being sent from the LLC to the PHY output differentiation 1 Hold The LLC is holding the bus while data is being prepared for transmission or indicating that another packet is to be transmitted concatenated without arbitrating i o When an Annex J type isolation barrier is implemented between the PHY and LLC the CTLO CTL1 00 07 and LREQ signals must be digitally differentiate
18. each were appropriate for the layout of that particular board The load specified for the crystal includes the load capacitors C9 C10 the loading of the PHY terminals and the loading of the board itself C gpy The value of is typically about 1 pF and is typically 0 8 pF per centimeter of board etch a typical board can have 3 pF to 6 pF or more The load capacitors C9 and C10 combine as capacitors in series so that the total load capacitance is C9 x C10 C9 C10 0 C9 24 576 MHz C PHY C BD Tt m C10 Figure 15 Load Capacitance for the TSB41AB1 PHY 30 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION crystal selection continued The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency minimizing noise introduced into the PHYs phase lock loop and minimizing any emissions from the circuit The crystal and two load capacitors should be considered as a unit during layout The crystal and load capacitors should be placed as close as possible to one another while minimizing the loop area created by the combination of the three components Varying the size of the ca
19. either the LPS input is inactive or the LCtrl register bit is cleared to 0 LLC request input The LLC uses this input to initiate a service request to the TSB41AB1 Bus holder is built into this terminal 48 5 INSTRUMENTS 12 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 Terminal Functions Continued MEL TYPE DESCRIPTION USE Each of these terminals is not connected to the silicon device Supply Each of these terminals is not connected to the silicon device but they are connected to each other It is recommended this group of terminals be used for a via connection to the GND plane in application board Supply Each of these terminals is not connected to the silicon device but they are connected to each other It is recommended this group of terminals be used for a via connection to the Vpp supply plane in application board F4 Supply Each of these terminals is not connected to the silicon device but they F5 are connected to each other It is recommended this group of terminals H3 be used for a via connection to the GND plane in application board Supply Each of these terminals are not connected to the silicon device but they are connected to each other It is recommended this group of terminals be used for a via connection to the Vpp supply plane in appli
20. maintaining a port to port connection between bus segments While in the suspended state a port is unable to transmit or receive data transaction packets However a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBIAS When the port of the TSB41AB1 is suspended all circuits except the band gap reference generator and bias detection circuit is powered down resulting in significant power savings For additional details of suspend resume operation see IEEE 1394a 2000 The use of suspend resume is recommended for new designs The port transmitter and receiver circuitry is disabled during power down when the PD input terminal is asserted high during reset when the RESET input terminal is asserted low when no active cable is connected to the port or when controlled by the internal arbitration logic The TPBIAS output is disabled during power down during reset or when the port is disabled as commanded by the LLC The cable not active CNA output terminal 64 terminal PAP package only is asserted high when there are no twisted pair cable ports receiving incoming bias that is they are either disconnected or suspended and can be used along with LPS to determine when to power down the TSB41AB1 The CNA output is not debounced When the PD terminal is asserted high the CNA detection circuitry is enabled regardless of the previous state of the ports and a pulldown is activated on the RESET t
21. more than 8 bits is received ACK packets exactly 8 data bits null packets no data bits and malformed packets less than 8 data bits do not clear fair and priority requests If 0 then fair and priority requests are cleared when any non ACK packet is received including null packets or malformed packets of less than 8 bits This bit is cleared to 0 by hardware reset and is unaffected by bus reset Link speed This field indicates the top speed capability of the attached LLC Encoding is as follows Code Speed 00 100 01 200 10 5400 11 illegal This field is replicated in the sp field of the self ID packet to indicate the speed capability of the node PHY and LLC in combination However this field does not affect the PHY speed capability indicated to peer PHYs during self ID the TSB41AB1 PHY identifies itself as S400 capable to its peers regardless of the value in this field This field is set to 10b S400 by hardware reset and is unaffected by bus reset Software hard reset Writing a 1 to this bit forces a hard reset of the PHY just as momentarily asserting the RESET terminal low This bit is always read as a 0 power class programming The 2 terminals are programmed to set the default value of the power class indicated in the pwr field bits 21 23 of the transmitted self ID packet Descriptions of the various power classes are given in Table 9 The default power class value is loaded following a hardware reset but
22. register set implemented Number of ports This field indicates the number of ports implemented in the PHY For the TSB41AB1 this field is 1 PHY_Speed Rd PHY speed capability For the TSB41AB1 PHY this field is 010b indicating S400 speed capability PHY repeater data delay This field indicates the worst case repeater data delay of the PHY expressed as 144 Delay 20 ns For the TSB41AB1 this field is 0 Link active status control This bit is used to control the active status of the LLC as indicated during self ID The logical AND of this bit and the LPS active status is replicated in the L field bit 9 of the self ID packet The LLC is considered active only if the LPS input is active and the LCtrl bit is set The LCtrl bit provides a software controllable means to indicate the LLC active status in lieu of using the LPS input The LCtrl bit is set to 1 by hardware reset and is unaffected by bus reset NOTE The state of the PHY LLC interface is controlled solely by the LPS input regardless of the state of the bit If the PHY LLC interface is operational as determined by the LPS input being active then received packets and status information continue to be presented on the interface and any requests indicated on the LREQ input are processed even if the LCtrl bit is cleared to 0 Contender status This bit indicates that this node is a contender for the bus or isochronous resource manager Th
23. the node to node communication paths between every pair of nodes in the network 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 39 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION using the TSB41AB1 with a lower speed link layer continued In the case of a node consisting of a higher speed PHY and a lower speed LLC the speed capability of the node PHY and LLC in combination is that of the lower speed LLC A sophisticated bus manager may be able to determine the LLC speed capability by reading the configuration ROM Bus Info Block or by sending asynchronous request packets at different speeds to the node and checking for an acknowledge the speed map may then be adjusted accordingly The speed map should reflect that communication to such a node must be done at the lower speed of the LLC instead of the higher speed of the PHY However speed map entries for paths that merely pass through the node PHY but do not terminate at that node should not be restricted by the lower speed of the LLC To assist in building an accurate speed map the TSB41AB1 can indicate a speed capability other than S400 in its transmitted self ID packet This is controlled by the Link Speed field in register 8 of the vendor dependent page page 7 Setting the Link Speed field affects only the speed indica
24. the IEEE 1394 1995 Serial Bus literature number SLLAO11 Link power status input This terminal monitors the active power status of the link layer controller and controls the state of the PHY LLC interface This terminal should be connected through a 10 kQ resistor either to the Vpp supplying the LLC or to a pulsed output which is active when the LLC is powered see Figure 13 A pulsed signal should be used when an isolation barrier exists between the LLC and PHY see Figure 14 The LPS input is considered inactive if it is sampled low by the PHY for more than 2 6 us 128 SYSCLK cycles and is considered active otherwise that is asserted steady high or an oscillating signal with a low time less than 2 6 us The LPS input must be high for at least 21 ns to assure that a high is observed by the PHY When the TSB41AB1 detects that LPS is inactive it places the PHY LLC interface into a low power reset state In the reset state the CTL and D outputs are held in the logic zero state and the LREQ input is ignored however the SYSCLK output remains active If the LPS input remains low for more than 26 us 1280 SYSCLK cycles the PHY LLC interface is put into a low power disabled state in which the SYSCLK output is also held inactive The PHY LLC interface is placed into the disabled state upon hardware reset The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1 and is considered inactive if
25. trademarks are the property of their respective owners MicroStar Junior is a trademark of Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date Copyright 2000 2004 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments Froduenon processing does not necessarily include 48 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 1 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5054231 JUNE 2000 REVISED MARCH 2005 description The TSB41AB1 provides the digital and analog transceiver functions needed to implement a one port node in a cable based IEEE 1394 network The cable port incorporates one differential line transceiver The transceiver includes circuitry to monitor the line conditions as needed for determining connection status for initialization and arbitration and for packet reception and transmission TSB41AB1 is designed to interface with a link layer controller LLC such as the TSB12LV21 TSB12LV22 TSB12LV23 TSB12LV26 TSB12LV31 TSB12LV41 TSB12LV42 or 121 0 The TSB41AB1 requires only an external 24 576 MHz crystal as a reference An external clock may be provided instead of a crystal An internal oscillator drives an internal phase locked loop PLL which generates the required 393 216 MHz reference signal This referenc
26. waiting the required minimum packet separation time and then asserting grant as before This function may be used to send a unified response after sending an acknowledge or to send consecutive isochronous packets during a single isochronous period Unless multispeed concatenation is enabled all packets transmitted during a single bus ownership must be of the same speed since the speed of the packet is set before the first packet If multispeed concatenation is enabled when the EMSC bit of PHY register 5 is set the LLC must specify the speed code of the next concatenated packet on the D terminals when it asserts hold on the CTL terminals at the end of a packet The encoding for this speed code is the same as the speed code that precedes received packet data as given in Table 20 50 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION transmit continued After sending the last packet for the current bus ownership the LLC releases the bus by asserting idle on the CTL terminals for two clock cycles The PHY begins asserting idle on the CTL terminals one clock after sampling idle from the link Note that whenever the D and CTL terminals change direction between the PHY and the LLC there is an extra clock period allowed so that both sides o
27. 00 L Link Controls CTL and D PHY CTL D Outputs High Impedance Figure 26 Cancelled Null Packet Transmission Timing The sequence of events for a cancelled null packet transmission is as follows 1 Transmit operation initiated PHY asserts grant on the CTL lines followed by idle to hand over control of the interface to the link Optional idle cycle The link may assert at most one idle cycle preceding assertion of hold This idle cycle is optional the link is not required to assert idle preceding hold Optional hold cycles The link may assert hold for up to 47 cycles preceding assertion of idle These hold cycle s are optional the link is not required to assert hold preceding idle Null transmit termination The null transmit operation is terminated by the link asserting two cycles of idle on the CTL lines and then releasing the interface and returning control to the PHY Note that the link may assert idle for a total of three consecutive cycles if it asserts the optional first idle cycle but does not assert hold It is recommended that the link assert three cycles of idle to cancel a packet transmission if no hold cycles are asserted This assures that either the link or PHY controls the interface in all cycles After regaining control of the interface the PHY asserts at least one idle cycle before any subsequent status transfer receive operation or transmit operation interface reset and disable The LLC contr
28. 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION LLC service request continued For a read register request the length of the LREQ bit stream is 9 bits as shown in Table 16 Table 16 Read Register Request Indicates the beginning of the transfer always 1 Request type A 100 indicating this is a read register request Identifies the address of the PHY register to be read 8 Stop bit Indicates the end of the transfer always 0 For a write register request the length of the LREQ bit stream is 17 bits as shown in Table 17 Table 17 Write Register Request rams ww Escmeno Treats the begining ofthe transfer aways For an acceleration control request the length of the LREQ bit stream is 6 bits as shown in Table 18 Table 18 Acceleration Control Request 5 DESCRIPTION 0 Startbit Indicates the beginning of the transfer always 1 Request type A 110 indicating this is an acceleration control request Asynchronous period arbitration acceleration is enabled if 1 and disabled if 0 Stop bit Indicates the end of the transfer always 0 For fair or priority access the LLC sends the bus request FairReq or PriReq at least one clock after the PHY LLC interface becomes idle If the CTL terminals are asserted receive 10b by the PHY then any pending fair or priority request is lost cleared Additionally
29. 22 hS 21 Power Class 12 pri 20 Programming 12 pF VDD 49 LKON T e C LKON Bus Manager 0 001 uF 10 sk DGND 18 u penn CNA OUT t See Figure 10 Figure 11 and Figure 12 POWER DOWN See Figure 13 and Figure 14 5 See Terminal Functions Table 41 See crystal selection section for more details Figure 4 External Component Connections PAP 49 5 INSTRUMENTS 22 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION component connection continued 0 1 0 001 0 001 4 Cables Interface Connection t 6 34 1 RESET 4 1 Optional p FILTERO 1 V FILTER1 L 0 001 0 001 10 1 10 001 uF TD M Lu Tag PLLGND Cable Power l DGND 5 41 1 12 poor 94576 MHz Power Class 12 pF Programming T vpp LKON 4101 C LKON Bus Manager 4 DGND LPS T See Figure 10 Figure 11 and Figure 12 See Figure 13 and Figure 14 See Terminal Functions Table z 2 o a oc o 4 See crystal selection section for more details Figure 5 External Component Conn
30. 3 DALLAS TEXAS 75265 17 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 electrical characteristics over recommended ranges of operating conditions unless otherwise noted continued device Vpp 3 3 V TA 25 C IDD ULP Supply current ultralow power mode Port disabled or unconnected 150 PD OV LPS 0 IDD PD Supply current power down mode 3 3 V 150 V TH Power status threshold CPS inputt 400 kQ resistort 4 7 7 5 High level output voltage CTLO CTL1 27 4 OH 00 07 CNA C LKON SYSCLK outputs Vpp 3t03 6 V lou 4 mA Low level output voltage CTLO CTL1 _ VOL 00 07 CNA C LKON SYSCLK outputs OL 4 04 y High level Annex J output voltage CTLO Annex J log 9 mA VOH AJ CTL1 00 07 C LKON SYSCLK outputs 50 04 Vpp23V Y V Low level Annex J output voltage CTLO Annex J loj 9 mA 04 V OL AJ CTL1 D0 D7 C LKON SYSCLK outputs ISO 0V Vpp23V Positive peak bus holder current 00 07 ISO 3 6 V Vpp 3 6 V BH CTLO CTL1 LREQ Vi 0 V to VDD 0 05 mn Negative peak bus holder current 150 3 6 Vpp 3 6V BH 00 07 CTLO CTL1 LREQ Vi 0 V to VDD ies 808 ma Input current LREQ LPS PD TESTM VA SM 2 inputs i 5 Tn Off state output current CTLO CTL1 laRST Pullup current RES
31. 41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION component connection continued GQE package terminal diagram TOP VIEW a 2 an On Zo gt 280 29 30 oF 926 TPB C LKON TPB LPS TPA D7 PD TPA D5 D6 TPBIAS D4 RO D3 AGND D2 AVDD D1 R1 DO CTL1 AGND CTLO AGND SYSCLK au 82 2 2 28 359 20 38 9 g 54 t ad Add zi a 4 NOTE NC connected Figure 7 Recommended Application Board Layout for GQE Package 40 EXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 25 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION component connection continued 26 6 34k VDD TP Cables p 0 001 _L0 001 Interface Connections t E 2 LKON Bus Manager C LKON 10k Ed o a a a 38181 81 21 8 4 4 4 4 222 4804 B E B 8 B D E F G H J de 2 C162 e207 OS ee 0 1 uF RESET 01uF FILTERO 8 LJ C C C 9 AGND 0 001 0 1 uF VDD FILTER1 AVDD PLLVDD 7 C 5 Optional VDD HF pLLGND SE 1 1 O eee uF uF XI DVDD ud T MH Cable Power BOO eee ofe 12 4 ASO
32. 9 and the timing is shown in Figure 22 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 47 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION status transfer continued Table 19 Status Bits rams 02 00 S Arbitration reset gap Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time as defined in IEEE Std 1394 1995 This bit is used by the LLC in the busy retry state machine 1 Subaction gap Indicates that the PHY has detected that the bus has been idle for a subaction gap time as defined in IEEE Std 1394 1995 This bit is used by the LLC to detect the completion of an isochronous cycle Indicates that the PHY has entered the bus reset start state 3 Indicates that a PHY interrupt event has occurred An interrupt event may be a configuration time out cable power voltage falling too low a state time out or a port status change This field holds the address of the PHY register whose contents are being transferred to the LLC 8 15 This field holds the register contents SYSCLK 1 2 CTLO CTL1 00 01 om Km Kemet Xo DO D1 00 S 0 1 00 0 0 1 LLL Figure 22 Status Transfer Timing The sequence of events for a status transfer is as follows 1 Status transfer init
33. EEE 1394a 2000 compliant and therefore both the reception and transmission of PHY config packets cause the RHB and gap count to be loaded unlike older IEEE Std 1394 1995 compliant PHYs which decode only received PHY config packets The gap count is set to the maximum value of 63 after two consecutive bus resets without an intervening write to the gap count either by a write to PHY register 1 or by a PHY config packet This mechanism allows a PHY config packet to be transmitted and then a bus reset initiated to verify that all nodes on the bus have updated their RHBs and gap count values without having the gap count set back to 63 by the bus reset The subsequent connection of a new node to the bus which initiates a bus reset then causes the gap count of each node to be set to 63 Note however that if a subsequent bus reset is instead initiated by a write to register 1 to set the IBR bit all other nodes on the bus have their gap count values set to 63 while the gap count of this node remains set to the value just loaded by the write to PHY register 1 Therefore in order to maintain consistent gap counts throughout the bus the following rules apply to the use of the IBR bit RHB and gap count in PHY register 1 Following the transmission of a PHY config packet a bus reset must be initiated in order to verify that all nodes have correctly updated their RHBs and gap count values and to ensure that a subsequent new connection to the bus cau
34. ET input Vj 1 5Vor0V lt 5 Pullup pulldown current SE input VI Vpp 2 or Positive input threshold voltage LREQ ica z CTLO CTL1 00 07 inputs ISO 0V Vpp 3Vto3 6V Vpp 2 0 3 V IT Positive input threshold voltage LPS ISO 0V Vpp 3Vto3 6V inputs Vret 0 4 Negative input threshold voltage LREQ _ CTLO CTL1 00 07 inputs ISO 0V Vpp 3Vto3 6V Vpp 2 0 9 Vpp 2 0 3 V Negative input threshold voltage LPS ISO 0 V Vref 0 4 Veat 0 2 inputs Vpp 23 V to 3 6 V reff Vo TPBIAS output voltage At rated l current t Measured at cable power side of resistor This parameter applicable only when ISO low TPBIAS is typically Vpp 0 2 V when the port is not connected NOTES 2 Transmit maximum packet one port transmitting maximum size isochronous packet 4096 bytes sent on every isochronous interval 5400 data value of CCCCCCCCh Vpp 3 3 V TA 25 3 Receive typical packet one port receiving DV packets on every isochronous interval S100 Vpp 3 3 V TA 25 C 4 Idle one port transmitting cycle starts Vpp 3 3 V TA 25 C 49 5 INSTRUMENTS 18 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 thermal characteristics PAP package PARAMETER TEST CONDITIONST ReJA Junction to ambient
35. Figure 1 Test Load Diagram SYSCLK Dx CTLx Figure 2 Dx CTLx LREQ Input Setup and Hold Time Waveforms SYSCLK 22 Dx CTLx X Figure 3 Dx and CTLx Output Delay Relative to SYSCLK Waveforms 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 21 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION component connection Details regarding connection of components to the various terminals of the TSB41AB1 are discussed primarily in entries for each terminal in the terminal functions table Figure 4 Figure 5 Figure 6 and Figure 8 are diagrammatic views showing the connections for all required external components Note All component connection diagrams are top view 6 34 1 L 0 001 L 0 001 TP Cables i Tu Pur Tp Interface VDD O Connection t 5 E AGND e Lo T 0 001 1 0 001 AGND 31 0 001 uF 0 1 uF pF HF uF 30 0 001 uF Vpp VDD 29 AV 0 1 uF DD og 1 Optional 6 RESET s FILTERO 27 ANY t aa 0 1 uF L 0 001 0 001 Lo 1 u 26 gt Vpp 5 DGND 21101 0 01 uF TSB41AB1 400 KO TF PLLGND Cable Power 23 PLLGND ISO
36. HY uses the C LKON terminal to notify the LLC to power up and become active When activated the C LKON signal is a square wave of approximately 163 ns period The PHY activates the C LKON output when the LLC is inactive and a wake up event occurs The LLC is considered inactive when either the LPS input is inactive as described above or the L Ctrl bit is cleared to 0 A wake up event occurs when a link on PHY packet addressed to this node is received or when a PHY interrupt occurs The PHY deasserts the C LKON output when the LLC becomes active both LPS active and the LCtrl bit set to 1 The PHY also deasserts the C LKON output when a bus reset occurs unless a PHY interrupt condition exists which would otherwise cause C LKON to be active PHP package terminal diagram PHP PACKAGE TOP VIEW 9 QF Fj Om 00 0 1104 1 LLL LL tC SYSCLK 1 36 AGND CTLO 35 CTL1 3 34 R1 114 RO D1 5 32 AGND D2 e 31 TPBIAS D3 81 1 30 TPA 04118 29 05 28 TPB D6 10 27 TPB 071111 26 AGND PD 12 25 NOTE A For latch up considerations it is recommended that the TESTM terminal have a pullup resistor 49 5 INSTRUMENTS 4 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 O
37. LLC data sheets The following paragraphs describe the operation of the PHY LLC interface The interface to the LLC consists of the SYSCLK CTLO CTL1 00 07 LREQ LPS C LKON and ISO terminals on the TSB41AB1 as shown in Figure 18 Link TSB41AB1 Layer Controller SYSCLK CTLO CTL1 D1 D7 LREQ LPS C LKON 150 Figure 18 PHY LLC Interface The SYSCLK terminal provides a 49 152 MHz interface clock All control and data signals are synchronized to and sampled on the rising edge of SYSCLK The CTLO and CTL1 terminals form a bidirectional control bus which controls the flow of information and data between the TSB41AB1 and LLC The 00 07 terminals form a bidirectional data bus which is used to transfer status information control information or packet data between the devices The TSB41AB1 supports S100 S200 and 5400 data transfers over the DO D7 data bus In S100 operation only the DO and D1 terminals are used S200 operation only the 00 03 terminals are used and S400 operation all DO D7 terminals are used for data transfer When the TSB41AB1 is in control of the DO D7 bus unused Dn terminals are driven low during S100 and S200 operations When the LLC is in control of the DO D7 bus unused Dn terminals are ignored by the TSB41AB1 The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access to the serial bus for packet transmission read or w
38. MARCH 2005 eee APPLICATION INFORMATION component connection continued Outer Shield Termination TSB41AB1 TPBIAS 56 ot TPA TPA Y ov Cable Port s 220pFt 5 kQ T The IEEE Std 1394 1995 calls for a 250 pF capacitor which is a nonstandard component value A 220 pF capacitor is recommended t 0 596 to meet 1394 1995 specification Figure 10 TP Cable Connections Outer Cable Shield 0 01 uF 0 001 uF e Chassis GND Figure 11 Compliant DC Isolated Outer Shield Termination 49 5 INSTRUMENTS 28 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION component connection continued Outer Shield Termination Chassis GND Figure 12 Nonisolated Outer Shield Termination 10 kQ Link Power LPS Square Wave Input LPS Figure 13 Nonisolated Circuit Connection Variations for LPS PHY Vpp 13 7 kQ Square Wave Signal LPS 0 033 uF 10 PHY GND NOTE As long as the resistance ratio is maintained between 1 61 1 and 1 33 1 any values of resistors may be used Figure 14 Isolated Circuit Connection for LPS crystal selection The TSB41AB1 and other TI PHY devices are designed to use an external 24 576 MHz crystal connected
39. Maximum junction temperature Ty FA 31 9 C W 70 C see RgJA values listed in thermal RgJA 65 8 C W TA 70 C 5 characteristics table 48PHP 85 6 C W 70 993 3 see RgJA values listed in thermal characteristics table 80GQE RgJA 118 12 C W Ta 70 C 022 9 3 26 Maximum junction temperature Ty RgJA 58 32 C W TA 70 C 80 50 e Maximum junction temperature TJ RgJA 56 61 C W Ta 70 C 80 19 see RgJA values listed thermal characteristics table 64ZQE RgJA 119 63 C W 70 C 022 985 53 Cable inputs during data reception Differential input voltage V EMT 9 ID Cable inputs during arbitration TPB cable inputs source power node Common mode input voltage Vic TPB inputs nonsource power node TPA TPB cable inputs S100 operation Receive input jitter TPA TPB cable inputs S200 operation ns TPA TPB cable inputs S400 operation 0 315 Between TPA and TPB cable inputs S100 operation Receive input skew Between TPA and TPB cable inputs S200 operation ns Between TPA and TPB cable inputs S400 operation All typical values at Vpp 3 3 V and TA 25 C For a node that does not source power see Section 4 2 2 2 in IEEE 1394a 2000 48 5 INSTRUMENTS 16 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRA
40. NE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 PAP package terminal diagram PAP PACKAGE TOP VIEW a 2 A Q 4 id 2 Z m uaz 2 60 lt 2222 lt lt 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AGND 49 32 AGND AGND 50 AVpp AVpp 51 so Vpp AVpp 52 29 SM RESET 53 28 SE FILTERO 54 27 TESTM FILTER1 55 26 DVpp PLLVpp 56 25 DVpp PLLGND 57 24 CPS PLLGND 58 230 ISO 59 22 2 60 21 DVpp 61 201 PCO DVpp 162 19 C LKON DGND I 63 18 DGND DGND I 64 17 DGND 1234 5 6 7 8 9 1011 1213 14 15 16 8 LESSE UE LL ILI LI 0 e sx 1 0 OO gt 2 NOTES A Pin 16 could be tied to Vpp for backward compatibility with the TSB41LV02A device B Forlatch up considerations it is recommended that the TESTM terminal have a pullup resistor 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 GQE package terminal diagram NC connections top view GQE PACKAGE TERMINAL DIAGRAM TOP VIEW a a a a z a an On Zo o gt Q oo 40 a
41. NSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 electrical characteristics over recommended ranges of operating conditions unless otherwise noted driver PARAMETER TEST CONDITIONS MIN TYP MAX VOD Differential output voltage 56 See Figure 1 172 265 20 m m m mV Driver difference current TPA TPA TPB Drivers enabled speed 1 051 1 05t mA DIFF e erence current signaling off ed lt 200 mode speed signaling current TPB TPB S200 speed signaling enabled 4 84 2 53t mA 5 400 mode speed signaling current TPB TPB S400 speed signaling enabled 12 4t 8 1t mA V V OFF state differential voltage Drivers disabled See Figure 1 2 T Limits defined as algebraic sum of TPA and driver currents Limits also apply to TPB and algebraic sum of driver currents t Limits defined as absolute limit of each of TPB and TPB driver currents receiver PARAMETER TEST CONDITIONS M MAX UNIT Differential impedance Drivers disabled Common mode impedance Drivers disabled 2 5 Drivers disabled 30 30 Positive arbitration comparator threshold voltage Drivers disabled 5 common mode voltage V TH SP200 Speed signal threshold drivereidisabl d 57 20 m 14 396 mV TPBIAS TPA common mode voltage 49 5 INSTRUMENTS POST OFFICE BOX 65530
42. ON output to notify the LLC to service the interrupt State time out interrupt This bit indicates that a state time out has occurred which also causes a bus reset to occur This bit is reset to 0 by hardware reset or by writing a 1 to this register bit If the STOI and RPIE bits are both set and the LLC is or becomes inactive the PHY activates the C LKON output to notify the LLC to service the interrupt Port event interrupt This bit is set to 1 upon a change in the bias connected disabled or fault bits for any port for which the port interrupt enable PIE bit is set Additionally if the resuming port interrupt enable RPIE bit is set the PEI bit is set to 1 at the start of resume operations on the port This bit is reset to 0 by hardware reset or by writing a 1 to this register bit If the PEI bit is set regardless of the state of the RPEI bit and the LLC is or becomes inactive the PHY activates the C LKON output to notify the LLC to service the interrupt Enable accelerated arbitration This bit enables the PHY to perform the various arbitration acceleration enhancements defined in IEEE 1394a 2000 ACK accelerated arbitration asynchronous fly by concatenation and isochronous fly by concatenation This bit is reset to 0 by hardware reset and is unaffected by bus reset NOTE The EAA bit should be set only if the attached LLC is IEEE 1394a 2000 compliant If the LLC is not IEEE 1394a 2000 compliant use of the arbitration accel
43. PERATION LLC service request continued The LLC may make only one bus request at a time Once the LLC issues any request for bus access ImmReq IsoReq FairReq or PriReq it cannot issue another bus request until the PHY indicates that the bus request was lost bus arbitration lost and another packet received or won bus arbitration won and the LLC granted control The PHY ignores new bus requests while a previous bus request is pending All bus requests are cleared upon a bus reset For write register requests the PHY loads the specified data into the addressed register as soon as the request transfer is complete For read register requests the PHY returns the contents of the addressed register to the LLC at the next opportunity through a status transfer If a received packet interrupts the status transfer then the PHY continues to attempt the transfer of the requested register until it is successful A write or read register request may be made at any time including while a bus request is pending Once a read register request is made the PHY ignores further read register requests until the register contents are successfully transferred to the LLC A bus reset does not clear a pending read register request The TSB41AB1 includes several arbitration acceleration enhancements which allow the PHY to improve bus performance and throughput by reducing the number and length of interpacket gaps These enhancements include autonomous fly by iso
44. agram for normal packets and Figure 24 is the reception timing diagram for null packets 774 svscux Qo o ___ CTLO CTL1 E 1 10 1 00 00 3 00 5 00 07 1 FF Data On spo do A a 00 Figure 23 Normal Packet Reception Timing The sequence of events for a normal packet reception is as follows 1 Receive operation initiated The PHY indicates a receive operation by asserting receive on the CTL lines Normally the interface is idle until receive is asserted However the receive operation may interrupt a status transfer operation that is in progress so that the CTL lines may change from status to receive without an intervening idle 2 Data on indication The PHY asserts the data on indication code on the D lines for one or more cycles preceding the speed code 3 Speed code The PHY indicates the speed of the received packet by asserting a speed code on the D lines for one cycle immediately preceding packet data The link decodes the speed code on the first receive cycle for which the D lines are not the data on code If the speed code is invalid or indicates a speed higher than that which the link is capable of handling the link should ignore the subsequent data 4 Receive data Following the data on indication if any and the speed code the PHY asserts packet data on the D lines with receive on the CTL lines for the remainder of the receive operation 5 Receive
45. am and a stop bit of 0 is required at the end of the stream The second through fourth bits of the request stream indicate the type of the request In the descriptions below bit 0 is the most significant and is transmitted first in the request bit stream The LREQ terminal is normally low Encoding for the request type is shown in Table 13 Table 13 Request Type Encoding LRi LR3 NAME DESCRIPTION Immediate bus request Upon detection of idle the PHY takes control of the bus immediately without arbitration Priority bus request The PHY arbitrates for the bus after a subaction gap ignores the fair protocol For a bus request the length of the LREQ bit stream is 7 or 8 bits as shown in Table 14 Table 14 Bus Request sms nwe mdcsesWebegmsngohevanseridwae T O O O OoOo Indicates the end of the transfer always 0 If bit 6 is 0 this bit may be omitted The 3 bit request speed field used in bus requests is shown in Table 15 Table 15 Bus Request NOTE TSB41AB1 does accept a bus request with an invalid speed code and process the bus request normally However during packet transmission for such a request the TSB41AB1 ignores any data presented by the LLC and transmits a null packet 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 45 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a
46. ansfer The PHY may prematurely end a status transfer by asserting something other than status on the CTL terminals This occurs if a packet is received before the status transfer completes The PHY continues to attempt to complete the transfer until all status information has been successfully transmitted There is at least one idle cycle between consecutive status transfers The PHY normally sends just the first four bits of status to the LLC These bits are status flags that are needed by the LLC state machines The PHY sends an entire 16 bit status packet to the LLC after a read register request or when the PHY has pertinent information to send to the LLC or transaction layers The only defined condition where the PHY automatically sends a register to the LLC is after self ID where the PHY sends the physical ID register that contains the new node address All status transfers are either 4 or 16 bits unless interrupted by a received packet The status flags are considered to have been successfully transmitted to the LLC immediately upon being sent even if a received packet subsequently interrupts the status transfer Register contents are considered to have been successfully transmitted only when all 8 bits of the register have been sent A status transfer is retried after being interrupted only if any status flags remain to be sent or if a register transfer has not yet completed The definitions of the bits in the status transfer are shown in Table 1
47. ata information is transmitted differentially on the TPB cable pair and the encoded strobe information is transmitted differentially on the TPA cable pair During packet reception the TPA and TPB transmitters of the receiving cable port are disabled and the receivers for that port are enabled The encoded data information is received on the TPA cable pair and the encoded strobe information is received on the TPB cable pair The received data strobe information is decoded to recover the receive clock signal and the serial data bits The serial data bits are split into two four or eight bit parallel streams depending upon the indicated receive speed resynchronized to the local 49 152 MHz system clock and sent to the associated LLC Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration The outputs of these comparators are used by the internal logic to determine the arbitration status The TPA channel monitors the incoming cable common mode voltage The value of this common mode voltage is used during arbitration to set the speed of the next packet transmission In addition the TPB channel monitors the incoming cable common mode voltage on the TPB pair for the presence of the remotely supplied twisted pair bias voltage The TSB41AB1 provides 1 86 V nominal bias voltage at the TPBIAS terminal for port termination This bias voltage when seen through a cable b
48. ate Interface reset After T RESET time the PHY determines that LPS is inactive terminates any interface bus activity and places its CTL and D outputs into a high impedance state the PHY terminates any output signal activity such that signals end a logic 0 state The PHY LLC interface is now in the reset state Interface restored After the minimum TRESTORE time the LLC may again assert LPS active The minimum TRESTORE interval provides sufficient time for the biasing networks used in Annex J type isolation barrier circuits to stabilize and reach a quiescent state if the isolation barrier has somehow become unbalanced When LPS is asserted the interface is initialized high 1 3 SYSCLK e 0000000000 gt 0000000000 V 4 Ec TLPs RESET gt 4 RESTORE gt Figure 28 Interface Reset ISO High 54 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION interface reset and disable continued The sequence of events for resetting the PHY LLC interface when it is in the nondifferentiated mode of operation ISO terminal is high is as follows 1 Normal operation Interface is operating normally with LPS asserted SYSCLK active status and packet data recep
49. ating all bus and request activity When the PHY observes that LPS has been deasserted for it resets the interface When the interface is in the reset state the PHY sets its CTL and D outputs in the logic O state and ignores any activity on the LREQ signal The timing for interface reset is shown in Figure 27 and Figure 28 ISO low 1 3 OTA CTLO CTL1 LS 08 2 LPS TLPSL d lt TLPS_RESET gt 4 TRESTORE 5 Ti psH Figure 27 Interface Reset ISO Low 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 53 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION interface reset and disable continued The sequence of events for resetting the PHY LLC interface when it is in the differentiated mode of operation ISO terminal is low is as follows 1 Normal operation Interface is operating normally with LPS active SYSCLK active status and packet data reception and transmission via the CTL and D lines and request activity via the LREQ line LPS deasserted The LLC deasserts the LPS signal and within 1 us terminates any request or interface bus activity and places its LREQ CTL and D outputs into a high impedance state the LLC should terminate any output signal activity such that signals end a logic 0 st
50. be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMA002 for information regarding recommended board layout This document is available at www ti com lt http www ti com gt E Falls within JEDEC 5 026 PowerPAD is a trademark of Texas Instruments 48 5 INSTRUMENTS www ti com 48 5 INSTRUMENTS THERMA INFORMATION THERMAL PAD MECHANICAL DATA www ti com S PQFP G64 This PowerPAD package incorporates an exposed thermal pad that is designed to be attached directly to an external h the PCB can be used as a heatsink In addition through the use of attached can be a from the For additi integrated circuit IC directly to the appropriate copper plane shown in the electri tached to a special heatsink structure designed into the PC information on the PowerPAD package and how to ta abilities refer to Technical Brief PowerPAD Thermally Enhanced Pac SLMAO02 and Application Brief PowerPAD Made Both doc uments are available at www ti com Easy Texas Ins eatsink The thermal pad must be soldered directly to the printed circuit board PCB After soldering hermal vias the thermal pad can be cal schematic for the device or alternatively B This design optimizes the heat transfer e advantage of its heat dissipating age Texas Instruments Literature
51. between the TSB41AB1 and the LLC Bus holders are built into these terminals Digital circuit ground terminals These terminals should be tied together to the low impedance circuit board ground plane Digital circuit power terminals A combination of high frequency decoupling capacitors near each terminal is suggested such as paralleled 0 1 uF and 0 001 uF Lower frequency 10 uF filtering capacitors are also recommended These supply terminals are separated from PLLVpp and AVpp inside the device to provide noise isolation They should be tied at a low impedance point on the circuit board PLL filter terminals These terminals are connected to an external capacitor to form a lag lead filter required for stable operation of the internal frequency multiplier PLL running from the crystal oscillator A 0 1 uF 10 capacitor is the only external component required to complete this filter Link interface isolation control input This terminal controls the operation of output differentiation logic on the CTL and D terminals If an optional Annex J type isolation barrier is implemented between the TSB41AB1 and LLC the ISO terminal should be tied low to enable the differentiation logic If no isolation barrier is implemented direct connection or bus holder isolation is implemented the 150 terminal should be tied high through a pullup to disable the differentiation logic For additional information see the TI application note Galvanic Isolation of
52. bits is set that is the link on output is active due solely to the reception of a link on PHY packet NOTE If an interrupt condition exists which would otherwise cause the link on output to be activated if the LLC were inactive the link on output is activated when the LLC subsequently becomes inactive Cable not active output This terminal is asserted high when there is no incoming bias voltage CNA is not valid at intial power up until a device hard reset is performed Cable power status input This terminal is normally connected to cable power through a 400 kQ resistor This circuit drives an internal comparator that is used to detect the presence of cable power This terminal should be tied directly to DGND through a 1 kQ resistor if the application does not require it to be J5 used B1 CMOS I O Control I Os These bidirectional signals control communication between the C2 TSB41AB1 and the LLC Bus holders are built into these terminals 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 11 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 Terminal Functions Continued TERMINAL DGND 17 18 63 64 DVpp 25 26 2 ue 61 62 FILTERO 4 5 6 7 8 9 10 11 38 FILTER1 39 19 13 1 0 DESCRIPTION Data I Os These are bidirectional data signals
53. cation board J2 CMOS Power class programming inputs On hardware reset these inputs set the default value of the power class indicated during self ID Programming is done by tying these terminals high or low See Table 9 for encoding CMOS Power down input A high on this terminal turns off all internal circuitry except the cable active monitor circuits which control the CNA output 64 terminal PAP package only Asserting the PD input high also activates an internal pulldown on the RESET terminal to force a reset of the internal control logic PD is provided for legacy compatibility and is not recommended for power management in place of IEEE 1394a 2000 suspend resume LPS and C LKON features 6 5 6 Supply PLL circuit ground terminals These terminals should be tied together to B5 the low impedance circuit board ground plane PLL circuit power terminals A combination of high frequency decoupling capacitors near each terminal is suggested such as paralleled 0 1 uF and 0 001 uF Lower frequency 10 uF filtering capacitors are also recommended This supply terminal is separated from DVpp AVpp inside the device to provide noise isolation It should be tied at a low impedance point on the circuit board Current setting resistor terminals These terminals are connected through an external resistor to set the internal operating currents and cable driver output currents A resistance of 6 34 1 0 is required to meet t
54. chronous packet concatenation autonomous fair and priority packet concatenation onto acknowledge packets and accelerated fair and priority request arbitration following acknowledge packets The enhancements are enabled when the EAA bit in PHY register 5 is set The arbitration acceleration enhancements may interfere with the ability of the cycle master node to transmit the cycle start message under certain circumstances The acceleration control request is therefore provided to allow the LLC to temporarily enable or disable the arbitration acceleration enhancements of the TSB41AB1 during the asynchronous period The LLC typically disables the enhancements when its internal cycle counter rolls over indicating that a cycle start message is imminent and then reenables the enhancements when it receives a cycle start message The acceleration control request may be made at any time however and is immediately serviced by the PHY Additionally a bus reset or isochronous bus request causes the enhancements to be reenabled if the EAA bit is set status transfer A status transfer is initiated by the PHY when there is status information to be transferred to the LLC The PHY waits until the interface is idle before starting the transfer The transfer is initiated by the PHY asserting status 01b on the CTL terminals along with the first two bits of status information on the DO and D1 terminals The PHY maintains CTL status for the duration of the status tr
55. d so that the isolation circuits function correctly Digital differentiation is enabled on the TSB41AB1 when the ISO terminal is low The differentiation operates such that the output is driven either low or high for one clock period whenever the signal changes logic state but otherwise places the output in a high impedance state for as long as the signal logic state remains constant On input hysteresis buffers are used to convert the signal to the correct logic state when the signal is high impedance the biasing network of the Annex J type isolation circuit pulls the signal voltage level between the hysteresis thresholds of the input buffer so that the previous logic state is maintained The correspondence between the output logic state and the output signal level is shown in Figure 19 Logic State 0 1 1 00 0 1 0 0 Signal Level ie L H Z O Z Z H L 7 Figure 19 Signal Transformation for Digital Differentiation 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 43 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION output differentiation The TSB41AB1 implements differentiation circuitry functionally equivalent to that shown in Figure 20 on the bidirectional CTLO CTL1 and 00 07 terminals The TSB41AB1 also implements an input hysteresis buffer on the LREQ in
56. e C Customers should place a note on the circuit board fabrication drawing not to alter the center solder mask defined pad D This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMA002 51 004 and also the Product Data Sheets for specific thermal information via requirements and recommended board layout These documents are available at www ti com http www ti com Publication 7351 is recommended for alternate designs E Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release Customers should contact their board assembly site for stencil design recommendations Example stencil design based on 50 volumetric metal load solder paste Refer to 7525 for other stencil recommendations F Customers should contact their board fabrication site for solder mask tolerances between and around signal pads 35 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products a
57. e at 25 C Total frequency variation for the complete circuit is 100 ppm A crystal with 30 ppm frequency tolerance is recommended for adequate margin Frequency stability over temperature and age A crystal with 30 ppm frequency stability is recommended for adequate margin NOTE The total frequency variation must be kept below 100 ppm from nominal with some allowance for error introduced by board and device variations Trade offs between frequency tolerance and stability may be made as long as the total frequency variation is less than 100 ppm For example the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible variation due to the crystal alone Crystal aging also contributes to the frequency variation Load capacitance For parallel resonant mode crystal circuits the frequency of oscillation is dependent upon the load capacitance specified for the crystal Total load capacitance is a function not only of the discrete load capacitors but also of the board layout and circuit It may be necessary to select discrete load capacitors iteratively until the SYSCLK output is within specification It is recommended that load capacitors with a maximum of 5 tolerance be used As an example for the OHCI 41AB1 evaluation module EVM which uses a crystal specified for 12 pF loading load capacitors C9 and C10 in Figure 15 of 16 pF
58. e signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information A 49 152 MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data The power down PD function when enabled by asserting the PD terminal high stops operation of the PLL The TSB41AB1 supports an optional isolation barrier between itself and its LLC When the ISO input terminal is tied high the LLC interface outputs behave normally When the ISO terminal is tied low internal differentiating logic is enabled and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394 1995 and in IEEE 1394a 2000 section 5 9 4 hereinafter referred to as Annex J type isolation To operate with TI bus holder isolation the ISO terminal on the PHY must be high Data bits to be transmitted through the cable port are received from the LLC on two four or eight parallel paths depending on the requested transmission speed and are latched internally in the TSB41AB1 in synchronization with the 49 152 MHz system clock These bits are combined serially encoded and transmitted at 98 304 196 608 or 393 216 Mbits s referred to as S100 S200 and S400 speeds respectively as the outbound data strobe information stream During transmission the encoded d
59. ections PHP 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 23 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION component connection continued 12 pF VDD 0 1 uF 6 34 k VDD 0 1 0 001 0 001 uF uF T uF a alia a a 816 Sle lt ajaj lt B 801010 0 1 uF RESET o1 uF FiLTERO 8 LJ C C FILTER1 7 BLLGND DVDD LREQ SYSCLK CTLO T See Figure 10 Figure 11 and Figure 12 See Figure 13 and Figure 14 See Terminal Functions Table ww O XI 24 576 MHz 12 0 001 DGND uF D CTL1 CNA OUT 4 See crystal selection section for more details 24 O O0 060 0 O O TP Cables Interface Connections t TPBIAS TPA TPB OQo 000000 07 0000 0 O 9 Oz POWER DOWN TPB O 0 001 0 001 0 1 AGND 2907 AVDD SM Optional 0 001 0 001 uF uF Cable Power NSO Power Class 1 Programming LKON 400 k Bus Manager C LKON 10k Figure 6 External Component Connections GQE 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB
60. ents to the Annex J interface that must be comprehended when using the TSB41AB1 with a non IEEE 1394a 2000 LLC device Anew LLC service request was added which allows the LLC to enable and disable asynchronous arbitration accelerations temporarily If the LLC does not implement this new service request the arbitration enhancements should not be enabled see the EAA bit in PHY register 5 The capability to perform multispeed concatenation the concatenation of packets of differing speeds was added in order to improve bus efficiency primarily during isochronous transmission If the LLC does not support multispeed concatenation multispeed concatenation should not be enabled in the PHY see the EMC bit in PHY register 5 In order to accommodate the higher transmission speeds expected in future revisions of the standard IEEE 1394a 2000 extended the speed code in bus requests from 2 bits to 3 bits increasing the length of the bus request from 7 bits to 8 bits The new speed codes were carefully selected so that new IEEE 1394a 2000 PHY and LLC devices would be compatible for speeds from S100 to S400 with legacy PHY and LLC devices that use the 2 bit speed codes The TSB41AB1 correctly interprets both 7 bit bus requests with 2 bit speed codes and 8 bit bus requests with 3 bit speed codes Moreover if a 7 bit bus request is immediately followed by another request for example a register read or write request the TSB41AB1 correctly int
61. eration enhancements may interfere with isochronous traffic by excessively delaying the transmission of cycle start packets Enable multispeed concatenated packets This bit enables the PHY to transmit concatenated packets of differing speeds in accordance with the protocols defined in IEEE 1394a 2000 This bit is reset to 0 by hardware reset and is unaffected by bus reset NOTE The use of multispeed concatenation is completely compatible with networks containing legacy IEEE Std 1394 1995 PHYs However use of multispeed concatenation requires that the attached LLC be IEEE 13942 2000 compliant Page Select 3 Rd Wr Page select This field selects the register page to use when accessing register addresses 8 through 15 This field is reset to 0 by hardware reset and is unaffected by bus reset Port Select 4 Rd Wr Port select This field selects the port when accessing per port status or control for example when one of the port status control registers is accessed in page 0 Ports are numbered starting at O This field is reset to 0 by hardware reset and is unaffected by bus reset 49 5 INSTRUMENTS 34 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION internal register configuration continued The port status page provides access to configuration and s
62. erface reset After RESET time the PHY determines that LPS is inactive terminates any interface bus activity and drives its CTL and D outputs low The PHY LLC interface is now in the reset state 4 Interface disabled If the LPS signal remains inactive for piSABLeE time the PHY terminates SYSCLK activity by driving the SYSCLK output low The PHY LLC interface is now in the disabled state After the interface has been reset or reset and then disabled the interface is initialized and restored to normal operation when LPS is reasserted by the LLC The timing for interface initialization is shown in Figure 31 and Figure 32 ISO 7 Cycles 5 3 y 14 5 Min 10 ns 2 4 D0 D7 4 TCLK ACTIVE Figure 31 Interface Initialization ISO Low 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 57 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION interface reset and disable continued The sequence of events for initialization of the PHY LLC interface when the interface is in the differentiated mode of operation ISO terminal is low is as follows 1 LPS reasserted After the interface has been in the reset or disabled state for at least the minimum time the LLC causes the int
63. erface to be initialized and restored to normal operation by reactivating the LPS signal In Figure 31 the interface is shown in the disabled state with SYSCLK high impedance inactive However the interface initialization sequence described here is also executed if the interface is merely reset but not yet disabled SYSCLK activated If the interface is disabled the PHY reactivates its SYSCLK output when it detects that LPS has been reasserted If the PHY has entered a low power state it takes between 5 3 ms to 7 3 ms for SYSCLK to be restored if the PHY is not in a low power state SYSCLK is restored within 60 ns The PHY commences SYSCLK activity by driving the SYSCLK output low for half a cycle Thereafter the SYSCLK output is a 50 duty cycle square wave with a frequency of 49 152 MHz 100 ppm period of 20 345 ns Upon the first full cycle of SYSCLK the PHY drives the CTL and D terminals low for one cycle The LLC is also required to drive its CTL D and LREQ outputs low during one of the first six cycles of SYSCLK this is shown in Figure 31 as occurring in the first SYSCLK cycle Receive indicated Upon the eighth SYSCLK cycle following reassertion of LPS the PHY asserts the receive state on the CTL lines and the data on indication all ones on the D lines for one or more cycles because the interface is in the differentiated mode of operation the CTL and D lines are in the high impedance state after the first cycle Initialization co
64. erminal so as to force a reset of the TSB41AB1 internal logic The LPS link power status terminal works with the C LKON terminal to manage the power usage in the node The LPS signal from the LLC is used in conjunction with the L Ctrl bit see Table 1 and Table 2 in the Application Information section to indicate the active power status of the LLC The LPS signal is also used to reset disable and initialize the PHY LLC interface the state of the PHY LLC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit The LPS input is considered inactive if it remains low for more than 2 6 us and is considered active otherwise When the TSB41AB1 detects that LPS is inactive it places the PHY LLC interface into a low power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored however the SYSCLK output remains active If the LPS input remains low for more than 26 us the PHY LLC interface is put into a low power disabled state in which the SYSCLK output is also held inactive The PHY LLC interface is also held the disabled state during hardware reset The TSB41AB1 continues the necessary repeater functions 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 50184231 JUNE 2000 REVISED MARCH 2005 description continued
65. erms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties has taken and continues to take reasonable steps to provide representative and accurate informati
66. erprets both requests Although the TSB41AB1 correctly interprets 8 bit bus requests a request with a speed code exceeding S400 results in the TSB41AB1 transmitting a null packet data prefix followed by data end with no data in the packet More explanation is included in the TI application note IEEE 1394a Features Supported by TI TSB41LVOX Physical Layer Devices literature number 511 019 using the TSB41AB1 with a lower speed link layer Although the TSB41AB1 is an S400 capable PHY it be used with lower speed LLCs such as the S200 capable TSB12LV31 In such a case the LLC has fewer data terminals than the PHY and some Dn terminals on the TSB41AB1 remain unused Unused Dn terminals should be pulled to ground through 10 resistors The TSB41AB1 transfers all received packet data to the LLC even if the speed of the packet exceeds the capability of the LLC to accept it Some lower speed LLC designs do not properly ignore packet data in such cases On the rare occasions that the first 16 bits of partial data accepted by such an LLC match the bus ID and node ID for that node spurious header CRC or tcode errors may result During bus initialization following a bus reset each PHY transmits a self ID packet that indicates among other information the speed capability of the PHY The bus manager if one exists builds a speed map from the collected self ID packets This speed map gives the highest possible speed that can be used on
67. ezoidal walls and also rounding corners will offer better paste release Customers should contact their board assembly site for stencil design recommendations Refer to IPC 7525 for stencil design considerations Customers should contact their board fabrication site for recommended solder mask tolerances and via tenting options for vias placed in the thermal pad 35 TEXAS INSTRUMENTS www ti com MECHANICAL DATA 5 80 PLASTIC BALL GRID ARRAY 4 00 TYP OOOO 6 00000 DOOOO gt 00 gt mn lt Or OO OUO 4 7 1 Bottom View 0 00 0 E Seating Plane 77 71 0 55 NINE 910 0 05 9 0 08 4200461 4 6 10 05 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice Falls within JEDEC 0 225 48 5 INSTRUMENTS www ti com MECHANICAL DATA PAP 5 064 PowerPAD PLASTIC QUAD FLATPACK Thermal Pad See Note D 0 13 NOM 4147702 C 08 03 NOTES All linear dimensions are in millimeters B This drawing is subject to change without notice C Body dimensions do not include mold flash or protrusion D This package is designed to
68. f CRC or any other data protection mechanisms 49 5 INSTRUMENTS 48 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION receive continued Table 20 Receive Speed Codes D0 D7 DATA RATE 00XX XXXX 5100 0100 5200 0101 0000 5400 NOTE X Output as 0 by PHY ignored by LLC Y Output as 1 by PHY ignored by LLC It is possible for the PHY to receive a null packet which consists of the data prefix state on the serial bus followed by the data end state without any packet data A null packet is transmitted whenever the packet speed exceeds the capability of the receiving PHY or whenever the LLC immediately releases the bus without transmitting any data In this case the PHY asserts receive on the CTL terminals with the data on indication all 1s on the D terminals followed by idle on the CTL terminals without any speed code or data being transferred In all cases the TSB41AB1 sends at least one data on indication before sending the speed code or terminating the receive operation The TSB41AB1 also transfers its own self ID packet transmitted during the self ID phase of bus initialization to the LLC This packet is transferred to the LLC just as any other received self ID packet Figure 23 is the reception timing di
69. f the interface can operate on registered versions of the interface signals Figure 25 is the transmission timing diagram for normal packets and Figure 26 is the transmission timing diagram for cancelled or null packets svscux L L E 1 1 L D0 D7 0 a Can 00 Link Controls CTL and D PHY CTL and D Outputs are High IMpedance NOTE SPD Speed code see Table 20 dO dn Packet data Figure 25 Normal Packet Transmission Timing The sequence of events for a normal packet transmission is as follows 1 Transmit operation initiated The PHY asserts grant on the CTL lines followed by idle to hand over control of the interface to the link so that the link may transmit a packet The PHY releases control of the interface that is it places its CTL and D outputs in a high impedance state following the idle cycle Optional idle cycle The link may assert at most one idle cycle preceding assertion of either hold or transmit This idle cycle is optional the link is not required to assert idle preceding either hold or transmit Optional hold cycles The link may assert hold for up to 47 cycles preceding assertion of transmit These hold cycle s are optional the link is not required to assert hold preceding transmit Transmit data When data is ready to be transmitted the link asserts transmit on the CTL lines along with the data on the D lines Transmit operation terminated The transm
70. gh time when pulsed t 0 021 26 TLPS DUTY LPS duty cycle when pulsed t 20 55 5 RESET Time for PHY to recognize LPS deasserted and reset the interface 26 2 68 TLPS_ DISABLE Time for PHY to recognize LPS deasserted and disable the interface 26 03 26 11 TRESTORE Time to permit optional isolation circuits to restore during an interface reset 15 238 T Time for SYSCLK to be activated f PHY not in low power state TOT s CLK ACTIVATE Time for S to be activated from reassertion o PHY in low pos 73 z T The specified ps and times are worst case values appropriate for operation with the TSB41AB1 These values are broader than those specified for the same parameters in IEEE 1394a 2000 that is an implementation of LPS that meets the requirements of IEEE 1394a 2000 operates correctly with the TSB41AB1 tA pulsed LPS signal must have a duty cycle ratio of psp to cycle period in the specified range to ensure proper operation when using an isolation barrier on the LPS signal for example as shown in Figure 14 The maximum value for TRESTORE does not apply when the PHY LLC interface is disabled which case an indefinite time may elapse before LPS is reasserted Otherwise in order to reset but not disable the interface it is necessary that the LLC ensure that LPS is deasserted for less than T PS DISABLE The LLC requests that the interface be reset by deasserting the LPS signal and termin
71. h performance thermally enhanced 48 64 terminal PHP PAP PowerPAD packages Use of a PowerPAD package does not require any special considerations except to note that the PowerPAD which is an exposed metallic pad on the bottom of the device is a thermal and electrical conductor This exposed pad is connected inside the package to the substrate of the silicon die it is not connected to any terminal of the package Therefore if not implementing PowerPAD PCB features the use of solder masks or other assembly techniques may be required to prevent any inadvertent shorting by the exposed PowerPAD of connection etches or vias under the package The recommended option however is to not run any etches or signal vias under the device but to have only a grounded thermal land as explained below Although the actual size of the exposed die pad may vary the minimum size required of the keep out area is 8 mm x 8 mm for the 64 terminal PAP PowerPAD package and 5 mm x 5 mm for the 48 terminal PHP PowerPAD package It is recommended that there be a thermal land which is an area of solder tinned copper see Figure 17 underneath the PowerPAD package The thermal land varies in size depending on the PowerPAD package being used the PCB construction and the amount of heat that needs to be removed In addition the thermal land may or may not contain numerous thermal vias depending on PCB construction 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS
72. he IEEE Std 1394 1995 output voltage limits NOTE It is strongly recommended that signals tied to Vpp use a 1 kQ resistor minimum Tying signals directly to Vc c may result in ESD failures Signals tied to ground may be tied directly 48 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 13 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 Terminal Functions Continued TERMINAL SYSCLK E TESTM DESCRIPTION GQE ZQE A8 Logic reset input Asserting this terminal low resets the internal logic An internal pullup resistor to Vpp is provided so only an external delay capacitor is required for proper power up operation see power up reset in the Application Information section The RESET terminal also incorporates an internal pulldown which is activated when the PD input is asserted high This input is otherwise a standard logic input and may also be driven by an open drain type driver 99 A 20 0 H6 Test control input This input is used in manufacturing test of the TSB41AB1 For normal use this terminal may be tied to GND through a 1 kQ pulldown resistor or it may be tied to GND directly J7 Test control input This input is used in manufacturing test of the TSB41AB1 For normal use this terminal should be tied to GND Al System clock output Provides a 49 152 MHz clock signal
73. her conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTES 1 All voltage values except differential I O bus voltages are with respect to network ground DISSIPATION RATING TABLE POWER RATING ABOVE Ta 25 C POWER RATING This is the inverse of the traditional junction to ambient thermal resistance 1 oz trace and copper pad with solder 11 oz trace and copper pad without solder Standard JEDEC low K board Standard high K board For more information refer to TI technical brief PowerPAD Thermally Enhanced Package TI literature number SLMAO02 PowerPAD is a trademark of Texas Instruments 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 15 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 recommended operating conditions Source power node Non source power node 2 3 se mur CSC O O f e Maximum junction temperature Ty 26 1 C W TA 70 C see RgJA values listed in thermal Roga 58 6 C W Ta 70 C characteristics table 64PAP 60 1 C W 70 90 5 5
74. iated The PHY indicates a status transfer by asserting status on the CTL lines along with the status data on the DO and D1 lines only two bits of status are transferred per cycle Normally unless interrupted by a receive operation a status transfer is either two or eight cycles long A 2 cycle 4 bit transfer occurs when only status information is to be sent An 8 cycle 16 bit transfer occurs when register data is to be sent in addition to any status information 2 Status transfer terminated The PHY normally terminates a status transfer by asserting idle on the CTL lines The PHY may also interrupt a status transfer at any cycle by asserting receive on the CTL lines to begin a receive operation The PHY asserts at least one cycle of idle between consecutive status transfers receive Whenever the PHY detects the data prefix state on the serial bus it initiates a receive operation by asserting receive on the CTL terminals and a logic 1 on each of the D terminals data on indication The PHY indicates the start of a packet by placing the speed code encoded as shown in Table 20 on the D terminals followed by packet data The PHY holds the CTL terminals in receive until the last symbol of the packet has been transferred The PHY indicates the end of packet data by asserting idle on the CTL terminals All received packets are transferred to the LLC Note that the speed code is part of the PHY LLC protocol and is not included in the calculation o
75. information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must ful
76. ion for the serial bus the PHY LLC interface bus is granted to the LLC by asserting the grant state 11b on the CTL terminals for one SYSCLK cycle followed by idle for one clock cycle The LLC then takes control of the bus by asserting either idle 00b hold 01b or transmit 10b on the CTL terminals Unless the LLC is immediately releasing the interface the LLC may assert idle for at most one clock before it must assert either hold or transmit on the CTL terminals The hold state is used by the LLC to retain control of the bus while it prepares data for transmission The LLC may assert hold for zero or more clock cycles that is the LLC need not assert hold before transmit The PHY asserts data prefix on the serial bus during this time When the LLC is ready to send data the LLC asserts transmit on the CTL terminals as well as sending the first bits of packet data on the D lines A transmit is held on the CTL terminals until the last bits of data have been sent The LLC then asserts either hold or idle on the CTL terminals for one clock cycle and then asserts idle for one additional cycle before releasing the interface bus and placing its CTL and D terminals in high impedance The PHY then regains control of the interface bus The hold asserted at the end of packet transmission indicates to the PHY that the LLC requests to send another packet concatenated packet without releasing the serial bus The PHY responds to this concatenation request by
77. is bit is replicated in the c field bit 20 of the self ID packet This bit is set to the state specified by the C LKON input terminal upon hardware reset and is unaffected by bus reset Jitter 3 PHY repeater jitter This field indicates the worst case difference between the fastest and slowest repeater data delay expressed as Jitter 1 x20 ns For the TSB41AB1 this field is 0 Pwr_Class Node power class This field indicates this node s power consumption and source characteristics and is replicated in the pwr field bits 21 23 of the self ID packet This field is set to the state specified by the 2 input terminals upon hardware reset and is unaffected by bus reset see Table 9 48 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 33 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION Table 2 Base Register Field Descriptions Continued FIELD SIZE TYPE DESCRIPTION Resuming port interrupt enable This bit if set to 1 enables the port event interrupt PEI bit to be set whenever resume operations begin on any port This bit also enables the C LKON output signal to be activated whenever the LLC is inactive and any of the CPSI STOI interrupt bits are set This bit is reset to 0 by hardware reset and is unaffected by bus reset Initiate short arbi
78. is overridden by any value subsequently loaded into the Pwr_Class field in register 4 Table 9 Power Class Descriptions DESCRIPTION Node does not need power and does not repeat power Node is self powered and provides a minimum of 15 W to the bus Node is self powered and provides a minimum of 30 W to the bus Node is self powered and provides a minimum of 45 W to the bus 100 Node may be powered from the bus for the PHY only using up to 3 W and may also provide power to the bus The amount of bus power that it provides can be found in the configuration ROM Node is powered from the bus and uses up to 3 W An additional 3 W is needed to enable the link Node is powered from the bus and uses up to 3 W An additional 7 W is needed to enable the link 49 5 INSTRUMENTS 38 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 51154231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION using the TSB41AB1 with non IEEE 1394a 2000 link layer The TSB41AB1 implements the PHY LLC interface specified in IEEE 1394 2000 This interface is based upon the interface described in informative Annex J of IEEE Std 1394 1995 which is the interface used in older PHY devices The PHY LLC interface specified in IEEE 1394a 2000 is completely compatible with the older Annex J interface IEEE 1394a 2000 includes enhancem
79. it operation is terminated by the link asserting hold or idle on the CTL lines The link asserts hold to indicate that the PHY is to retain control of the serial bus in order to transmit a concatenated packet The link asserts idle to indicate that packet transmission is complete and the PHY may release the serial bus The link then asserts idle for one more cycle following this cycle of hold or idle before releasing the interface and returning control to the PHY Concatenated packet speed code If multispeed concatenation is enabled in the PHY the link asserts a speed code on the D lines when it asserts hold to terminate packet transmission This speed code indicates the transmission speed for the concatenated packet that is to follow The encoding for this concatenated packet speed code is the same as the encoding for the received packet speed code see Table 20 The link may not concatenate an S100 packet onto any higher speed packet After regaining control of the interface the PHY shall assert at least one cycle of idle before any subsequent status transfer receive operation or transmit operation 48 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 51 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION transmit continued 1 3 4 5 Na Kee Xo Xn 07 00 00 X
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82. me active The link on output is a square wave signal with a period of approximately 163 ns 8 SYSCLK cycles when active The link on output is otherwise driven low except during hardware reset when it is high impedance The link on output is activated if the LLC is inactive LPS inactive or the LCtrl bit cleared and when a the PHY receives a link on PHY packet addressed to this node or b the PEI port event interrupt register bit is 1 or any of the CTOI configuration time out interrupt CPSI cable power status interrupt or STOI state time out interrupt register bits are 1 and the RPIE resuming port interrupt enable register bit is also 1 Once activated the link on output continues active until the LLC becomes active both LPS active and the LCtrl bit set The PHY also deasserts the link on output when a bus reset occurs unless the link on output would DESCRIPTION Analog circuit ground terminals These terminals should be tied together to the low impedance circuit board ground plane Analog circuit power terminals A combination of high frequency decoupling capacitors near each terminal is suggested such as paralleled 0 1 uF and 0 001 uF Lower frequency 10 uF filtering capacitors are also recommended These supply terminals are separated from PLLVpp and DVpp inside the device to provide noise isolation They should be tied at a low impedance point on the circuit board otherwise be active because one of the interrupt
83. mplete The PHY asserts the idle state on the CTL lines and logic 0 on the D lines This indicates that the PHY LLC interface initialization is complete and normal operation may commence The PHY now accepts requests from the LLC via the LREQ line ISO high 7 Cycles SYSCLK EL LC 2 3 CTLO CTL1 a ELE E23 TCLK ACTIVE Figure 32 Interface Initialization ISO High 58 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION interface reset and disable continued The sequence of events for initialization of the PHY LLC interface when the interface is in the nondifferentiated mode of operation ISO terminal is high is as follows 1 LPS reasserted After the interface has been in the reset or disabled state for at least the minimum TREsTORE time the LLC causes the interface to be initialized and restored to normal operation by reasserting the LPS signal In Figure 32 the interface is shown in the disabled state with SYSCLK low inactive However the interface initialization sequence described here is also executed if the interface is merely reset but not yet disabled SYSCLK activated If the interface is disabled the PHY reactivates its SYSCLK output when it detects
84. n the TSB41AB1 The configuration of the registers at addresses Oh through 7h the base registers is fixed while the configuration of the registers at addresses 8h through Fh the paged registers is dependent upon which one of eight pages numbered 0 through 7 is currently selected The selected page is set in base register 7 The configuration of the base registers is shown in Table 1 and corresponding field descriptions are given in Table 2 The base register field definitions are unaffected by the selected page number A reserved register or register field marked as Reserved or Rsvd in register configuration tables is read as 0 but is subject to future usage All registers in pages 2 through 6 are reserved Table 1 Base Register Configuration BIT POSITION 0000 Physical ID oor me m 01001 0010 Extended 111b Num Ports 000010 Reserved 49 EXAS INSTRUMENTS 32 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION internal register configuration continued Table 2 Base Register Field Descriptions TYPE DESCRIPTION This field contains the physical address ID of this node determined during self ID The physical ID is invalid after a bus reset until self ID has completed as indicated by an unsolicited register O status transfer
85. naffected by bus reset Fault This bit indicates that a resume fault or suspend fault has occurred on the selected port and that the port is in the suspended state A resume fault occurs when a resuming port fails to detect incoming cable bias from its attached peer A suspend fault occurs when a suspending port continues to detect incoming cable bias from its attached peer Writing 1 to this bit clears the bit to 0 This bit is reset to 0 by hardware reset and is unaffected by bus reset 49 5 INSTRUMENTS 36 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION internal register configuration continued The vendor identification page is used to identify the vendor manufacturer and compliance level The page is selected by writing 1 to the Page_Select field in base register 7 The configuration of the vendor identification page is shown in Table 5 and corresponding field descriptions are given in Table 6 Table 5 Page 1 Vendor ID Register Configuration BIT POSITION Compliance Compliance level For the TSB41AB1 this field is 01h indicating compliance with IEEE 1394a 2000 Vendor ID 24 Manufacturer s organizationally unique identifier OUI For the TSB41AB1 this field is 08 0028h Texas Instruments the MSB is at registe
86. ols the state of the PHY LLC interface using the LPS signal The interface may be placed into a reset state a disabled state or be made to initialize and then return to normal operation When the interface is not operational whether reset disabled or in the process of initialization the PHY cancels any outstanding bus request or register read request and ignores any requests made via the LREQ line Additionally any status information generated by the PHY is not queued and thus does not cause a status transfer upon restoration of the interface to normal operation The LPS signal may be either a level signal or a pulsed signal depending upon whether the PHY LLC interface is a direct connection or is made across an isolation barrier When an isolation barrier exists between the PHY and LLC whether of the bus holder type or Annex J type the LPS signal must be pulsed In a direct connection the LPS signal may be either a pulsed or a level signal Timing parameters for the LPS signal are given in Table 21 52 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION interface reset and disable continued Table 21 LPS Timing Parameters PARAMETER DESCRIPTION UNIT TLPSL LPS low time when pulsed t 0 00 26 TLPSH LPS hi
87. on but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by to Customer on an annual basis Addendum Page 1 MECHANICAL DATA PHP 5 048 PowerPAD PLASTIC QUAD FLATPACK Thermal Pad See Note D X Gage Plane T jeg Seating Plane ba 0 08 4146927 08 03 NOTES All linear dimensions are in millimeters B This drawing is subject to change without notice C Body dimensions do not include mold flash or protrusion D This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMA002 for information regarding recommended board layout This document is available at www ti com lt http
88. operation terminated The PHY terminates the receive operation by asserting idle on the CTL lines The PHY asserts at least one cycle of idle following a receive operation 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 49 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION receive continued t 06 1 00 CTLO CTL1 o1 10 2 3 D0 D7 XX 1 Data On 1 00 Figure 24 Null Packet Reception Timing The sequence of events for a null packet reception is as follows 1 Receive operation initiated The PHY indicates a receive operation by asserting receive on the CTL lines Normally the interface is idle until receive is asserted However the receive operation may interrupt a status transfer operation that is in progress so that the CTL lines may change from status to receive without an intervening idle Data on indication The PHY asserts the data on indication code on the D lines for one or more cycles Receive operation terminated The PHY terminates the receive operation by asserting idle on the CTL lines The PHY asserts at least one cycle of idle following a receive operation transmit When the LLC issues a bus request through the LREQ terminal the PHY arbitrates to gain control of the bus If the PHY wins arbitrat
89. pacitors may help in this Minimizing the loop area minimizes the effect of the resonant current Is that flows in this resonant circuit This layout unit crystal and load capacitors should then be placed as close as possible to the PHY XI and XO terminals to minimize trace lengths Figure 16 depicts a layout that meets these guidelines Figure 16 Recommended Crystal and Capacitor Layout It is strongly recommended that part of the verification process for the design be to measure the frequency of the SYSCLK output of the PHY This should be done with a frequency counter with an accuracy of six digits or better If the SYSCLK frequency is more than the crystal tolerance from 49 152 MHz the load capacitance of the crystal may be varied to improve frequency accuracy If the frequency is too high add more load capacitance if the frequency is too low decrease load capacitance Typically changes should be done to both load capacitors C9 and C10 see Figure 15 at the same time and both should be of the same value Additional design details and requirements may be provided by the crystal vendor For more information see Selection and Specification of Crystals for Texas Instruments IEEE 1394 Physical Layers literature number SLLA051 EMI guidelines For electromagnetic interference EMI guidelines and recommendations check the web site http www ti com 1394emi guidelines designing with the PowerPad package The TSB41AB1 is housed in hig
90. put to convert this signal to the correct logic level when differentiated The LLC must also implement similar output differentiation and input hysteresis circuitry on its CTL and D terminals and output differentiation circuitry on its LREQ terminal Input Buffer With Hysteresis DIN lt DOUT Internal Device Logic D Terminal 3 State Output Driver 150 OUTEN e INIT SYSCLK Figure 20 Input Output Differentiation Logic LLC service request To request access to the bus to read or write a PHY register or to control arbitration acceleration the LLC sends a serial bit stream on the LREQ terminal as shown in Figure 21 NOTE Each cell represents one clock sample time and n is the number of bits in the request stream Figure 21 LREQ Request Stream The length of the stream varies depending on the type of request as shown in Table 12 Table 12 Request Stream Bit Length REQUEST TYPE NUMBER OF BITS Acceleration control request 60000 49 5 INSTRUMENTS 44 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION LLC service request continued Regardless of the type of request a start bit of 1 is required at the beginning of the stre
91. r address 1010b Product ID 24 Product identifier For the TSB41AB1 this field is 42 XXXXh the MSB is at register address The vendor dependent page provides access to the special control features of the TSB41AB1 as well as configuration and status information used in manufacturing test and debug This page is selected by writing 7 to the Page Select field in base register 7 The configuration of the vendor dependent page is shown in Table 7 and corresponding field descriptions are given in Table 8 Table 7 Page 7 Vendor Dependent Register Configuration BIT POSITION 0 22 20 0000000000 3 2 I5 5s 6 7 1000 Reserved Link_Speed 1011 Reserved for test 1100 Reserved for test 1101 Reserved for test 1110 Reserved for test 1111 Reserved for test 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 37 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION internal register configuration continued Table 8 Page 7 Vendor Dependent Register Field Descriptions FIELD SIZE DESCRIPTION Null packet actions flag This bit instructs the PHY not to clear fair and priority requests when a null packet is received with arbitration acceleration enabled If 1 then fair and priority requests are cleared only when a packet of
92. re sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI
93. re the device is taken out of reset NOTE It is strongly recommended that signals tied to Vpp use 1 kQ resistor minimum Tying signals directly to Vc c may result in ESD failures Signals tied to ground may be tied directly 49 5 INSTRUMENTS 14 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 absolute maximum ratings over operating free air temperature unless otherwise Supply voltage range Vpp see Note 1 0 3Vto4V Input voltage tange edd ret oe 0 5 V to Vpp 0 5 V Output voltage range at any output VO 0 5 V to Vpp 0 5V Continuous total power dissipation See Dissipation Rating Table Operating free air temperature TA 0 C to 70 C Storage temperature range Tstg 65 C to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 260 C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any ot
94. ree ID has completed Debounced port connection status This bit indicates that the selected port is connected The connection must be stable for the debounce time of approximately 341 ms for the con bit to be set to 1 The con bit is reset to 0 by hardware reset and is unaffected by bus reset NOTE The con bit indicates that the port is physically connected to a peer PHY but the port is not necessarily active Debounced incoming cable bias status A 1 indicates that the selected port is detecting incoming cable bias The incoming cable bias must be stable for the debounce time of 52 us for the bias bit to be set to 1 Port disabled control If 1 the selected port is disabled The dis bit is reset to 0 by hardware reset all ports are enabled for normal operation following hardware reset The dis bit is not affected by bus reset Port peer speed This field indicates the highest speed capability of the peer PHY connected to the selected port encoded as follows Code Peer Speed 000 5100 001 5200 010 5400 011 111 invalid The Peer_Speed field is invalid after a bus reset until self ID has completed NOTE Peer speed codes higher than 010b S400 are defined in IEEE 1394a 2000 However the TSB41AB1 is only capable of detecting peer speeds up to S400 Port event interrupt enable When set to 1 a port event on the selected port sets the port event interrupt PEI bit and notifies the link This bit is reset to 0 by hardware reset and is u
95. rite PHY registers or control arbitration acceleration The LPS and C LKON terminals are used for power management of the PHY and LLC The LPS terminal indicates the power status of the LLC and may be used to reset the PHY LLC interface or to disable SYSCLK The C LKON terminal is used to send a wake up notification to the LLC and to indicate an interrupt to the LLC either when LPS is inactive or when the PHY register LCirl bit is zero The ISO terminal is used to enable the output differentiation logic on the CTLO CTL1 and 00 07 terminals Output differentiation is required when an Annex J type isolation barrier is implemented between the PHY and LLC The TSB41AB1 normally controls the CTLO CTL1 00 07 bidirectional buses The LLC is allowed to drive these buses only after the LLC has been granted permission to do so by the PHY There are four operations that may occur on the PHY LLC interface link service request status transfer data transmit and data receive The LLC issues a service request to read or write a PHY register to request the PHY to gain control of the serial bus in order to transmit a packet or to control arbitration acceleration 49 5 INSTRUMENTS 42 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION PHY Link layer interface
96. ruments Literature No 51 004 The exposed thermal pad dimensions for this package are shown in the following illustration 48 55 m Exposed Thermal Pad 49 5 00 4 50 64 5 00 NOTE All linear dimensions are in millimeters 4 30 Top View Exposed Thermal Pad Dimensions 4206326 3 E 09 07 LAND PATTERN 5 064 PowerPAD Example Board Layout Stencil Openings Via pattern and copper area under solder mask Based on a stencil thickness may vary depending on layout constraints of 127mm 005 Reference table below for other solder stencil thicknesses 36 0 5 775 WOO 64 0 25 Solder Mask Solder Mask Over Copper Defined Pad See Note C D See Note E Example Solder Mask Opening See Note F CENTER POWER PAD SOLDER STENCIL OPENING STENCIL_THICKNESS 0 152mm Pad Geometry 0 05 All Around Example 4208775 4 07 07 NOTES All linear dimensions are in millimeters B This drawing is subject to change without notic
97. ses the gap count to be set to 63 on all nodes in the bus If this bus reset is initiated by setting the IBR bit to 1 the RHB and gap count register must also be loaded with the correct values consistent with the just transmitted PHY config packet In the TSB41AB1 the RHB and gap count have been updated to their correct values upon the transmission of the PHY config packet and so these values may first be read from register 1 and then rewritten Other than to initiate the bus reset which must follow the transmission of a PHY config packet whenever the IBR bit is set to 1 in order to initiate a bus reset the gap count value must also be set to 63 to be consistent with other nodes on the bus and the RHB should be maintained with its current value The PHY register 1 should not be written to except to set the IBR bit The RHB and gap count should not be written without also setting the IBR bit to 1 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 41 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION PHY Link layer interface The TSB41AB1 is designed to operate with an LLC such as the Texas Instruments TSB12LV21 TSB12LV22 TSB12LV23 TSB12LV26 TSB12LV31 TSB12LV41 TSB12LV42 or TSB12LV01A Details of operation for the Texas Instruments LLC devices are found in the respective
98. set To ensure proper operation of the TSB41AB1 the RESET terminal must be asserted low for a minimum of 2 ms from the time that PHY power reaches the minimum required supply voltage When using a passive capacitor on the RESET terminal to generate a power on reset signal the minimum reset time is assured if the capacitor has a minimum value of 0 1 uF and also satisfies the following equation C nin 0 0077 x T 0 085 2 where Cmin is the minimum capacitance on the RESET terminal in uF and T is the Vpp ramp time 10 90 in milliseconds bus reset In the TSB41AB1 the initiate bus reset IBR bit may be set to 1 in order to initiate a bus reset and initialization sequence The IBR bit is located in PHY register 1 along with the root holdoff bit RHB and gap count register as required by IEEE 13942 2000 this configuration also maintains compatibility with older PHY designs which were based upon the suggested register set defined in Annex J of IEEE Std 1394 1995 Therefore whenever the IBR bit is written the RHB and gap count are also necessarily written 40 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION bus reset continued The RHB and gap count may also be updated by PHY config packets The TSB41AB1 is I
99. t board with 1 oz copper t Use of thermally enhanced PowerPad PHP package is assumed in all three test conditions thermal characteristics GQE package baard ho Vies beard Board mounted no air flow JEDEC high k test board no thermal vias used on board thermal characteristics ZQE package PARAMETER TEST CONDITIONS MIN TYP UNIT ReJA Junction to ambient thermal resistance Board mounted no air flow JEDEC low k test 119 63 board no thermal vias used on board 39 03 ReJC Junction to case thermal resistance ReJA Junction to ambient thermal resistance Board mounted no air flow JEDEC high k test 58 32 ReJC Junction to case thermal resistance board no thermal vias used on board 39 09 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 19 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 switching characteristics PARAMETER TEST CONDITIONS MIN UNIT Titer tanemi Between and TPB 2 5 t Test Conditions 3 3 Vcc TA 25 C 49 5 INSTRUMENTS 20 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION TPA TPB TPA TPB
100. tatus information for each of the ports The port is selected by writing 0 to the Page Select field and the desired port number to the Port Select field in base register 7 The configuration of the port status page registers is shown in Table 3 and corresponding field descriptions are given in Table 4 If the selected port is unimplemented all registers in the port status page are read as 0 Table 3 Page 0 Port Status Register Configuration BIT POSITION o ADDRESS 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 35 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 APPLICATION INFORMATION internal register configuration continued Table 4 Page 0 Port Status Register Field Descriptions TPA line state This field indicates the TPA line state of the selected port encoded as follows Code Line State 00 invalid 01 10 11 TPB line state This field indicates the TPB line state of the selected port This field has the same encoding as the Astat field Child parent status A 1 indicates that the selected port is a child port A 0 indicates that the selected port is the parent port A disconnected disabled or suspended port is reported as a child port The Ch bit is invalid after a bus reset until t
101. ted in the self ID packet it has no effect on the speed signaled to peer PHYs during self ID The TSB41AB1 identifies itself as S400 capable to its peers regardless of the value in the Link Speed field Generally the Link Speed field should not be changed from its power on default value of S400 unless it is determined that the speed map if one exists is incorrect for path entries terminating in the local node If the speed map is incorrect it can be assumed that the bus manager has used only the self ID packet information to build the speed map In this case the node may update the Link Speed field to reflect the lower speed capability of the LLC and then initiate another bus reset to cause the speed map to be rebuilt Note that in this scenario any speed map entries for node to node communication paths that pass through the local node s PHY are restricted by the lower speed In the case of a leaf node which has only one active port the Link Speed field may be set to indicate the speed of the LLC without first checking the speed map Changing the Link Speed field in a leaf node can only affect those paths that terminate at that node Because no other paths can pass through a leaf node it can have no effect on other paths in the speed map For hardware configurations which can only be a leaf node all ports but one are unimplemented it is recommended that the Link Speed field be updated immediately after power on or hardware reset power up re
102. that LPS has been reasserted If the PHY has entered a low power state it takes between 5 3 ms to 7 3 ms for SYSCLK to be restored if the PHY is not in a low power state SYSCLK is restored within 60 ns The SYSCLK output is a 50 duty cycle square wave with a frequency of 49 152 MHz 100 ppm period of 20 345 ns During the first seven cycles of SYSCLK the PHY continues to drive the CTL and D terminals low The LLC is also required to drive its CTL and D outputs low for one of the first six cycles of SYSCLK but otherwise to place its CTL and D outputs in a high impedance state The LLC continues to drive its LREQ output low during this time Receive indicated Upon the eighth SYSCLK cycle following reassertion of LPS the PHY asserts the receive state on the CTL lines and the data on indication all ones on the D lines for one or more cycles Initialization complete The PHY asserts the idle state on the CTL lines and logic 0 on the D lines This indicates that the PHY LLC interface initialization is complete and normal operation may commence The PHY now accepts requests from the LLC via the LREQ line 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 59 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 49 Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 20 Mar 2008 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type
103. thermal resistance Board mounted no air flow high conductivity MIN TYP MAX Tl recommended test board chip soldered or RgJc Junction to case thermal resistance greased to thermal land with 1 oz copper no solder grease thermal connection to thermal E ReJC Junction to case thermal resistance land with 1 oz copper ReJA Junction to ambient thermal resistance Board mounted no air flow low conductivity Resco Junction to case thermal resistance JEDEC test board with 1 oz copper t Use of thermally enhanced PowerPad PAP package is assumed in all three test conditions Reja Junction to ambient thermal resistance Board mounted no air flow high conductivity Tl recommended test board with thermal land but thermal characteristics PHP package PARAMETER TEST CONDITIONST MIN UNIT ReJA Junction to ambient thermal resistance Board mounted no air flow high conductivity Tl recommended test board chip soldered or Junction to case thermal resistance greased to thermal land with 1 oz copper RoJA Junction to ambient thermal resistance Board mounted no air flow high conductivity Tl recommended test board with thermal land but no solder or grease thermal connection to thermal ReJC Junction to case thermal resistance land with 1 02 copper ReJA Junction to ambient thermal resistance Board mounted no air flow low conductivity Rejc Junction to case thermal resistance JEDEC tes
104. tion and transmission via the CTL and D lines and request activity via the LREQ line In Figure 28 the LPS signal is shown as a nonpulsed level signal However it is permissible to use a pulsed signal for LPS in a direct connection between the PHY and LLC a pulsed signal is required when using an isolation barrier whether of the TI bus holder type or Annex J type 2 LPS deasserted The LLC deasserts the LPS signal and within 1 us terminates any request or interface bus activity places its CTL and D outputs into a high impedance state and drives its LREQ output low 3 Interface reset After T ps time the PHY determines that LPS is inactive terminates any interface bus activity and drives its CTL and D outputs low The PHY LLC interface is now in the reset state 4 Interface restored After the minimum TRESTORE time the LLC may again assert LPS active When LPS is asserted the interface is initialized If the LLC continues to keep the LPS signal deasserted it requests that the interface be disabled The PHY disables the interface when LPS has been deasserted for piSABLE When the interface is disabled the PHY sets its CTL and D outputs as stated above for interface reset but also stops SYSCLK activity The interface is also placed into the disabled condition upon a hardware reset of the PHY The timing for interface disable is shown in Figure 29 and Figure 30 When the interface is disabled the PHY enters a lo
105. tivity such that signals end a logic 0 state The PHY LLC interface is now in the reset state 4 Interface disabled If the LPS signal remains inactive for ps pisAp p time the PHY terminates SYSCLK activity by placing the SYSCLK output into a high impedance state The PHY LLC interface is now in the disabled state ISO 3 4 SYSCLK UU Y000000000 4 27 0000000004 _ LPS TLPS RESET gt TLPS DISABLE P Figure 30 Interface Disable ISO High 49 5 INSTRUMENTS 56 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER 5 54231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION interface reset and disable continued The sequence of events for disabling the PHY LLC interface when it is in the nondifferentiated mode of operation ISO terminal is high is as follows 1 Normal operation Interface is operating normally with LPS active SYSCLK active status and packet data reception and transmission via the CTL and D lines and request activity via the LREQ line 2 LPS deasserted The LLC deasserts the LPS signal and within 1 us terminates any request or interface bus activity places its CTL and D outputs into a high impedance state and drives its LREQ output low Int
106. trated bus reset This bit if set to 1 instructs the PHY to initiate a short 1 30 us arbitrated bus reset at the next opportunity This bit is reset to 0 by bus reset NOTE Legacy IEEE Std 1394 1995 compliant PHYs may not be capable of performing short bus resets Therefore initiation of a short bus reset in a network that contains such a legacy device results in a long bus reset being performed Configuration time out interrupt This bit is set to 1 when the arbitration controller times out during tree ID start and may indicate that the bus is configured in a loop This bit is reset to 0 by hardware reset or by writing a 1 to this register bit If the CTOI and RPIE bits are both set and the LLC is or becomes inactive the PHY activates the C LKON output to notify the LLC to service the interrupt NOTE If the network is configured in a loop only those nodes that are part of the loop generate a configuration time out interrupt other nodes instead time out waiting for the tree ID and or self ID process to complete and then generate a state time out interrupt and bus reset Cable power status interrupt This bit is set to 1 whenever the CPS input transitions from high to low indicating that cable power may be too low for reliable operation This bit is reset to 1 by hardware reset It can be cleared by writing a 1 to this register bit If the CPSI and RPIE bits are both set and the LLC is or becomes inactive the PHY activates the C LK
107. ts This current setting resistor has a value of 6 34 1 0 When the power supply of the TSB41AB1 is off while the twisted pair cables are connected the TSB41AB1 transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage at the other end of the cable Fail safe circuitry blocks any leakage path from the port back to the device power plane The TESTM SE and SM terminals are used to set up various manufacturing test conditions For normal operation the TESTM terminal should be connected to Vpp through a 1 resistor SE should be tied to ground through a 1 kQ resistor and SM should be connected directly to ground Four package terminals are used as inputs to set the default value for four configuration status bits in the self ID packet and are tied high through a 1 k resistor or hardwired low as a function of the equipment design The PCO PC2 terminals are used to indicate the default power class status for the node the need for power from the cable or the ability to supply power to the cable See Table 9 for power class encoding The C LKON terminal is used as an input to indicate that the node is a contender for either isochronous resource manager IRM or for bus manager BM The TSB41AB1 supports suspend resume as defined the IEEE 13942 2000 specification The suspend mechanism allows pairs of directly connected ports to be placed into a low power state suspended state while
108. w power state if none of its ports is active ISO low 1 3 4 SYSCLK nH AU VJ 5 D0 D7 200 _ 2 LPS TLPSL RESET gt gt TLPSH 4 TLPS DISABLE _ Figure 29 Interface Disable ISO Low 49 5 INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 55 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 PRINCIPLES OF OPERATION interface reset and disable continued The sequence of events for disabling the PHY LLC interface when it is in the differentiated mode of operation ISO terminal is low is as follows 1 Normal operation Interface is operating normally with LPS active SYSCLK active status and packet data reception and transmission via the CTL and D lines and request activity via the LREQ line 2 LPS deasserted The LLC deasserts the LPS signal and within 1 us terminates any request or interface bus activity and places its LREQ CTL and D outputs into a high impedance state the LLC should terminate any output signal activity such that signals end a logic 0 state Interface reset After Tj PS RESET time the PHY determines that LPS is inactive terminates any interface bus activity and places its CTL and D outputs into a high impedance state the PHY terminates any output signal ac
109. y a remote receiver indicates the presence of an active connection This bias voltage source must be stabilized by an external filter capacitor of 1 uF TPBIAS is typically 0 2 V when the port is not connected to another node The line drivers in the TSB41AB1 operate in a high impedance current mode and are designed to work with external 112 Q line termination resistor networks in order to match the 110 Q cable impedance One network is provided at each end of a twisted pair cable Each network is composed of a pair of series connected 56 0 resistors The midpoint of the pair of resistors that is directly connected to the twisted pair A terminals is connected to its corresponding TPBIAS voltage terminal The midpoint of the pair of resistors that is directly 49 5 INSTRUMENTS 2 POST OFFICE BOX 655303 DALLAS TEXAS 75265 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER ARBITER SLLS4231 JUNE 2000 REVISED MARCH 2005 description continued connected to the twisted pair B terminals is coupled to ground through a parallel R C network with recommended values of 5 and 220 pF The values of the external line termination resistors are designed to meet IEEE Std 1394 1995 when connected in parallel with the internal receiver circuits An external resistor connected between the RO and R1 terminals sets the driver output current along with other internal operating curren

TEXAS INSTRUMENTS TSD41AB1 handbook

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