ANALOG DEVICES -AD8591/AD8592/AD8594 handbook
Contents
1. 1k 0 90 Vg 2 7V lt Ta 25 C E gt gt E 100 E amp 0 80 uL i 9 g amp 075 SOURCE SINK 5 lt 9 10 9 E 0 70 Vs 45V 5 5 E a z E 0 65 E 5 8 Q 4 9 gt 0 60 a Vg 2 7V 7 0 55 0 1 E 0 50 001 01 1 10 100 1k 001 01 1 10 100 1k 40 20 O 20 40 60 80 100 LOAD CURRENT mA LOAD CURRENT mA TEMPERATURE C Figure 1 Output Voltage to Supply Rail vs Load Current Figure 2 Output Voltage to Supply Rail vs Load Current Figure 3 Supply Current per Amplifier vs Temperature REV A 0 8 0 7 pea 0 6 0 5 0 4 0 3 0 2 J 0 1 SUPPLY CURRENT AMPLIFIER mA 0 0 75 1 25 1 75 2 25 2 75 3 SUPPLY VOLTAGE Volts Figure 4 Supply Current per Amplifier vs Supply Voltage Vg 2 7V 45V Ven Vs 2 INPUT OFFSET CURRENT pA TEMPERATURE C Figure 7 Input Offset Current vs Temperature 80 Vs 45V 60 Ri NO LOADH 45 TA 25 C 40 90 3 20 1 I z lt E 0 18 1k 10k 100k 1M 10M 100M FREQUENCY Hz Figure 10 Open Loop Gain and Phase vs Frequency REV A PHASE SHIFT Degrees N Vs 45V Ven 2 5V wo 2 a INPUT OFFSET VOLTAGE mV o E 82. 100 1k FREQUENCY Hz Figure 16 Power Supply Rejection Ratio vs Frequency 0v Vg 1 35V Vin 50mV Ay 1 R 2k0 C 300pF T4 25 C 20mV DIV 500 ns DIV Figure 19 Small Signal Transient Response CMRR dB 1k 10k 100k 1M 10M FREQUENCY Hz Figure 14 Common Mode Rejection Ratio vs Frequency 60 Vg 2 5V soL Ri 2k TA 25 C OS 40 30 20 LL SIGNAL OVERSHOOT 00 1 APACITANCE pF Figure 17 Small Signal Overshoot vs Load Capacitance Vg 2 5V Vin 50mV Ay 1 R 2k0 C 300pF Tp 425 C 20mV DIV 500 ns DIV Figure 20 Small Signal Transient Response PSRR dB 60 100 1k 10k 100k 1M FREQUENCY Hz zx SS ee SS Figure 15 Power Supply Rejection Ratio vs Frequency Di l E o o v tr ui gt o a x z o o E mI lt Figure 18 Small Signal Overshoot vs Load Capacitance Figure 21 Large Signal Transient Response REV A AD8591 AD8592 AD8594 SEPARA Ad AN Bare TERAN E E CURRENT NOISE DENSITY pA
3. 10 11 BDI C conf 0 2 19E 5 2 19E 5 VN1 600 0 RN1 60 0 16 45E 3 HN 61 0 VN1 30 RN2 61 0 1 GAIN STAGE G2 98 30 POLY 2 4 6 R2 30 98 13E6 CF 45 30 5E 12 S5 30 98 98 82 SCLOSE D3 30 31 oa 5 30 NANI V3 99 31 0 V4 32 50 0 6 OUTPUT STAGE M5 45 46 99 99 POX L 0 8E 6 W 16E 3 M6 45 47 50 50 NOX L 0 8E 6 W 16E 3 EG1 99 48 POLY 1 98 30 1 06 1 EG2 49 50 POLY 1 30 98 1 05 1 RG1 48 46 10E3 RG2 49 47 10E3 S6 46 99 98 82 SCLOSE S7 47 50 98 82 SCLOSE MODELS MODEL PIX PMOS LEVEL 2 KP 20E 6 VTO 0 7 LAMBDA 0 01 AF 1 KF 1E 31 MODEL NIX NMOS LEVEL 2 KP 20E 6 VTO 0 7 LAMBDA 0 01 AF 1 KF 1E 31 MODEL POX PMOS LEVEL 2 KP 8E 6 VTO 1 LAMBDA 0 067 MODEL NOX NMOS LEVEL 2 KP 13 4E 6 VTO 1 LAMBDA 0 067 MODEL SOPEN VSWITCH VON 2 4 VOFF 0 8 RON 10 ROFF 1E9 MODEL SCLOSE VSWITCH VON 0 8 VOFF 2 4 RON 10 ROFF 1E9 MODEL DX D IS 1E 14 ENDS AD8592 14 REV A AD8591 AD8592 AD8594 OUTLINE DIMENSIONS Dimensions shown in inches and mm 6 Lead SOT RT 6 0 122 3 10 0 106 2 70 4 0 071 1 80 0 118 3 00 0 059 1 50 0 098 2 50 piv 177 0 037 0 95 BSC 0 075 1 90 BSC 0 051 1 30 0 057 1 45 0 035 0 90 y y 0 035 0 90 Y gt de 10 gt je 0 059 0 15 0 020 0 50 SEATING 0 009 0 23 0 0 022 0 55
4. Where Ry is the resistance of the headphones 10 A Combined Microphone and Speaker Amplifier for Cellphone and Portable Headsets The dual amplifiers in the AD8592 make an efficient design for interfacing with a headset containing a microphone and speaker Figure 36 demonstrates a simple method for constructing an interface to a codec R1 C1 R2 0 1pF 10kQ TO CODEC VREF FROM CODEC FROM CODEC MONO OUT OR LEFT OUT U1 AD8592 AW RIGHT OUT R5 R6 10kQ 10k0 OPTIONAL Figure 36 A Speaker Mic Headset Amplifier Circuit UI A is used as a microphone preamplifier where the gain of the preamplifier is set as R3 R2 RI is used to bias an electret Using the same principle as described in the previous section the normalizing contact on the microphone speaker jack can be used to put the AD8592 into shutdown when the headset is not plugged in The AD8592 shutdown inputs can also be con trolled with TTL or CMOS compatible logic allowing micro phone or speaker muting if desired An Inexpensive Sample and Hold Circuit The independent shutdown control of each amplifier in the AD8592 allows a degree of flexibility in circuit design One par ticular application for which this feature is useful is in designing a sample and hold circuit for data acquisition Figure 37 shows a schematic of a simple yet extremely effective sample and hold circuit using a single AD8592 and one capacitor SAMPLE O AND HOLD
5. 0 000 0 00 0 010 0 25 PLANE 5 coc 0 08 0 014 0 35 16 Lead Thin Shrink Small Outline RU 16 F ns 2S ae ER sis EB e bard jar NIN elo olo 4 le UND Lud PIN 1 0 006 0 15 0 002 0 05 0 0433 i 10 y qe AX E 0 028 0 70 p 0 0256 0 0118 0 30 0 0 020 0 50 SEATING 0 65 0 0075 0 19 0 0079 0 20 PLANE BSC 0 0035 0 090 REV A 15 10 Lead pSOIC RM 10 0 124 3 15 7 0 112 2 84 E LLLI 0 124 3 15 0 199 5 05 0 112 2 84 0 187 4 75 pin 1L gt e 0 0197 0 50 BSC 0 122 3 10 0 120 3 05 inan 0 110 2 79 LEER 0 112 2 84 I 0 043 1 09 0 030 076 HTE 0 037 0 94 e le SEATING THE ooi6 Gn PLANE 0 011 0 28 O 0 022 0 56 0 003 0 08 0 021 0 53 16 Lead Narrow Body SO R 16A EXC 16 9 0 1574 4 00 0 2440 6 20 0 1497 3 80 1 8 0 2284 5 80 PIN1 0 0688 1 75 0 0196 0 50 0 0098 0 25 0 0532 1 35 0 0099 0 25 9 0 0040 0 10 SEATING 5 aoise pgs 0 0099 0 25 O 0 0500 1 27 PLANE 0 0075 0 19 0 0160 0 41 C3456a 0 2 99 PRINTED IN U S A
6. A PC 98 Compliant Headphone Speaker Amplifier Because of its high output current performance and shutdown plifier for driving an audio igure 34 shows ow t 97 codec to drive eadphones or Speakers 45V NOTE ADDITIONAL PINS OMITTED FOR CLARITY Figure 34 A PC 98 Compliant Headphone Line Out Amplifier When headphones are plugged into the jack the normalizing con tacts disconnect from the audio contacts This allows the voltage to the AD8592 shutdown pins to be pulled up to 5 V activating the amplifiers With no plug in the output jack the shutdown voltage is pulled to 100 mV through the R1 and R3 R5 voltage divider This powers the AD8592 down when it is not needed saving current from the power supply or battery U1 AD8592 AD8591 AD8592 AD8594 If gain is required from the output amplifier four additional resistors should be added as shown in Figure 35 The gain of the AD8592 can be set as Ay gt 5 R7 20k0 U1 AD8592 NOTE ADDITIONAL PINS OMITTED FOR CLARITY Figure 35 A PC 98 Compliant Headphone Amplifier With Gai Input coupling the reference voltage p R7 Ay 6dB WITH VALUES SHOWN R6 R4 and R5 help protect the AD8592 output in case the output jack or headphone wires accidentally get shorted to ground The output coupling capacitors C1 and C2 block dc current from the headphones and create a high pass filter with a corner frequency of 1 27 C1 R4 Ri 6 f aB
7. C 1 Package Type Oja Ojc Units 6 Lead SOT 23 RT 230 92 C W 10 Lead SOIC RM 200 44 C W 16 Lead SOIC R 120 36 C W 16 Lead TSSOP RU 180 35 C W NOTE UA is specified for worst case conditions i e Oya is specified for device in socket for surface mount packages ORDERING GUIDE Temperature Package Package Model Range Description Option AD8591ART 40 C to 85 C 6 Lead SOT 23 RT 6 AD8592ARM 40 C to 85 C 10 Lead SOIC RM 10 AD8594AR 40 C to 85 C 16 Lead SOIC R 16A AD8594ARU 40 C to 85 C 16 Lead TSSOP RU 16 tions for extended periods may affect device reliability For supplies less than 5 V the differential input voltage is limited to the supplies CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD8591 AD8592 AD8594 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality Typical Port n Char WARNING sper q ESD SENSITIVE DEVICE
8. Hz FREQUENCY Hz Figure 22 Large Signal Transient Figure 23 No Phase Reversal Figure 24 Current Noise Density vs Response Frequency Vg 2 7V Voy 1 35V TA 25 C 1001 V DIV 200 V DIV CU 0 aS es ee QUANTITY Amplifiers wee afia 024 ET VOLTAGE mV Figure 25 Voltage Noise Density vs Figure 26 Voltage Noise Density vs Figure 27 Input Offset Voltage Frequency Frequency Distribution a o o T4 25 C QUANTITY Amplifiers 12 10 8 6 4 2 0 2 4 INPUT OFFSET VOLTAGE mV Figure 28 Input Offset Voltage Distribution REV A AD8591 AD8592 AD8594 AD8591 AD8592 AD8594 APPLICATION SECTION Theory of Operation The AD859x family of amplifiers are all CMOS high output drive rail to rail input and output single supply amplifiers designed for low cost and high output current drive The parts include a power saving shutdown function making the AD8591 AD8592 AD8594 op amps ideal for portable multimedia and telecom applications Figure 29 shows the simplified schematic for an AD8591 AD8592 AD8594 amplifier Two input differential pairs consisting of an n channel pair M1 M2 and a p channel pair M3 M4 provide a rail to rail input common mode range The outputs of the input differential pairs are co
9. OUTPUT SAMPLE CLOCK U1 AD8592 Figure 37 An Efficient Sample and Hold Circuit REV A AD8591 AD8592 AD8594 The U1 A amplifier is configured as a unity gain buffer driving a 1 nF capacitor The input signal is connected to the noninverting input while the sample clock controls the shutdown for that amplifier When the sample clock is high the U1 A amplifier is active and the output follows V Once the sample clock goes low U1 A shuts down with the output of the amplifier going to a high impedance state holding the voltage on the C1 capacitor The U1 B amplifier is used as a unity gain buffer to prevent load ing on Cl Because of the low input bias current of the U1 B CMOS input stage and the high impedance state of the U1 A output in shutdown there is very little voltage droop from C1 during the Hold period This circuit can be used with sample frequencies as high as 500 kHz and as low as below 1 Hz Even lower voltage droop can be achieved for very low sample rates by increasing the value of C1 Direct Access Arrangement for PCMCIA Modems Telephone Line Interface Figure 38 illustrates a 5 V transmit receive telephone line interface for 600 Q systems It allows full duplex transmission of signals on a transformer coupled 600 Q line in a differential manner Amplifier Al provides gain that can be adjusted to meet the modem output drive requirements Both Al and A2 are configured to apply the largest possible signal on a si
10. Figure 30 Output Short Circuit Protection Power Dissipation Although the AD859x family of amplifiers are able to provide load currents of up to 250 mA proper attention should be given to not exceeding the maximum junction temperature for the device The equation for finding the junction temperature is given as 3 T Pprss X Oya Ta Where T AD859x junction temperature Ppiss AD859x power dissipation 0 4 AD859x junction to ambient thermal resistance of the package and T4 The ambient temperature of the circuit REV A AD8591 AD8592 AD8594 In any application the absolute maximum junction temperature must be limited to 150 C If this junction temperature is ex ceeded the device could suffer premature failure If the output voltage and output current are in phase for example with a purely resistive load the power dissipated by the AD859x can be found as Ppiss Iroa X Vsy Vovr 4 Where Izo4p AD859x output load current Vsy AD859x supply voltage and Vour The output voltage By calculating the power dissipation of the device and using the thermal resistance value for a given package type the maximum allowable ambient temperature for an application can be found using Equation 3 Capacitive Loading The AD859x exhibits excellent capacitive load driving capabilities and can drive up to 10 nF directly Although the device is stable with large capacitive loads there is a decrease in am
11. The AD8591 AD8592 AD8594 are immune to output voltage phase reversal with an input voltage within the supply voltages of the device However if either of the device s inputs exceeds 0 6 V outside of the supply rails the output could exhibit phase reversal This is due to the ESD protection diodes be coming forward biased thus causing the polarity of the input terminals of the device to switch The technique recommended in the Input Overvoltage Protection section should be applied in applications where the possibility of input voltages exceeding the supply voltages exists Output Short Circuit Protection To achieve high output current drive and rail to rail performance the outputs of the AD859x family do not have internal short cir cuit protection circuitry Although these amplifiers are designed to sink or source as much as 250 mA of output current shorting the output directly to the positive supply could damage or destroy the device To protect the output stage the maximum output current should be limited to 250 mA By placing a resistor in series with the output of the amplifier as shown in Figure 30 the output current can be limited The minimum value for Rx can be found from Equation 2 Vs a Ry S 250 mA 2 For a 5 V single supply application Ry should be at least 20 Q use Ry i is inside the feedba affected The tradeoff in voltage swing under hea y out na Pase the effec lt 1 where Ro is
12. 50 35 15 5 25 45 65 85 TEMPERATURE C Figure 5 Input Offset Voltage vs Temperature UT BIAS CURRENT pA 3 4 COMMON MODE VOLTAGE Volts Figure 8 Input Bias Current vs Common Mode Voltage OUTPUT SWING V p p 1k 10k 100k 1M 1 FREQUENCY Hz Figure 11 Closed Loop Output Voltage Swing vs Frequency AD8591 AD8592 AD8594 Vs 2 7V 5V Vom Vs 2 INPUT BIAS CURRENT pA 2 50 35 15 5 25 45 65 85 TEMPERATURE C Figure 6 Input Bias Current vs Temperature 80 Vs 427V 60 Ri NO LOADH 45 TA 25 C 40 90 3 20 135 I z lt q io 180 1 10k M 10M 100M FREQUENCY Hz PHASE SHIFT Degrees Figure 9 Open Loop Gain and Phase vs Frequency Vin 4 9V p p OUTPUT SWING V p p 1k 10k 100k 1M 10M FREQUENCY Hz Figure 12 Closed Loop Output Voltage Swing vs Frequency AD8591 AD8592 AD8594 200 180 E eo o 140 N o CE O 100 IMPEDAN o 1k 10k 100k 1M 10M 100M FREQUENCY Hz Figure 13 Closed Loop Output Impedance vs Frequency PSRR dB
13. 8594 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Vs 2 7 V Vey 1 35 V T 25 C unless otherwise noted Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage Vos 25 mV 40 C lt T4 lt 85 C 30 mV Input Bias Current Ig 5 50 pA 40 C lt T4 lt 85 C 60 pA Input Offset Current los 1 25 pA 40 C lt T4 lt 85 C 30 pA Input Voltage Range 0 2 7 V Common Mode Rejection Ratio CMRR Vem 0V to 2 7 V 38 45 dB Large Signal Voltage Gain Avo Ri 2 kQ Vo 0 3 V to 2 4 V 25 V mV Offset Voltage Drift AVos AT 20 uV C Bias Current Drift ATg AT 50 fA C Offset Current Drift Alos AT 20 fA C OUTPUT CHARACTERISTICS Output Voltage High Vou IL 10mA 2 55 2 61 V 40 C to 85 C 2 5 V Output Voltage Low VoL L 10 mA 60 100 mV 40 C to 85 C 125 mV Output Current Tour 250 mA Open Loop Impedance Zout f 1 MHz Ay 1 60 Q POWER SUPPLY Power Supply Rejection Ratio PSRR Vs 2 5 V to 6 V 45 dB Supply Current Amplifier Isy Vo 0V mA C lt 5 C mA Supply Current e 11 Amplifiers Shut D wn LA 408C lt TY lt 85 C uA SDI Amplifier Down mA Ispz Amplifier 2 Shut Down AD8592 mA SHUTDOWN INPUTS Logic High Voltage Vina 40 C lt Ta lt 85 C 1 6 V Logic Low Voltage Viu 40 C lt Ta lt 85 C 0 5 V Logic Input Current In 40 C lt T4 lt 85 C 1 LA DYNAMIC PERFORMANCE Slew Rate SR RL 2 kQ 3 5 V us Settling Time ts To 0 01 1 4 us Gain Band
14. ANALOG DEVICES CMOS Single Supply Rail to Rail Input Output Operational Amplifiers with Shutdown AD8591 AD8592 AD8594 FEATURES Single Supply Operation 2 5 V to 6 V High Output Current 250 mA Extremely Low Shutdown Supply Current 100 nA Low Supply Current 750 A Amp Wide Bandwidth 3 MHz Slew Rate 5 V s No Phase Reversal Very Low Input Bias Current High Impedance Outputs When in Shutdown Mode Unity Gain Stable APPLICATIONS Mobile Communication Handset Audio PC Audio PCMCIA Modem Line Driving Battery Powered Instrumentation Data Acquisition ASIC Input or Output Amplifier LCD Display Reference Level Driver GENERAL DESCRIPTION The AD8591 AD8592 and AD8594 rail to rail np ingle s 4 250 mA ou d a power mode The 8 in estam inde e tion for each amplifier When both amplifiers are in shutdown mode the total supply current is reduced to less than 1 uA The AD8591 and AD8594 include a single master shutdown func tion that reduces total supply current to less than 1 yA All amplifier outputs are in a high impedance state when in shut down mode These amplifiers have very low input bias currents making them suitable for integrators and diode amplification Outputs are stable with virtually any capacitive load Supply current is less than 750 uA per amplifier in active mode Applications for these amplifiers include audio amplification for portable computers portable phone headsets sound po
15. mbined in a compound folded cascode stage which drives the input to a second differential pair gain stage The outputs of the second gain stage provide the gate volt age drive to the rail to rail output stage The rail to rail output stage consists of M15 and M16 which are configured in a complementary common source configuration As with any rail to rail output amplifier the gain of the output stage and thus the open loop gain of the amplifier is dependent on the load resistance Also the maximum output voltage swing is directly proportional to the load current The difference be tween the maximum output voltage to the supply rails known as the dropout voltage is determined by the AD8591 AD8592 AD8594 output transistors on channel resistance The output dropout voltage is given in Figure 1 and Figure 2 100 amp A NOTE ALL CURRENT SOURCES GO TO 0 pA IN SHUTDOWN MODE Figure 29 AD8591 AD8592 AD8594 Simplified Schematic Input Voltage Protection Although not shown on the simplified schematic ESD protec tion diodes are connected from each input to each power supply rail These diodes are normally reverse biased but will turn on if either input voltage exceeds either supply rail by more than 0 6 V Should this condition occur the input current should be limited to less than 5 mA This can be done by placing a resistor in series with the input s The minimum resistor value should be 1 Output Phase Reversal
16. ngle supply to the transformer Because of the AD8594 s high output current drive and low dropout voltages the largest signal avail able on a single 5 V supply is approximately 4 5 V p p into a 600 Q transmission system Amplifier A3 is configured as a difference amplifier for two reasons signal fromin i i the receive A4 Amplifi Al s to meet the modem s input signal requirements Standard resistor values permit the use of SIP Single In line Package format resistor arrays Couple this with the AD8594 16 lead TSSOP or SOIC footprint and this circuit offers a compact cost effective solution P1 Tx GAIN ADJUST p2 TO TELEPHONE TxA LINE q 1 1 SHUTDOWN 5V Ti n MIDCOM 671 8005 10k0 ADJUST R13 R14 10kQ 14 3kO RECEIVE A1 A2 1 2 AD8592 A3 A4 z 1 2 AD8592 Figure 38 A Single Supply Direct Access Arrangement for PCMCIA Modems REV A Single Supply Differential Line Driver Figure 39 shows a single supply differential line driver circuit that can drive a 600 Q load with less than 0 796 distortion from 20 Hz to 15 kHz with an input signal of 4 V p p and a single 5 V supply The design uses an AD8594 to mimic the performance of a fully balanced transformer based solution However this design occu pies much less board space while maintaining low distortion and can operate down to dc Like the transformer based design either output can be shorted to ground for unbalanced line dri
17. or License Statement Use of this model indicates your acceptance of the terms and provisions in the License Statement Node Assignments noninverting input inverting input positive supply negative supply output x shutdown SUBCKT AD8592 1 2 99 50 45 80 INPUT STAGE M1 13 3 PIX L 0 8E 6 W 125E 6 M2 7 3 3 PIX L 0 8E 6 W 125E 6 RC1 50 4E3 Man BOT C coni AD M3 10 12 12 NIX L 0 8E 6 W 125E 6 MA 11 12 12 NIX L 0 8E 6 W 125E 6 RC3 10 99 4E3 RC4 11 99 4E3 C2 10 11 2E 12 I2 13 50 100E 6 EOS 7 2 POLY 3 21 98 73 98 61 0 1E 3 1 1 1 IOS 1 2 2 5E 12 V1 99 9 0 9 D1 3 9 DX v2 14 50 0 9 D2 14 12 DX S1 3 8 82 98 SOPEN S2 99 8 98 82 SCLOSE s3 12 13 82 98 SOPEN S4 13 50 98 82 SCLOSE CMRR 64dB ZERO AT 20kHz ECM1 20 98 POLY 2 1 98 2 98 0 5 5 RCM1 20 21 79 6E3 CCM1 20 21 100E 12 RCM2 21 98 50 PSRR 80dB ZERO AT 200Hz RPS1 70 O 1E6 RPS2 71 0 1E6 CPS1 99 70 1E 5 REV A 13 AD8591 AD8592 AD8594 CPS2 EPSY RPS3 CPS3 RPS4 EREF 98 00 GSY El 81 98 R1 81 82 1E3 C3 82 98 1E 50 98 72 72 73 T3 72 73 73 98 INTERNAL 99 50 SHUTDOWN 80 POLY 2 POLY 1 1E 5 POLY 2 1 59E6 500E 12 80 SECTION 720 1 9 70 0 99 0 99 50 0 71 0 1 1 VOLTAGE REFERENCE 50 0 0 5 5 20E 6 10E 7 VOLTAGE NOISE REFERENCE OF 30nV rt Hz
18. plifier band width as the capacitive load increases Figure 31 shows a graph of the AD8592 unity gain bandwidth under various capacitive loads 4 Vg 2 5V 3 5 R 1k0 TA 25 C 3 N ds 25 m E A 2 a 215 a 1 0 5 0 0 01 0 1 1 10 100 CAPACITIVE LOAD nF Figure 31 Unity Gain Bandwidth vs Capacitive Load When driving heavy capacitive loads directly from the AD859x output a snubber network can be used to improve transient response This network consists of a series R C connected from the amplifier s output to ground placing it in parallel with the capacitive load The configuration is shown in Figure 32 Al though this network will not increase the bandwidth of the am plifier it will significantly reduce the amount of overshoot as shown in Figure 33 ra AD8592 Figure 32 Configuration for Snubber Network to Compensate for Capacitive Loads REV A 47nF LOAD ONLY metal Lc pg zo NN NUR EUG IN CIRCUIT Figure 33 Snubber Network Reduces Overshoot and Ringing Caused from Driving Heavy Capacitive Loads The optimum values for the snubber network should be determined empirically based on the size of the capacitive load Table I shows a few sample snubber network values for a given load capacitance Table I Snubber Networks for Large Capacitive Loads Load Capacitance Snubber Network Cr Rs Cs 0 47 nF 300 Q 0 1 LF 4 7 nF 300 1 uF 47 nF 5 Q 1 uF
19. rts sound cards and set top boxes The AD859x family is capable of driving heavy capacitive loads such as LCD panel reference levels The ability to swing rail to rail at both the input and output enables designers to buffer CMOS DACs ASICs and other wide output swing devices in single supply systems The AD8591 AD8592 and AD8594 are specified over the indus trial 40 C to 85 C temperature range The AD8591 single is available in the tiny 6 lead SOT package The AD8592 dual is available in the 10 lead USOIC surface mount package The AD8594 quad is available in 16 lead narrow SOIC and 16 lead TSSOP packages REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices PIN CONFIGURATIONS 6 Lead SOT RT Suffix 2 AD8591 10 Lead pSOIC RM Suffix 16 Lead Narrow SOIC R Suffix OUTA 1 TOP VIEW IN B s Not to Scale 12 IN C IN B 6 INC NC NO CONNECT 16 Lead TSSOP RU Suffix NC NO CONNECT One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 O Analog Devices Inc 1999 AD8591 AD8592 AD
20. sed to simulate the common mode rejection power supply rejection and input voltage noise characteristics for the model In addition G2 R2 and CF are used to help set the open loop gain and gain bandwidth product of the model A number of secondary characteristics are also accurately por trayed in the SPICE model Flicker noise is accurately modeled with the 1 f corner frequency set through the KF and AF terms in the input stage transistors C1 and C2 are used in the input section to create secondary poles to achieve an accurate phase margin characteristic for the model The AD8591 AD8592 AD8594 shutdown circuitry is included in the model Switches S1 through S7 deactivate the op amp circuitry in shutdown mode The logic threshold for the shut down circuitry is accurately modeled through the VSWITCH model parameters near the end of the listing The active supply current versus supply voltage is also modeled through the volt age controlled current source GSY Characteristics of this model are based on typical values for the AD8591 AD8592 AD8594 amplifier at 27 C The model s characteristics are optimized specifically at 27 C and may lose accuracy at different simulation temperatures ww BDI C com AD 9 REV A AD8591 AD8592 AD8594 Listing 1 AD859x SPICE Macro Model AD8592 SPICE Macro Model Typical Values 9 98 Ver 1 TAM ADSC Copyright 1998 by Analog Devices Refer to README DOC file f
21. t 85 C 2 4 V Logic Low Voltage VINL 40 C lt T4 lt 85 C 0 8 V Logic Input Current In 40 C lt Ta lt 85 C 1 uA DYNAMIC PERFORMANCE Slew Rate SR RL 2 kQ 5 V us Full Power Bandwidth BWp 1 Distortion 325 kHz Settling Time ts To 0 01 1 6 us Gain Bandwidth Product GBP 3 MHz Phase Margin Do 70 Degrees Channel Separation CS f 1 kHz Ri 10 kQ 65 dB NOISE PERFORMANCE Voltage Noise Density en f 1 kHz 45 nV A Hz f 10 kHz 30 nV VHz Current Noise Density in f 1kHz 0 05 pANHz Specifications subject to change without notice REV A AD8591 AD8592 AD8594 ABSOLUTE MAXIMUM RATINGS Supply Voltage 2 ee a eee eee 6 V Input Voltage ss am aaa nen GND to Vs Differential Input Voltage o oo oooomoooom t6V Output Short Circuit Duration to GND Storage Temperature Range R RT RM RU Packages Operating Temperature Range AD8591 AD8592 AD8594 Junction Temperature Range R RT RM RU Packages Lead Temperature Range Soldering 60 sec NOTES Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating condi Observe Derating Curves Solis wit SOR s 65 C to 150 C TORT 40 C to 85 C 65 C to 150 C Tm 300
22. ver applica tions without changing the circuit gain of 1 R3 A1 A2 1 2 AD8592 R3 GAIN R2 SET R7 R10 R11 R2 SET R6 R12 R13 R3 Fi f D 8an se oltage equal to half of the supply voltage C1 is used to couple the input signal and can be omitted if the input s dc voltage is equal to half of the supply voltage y Differential The circuit can also be configured to provide additional gain if desired The gain of the circuit is Vour R3 Ay UE R2 Where Vour Voi Voz R2 R7 R10 RII and R3 R6 R12 R13 11 AD8591 AD8592 AD8594 SPICE Model for the AD8591 AD8592 AD8594 Amplifier The SPICE model for the AD8591 AD8592 AD8594 amplifier is one of the more realistic computer simulation macro models available providing a high degree of realism with respect to char acteristics of the actual amplifier This model shown in Listing 1 is based on typical values for the device and can be downloaded from Analog Devices Internet site at www analog com The model uses a common source output stage to provide rail to rail performance This allows realistic simulation of open loop gain dependency on load resistance as well as maximum output voltage versus output current Two differential pairs are used in the input stage of the model simulating the rail to rail input stage of the AD8591 AD8592 AD8594 amplifier The EOS voltage source establishes the input offset voltage and is also u
23. width Product GBP 2 2 MHz Phase Margin Do 67 Degrees Channel Separation CS f 1 kHz R 2 KQ 65 dB NOISE PERFORMANCE Voltage Noise Density en f 1kHz 45 nV VHz f 10 kHz 30 nV VHz Current Noise Density ls f 1 kHz 0 05 pA VHz Specifications subject to change without notice 2 REV A AD8591 AD8592 AD8594 ELECTRICAL CHARACTERISTICS Vs 5 0 V Vey 2 5 V Ty 25 C unless otherwise noted Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage Vos 2 25 mV 40 C lt T4 lt 85 C 30 mV Input Bias Current Ig 5 50 pA 40 C lt Ta lt 85 C 60 pA Input Offset Current los 1 25 pA 40 C lt Ta lt 85 C 30 pA Input Voltage Range 0 5 V Common Mode Rejection Ratio CMRR Vem 0V to 5 V 38 47 dB Large Signal Voltage Gain Avo Ri 2 kQ Vo 0 5 V to 4 5 V 15 30 V mV Offset Voltage Drift AVos AT 40 C lt T4 lt 85 C 20 uV C Bias Current Drift AIg AT 50 fA C Offset Current Drift Alos AT 20 fA C OUTPUT CHARACTERISTICS Output Voltage High Vou IL 10mA 4 9 4 94 V 40 C to 85 C 4 85 V Output Voltage Low Vor Ii 10mA 50 100 mV 40 C to 85 C 125 mV Output Current Tour 250 mA Open Loop Impedance Zout f 1 MHz Ay 1 40 Q POWER SUPPLY Power Supply Rejection Ratio PSRR Vs 2 5 V to 6 V dB Supply Current Amplifier Isy mA mA Supply Gur t de uA uA SDI mA Ispz Amplifier 2 Shut Down AD8592 mA SHUTDOWN INPUTS Logic High Voltage Vnu 40 C lt Ta l
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ANALOG DEVICES AD8591/AD8592/AD8594 handbook