NATIONAL SEMICONDUCTOR - LMH2180 75 MHz Dual Clock Buffer handbook
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1. 8X 0 251 Dog feat 6x 6 5 RECOMMENDED LAND PATTERN AREA p 6X 0 51 NCP N 1 INDEX DIMENSIONS ARE IN MILLIMETERS DIMENS ONS IN lt FOR REFERENCE ONLY 1 ex 0 510 1 8 8 LLP Rev 8x 0 Uo 18 0 665 S1 x 54 NS Package Number SDA08A 6 0 5 Rev www national com 14 Notes www national com 08LCHW 1 LMH2180 75 MHz Dual Clock Buffer Displays Ethernet Interface Notes For more National Semiconductor product information and proven design tools visit the following Web sites at LVDS Power Management www national com ethernet Packaging www national com packaging www national com interface Quality and Reliability www national com quality www national com lvds Reference Designs www national com refdesigns Switching Regulators LDOs LED Lighting PowerWise www national com switchers www national com Ido www national com led www national com power Feedback www national com feedback www national com sdi www national com tempsensors www national com wireless THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTO2. 3 dB 1 amp LSBW Large Signal Bandwidth Vin 1 0 Vpp 3 dB e GFN Gain Flatness lt 0 1 dB f gt 100 kHz Distortion and Noise Performance Phase Noise Vin 1 Vpp fo 38 4 MHz Af 1 128 Input Referred Voltage Noise H 1MHz Reounce 502 nVA Hz EC ns ns ns 96 V us Enabl nable gt Vpp No Load mA Enable V 2 1 Enable Vas No HA Load Enable Vss No Load 1 2 ss 3 www national com 08LCHW 1 LMH2180 V V Parameter Conditions Typ Max 7 Note 6 Note 7 Power Supply Rejection Ratio C 3 0V to 5 0V ccc 1 0 22 Offset Voltage Note 9 mom v Input Resistance per Buffer Enable Jod Te MHz Jae desc E 4 95 x 50 Output Short Circuit Current Sourcing Vi Vout Vss Notes 10 11 Sinking Vin Vss en hmin Enable High Active Minimum Voltage Enable High Active Minimum Voltage Active Minimum imax Enable Low Inactive Maximum V Voltage Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur including inoperability and degradation of the device reliability and or performance Function
3. Supply Current Enable 5 No Load 23 2 7 mA 2 9 E 3 nable Enable Vgg No 13 1 5 mA Load 1 6 Enable z Vas No Load ENS m Power Supply Rejection Ratio DC 3 0V to 5 0V 64 Small Signal Voltage Gain Vin 0 2 095 10 1 05 vv Output Offset Voltage 17 Temperature Coefficient Output Offset Voltage Note 9 Output Resistance f 100 kHz os a 7384 MHz 1 www national com 2 Symbol Parameter Conditions Min Typ Max Units Note 7 Note 6 Note 7 Miscellaneous Performance Rin Input Resistance per Buffer Enable kQ Input Capacitance per Buffer Enable Vpp ar pF Zin Input Impedance id V 2 Output Swing Negative mV lsc Output Short Circuit Current Sourcing Vin Vpp Vout Vss Notes 10 11 Sinking Vin Vss Ven hmin Enable High Active Minimum Voltage Ven imax Enable Low Inactive Maximum V Voltage 5V Electrical Characteristics Unless otherwise specified all limits are guaranteed for 25 C 5V Vss OV Voy 1V Enable gt C 10 pF 30 Load is connected to 10 nF Boldface limits apply at temperature range extremes of operating condition See Note 2 Symbol Parameter Conditions Min Typ Max Units Note 7 Note 6 Note 7 Frequency Domain Response SSBW Small Signal Bandwidth Vin 100
4. 20 25 30 35 40 45 50 55 VsuPPLY V 30024621 IsuppL v VS Vsuppi v No Load Enable 2 Vas 25 30 35 40 45 50 55 Vguppcy V 30024623 Vos VS Vsuppty VsuPPLY V 30024625 IsuPPLY mA PSRR dB Rour Q 300 250 200 150 100 50 Isuppy VS Vsuppy No Load Enable4 Vop Enables Vss 0 0 20 25 3 0 35 40 45 50 55 V 30024622 PSRR vs Frequency 10k 100k FREQUENCY Hz 30024624 Rout VS Frequency FREQUENCY Hz 30024626 www national com 08LCHW 1 LMH2180 IMPEDANCE kQ Vout V Vout Input Impedance vs Frequency 150 120 90 60 30 10k 100k 1M 10M 100M FREQUENCY Hz 30024627 Vout VS Sourcing Open Input Vs 5V 9 90 80 70 60 50 40 30 20 10 0 lout mA 30024629 Vout VS lour Sinking Open Input Vs 5 lout mA 30024632 Vout VS lour Sourcing Vout V Open Input Vs 2 7V 25 20 15 10 5 0 lout mA 30024628 Vout 5 lour Sinking Open Input V
5. 70 Vs 2 7 or 5V 80 VIN 1 fc 38 4 MHz 90 100 110 Limited number of samples 120 1 30 Mean 30 140 150 10 100 1k 10k 100k 1M Gain Flatness lt 0 1 dB GFN 0 5 100k 1M 10M 100M FREQUENCY Hz 30024610 Phase Noise OFFSET FREQUENCY Hz 30024612 Crosstalk Rejection vs Frequency IN NY 0 100k 1M 10M 100M FREQUENCY Hz 30024614 www national com 08LCHW 1 Transient Response Positive LMH2180 Vout mV 0 20 40 60 80 100 120 140 160 TIME ns 30024615 Small Signal Pulse Response Vour mV 0 200 400 600 800 1000 30024617 Vour V TIME ns 30024619 Vour mV Transient Response Negative 1100 1075 1050 1025 1000 975 0 20 40 60 80 100 120 140 160 TIME ns 30024616 Small Signal Pulse Response gt 2 o gt 0 200 400 600 800 1000 TIME ns 30024618 gt gt 0 200 400 600 800 1000 30024620 www national com 0 mA IsuppLy Vos mV IsuppL v VS Vsuppi v No Load Enable 2 0 0
6. eliminate problems and will optimize the performance of the LMH2180 It is best to have the same ground plane on the PCB for all decoupling and other ground connections To ensure a clean supply voltage it is best to place decoupling capacitors close to the LMH2180 between and Vas Another important issue is the value of the components be cause this also determines the sensitivity to disturbances Resistor values have to be low enough to avoid a significant noise contribution and large enough to avoid a significant in crease in power consumption while loading inputs or outputs to heavily E5052A B LMH6559 Signal Source 10 nF Analyzer Buffer for driving 500 30024647 FIGURE 5 Measurement Setup www national com 08LCHW 1 LMH2180 Physical Dimensions inches millimeters unless otherwise noted 8x 0 8X 0 75 ke RECOMMENDED LAND PATTERN 1 1 RATIO WITH PKG SOLDER PADS 9 0 qii EE poe PIN 1 IND X AREA 0 2 45 0 25 B 1 4 PIN 1 1D 320 1 0000 Y al E E k BK 0 2540 05 0 035 0 110 i SOLDER BJMF 0 1m c 4 amp BS AAE 15 8 Pin LLP NS Package Number YDA08A DIMENSIONS ARE IN MILLIMETERS DIMENSIONS IN FOR REFERENCE ONLY i 10 1 6 UD
7. 00k 1M 10M 100M FREQUENCY Hz 30024603 Frequency Response Over Temperature D 3 0 3 2 lt 6 5 9 12 FVN 0 1Vp 15 100k 1M 10M 100M FREQUENCY Hz 30024605 Phase Response Over Temperature Lid MENA N lt FREQUENCY Hz 30024607 PHASE Phase Response 100k 1M 10M 100M FREQUENCY Hz 30024604 Frequency Response Over Temperature GAIN dB PHASE 5 100k 1M 10M 100M FREQUENCY Hz 30024606 Phase Response Over Temperature 100k 1M 10M 100M FREQUENCY Hz 30024608 www national com VOLTAGE NOISE nV VHz GAIN dB ISOLATION dB Large Signal Bandwidth FREQUENCY Hz 30024609 Voltage Noise 100 1k 10k 100k 1M FREQUENCY Hz 30024611 Isolation Output to Input vs Frequency S 0 100k 1M 10 FREQUENCY Hz 30024613 NORMALIZED GAIN dB PHASE NOISE dBc Hz CROSSTALK REJECTION dB
8. 44 0 870 850 4288 National Semiconductor Japan Technical Support Center Email jpn feedback 9 nsc com www national com
9. National Semiconductor LMH2180 75 MHz Dual Clock Buffer General Description The LMH2180 is a high speed dual clock buffer designed for portable communications and applications requiring multiple accurate multi clock systems The LMH2180 integrates two 75 MHz low noise buffers with independent shutdown pins into a small package The LMH2180 ensures superb system operation between the baseband and the oscillator signal path by eliminating crosstalk between the multiple clock sig nals Unique technology and design provides the LMH2180 with the ability to accurately drive both large capacitive and resis tive loads Low supply current combined with shutdown pins for each channel means the LMH2180 is ideal for battery powered applications The LMH2180 s rapid recovery after disable optimizes performance and current consumption This part does not use an internal ground reference thus pro viding additional system flexibility The LMH2180 operates both with single and split supplies The flexible buffers provide system designers the capacity to manage complex clock signals in the latest wireless applica tions Each buffer delivers 106 V us internal slew rate with independent shutdown and duty cycle precision The patent ed analog circuit of each buffer drives capacitive loads greater than 20 pF Each input is internally biased to 1V removing the need for external resistors Both channels have rail to rail inputs and outputs a gain of one
10. Note 9 Average Temperature Coefficient is determined by dividing the changing in a parameter at temperature extremes by the total temperature change Note 10 Short Circuit test is a momentary test Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150 C Note 11 Positive current corresponds to current flowing into the device www national com 4 Block Diagram Vpp ENABLE 1 IN 1 OUT 1 IN 2 OUT 2 ENABLE 2 Vss 30024601 Pin Descriptions Pin No PinName Description Voltage supply connection input input 2 Ground connection lt o ENABLE 1 Enable buffer 1 Connection Diagram 8 Pin LLP ENABLE 1 IN 1 OUT 1 DEVICE CODE IN 2 OUT 2 ENABLE 2 Vss 30024631 Top View Ordering Information Package Part Number Package Marking Transport Media NSC Drawing 8 Pin LLP 1k Units Tape and Reel LMH2180YD Solder Bump 4 5k Units Tape and Reel Pi 1k Units Tape and Reel 8 Pin LLP LMH2180SD 5 Pullback LMH2180SDX 4 5 Units Tape and Reel 5 www national com 08LCHW 1 LMH2180 Typical Performance Characteristics 25 C Vp 27v Vss OV Enable Vpp C 10 pF 30kQ and 10 unless otherwise specified Frequency Response 6 0 3 z lt 5 5 9 12 VIN 0 1Vpp 15 1
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12. S ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein Life support devices or systems are devices which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation All other brand or product names may be trademarks or registered trademarks of their respective holders Copyright 2008 National Semiconductor Corporation For the most current product information visit us at www national com National Semiconductor Asia Pacific Technical Support Center Email ap support nsc com National Semiconductor Americas Technical Support Center Email new feedback nsc com Tel 1 800 272 9959 National Semiconductor Europe Technical Support Center Email europe support nsc com German Tel 49 0 180 5010 771 English Tel
13. al operation of the device and or non degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions All voltages are measured with respect to the ground pin unless otherwise specified Note 2 The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and or Notes Typical specifications are estimations only and are not guaranteed Note 3 The maximum power dissipation must be derated at elevated temperatures and is dictated by ymax and the ambient temperature T The maximum allowable power dissipation is Tymax Ta 84 or the number given in the Absolute Maximum Ratings whichever is lower Note 4 Human body model applicable std JESD22 A114C Note 5 Machine model applicable std JESD22 A115 A Note 6 Typical values represent the most likely parametric norms at T4 25 C and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed Note 7 Datasheet min max specification limits are guaranteed by test or statistical analysis Note 8 Slew rate is the average of the rising and falling slew rates
14. and are AC coupled with the use of one capacitor Replacing a discrete buffer solution with the LMH2180 pro vides many benefits simplified board layout minimized par asitic components simplified BOM design durability across multiple applications simplification of clock paths and the ability to reduce the number of clock signal generators in the system The LMH2180 is produced in the tiny 8 pin LLP solder bump and no pullback packages minimizing the required PCB space National s advanced packaging offers direct PCB IC evaluation via pin access Typical Application Enable 1 VCTCXO a Enable 2 January 24 2008 Features Typical values are 2 7V and C 10 pF unless otherwise specified m Small signal bandwidth 78 MHz m Supply voltage range 2 4V to 5V m Phase noise 1 Vpp 123dBc Hz 38 4 MHz Af 1kHz Slew rate 106 V us Total supply current 2 3 mA Shutdown current 30 pA Rail to rail input and output Individual buffer enable pins Rapid T technology Crosstalk rejection circuitry 8 pin LLP pin access packaging Temperature range 40 C to 85 C Applications 3G mobile applications WLAN WiMAX modules m TD_SCDMA multi mode and camera GSM modules Oscillator modules LOAD2 30024602 2008 National Semiconductor Corporation 300246 www national com ng 490 9 ZHIN SZ 081 LMH2180 Absolute Maximum Ratings N
15. his uncer tainty is described by jitter time domain or phase noise frequency domain Communication systems such as Wire less LAN require a low jitter phase noise clock signal to obtain a low Bit Error Rate Figure 4 shows the frequency do main representation of a clock signal with frequency fc With out Phase Noise the entire signal power would only be located at the frequency fc Phase Noise spreads some of the power to adjacent frequencies Phase Noise is usually specified in dBc Hz at a given frequency offset Af from the carrier where dBc is the power level in dB relative to the carrier The noise power is measured within a 1Hz bandwidth Phase Noise dBc Hz POWER dB BW 1Hz FREQUENCY Hz 30024648 FIGURE 4 Phase Noise Enable 1 10 nF 38 4 MHz Enable 2 Figure 5 shows the setup used to measure the LMH2180 phase noise The clock driving the LMH2180 is a state of the art 38 4MHz TCXO Both the TCXO phase noise and the phase noise at the LMH2180 output were measured At offset frequencies of 1 2 and higher from the carrier the phase noise is sufficiently low to accurately calculate the LMH2180 contribution to the phase noise at the output The LMH6559 whose phase noise contribution can be neglected is used to drive the 50Q input impedance of the Signal Source Analyzer LAYOUT DESIGN RECOMMENDATION Careful consideration during circuit design and PCB layout will
16. ote 1 Junction Temperature Note 3 150 C a Soldering Information If Military Aerospace specified devices are required 2 please contact the National Semiconductor Sales Office Infrared or Convection 35 sec 235 C Distributors for availability and specifications ti Rati Supply Voltages V V 5 5V pera ing a ings Note 1 ESD Tolerance Supply Voltage V V 2 4V to 5 0V Human Body Note 4 2000V Temperature Range Notes 2 3 40 C to 85 C Machine Model Note 5 200V Package Thermal Resistance Notes 2 3 Charged Device Model 1000V LLP 8 8 4 217 C W Storage Temperature Range 65 C to 150 C 2 7V Electrical Characteristics Unless otherwise specified all limits are guaranteed for 25 C 2 7V Vss OV Vow 1V Enable C 10 pF 30 Load is connected to 10 nF Boldface limits apply at temperature range extremes of operating condition See Note 2 Symbol Parameter Conditions Min Typ Max Units Note 7 Note 6 Note 7 Frequency Domain Response SSBW Small Signal Bandwidth 100 3 dB z LSBW Large Signal Bandwidth 1 0 Vpp 3 dB e m GFN Gain Flatness 0 1 dB f 100 kHz 49 Distortion and Noise Performance Phase Noise dBc Hz Input Referred Voltage Noise f 1MHz 500 se Rise Time 0 1 Vpp Step 10 90 ns ns ns
17. oupling of the input signal This biasing avoids the use of external resistors as depicted in Figure 1 The biasing prevents a large DC load at the oscillators output that creates a load impedance and may affect it s oscillating frequency As a result of this biasing the maximum amplitude of the AC signal is 2Vpp The coupling capacitance C1 should be large enough to let the AC signal pass This is a unity gain buffer with rail to rail inputs and outputs VDD ENABLE OUT Vss 30024644 FIGURE 1 Input Configuration FREQUENCY PULLING Frequency pulling is the frequency variation of an oscillator caused by a varying load In the typical application the load of the oscillator is a fixed capacitor C1 in series with the input impedance of the buffer To keep the input impedance as constant as possible the in put is biased at 1V even when the part is disabled A simpli fied schematic of the input configuration is shown in Figure 1 ISOLATION AND CROSSTALK Output to input isolation prevents the clock signal of the os cillator from being affected by spurious signals generated by the digital blocks behind the output buffer See the charac teristic graphic entitled Isolation Output to Input vs Frequen cy A block diagram of the isolation is shown in Figure 2 Crosstalk rejection between buffers prevents signals from af fecting each other Figure 2 shows a Baseband IC and a Bluetooth module as an example See the cha
18. out V 0 5 10 15 20 25 lout mA 30024630 lgc Sourcing vs Over Temperature lsc mA 100 120 2 5 VsuPPLv V 30024633 www national com 10 lgc mA IsuPPLY mA Sinking vs Vsypp Over Temperature 100 2 5 3 0 3 5 4 0 4 5 5 0 Vguppcy V 30024634 IsuppLv VS VENABLE 79 0 0 4 08 12 16 2 0 VENABLE V 30024636 IsuppLy MA IsuppL v VS VENABLE ENABLE V No Load 30024635 11 www national com 08LCHW 1 LMH2180 Application Information GENERAL The LMH2180 is designed to minimize the effects of spurious signals from the base chip to the oscillator Also the influence of varying load resistance and capacitance to the oscillator is minimized while the drive capability is increased The inputs of the LMH2180 are internally biased at 1V mak ing AC coupling possible without external bias resistors To optimize current consumption a buffer that is not in use can be disabled by connecting it s enable pin to Vas The LMH2180 has no internal ground reference therefore either single or split supply configurations can be used The LMH2180 is an easy replacement for discrete circuitry It simplifies board layout and minimizes the effect of layout re lated parasitic components INPUT CONFIGURATION The internal 1V input biasing allows AC c
19. racteristic graphic labeled Crosstalk Rejection vs Frequency for more information LMH2180 VCTCXO Clam FIGURE 2 Isolation Block Diagram Isolation Crosstalk IN 2 1 1 1 WLAN OUT 2 30024645 DRIVING CAPACITIVE LOADS Each buffer can drive a capacitive load Be aware that every capacitor directly connected to the output becomes part of the loop of the buffer In most applications the load consists of the capacitance of copper tracks and the input capacitance of the application blocks Capacitance reduces the gain phase mar gin and decreases the stability This leads to peaking in the frequency response and in extreme situations oscillations can occur To drive a large capacitive load it is recommended to include a series resistor between the buffer and the load ca pacitor The best value for this isolation resistance can be found by experimentation The LMH2180 datasheet reflects measurements with capac itive loads of 10 pF at the output of the buffers Most common applications will probably use a lower capacitive load which will result in lower peaking and significantly greater band width see Figure 3 9 6 3 0 GAIN dB FREQUENCY Hz 30024646 FIGURE 3 Bandwidth and Peaking www national com 12 PHASE NOISE A clock buffer adds noise to the clock signal This noise caus es uncertainty in the phase of the clock signal T
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NATIONAL SEMICONDUCTOR LMH2180 75 MHz Dual Clock Buffer handbook