intel 8XC152JA/JB/JC/JD Manual
Contents
1. PRELIMINARY 15 LI 8XC152JA JB JC JD intel GSC TIMINGS EXTERNAL CLOCK EXTERNAL CLOCK i ECL lt ECH I gt dM ECDVT TRANSMIT DATA X X I ECDHT I EXTERNAL CLOCK ECDSR ECDHR i I I RECEIVE DATA X X I I I 270431 17 NOTES 1 N C pins on PLCC package may be connected to internal die and should not be used in customer applications 2 It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices 3 Typicals are based on samples taken from early manufacturing lots and are not guaranteed The measurements were made with Vcc 5V at room temperature 4 Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vo s of ALE and Ports 1 and 3 The noise is due to external bus capacitance discharging into the Port O and Port 2 pins when these pins make 1 to 0 transitions during bus operations In the worst cases capacitive loading gt 100 pF the noise pulse on the ALE pin may exceed 0 8V In such cases it may be desirable to qualify ALE with a Schmitt Trigger or use an address latch with a Schmitt Trigger STROBE input 5 Capacitive loading on Ports 0 and 2 may cause the on ALE and PSEN to momentarily fall below the 0 9Vcc specifi cation when the address bits are stabilizing 6 Icc is measured with all output pins disconnected XTAL12. Program De6ru Mode Memory ALE PSEN Port 0 Port 1 Port 2 Port 3 Port 4 Idle Internal 1 1 Data Data Data Data Data Idle External 1 1 Float Data Address Data Data Power Down Internal 0 0 Data Data Data Data Data Power Down External 0 Ot Float Data Data Data Data 80C152JB 80C152JD Mode ALE PSEN EPSEN 10 11 Port2 Port3 Port4 Port5 6 Idle PO P2 1 1 1 Float Data Address Data Data OFFH OFFH Idle P5 P6 1 1 1 Data Data Data Data Data OFFH Address Power Down PO P2 0 1 Float Data Data Data Data OFFH OFFH Power Down P5 P6 0 17 0 Data Data Data Data Data OFFH OFFH NOTE For more detailed information on the reduced power modes refer to the Embedded Controller Handbook and Application Note AP 252 Designing with the 80C51BH TNote difference of logic level of PSEN during Power Down for ROM JA JC and ROM emulation mode for JC JD PRELIMINARY 8XC152JA JB JC JD ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias 0 C to 70 C Storage Temperature 65 C to 150 C Voltage on Any pin to Vss 0 5V to Vcc 0 5V Voltage on Vcc to 55 0 5V to 6 5V Power Dissipation 1 0W 9 intel NOTICE This data sheet contains preliminary infor mation on new products in production The specifica tions are subject to change without notice Verify with your local Intel Sales office that you have th
3. 852A IMINARY intel PRELIMINAR 8XC152JA JB JC JD UNIVERSAL COMMUNICATION CONTROLLER 8 BIT MICROCONTROLLER W 8K Factory Mask Programmable ROM Available W Superset of 80C51 Architecture m 64KB Data Memory Addressing m Multi Protocol Serial Communication m 256 Bytes On Chip RAM 1 O Port 2 048 Mbps 2 4 Mbps Max Chi SDLC HDLC Only m Dual On Chip DMA Channels CSMA CD and SDLC HDLC m Hold Hold Acknowledge User Definable Protocols m Two General Purpose Timer Counters m Full Duplex Half Duplex 50r 7 1 0 Ports m MCS 51 Compatible UART W 56 Special Function Registers m 16 5 MHz Maximum Clock Frequency m 11 Interrupt Sources m Multiple Power Conservation Modes m Available in 48 Pin Dual in Line Package m 64KB Program Memory Addressing and 68 Pin Surface Mount PLCC Package See Packaging Spec Order 231369 The 80C152 which is based on the MCS 51 CPU is a highly integrated single chip 8 bit microcontroller designed for cost sensitive high speed serial communications It is well suited for implementing Integrated Services Digital Networks ISDN emerging Local Area Networks and user defined serial backplane applica tions In addition to the multi protocol communication capability the 80C152 offers traditional microcontroller features for peripheral I O interface and control Silicon implementations are much more cost effective than multi wire cables found in board level parallel to serial and serial to pa
4. g HLD HLDA i 8 T o M 1 On 80C152JB JD Only 270431 18 Figure 2 Block Diagram PRELIMINARY 3 8XC152JA JB JC JD 80C152JB JD General Description The 80C152JB JD is a ROMIess extension of the 80C152 Universal Communication controller The 80C152JB has the same five 8 bit I O ports of the 80C152 plus an additional two 8 bit I O ports Port 5 and Port 6 The 80C152JB JD also has two addi tional control pins EBEN EPROM Bus ENable and EPSEN EPROM bus Program Store ENable EBEN selects the functionality of Port 5 and Port 6 intel EPSEN is used in conjunction with Port 5 and Port 6 program memory operations EPSEN functions like PSEN during program memory operation but sup ports Port 5 and Port 6 EPSEN is the read strobe to external program memory for Port 5 and Port 6 EPSEN is activated twice during each machine cycle unless an external data memory operation occurs on Port s O and Port 2 When external data memory is accessed the second activation of EPSEN is skipped which is the same as when using PSEN Note that data memory fetches cannot be made When EBEN is low these ports are strictly simi lar to Port 4 The SFR location for Port 5 is 91H and Port 6 is OA1H This means Port 5 and Port 6 are not bit addressable With EBEN low all program memo ry fetches take place via Port 0 and Port 2 The 80C152 is a ROMIes
5. DATA SHEET REVISION SUMMARY The following represent the key differences between the 003 and the 002 version of the 80C152 83C152 data sheet Please review this summary carefully 1 Removed minimum GSC frequency spec when used with an external clock 2 Change figure External Program Memory Read Cycle to show Port 0 Port 5 address floating after PSEN goes low Added design note on terminating idle with reset Added status of PSEN during Power Down mode to Table 3 Moved all notes to back of data sheet Changed microcomputer to microcontroller O OQ o Added External Oscillator start up capacitance note The following represent the key differences between the 002 and the 001 version of the 80C152 83C152 data sheet Please review this summary carefully 1 Status of data sheet changed from ADVANCED to PRELIMINARY 80C152JC 83C152JC and 80C152JD were added Added AE RDN design note This revision summary was added Note 13 was added Effective ECL spec at higher clock rates Table 2 changed to Table 3 Status of pins during Idle Power Down Current Table 2 was added JA vs JB vs JC vs JD matrix Transmit jitter spec changed from 35 ns and 70 ns to 10 ns O WO Im PRELIMINARY 17
6. SHIFT REGISTER MODE TIMING WAVEFORMS INSTRUCTION 0 1 2 3 4 5 6 7 8 F TXLXL mravi ie TXHOX OUTPUT DATA N X X 2 A X 4 KS X X Rp ll TXHDX I 4 WRITE TO SBUF sET TI NEL AT vario X VALI D CLEAR RI SET RI 270431 12 A C TESTING INPUT OUTPUT WAVEFORMS FLOAT WAVEFORM Vec70 5 ne VU Vi 0 1 V 0 1 se VLOAD MING REFERENCE gt 0 2 Vcc70 1 POINTS 0 45 Vi oAp7 0 1 V Vg 0 1 V 270431 13 270431 14 NET For Timing Purposes a Port Pin is no Longer Floating when a AC Inputs During Testing ars piven at Vcc 0 6 for a Logic 1 100 mV change from Load Voltage Occurs and Begins to Float and 0 45V for a Logic 0 Timing Measurements are made at when 100 mV change from the Loaded Vor VoL Level occurs Min for a Logic 1 and Max for a Logic 0 loL lou 20 mA PRELIMINARY 13 8XC152JA JB JC JD intel GLOBAL SERIAL PORT TIMINGS Internal Baud Rate Generator 16 5 MHz BAUD 0 Variable Oscillator Symbol Parameter Unit Min Max Min Max HBTJR Allowable jitter on 0 0375 0 125 x ps the Receiver for 1 BAUD 1 bit time Manchester 8TCLCL encoding only 25ns FBTJR Allowable jitter on 0 10 0 25 x ps the Receiver for one BAUD 1 x full bit time NRZI 8TCLCL and Manchester 25 ns HBTJT Jitter of data from 10 10
7. Outputs 80 pF EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS Note 7 10 Symbol Parameter 16 5 MHz Variable Oscillator Unit Min Max Min Max 1 TCLCL Oscillator Frequency 3 5 12 MHz 80C152JA JC 83C152JA JC 80C152JB JD 80C152JA JC 1 3 5 16 5 MHz 83C152JA JC 1 80C152JB JD 1 TLHLL ALE Pulse Width 81 2TCLCL 40 ns TAVLL Address Valid to ALE Low 5 TCLCL 55 ns TLLAX Address Hold After ALE Low 25 TCLCL 35 ns TLLIV ALE Low to Valid 142 A4TCLCL 100 ns Instruction In TLLPL ALE Low to PSEN Low 20 TCLCL 40 ns TPLPH PSEN Pulse Width 137 3TCLCL 45 ns TPLIV PSEN Low to Valid 77 8TCLCL 105 ns Instruction In TPXIX Input Instruction 0 0 ns Hold After PSEN TPXIZ Input Instruction 35 TCLCL 25 ns Float After PSEN TAVIV Address to Valid 198 5TCLCL 105 ns Instruction In TPLAZ PSEN Low to Address 10 10 ns Float TRLRH RD Pulse Width 263 6TCLCL 100 ns TWLWH WR Pulse Width 263 6TCLCL 100 ns TRLDV RD Low to Valid 138 5TCLCL 165 ns Data In TRHDX Data Hold After RD 0 0 ns TRHDZ Data Float After RD 51 2TCLCL 70 ns TLLDV ALE Low to Valid 335 8TCLCL 150 ns Deta In TAVDV Address to Valid 380 9TCLCL 165 ns Deta In TLLWL ALE Low to RD or 132 232 STCLCL 50 STCLCL 50 ns WR Low TAVWL Address to RD or 112 ATCLCL 130 ns WR Low TQVWX 8 Data Valid to WR 196 6TCLCL 167 ns Transition TWHQX Data Hold After WR 10 TCLCL 50 ns TRLAZ RD Low to Address 0 0 n
8. 152JA JB JC JD DESIGN NOTES Within the 8XC152 there exists a race condition that may set both the RDN and AE bits at the end of a valid reception This will not cause a problem in the application as long as the following steps are followed Never give the receive error interrupt a higher priority than the valid reception interrupt Do not leave the valid reception interrupt service routine when AE is set by using a RETI instruction until AE is cleared To clear AE set the GREN bit this enables the receiver If the user desires that the receiver remain disabled clear GREN after setting it before leaving the interrupt service routine lf the AE bit is checked by user software in response to a valid reception interrupt the status of AE should be considered invalid The race condition is dependent upon both the temperature that the device is currently operating at and the processing the device received during the wafer fabrication When the idle mode is terminated by a hardware reset the device normally resumes program execution from where it left off up to two machine cycles before the internal reset algorithm takes control On chip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write when Idle is terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory
9. 2 Port 2 is an 8 bit bidirectional I O port with internal pullups Port 2 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 2 pins that are externally being pulled low will source current lj on the data sheet because of the internal pullups Port 2 emits the high order address byte during fetches from external Program Memory if EBEN is pulled low During accesses to external Data Memory that use 16 bit addresses MOVX DPTR and DMA operations Port 2 emits the high order address byte In these applications it uses strong internal pullups when emitting 1s During accesses to external Data Memory that use 8 bit addresses MOVX Ri Port 2 emits the contents of the P2 Special Function Register Port 2 also receives the high order address bits during program verification 10 17 14 16 18 19 23 25 Port 3 Port 3 is an 8 bit bidirectional I O port with internal pullups Port pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are externally being pulled low will source current lj on the data sheet because of the pullups Port 3 also serves the functions of various special features of the MCS 51 Family as listed below Pin Name Alternate Function P3 0 P3 1 RXD TXD P3 2 INTO P3 3 4 TO P3 5 T1 P3 6 WR P3 7 RD Ser
10. C152JA 38 ALE 80 152 N C INTO P3 2 12 80C152JC 370 PSEN N C INT1 30 P2 INTi P3 3 15 83C152JC se 3P2 7 A15 83C152JC N C 0 P3 4 O14 P2 6 A14 N C P3 5 15 P2 5 13 P2 7 WR P3 6 16 2 4 A12 P2 6 RD P3 7 17 2 3 11 2 5 A DO Po o 18 P2 2 A10 P2 4 A D1 P0 1 19 P2 1 A9 P2 3 A D2 0 2 220 P2 0 A8 Sa 8 s nn 3 3 O S 5 n 5 9 9 4 02 8 UUUUUUUUUUUUUUUUU A D3 Po s 21 7 A D7 Que A MSN E io as e Riu God Goes XTAL2 22 6 A D6 PRE SSA PPS Paces ee XTAL1 23 PO 5 A D5 QE vss Cf 24 255 P0 4 4704 270431 2 270431 1 WOES PTY 2 CORNER k k KK Kk k gt gt e e e 2 2 2 2 Z OH 9 rt O m G G 593992 P1 6 O P4 5 P1 7 O P4 6 EBEN P4 7 RESET P6 3 P3 0 O EA P3 1 ALE P3 2 E TOP VIEW PSEN P5 0 O EPSEN 80C152JB D ed 80C152JD Hs P510 P6 4 P5 2 O PS P5 3 O P2 7 P3 5 O P2 6 P3 6 C P2 5 P3 7 O P2 4 N C E P2 3 o o r Q AN rm m rm YM m nm HY pIuuuusuUuuUuuuuUuuUuuu go C2sSggR RPRPPPPROPCIZSE 270431 3 Figure 1 Connection Diagrams PRELIMINARY a intel e 8XC152JA JB JC JD d E U Ryp que Fe 4 i Typ L 7 GLOBAL g SERIAL CHANNEL i d D
11. cation it uses strong pullups when emitting 1s N A 67 66 52 57 50 68 1 51 Port 6 Port 6 is an 8 bit bidirectional I O port with internal pullups Port 6 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 6 pins that are externally pulled low will source current lj on the data sheet because of the internal pullups Port 6 emits the high order address byte during fetches from external Program Memory if EBEN is pulled high In this application it uses strong pullups when emitting 1s N A 12 EBEN E Bus Enable input that designates whether program memory fetches take place via Ports 0 and 2 or Ports 5 and 6 Table 1 shows how the ports are used in conjunction with EBEN N A 53 EPSEN E bus Program Store Enable is the Read strobe to external program memory when EBEN is high Table 2 shows when EPSEN is used relative to PSEN depending on the status of EBEN and EA PRELIMINARY intel OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output respec tively of an inverting amplifier which can be config ured for use as an on chip oscillator as shown in Figure 3 To drive the device from an external clock source XTAL1 should be driven while XTAL2 is left uncon nected as shown in Figure 4 There are no require ments on the duty cycle of the external clock signal since the input to the inte
12. cess to external Data Memory While in Reset ALE remains at a constant high level 37 54 PSEN Program Store Enable is the Read strobe to External Program Memory When the 8XC152 is executing from external program memory PSEN is active low When the device is executing code from External Program Memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to External Data Memory While in Reset PSEN remains at a constant high level 39 56 EA External Access enable EA must be externally pulled low in order to enable the 8XC152 to fetch code from External Program Memory locations 0000H to OFFFH EA must be connected to for internal program execution 23 32 XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generating circuits 22 31 XTAL2 Output from the inverting oscillator amplifier N A 17 20 21 22 38 39 40 49 Port 5 Port 5 is an 8 bit bidirectional I O port with internal pullups Port 5 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 5 pins that are externally being pulled low will Source current li on the data sheet because of the internal pullups Port 5 is also the multiplexed low order address and data bus during accesses to external program memory if EBEN is pulled high In this appli
13. driven with TCLCH TCHCL 5 ns Vj Vss 0 5V Vcc 0 5V XTAL2 N C Port 0 pins connected to Operating current is measured with EA connected to and RST connected to Vgs Idle current is measured with EA connected to Vss RST connected to Vcc and GSC inactive 7 The specifications relating to external data memory characteristics are also applicable to DMA operations 8 TQVWX should not be confused with TQVWX as specified for 80C51BH On 80C152 TQVWX is measured from data valid to rising edge of WR On 80C51BH TQVWX is measured from data valid to falling edge of WR See timing diagrams 9 This value is based on the maximum allowable die temperature and the thermal resistance of the package 10 All specifications relating to external program memory characteristics are applicable to EPSEN for PSEN Port 5 for Port 0 Port 6 for Port 2 when EBEN is at a Logical 1 on the 80C152JB JD 11 Same as TCLCH use External Clock Drive Waveform 12 Same as TCHCL use External Clock Drive Waveform 13 When using the same external clock to drive both the receiver and transmitter the minimum ECL spec effectively becomes 195 ns at all frequencies assuming 0 ns propagation delay because ECDVT 150 ns plus ECDSR 45 ns re quirements must also be met 150 45 195 ns The 195 ns requirement would also increase to include the maximum propagation delay between receivers and transmitters 19 PRELIMINARY n intel 8XC
14. e latest data sheet before finalizing a design WARNING Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage These are stress ratings only Operation beyond the Operating Conditions is not recommended and ex tended exposure beyond the Operating Conditions may affect device reliability D C CHARACTERISTICS T 0 C to 70 C Voc 5V 10 Vss OV Symbol Parameter Min Typ Max Unit Test Conditions Note 3 ViL Input Low Voltage 0 5 0 2Vcc 0 1 V All Except EA EBEN VIL1 Input Low Voltage 0 5 0 2Vcc 0 3 V EA EBEN ViH Input High Voltage 0 2Vcc 0 9 Vcc 4 0 5 V Except XTAL1 RST Input High Voltage 0 7Vcc Voc t 0 5 V XTAL1 RST VoL Output Low Voltage 0 45 V lo 1 6 mA Ports 1 2 3 4 5 6 Note 4 Vout Output Low Voltage 0 45 V lol 3 2 mA Port 0 ALE PSEN EPSEN Note 4 VoH Output High Voltage 2 4 V 60 pA Ports 1 2 8 4 5 6 COMM9 Voc 5V 10 ALE PSEN EPSEN 0 9Vcc V lon 10 pA Vout Output High Voltage 2 4 V 400 pA Port 0 in External Voc 5V 10 Bus Mode 0 9Vcc V 40 pA Note 5 lit Logical 0 Input 50 pA Vin 0 45V Current Ports 1 2 3 4 5 6 ITL Logical 1 to 0 650 pA Vin 2V Transition Current Ports 1 2 3 4 5 6 li Input Leakage t10 pA 0 45 ViN Voc Port 0 EA RRST Reset Pull
15. ial input line Serial output line External Interrupt 0 External Interrupt 1 Timer 0 external input Timer 1 external input External Data Memory Write strobe External Data Memory Read strobe PRELIMINARY 5 8XC152JA JB JC JD intel Pin Description Continued Pin Description Port 4 Port 4 is an 8 bit bidirectional I O port with internal pullups Port 4 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 4 pins that are externally being pulled low will Source current liL on the data sheet because of the internal pullups In addition Port 4 also receives the low order address bytes during program verification 18 RST Reset input A logic low on this pin for three machine cycles while the oscillator is running resets the device An internal pullup resistor permits a power on reset to be generated using only an external capacitor to Vss Although the GSC recognizes the reset after three machine cycles data may continue to be transmitted for up to 4 machine cycles after Reset is first applied 38 55 ALE Address Latch Enable output signal for latching the low byte of the address during accesses to external memory In normal operation ALE is emitted at a constant rate of 1 the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped during each ac
16. ns Transmitter for 1 2 bit time Manchester encoding only FBTJT Jitter of data from 10 10 ns Transmitter for one full bit time NRZI and Manchester DRTR Data rise time for 20 20 ns Receiver 11 DFTR Data fall time for 20 20 ns Receiver 12 GSC RECEIVER TIMINGS INTERNAL BAUD RATE GENERATOR BT I I wnes e I HBTJR FBTJR I 270431 15 14 PRELIMINARY intel 8XC152JA JB JC JD GSC TRANSMIT TIMINGS INTERNAL BAUD RATE GENERATOR BT I I YY Y Y V MANCHESTER j I or o HBTJT I FBTJT NRZI GTxD I e Os T A I 270431 16 GLOBAL SERIAL PORT TIMINGS External Clock Symbol Parameter 16 5 MHz Variable Oscillator Unit Min Max Min Max 1 ECBT GSC Frequency with an 2 4 0 009 Fosc X 0 145 MHz External Clock ECH External Clock High 170 2TCLCL ns T 45ns ECL 13 External Clock Low 170 2TCLCL ns 45ns ECRT External Clock Rise 20 20 ns Time 11 ECFT External Clock Fall 20 20 ns Time 12 ECDVT External Clock to Data ns Valid Out Transmit 150 150 to External Clock Negative Edge ECDHT External Clock Data ns Hold Transmit 0 0 to External Clock Negative Edge ECDSR External Clock Data 45 45 ns Set up Receiver to External Clock Positive Edge ECDHR External Clock to Data 50 50 ns Hold Receiver to External Clock Positive Edge
17. rallel converters The 83C152 contains in silicon all the features needed for the serial to parallel conversion Other 83C152 benefits include 1 better noise immunity through differential signaling or fiber optic connections 2 data integrity utilizing the standard designed in CRC checks and 3 better modulari ty of hardware and software designs All of these cost network parameter and real estate improvements apply to 83C152 serial links between boards or systems and 83C152 serial links on a single board Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 October 1989 Order Number 270431 003 In e nanao L G 9 N m INDEX 0899 444 eod VES EMEN P1 1 2 P4 0 oan eo q 5 a 8 9 3 28 DEN P1 2 O3 P4 1 zii P1 3 4 P4 2 DM RXC P1 4 045 P4 3 PAF HUD Pi Oje P4 4 x P1 6 7 4 5 P1 7 8 P4 6 EN ite RESET 9 P4 7 PSEN P3 0 10 goc152JA 39 Nc P3 1 11 82
18. rnal clocking circuitry is through a divide by two flip flop but minimum and maximum high and low times specified on the Data Sheet must be observed An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up This is due to interaction between the amplifier and its feedback capacitance Once the external signal meets the and specifications the capacitance will not ex ceed 20 pF 270431 5 Figure 3 Using the On Chip Oscillator 8XC152JA JB JC JD EXTERNAL OSCILLATOR SIGNAL 270431 6 Figure 4 External Clock Drive IDLE MODE In Idle Mode the CPU puts itself to sleep while most of the on chip peripherals remain active The major peripherals that do not remain active during Idle are the DMA channels The Idle Mode is invoked by software The content of the on chip RAM and all the Special Function Registers remain unchanged during this mode The Idle Mode can be terminated by any enabled interrupt or by a hardware reset POWER DOWN MODE In Power Down Mode the oscillator is stopped and all on chip functions cease except that the on chip RAM contents are maintained The mode Power Down is invoked by software The Power Down Mode can be terminated only by a hardware reset Table 3 Status of the External Pins During Idle and Power Down Modes 80C152JA 83C152JA 80C152JC 83C152JC
19. rt 0 is an 8 bit open drain bidirectional I O port As an output port each pin can sink 8 LS TTL inputs Port 0 pins that have 1s written to them float and in that state can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program memory if EBEN is pulled low During accesses to external Data Memory Port 0 always emits the low order address byte and serves as the multiplexed data bus In these applications it uses strong internal pullups when emitting 1s Port 0 also outputs the code bytes during program verification External pullups are required during program verification 1 8 Port 1 Port 1 is an 8 bit bidirectional I O port with internal pullups Port 1 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 1 pins that are externally being pulled low will source current lj on the data sheet because of the internal pullups Port 1 also serves the functions of various special features of the 8XC152 as listed below Pin Name Alternate Function P1 0 P1 1 P1 2 P1 3 P1 4 GRXD GTXD DEN TXC RXC GSC data input pin GSC data output pin GSC enable signal for an external driver GSC input pin for external transmit clock GSC input pin for external receive clock P1 5 HLD DMA hold input output P1 6 HLDA DMA hold acknowledge input output 29 36 41 48 Port
20. s Float TWHLH RD or WR High to 20 100 TCLCL 40 TCLCL 40 ns ALE High M PRELIMINARY intel 8XC152JA JB JC JD EXTERNAL PROGRAM MEMORY READ CYCLE PSEN EPSEN PORTO PORT5 PORT 2 PORT 6 EXTERNAL DATA MEMORY READ CYCLE ALE 270431 8 ALE PORTO PORT2 TRLDV TRHDZ TAVLL TLLAX RAE yyy SS A0 A7 FROM R OR DPL XX X DATAIN DX A0 A7 FROM PCL INSTR IN TAVWL TAVDV 2 0 2 7 OR A8 A15 FROM DPH A8 A15 FROM PCH 270431 9 PRELIMINARY 11 8XC152JA JB JC JD intel EXTERNAL DATA MEMORY WRITE CYCLE ALE PSEN TLLWL 270431 10 EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 1 TCLCL Oscillator Frequency 3 5 16 5 MHz TCHCX High Time 20 ns TCLCX Low Time 20 ns TCLCH Rise Time 20 ns TCHCL Fall Time 20 ns EXTERNAL CLOCK DRIVE WAVEFORM 0 5 0 45 270431 11 2 PRELIMINARY intel e 8XC152JA JB JC JD LOCAL SERIAL CHANNEL TIMING SHIFT REGISTER MODE Symbol Parameter 16 5 MHz Variable Oscillator Units Min Max Min Max TXLXL Serial Port Clock Cycle 727 12TCLCL ns Time TQVXH Output Data Setup to 473 10TCLCL 133 ns Clock Rising Edge TXHQX Output Data Hold After 4 2TCLCL 117 ns Clock Rising Edge TXHDX Input Data Hold After 0 0 ns Clock Rising Edge TXHDV Clock Rising Edge to 473 10TCLCL 133 ns Input Data Valid
21. s only product When EBEN is high Port 5 and Port 6 form an address data bus called the E Bus EPROM Bus for program memory operations through Ports 5 and 6 When EBEN is high and EA is low all program mem ory operations take place via Ports 5 and 6 The high byte of the address goes out on Port 6 and the low byte is output on Port 5 ALE is still used to latch the address on Port 5 Next the op code is read on Port 5 The timing is the same as when using Ports 0 and 2 for external program memory operations Table 1 Program Memory Fetches EBEN EA Program PSEN EPSEN Comments Fetch via 0 0 PO P2 Active Inactive Addresses 0 0FFFFH 0 1 N A N A N A Invalid Combination 1 0 P5 P6 Inactive Active Addresses 0 0FFFFH 1 1 P5 P6 Inactive Active Addresses 0 1FFFH PO P2 Active Inactive Addresses 2 2000H Table 2 8XC152 Product Differences ROMIess CSMA CD HDLC SDLC ROM PLCC 51 0 71 0 Version and Onl Version ang Onl Ports Ports HDLC SDLC y Available DIP y 80C152JA 83C152JA 80C152JB 80C152JC 83C152JC 80C152JD NOTES options available 0 standard frequency range 3 5 MHz to 12 MHz 0 1 frequency range 3 5 MHz to 16 5 MHz PRELIMINARY intel Pin 8XC152JA JB JC JD Pin Description PLCC 1 2 Vcc Supply voltage 3 33 2 Vss Circuit ground 27 30 34 37 Port 0 Po
22. up Resistor 40 Logical 1 Input Current EBEN 60 pA Icc Power Supply Current Active 16 5 MHz 31 41 1 mA Note 6 Idle 16 5 MHz 8 15 4 mA Note 6 Power Down Mode 10 Voc 2 0V to 5 5V 8 PRELIMINARY intel 8XC152JA JB JC JD MAX 1 ACTIVE 2 24 x FREQ 4 16 Note 6 MAX lec IDLE 0 8 x FREQ 2 2 Note 6 45 45 MAX lec ACTIVE 35 30 TYPICAL Icc 25 ACTIVE NOTE 1 20 15 MAX lec IDLE 10 TYPICAL 5 IDLE NOTE 1 0 4 8 12 16 FREQUENCY MHz 270431 7 Figure 5 1 vs Frequency EXPLANATION OF THE AC SYMBOLS P PSEN Q Output data Each timing symbol has 5 characters The first char R READ signal acter is always a T stands for time The other T Time characters depending on their positions stand for V Valid the name of a signal or the logical status of that W WRITE signal signal The following is a list of all the characters and X No longer a valid logic level what they stand for Z Float A Address For example C Clock D Input data TAVLL Time for Address Valid to ALE Low H Logic level HIGH TLLPL Time for ALE Low to PSEN Low I Instruction program memory contents L Logic level LOW or ALE PRELIMINARY 9 8XC152JA JB JC JD intel A C CHARACTERISTICS TA 0 C to 70 Voc 5V 10 Vss OV Load Capacitance for Port 0 ALE and PSEN 100 pF Load Capacitance for All Other
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