CYPRESS CY7C109B/CY7C1009B Manual
Contents
1. CY7C109B 15VI V33 32 Lead 400 Mil Molded SOJ Industrial CY7C109BL 15VI V33 32 Lead 400 Mil Molded SOJ CY7C1009B 15VI V32 32 Lead 300 Mil Molded SOJ CY7C109B 15ZI 732 32 Lead TSOP Type 20 CY7C109B 20VC V33 32 Lead 400 Mil Molded SOJ Commercial CY7C1009B 20VC V32 32 Lead 300 Mil Molded SOJ CY7C109B 20VI V33 32 Lead 400 Mil Molded SOJ Industrial CY7C109B 20ZC 232 32 Lead TSOP I Commercial CY7C109B 20ZI 732 32 Lead TSOP I Industrial 25 CY7C109B 25VC V33 32 Lead 400 Mil Molded SOJ Commercial CY7C1009B 25VC V32 32 Lead 300 Mil Molded SOJ CY7C109B 25VI V33 32 Lead 400 Mil Molded SOJ Industrial CY7C109B 25ZC 732 32 Lead TSOP Type I Commercial CY7C109B 25ZI 232 32 Lead TSOP I Industrial 35 CY7C109B 35VC V33 32 Lead 400 Mil Molded SOJ Commercial CY7C1009B 35VC V32 32 Lead 300 Mil Molded SOJ CY7C109B 35VI V33 32 Lead 400 Mil Molded SOJ Industrial Document 38 05038 Rev Page 9 of 12 CY7C109B CY7C1009B _ A a m RN m O A wea Y PRESS Package Diagrams 32 Lead 300 Mil Molded SOJ V32 PIN 1 LD DIMENSIONS IN INCHES MIN MAX LEAD COPLANARITY 0 004 0 006 0 012 0 MIN 51 85041 0 014 0 020 DETAIL EXTERNAL LEAD DESIGN 007 013 51 85033 Page 10 of 12 Document 38 05038 Rev CY7C109B CY7C1009B 2 CYPRESS Package Diagram2. i8 CY 7C 1009B 12V C f v CY7C109B CY7C1009B Features High speed 1 12 ns Low active power 495 mW max 12 ns Low CMOS standby power 55 mW max 4 mW 2 0V Data Retention Automatic power down when deselected TTL compatible inputs and outputs Easy memory expansion with CE CE and OE options Functional Description The CY7C109B CY7C1009B is a high performance CMOS static RAM organized as 131 072 words by 8 bits Easy mem ory expansion is provided by an active LOW Chip Enable CE4 an active HIGH Chip Enable CE3 an active LOW Out 128K x 8 Static RAM put Enable OE and three state drivers Writing to the device is accomplished by taking Chip Enable One CE4 and Write Enable WE inputs LOW and Chip Enable Two input HIGH Data on the eight I O pins I Og through l O7 is then written into the location specified on the address pins Ao through A4 Reading from the device is accomplished by taking Chip En able One CE and Output Enable OE LOW while forcing Write Enable WE and Chip Enable Two HIGH Under these conditions the contents of the memory location speci fied by the address pins will appear on the I O pins The eight input output pins I Og through I O7 are placed in a high impedance state when the device is deselected CE HIGH or LOW the outputs are disabled OE HIGH or during a write operation CE LOW HIGH a
3. to 125 C Ambient Supply Voltage on to Relative 0 5V to 7 0V Range Temperature Vcc DC Voltage Applied to Outputs Commercial 0 C to 70 C 5V t 10 In High Z State eerren 0 5V to Vec 4 0 5V Industrial 40 C to 85 C 5V 10 DC Input 1 0 5V to Voc 0 5V Current into Outputs LOW eeeeeeeee 20 mA Electrical Characteristics Over the Operating Range 7C109B 12 7C109B 15 7C1009B 12 7C1009B 15 Parameter Description Test Conditions Min Max Min Max Unit VoH Output HIGH Voltage Vcc Min 2 4 2 4 V lou 4 0 mA VoL Output LOW Voltage Vcc Min 0 4 0 4 V lot 8 0 mA Vin Input HIGH Voltage 2 2 Voc 2 2 Voc V 0 3 0 3 Vi Input LOW Voltagel 0 3 0 8 0 3 0 8 V lix Input Load Current GND lt lt Vcc 1 1 1 1 uA loz Output Leakage GND lt Vi lt Vec 5 5 5 5 uA Current Output Disabled los Output Short Vcc Max 300 300 mA Circuit Current Vour loc Voc Operating Voc Max 90 80 mA Supply Current lout 0 mA f fmax l tnc Ispy Automatic CE Max Voc CE gt 45 40 mA Power Down Current jor lt Vy TTL Inputs Vin gt Vin or Vin lt Vii f fmax Ispe Automatic CE Max Voc 10 10 mA Power Down Current CE gt Voc 0 3V L CMOS Inputs or CE 0 3V Vin gt Voc d 0 3V or Vin lt 0 3V f 20 Notes 1 min 2 0V for pulse dura
4. or Vy lt 0 3V f 0 Capacitance Parameter Description Test Conditions Max Unit Cin Input Capacitance Ty 25 C f 1 MHz 9 pF Cour Output Capacitance Vcc 5 0V 8 pF AC Test Loads and Waveforms R1 4800 R1 4802 ALL INPUT PULSES 5V 5V 3 0V OUTPUT OUTPUT R2 R2 GND 2550 2550 j INCLUDING INCLUDING lt 3 ns JIG AND JIG AND SCOPE SCOPE b 109B 5 TH VENIN EQUIVALENT 1670 OUTPUT O wwW O 1 73V Equivalent to Note 4 Tested initially and after any design or process changes that may affect these parameters Document 38 05038 Rev Page 3 of 12 CY7C109B Switching Characteristics Over the Operating Range 7C109B 12 7C109B 15 7C1009B 12 7C1009B 15 Parameter Description Min Max Min Max Unit READ CYCLE tnc Read Cycle Time 12 15 ns Address to Data Valid 12 15 ns Data Hold from Address Change 3 3 ns tace CE LOW to Data Valid HIGH to Data 12 15 ns Valid ipoE OE LOW to Data Valid 6 7 ns tizoE OE LOW to Low Z 0 0 ns tuzoE OE HIGH to High 216 6 7 ns lizcE CE LOW to Low Z CE HIGH to Low 27 3 3 ns luzcE CE HIGH to High Z CE LOW to High 218 7 6 7 ns tpu CE LOW to Power Up HIGH to 0 0 ns Power Up tpp CE HIGH to Power Down LOW to 12 15 ns Power Down WRITE CYCLE twc Write Cycle Time 12 15 ns tsce CE LOW to Write
5. End HIGH to Write End 10 12 ns tAW Address Set Up to Write End 10 12 ns 1 Address Hold from Write End 0 0 ns tsa Address Set Up to Write Start 0 0 ns tpwe WE Pulse Width 10 12 ns tsp Data Set Up to Write End 7 8 ns tup Data Hold from Write End 0 0 ns tLzwe WE HIGH to Low Z1 3 3 ns tuzwE WE LOW to High 216 6 7 ns Notes 5 Test conditions assume signal transition time of ns or less timing reference levels of 1 5V input pulse levels of 0 to 3 0V and output loading of the specified loj and 30 pF load capacitance 6 thzoe tuzce and tyzwe are specified with a load capacitance of 5 pF as in part b of AC Test Loads Transition is measured 500 mV from steady state voltage 7 Atany given temperature and voltage condition is less than ti zce thzoe is less than zog and tyzwe is less than tj zwe for any given device 8 internal write time of the memory is defined by the overlap of CE LOW CE HIGH and WE LOW CE and WE must be LOW and CE HIGH to initiate a write and the transition of any of these signals can terminate the write The input data set up and hold timing should be referenced to the leading edge ofthe signal that terminates the write 9 The minimum write cycle time for Write Cycle No WE controlled OE LOW is the sum of tyzwe and tgp Document 38 05038 Rev Page 4 of 12 CY7C109B 8 CYPRESS CY7C1
6. 009B Switching Characteristics Over the Operating Range continued 7C109B 20 7C109B 25 7C109B 35 7C1009B 20 7C1009B 25 7C1009B 35 Parameter Description Min Max Min Max Min Min Unit READ CYCLE tnc Read Cycle Time 20 25 35 ns taa Address to Data Valid 20 25 35 ns Data Hold from Address Change 3 5 5 ns tACE CE LOW to Data Valid CE HIGH to Data 20 25 35 ns Valid iboE OE LOW to Data Valid 8 10 15 ns tizoE OE LOW to Low Z 0 0 0 ns tuzoE OE HIGH to High 2 5 8 10 15 ns tizcE CE LOW to Low Z HIGH to Low 217 3 5 5 ns tHzcE CE HIGH to High Z CE LOW to High 216 8 10 15 ns tpu CE LOW to Power Up CE HIGH to 0 0 0 ns Power Up tpp CE HIGH to Power Down LOW to 20 25 35 ns Power Down WRITE CYCLES twc Write Cycle Timel l 20 25 35 ns tscE CE LOW to Write End HIGH to Write End 15 20 25 ns taw Address Set Up to Write End 15 20 25 ns tua Address Hold from Write End 0 0 0 ns tsa Address Set Up to Write Start 0 0 0 ns tpwe WE Pulse Width 12 15 20 ns tsp Data Set Up to Write End 10 15 20 ns tup Data Hold from Write End 0 0 0 ns tizwE WE HIGH to Low Zl 3 5 5 ns tuzwE WE LOW to High 216 8 10 15 ns Data Retention Characteristics Over the Operating Range Low Power version only Parameter Description Conditions Min Max Unit VDR Vcc for Data Retention No input may exceed Vcc 0 5V 2 0 V Vec 2 0V IccpR Data Retention Curren
7. ange from Spec number 38 00971 to 38 05038 Document 38 05038 Rev Page 12 of 12
8. g HIGH the output remains in a high impedance state 15 During this period the I Os are in the output state and input signals should not be applied Document 38 05038 Rev Page 7 of 12 YPRESS CY7C109B CY7C1009B Switching Waveforms continued Write Cycle No 3 WE Controlled Low 4 ADDRESS twc tsce Co 44 ma DR AUN taw tsa tpwe WE NNNNNN WE 00 60 64 __ XX DATA WO X NE ALAA ay DATA VALID XX tHZWE 10B9 11 Truth Table CE CE OE WE l Og l Oz Mode Power H X X X HighZ Power Down Standby lag X L X X High Z Power Down Standby lag L H L H Data Out Read Active loc L H X L Data In Write Active lcc L H H H High Z Selected Outputs Disabled Active 1 Page 8 of 12 Document 38 05038 Rev CY7C109B Ordering Information Speed Package Operating ns Ordering Code Name Package Type Range 12 CY7C109B 12VC V33 32 Lead 400 Mil Molded SOJ Commercial CY7C1009B 12VC V32 32 Lead 300 Mil Molded SOJ CY7C109B 12ZC 232 32 1 TSOP 15 CY7C109B 15VC V33 32 Lead 400 Mil Molded SOJ Commercial CY7C109BL 15VC V33 32 Lead 400 Mil Molded SOJ CY7C1009B 15VC V32 32 Lead 300 Mil Molded SOJ CY7C109B 15ZC 232 32 Lead TSOP CY7C109BL 15ZC 232 32 1 TSOP
9. nd WE LOW The CY7C109B is available in standard 400 mil wide SOJ and 32 pin TSOP type packages The CY7C1009B is available in a 300 mil wide SOJ package The CY7C1009B and CY7C109B are functionally equivalent in all other respects Logic Block Diagram 512 x 256 x8 RAY COLUMN DECODER oc a Q a z O Pin Configurations SOJ Top View TSOPI Top View not to scale Selection Guide Cypress Semiconductor Corporation Document 38 05038 Rev 7C109B 12 7C109B 15 7C109B 20 7C109B 25 7C109B 35 7C1009B 12 7C1009B 15 7C1009B 20 7C1009B 25 7C1009B 35 Maximum Access Time ns 12 15 20 25 35 Maximum Operating Current mA 90 80 75 70 60 Maximum CMOS Standby Current mA 10 10 10 10 10 Maximum CMOS Standby Current mA Low Power Version 2 2 2 3901 North First Street SanJose 95134 408 943 2600 Revised August 24 2001 CY7C109B Cypress CY7C1009B Maximum Ratings Static Discharge Voltage gt 2001V Above which the useful life may be impaired For user guide per MIL STD 883 Method 3015 lines not tested Latch Up Current sese gt 200 mA Storage Temperature 65 C to 150 C i Ambient Temperature with Operating Range Power Applied sss 55
10. s continued 32 Lead Thin Small Outline Package Z32 DIMENSI 19 80 20 50 NL 18 30 zi 8 50 7 0 50 1 V Ek ie i 17 Suede J 2 0 10 0 55 0 20 rax a Y v BN i 51 85056 C 0 40 0 60 Document 38 05038 Rev Page 11 of 12 Cypress Semiconductor Corporation 2001 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product Nor does it convey or imply any license under patent or other rights Cypress Semiconductor does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress Semiconductor products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges RR HEE IET _ IL E Soe 5 p gt a a gt CYPRESS CY7C109B CY7C1009B Document Title CY7C109B CY7C1009 128K x 8 SRAM Document Number 38 05038 Issue Orig of REV ECN NO Date Change Description of Change dd 106832 09 22 01 SZV Ch
11. t CE gt 0 3V or lt 0 3V 150 uA tcpr Chip Deselect to Data Retention Time Vin gt Vcc 0 3V or Vin lt 0 3V 0 ns tr Operation Recovery Time 200 us Document 38 05038 Rev Page 5 of 12 CY7C109B Say CYPRESS 0 9 DATA RETENTION MODE Vpr gt 2V lt tcpR gt 109B 6 Switching Waveforms Read Cycle No 1 19 11 tac ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID 109B 7 Read Cycle No 2 OE Controlled t 121 ADDRESS SQ CSSCSCSCi CY CE tHZOE DOE tLZ0E i 2 HIGH HIGH IMPEDANCE 77777 IMPEDANCE DATA OUT DATA VALID NNNNNN tLZCE Voc SUPPLY CURRENT Notes ME 10 Device is continuously selected OE CE Vi_ CE2 11 WEis HIGH for read cycle 12 Address valid prior to or coincident with CE transition LOW and CE transition HIGH Document 38 05038 Rev Page 6 of 12 CY7C109B CEN CV 55 CY7C1009B Switching Waveforms continued Write Cycle No 1 CE or CE Controlled 3 141 DATA I O DATA VALID Write Cycle No 2 WE Controlled OE HIGH During Write 14 109B 9 twc nuu iscE taw tsa tpwe RASS tHZOE 109B 10 Notes 13 Data I O is high impedance if OE Vy 14 If CE goes HIGH or goes LOW simultaneously with WE goin
12. tions of less than 20 ns 2 Ty is the case temperature 3 Not more than one output should be shorted at one time Duration of the short circuit should not exceed 30 seconds Document 38 05038 Rev Page 2 of 12 CY7C109B Electrical Characteristics Over the Operating Range continued 7C109B 20 7C109B 25 7C109B 35 7C1009B 20 7C1009B 25 7C1009B 35 Parameter Description Test Conditions Min Max Min Max Min Max Unit Vou Output HIGH Voltage Voc Min 2 4 2 4 2 4 V 4 0 mA VoL Output LOW Voltage Voc Min 0 4 0 4 0 4 V lot 8 0 mA Input HIGH Voltage 22 Vcg 2 2 Vec 22 Voc V 0 3 0 3 0 3 Vit Input LOW Voltage 0 3 08 0 3 08 0 3 0 8 V lix Input Load Current GND lt VI lt Vcc 1 1 1 1 1 1 uA loz Output Leakage GND lt Vi lt Vcc 5 5 5 5 5 5 uA Current Output Disabled los Output Short Vcc Max 300 300 300 mA Circuit Current Vour loc Voc Operating Voc Max 75 70 60 mA Supply Current lout 0 mA f fmax T tac Automatic CE Vcc gt Vin 30 30 25 mA Power Down Current or CE3 lt Vj TTL Inputs Vin gt Vin or Vin lt Vit f fmax Ispo Automatic CE Max Vcc 10 10 10 mA Power Down Current gt Vcc 0 3V 2 mA CMOS Inputs or lt 0 3V gt Vcc 0 3V
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CYPRESS CY7C109B/CY7C1009B Manual