SAMSUNG Electronics K4S64323LH - F(H)E/N/G/C/L/F handbook
Contents
1. o S Column Decoder Q gt 0 o m g Latency amp Burst Length gt g i LOKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE cs RAS CAS WE DQM a February 2004 ELECTRONICS K4S64323LH F H E N G C L F Mobile SDRAM Package Dimension and Pin Configuration lt Top View gt 90Ball 6x15 FBGA lt Bottom View gt 2 d 987654321 1 00o 2000 DOGO 000 gt F O e 000 0006 alt HOOO _ 000 J eoe 0060 LOOO oeoo0e 000 eoo 000 000 2 eoo re E E 2 3 vee A1 Substrate 2Layer b Z a Top View gt A1 Ball Origin Indicator JOOOCH I CEV9STM xooM ONNSWNVS 2 DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 AS A8 NC 2 2 1 Pin Function System Clock cs Chip Select Clock Enable Ao A10 Adaress BAo 1 Bank Select Address RAS Row Address Strobe CAS Column Address Strobe WE Write Enable DQMo DQM3 Data Input Output Mask DQo 31 Data Input Output 55 Power Supply Ground VpDo Vs2. Column Address Address Auto Precharge Enable A0 A7 Burst Stop Bank Selection Precharge All Banks Clock Suspend or Active Power Down Precharge Power Down Mode DQM No Operation Command I x X lt ox lt x V Valid X Don t Care H Logic High L Logic Low NOTES OP Code Operand Code AO A10 amp BAO BA1 Program keys MRS 2 MRS can be issued only at all banks precharge state new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are the same as CBR refresh of DRAM The automatical precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state Partial self refresh can be issued only after setting partial self refresh mode of EMRS 4 BAO BA1 Bank select addresses 5 During burst read or write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length DQM sampled at the positive going edge of CLK masks the data in at that same CLK in write operation Write DQM latency is 0 but in read operation it makes the data out Hi Z state after 2 CLK cycles Read DQM latency is 2 a a February 2004
3. s amp JKAS64323LH FC 1H f v R3 K4S64323LH F H E N G C L F Mobile SDRAM 512K x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES 2 5V power supply LVCMOS compatible with multiplexed address Four banks operation MRS cycle with address key programs CAS latency 1 2 amp 3 Burst length 1 2 4 8 amp Full page Burst type Sequential amp Interleave EMRS cycle with address key programs All inputs are sampled at the positive going edge of the system clock Burst read single bit write operation Special Function Support PASR Partial Array Self Refresh Internal TCSR Temperature Compensated Self Refresh DQM for masking Auto refresh 64ms refresh period 4K cycle Commercial Temperature Operation 25 C 70 Extended Temperature Operation 25 C 85 90Balls FBGA with 0 8mm ball pitch FXXX Leaded HXXX Lead Free ORDERING INFORMATION Part No Max Freq GENERAL DESCRIPTION The K4S64323LH is 67 108 864 bits synchronous high data rate Dynamic RAM organized as 4 x 524 288 words by 32 bits fabricated with SAMSUNG s high performance CMOS technol ogy Synchronous design allows precise cycle control with the use of system clock and I O transactions are possible on every clock cycle Range of operating frequencies programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth
4. February 2004 K4S64323LH F H E N G C L F Mobile SDRAM AC CHARACTERISTICS operating conditions unless otherwise noted Parameter CAS latency 3 CLK cycle time CAS latency 2 CAS latency 1 CAS latency 3 CLK to valid output delay CAS latency 2 CAS latency 1 CAS latency 3 Output data hold time CAS latency 2 CAS latency 1 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low Z CAS latency 3 CLK to output in Hi Z CAS latency 2 CAS latency 1 NOTES 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter a February 2004 ELECTRONICS K4S64323LH F H E N G C L F Mobile SDRAM SIMPLIFIED TRUTH TABLE COMMAND A10 AP A9 AO Mode Register Set X OP CODE Auto Refresh X Entry Self L Refresh Exit X Bank Active amp Row Addr E L H H Row Address Read amp Auto Precharge Disable L Column Column Address Address Auto Precharge Enable A0 A7 H Write amp Auto Precharge Disable L Column H
5. ELECTRONICS K4S64323LH F H E N G C L F Mobile SDRAM A MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with Normal MRS Address BAO BA1 A10 AP A9 A8 A7 A6 A5 A4 A3 A2 A1 AO 0 Setting for Normal MRS RFU W B L Test Mode CAS Latency BT Burst Length Normal MRS Mode Test Mode CAS Latency Burst Type Burst Length Type A5 A4 Latency Type AO BT 0 Mode Register Set 0 0 Reserved Sequential 0 1 Reserved 0 1 1 Interleave 1 Reserved 1 2 Mode Select Reserved 1 3 BA1 Mode Write Burst Length Reserved Reserved Reserved Length Reserved Setting Reserved Reserved for Nor Burst Reserved mal MRS Reserved Reserved Single Bit Reserved Full Page Reserved Full Page Length x32 64Mb 256 Register Programmed with Extended MRS Address A10 AP Function Mode Select EMRS for PASR Partial Array Self Ref amp DS Driver Strength Mode Select Driver Strength PASR Mode A5 Driver Strength Size of Refreshed Array Normal MRS 0 Full Full Array Reserved 1 1 2 1 2 of Full Array EMRS for Mobile SDRAM Reserved 1 4 of Full Array Reserved Reserved Reserved Reserved Address Reserved A10 AP A8 A7 Reserved Reserved Reserved NOTES 1 RFU Reserved for future use should stay 0 during MRS cycle 2 If A9 is hig
6. refresh commands 5 Issue a mode register set command to initialize the mode register 6 Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used The default state without EMRS command issued is the full driver strength and full array refreshed The device is now ready for the operation selected by EMRS For operating with DS or PASR set DS or PASR mode in EMRS setting stage In order to adjust another mode in the state of DS or PASR mode additional EMRS set is required but power up sequence is not needed again at this time In that case all banks have to be in idle state prior to adjusting EMRS set m February 2004 ELECTRONICS K4S64323LH F H E N G C L F Mobile SDRAM C BURST SEQUENCE 1 BURST LENGTH 4 Initial Address A0 Sequential Interleave Initial Address Sequential A2 Interleave 0 0 0 0 0 February 2004
7. and high per formance memory system applications Interface Package K4S64323LH F H E N G C L F60 166MHz CL 3 K4S64323LH F H E N G C L F75 133MHz CL 3 LVCMOS 90 FBGA 105MHz CL 2 Leaded Lead Free H K4S64323LH F H E N G C L F 1H K4S64323LH F H E N G C L F1L 105MHz CL 3 F H E N G Normal Low Low Power Extended Temperature 25 C 85 C F H O L F Normal Low Low Power Commercial Temperature 25 C 70 NOTES 1 In case of 40MHz Frequency CL1 can be supported 2 Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose such as medical aerospace nuclear military vehicular or undersea repeater use February 2004 K4S64323LH F H E N G C L F Mobile SDRAM FUNCTIONAL BLOCK DIAGRAM Y 6 4 L1WE o Data Input Register 3 5 S lt LDQM Bank Select Y D I 512K x 32 o m H 2 o 512K x 32 2 g BI 0 gt w lt gt E gt 512 32 amp CLK zum E g Q m 512K x 32 ADD
8. h during MRS cycle Burst Read Single Bit Write function will be enabled a February 2004 K4S64323LH F H E N G C L F Mobile SDRAM Partial Array Self Refresh 1 In order to save power consumption Mobile SDRAM has PASR option 2 Mobile SDRAM supports 3 kinds of PASR in self refresh mode Full Array 1 2 of Full Array and 1 4 of Full Array BA1 0 BAO 1 BA1 1 BA1 1 BA1 1 BA1 1 BAO 0 BAO 1 BAO 0 BAO 1 Full Array 1 2 Array 1 4 Array Partial Self Refresh Area Temperature Compensated Self Refresh 1 In order to save power consumption Mobile DRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the two temperature range Max 40 C and Max 85 C for Extended Max 70 C for Commercial 2 If the EMRS for external TCSR is issued by the controller this EMRS code for TCSR is ignored Self Refresh Current Icc6 Temperature Range G F Full Array 1 2 of Full Array 1 4 of Full Array Max 85 70 C 300 240 220 Max 40 C 160 140 120 B POWER UP SEQUENCE 1 Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined Apply VDD before or at the same time as VDDQ 2 Maintain stable power stable clock and NOP input condition for a minimum of 200us 3 Issue precharge commands for all banks of the devices 4 Issue 2 or more auto
9. ime during in non power down mode 20ns One Bank Active gt Vin min CLK lt ViL max tcc oo ans Input signals are stable lo 0 mA Operating Current Page burst Burst Mode 4Banks Activated tccp 2CLKs Refresh Current tRC gt tRc min 115 110 E C 1000 N L 300 Internal TCSR Max 85 70 Self Refresh Current CKE lt 0 2V Full Array 300 1 2 of Full Array 240 1 4 of Full Array 220 NOTES 1 Measured with outputs open 2 Refresh period is 64ms 3 Internal TCSR can be supported In commercial Temp Max 40 C Max 70 C In extended Temp Max 40 C Max 85 C K4S64323LH F H E C KAS64323LH F H N L K4S64323LH F H S R Unless otherwise noted input swing level is CMOS VIH VIL VDDQ VSSQ a February 2004 ELECTRONICS K4S64323LH F H E N G C L F Mobile SDRAM AC OPERATING TEST CONDITIONS vpn 2 5v 0 2V Ta 25 to 85 C for Extended 25 to 70 C for Commercial Parameter Value AC input levels Vih Vil 0 9 x Vppa 0 2 Input timing measurement reference level 0 5 x VDDQ Input rise and fall time tr tf 1 1 Output timing measurement reference level 0 5 x VDDQ Output load condition See Figure 2 o VDDQ S 5000 e o Vtt 0 5 x VDDQ Output gt 5000 Output o 20 500 Figure 1 DC Output Load Circuit Figure 2 AC Ou
10. sa Data Output Power Ground Unit mm February 2004 K4S64323LH F H E N G C L F Mobile SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Voltage on any pin relative to Vss Vin VOUT 1 0 3 6 Voltage on supply relative to Vss VDD VDDQ 1 0 3 6 Storage temperature TSTG 55 150 Power dissipation 1 0 Short circuit current 50 NOTES Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended operating conditions Voltage referenced to Vss OV Ta 25 to 85 C for Extended 25 to 70 C for Commercial Parameter Min Max 2 3 2 7 Supply voltage 2 3 2 7 1 65 2 7 Input logic high voltage 0 8 x VDDQ VDDQ 0 3 Input logic low voltage 0 3 0 3 Output logic high voltage VDDQ 0 2 0 1mA Output logic low voltage 0 2 lo 0 1mA Input leakage current 10 4 NOTES 1 Samsung can support VDDQ 2 5V in general case and 1 8V in specific case for VDD 2 5V products Please contact to the memory marketing team in Samsung Electronics when considering the use of VDDQ 1 8V Min 1 65V 2 VIH max 3 0V AC The overshoot vol
11. tage duration is x 3ns 3 VIL min 1 0V AC The undershoot voltage duration is x 3ns 4 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with tri state outputs Dout is disabled OV lt VOUT lt VDDQ CAPACITANCE vpn 2 5V Ta 23 C f 1MHz VREF 0 9V 50 mV Address DQ31 a February 2004 ELECTRONICS K4S64323LH F H E N G C L F Mobile SDRAM DC CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss OV Ta 25 to 85 C for Extended 25 to 70 C for Commercial Version Parameter Symbol Test Condition 75 1H Burst length 1 lcc1 tRC gt tRc min 70 70 lo 0 mA Operating Current One Bank Active Precharge Standby Current 2 lt ViL max tcc 10ns power down mode IccaPS CKE amp CLK lt ViL max tcc gt Vin min CS gt Vin min tcc 10ns Icc2N Input signals are changed one time during Precharge Standby Current 20ns in non power down mode CKE gt Vin min CLK lt ViL max tcc Input signals are stable Active Standby Current lccaP lt ViL max tcc 10ns power down mode IccaPS amp CLK lt ViL max tcc gt Vin min CS gt ViH min tcc 10ns Active Standby Current Icc3N Input signals are changed one t
12. tput Load Circuit a February 2004 ELECTRONICS K4S64323LH F H E N G C L F Mobile SDRAM OPERATING AC PARAMETER AC operating conditions unless otherwise noted Version Parameter Symbol Unit Note 60 75 1 1L Row active to row active delay tRRD min 12 15 19 19 ns 1 RAS to CAS delay 18 19 19 24 ns 1 Row precharge time tRP min 18 19 19 24 ns 1 tRAS min 42 45 50 60 ns 1 Row active time tRAs max 100 us Row cycle time tRc min 60 64 69 84 ns 1 Last data in to row precharge tRDL min 2 CLK 2 Last data in to Active delay tDaL min tRDL tRP 3 Last data in to new col address delay min 1 CLK 2 Last data in to burst stop 1 CLK 2 Col address to col address delay tccp min 1 CLK 4 Number of valid output data CAS latency 3 2 Number of valid output data CAS latency 2 1 ea 5 Number of valid output data CAS latency 1 0 NOTES 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 Minimum tRDL 2CLK and tDAL tRDL tRP is required to complete both of last data write command tRDL and precharge command tRP 4 All parts allow every cycle column address change 5 In case of row precharge interrupt auto precharge and read burst stop
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SAMSUNG Electronics K4S64323LH F(H)E/N/G/C/L/F handbook