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ANALOG DEVICES ADG3300 handbook(1)

1. 18 23 28 33 38 43 48 53 CAPACITIVE LOAD pF Vecy 1 8V 18 23 28 33 38 43 48 53 CAPACITIVE LOAD pF 05061 015 05061 016 Y A Level Translation Figure 16 Fall Time vs Capacitive Load at Pin A Y A Level Translation PROPAGATION DELAY ns Ty 25 C 1 CHANNEL 12 DATA RATE 50kbps cey 1 8V Veca 1 8V Vecy 3 Veca 3 3V Vecy 5V 0 13 23 33 43 53 63 73 CAPACITIVE LOAD pF Figure 17 Propagation Delay teu vs Capacitive Load at Pin Y A Y Level Translation 05061 017 Rev 0 Page 10 of 20 12 DATA RATE 50kbps TA 25 C Veca 1 2V Vecy 1 8V 1 CHANNEL 10 T a ul a z o E lt 5 E n o fd a CAPACITIVE LOAD pF Figure 18 Propagation Delay tpi vs Capacitive Load at Pin Y A Y Level Translation TA 25 C 1 CHANNEL DATA RATE 50kbps _ Veca 1 2V Vecy 1 8V gt lt l ul a z o lt fo n e ra a 13 18 23 28 33 38 43 48 53 CAPACITIVE LOAD pF Figure 19 Propagation Delay tpi vs Capacitive Load at Pin A Y A Level Translation TA 25 C 1 CHANNEL DATA RATE 50kbps Veca 1 2V Vecy 1 8V T gt q l ul a z o E lt 6 E n o c n 13 18 23 28 33 38 43 48 53 CAPACITIVE LOAD pF Figure 20 Propagati
2. ESD SENSITIVE DEVICE Rev 0 Page 6 of 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADG3300 TOP VIEW Not to Scale 05061 002 Figure 2 Pin Configuration Table 3 Pin Function Descriptions ADG3300 Pin No Mnemonic Description 1 A1 Input Output A1 Referenced to Vcca 2 Veca Power Supply Voltage Input for tle A1 to A8 1 0 pins 1 15 V lt Veca lt Mcog 3 A2 Input Output A2 Referenced to Veca i 4 A3 MA put A3 Referenced to Veca 5 A4 Input Output A4 Referenced to Vcca 6 A5 Input Output A5 Referenced to Vcca 7 A6 Input Output A6 Referenced to Vcca 8 A7 Input Output A7 Referenced to Vcca 9 A8 Input Output A8 Referenced to Vcca 10 EN Active High Enable Input 11 GND Ground 12 Y8 Input Output Y8 Referenced to Vccy 13 Y7 Input Output Y7 Referenced to Vccyv 14 Y6 Input Output Y6 Referenced to Vccy 15 Y5 Input Output Y5 Referenced to Vccv 16 Y4 Input Output Y4 Referenced to Vccy 17 Y3 Input Output Y3 Referenced to Vccy 18 Y2 Input Output Y2 Referenced to Vccy 19 Vccy Power Supply Voltage Input for the Y1 to Y8 I O pins 1 65 V lt Vccy lt 5 5 V 20 Y1 Input Output Y1 Referenced to Vccy Rev 0 Page 7 of 20 ADG3300 TYPICAL PERFORMANCE CHARACTERISTICS 05061 006 1 0 rS 25C Tas 25 C 1 CHANNEL 1 CHANNEL 0 9 C 50pF
3. 9 CAPACITIVE LOAD pF 8 CAPACITIVE LOAD pF E Figure 9 Iccy vs Capacitive Load at Pin Y for A Y 1 8 V 3 3 V Figure 12 Icca vs Capacitive Load at Pin A for Y A 5 V 3 3 V Level Translation Level Translation 10 TA 25 C TA 25 C 1 CHANNEL 9 1 CHANNEL Vcca 1 8V DATA RATE 50kbps Vga 1 2V Vccy 1 8V Vecy 3 3V 8 7 86 W 25 E W 2 4 Veca 1 8V Vecy 3 3V 2 T Veca 3 3V Vecy 5V 1 S 0 2 13 23 33 43 53 63 73 3 CAPACITIVE LOAD pF S CAPACITIVE LOAD pF E Figure 10 Icca vs Capacitive Load at Pin A for Y A 3 3 V 1 8 V Figure 13 Rise Time vs Capacitive Load at Pin Y A Y Level Translation Level Translation 12 4 0 Ta 25 C Ta 25 C 1 CHANNEL 1 CHANNEL Veca 3 3V 3 5 DATA RATE 50kbps 10 vccy 5v p Vcca 1 2V Voy 1 8V 3 0 8 g 25 u A 1 8V Vccy 3 3V 6 z E 2 0 a X 5 1 0 2 0 5 0 0 13 23 33 43 53 63 73 9 13 23 33 43 53 63 73 iul CAPACITIVE LOAD pF 8 CAPACITIVE LOAD pF E Figure 11 lccy vs Capacitive Load at Pin Y for A Y 3 3 V 5 V Figure 14 Fall Time vs Capacitive Load at Pin Y A Y Level Translation Level Translation Rev 0 Page 9 of 20 ADG3300 RISE TIME ns Figure 15 Rise Time vs Capacitive Load at Pin A FALL TIME ns 10 Ta 25 C 1 CHANNEL DATA RATE 50kbps Veca 1 2V Vecy 1 8V Veca 1 8V Vecy 3 3V Ta 25 C 1 CHANNEL 3 5 DATA RATE 50kbps Veca 3 3V Vecy 5V
4. TABLE OF CONTENTS Specifications iive i t REIR RR RM ERE REDI RE 3 Absolute Maximum Ratings eene 6 ESD Caan c sostenere sies esee DI M estat 6 Pin Configuration and Function Descriptions 7 Typical Performance Characteristics sse 8 Test CITCUIUS estet eii HS e d edet HH RA n 12 Terminology oie libe OTTEET 14 Theory of Operationjc siete bett teh Pets 15 Level Translator Architecture sse 15 REVISION HISTORY 4 05 Revision 0 Initial Version UM Input Driving Requirements sse 15 Output Load Requirements senten 15 Enable Operation cscs estt REOR URRRA 15 Power SUPPLIES 25cm te dette 15 Data Rate uscite neteneee tente uen deien 16 ADDpLICatiODS 2t ete Ie Reate a 17 Eayout Guidelines uere eerte eb endbbten 17 Outline Dimensions ettet tette tdt 18 Ordering Guide ace bene eee eniin 18 Rev 0 Page 2 of 20 SPECIFICATIONS Vccx 1 65 V to 5 5 V Veca 1 15 V to Vccy GND 0 V All specifications Tm to Tmax unless otherwise noted ADG3300 Table 1 Parameter Symbol Conditions Min Typ Max Unit LOGIC INPUTS OUTPUTS A Side Input High Voltage Vina Veca 1 15 V Vcca 0 3 V Vina Vcca 1 2 V to 5 5 V Vcca 0 4 V Input Low Voltage Vita 0 4 V Output High Voltage Vona Vy Vecy lou 20 pA Figure 27 Vcca 0 4 V Output Low Voltage Vora Vy OV lo 20 pA Figure 27 0 4 V Three State Pull Do
5. 65 V to 1 95 V 2 3 V to 2 7 V 3 0 V to 3 6 V 4 5 V to 5 5 V 1 2 V 1 15 V to 1 3 V 25 30 40 40 1 8 V 1 65 V to 1 95 V 45 50 50 2 5 V 2 3 V to 2 7 V 60 50 3 3 V 3 0 V to 3 6 V 50 5 V 4 5 V to 5 5 V The load capacitance used is 50 pF when translating in the A Y direction and 15 pF when translating in the Y A direction IN D ALI Rev 0 Page 16 of 20 APPLICATIONS The ADG3300 is designed for digital circuits that operate at different supply voltages therefore logic level translation is required The lower voltage logic signals are connected to the A pins and the higher voltage logic signals are connected to the Y pins The ADG3300 can provide level translation in both directions from A Y and Y A on all eight channels eliminating the need for a level translator IC for each direction The internal architecture allows the ADG3300 to perform bidirectional level translation without an additional signal to set the direction of the translation It also allows simultaneous data flow in both directions on the same part for example four channels translate in the A Y direction while the other four translate in the Y A direction This simplifies the design by eliminating the timing requirements for the direction signal and reduces the number of ICs used for level translation Figure 36 shows an application where a 1 8 V microprocessor can read or write data to or from a 3 3 V peripheral de
6. C 15pF 0 8 Veca 3 3V Vecy 5V 0 7 CCA ccv 2 06 z Ei E 0 5 8 0 4 Veca 1 8V Vecy 3 3V 0 3 CC ccv 0 2 0 1 Veca 1 2V Vecy 1 8V o 0 2 0 5 10 15 20 25 30 35 40 45 50 MALUS RCM AE UE E LE DATA RATE Mbps Ed DATA RATE Mbps Figure 3 lcca vs Data Rate A Y Level Translation Figure 6 Iccy vs Data Rate Y A Level Translation 10 aC Ta 25 C 1 CHANNEL 1 CHANNEL 9 c 50pF Veca 1 2V z 1 E gt x 8 L 3 1 8V Vocy 3 i 0 5 10 15 20 25 30 35 40 45 50 z DATA RATE Mbps E CAPACITIVE LOAD pF Figure 4 lccy vs Data Rate A Y Level Translation Figure 7 Iccy vs Capacitive Load at Pin Y for A Y 1 2 V 1 8 V Level Translation TA 25 C Ta 25 C 1 CHANNEL 1 CHANNEL C 15pF Veca 1 2V Vecy 1 8V E 0 5 10 15 20 25 30 35 40 45 50 DATA RATE Mbps Figure 5 Icca vs Data Rate Y A Level Translation 05061 005 Rev 0 Page 8 of 20 Figure 8 Icca vs Capacitive Load at Pin A for Y A 1 8 V 1 2 V CAPACITIVE LOAD pF Level Translation 05061 007 05061 008 Iccy mA Ioca mA lccv mA ADG3300 Ta 25 C TA 25 C 1 CHANNEL 1 CHANNEL Veca 1 8V Vecy 3 3V E q o
7. Dmax A Y 50 Mbps Channel to Channel Skew tskew AY 2 4 ns Part to Part Skew tepskew A Y 4 ns Rev 0 Page 3 of 20 ADG3300 Parameter Symbol Conditions Min Typ Max Unit Y ATranslation Rs Rr 50 O C1 15 pF Figure 34 Propagation Delay tp Y A 5 8 ns Rise Time n Y A 2 3 5 ns Fall Time tr Y a 2 3 5 ns Maximum Data Rate Dmax Y A 50 Mbps Channel to Channel Skew tskew Y A 2 3 ns Part to Part Skew tepskew Y A 3 ns 1 15 V to 1 3 V Vcca Vecy Vecy 2 3 3 V 0 3 V A Y Translation Rs Rt 50 O C 50 pF Figure 33 Propagation Delay tp A Y 9 18 ns Rise Time tR A Y 3 5 ns Fall Time tF AY 2 5 ns Maximum Data Rate Dmax A Y 40 Mbps Channel to Channel Skew tskew A Y 2 5 ns Part to Part Skew tePskEW A Y 10 ns Y A Translation Rs Rt 50 O C1 15 pF Figure 34 Propagation Delay tp Y A 5 9 ns Rise Time tR Y A 2 4 ns Fall Time tF Y A 2 4 ns Maximum Data Rate Dmax Y A 40 Mbps Channel to Channel Skew tskew Y A 2 4 ns Part to Part Skew tPPSKEW Y A 4 ns 1 15 V to 1 3 Vx Vcca Vecy Vecy 1 8 V 0 3 V A Y Translation ges R50 O C 50 pF Figure 33 Propagation Delay i i im i 12 25 ns Rise Time tR AY 1 12 ns Fall Time tF AY 5 ns Maximum Data Rate Dmax A Y 25 Mbps Channel to Channel Skew tskew AY 2 5 ns Part to Part Skew tePskEW A Y 15 ns Y A Translation Rs Rr 50 O C1 15 pF Figure 34 Propagation Delay tp Y A 14 35 ns Rise Time tn Y A 5 16 ns Fall Time tF Y A 2 5 6 5 ns Max
8. logic levels in the A Y direction tr A Y Fall time when translating logic levels in the A Y direction Dmax a Y Guaranteed data rate when translating logic levelstin the A Y direction under the drivigg and loading conditions specified in Table 1 tskew A Y Difference bet Mi prdpagation delays on any two hannels when translating logiel Vels in the A Y direction tPPSKEW A Y Difference in propagation delay between any one channel and the same channel on a different part under the same driving loading conditions when translating logic levels in the A Y direction tp Y A Propagation delay when translating logic levels in the Y A direction tR Y A Rise time when translating logic levels in the Y A direction tF Y A Fall time when translating logic levels in the Y A direction Dmax Y A Guaranteed data rate when translating logic levels in the Y A direction under the driving and loading conditions specified in Table 1 tskew Y A Difference between propagation delays on any two channels when translating logic levels in the Y A direction tPPsKEw Y A Difference in propagation delay between any one channel and the same channel on a different part under the same driving loading conditions when translating in the Y A direction Vcca Vcca supply voltage Vccy Vccy supply voltage Icca Vcc supply current lccv Vccy supply current lHiza Vcca supply current during three state mode EN 0 luizv Vccy supply current during three stat
9. ANALOG Low Voltage 1 15 V to 5 5 V 8 Channel DEVICES Bidirectional Logic Level Translator ADG3300 FEATURES Bidirectional level translation Operates from 1 15 V to 5 5 V Low quiescent current 1 pA No direction pin APPLICATIONS Low voltage ASIC level translation Smart card readers Cell phones and cell phone cradles Portable communications devices Telecommunications equipment Network switches and routers Storage systems SAN NAS Computing server applications GPS Portable POS systems Low cost serial interfaces W GENERAL DESCRIPTION I The ADG3300 is a bidirectional logic level translator that con tains eight bidirectional channels It can be used in multivoltage digital system applications such as data transfer between a low voltage DSP controller and a higher voltage device The internal architecture allows the device to perform bidirectional logic level translation without an additional signal to set the direction of the translation The voltage applied to Vcca sets the logic levels on the A side of the device while Vccy sets the levels on the Y side For proper operation Vcca must always be less than Vccy The Vcca com patible logic signals applied to the A side of the device appear as Vccy compatible levels on the Y side Similarly Vccy compatible logic levels applied to the Y side of the device appear as Vcca compatible logic levels on the A side The enable pin provides three state operation of the
10. DG3300 d Q Q Q Figure 31 Capacitance at Pin Y CAPACITANCE METER 05061 031 05061 033 ADG3300 ADG3300 1MQ NOTES 1 ten IS WHICHEVER IS LARGER BETWEEN ten AND tenz 05061 034 Figure 32 Enable Time ADG3300 ADG3300 SIGNAL 05061 035 05061 036 tey a try a te a y tra y Figure 33 Switching Characteristics A Y Level Translation Figure 34 Switching Characteristics Y A Level Translation Rev 0 Page 13 of 20 ADG3300 TERMINOLOGY Table 4 Symbol Description Vina Logic input high voltage at Pins A1 to A8 Vita Logic input low voltage at Pins A1 to A8 Vona Logic output high voltage at Pins A1 to A8 Vora Logic output low voltage at Pins A1 to A8 RAuiz Pull down resistance measured at Pins A1 to A8 when EN O Viny Logic input high voltage at Pins Y1 to Y8 Viry Logic input low voltage at Pins Y1 to Y8 Von Logic output high voltage at Pins Y1 to Y8 Vo Logic output low voltage at Pins Y1 to Y8 Cy Capacitance measured at Pins Y1 to Y8 EN 0 lv Hiz Leakage current at Pins Y1 to Y8 when EN 0 high impedance state at Pins Y1 to Y8 ViHEN Logic input high voltage at the EN pin Vien Logic input low voltage at the EN pin Cen Capacitance measured at EN pin ILeN Enable EN pin leakage curent ten Three state enable time for Pins Y1 to Y8 tp A Y Propagation delay when translating logic levels in the A Y direction tray Rise time when translating
11. Y side pins When the enable pin EN is pulled low the A1 to A8 pins are Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM VccA Vccv O O O O O O A1 Y1 gt v Ne J va A6 Q C 7 O Ye 05061 001 GND a I 1 internally pulled down by 6 kQ resistors while the Y terminals are in the high impedance state The EN pin is referred to Vcca supply voltage and driven high for normal operation The ADG3300 is available in a compact 20 lead TSSOP package and it is guaranteed to operate over the 1 15 V to 5 5 V supply voltage range and extended 40 C to 85 C temperature range PRODUCT HIGHLIGHTS 1 Bidirectional level translation 2 Fully guaranteed over the 1 15 V to 5 5 V supply range 3 No direction pin 4 20 lead TSSOP package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 Analog Devices Inc All rights reserved ADG3300
12. e mode EN 0 Rev 0 Page 14 of 20 ADG3300 THEORY OF OPERATION The ADG3300 level translator allows the level shifting necessary for data transfer in a system where multiple supply voltages are used The device requires two supplies Vcca and Vccy Vcca Vccy These supplies set the logic levels on each side of the device When driving the A pins the device translates the Vcca compatible logic levels to Vccy compatible logic levels available at the Y pins Similarly since the device is capable of bidirectional translation when driving the Y pins the Vccy compatible logic levels are translated to Vcca compatible logic levels available at the A pins When EN 0 the A1 to A8 are internally pulled down with 6 kQ resistors while Y1 to Y8 pins are three stated When EN is driven high the ADG3300 goes into normal operation mode and performs level translation LEVEL TRANSLATOR ARCHITECTURE The ADG3300 consists of eight bidirectional channels Each channel can translate logic levels in either the A Y or the Y A direction It uses a one shot accelerator architecture which ensures excellent switching characteristics Figure 35 shows a simplified block diagram of a bidirectional channel VccA Vccv 05061 037 Figure 35 Simplified Block Diagram of an ADG3300 Channel The logic level translation in the A Y direction is performed using a level translator U1 and an inverter U2 and the translation in the Y A direction i
13. educed allowing the user to save power which is critical especially for battery operated systems The EN input pin can be driven with either Vcca or Vccy compatible logic levels POWER SUPPLIES For proper operation of the ADG3300 the voltage applied to the Vcca must always be less than or equal to the voltage applied to Vccy To meet this condition the recommended power up sequence is Vccy first and then Vcca The ADG3300 operates properly only after both supply voltages reach their nominal values It is not recommended to use the part in a system where Vcca might be greater than Vccy during power up due to a sig nificant increase in the current taken from the Vcca supply For optimum performance the Vcca and Vccy pins should be decoupled to GND as close as possible to the device Rev 0 Page 15 of 20 ADG3300 DATA RATE The maximum data rate at which the device is guaranteed to operate is a function of the Vcca and Vccy supply voltage combination and the load capacitance It is given by the maximum frequency of a square wave that can be applied to the device which meets the Vou and Vor levels at the output and does not exceed the maximum junction temperature see Table 2 Table 6 shows the guaranteed data rates at which the ADG3300 can operate in both directions A Y and Y A level translation for various Vcca and Vccy supply combinations Table 6 Guaranteed Data Rate Mbps Vccv 1 8V 2 5V 3 3V 5V Vcca 1
14. imum Data Rate Dmax Y A 25 Mbps Channel to Channel Skew tskew Y A 3 6 5 ns Part to Part Skew tePskEW Y A 23 5 ns 2 5 V 0 2 V lt Veca lt Vecy Vecy 2 3 3 V 0 3 V A Y Translation Rs Rr 50 O C 50 pF Figure 33 Propagation Delay tp A Y 7 10 ns Rise Time tR AY 2 5 4 ns Fall Time tF AY 2 5 ns Maximum Data Rate Dmax A Y 60 Mbps Channel to Channel Skew tskEW A Y 1 5 2 ns Part to Part Skew tPPSKEW A Y 4 ns Y ATranslation Rs Rr 50 0 C 15 pF Figure 34 Propagation Delay tp Y A 5 8 ns Rise Time n Y A 1 4 ns Fall Time tF Y A 3 5 ns Maximum Data Rate Dmax Y A 60 Mbps Channel to Channel Skew tskew Y A 2 3 ns Part to Part Skew tepskew Y A 3 ns Rev 0 Page 4 of 20 ADG3300 Parameter Symbol Conditions Min Typ Max Unit POWER REQUIREMENTS Power Supply Voltages Veca Veca Vecy 1 15 5 5 V Vccv 1 65 5 5 V Quiescent Power Supply Current Icca Va 0 V Vcaa Vy 0 V Vecy 0 17 5 uA Vcca Vccv 2 5 5 V EN 1 lccv Va 0 V Vca Vy O V Vecy 0 27 5 uA Vcca 2 Vccv 5 5 V EN 1 Three State Mode Power Supply Current liza Vcca Vecy 5 5 V EN 0 0 1 5 uA luizv Vcca Vecy 5 5 V EN 0 0 1 5 uA 1 Temperature range is a follows B version 40 C to 85 C All typical values are at Ta 25 C unless otherwise noted 3 Guaranteed by design not subject to production test Jl AL Rev 0 Page 5 of 20 ADG3300 ABSOLUTE MAXIMUM RATINGS Ta 25 C unle
15. on Delay tpu vs Capacitive Load at Pin A Y A Level Translation 05061 018 05061 019 05061 020 ADG3300 Ta 25 C C 50pF Ta 25 C DATA RATE 25Mbps 1 CHANNEL DATA RATE 50Mbps C 15pF 1 CHANNEL 05061 021 200mV DIV 5ns DIV Figure 21 Eye Diagram at Y Output 1 2 V to 1 8 V Level Translation 25 Mbps Figure 24 Eye Diagram at A Output 3 3 V to 1 8 V Level Translation 50 Mbps 400mV DIV 3ns DIV 05061 024 TA 25 C DATA RATE 25Mbps C 50pF 1 CHANNEL Ta 25 C DATA RATE 50Mbps CL 50pF 1 CHANNEL 400mV DIV 05061 025 Figure 22 Eye Diagram at A Output 1 8 V to 1 2 V Level Translation 25 Mbps Figure 25 Eye Diagram at Y Output 3 3 V to 5 V Level Translation 50 Mbps TA 25 C CL O Bite saps eae DATA RATE Bite saps eae 1 CHANNEL Ta 25 C DATA RATE 50Mbps C 15pF 1 CHANNEL Eu HF aan eee nni mpm 3ns DIV 023 05061 026 800mV DIV 3ns DIV Figure 23 Eye Diagram at Y Output 1 8 V to 3 3 V Level Translation 50 Mbps Figure 26 Eye Diagram at A Output 5 V to 3 3 V Level Translation 50 Mbps Rev 0 Page 11 of 20 ADG3300 TEST CIRCUITS Q ADG3300 C O HH O Figure 28 Vou Vo1 Voltages at Pin Y Q ADG3300 Q C e O lt Figure 29 Three State Leakage Current at Pin Y 05061 027 05061 028 05061 030 Rev 0 Page 12 of 20 ADG3300 O Q HLZEH Figure 30 EN Pin Leakage Current d A
16. ot This effect can be reduced by keeping the length of the tracks as short as possible A solid copper plane for the return path GND is also recommended Rev 0 Page 17 of 20 ADG3300 OUTLINE DIMENSIONS 0 75 amp gt ke 0 60 0 0 45 COMPLIANT TO JEDEC STANDARDS MO 153AC Figure 38 20 Lead Thin Shrink Small Outline Package TSSOP RU 20 Dimensions shown in millimeters ORDERING GUIDE EL Model TRATAT Range Package D scription prose Option ADG3300BRUZ 40 C to4 85 C WW 1 TSS P U 20 ADG3300BRUZ REEL 40 C to 85 C TSSOP RU 20 ADG3300BRUZ REEL 7 40 C to 85 C TSSOP RU 20 Z Pb free part Rev 0 Page 18 of 20 ADG3300 NOTES ww BDI C conh ALI ADG3300 NOTES VW D i AL 2005 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www ana l 0 g com 55535 Lagi DEVICES Rev 0 Page 20 of 20
17. s performed using the inverters U3 and U4 The one shot generator detects a rising or falling edge present on either the A side or the Y side of the channel It sends a short pulse that turns on the PMOS transistors T1 T2 for a rising edge or the NMOS transistors T3 T4 for a falling edge This charges discharges the capacitive load faster which results in fast rise and fall times The inputs of the unused channels A or Y should be tied to their corresponding Vcc rail Voca or Vocy or to GND INPUT DRIVING REQUIREMENTS To ensure correct operation of the ADG3300 the circuit that drives the input of an ADG3300 channels should have an output impedance of less than or equal to 150 Q and a minimum current driving capability of 36 mA OUTPUT LOAD REQUIREMENTS The ADG3300 level translator is designed to drive CMOS compatible loads If current driving capability is required it is recommended to use buffers between the ADG3300 outputs and the load ENABLE OPERATION The ADG3300 provides three state operation at the Y I O pins by using the enable EN pin as shown in Table 5 Table 5 Truth Table EN Y I O Pins A 1 0 Pins 0 Hi Z 6 kQ pull down to GND 1 Normal operation Normal operation High impedance state In normal operation the ADG3300 performs level translation When EN 0 thie AIVG3800gnters into three state mode In this mode the current consuniption from both the Vcca and Vey supplies is r
18. ss otherwise noted Table 2 Parameter Rating Vcca to GND 0 3 V to 7 V Vccy to GND Vcca to 7 V Digtal Inputs A 0 3 V to Vcca 0 3 V Digtal Inputs Y 0 3 V to Vccy 0 3 V EN to GND 0 3 V to 7 V Operating Temperature Range Industrial B Version 40 C to 85 C Storage Temperature Range 65 C to 150 C Junction Temperature 150 C Oja Thermal Impedance 4 Layer Board 20 Lead TSSOP 78 C W Lead Temperature Soldering 10 sec 300 C IR Reflow Peak Temperature lt 20 sec 260 C ESD CAUTION ESD electrostatic discharge sensitivesdevice Electrostatic charges as High as 4090 readily aceumulate on J S proprietary ESD protection circuitry permanent damage may Occur Off devices subjected to high Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Only one absolute maximum rating may be applied at any one time human body and test equipment Bad kan discharge without detection Although Jthis product de WARNING S nergy Ath electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality
19. vice using an 8 bit bus V0 2 O 34 0 3 O 34 microprocessor 14 C MICROCONTROLLER DSP vos O 3 4 PERIPHERAL DEVICE 0 6 O 34 v0 7 O 10 8 O 34 lt a 05061 038 Figure 36 1 8 V to 3 3 V 8 Bit Level Translation Circuit When the application requires level translation between a microprocessor and multiple peripheral devices the ADG3300 Y I O pins Y1 to Y8 can be three stated by setting EN 0 This feature allows the ADG3300 to share the data buses with ADG3300 other devices without causing contention issues Figure 37 shows an application where a 3 3 V microprocessor is connected to 1 8 V peripheral devices using the three state feature MICROPROCESSOR l Op4 Ya Q V0 4 PERIPHERAL MICROCONTROLLER DEVICE 1 PERIPHERAL DEVICE 2 05061 039 Figure 37 1 8V to d Level Translation Circuit Using the Tfiree State Feature LAYOUT GUIDELINES As with any high speed digital IC the printed circuit board layout is important in the overall circuit performance Care should be taken to ensure proper power supply bypass and return paths for the high speed signals Each Vcc pin Vcca and Vccy should be bypassed using low effective series resistance ESR and effective series inductance ESI capacitors placed as close as possible to the Vcca and Vccy pins The parasitic induc tance of the high speed signal track might cause significant oversho
20. wn Resistance RAuiz EN 0 4 2 6 8 4 kQ Y Side Input Low Voltage Viny Vcc 0 4 V Input High Voltage Vi 0 4 V Output High Voltage Vonv Va Vcca lon 20 uA Figure 28 Vecy 0 4 V Output Low Voltage Voi Va 0 V lo 20 uA Figure 28 0 4 V Capacitance C f 1 MHz EN 0 Figure 31 6 pF Leakage Current lv Hiz Vy 0 V Vccy EN 0 Figure 29 1 uA Enable EN Input High Voltage ViHEN Vcca 1 15 V Vcca 0 3 V Vihen Vcca 1 2 V to 5 5 V Vcca 0 4 V Input Low Voltage Vien 0 4 V Leakage Current In Veys 0 V Veca Va 0 V Figure 30 1 uA Capacitance i i Cen i 3 pF Enable Time ten RO RE 50 9 VR 0 VIE AY E 1 18 us Figure 32 SWITCHING CHARACTERISTICS 3 3 V 0 3 V Vcc Vecy Vev 2 5 V 0 5 V A Y Level Translation Rs Rt 50 O C 50 pF Figure 33 Propagation Delay tp A Y 6 10 ns Rise Time tR A Y 2 3 5 ns Fall Time tF AY 2 3 5 ns Maximum Data Rate Dmax A Y 50 Mbps Channel to Channel Skew tskew AY 2 4 ns Part to Part Skew tPPSkEW A Y 3 ns Y A Level Translation Rs Rr 50 O C 15 pF Figure 34 Propagation Delay tp Y A 4 7 ns Rise Time n Y A 1 3 ns Fall Time tF Y A 3 7 ns Maximum Data Rate Dmax Y A 50 Mbps Channel to Channel Skew tskew Y A 2 3 5 ns Part to Part Skew tPPSKEW Y A 2 ns 1 8 V 0 15 V lt Vcc lt Vecy Vecy 3 3 0 3 V A Y Translation Rs Rr 50 O C 50 pF Figure 33 Propagation Delay tp A Y 8 11 ns Rise Time tn A Y 2 5 ns Fall Time tF AY 2 5 ns Maximum Data Rate

ANALOG DEVICES ADG3300 handbook(1)

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