ANALOG DEVICES +2.5 V to +5.5 V 230 mA Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs AD5302/AD5312/AD5322* handbook
Contents
1. 005 150 C 10 Lead wSOIC Package Power Dissipation 05 T Max T y4 Oja Thermal Impedance 0000 206 C W Ojc Thermal Impedance 00005 44 C W Lead Temperature Soldering Vapor Phase 60 sec 2 cece eee eee eee 215 C Infrared 15 Seg Iren isk Seeds r E EEA 220 C NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating condi tions for extended periods may affect device reliability Transient currents of up to 100 mA will not cause SCR latch up ORDERING GUIDE Temperature Package Package Branding Model Range Description Option Information AD5302BRM 40 C to 105 C uSOIC RM 10 D5B AD5312BRM 40 C to 105 C uSOIC RM 10 D6B AD5322BRM 40 C to 105 C uSOIC RM 10 D7B CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily WARNING s accumulate on the human body and test equipment and can discharge without detection Although the AD5302 AD5312 AD5322 features proprietary ESD protection circuitry perma eprint 4 nent damage may occur on devices subjected to high energy electrostatic discharges Therefore ESD SENSI2. The bias generator the output amplifier the resistor string and all other associated linear circuitry are all shut down when the power down mode is activated However the contents of the registers are unaffected when in power down The time to exit power down is typically 2 5 us for Vpp 5 V and 5 us when Vpop 3 V See Figure 21 for a plot RESISTOR STRING DAC POWER DOWN CIRCUITRY Figure 31 Output Stage During Power Down 2 MICROPROCESSOR INTERFACING AD5302 AD5312 AD5322 to ADSP 2101 ADSP 2103 Interface Figure 32 shows a serial interface between the AD5302 AD5312 AD5322 and the ADSP 2101 ADSP 2103 The ADSP 2101 ADSP 2103 should be set up to operate in the SPORT Trans mit Alternate Framing Mode The ADSP 2101 ADSP 2103 SPORT is programmed through the SPORT control register and should be configured as follows Internal Clock Operation Active Low Framing 16 Bit Word Length Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled The data is clocked out on each falling edge of the DSP s serial clock and clocked into the AD5302 AD5312 AD5322 on the rising edge of the DSP s serial clock This corre sponds to the falling edge of the DAC s SCLK AD5302 AD5312 AD5322 ADSP 2101 ADSP 2103 SYNC ADDITIONAL PINS OMITTED FOR CLARITY Figure 32 AD5302 AD5312 AD5322 to ADSP 2101 ADSP 2103 Interface AD5302 AD5312 AD5322 to 68HC11 68L11 Interface Figu
3. Figure 10 AD5302 INL and DNL Error vs VREF REV 0 Ta 25 C Vpp 5V INL ERROR LSBs 0 200 400 600 800 1000 CODE Figure 5 AD5312 Typical INL Plot Ty 25 C Vpp 5V DNL ERROR LSBs 0 200 400 600 800 1000 CODE Figure 8 AD5312 Typical DNL Plot Vpp 5V Vrer 3V a MAX DNL MAX INL a N 4 i a o 0 25 m 0 50 0 75 1 00 40 0 40 80 120 TEMPERATURE C Figure 11 AD5302 INL Error and DNL Error vs Temperature DNL ERROR LSBs INL ERROR LSBs 3000 4000 0 1000 2000 CODE Figure 6 AD5322 Typical INL Plot 0 1000 2000 3000 4000 CODE Figure 9 AD5322 Typical DNL Plot GAIN ERROR OFFSET ERR 1 0 40 0 40 80 120 TEMPERATURE C Figure 12 Offset Error and Gain Error vs Temperature AD5302 AD5312 AD5322 ZL 100 150 200 250 300 350 400 Ibp BA FREQUENCY Figure 13 Ipp Histogram with Vpp 3 Vand Vpp 5 V BOTH DACS IN GAIN OF TWO MODE REFERENCE INPUTS BUFFERED 25 30 35 40 45 50 5 5 Vpp Volts Figure 16 Supply Current vs Supply Voltage CH2 CH1 CH1 1V CH2 5V TIME BASE 5ys DIV Figure 19 Half Scale Settling 1 4 to 3 4 Scale Code Change Vout Volts SINK SOURCE CURREN
4. 0 30 SEATING g zan rg T PLANE 0 009 0 23 0 028 0 70 i 0 005 0 13 0 016 0 40 16 REV 0 C3447 8 3 99 PRINTED IN U S A
5. 11 AD5302 AD5312 AD5322 POWER DOWN MODES The AD5302 AD5312 AD5322 have very low power consump tion dissipating only 0 7 mW with a 3 V supply and 1 5 mW with a 5 V supply Power consumption can be further reduced when the DACs are not in use by putting them into one of three power down modes which are selected by Bits 13 and 12 PD1 and PDO of the control word Table II shows how the state of the bits corresponds to the mode of operation of that particular DAC Table II PD1 PD0 Operating Modes PD1 PDO Operating Mode 0 0 Normal Operation 0 1 Power Down 1 kQ Load to GND 1 0 Power Down 100 kQ Load to GND 1 1 Power Down High Impedance Output When both bits are set to 0 the DACs work normally with their normal power consumption of 300 uA at 5 V However for the three power down modes the supply current falls to 200 nA at 5 V 50 nA at 3 V Not only does the supply current drop but the output stage is also internally switched from the output of the amplifier to a resistor network of known values This has the advantage that the output impedance of the part is known while the part is in power down mode and provides a defined input condition for whatever is connected to the output of the DAC amplifier There are three different options The output is con nected internally to GND through a 1 KQ resistor a 100 KQ resistor or it is left open circuited Three State The output stage is illustrated in Figure 31
6. The 10 uF capaci tors are the tantalum bead type The 0 1 uF capacitor should have low Effective Series Resistance ESR and Effective Series Inductance ESI like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching The power supply lines of the AD5302 AD5312 AD5322 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs Avoid crossover of digital and analog signals Traces on opposite sides of the board should run at right angles to each other This reduces the effects of feedthrough through the board A microstrip tech nique is by far the best but not always possible with a double sided board In this technique the component side of the board is dedicated to ground plane while signal traces are placed on the solder side 15 AD5302 AD5312 AD5322 OUTLINE DIMENSIONS Dimensions shown in inches and mm 10 Lead pSOIC RM 10 0 122 3 10 7 0 114 2 90 0 122 3 10 0 199 5 05 0 114 2 90 0 187 4 75 PIN gt e 0 0197 0 50 BSC 0 120 3 05 0 120 3 05 0 112 2 85 ME 2 85 0 037 0 98 Fe Gar F 0 043 1 10 0 031 0 78 MAX 4 0 006 0 15 0 012
7. AD5302 AD5312 AD5322 while RXD drives the serial data line of the part The SYNC signal is again derived from a bit programmable pin on the port In this case port line P3 3 is used When data is to be transmitted to the AD5302 AD5312 AD5322 P3 3 is taken low The 80C51 80L51 trans mits data only in 8 bit bytes thus only eight falling clock edges occur in the transmit cycle To load data to the DAC P3 3 is left low after the first eight bits are transmitted and a second write cycle is initiated to transmit the second byte of data P3 3 is taken high following the completion of this cycle The 80C51 80L51 outputs the serial data in a format that has the LSB first The AD5302 AD5312 AD5322 requires its data with the MSB as the first bit received The 80C51 80L51 transmit routine should take this into account AD5302 AD5312 AD5322 80C51 80L51 SYNC ADDITIONAL PINS OMITTED FOR CLARITY Figure 34 AD5302 AD5312 AD5322 to 80C51 80L51 Interface AD5302 AD5312 AD5322 to MICROWIRE Interface Figure 35 shows an interface between the AD5302 AD5312 AD5322 and any MICROWIRE compatible device Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5302 AD5312 AD5322 on the rising edge of the SK AD5302 AD5312 AD5322 SYNC MICROWIRE ADDITIONAL PINS OMITTED FOR CLARITY Figure 35 AD5302 AD5312 AD5322 to MICROWIRE Interface REV 0 APPLICATIONS INFORMATION Typical A
8. design A typical DNL vs code plot can be seen in Figure 7 OFFSET ERROR This is a measure of the offset error of the DAC and the output amplifier It is expressed as a percentage of the full scale range GAIN ERROR This is a measure of the span error of the DAC It is the devia tion in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full scale range OFFSET ERROR DRIFT This is a measure of the change in offset error with changes in temperature It is expressed in ppm of full scale range C REV 0 perature It is expressed in ppm of full scale range C MAJOR CODE TRANSITION GLITCH ENERGY Major code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC regis ter changes state It is normally specified as the area of the glitch in nV secs and is measured when the digital code is changed by 1 LSB at the major carry transition 011 11 to 100 00 or 100 00 to 011 11 DIGITAL FEEDTHROUGH Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device but is measured when the DAC is not being written to SYNC held high It is specified in nV secs and is measured with a full scale change on the digital input pins i e from all 0s to all 1s and vice versa ANALOG CROSSTALK This is the glitch impulse transferred to the output of one DAC due
9. 10 or 12 bits of DAC data depend ing on the device type The first bit loaded is the MSB Bit 15 which determines whether the data is for DAC A or DAC B Bit 14 determines if the reference input will be buffered or unbuf fered Bits 13 and 12 control the operating mode of the DAC Table I Control Bits Power On Bit Name Function Default 15 A B 0 Data Written to DACA N A 1 Data Written to DAC B 14 BUF 0 Reference Is Unbuffered 0 1 Reference Is Buffered 13 PD1 Mode Bit 0 12 PDO Mode Bit 0 DB15 MSB DBO LSB fare uF Po1 Po9 o7 ve os va os o2 o1 vo x x x x lt pata sits gt Figure 28 AD5302 Input Shift Register Contents DB15 MSB DBO LSB are uF Pox Poo os ve o7 ps os oa vs va ot oo x x lt pata sits gt Figure 29 AD5312 Input Shift Register Contents DB15 MSB DBO LSB aie ee us bie a oe e Oe ne be Bo je pata sits _ gt Figure 30 AD5322 Input Shift Register Contents The remaining bits are DAC data bits starting with the MSB and ending with the LSB The AD5322 uses all 12 bits of DAC data the AD5312 uses 10 bits and ignores the 2 LSBs The AD5302 uses eight bits and ignores the last four bits The data format is straight binary with all zeroes corresponding to 0 V output and all ones corresponding to full scale output Vrer 1 LSB REV 0 The SYNC input is a level triggered i
10. 6 Single DAC Channel Architecture Resistor String The resistor string section is shown in Figure 27 It is simply a string of resistors each of value R The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier The voltage is tapped off by closing one of the switches connecting the string to the amplifier Because it is a string of resistors it is guaranteed monotonic 10 R R R TO OUTPUT AMPLIFIER 1 1 I I i i 1 1 I I R R Figure 27 Resistor String DAC Reference Inputs There is a reference input pin for each of the two DACs The reference inputs are buffered but can also be configured as un buffered The advantage with the buffered input is the high impedance it presents to the voltage source driving it However if the unbuffered mode is used the user can have a reference voltage as low as GND and as high as Vpp since there is no restriction due to headroom and foot room of the reference amplifier If there is a buffered reference in the circuit e g REF192 there is no need to use the on chip buffers of the AD5302 AD5312 AD5322 In unbuffered mode the impedance is still large 180 kQ per reference input The buffered unbuffered option is controlled by the BUF bit in the control word see Serial Interface section for a description of the register contents Output Amplifier The output buffer amplifier is capable of gen
11. AD5322 RESISTOR NETWORK One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 1999 AD9302 AD5312 AD5322 SPECIFICATIONS vn 25vt 55v vr 2v R 240 to GND C 200 pF to GND all specifications Tm to Tmax unless otherwise noted B Version Parameter Min Typ Max Units Conditions Comments DC PERFORMANCE AD5302 Resolution 8 Bits Relative Accuracy 0 15 1 LSB Differential Nonlinearity 0 02 0 25 LSB Guaranteed Monotonic by Design Over All Codes AD5312 Resolution 10 Bits Relative Accuracy 0 5 3 LSB Differential Nonlinearity 0 05 0 5 LSB Guaranteed Monotonic by Design Over All Codes AD5322 Resolution 12 Bits Relative Accuracy 2 12 LSB Differential Nonlinearity 0 2 1 LSB Guaranteed Monotonic by Design Over All Codes Offset Error 0 4 of FSR See Figures 2 and 3 Gain Error 0 15 1 of FSR See Figures 2 and 3 Lower Deadband 10 60 mV See Figures 2 and 3 Offset Error Drift 12 ppm of FSR C Gain Error Drift 5 ppm of FSR C Power Supply Rejection Ratio 60 dB AVpp 10 DC Crosstalk 30 uV DAC REFERENCE INPUTS Veer Input Range 1 Vpp Vv Buffered Reference Mode 0 Vpp Vv Unbuffered Reference Mode Veer Input Impedance gt 10 MQ Buffered Reference Mode 180 kQ Unbuffered Reference Mode Input Impedance Rpac Reference Feedthrough 90 dB Frequency 10 kHz Cha
12. ANALOG DEVICES 2 5 V to 5 5 V 230 pA Dual Rail to Rail Voltage Output 8 10 12 Bit DACs AD9302 AD5312 AD5322 FEATURES AD5302 Two 8 Bit Buffered DACs in One Package AD5312 Two 10 Bit Buffered DACs in One Package AD5322 Two 12 Bit Buffered DACs in One Package 10 Lead SOIC Package Micropower Operation 300 pA 5 V Including Reference Current Power Down to 200 nA 5V 50nA 3V 2 5 V to 5 5 V Power Supply Double Buffered Input Logic Guaranteed Monotonic By Design Over All Codes Buffered Unbuffered Reference Input Options 0 Vper Output Voltage Power On Reset to Zero Volts Simultaneous Update of DAC Outputs via LDAC Low Power Serial Interface with Schmitt Triggered Inputs On Chip Rail to Rail Output Buffer Amplifiers APPLICATIONS Portable Battery Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators GENERAL DESCRIPTION The AD5302 AD5312 AD5322 are dual 8 10 and 12 bit buff ered voltage output DACs in a 10 lead SOIC package that operate from a single 2 5 V to 5 5 V supply consuming 230 uA at 3 V Their on chip output amplifiers allow the outputs to swing rail to rail with a slew rate of 0 7 V us The AD5302 AD5312 AD5322 utilize a versatile 3 wire serial interface which operates at clock rates up to 30 MHz and is compatible with standard SPI QSPI MICROWIRE and DSP interface standards The references for the two DACs
13. F X R2 R1 where D is the decimal equivalent of the code loaded to the DAC N is the DAC resolution Veer is the reference voltage input with Vrer 5 V R1 R2 10 kQ and Vpp 5 V Vour 10 x DI2 5 V Opto Isolated Interface for Process Control Applications The AD5302 AD5312 AD5322 has a versatile 3 wire serial interface making it ideal for generating accurate voltages in process control and industrial applications Due to noise safety requirements or distance it may be necessary to isolate the AD5302 AD5312 AD5322 from the controller This can easily be achieved by using opto isolators which will provide isolation in excess of 3 kV The serial loading structure of the AD5302 AD5312 AD5322 makes it ideally suited for use in opto isolated applications Figure 39 shows an opto isolated interface to the AD5302 AD5312 AD5322 where DIN SCLK and SYNC are driven from opto couplers The power supply to the part also needs to be isolated This is done by using a transformer On the DAC side of the transformer a 5 V regulator provides the 5 V supply required for the AD5302 AD5312 AD5322 5V REGULATOR POWER AD5302 AD5312 AD5322 SYNC O Figure 39 AD5302 AD5312 AD5322 in an Opto Isolated Interface 14 REV 0 AD5302 AD5312 AD5322 Decoding Multiple AD5302 AD5312 AD5322s The SYNC pin on the AD5302 AD5312 AD5322 can be used in applications to decode a number of DACs In this applica tion all the DACs in t
14. T mA Figure 14 Source and Sink Current Capability DACS IN E STATE CONDITION 2 7 3 2 3 7 4 2 4 7 5 2 Vpp Volts Figure 17 Power Down Current vs Supply Voltage Ta 25 C CH1 VoutA CH2 CH1 1V CH2 1V TIME BASE 20us DIV Figure 20 Power On Reset to 0 V o ZERO SCALE FULL SCALE Figure 15 Supply Current vs Code Ta 25 C 0 0 5 1 01 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 Viogic Volts Figure 18 Supply Current vs Logic Input Voltage Ta 25 C CH1 CH1 1V CH3 5V TIME BASE 1ps DIV Figure 21 Exiting Power Down to Midscale REV 0 N A Vout Volts N A 2 47 ied 1ps DIV Figure 22 AD5322 Major Code Transition FULL SCALE ERROR Volts 0 1 2 3 4 5 Vrer Volts Figure 25 Full Scale Error vs Vrer Buffered REV 0 dB 60 0 01 0 1 1 10 100 1k 10k FREQUENCY kHz Figure 23 Multiplying Bandwidth Small Signal Frequency Response AD5302 AD5312 AD5322 2mv DIV 500ns DIV Figure 24 DAC DAC Crosstalk AD5302 AD5312 AD5322 GENERAL DESCRIPTION The AD5302 AD5312 AD5322 are dual resistor string DACs fabricate
15. TIVE DEVICE proper ESD precautions are recommended to avoid performance degradation or loss of functionality oe REV 0 AD5302 AD5312 AD5322 PIN FUNCTION DESCRIPTIONS Pin No Mnemonic Function 1 LDAC Active low control input that transfers the contents of the input registers to their respective DAC regis ters Pulsing this pin low allows either or both DAC registers to be updated if the input registers have new data This allows simultaneous update of both DAC outputs 2 Vpp Power Supply Input These parts can be operated from 2 5 V to 5 5 V and the supply should be de coupled to GND 3 VRerB Reference Input Pin for DAC B This is the reference for DAC B It may be configured as a buffered or an unbuffered input depending on the BUF bit in the control word of DAC B It has an input range from 0 V to Vpp in unbuffered mode and from 1 V to Vpp in buffered mode 4 VrerA Reference Input Pin for DAC A This is the reference for DAC A It may be configured as a buffered or an unbuffered input depending on the BUF bit in the control word of DAC A It has an input range from 0 V to Vpp in unbuffered mode and from 1 V to Vpp in buffered mode 5 VoutA Buffered Analog Output Voltage from DAC A The output amplifier has rail to rail operation VoutB Buffered Analog Output Voltage from DAC B The output amplifier has rail to rail operation 7 SYNC Active Low Control Input This is the frame synchronization signal for the inpu
16. are derived from two reference pins one per DAC The reference inputs may be configured as buffered or unbuffered inputs The outputs of both DACs may be updated simultaneously using the asynchronous LDAC in put The parts incorporate a power on reset circuit that ensures that the DAC outputs power up to 0 V and remain there until a valid write takes place to the device The parts contain a power down feature that reduces the current consumption of the devices to 200 nA at 5 V 50 nA at 3 V and provides software selectable output loads while in power down mode The low power consumption of these parts in normal operation make them ideally suited to portable battery operated equip ment The power consumption is 1 5 mW at 5 V 0 7 mW at 3 V reducing to 1 uW in power down mode FUNCTIONAL BLOCK DIAGRAM VoD INPUT DAC REGISTER REGISTER ae V INPUT V DAC REGISTER C REGISTER Patent Pending protected by U S Patent No 5684481 SPI and QSPI are trademarks of Motorola Inc MICROWIRE is a trademark of National Semiconductor Corporation REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices VrerA AD5302 AD5312
17. d from the REF195 is 300 uA supply current and approximately 30 uA into each of the reference inputs This is with no load on the DAC outputs When the DAC outputs are loaded the REF 195 also needs to supply the current to the loads The total current required with a 10 kQ load on each output is 360 pA 2 5 V 10 kQ 1 36 mA The load regulation of the REF195 is typically 2 ppm mA which results in an error of 2 7 ppm 13 5 uV for the 1 36 mA current drawn from it This corresponds to a 0 0007 LSB error at 8 bits and 0 011 LSB error at 12 bits 13 AD5302 AD5312 AD5322 6V TO 16V O REF195 Vout VrerB VoutA AD5302 AD5312 SERIAL INTERFACE Figure 37 Using an REF195 as Power and Reference to the AD5302 AD5312 AD5322 Bipolar Operation Using the AD5302 AD5312 AD5322 The AD5302 AD5312 AD5322 has been designed for single supply operation but bipolar operation is also achievable using the circuit shown in Figure 38 The circuit shown has been config ured to achieve an output voltage range of 5 V lt Vour lt 5 V Rail to rail operation at the amplifier output is achievable using an AD820 or OP295 as the output amplifier 6V TO 16V Vpp 5V 5 DD 5 R2 AD5302 AD5312 AD5322 SCLK DIN VoutA B SYNC SERIAL INTERFACE Figure 38 Bipolar Operation Using the AD5302 AD5312 AD5322 The output voltage for any input code can be calculated as follows Vour Vrer X D 2 x R1 R2 R1 VRE
18. d i e LDAC is high It is expressed in dBs TOTAL HARMONIC DISTORTION This is the difference between an ideal sine wave and its attenu ated version using the DAC The sine wave is used as the refer ence for the DAC and the THD is a measure of the harmonics present on the DAC output It is measured in dBs MULTIPLYING BANDWIDTH The amplifiers within the DAC have a finite bandwidth The multiplying bandwidth is a measure of this A sine wave on the reference with full scale code loaded to the DAC appears on the output The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input CHANNEL TO CHANNEL ISOLATION This is a ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of the other DAC It is measured in dBs GAIN ERROR PLUS OFFSET ERROR OUTPUT VOLTAGE ACTUAL POSITIVE OFFSET ERROR DAC CODE DEADBAND AMPLIFIER FOOTROOM 1mV NEGATIVE OFFSET ERROR Figure 2 Transfer Function with Negative Offset GAIN ERROR PLUS ACTUAL OFFSET ERROR OUTPUT VOLTAGE POSITIVE OFFSET ERROR DAC CODE Figure 3 Transfer Function with Positive Offset REV 0 Typical Performance Characteristics AD5302 AD5312 AD5322 INL ERROR LSBs Ty 25 C Vpp 5V DNL ERROR LSBs MAX DNL MIN DNL MIN INL ERROR LSBs Vrer Volts
19. d on a CMOS process with resolutions of 8 10 and 12 bits respectively They contain reference buffers output buffer amplifiers and are written to via a 3 wire serial interface They operate from single supplies of 2 5 V to 5 5 V and the output buffer amplifiers provide rail to rail output swing with a slew rate of 0 7 V s Each DAC is provided with a separate refer ence input which may be buffered to draw virtually no current from the reference source or unbuffered to give a reference input range from GND to Vpp The devices have three program mable power down modes in which one or both DACs may be turned off completely with a high impedance output or the output may be pulled low by an on chip resistor Digital to Analog Section The architecture of one DAC channel consists of a reference buffer and a resistor string DAC followed by an output buffer amplifier The voltage at the Vggr pin provides the reference voltage for the DAC Figure 26 shows a block diagram of the DAC architecture Since the input coding to the DAC is straight binary the ideal output voltage is given by Vrer X D Vour a aa where D decimal equivalent of the binary code that is loaded to the DAC register 0 255 for AD5302 8 Bits 0 1023 for AD5312 10 Bits 0 4095 for AD5322 12 Bits N DAC resolution SWITCH REFERENCE CONTROLLED BUFFER BY CONTROL LOGIC DAC REGISTER O VourA OUTPUT BUFFER INPUT REGISTER AMPLIFIER Figure 2
20. er output to reach its minimum voltage Offset Error must be negative In order for the amplifier output to reach its maximum voltage Veer Vpp and Offset plus Gain Error must be positive Specifications subject to change without notice 2 REV 0 AD5302 AD5312 AD5322 Von 2 5 V to 5 5 V Ri 2 KQ to GND C 200 pF to GND all specifications Tm to Tmax unless AC CHARACTERISTICS otherwise noted B Version Parameter Min Typ Max Units Conditions Comments Output Voltage Settling Time Veer Vpp 5 V AD5302 6 8 us 1 4 Scale to 3 4 Scale Change 40 Hex to C0 Hex AD5312 7 9 us 1 4 Scale to 3 4 Scale Change 100 Hex to 300 Hex AD5322 8 10 us 1 4 Scale to 3 4 Scale Change 400 Hex to C00 Hex Slew Rate 0 7 V us Major Code Transition Glitch Energy 12 nV s 1 LSB Change Around Major Carry 011 11 to 100 00 Digital Feedthrough 0 10 nV s Analog Crosstalk 0 01 nV s DAC to DAC Crosstalk 0 01 nV s Multiplying Bandwidth 200 kHz Vere 2 Vt 0 1 V p p Unbuffered Mode Total Harmonic Distortion 70 dB Veer 2 5 V t 0 1 V p p Frequency 10 kHz NOTES 1Guaranteed by design and characterization not production tested See Terminology 3Temperature range B Version 40 C to 105 C Specifications subject to change without notice TIM NG C HARACTERISTI cs 2 3 Vio 2 5 V to 5 5 V all specifications Tm to Tmax unless otherwise noted Limit at Tins Tmax Parameter B Versio
21. erating output voltages to within 1 mV of either rail which gives an output range of 0 001 V to Vpp 0 001 V when the reference is Vpp It is capable of driving a load of 2 kQ in parallel with 500 pF to GND and Vpp The source and sink capabilities of the output amplifier can be seen in Figure 14 The slew rate is 0 7 V us with a half scale settling time to 0 5 LSB at 8 bits of 6 us See Figure 19 POWER ON RESET The AD5302 AD5312 AD5322 are provided with a power on reset function so that they power up in a defined state The power on state is Normal operation Reference inputs unbuffered Output voltage set to 0 V Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up REV 0 AD5302 AD5312 AD5322 SERIAL INTERFACE The AD5302 AD5312 AD5322 are controlled over a versatile 3 wire serial interface which operates at clock rates up to 30 MHz and is compatible with SPI QSPI MICROWIRE and DSP interface standards Input Shift Register The input shift register is 16 bits wide see Figures 28 30 below Data is loaded into the device as a 16 bit word under the con trol of a serial clock input SCLK The timing diagram for this operation is shown in Figure 1 The 16 bit word consists of four control bits followed by 8
22. fered Interface The AD5302 AD5312 AD5322 DACs all have double buffered interfaces consisting of two banks of registers input registers and DAC registers The input register is connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence The DAC register contains the digital code used by the resistor string Access to the DAC register is controlled by the LDAC function When LDAC is high the DAC register is latched and the input register may change state without affecting the contents of the DAC register However when LDAC is brought low the DAC register becomes transparent and the contents of the input regis ter are transferred to it This is useful if the user requires simultaneous updating of both DAC outputs The user may write to both input registers indi vidually and then by pulsing the LDAC input low both outputs will update simultaneously These parts contain an extra feature whereby the DAC register is not updated unless its input register has been updated since the last time that LDAC was brought low Normally when LDAC is brought low the DAC registers are filled with the contents of the input registers In the case of the AD5302 AD5312 AD5322 the part will only update the DAC register if the input register has been changed since the last time the DAC register was updated thereby removing unnecessary digital crosstalk
23. he system receive the same serial clock and serial data but only the SYNC to one of the devices will be active at any one time allowing access to two channels in this eight channel system The 74HC139 is used as a 2 to 4 line decoder to address any of the DACs in the system To prevent timing errors from occurring the enable input should be brought to its inactive state while the coded address inputs are changing state Figure 40 shows a diagram of a typical setup for decoding multiple AD5302 AD5312 AD5322 devices in a system AD5302 AD5312 AD5322 CODED ADDRESS Figure 40 Decoding Multiple AD5302 AD5312 AD5322 Devices in a System AD5302 AD5312 AD5322 as a Digitally Programmable Window Detector A digitally programmable upper lower limit detector using the two DACs in the AD5302 AD5312 AD5322 is shown in Figure 41 The upper and lower limits for the test are loaded to DACs A and B which in turn set the limits on the CMP04 If the signal at the Vw input is not within the programmed window an LED will indicate the fail condition 5V O VREF O AD5302 AD5312 AD5322 SYNC O DIN O SOLO 1 6 74HC05 Figure 41 Window Detector Using AD5302 AD5312 AD5322 REV 0 Coarse and Fine Adjustment Using the AD5302 AD5312 AD5322 The DACs in the AD5302 AD5312 AD5322 can be paired together to form a coarse and fine adjustment function as shown in Figure 42 DAC A is used to provide the coarse ad justment while DAC B provides
24. n Units Conditions Comments t 33 ns min SCLK Cycle Time ty 13 ns min SCLK High Time t3 13 ns min SCLK Low Time t4 0 ns min SYNC to SCLK Active Edge Setup Time ts 5 ns min Data Setup Time te 4 5 ns min Data Hold Time t7 0 ns min SCLK Falling Edge to SYNC Rising Edge tg 100 ns min Minimum SYNC High Time to 20 ns min LDAC Pulsewidth tio 20 ns min SCLK Falling Edge to LDAC Rising Edge NOTES 1Guaranteed by design and characterization not production tested All input signals are specified with tr tf 5 ns 10 to 90 of Vpp and timed from a voltage level of Vy Vm 2 3See Figure 1 Specifications subject to change without notice t SCLK SYNC DIN LDAC LDAC SEE PAGE 11 FOR DESCRIPTION OF INPUT REGISTER Figure 1 Serial Interface Timing Diagram REV 0 3 AD5302 AD5312 AD5322 ABSOLUTE MAXIMUM RATINGS 2 PIN CONFIGURATION Ta 25 C unless otherwise noted Vpp TOPGND Tir rentot am a Bone Cate eran ois 0 3 V to 7 V Digital Input Voltage to GND 0 3 V to Vpp 0 3 V EDAC 1 o 10 GND Reference Input Voltage to GND 0 3 V to Vpp 0 3 V Voo 2 AD5302 9 DIN Vour VourBto GND o on 0 3 V to Vpp 0 3 V vB 5 Apegos 8 SCLK Operating Temperature Range VperA a TOP VIEW SYNC Industrial B Version 40 C to 105 C VourA 5 Not to Scale re VourB Storage Temperature Range 65 C to 150 C Junction Temperature Tj Max
25. nnel to Channel Isolation 80 dB Frequency 10 kHz OUTPUT CHARACTERISTICS Minimum Output Voltage 0 001 V min This is a measure of the minimum and maximum Maximum Output Voltage Vpp 0 001 V max drive capability of the output amplifier DC Output Impedance 0 5 Q Short Circuit Current 50 mA Vpp 5 V 20 mA Vpop 3 V Power Up Time 2 5 us Coming Out of Power Down Mode Vpp 5 V 5 us Coming Out of Power Down Mode Vpp 3 V LOGIC INPUTS Input Current 1 uA Viz Input Low Voltage 0 8 V Vpp 5 V 10 0 6 V Vpp 3 Vt 10 0 5 V Vpp 2 5 V Vm Input High Voltage 2 4 vV Vpp 5 V 10 2 1 V Vpp 3 Vt 10 2 0 V Vpp 2 5 V Pin Capacitance 2 3 5 pF POWER REQUIREMENTS Vpp 2 5 5 5 Vv Ipp Specification Is Valid for All DAC Codes Ipp Normal Mode Both DACs Active and Excluding Load Currents Vpp 4 5 V to 5 5 V 300 450 uA Both DACs in Unbuffered Mode Viy Vpp and Vpp 2 5 V to 3 6 V 230 350 uA Vi GND In Buffered Mode extra current is typically x A per DAC where x 5 uA Vger Rpac Ipp Full Power Down Vpp 4 5 V to 5 5 V 0 2 1 uA Vpp 2 5 V to 3 6 V 0 05 1 uA NOTES 1See Terminology Temperature range B Version 40 C to 105 C 3DC specifications tested with the outputs unloaded Linearity is tested using a reduced code range AD5302 Code 8 to 248 AD5312 Code 28 to 995 AD5322 Code 115 to 3981 gt Guaranteed by design and characterization not production tested In order for the amplifi
26. nput that acts as a frame synchronization signal and chip enable Data can only be trans ferred into the device while SYNC is low To start the serial data transfer SYNC should be taken low observing the mini mum SYNC to SCLK active edge setup time ty After SYNC goes low serial data will be shifted into the device s input shift register on the falling edges of SCLK for 16 clock pulses Any data and clock pulses after the 16th will be ignored and no further serial data transfer will occur until SYNC is taken high and low again SYNC may be taken high after the falling edge of the 16th SCLK pulse observing the minimum SCLK falling edge to SYNC rising edge time t7 After the end of serial data transfer data will automatically be transferred from the input shift register to the input register of the selected DAC If SYNC is taken high before the 16th falling edge of SCLK the data transfer will be aborted and the input registers will not be updated When data has been transferred into both input registers the DAC registers of both DACs may be simultaneously updated by taking LDAC low Low Power Serial Interface To reduce the power consumption of the device even further the interface only powers up fully when the device is being writ ten to As soon as the 16 bit control word has been written to the part the SCLK and DIN input buffers are powered down They only power up again following a falling edge of SYNC Double Buf
27. pplication Circuit The AD5302 AD5312 AD5322 can be used with a wide range of reference voltages especially if the reference inputs are con figured to be unbuffered in which case the devices offer full one quadrant multiplying capability over a reference range of 0 V to Vpp More typically the AD5302 AD5312 AD5322 may be used with a fixed precision reference voltage Figure 36 shows a typical setup for the AD5302 AD5312 AD5322 when using an external reference If the reference inputs are unbuf fered the reference input range is from 0 V to Vpp but if the on chip reference buffers are used the reference range is reduced Suitable references for 5 V operation are the AD780 and REF192 2 5 V references For 2 5 V operation a suitable external reference would be the REF191 a 2 048 V reference Vpp 2 5V TO 5 5V Q AD780 REF192 WITH Vpp 5V OR REF191 WITH Vpp 2 5V SERIAL INTERFACE Figure 36 AD5302 AD5312 AD5322 Using External Reference If an output range of 0 V to Vpp is required when the reference inputs are configured as unbuffered for example 0 V to 5 V the simplest solution is to connect the reference inputs to Vpp As this supply may not be very accurate and may be noisy the AD5302 AD5312 AD5322 may be powered from the reference voltage for example using a 5 V reference such as the REF195 as shown in Figure 37 The REF195 will output a steady supply voltage for the AD5302 AD5312 AD5322 The current require
28. re 33 shows a serial interface between the AD5302 AD5312 AD5322 and the 68HC11 68L11 microcontroller SCK of the 68HC11 68L11 drives the SCLK of the AD5302 AD5312 AD5322 while the MOSI output drives the serial data line of the DAC The SYNC signal is derived from a port line PC7 The setup conditions for correct operation of this interface are as follows the 68HC11 68L11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 1 When data is being transmitted to the DAC the SYNC line is taken low PC7 When the 68HC11 68L11 is configured as above data appear ing on the MOSI output is valid on the falling edge of SCK Serial data from the 68HC11 68L11 is transmitted in 8 bit bytes with only eight falling clock edges occurring in the trans mit cycle Data is transmitted MSB first In order to load data to the AD5302 AD5312 AD5322 PC7 is left low after the first eight bits are transferred and a second serial write operation is performed to the DAC and PC7 is taken high at the end of this procedure AD5302 AD5312 AD5322 SYNC 68HC11 68L11 ADDITIONAL PINS OMITTED FOR CLARITY Figure 33 AD5302 AD5312 AD5322 to 68HC11 68L11 Interface REV 0 AD5302 AD5312 AD5322 AD5302 AD5312 AD5322 to 80C51 80L51 Interface Figure 34 shows a serial interface between the AD5302 AD5312 AD5322 and the 80C51 80L51 microcontroller The setup for the interface is as follows TXD of the 80C51 80L51 drives SCLK of the
29. t data When SYNC goes low it powers on the SCLK and DIN buffers and enables the input shift register Data is transferred in on the falling edges of the following 16 clocks If SYNC is taken high before the 16th falling edge the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device 8 SCLK Serial Clock Input Data is clocked into the input shift register on the falling edge of the serial clock in put Data can be transferred at rates up to 30 MHz The SCLK input buffer is powered down after each write cycle 9 DIN Serial Data Input This device has a 16 bit input shift register Data is clocked into the register on the falling edge of the serial clock input The DIN input buffer is powered down after each write cycle 10 GND Ground reference point for all circuitry on the part TERMINOLOGY GAIN ERROR DRIFT RELATIVE ACCURACY This is a measure of the change in gain error with changes in tem For the DAC relative accuracy or Integral Nonlinearity INL is a measure of the maximum deviation in LSBs from a straight line passing through the actual endpoints of the DAC transfer function A typical INL vs code plot can be seen in Figure 4 DIFFERENTIAL NONLINEARITY Differential Nonlinearity DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes A specified differential nonlinearity of 1 LSB maximum ensures monotonicity This DAC is guaranteed monotonic by
30. the fine adjustment Varying the ratio of R1 and R2 will change the relative effect of the coarse and fine adjustments With the resistor values and exter nal reference shown the output amplifier has unity gain for the DAC A output so the output range is 0 V to 2 5 V 1 LSB For DAC B the amplifier has a gain of 7 6 x 107 giving DAC Ba range equal to 19 mV The circuit is shown with a 2 5 V reference but reference volt ages up to Vpp may be used The op amps indicated will allow a rail to rail output swing Vpp 5V R3 9 51 2kQ AD5302 AD5312 AD5322 AD780 REF192 WITH Vpp 5V Figure 42 Coarse Fine Adjustment Power Supply Bypassing and Grounding In any circuit where accuracy is important careful consideration of the power supply and ground return layout helps to ensure the rated performance The printed circuit board on which the AD5302 AD5312 AD5322 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board If the AD5302 AD5312 AD5322 is in a system where multiple devices require an AGND to DGND connection the connection should be made at one point only The star ground point should be established as close as possible to the AD5302 AD5312 AD5322 The AD5302 AD5312 AD5322 should have ample supply bypassing of 10 UF in paral lel with 0 1 uF on the supply located as close to the package as possible ideally right up against the device
31. to a change in the output of the other DAC It is measured by loading one of the input registers with a full scale code change all Os to all 1s and vice versa while keeping LDAC high Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed The area of the glitch is expressed in nV secs AD5302 AD5312 AD5322 DAC TO DAC CROSSTALK This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of the other DAC This includes both digital and analog crosstalk It is measured by loading one of the DACs with a full scale code change all 0s to all 1s and vice versa while keeping LDAC low and monitoring the output of the other DAC The area of the glitch is expressed in nV secs DC CROSSTALK This is the dc change in the output level of one DAC in re sponse to a change in the output of the other DAC It is mea sured with a full scale output change on one DAC while monitoring the other DAC It is expressed in uV POWER SUPPLY REJECTION RATIO PSRR This indicates how the output of the DAC is affected by changes in the supply voltage PSRR is the ratio of the change in Vout to a change in Vpp for full scale output of the DAC It is measured in dBs Vggr is held at 2 V and Vpp is varied 10 REFERENCE FEEDTHROUGH This is the ratio of the amplitude of the signal at the DAC out put to the reference input when the DAC output is not being update
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