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MICROCHIP PIC16F685/687/689/690 Data Sheet Manual

1. Pan Data Memory rrr Timers Device 1 0 Comparators E SSP ECCP EUSART Flash SRAM EEPROM ch 8 16 bit words bytes bytes PIC16F685 4096 256 256 18 12 2 2 1 No Yes No PIC16F687 2048 128 256 18 12 2 11 Yes No Yes PIC16F689 4096 256 256 18 12 2 1 1 Yes No Yes PIC16F690 4096 256 256 18 12 2 2 1 Yes Yes Yes Pin Diagrams 20 pin PDIP SOIC SSOP VDD eh 1 KE 20 Vss RA5 T1CKI OSC1 CLKIN s 2 19 s RAO ANO C1IN ICSPDAT ULPWU RA4 AN3 T1G OSC2 CLKOUT lt 113 18 RA1 AN1 C12IN VREF ICSPCLK RAS MCLR VPP gt 4 we 17 Ces RA2 AN2 TOCKI INT C1OUT ROS COPT P Ase S 16 RC0 AN4 C2IN RC4 C2OUT P1B 16 IB RC1 AN5 C12IN RC3 AN7 P1C 7 O 14 lt RC2 AN6 P1D RC6 AN8 gt 8 isha RB4 AN10 RC7 AN9 lt 119 12 s RB5 AN11 RB7 a 1110 1171 RB6 VDD 1 sa 20 Vss RA5 T1CKI OSC1 CLKIN lt T 2 19 lt RAO ANO C1IN ICSPDAT ULPWU RA4 AN3 T1G OSC2 CLKOUT 3 3 18 lt RA1 AN1 C12IN VREF ICSPCLK RA3 MCLR VpP gt 4 47 RA2 AN2 TOCKI INT C1OUT RCS CPP1 5 3 16 s RC0 AN4 C2IN RC4 C2OUT 6 e 15 s RC1 AN5 C12IN RC3 AN7 gt 7 O
2. Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR all other Reset Resets Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory not a physical register XXXX XXXX XXXX XXXX 101h TMRO TimerO Module Register XXXX XXXX uuuu uuuu 102h PCL Program Counter s PC Least Significant Byte 0000 0000 0000 0000 103h STATUS IRP RP1 RPO TO PD Z DC e 0001 1xxx 000q quuu 104h FSR Indirect Data Memory Address Pointer XXXX XXXX uuuu uuuu 105h PORTA RA5 RA4 RA3 RA2 RA1 RAO XX xxxx uu uuuu 106h PORTB RB7 RB6 RB5 RB4 XXXX uuuu 107h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RCO XXXX XXXX uuuu uuuu 108h Unimplemented Se 109h Unimplemented SS 10Ah PCLATH Write Buffer for the upper 5 bits of the Program Counter 0 0000 0 0000 10Bh INTCON GIE PEIE TOIE INTE RABIE TOIF INTF RABIF 0000 000x 0000 000x 10Ch EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDATO 0000 0000 0000 0000 10Dh EEADR EEADR7 EEADR6 EEADRS5 EEADR4 EEADR3 EEADR2 EEADR1 EEADRO 0000 0000 0000 0000 10Eh EEDATH Es EEDATHS EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATHO 00 0000 00 0000 10Fh EEADRHS EEADRHS EEADRH2 EEADRH1 EEADRHO
3. FIGURE 1 1 PIC16F685 BLOCK DIAGRAM INT Configuration X N Data Bus 8 PORTA K Program Counter a Flash Le RAO ANO C1IN ICSPDAT ULPWU 4k x 14 Le RA1 AN1 C12IN VREF ICSPCLK gt X RA2 AN2 TOCKI INT C1 OUT Program 8 Level Stack 13 bit RAN de RAS MELRNPP Memory 256 bytes AAs File gt A RA4 AN3 T1G OSG2 CLKOUT Registers a RA5 T1CKI OSC1 CLKIN Program 14 Bus d RAM Addr 9 PORTB Instruction Reg Direct Addr 7 Indirect lt gt RB4 AN10 ra CH Je eX RB5 AN11 S RB6 FSR Re 9 Fo X RB7 2 StatusReg KE 8 Deve eee PORTC LP RCO AN4 C2IN 3 e S2 RC1 AN5 C12IN RER e RC2 AN6 P1D imer instruction d me sein Decode and Ks Oscillator C20UT Control Start up Timer ALU 1X RC5 CCP1 P1A lt gt RC6 AN8 OSC1 CLKI SEH 8 Li ua RC7 AN9 Timin ml OSC2 CLKO Generation K Watchdog W Reg Timer Brown out Reset Internal Oscillator Block MCLR VDD Vss CCP1 PIA TOCKI TIG TICKI S P1B i P1D TimerO Timer1 Timer2 ECCP AN8 AN9 AN10 AN11 it ili i il ed TT 2 Analog To Digital Converter Analog Comparators EEDAT and Reference 8 256 Bytes E E AA seed We Oe Vie a E EEPROM PI b4 b4 b4 b4 x x x d d XR SX VREF ANO AN1 AN2 AN3 AN4 AN5 AN6 AN7 C1IN C1IN C1OUT C2IN C2IN COOUT EEADR 2005 Microchip Technology Inc Preliminary DS41262A
4. Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR all other Reset Resets Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory not a physical XXXX XXXX XXXX XXXX register 18th OPTION_REG RABPU INTEDG TOCS TOSE PSA PS2 PS1 PSO 111 111 1111 1111 182h PCL Program Counter s PC Least Significant Byte 0000 0000 0000 0000 183h STATUS IRP RP1 RPO TO PD 7 DC C 0001 1xxx 000g guuu 184h FSR Indirect Data Memory Address Pointer XXXX XXXX uuuu uuuu 185h TRISA TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 1 111 11 1111 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 1111 187h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISCO 111 111 1111 1111 188h Unimplemented 189h Unimplemented 18Ah PCLATH Write Buffer for the upper 5 bits of the Program Counter 0 0000 0 0000 18Bh INTCON GIE PEIE TOIE INTE RABIE TOIF INTF RABIF 0000 000 0000 000 18Ch EECONT EEPGD WRERR WREN WR RD x x000 0 q000 18Dh EECON2 EEPROM Control Register 2 nota physical register ee 18Eh Unimplemented 18Fh Unimplemented aa 190h Unimplemented 191h Unimplemented 192h Unimplemented
5. Standard Operating Conditions unless otherwise stated BC CHARACTERISTICS Operating mae eg TA lt 85 C for ee b Device Characteristics Min Typt Max Units gees VDD Note D020 Power down Base 0 1 TBD uA 2 0 WDT BOR Comparators VREF and Current Ipp 4 0 4 TBD UA ao MOSC disabled 08 TBD HA 5 0 D021 0 3 TBD HA 2 0 WDT Current 18 TBD HA 3 0 84 TBD HA 5 0 D022 58 TBD LA 3 0 BOR Current 109 TBD uA 5 0 D023 3 3 TBD uA 2 0 Comparator Current 6 1 TBD uA 3 0 11 5 TBD uA 5 0 D024 58 TBD HA 2 0 CVREF Current 85 TBD HA 3 0 138 TBD HA 5 0 D025 4 0 TBD HA 2 0 T10SC Current 46 TBD HA 3 0 60 TBD LA 5 0 D026 1 2 TBD nA 3 0 A D Current 2 2 TBD nA 5 0 D027 TBD TBD HA 3 0 VP6 Current TBD TBD uA 5 0 Legend TBD To Be Determined t Data in Typ column is at 5 0V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all I O pins tri stated pulled to VDD MCLR VDD WDT disabled 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as 1 0 pin loading and switching rate oscillator type internal code execution pattern and temperature also h
6. Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR ali other esets foch PR ADIF RCF TXF SSPIF CCP1IF TMR2IF TMRIIF 000 0000 ong 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X 19h TXREG EUSART Transmit Register 0000 0000 0000 0000 1Ah RCREG EUSART Receive Register 0000 0000 0000 0000 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 1111 8Ch PIE1 ADIE RCIE TXIE SSPIE CCPIE TMR2IE TMR1IE 000 0000 000 0000 98h TXSTA CSRC TX9 TXEN SYNC SENB BRGH TRMT TX9D 0000 0010 0000 0010 99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRGO 0000 0000 0000 0000 9Ah SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 9Bh BAUDCTL ABDOVF RCIDL SCKP BRG16 WUE ABDEN 01 0 0 00 01 0 0 00 Legend x unknown unimplemented locations read as 0 Shaded cells are not used for Asynchronous Reception Note 1 PIC16F687 PIC16F689 PIC16F690 only O 2005 Microchip Technology Inc Preliminary DS41262A page 153 PIC16F685 687 689 690 NOTES mn wwwwwwwwwwww ww w a vwv vx wv www v wwwvvwv wwvww avwvvvwwww v vww wwww ww wwv wawv wwwwwwwwwwvvwvvwwwwvwwwww ww DS41262A page 154 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 13 0 SSP MODULE OVERVIEW FIGURE 13 1 SSP BLOCK DIAGRAM E SPI MODE The Synchronous Serial Port SSP module is a serial int
7. Write to SSPBUF SDO T DXB REX BEEK CID KEE bit 0 Ra E O O Rd E oh a d l SMP 0 SSPIF Interrupt Flag l l A Next Q4 Cycle SSPSR to i after Q24 SSPBUF FIGURE 13 6 SPI MODE WAVEFORM SLAVE MODE WITH CKE 1 Ss Not Optional SCK CKP 0 i CKE 1 SCK annn Write to i SSPBUF l SDO y To CRCC CC SMP o eS CC a bit7 Set ttt t tt SMP 0 lag SE i b i i i i i nterrupt T F P i i i i I i AA 1 Next Q4 Cycle SSPSR to t after 02 SSPBUF DS41262A page 162 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 138 Sleep Operation 13 10 Bus Mode Compatibility In Master mode all module clocks are halted and the Table 13 1 shows the compatibility between the transmission reception will remain in that state until the standard SPI modes and the states of the CKP and device wakes from Sleep After the device returns to CKE control bits normal mode the module will continue to transmit receive data TABLE 13 1 SPI BUS MODES In Slave mode the SPI Transmit Receive Shift register Standard SPI Control Bits State operates asynchronously to the device This allows the E device to be placed in Sleep mode and data to be Mode Terminology CKP CKE shift
8. WDTCON Watchdog Timer Control Ge WPUA Weak Pull up PORTA S S Start e EE Shoot through Cumrent Slave Select Synchronization xi SMP pitianer a NE EE Software Simulator MPLAB GIMi Software Simulator MPLAB SIM30 dE EE Nd ELE 135 Special Event Trigger wa Special Function Registers 16 SPI Mode AAA 155 161 Associated Registers 163 Bus Mode Compatibility 163 Effects of a Reset 163 Enabling SPI I O 159 Master Mode s saaaaeeen 160 Master Slave Connection 159 Serial Clock SCK pin 155 Serial Data In SDI pin 155 Serial Data Out SDO pin 155 EE 155 Slave Select Synchronization eseeeeseeeeerreren 161 Sleep Operation Es SPI Cloaks gege Typical Connection 159 SRGON Register sissi dana aaa Washia niwa maada sise 87 SSP Overview SPI Master Slave Connection s es 159 Ee EEN 164 Slave Mode mu cig atv waa 164 SSP Module Clock Synchronization and the CKP Bit 171 SPI Master Mode 160 SPI Slave Mode SO PBUR sia aden ae Ra ha ae OA Ade aes SEET SSPCON Register wh SSPEN Ke TEE SOPM Pits 3 ec Meet en SSPMSK Register Es SEELEN ER c ic has sh er cae faon SSPSTAT Register s essere Status Register AAA Synchronous Serial Port Enable bit SSPEN A Synchronous Serial Port Mode Select bits S
9. C mbarator Voltage Reference Sbecifications Standard Operating Conditions unless otherwise stated p g p Operating temperature 40 C lt TA lt 125 C Sra Symbol Characteristics Min Typ Max Units Commenis CV01 CVRes Resolution Vpp 24 Vpp 32 LSb CV02 Absolute Accuracy 1 4 LSb Low Range VRR 1 1 2 LSb High Range VRR o CV03 Unit Resistor Value R 2kK Q CV04 R Ladder Settling Time 10 us CV05 VP6 Settling Time TBD TBD TBD Legend TBD To Be Determined These parameters are characterized but not tested Note 1 Settling time measured while VRR 1 and VR lt 3 0 gt transitions from 0000 to 1111 TABLE 17 9 VOLTAGE VR REFERENCE SPECIFICATIONS Bas Standard Operating Conditions unless otherwise stated VR Voltage Reference Specifications Operating temperature 40 C lt TA lt 4125 C Fe Symbol Characteristics Min Typ Max Units Comments VR01 VROUT VR voltage output TBD 0 6 TBD V VR02 TCVOUT Voltage drift temperature 150 TBD ppm C coefficient VRO3 Avrout Voltage drift with respect to 200 uV V AvDD _ VDD regulation VRO4 TSTABLE Settling Time 10 100 us Legend TBD To Be Determined These parameters are characterized but not tested DS41262A page 226 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 FIGURE 17 9 EU
10. I RCREG RCIF f Interrupt Flag OERR bit i f CREN j i a Note This timing diagram shows three words appearing on the RX input The RCREG receive buffer is read after the third word causing the OERR overrun bit to be set TABLE 12 6 REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION i E z i E Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR all other Resets ocn IPR ADF RCF TXF SSPIF CCP1IF TMR2IF TMRIIF 000 0000 000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X 19h TXREG EUSART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG EUSART Receive Data Register 0000 0000 0000 0000 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 1111 8Ch PIE1 ADIE RCIE TXIE SSPIE CCPIE TMR2IE TMR1IE 000 0000 000 0000 98h TXSTA CSRC TX9 TXEN SYNC SENB BRGH TRMT TX9D 0000 0010 0000 0010 99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRGO 0000 0000 0000 0000 9Ah SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 9Bh BAUDCTL ABDOVF RCIDL SCKP BRG16 WUE ABDEN 01 0 0 00 01 0 0 00 Legend x unknown unimplemented locations read as 0 Shaded cells are not used for Asynchronous Reception Note 1 PIC16F687 PIC16F689 PIC16F690 only O 2005 Microchip Technology Inc Preliminary
11. R W 0 R 0 R W 0 RW 0 U 0 RW 0 RW O BW C20N C20UT C2OE C2POL C2R C2CH1 C2CHO bit 7 bit O bit 7 C20N Comparator C2 Enable bit 1 C2 Comparator is enabled 0 C2 Comparator is disabled bit 6 C2OUT Comparator C2 Output bit If C2POL 1 inverted polarity C20UT 1 C2VP lt C2VN C20UT 0 C2VP gt C2VN If C2POL 0 non inverted polarity C20UT 1 C2VP gt C2VN C20UT 0 C2VP lt C2VN bit 5 C20E Comparator C2 Output Enable bit 1 C2OUT is present on RC4 C20UT P1B 0 C20UJT is internal only bit 4 C2POL Comparator C2 Output Polarity Select bit 1 C2OUT logic is inverted 0 C2OUT logic is not inverted bit 3 Unimplemented Read as o bit 2 C2R Comparator C2 Reference Select bits non inverting input 1 C2VP connects to C2VREF o C2VP connects to RCO AN4 C2IN bit 1 0 C2CH lt 1 0 gt Comparator C2 Channel Select bits 00 C2VN of C2 connects to RA1 AN1 C12IN VREF ICSPCLK 01 C2VN of C2 connects to RC1 AN5 C12IN 10 C2VN of C2 connects to RC2 AN6 P1D 11 C2VN of C2 connects to RC3 AN7 P1C Note 1 C2OUT will only drive RC4 C2OUT P1B if C20E 1 C2ON 1 and TRISC lt 4 gt 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 83 PIC16F685 687 689 690 8 1 2 2 Comparator 2 Control R
12. 130 Associated registers wl Capture Compare Timer1 115 Capture Mode ccs scccesssecssscessseesseessseeesnssensseaeens 114 Prescaler 114 CCP1 Pin Configuration 114 Compare Mode a 114 CCP1 Pin CGonfiouration eee 115 Software Interrupt Mode eee eee eee 115 Special Event Trigger and A D Conversions 115 Timert Mode Gelecton 115 Enhanced PWM Mode ssseeeeeseesreerrrnernernn 116 Auto restart ria 128 Auto shutdown ssseessesnneeseenernneenseren nee 127 128 Direction Change in Full Bridge Output Mode 121 Duty ee 117 Effects of RAS ai akawa 129 Example PWM Frequencies and Resolutions 117 Full Bridge Application Example Full Bridge Mode sseseeeeeeeeeene Half Bridge Application Examples 119 Half Bridge Mode 119 Operation in Power Managed Modes 129 Operation with Fail Safe Clock Monitor 129 Output CGonftgurations 116 Output Relationships Active High and Acthve Lowl Output Relationships Diagram POriOd WEE Programmable Dead Band Delay 126 Setup for Operation 129 Shoot through Cumrent 126 Start up Considerations o TMR2 to PR2 Match 77 Specifications ws scien eal eave veh 225 Timer Resources ssssssssssssiesssseressrseriessrrrsrrnrserresennt 113 Enhanced Universal Synchronous Asynchronous Receiver Transmitter EUSART 131 EUSAR
13. 6 7 Timer1 Operation During Sleep Timer can only operate during Sleep when setup in Asynchronous Counter mode In this mode an external crystal or clock source can be used to increment the counter To set up the timer to wake the device e Timert must be on T1CON lt 0 gt e TMRI1IE bit PIE1 lt 0 gt must be set e PEIE bit INTCON lt 6 gt must be set The device will wake up on an overflow If the GIE bit INTCON lt 7 gt is set the device will wake up and jump to the Interrupt Service Routine 0004h on an overflow If the GIE bit is clear execution will continue with the next instruction TABLE 6 1 REGISTERS ASSOCIATED WITH TIMER1 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOA kali othe Resets 0Bh 8Bh INTCON GIE PEIE TOIE INTE RABIE TOIF INTF RABIF 0000 000x 0000 000x 10Bh 18Bh OCh PIR1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 000 0000 000 0000 0Eh TMRIL Holding register for the Least Significant Byte of the 16 bit TMR1 Register XXXX XXXX UUUU uuuu OFh TMR1H Holding register for the Most Significant Byte of the 16 bit TMR1 Register XXXX XXXX UUUU uuuu 10h T1CON TIGINV TMR1GE TICKPS1 TICKPSO TIOSCEN TISYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu 11Bh CM2CON1 MC1OUT MC2OUT T1GSS C2SYNC 00 10 00 10 8Ch PIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMRIIE 000 0000 000 00
14. RCSTA TXREG RCREG ADRESH ADCONO General Purpose Register 96 Bytes Bank 0 PIC16F687 PIC16F689 SPECIAL FUNCTION REGISTERS File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah OBh OCh ODh OEh OFh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 7Fh Indirect addr 1 OPTION_REG PCL STATUS FSR TRISA TRISB TRISC PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE SSPADD SSPSTAT WPUA IOCA WDTCON TXSTA SPBRG SPBRGH BAUDCTL ADRESL ADCON1 General Purpose Register 32 Bytes 48 Bytes PIC16F689 only accesses 70h 7Fh Bank1 File Address 80h 81th 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh AOh BFh COh EFh FOh FFh Indirect addr 1 TMRO PCL STATUS FSR PORTA PORTB PORTC PCLATH INTCON EEDAT EEADR EEDATH EEADRH WPUB IOCB VRCON CM1CONO CM2CONO CM2CON1 ANSEL ANSELH General Purpose Register 80 Bytes PIC16F689 only accesses 70h 7Fh Bank2 oO Unimplemented data memory locations read as 0 Note 1 Not a physical register
15. i i Fetched i Inst PC 1 Inst PC 1 i b Inst 0004h i Inst 0005h Instruction i i i i Inst 0004h i Executed Inst PC 1 Inst PC Dummy Cycle Dummy Cycle 1 Note 1 INTF flag is sampled here every Q1 2 Asynchronous interrupt latency 3 4 Tcy Synchronous latency 3 Tcy where Tcy instruction cycle time Latency is the same whether Inst PC is a single cycle or a 2 cycle instruction CLKOUT is available only in INTOSC and RC Oscillator modes For minimum width of INT pulse refer to AC specifications in Section 17 0 Electrical Specifications INTF is enabled to be set any time during the Q4 Q1 cycles TABLE 14 6 SUMMARY OF INTERRUPT REGISTERS Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR BOR Resets OBh 8Bh INTCON GIE PEIE TOIE INTE RABIE TOIF INTF RABIF 0000 000x 0000 000x 10Bh 18Bh 0Ch PIR1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 000 0000 000 0000 ODh PIR2 OSFIF C2IF C1IF EEIF 0000 0000 8Ch PIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMRIIE 000 0000 000 0000 8Dh PIE2 OSFIE C2IE CIE EEIE 0000 0000 Legend x unknown u unchanged unimplemented read as 0 g value depends upon condition Shaded cells are not used by the interrupt module 2005 Microchip Technology Inc Preliminary DS41262A page 185
16. 1 2 H A det FE Sleep input T1CKPS lt 1 0 gt 1 C20UT 0 T1GSS 2005 Microchip Technology Inc Preliminary DS41262A page 73 PIC16F685 687 689 690 6 1 Timer1 Modes of Operation Timer1 can operate in one of three modes e 16 bit Timer with prescaler 16 bit Synchronous counter e 16 bit Asynchronous counter In Timer mode Timert is incremented on every instruction cycle In Counter mode Timer1 is incremented on the rising edge of the external clock input T1CKI In addition the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously In Counter and Timer modules the counter timer clock can be gated by the Timer1 gate which can be selected as either the T1G pin or Comparator 2 output If an external clock oscillator is needed and the microcontroller is using the INTOSC without CLKOUT Timer1 can use the LP oscillator as a clock source Note In Counter mode a falling edge must be registered by the counter prior to the first incrementing rising edge 6 2 Timer1 Interrupt The Timer1 register pair TMR1H TMR1L increments to FFFFh and rolls over to 0000h When Timer rolls over the Timer1 interrupt flag bit PIR1 lt 0 gt is set To enable the interrupt on rollover you must set these bits Timer1 interrupt enable bit PIE1 lt 0 gt e PEIE bit INTCON lt 6 gt e GIE bit INTCON lt 7 gt The interrupt is cleared by clearing th
17. TON External Switch C a OFF External Switch D Potential 1 T TOFF TON Shoot Through E Peste Ss Current Note 1 All signals are shown as active high 2 TON is the turn on delay of power switch QC and its driver 3 TOFF is the turn off delay of power switch QD and its driver DS41262A page 122 Preliminary O 2005 Microchip Technology Inc PIC16F685 687 689 690 11 3 6 PULSE STEERING MODE The PWM Steering is available only when the CCP1M lt 3 2 gt 11 and P1M lt 1 0 gt 00 CCP1CON register Upon any chip Reset the PSTRCON register is initialized to enable the PWM output to P1A only Once the Single Output mode is selected by CCP1M lt 3 0 gt the user firmware can bring out the same PWM signal to one two three or four output pins by setting the appropriate STR lt D A gt bits as shown in Note The relevant TRIS bits must be set to output 0 to enable the pin output driver in order to see the PWM signal on the pin While the PWM Steering mode is active CCP1M lt 1 0 gt selects the PWM output polarity for the P1 lt D A gt pins See Register 11 1 CCP1CON for details The PWM auto shutdown operation also applies to this Table 11 5 REGISTER 11 2 bit 7 5 bit 4 bit 3 bit 2 bit 1 bit 0 PWM Steering mode as described in the Section 11 3 8 Enhanced PWM Auto shutdown and Section 11 3 11 Effects of a Reset and follows
18. 2005 Microchip Technology Inc PIC16F685 687 689 690 REGISTER 12 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 RCSTA RECEIVE STATUS AND CONTROL REGISTER ADDRESS 18h R W 0 R W 0 R W 0 R W 0 R W 0 R 0 R 0 R x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 SPEN Serial Port Enable bit 1 Serial port enabled 0 Serial port disabled holds module in Reset RX9 9 bit Receive Enable bit 1 Selects 9 bit reception 0 Selects 8 bit reception SREN Single Receive Enable bit Asynchronous mode Don t care Synchronous mode Master 1 Enables single receive o Disables single receive This bit is cleared after reception is complete Synchronous mode Slave Don t care CREN Continuous Receive Enable bit Asynchronous mode 1 Enables receiver o Disables receiver Synchronous mode 1 Enables continuous receive until enable bit CREN is cleared CREN overrides SREN o Disables continuous receive ADDEN Address Detect Enable bit Asynchronous mode 9 bit RX9 1 1 Enables address detection enable interrupt and load the receive buffer when RSR lt 8 gt is set 0 Disables address detection all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8 bit RX9 0 Don t care FERR Framing Error bit 1 Framing error can be updated by reading RCREG register and receive next valid byte
19. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 8 2 TABLE 8 2 C2 OUTPUT STATE VS INPUT CONDITIONS Input Condition C2POL C20UT C2VN gt C2VP 0 0 C2VN lt C2VP 0 1 C2VN gt C2VP 1 1 C2VN lt C2VP 1 0 Note 1 The internal output of the comparator is latched at the end of each instruction cycle External outputs are not latched 2 The C2 interrupt will operate correctly with C2OE set or cleared An external output is not reguired for the C2 interrupt 3 For C2 output on RC4 C2OUT P1B C20E 1 C2ON 1 and TRISC lt 4 gt 0 COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM C2CH lt 1 0 gt RA1 AN1 C12IN VREF ICSPCLK X RC1 AN5 C12IN Xx RC2 AN6 P1D X RC3 AN7 P1C EN C2R RCO AN4 C2IN A 0 MUX C2VREF 1 C2ON 1 Note 1 When C2ON 0 the C2 comparator will produce a o output to the KOR Gate 2 Output shown for reference only See Figure 4 14 for more detail C2POL To D Q Data Bus Q1 ten RD_CM2CONO Set C2IF D Q gt Q3 RD_CM2CONO EN CL Timeri NRESET C20UT To PWM Logic C2SYNC C2OE I 0 I MUX TY SN p RC4 C20UT P1B From TMR1 Clock DS41262A page 82 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 REGISTER 8 2 CM2CONO COMPARATOR 2 CONTROL REGISTER 0 ADDRESS 11AH
20. A simple program to clear RAM location 20h 2Fh using indirect addressing is shown in Example 2 1 EXAMPLE 2 1 INDIRECT ADDRESSING MOVLW 0x20 initialize pointer MOVWF FSR to RAM NEXT CLRF INDF INCF FSR BTFSS FSR 4 GOTO NEXT CONTINUE clear INDF register inc pointer all done no clear next yes continue DS41262A page 32 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 FIGURE 2 7 DIRECT INDIRECT ADDRESSING PIC16F685 687 689 690 Direct Addressing Indirect Addressing RP1 RPO 6 From Opcode 0 IRP 7 File Select Register 0 kl r J e 5 A Bank Select Location Select Bank Select Location Select 00 01 10 11 00h 180h q Data Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail see Figures 2 3 2 4 and 2 5 2005 Microchip Technology Inc Preliminary DS41262A page 33 PIC16F685 687 689 690 NOTES a a a a a a a ee AN DS41262A page 34 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 3 0 CLOCK SOURCES 3 1 The PIC16F685 687 689 690 devices have a wide variety of clock sources and selection features to allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption Figure 3 1 illustrates a block diagram of the PIC16F685 687 689 690 clock sources Clock sources can be config
21. DS41262A page 42 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 8 7 Fail Safe Clock Monitor The Fail Safe Clock Monitor FSCM allows the device to continue operating should the external oscillator fail The FSCM can detect oscillator failure anytime after the Oscillator Start up Timer OST has expired The FSCM is enabled by setting the FCMEN bit in the Configuration Word register CONFIG The FSCM is applicable to all external oscillator modes LP XT HS EC RC and RCIO FIGURE 3 8 FSCM BLOCK DIAGRAM Clock Monitor Latch CM edge triggered Primary Clock LFINTOSC Oscillator 64 31 kHz 488 Hz 32 us 2 ms Clock Failure Detected 3 7 1 FAIL SAFE DETECTION The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock The sample clock is generated by dividing the LFINTOSC by 64 See Figure 3 8 Inside the fail detector block is a latch The external clock sets the latch on each falling edge of the external clock The sample clock clears the latch on each falling edge of the sample clock If a sample clock edge occurs while the latch is cleared a failure has occurred 3 7 2 FAIL SAFE OPERATION When the external clock fails the FSCM switches the device clock to an internal clock source and sets the OSFIF PIR2 lt 75 flag Setting this flag will generate an interrupt if the OSF
22. E E EC a CKP 1 i f e SDO SDI Note Refer to Figure 17 2 for load conditions FIGURE 17 12 SPITM MASTER MODE TIMING CKE 1 SMP 1 35 81 SCK CKP 0 N Ii Wa 72 Aaa 79 e 78 SDO V uso X SS x LSb SDI Note Refer to Figure 17 2 for load conditions DS41262A page 228 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 FIGURE 17 13 SPITM SLAVE MODE TIMING CKE 0 SCK CKP 0 Nili i 78 79 i ca ai de e CKP 1 i A SDO SDI Note Refer to Figure 17 2 for load conditions FIGURE 17 14 SPI SLAVE MODE TIMING CKE 1 s Vi A Note Refer to Figure 17 2 for load conditions 2005 Microchip Technology Inc Preliminary DS41262A page 229 PIC16F685 687 689 690 TABLE 17 12 SPI MODE REQUIREMENTS a Symbol Characteristic Min Typt Max Units Conditions 70 TssL2scH SSJ to SCK or SCKT input Tcy ns TssL2scL 71 ISCH SCK input high time Slave mode Tey 20 ns CNA e SCK input low time Slave mode TC 20 ns 73 TDIV2SCH Setup time of SDI data input to SCK edge 100 ns TDIV2scL 74 TSCH2DIL Hold time of SDI data input to SCK edge 100 ns TscL2DIL 75
23. File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h 170h 17Fh Indirect addr 1 PCL OPTION_REG STATUS FSR TRISA TRISB TRISC PCLATH INTCON EECON1 EECON2 SRCON accesses 70h 7Fh Bank3 2 Address 93h also accesses the SSP Mask SSPMSK register under certain conditions See Registers 13 2 and 13 3 for more details 3 PIC16F689 only DS41262A page 18 Preliminary 2005 Microchip Technology Inc File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h 1FOh 1FFh PIC16F685 687 689 690 FIGURE 2 5 PIC16F690 SPECIAL FUNCTION REGISTERS File File File File Address Address Address Address Indirect addr 1 ooh Indirect addr 1 goh Indirect addr 1 100h Indirect addr
24. The PIC16F685 687 689 690 instruction set is highly orthogonal and is comprised of three basic categories e Byte oriented operations Bit oriented operations Literal and control operations Each PIC16 instruction is a 14 bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction The formats for each of the categories is presented in Figure 15 1 while the various opcode fields are summarized in Table 15 1 Table 15 2 lists the instructions recognized by the MPASM assembler For byte oriented instructions represents a file register designator and d represents a destination designator The file register designator specifies which file register is to be used by the instruction The destination designator specifies where the result of the operation is to be placed If d is zero the result is placed in the W register If d is one the result is placed in the file register specified in the instruction For bit oriented instructions b represents a bit field designator which selects the bit affected by the operation while represents the address of the file in which the bit is located For literal and control operations k represents an 8 bit or 11 bit constant or literal value One instruction cycle consists of four oscillator periods for an oscillator frequency of 4 MHz this gives a
25. for details If the BOR is enabled the maximum rise time specification does not apply The BOR circuitry will keep the device in Reset until VDD reaches VBOR see Section 14 2 4 Brown Out Reset BOR Note The POR circuit does not produce an internal Reset when VDD declines To re enable the POR VDD must reach Vss for a minimum of 100 us When the device starts normal operation exits the Reset condition device operating parameters e voltage frequency temperature etc must be met to ensure operation If these conditions are not met the device must be held in Reset until the operating conditions are met For additional information refer to Application Note AN607 Power up Trouble Shooting DS00607 14 2 2 MCLR PIC16F685 687 689 690 has a noise filter in the MCLR Reset path The filter will detect and ignore small pulses It should be noted that a WDT Reset does not drive MCLR pin low The behavior of the ESD protection on the MCLR pin has been altered from early devices of this family Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event For this reason Microchip recommends that the MCLR pin no longer be tied directly to VDD The use of an RC network as shown in Figure 14 2 is suggested An internal MCLR option is enabled by clearing the MCLRE bit in the Configurati
26. 0000 10Ch EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDATO 0000 0000 0000 0000 10Dh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADRO 0000 0000 0000 0000 18Ch EECON1 EEPGD WRERR WREN WR RD x x000 0 g000 18Dh EECON2 EEPROM Control Register 2 not a physical register ne ane Legend x unknown u unchanged unimplemented read as 0 q value depends upon condition Shaded cells are not used by data EEPROM module Note 1 PIC16F685 PIC16F689 PIC16F690 only DS41262A page 112 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 11 0 ENHANCED CAPTURE COMPARE PWM ECCP MODULE The enhanced Capture Compare PWM ECCP module contains a 16 bit register which can operate as a e 16 bit Capture register e 16 bit Compare register e PWM Master Slave Duty Cycle register Capture Compare PWM Register 1 CCPR1 is comprised of two 8 bit registers CCPR1L low byte and CCPR1H high byte The CCP1CON register controls the operation of ECCP The special event trigger is generated by a compare match and will clear both TMR1H and TMR1L registers TABLE 11 1 ECCP MODE TIMER RESOURCES REQUIRED ECCP Mode Timer Resource Capture Timer1 Compare Timer1 PWM Timer2 REGISTER 11 1 CCP1CON ENHANCED CCP OPERATION REGISTER ADDRESS 17h R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0
27. 1 TMRO PCL STATUS FSR PORTA PORTB PORTC PCLATH INTCON EEDAT EEADR EEDATH EEADRH WPUB IOCB VRCON CM1CONO CM2CONO CM2CON1 ANSEL ANSELH General Purpose Register 80 Bytes accesses 70h 7Fh Bank2 Unimplemented data memory locations read as 0 Not a physical register File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h 16Fh 170h 17Fh Indirect addr 1 OPTION_REG PCL STATUS FSR TRISA TRISB TRISC PCLATH INTCON EECON1 EECON2 PSTRCON SRCON accesses 70h 7Fh Bank3 File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h 1FOh 1FFh 2005 Microchip Technology Inc Preliminary DS41262A page 17 PIC16F685 687 689 690 FIGURE 2 4 Indirect addr 1 TMRO PCL STATUS FSR PORTA PORTB PORTC PCLATH INTCON PIR1 PIR2 TMRIL TMRTH T1CON SSPBUF SSPCON
28. 1 180h TMRO Oth OPTION REG 81h TMRO 101h OPTION REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h PORTA 105h TRISA 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h PORTC 107h TRISC 187h 08h 88h 108h 188h 09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON OBh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 OCh PIE1 8Ch EEDAT 10Ch EECON1 18Ch PIR2 ODh PIE2 8Dh EEADR 10Dh EECON2 18Dh TMRIL 0Eh PCON 8Eh EEDATH 10Eh 18Eh TMR1H OFh OSCCON 8Fh EEADRH 10Fh 18Fh T1CON 10h OSCTUNE 90h 110h 190h TMR2 11h 91h 111h 191h T2CON 12h PR2 92h 112h 192h SSPBUF 13h SSPADD 93h 113h 193h SSPCON 14h SSPSTAT 94h 114h 194h CCPRIL 15h WPUA 95h WPUB 115h 195h CCPR1H 16h IOCA 96h IOCB 116h 196h CCP1CON 17h WDTCON 97h 117h 197h RCSTA 18h TXSTA 98h VRCON 118h 198h TXREG 19h SPBRG 99h CM1CONO 119h 199h RCREG 1Ah SPBRGH 9Ah CM2CONO 11Ah 19Ah 1Bh BAUDCTL 9Bh CM2CON1 11Bh 19Bh PWM1CON 1Ch 9Ch 11Ch 19Ch ECCPAS 1Dh 9Dh 11Dh PSTRCON 19Dh ADRESH 1Eh ADRESL 9Eh ANSEL 11Eh SRCON 19Eh ADCONO 1Fh ADCON1 9Fh ANSELH 11Fh 19Fh 20h AOh 120h 1A0h General General General Purpose Purpose Purpose Register Register Register 80 Bytes 80 Bytes 96 Bytes EFh 16Fh accesses FOh accesses 170h accesses 1FOh 7Fh 70h 7Fh FFh 70h 7Fh 17Fh 70h 7Fh 1FFh Bank O Banki Bank2 Bank3 EI Unimplemented data memory locations read as o Note 1 Not a physica
29. 1 Analog input Pin is assigned as analog input 0 Digital I O Pin is assigned to port or special function Note 1 Setting a pin to an analog input automatically disables the digital input circuitry weak pull ups and interrupt on change if available The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown TABLE 9 2 ANALOG SELECT CROSS REFERENCE UO Pins Analog RB5 RB4 RC7 RC6 RC3 RC2 RC1 RCO RA4 RA2 RA1 RAO Select ANS11 ANS10 ANS9 ANS8 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANSO Channel AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 ANO DS41262A page 96 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 REGISTER 9 3 ADCONO A D CONTROL REGISTER ADDRESS 1Fh R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 ADFM VCFG CHS3 CHS2 CHS1 CHSO GO DONE ADON bit 7 bit O bit 7 ADFM A D Result Formed Select bit 1 Right justified 0 Left justified bit 6 VCFG Voltage Reference bit 1 VREF pin 0 VDD bit 5 2 CHS lt 3 0 gt Analog Channel Select bits 0000 Channel 00 ANO 0001 Channel 01 AN1 0010 Channel 02 AN2 0011 Channel 03 AN3 0100 Channel 04 AN4 0101 Channel 05 AN5 011
30. 193h Unimplemented 194h Unimplemented 195h Unimplemented 196h Unimplemented 197h Unimplemented 198h Unimplemented 199h Unimplemented 19Ah Unimplemented 19Bh Unimplemented 19Ch Unimplemented 19Dh PSTRCON STRSYNC STRD STRC STRB STRA o 0001 o 0001 19Eh SRCON SR1 SRO C1SEN C2REN PULSS PULSR 0000 00 0000 00 19Fh Unimplemented Legend Unimplemented locations read as 0 u unchanged x unknown q value depends on condition shaded unimplemented Note 1 Other non Power up Resets include MCLR Reset and Watchdog Timer Reset during normal operation 2 MCLR and WDT Reset does not affect the previous value data latch The RABIF bit will be cleared upon Reset but will set again if the mismatched exists 3 PIC16F685 PIC16F690 only 2005 Microchip Technology Inc Preliminary DS41262A page 23 PIC16F685 687 689 690 2 2 2 1 Status Register The Status register shown in Register 2 1 contains the arithmetic status of the ALU the Reset status the bank select bits for data memory GPR and SFR The Status register can be the destination for any instruction like any other register If the Status register is the destination for an instruction that affects the Z writable Therefore the result of an instruction with the Status register as destination may be
31. 205 Program Memory a Map and Stacks icc iii 15 Programming Device Instructions 00 0 0 eee eects 193 PSTRCON Register Pulse Stering AAA PWM ECCP Module Pulse Stern Gees Setzeeg geesde edd GEN 123 PWM Steering Operation Table sseseesseseeeeeen 124 Steering Synchronization eseeseeeereeeeesreeresrese 125 PWM Mode See Enhanced Capture Compare PWM 116 PWM Steringa anana iniedi ano 124 PWM1CON Hegister A 126 R RIN BIE ESA EAR 156 RGRE EE 144 RCSTA Register cccecsscessessesescesssesesessseesenesseneeesees 133 SPEN Bit E Reader Response is ceseerereraaereanos 254 Read Write Modify Operations seeeseeserereerrerreereeee 193 Receive Overflow Indicator bit SSPOV 157 Register RCREG Register saisine raidai ias 139 Registers ADCONO A D Control 0 97 ADCON1 A D Control 1 98 ANSEL Analog Select 96 ANSELH Analog Select High 96 BAUDCTL Baud Rate Control 134 CCP1CON Enhanced CCP Operation CCPRIH CCPR td Ace et CM1CONO C1 Control CM2CONO C2 Control CM2CON1 C2 Control CONFIG Configuration Word 174 ECCPAS Enhanced CCP Auto shutdown Control 127 EEADR EEPROM Address 106 EEADRH EEPROM Address 106 EECON1 EEPROM Control 1 lt w swmmmmaaa 107 EEDAT EEPROM Data can EEDATH EEPROM Datai INTCON Interrupt Contro
32. CONFIG CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSCO Legend Shaded cells are not used by the Watchdog Timer Note 1 See Register 14 1 for operation of all Configuration Word register bits DS41262A page 188 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 146 Power Down Mode Sleep The Power down mode is entered by executing a SLEEP instruction If the Watchdog Timer is enabled e WDT will be cleared but keeps running e PD bit in the Status register is cleared e TO bit is set Oscillator driver is turned off I O ports maintain the status they had before SLEEP was executed driving high low or high impedance For lowest current consumption in this mode all I O pins should be either at VDD or Vss with no external circuitry drawing current from the I O pin and the comparators and CVREF should be disabled I O pins that are high impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs The TOCKI input should also be at VDD or Vss for lowest current consumption The contribution from on chip pull ups on PORTA should be considered The MCLR pin must be at a logic high level Note It should be noted that a Reset generated by a WDT time out does not drive MCLR pin low 14 6 1 WAKE UP FROM SLEEP The device can wake up from Sleep through one of the following events 1 External Reset input on MCLR p
33. PIC16F685 687 689 690 14 2 5 TIME OUT SEQUENCE On power up the time out sequence is as follows first PWRT time out is invoked after POR has expired then OST is activated after the PWRT time out has expired The total time out will vary based on oscillator configuration and PWRTE bit status For example in EC mode with PWRTE bit erased PWRT disabled there will be no time out at all Figures 14 3 14 4 and 14 5 depict time out sequences The device can execute code from the INTOSC while OST is active by enabling Two Speed Start up or Fail Safe Monitor see Section 3 6 2 Two Speed Start up Sequence and Section 3 7 Fail Safe Clock Monitor Since the time outs occur from the POR pulse if MCLR is kept low long enough the time outs will expire Then bringing MCLR high will begin execution immediately see Figure 14 4 This is useful for testing purposes or to synchronize more than one PIC16F685 687 689 690 device operating in parallel Table 14 5 shows the Reset conditions for some 14 2 6 POWER CONTROL PCON REGISTER The Power Control register PCON address 8Eh has two Status bits to indicate what type of Reset that last occurred Bit 0 is BOR Brown out Reset BOR is unknown on Power on Reset It must then be set by the user and checked on subsequent Resets to see if BOR 0 indicating that a Brown out has occurred The BOR Status bit is a don t care and is not necessarily predictable
34. PIC16F685 687 689 690 8 1 2 COMPARATOR 2 CONTROL REGISTERS The Comparator 2 C2 register CM2CONO is a functional copy of the CM1CONO register described in Section 8 1 1 Comparator C1 Control Register A second control register CM2CON1 is also present for control of an additional synchronizing feature as well as mirrors of both comparator outputs 8 1 2 1 Comparator 2 Control Register 0 The CM2CONO register shown in Register 8 2 contains the control and Status bits for Comparator C2 Setting C2ON CM2CONO lt 7 gt enables Comparator C2 for operation Bits C2CH lt 1 0 gt CM2CONO lt 1 0 gt select the compar ator input from the four analog pins AN lt 7 5 1 gt Note 1 To use AN lt 7 5 1 gt as analog inputs the appropriate bits must be programmed to 1 in the ANSEL register C2R CM2CONO lt 2 gt selects the reference to be used with the comparator Setting C2R CM2CONO lt 2 gt selects the C2VREF output of the comparator voltage reference module as the reference voltage for the comparator Clearing C2R selects the C2IN input on the RCO AN4 C2IN pin The output of the comparator is available internally via the C2OUT bit CM2CONO lt 6 gt To make the output available for an external connection the C20E bit CM2CONO lt 5 gt must be set FIGURE 8 2 The comparator output C2OUT can be inverted by setting the C2POL bit CM2CONO lt 4 gt Clearing C2POL results in a non inverted output
35. SPBRG Actual SPBRG Rate Error value Rate Error value Rate Err value K decimal K decimal K decimal 0 3 0 300 0 04 832 300 0 16 415 300 0 16 207 1 2 1 202 0 16 207 1201 0 16 103 1201 0 16 51 2 4 2 404 0 16 103 2403 0 16 51 2403 0 16 25 9 6 9 615 0 16 25 9615 0 16 12 19 2 19 231 0 16 12 57 6 62 500 8 51 3 115 2 125 000 8 51 1 SYNC 0 BRGH 1 BRG16 1 or SYNC 1 BRG16 1 Zoe Fosc 20 000 MHz Fosc 10 000 MHz Fosc 8 000 MHz K Actual SPBRG Actual ai SPBRG Actual 3 SPBRG Fo Error Sheain b i Error ean pe Error Ge 0 3 0 300 0 00 16665 0 300 0 00 8332 300 0 01 6665 1 2 1 200 0 02 4165 1 200 0 02 2082 1200 0 04 1665 2 4 2 400 0 02 2082 2 402 0 06 1040 2400 0 04 832 9 6 9 596 0 03 520 9 615 0 16 259 9615 0 16 207 19 2 19 231 0 16 259 19 231 0 16 129 19230 0 16 103 57 6 57 471 0 22 86 58 140 0 94 42 57142 0 79 34 115 2 116279 0 94 42 113 636 1 36 21 117647 2 12 16 SYNC 0 BRGH 1 BRG16 1 or SYNC 1 BRG16 1 his Fosc 4 000 MHz Fosc 2 000 MHz Fosc 1 000 MHz K Actual SPBRG Actual SPBRG Actual SPBRG Rate Error value Rate Error value Rate Error value K decimal K decimal K decimal 0 3 0 300 0 01 3332 300 0 04 1665 300 0 04 832 1 2 1 200 0 04 832 1201 0 16 415 1201 0 16 207 2 4 2 404 0 16 415 2403 0 16 207 2403 0 16 103 9 6 9 615 0 16 103 9615 0 16 51 9615 0 16 25 19 2 19 231 0 16 51 19230 0 16 25 19230 0 16 12 57 6 58 824 2 12 16 55555 3 55 8 115 2
36. TABLE 1 3 PINOUT DESCRIPTION PIC16F690 Name Function o Es ea Description RAO ANO C1IN ICSPDAT RAO TIL General purpose UO Individually controlled interrupt on ULPWU change Individually enabled pull up ANO AN A D Channel 0 input C1IN AN Comparator 1 positive input ICSPDAT TTL CMOS ICSP Data I O ULPWU AN Ultra Low Power Wake up input RA1 AN1 C12IN VREF ICSPCLK HAT TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up AN1 AN A D Channel 1 input C12IN AN Comparator 1 or 2 negative input VREF AN External Voltage Reference for A D ICSPCLK ST ICSPTM clock RA2 AN2 TOCKI INT C1OUT RA2 ST CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up AN2 AN A D Channel 2 input TOCKI ST Timer0 clock input INT ST External Interrupt C10OUT CMOS Comparator 1 output RA3 MCLR VPP RA3 TTL General purpose input Individually controlled interrupt on change MCLR ST Master Clear with internal pull up VPP HV Ge Programming voltage RA4 AN3 T1G OSC2 CLKOUT RA4 TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up AN3 AN A D Channel 3 input TIG ST Timer1 gate input OSC2 XTAL Crystal Resonator CLKOUT
37. The auto shutdown feature can be configured to allow auto restarts of the module following a shutdown event This is enabled by setting the PRSEN bit of the PWM1CON register PWM1CON lt 7 gt In Shutdown mode with PRSEN 1 Figure 11 14 the ECCPASE bit will remain set for as long as the cause of the shutdown continues When the shutdown condition clears the ECCPASE bit is cleared If PRSEN 0 Figure 11 15 once a shutdown condition occurs the ECCPASE bit will remain set until it is cleared by firmware Once ECCPASE is cleared the enhanced PWM will resume at the beginning of the next PWM period Auto shutdown and Auto restart Note Writing to the ECCPASE bit is disabled while a shutdown condition is active Independent of the PRSEN bit setting whether the auto shutdown source is one of the comparators or INT the shutdown condition is a level The ECCPASE bit cannot be cleared as long as the cause of the shutdown persists The Auto shutdown mode can be forced by writing a 1 to the ECCPASE bit FIGURE 11 14 11 3 9 START UP CONSIDERATIONS When the ECCP module is used in the PWM mode the application hardware must use the proper external pull up and or pull down resistors on the PWM output pins When the microcontroller is released from Reset all of the I O pins are in the high impedance state The external circuits must keep the power switch devices in the OFF state until the microcontroller drives
38. and BRG16 bits as required to achieve the desired baud rate 4 2 Enable the asynchronous serial port by clearing 5 bit SYNC and setting bit SPEN 6 3 If interrupts are desired set enable bit RCIE 7 4 If 9 bit reception is desired set bit RX9 5 Enable the reception by setting bit CREN 6 Flag bit RCIF will be set when reception is 8 complete and an interrupt will be generated if enable bit RCIE was set 7 Read the RCSTA register to get the 9th bit if 9 enabled and determine if any error occurred during reception 10 8 Read the 8 bit received data by reading the 11 RCREG register 9 If any error occurred clear the error by clearing enable bit CREN 10 If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON lt 7 6 gt are set FIGURE 12 5 EUSART RECEIVE BLOCK DIAGRAM 12 3 3 SETTING UP 9 BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS 485 systems To set up an Asynchronous Reception with Address Detect Enable 1 Initialize the SPBRGH SPBRG registers for the appropriate baud rate Set or clear the BRGH and BRG16 bits as required to achieve the desired baud rate Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit If interrupts are required set the RCEN bit and select the desired priority level with the RCIP bit Set the RX9 bit to enable 9 bit reception Set the ADDEN bit to enable address detect Enable receptio
39. 0000 0000 110h Unimplemented 11th Unimplemented Se 112h Unimplemented pre 113h Unimplemented 114h Unimplemented 115h WPUB WPUB7 WPUB6 WPUB5 WPUB4 1111 1111 116h IOCB IOCB7 IOCB6 IOCB5 IOCB4 0000 0000 117h Unimplemented 118h VRCON C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VRO 0000 0000 0000 0000 119h CM1CONO C1ON C10UT C1OE C1POL C1R C1CH1 C1CHO 0000 000 0000 000 11Ah CM2CONO C2ON C20UT C2OE C2POL C2R C2CH1 C2CHO 0000 000 0000 000 11Bh CM2CON1 MC10UT MC20UT T1GSS C2SYNC 00 10 00 10 11Ch Unimplemented 11Dh Unimplemented San 11Eh ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANSO 1111 1111 1111 1111 11Fh ANSELH ANS11 ANS10 ANS9 ANS8 1111 1111 Legend Unimplemented locations read as 0 u unchanged x unknown a value depends on condition shaded unimplemented Note 1 Other non Power up Resets include MCLR Reset and Watchdog Timer Reset during normal operation 2 MCLR and WDT Reset does not affect the previous value data latch The RABIF bit will be cleared upon Reset but will set again if the mismatched exists 3 PIC16F685 PIC16F689 PIC16F690 only DS41262A page 22 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 TABLE 2 4 PIC16F685 687 689 690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
40. 1110 IC Slave mode 7 bit address with Start and Stop bit interrupts enabled 1111 IC Slave mode 10 bit address with Start and Stop bit interrupts enabled Note 1 PIC16F687 PIC16F689 PIC16F690 only 2 When this mode is selected any reads or writes to the SSPADD SFR address actually accesses the SSPMSK register Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 157 PIC16F685 687 689 690 13 2 Operation When initializing the SPI several options need to be specified This is done by programming the appropriate control bits SSPCON lt 5 0 gt and SSPSTAT lt 7 6 gt These control bits allow the following to be specified Master mode SCK is the clock output Slave mode SCK is the clock input Clock Polarity Idle state of SCK Data Input Sample Phase middle or end of data output time Clock Edge output data on rising falling edge of SCK e Clock Rate Master mode only Slave Select mode Slave mode only The SSP consists of a transmit receive shift register SSPSR and a buffer register SSPBUF The SSPSR shifts the data in and out of the device MSb first The SSPBUF holds the data that was written to the SSPSR until the received data is ready Once the eight bits of data have been received that byte is moved to th
41. 1Eh ADRESH A D Result Register High Byte XXXX XXXX uuuu uuuu 1Fh ADCONO ADFM VCFG CHS3 CHS2 CHS1 CHSO GO DONE ADON 0000 0000 0000 0000 Legend Unimplemented locations read as 0 u unchanged x unknown q value depends on condition shaded unimplemented Note 1 Other non Power up Resets include MCLR Reset and Watchdog Timer Reset during normal operation 2 MCLR and WDT Reset do not affect the previous value data latch The RABIF bit will be cleared upon Reset but will set again if the mismatched exists 3 PIC16F687 PIC16F689 PIC16F690 only 4 PIC16F685 PIC16F690 only 5 When SSPCON bits SSPM lt 3 0 gt 1001 any reads or writes to the SSPADD SFR address are accessed through the SSPMSK register See Registers 13 2 and 13 3 for more detail DS41262A page 20 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 TABLE 2 2 PIC16F685 687 689 690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR all other Reset Resets Bank 1 80h INDF een this location uses contents of FSR to address data memory not a physical XXXX XXXX XXXX XXXX register 81h OPTION REG RABPU INT
42. 2 4 N 256 Abr TT1H T1CKI High Synchronous No Prescaler 0 5 TCY 20 ns Time Synchronous 15 D ns with Prescaler Asynchronous 30 ns 465 TTIL T1CKI Low Time Synchronous No Prescaler 0 5 TCY 20 ns Synchronous 15 ns with Prescaler Asynchronous 30 ns 47 TTIP T1CKI Input Synchronous Greater of ns N prescale Period 30 or Icy 40 value 1 2 4 N 8 Asynchronous 60 ns FT1 Timer1 oscillator input freguency range DC 200 kHz oscillator enabled by setting bit T1OSCEN 48 TCKEZTMR1 Delay from external clock edge to timer increment 2 Tosc 7Tosc These parameters are characterized but not tested tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not DS41262A page 224 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 FIGURE 17 8 CAPTURE COMPARE PWM TIMINGS ECCP CCP1 Capture mode NEE I ba 52 CCP1 Compare or PWM mode WA 53 e i gt j 54 Note Refer to Figure 17 2 for load conditions TABLE 17 6 CAPTURE COMPARE PWM REQUIREMENTS ECCP Standard Operating Conditions unless otherwise stated Operating Temperature 40 C lt TA lt 125 C Fan Symbol Characteristic Min Typt Max Units Conditions 50 TccL CCP1 Input Low
43. 2005 Microchip Technology Inc Preliminary DS41262A page 187 PIC16F685 687 689 690 REGISTER 14 2 R W 0 WDTCON WATCHDOG TIMER CONTROL REGISTER ADDRESS 97h R W 0 R W 0 U 0 U 0 U 0 R W 0 R W 1 WDTPS3 WDTPS2 WDTPS1 bit 7 bit 7 5 Unimplemented Read as oi bit 4 1 WDTPS lt 3 0 gt Watchdog Timer Period Select bits Bit Value Prescale Rate 0000 1 32 0001 1 64 0010 1 128 0011 1 256 0100 1 512 Reset value 0101 1 1024 0110 1 2048 0111 1 4096 1000 1 8192 1001 1 16384 1010 1 32768 1011 1 65536 1100 reserved 1101 reserved 1110 reserved 1111 reserved bit O SWDTEN Software Enable or Disable the Watchdog Timer 1 WDT is turned on 0 WDT is turned off Reset value WDTPSO SWDTEN D bit 0 Note 1 If WDTE configuration bit 1 then WDT is always enabled irrespective of this control bit If WDTE configuration bit 0 then it is possible to turn WDT on off with this control bit Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown TABLE 14 8 SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O 97h WDTCON WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN 81h 181h OPTION_REG RABPU INTEDG TOCS TOSE PSA PS2 PS1 PSO 2007h
44. 5 6 ms D123 TRETD Characteristic Retention 40 Year Provided no other specifications are violated D124 TREF Number of Total Erase Write 1M 10M Sg EM 40 C lt TA lt 85 C Cycles before Refresh 4 Program Flash Memory D130 EP Cell Endurance 10K 100K E W 40 C lt TA lt 85 C D130A ED Cell Endurance 1K 10K E W 85 C lt TA lt 125 C D131 VPR VDD for Read VMIN 5 5 V VMIN Minimum operating voltage D132 VPEW VDD for Erase Write 4 5 a 5 5 V D133 TPEw Erase Write cycle time 2 2 5 ms D134 TRETD Characteristic Retention 40 Year Provided no other specifications are violated Note 1 These parameters are characterized but not tested Data in Typ column is at 5 0V 25 C unless otherwise stated These parameters are for design guidance only and are not tested In RC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended to use an external clock in RC mode Negative current is defined as current sourced by the pin The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages See Section 10 0 Data EEPROM and Flash Program Memory Control for additional information 2005 Microchip Technology Inc Preliminary DS41262A page 217 PIC16F685 687 689 6
45. High speed crystal resonator on RA4 AN3 T1G OSC2 CLKOUT and RA5 T1CKI OSC1 CLKIN 001 XT oscillator Crystal resonator on RA4 AN3 T1G OSC2 CLKOUT and RA5 T1CKI OSC1 CLKIN 000 LP oscillator Low power crystal on RA4 AN3 T1G OSC2 CLKOUT and RA5 T1CKI OSC1 CLKIN Note 1 Enabling Brown out Reset does not automatically enable Power up Timer 2 The entire data EEPROM will be erased when the code protect is turned off 3 The entire program memory will be erased when non code protect is turned off 4 When MCLR is asserted in INTOSC or RC mode the internal clock oscillator is disabled Legend R Readable W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown DS41262A page 174 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 142 Reset The PIC16F685 687 689 690 differentiates between various kinds of Reset a Power on Reset POR b WDT Reset during normal operation WDT Reset during Sleep d MCLR Reset during normal operation MCLR Reset during Sleep f Brown out Reset BOR Some registers are not affected in any Reset condition their status is unknown on POR and unchanged in any other Reset Most other registers are reset to a Reset state on e Power on Reset MCLR Reset e MCLR Reset during Sleep e WDT Reset Brown out Reset BOR They are not affected by a WDT wake up since this is viewed
46. Note 1 ANSEL determines Analog Input mode Available on PIC16F685 PIC16F690 only Note 1 ANSEL determines Analog Input mode 2005 Microchip Technology Inc Preliminary DS41262A page 67 PIC16F685 687 689 690 TABLE 4 3 SUMMARY OF REGISTERS ASSOCIATED WITH PORTC A i s g Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR all other Resets 07h 107h PORTO RC7 RC6 RC5 RC4 RC3 RC2 RC1 RCO xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO 0000 0000 0000 0000 17h CCP1CON P1M1 P1M0 DC1B1 DC1BO CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 1Dh ECCPAS ECCPASE ECCPAS2 ECCPASd ECCPASO PSSAC1 PSSACO PSSBD1 PSSBDO 0000 0000 0000 0000 87h 187h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISCO 1111 1111 1111 1111 11Ah CM2CONO C20N C20UT C2OE C2POL C2R C2CH1 C2CHO 0000 ooo 0000 000 11Bh CM2CON1 MC1OUT MC20UT T1GSS C2SYNC 00 10 00 10 11Eh ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANSO 1111 1111 1111 1111 11Fh ANSELH ANS11 ANS10 ANS9 ANS8 1111 1111 19Dh PSTRCON STRSYNC STRD STRC STRB STRA 0 0001 0 0001 19Eh SRCON SR1 SRO C1SEN C2REN PULSS PULSR 0000 00 0000 00 118h VRCON C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VRO 0000 0000 0000 0000 Le
47. Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown DS41262A page 106 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 REGISTER 10 5 bit 7 bit 6 4 bit 3 bit 2 bit 1 bit 0 EECON1 EEPROM CONTROL REGISTER 1 ADDRESS 18Ch R W x U 0 U 0 U 0 R W x R W 0 R S 0 R S 0 EEPGD WRERR WREN WR RD bit 7 bit 0 EEPGD Program Data EEPROM Select bit 1 Accesses program memory 0 Accesses data memory Unimplemented Read as 0 WRERR EEPROM Error Flag bit 1 A write operation is prematurely terminated any MCLR Reset any WDT Reset during normal operation or BOR o The write operation completed WREN EEPROM Write Enable bit 1 Allows write cycles 0 Inhibits write to the data EEPROM WR Write Control bit EEPGD 1 This bit is ignored EEPGD 0 1 Initiates a write cycle The bit is cleared by hardware once write is complete The WR bit can only be set not cleared in software o Write cycle to the data EEPROM is complete RD Read Control bit 1 Initiates a memory read the RD is cleared in hardware and can only be set not cleared in software 0 Does not initiate a memory read Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is clear
48. SLEEP instruction to be executed TABLE 17 17 PIC16F685 687 689 690 A D CONVERSION REGUIREMENTS SLEEP MODE Standard Operating Conditions unless otherwise stated Operating Temperature 40 C lt TA lt 125 C a Sym Characteristic Min Typt Max Units Conditions 130 TAD A D Internal RC ADCS lt 1 0 gt 11 RC mode Oscillator Period 3 0 6 0 9 0 us Ar VDD 2 5V 2 0 4 0 6 0 us At VDD BON 131 Tenv Conversion Time 11 TAD not including Acquisition Time 1 132 Taca Acquisition Time 0 11 5 us 5 us The minimum time is the amplifier settling time This may be used if the new input voltage has not changed by more than 1 LSb i e 4 1 mV 4 096V from the last sampled voltage as stored on CHOLD 134 Teo Q4 to A D Clock Tosc 2 Tcy lf the A D clock source is selected Start as RC a time of Tcy is added before the A D clock starts This allows the SLEEP instruction to be executed These parameters are characterized but not tested t Data in Typ column is at 5 0V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 ADRES register may be read on the following Tcy cycle 2 See Table 9 1 for minimum conditions 2005 Microchip Technology Inc Preliminary DS41262A page 235 PIC16F685 687 689 690 NOTES Kee REAR ERES ERRAR SAR GE EE EEE ES DS41262A page 2
49. TCY 4 16 64 2 If the SPI is used in Slave mode with CKE 1 then the SS pin control must be enabled 3 When the SPI is in Slave mode with SS pin control enabled SSPCON lt 3 0 gt 0100 the state of the SS pin can affect the state read back from the TRISC lt 4 gt bit The peripheral OE signal from the SSP module into PORTC controls the state that is read back from the TRISC lt 4 gt bit see Section 17 0 Electrical Specifications for information on PORTC If read write modify instructions such as BSF are performed on the TRISC register while the SS pin is high this will cause the TRISC lt 7 gt bit to be set thus disabling the SDO output 2005 Microchip Technology Inc Preliminary DS41262A page 155 PIC16F685 687 689 690 REGISTER 13 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SSPSTAT SYNC SERIAL PORT STATUS REGISTER ADDRESS 94h R W 0 R W 0 R 0 R 0 R 0 R 0 R 0 R 0 SMP CKE D A P S RAN UA BF bit 7 bit O SMP SPI Data Input Sample Phase bit SPI Master mode 1 Input data sampled at end of data output time 0 Input data sampled at middle of data output time Microwire SPI Slave mode SMP must be cleared when SPI is used in Slave mode I2CTM mode This bit must be maintained clear CKE SPI Clock Edge Select bit SPI mode CKP 0 1 Data transmitted on rising edge of SCK Microwi
50. The Break character transmit consists of a Start bit followed by 12 o bits and a Stop bit The frame Break character is sent whenever the SENB and TXEN bits TXSTA lt 3 gt and TXSTA lt 5 gt are set while the Transmit Shift register is loaded with data Note that the value of data written to TXREG will be ignored and all o s will be transmitted The SENB bit is automatically reset by hardware after the corresponding Stop bit is sent This allows the user to preload the transmit FIFO with the next transmit byte following the Break character typically the Sync character in the LIN specification Note that the data value written to the TXREG for the Break character is ignored The write simply serves the purpose of initiating the proper sequence The TRMT bit indicates when the transmit operation is active or IDLE just as it does during normal transmission See Figure 12 9 for the timing of the Break character sequence 12 3 5 1 The following sequence will send a message frame header made up of a Break followed by an auto baud Sync byte This sequence is typical of a LIN bus master 1 Configure the EUSART for the desired mode 2 Set the TXEN and SENB bits to setup the Break character 3 Load the TXREG with a dummy character to initiate transmission the value is ignored 4 Write 55h to TXREG to load the Sync character into the transmit FIFO buffer 5 After the Break has been sent the SENB bit is
51. Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown DS41262A page 98 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 9 1 7 CONFIGURING THE A D EXAMPLE 9 1 A D CONVERSION After the A D module has been configured as desired Thig code block configures the A D the selected channel must be acguired before the ifor polling Vdd reference R C clock conversion is started The analog input channels must jand RAD input have their corresponding TRIS bits selected as inputs Conversion start amp wait for complete To determine sample time see Tables 17 16 and 17 17 polling code included After this sample time has elapsed the A D conversion can be started BSF STATUS RPO Bank 1 SCHER BCF STATUS RP1 These steps should be followed for an A D conversion SE BRO Oda Fearais 1 Configure the A D module MOVWF ADCON1 Configure analog digital UO ANSx BSF TRISA 0 EE to input i g BCF STATUS RPO Bank 2 Select A D conversion clock ADCON1 lt 6 4 gt on STATUS RP1 e Configure voltage reference ADCONO lt 6 gt BSF ANSEL 0 Set RAO to analog Select A D input channel ADCONO lt 5 2 gt BCF STATUS RPO iBank 0 MOVLW B 10000001 Right Vdd Vref ANO Select result format ADCONO lt 7 gt EEN Turn on A D module ADCONO lt 0 gt CALL SampleTime Wait min sample time 2 Configure A D interrupt if desired BSF ADCONO GO Start conversion
52. _ Desired Baud Rate E 64 16000000 9600 1 64 25 042 25 16000000 Calculated Baud Rate ZS T 9615 Calc Baud Rate Desired Baud Rate Desired Baud Rate Error _ 9615 9600 gt o 9600 EE SPBRGH SPBRG values lt 4 are invalid TABLE 12 1 BAUD RATE FORMULAS Configuration Bits BRG EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8 bit Asynchronous Fosc 64 n 1 0 0 1 8 bit Asynchronous Fosc 16 n 1 0 1 0 16 bit Asynchronous 0 1 1 16 bit Asynchronous Fosc 4 n 1 T 0 x 8 bit Synchronous Master 1 1 x 16 bit Synchronous Master Legend x Don t care n value of SPBRGH SPBRG register pair 2005 Microchip Technology Inc Preliminary DS41262A page 135 PIC16F685 687 689 690 TABLE 12 2 REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR letha Resets 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 98h TXSTA CSRC TX9 TXEN SYNC SENB BRGH TRMT TX9D 0000 0010 0000 0010 99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRGO 0000 0000 0000 0000 9Ah SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 9Bh BAUDCTL ABDOVF RCIDL SCKP BRG16 WUE ABDEN 01 0 0 00 01 0 0 00 Legend x unknown u unchanged unimplemented locations read as o Shaded ce
53. a write to the port can cause a capture condition FIGURE 11 1 CAPTURE MODE OPERATION BLOCK DIAGRAM Set Flag bit CCP1IF PIR1 lt 2 gt CCPRTH CCPR1L Prescaler RC5 CCP1 P1A pin and 7 Capture Edge Detect Enable D TMR1H TMRIL CCP1CON lt 3 0 gt Q s 11 1 2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchronized Counter mode for the ECCP module to use the capture feature In Asynchronous Counter mode the capture operation may not work 11 1 3 SOFTWARE INTERRUPT When the Capture mode is changed a false capture interrupt may be generated The user should keep bit CCP1IE PIE1 lt 2 gt clear to avoid false interrupts and should clear the flag bit CCP1IF PIR1 lt 2 gt following any such change in operating mode 11 1 4 ECCP PRESCALER There are four prescaler settings specified by bits CCP1M lt 3 0 gt CCP1CON lt 3 0 gt Whenever the ECCP module is turned off or the ECCP module is not in Capture mode the prescaler counter is cleared Any Reset will clear the prescaler counter Switching from one capture prescaler to another may generate an interrupt Also the prescaler counter will not be cleared therefore the first capture may be from a non zero prescaler Example 11 1 shows the recommended method for switching between capture prescalers This example also clears the prescaler counter and will not generate the false i
54. and the internal sampling switch Rss impedance directly affect the time reguired to charge the capacitor CHOLD The sampling switch Rss impedance varies over the device voltage VDD see Figure 9 4 The maximum recommended impedance for analog sources is 10 kQ As the impedance is decreased the acquisition time may be decreased After the analog input channel is selected changed this acquisition must be done before the conversion can be started EQUATION 9 1 ACQUISITION TIME EXAMPLE Assumptions Temperature 50 C and external impedance of 10k 2 5 0V VDD Taco Amplifier Settling Time Hold Capacitor Charging Time Temperature Coefficient TAMP TC TCOFF 2us TC Temperature 25 C 0 05us C The value for TC can be approximated with the following equations 1 Vapeueo 1 22027 VcHOLD 1 VCHOLD charged to within 1 2 lsb Te Var g RET ee VCHOLD 2 VCHOLD charge response to VAPPLIED e RC 1 et Vappuagp e VAPPLIED 2047 combining 1 and 2 Solving for Tc Tc CHoLD RIC Rss RS In 1 2047 0OpF 1k2 7kQ 10kQ In 0 0004885 1 57us Therefore TACO 2us 1 37us 50 C 25 C 0 05us C 4 67us DS41262A page 100 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 Note 1 The reference voltage VREF has no effect on the eguation since it cancels itself out 2 The charge holding capac
55. e TMRO e Weak pull ups on PORTA PORTB REGISTER 2 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 0 OPTION REG OPTION REGISTER ADDRESS 81h OR 181h R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 RABPU INTEDG TOCS TOSE PSA PS2 PS1 PSO bit 7 bit 0 RABPU PORTA PORTB Pull up Enable bit 1 PORTA PORTB pull ups are disabled 0 PORTA PORTB pull ups are enabled by individual port latch values INTEDG Interrupt Edge Select bit 1 Interrupt on rising edge of RA2 AN2 TOCKI INT C1O0UT pin o Interrupt on falling edge of RA2 AN2 TOCKI INT C1OUT pin TOCS TMRO Clock Source Select bit 1 Transition on RAZ AN2 TOCKI INT C1OUT pin 0 Internal instruction cycle clock CLKOUT TOSE TMRO Source Edge Select bit 1 Increment on high to low transition on RA2 AN2 TOCKI INT C1O0UT pin 0 Increment on low to high transition on RA2 AN2 TOCKI INT C1O0UT pin PSA Prescaler Assignment bit 1 Prescaler is assigned to the WDT 0 Prescaler is assigned to the Timer0 module PS lt 2 0 gt Prescaler Rate Select bits Bit Value TMRO Rate WDT Rate 000 1 2 1 1 001 1 4 1 2 010 1 8 1 4 011 1 16 1 8 100 1 32 1 16 101 1 64 1 32 110 1 128 1 64 111 1 256 1 128 Note 1 A dedicated 16 bit WDT postscaler is available See Section 14 5 Watchdog Timer WDT for more information Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR
56. f is 0 the next instruction is discarded and a NOP is executed instead making this a two cycle instruction 2005 Microchip Technology Inc Preliminary DS41262A page 195 PIC16F685 687 689 690 BTFSS Bit Test f Skip if Set Syntax label BTFSS fb Operands 0 lt f lt 127 O0 lt b lt 7 Operation skip if f lt b gt 1 Status Affected None Description If bit b in register f is 0 the next instruction is executed If bit b is 1 then the next instruction is discarded and a NOP is executed instead making this a two cycle instruction CALL Call Subroutine Syntax label CALL k Operands 0 lt k lt 2047 Operation PC 1 TOS k PC lt 10 0 gt PCLATH lt 4 3 gt PC lt 12 11 gt Status Affected None Description Call Subroutine First return address PC 1 is pushed onto the stack The eleven bit immediate address is loaded into PC bits lt 10 0 gt The upper bits of the PC are loaded from PCLATH CALL is a two cycle instruction CLRF Clear f Syntax label CLRF f Operands 0 lt f lt 127 Operation 00h f 15Z Status Affected Z Description The contents of register f are cleared and the Z bit is set CLRW Clear W Syntax label CLRW Operands None Operation 00h gt W 152 Status Affected Z Description W register is cleared Zero bit Z is set CLRWDT Syntax Operands Operation Status Affected De
57. gt ECCPASE Cleared by Start of Shutdown Shutdown Firmware PWM PWM Period Event Occurs Event Clears Resumes DS41262A page 128 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 11 3 10 OPERATION IN SLEEP MODE In Sleep mode all clock sources are disabled Timer2 will not increment and the state of the module will not change If the ECCP pin is driving a value it will continue to drive that value When the device wakes Up it will continue from this state 11 3 10 1 OPERATION WITH FAIL SAFE CLOCK MONITOR If the Fail Safe Clock Monitor is enabled a clock failure will force the ECCP to be clocked from the internal oscillator clock source which may have a different clock frequency than the primary clock See Section 3 0 Clock Sources for additional details 11 3 11 EFFECTS OF A RESET Both Power on Reset and Resets will force all ports to Input mode and the ECCP registers to their Reset states This forces the Enhanced CCP module to reset to a state compatible with the standard CCP module 11 3 12 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP module for PWM operation 1 Configure the PWM pins PIA and P1B and P1C and P1D if used as inputs by setting the corresponding TRISC bits 2 Set the PWM period by loading the PR2 register 3 Configure the ECCP module for the desired PWM mode and configuration by loading the CCP1CON register w
58. reset by hardware The Sync character now transmits in the Pre Configured mode Break and Sync Transmit Sequence When the TXREG becomes empty as indicated by the TXIF the next data byte can be written to TXREG 12 3 6 RECEIVING A BREAK CHARACTER The EUSART module can receive a Break character in two ways The first method forces to configure the baud rate ata frequency of 9 13 the typical speed This allows for the Stop bit transition to be at the correct sampling location 13 bits for Break versus Start bit and 8 data bits for typical data The second method uses the auto wake up feature described in Section 12 3 4 Auto Wake up on RX Pin Falling Edge By enabling this feature the EUSART will sample the next two transitions on RX DT cause an RCIF interrupt and receive the next data byte followed by another interrupt Note that following a Break character the user will typically want to enable the Auto Baud Detect feature For both methods the user can set the ABD bit before placing the EUSART in its Sleep mode FIGURE 12 9 SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output Shift Clock TX pin Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXIF bit Transmit Buffer Reg Empty Flag TRMT bit Transmit Shift Reg Empty Flag SENB Im SENB Sampled Here Auto EE
59. status of the pins whereas writing to it will write to the port latch All write operations are read modify write operations Therefore a write to a port implies that the port pins are read this value is modified and then written to the port data latch RA3 reads o when MCLRE 1 The TRISA register controls the direction of the PORTA pins even when they are being used as analog inputs The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs I O pins configured as analog input always read o Note The ANSEL 11Eh register must be initialized to configure an analog channel as a digital input Pins configured as analog inputs will read o EXAMPLE 4 1 INITIALIZING PORTA BCF STATUS RPO Bank 0 BCF STATUS RP1 CLRF PORTA Init PORTA BSF STATUS RP1 Bank 2 CLRF ANSEL digital I O BSF STATUS RPO Bank 1 BCF STATUS RP1 MOVLW OCh MOVWF TRISA Set RA lt 3 2 gt as inputs and set RA lt 5 4 1 0 gt as outputs BCF STATUS RPO Bank 0 4 2 Additional Pin Functions Every PORTA pin on the PIC16F685 687 689 690 has an interrupt on change option and a weak pull up option RAO also has an Ultra Low Power Wake up option The next three sections describe these functions 4 2 1 WEAK PULL UPS Each of the PORTA pins except RA3 has an individually configurable internal weak pull up Control bits WPUAx enable or disable each pull up Refer to Regist
60. the Program Counter PC is at location 00h A 6 bit command is then supplied to the device Depending on the command 14 bits of program data are then supplied to or from the device depending on whether the command was a load or a read For used 8 i complete details of serial programming please refer to 5 i the PIC12F6XX 16F6EXX Memory Programming 14 9 In Circuit Serial Programming Specification DS41204 The PIC16F685 687 689 690 microcontrollers can be A typical In Circuit Serial Programming connection is serially programmed while in the end application circuit shown in Figure 14 10 This is simply done with two lines for clock and data and three other lines for power ground programming voltage DS41262A page 190 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 FIGURE 14 10 TYPICAL IN CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections External Connector PIC16F685 Signals 687 689 690 5V e VDD DV j Vss VPP 7 RA3 MCLR VPP CLK Lo aa Data 1 0 e RAO To Normal Connections Isolation devices as required 2005 Microchip Technology Inc Preliminary DS41262A page 191 PIC16F685 687 689 690 NOTES EEE SRA RE REA RAR SAR ERES EEE EEE DS41262A page 192 Preliminary O 2005 Microchip Technology Inc PIC16F685 687 689 690 15 0 INSTRUCTION SET SUMMARY
61. 0 16 64 19531 1 73 31 19230 0 16 25 57 6 56 818 1 36 21 56 818 1 36 40 55555 355 8 115 2 113 636 1 36 10 125 000 851 4 SYNC 0 BRGH 1 BRG16 0 ATE FOSC 4 000 MHz Fosc 2 000 MHz Fosc 1 000 MHz id Im s 4 Shana Amal Com kee Error ee K Error decimal K Error decimal 0 3 300 0 16 207 12 1202 016 207 1201 oe 103 1201 0 16 51 24 2404 016 103 2403 016 51 2403 0 16 25 96 9615 0 16 25 9615 0 16 12 19 2 19 231 0 16 12 57 6 62 500 8 51 3 115 2 125 000 8 51 1 2005 Microchip Technology Inc Preliminary DS41262A page 137 PIC16F685 687 689 690 TABLE 12 3 BAUD RATES FOR ASYNCHRONOUS MODES CONTINUED SYNC 0 BRGH 0 BRG16 1 Se Fosc 20 000 MHz Fosc 10 000 MHz Fosc 8 000 MHz K Actual SPBRG Actual SPBRG Actual SPBRG Rate Error value Rate Eror value Rate Error value K decimal K decimal K decimal 0 3 0 300 0 02 4165 0 300 0 02 2082 300 0 04 1665 1 2 1 200 0 03 1041 1 200 0 03 520 1201 0 16 415 2 4 2 399 0 03 520 2 404 0 16 259 2403 0 16 207 9 6 9 615 0 16 129 9 615 0 16 64 9615 0 16 51 19 2 19 231 0 16 64 19 531 1 73 31 19230 0 16 25 57 6 56 818 1 36 21 56 818 1 36 10 55555 3 55 8 115 2 113 636 1 36 10 125 000 8 51 4 SYNC 0 BRGH 0 BRG16 1 Se Fosc 4 000 MHz Fosc 2 000 MHz Fosc 1 000 MHz K Actual SPBRG Actual
62. 1 PIA PIB P1C and P1D are available on PIC16F685 PIC16F690 only 2 SS SDO SDA RX and DT available on PIC16F687 PIC16F689 PIC16F690 only 2005 Microchip Technology Inc Preliminary DS41262A page 3 PIC16F685 687 689 690 Table of Contents 140 Dovicg EE 5 2 0 Memory Organization wakai naa CANNES da dE RSRS ee ENEE 15 3 0 Clock Sources 40 WOPoris 5 0 Timer0 Module se 6 0 Timert Module with Gate Control 73 EOF Timez Module si eege ee Eed ENEE SEENEN 77 8 0 Comparator Module rA 9 0 Analog to Digital Converter A D Module see 6 10 0 Data EEPROM and Flash Program Memory Control 105 11 0 Enhanced Capture Compare PWM ECCP Module cece cere e eee ceneeeeeeeeeeeeeeenaeecaeeseaeseeeseaeeseesseeseeeesaeeseeseaeees 113 12 0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter EUSART manini 131 13 0 SSP Module Overview 14 0 Special Features of the CPUs a ccisesccsdavseccccevecsnsanesetentdhgeancendebvevdvsndadenndescasesSeudenuenpdar doi saith wanakagua walaa ku kauka kaaa kii kusaka 15 0 E tee 16 0 Development SUpport siia Aiei Shania aa MWEZA mwaa Wa Kua aneesveveseceovecuseresnbevyueveee sit casa geal estdenusienstenvestaaviva esedbeeoveareatvesterts 17 0 Electrical Specifications At iz wka Bakaa dia cagada eaa ah sin Aaaa adah Aaaa aaah aie aa ap Daa ia aka aaia 18 0 DC and AC Characteristics Graphs and Tables 19 0 Packaging IMO ANA EE Appendi
63. 10 8 7 6 6 Note 1 Changing duty cycle will cause a glitch 2005 Microchip Technology Inc Preliminary DS41262A page 117 PIC16F685 687 689 690 FIGURE 11 4 PWM OUTPUT RELATIONSHIPS ACTIVE HIGH STATE d H Duty PR2 1 CCP1CON Signal a 5 i Cycle i 1 lt 7 6 gt d i dt Period 00 Single Output P1A Modulated i ai Delay Delay i P1A Modulated j Bica 10 Half bridge P1B Modulated PIA Active YA i i Full bridge P1B Inactive i 01 Forward i P1C Inactive 1 i i P1D Modulated i P1A Inactive i i e Full bridge P1B Modulated ps Sr Reverse i P1C Active i P1D Inactive i i i Relationships Period 4 Tosc PR2 1 TMR2 prescale value Duty Cycle Tosc CCPR1L lt 7 0 gt CCP1CON lt 5 4 gt TMR2 prescale value Delay 4 Tosc PWM1CONK lt 6 0 gt Note 1 Dead band delay is programmed using the PWM1CON register Section 11 3 7 Programmable Dead Band Delay FIGURE 11 5 PWM OUTPUT RELATIONSHIPS ACTIVE LOW STATE 0 Duty PR2 1 CCP1CON Signal Col os ge lt 7 6 gt yaa i i lt Period ad on Single Output PiAModulated __ i P1A Modulated 1 lt gt i l Delay 1 Delay i to Malibridge pygmodulated qt PIA Active i i i Full b
64. 17 30 ms Extended temperature 32 TOST Oscillation Start up Timer 1024Tosc Tosc OSC1 period Period 33 TPWRT Power up Timer Period 28 64 132 ms VDD 5V 40 C to 85 C TBD TBD TBD ms Extended Temperature 34 Tioz I O High impedance from 2 0 us MCLR Low or Watchdog Timer Reset BVHY Brown out Reset Hysteresis 25 mV BVDD Brown out Reset Voltage 2 025 2 175 V 35 TBOR Brown out Reset Pulse Width 100 us VDD lt Bvpp D005 Legend TBD To Be Determined These parameters are characterized but not tested Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 2005 Microchip Technology Inc Preliminary DS41262A page 223 PIC16F685 687 689 690 FIGURE 17 7 TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS TOCKI A K lt 40 H 41 gt I 42 woo mas Ma aa T1CKI 45 46 I a 47 gt lt 48 gt TMRO or TMR1 X I TABLE 17 5 TIMERO AND TIMER1 EXTERNAL CLOCK REQUIREMENTS a Sym Characteristic Min Typt Max Units Conditions A0 TTOH TOCKI High Pulse Width No Prescaler 0 5 TcY 20 ns With Prescaler 10 ns 415 TTOL TOCKI Low Pulse Width No Prescaler 0 5 Tcy 20 ns With Prescaler 10 ns 42 TTOP TOCKI Period Greater of ns N prescale 20 or Icy 40 value
65. 1xxx 0009 quuu 103h 183h 8Eh PCON ULPWUE SBOREN POR BOR 01 qq 0u uu Legend u unchanged x unknown unimplemented bit reads as 0 q value depends on condition Shaded cells are not used by BOR Note 1 Other non Power up Resets include MCLR Reset and Watchdog Timer Reset during normal operation DS41262A page 178 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 FIGURE 14 3 TIME OUT SEOUENCE ON POWER UP DELAYED MCLR CASE 1 VDD m MCLR Internal POR gt TPwRT PWRT Time out Le Tost OST Time out FIGURE 14 4 TIME OUT SEQUENCE ON POWER UP DELAYED MCLR CASE 2 VDD ma MCLR Internal POR Is Jill o i ER Internal Reset PWRT Time out e TOST OST Time out Internal Reset FIGURE 14 5 TIME OUT SEQUENCE ON POWER UD MCLR WITH VDD VDD C MCLR Internal POR a TewaT PWRT Time out e TOST OST Time out Internal Reset 2005 Microchip Technology Inc Preliminary DS41262A page 179 PIC16F685 687 689 690 TABLE 14 4 INITIALIZATION CONDITION FOR REGISTER MCLR Reset Kee ierg Register Address Power on Reset WDT Reset Wake up from Slee Brown out Reset p eee through WDT Time out W XXXX XXX
66. 2 00 0000 0000 1000 SLEEP Go into Standby mode 1 00 0000 0110 0011 TO PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk CG DC 7 XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1 When an I O register is modified as a function of itself e g MOVF PORTA 1 the value used will be that value present on the pins themselves For example if the data latch is 1 for a pin configured as input and is driven low by an external device the data will be written back with a o 2 lf this instruction is executed on the TMRO register and where applicable d 1 the prescaler will be cleared if assigned to the Timer0 module 3 Ifthe Program Counter PC is modified or a conditional test is true the instruction requires two cycles The second cycle is executed as a NOP DS41262A page 194 Prelimina ry 2005 Microchip Technology Inc PIC16F685 687 689 690 15 2 Instruction Descriptions ADDLW Syntax Operands Operation Status Affected Description ADDWF Syntax Operands Operation Status Affected Description ANDLW Syntax Operands Operation Status Affected Description ANDWF Syntax Operands Operation Status Affected Description Add literal and W label ADDLW k 0 lt k lt 255 W k gt W C DC Z The contents of the W register are added to the eight bit literal k and the result is placed in the W register
67. ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 12 2 The heart of the transmitter is the Transmit serial Shift Register TSR The shift register obtains its data from the read write transmit buffer TXREG The TXREG register is loaded with data in software The TSR register is not loaded until the Stop bit has been transmitted from the previous load As soon as the Stop bit is transmitted the TSR is loaded with new data from the TXREG register if available Once the TXREG register transfers the data to the TSR register occurs in one Tcy the TXREG register is empty and flag bit TXIF PIR1 lt 4 gt is set This interrupt can be enabled disabled by setting clearing enable bit TXIE PIE1 lt 4 gt Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software Flag bit TXIF is not cleared immediately upon loading the transmit buffer register TXREG TXIF becomes valid in the second instruction cycle following the load instruction Polling TXIF immediately following a load of TXREG will return invalid results While flag bit TXIF indicates the status of the TXREG register another bit TRMT TXSTA lt 1 gt shows the status of the TSR register Status bit TRMT is a read only bit which is set when the TSR register is empty No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty Note 1 T
68. Add W and f label ADDWF fd 0 lt f lt 127 de 0 1 W f destination C DC Z Add the contents of the W register with register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f AND literal with W label ANDLW k 0 lt k lt 255 W AND k gt W 7 The contents of W register are AND ed with the eight bit literal kK The result is placed in the W register AND W with f label ANDWF fd O lt f lt 127 de 0 1 W AND f destination Z AND the W register with register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f BCF Syntax Operands Operation Status Affected Description BSF Syntax Operands Operation Status Affected Description BTFSC Syntax Operands Operation Status Affected Description Bit Clear f label BCE fb 0 lt f lt 127 O lt bs7 0 gt f lt b gt None Bit b in register f is cleared Bit Set f label BSF tb 0 lt f lt 127 0 lt b lt 7 1 f lt b gt None Bit b in register f is set Bit Test f Skip if Clear label BTFSC f b 0 lt f lt 127 0O lt b lt 7 skip if f lt b gt 0 None If bit b in register f is 1 the next instruction is executed If bit b in register
69. CIVP 0 1 e Wake up from Sleep C1VN gt CIVP 1 1 Configurable as feedback input to the PWM C1VN lt C1VP 1 0 e Programmable four input multiplexer Programmable two input reference selections E Note 1 The internal output of the comparator is e orgao ea i ji latched at the end of each instruction e Output synchronization to Timer1 clock input cycle External outputs are not latched Comparator C2 only 2 The C1 interrupt will operate correctly Note C2 can be linked to Timer1 Gate with C1OE set or cleared 3 For C1 output on RA2 AN2 TOCKI INT 8 1 Control Registers CIOUT S Both comparators have separate control and C10E 1 CION 1 and TRISA lt 2 gt 0 configuration registers CM1CONO for C1 and CM2CONO for C2 In addition Comparator C2 has a second control register CM2CON1 for synchronization control and simultaneous reading of both comparator outputs 8 1 1 COMPARATOR C1 CONTROL REGISTER The CM1CONO register shown in Register 8 1 contains the control and Status bits for the following Comparator enable Comparator input selection Comparator reference selection Output mode Setting CION CM1CONO lt 7 gt enables Comparator C1 for operation Bits C1CH lt 1 0 gt CM1CONO lt 1 0 gt select the comparator input from the four analog pins AN lt 7 5 1 gt Note To use AN lt 7 5 1 gt as analog inputs the appropriate bits must be programmed to 1 in t
70. CMOS Fosc 4 output RA5 T1CKI OSC1 CLKIN RA5 TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up T1CKI ST Timer clock input OSC1 XTAL Crystal Resonator CLKIN ST External clock input RC oscillator connection RB4 AN10 SDI SDA RB4 TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up AN10 AN A D Channel 10 input SDI ST SC SPI data input SDA ST OD IC data input output RB5 AN11 RX DT RB5 TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up AN11 AN A D Channel 11 input RX ST EUSART asynchronous input DT ST CMOS EUSART synchronous data Legend AN Analog input or output CMOS CMOS compatible input or output OD Open Drain TTL TTL compatible input ST Schmitt Trigger input with CMOS levels HV High Voltage XTAL Crystal DS41262A page 12 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 TABLE 1 3 PINOUT DESCRIPTION PIC16F690 CONTINUED Name Function tse a ve Description RB6 SCK SCL RB6 TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up SCK ST CMOS SPI clock SCL ST OD CTM clock RB7 TX CK RB7 TTL CMOS General purpose I O Individually controlled interru
71. Comparator 2 Interrupt Enable bit 1 Enables Comparator 2 interrupt 0 Disables Comparator 2 interrupt bit 5 CIE Comparator 1 Interrupt Enable bit 1 Enables Comparator 1 interrupt o Disables Comparator 1 interrupt bit 4 EEIE EE Write Operation Interrupt Enable bit 1 Enabled 0 Disabled bit 3 0 Unimplemented Read as 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown DS41262A page 28 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 2 2 2 6 PIR1 Register The PIR1 register contains the interrupt flag bits as Note Interrupt flag bits are set when an interrupt shown in Register 2 6 condition occurs regardless of the state of its corresponding enable bit or the global enable bit GIE INTCON lt 7 gt User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt REGISTER 2 6 PIR1 PERIPHERAL INTERRUPT REQUEST REGISTER 1 ADDRESS 0Ch U 0 R W 0 R 0 R 0 R W 0 R W 0 R W 0 R W 0 ADIF RCIF TxIF SSPIF CCP1IF TMR2IF TMRIIF bit 7 bit 0 bit 7 Unimplemented Read as oi bit 6 ADIF A D Converter Interrupt Flag bit 1 The A D conversion completed must be cleared in software o The A D conversion is not complete bit 5 RCIF EUSART Receive Interrupt Flag bit 1
72. DS41262A page 145 PIC16F685 687 689 690 12 3 4 AUTO WAKE UP ON RX PIN Special care should be taken when using the FALLING EDGE Two Speed Start up or the Fail Safe Clock Monitor because the application will start running from the The auto wakekup feature allows ine controller 10 internal oscillator before the primary oscillator is ready wake up due to activity on the RX DT line despite the baud clock being turned off This allows communications Because the auto wake up feature uses the RCIF flag systems to save power by only responding to direct to signify the wake up event the application should requests discard the data read from RCREG when servicing the Setting the WUE bit BAUDCTL lt 1 gt enables the Reece nessa hE vee auto wake up feature When the auto wake up feature When entering Sleep with auto wake up enabled the is enabled the next falling edge on the RX DT line will following procedure should be used trigger an RCIF interrupt The WUE bit will automatically 1 Clear all interrupt flags including RCIF clear after the rising RX DT edge after triggering a falling 2 Check RCIDL to ensure no receive is currently edge Receiving a RCIF interrupt after setting the WUE bit signals to the user that the wake up event has occurred See Figure 12 7 and Figure 12 8 for timing details of the auto wake up process in progress 3 No characters are being received so the WUE bit can be set 4 Sleep 12 3 4 1 Special Consi
73. EN Interrupt on Lc I Interrupt on Change Ei Change lt E RD PORTA RD PORTA To Comparator To A D Converter To TMRO e a DINT Note 1 ANSEL determines Analog Input mode To A D Converter Note 1 ANSEL determines Analog Input mode DS41262A page 52 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 4 2 4 4 RA3 MCLR VPP Figure 4 4 shows the diagram for this pin The RA3 MCLR VPP pin is configurable to function as one of the following ageneral purpose input as Master Clear Reset with weak pull up FIGURE 4 4 BLOCK DIAGRAM OF RA3 voo MCLRE ed Weak Data Bus MCLRE Reset NEM Input Pin RD Vss TRISA MCLRE Vss RD 4 a A PORTA J eD Q S oa De WR gt CK o IOCA NA EN Q3 RD IOCA Q D EN Interrupt on Change LC J RD PORTAT 4 2 4 5 RA4 AN3 T1G OSC2 CLKOUT Figure 4 5 shows the diagram for this pin The RA4 AN3 T1G OSC2 CLKOUT pin is configurable to function as one of the following a general purpose I O an analog input for the A D e a TMR gate input a crystal resonator connection a clock output FIGURE 4 5 BLOCK DIAGRAM OF RA4 Analog Input Mode CLK D Data Bus Modes ais ee Vop WR
74. Lead Plastic Quad Flat No Lead Package ML 4x4x0 9 mm Body QFN Saw Singulated ja D D1 EXPOSED METAL i PAD Um i ED qa e ED a E o ED a 2 ED a ms E 1 Dp 1 a x ANN OPTIONAL S INDEX bo AREA TOP VIEW BOTTOM VIEW ES Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins 20 20 Pitch e 020 BSC 0 50 BSC Overall Height A 031 035 039 0 80 0 90 1 00 Standoff Al 000 001 002 0 00 0 02 0 05 Contact Thickness A3 008 REF 0 20 REF Overall Width E 152 157 163 3 85 4 00 4 15 Exposed Pad Width E2 100 106 110 2 55 2 70 2 80 Overall Length D 152 157 163 3 85 4 00 4 15 Exposed Pad Length D2 100 106 110 2 55 2 70 2 80 Contact Width b 007 010 012 0 18 0 25 0 30 Contact Length L 012 016 020 0 30 0 40 0 50 Controlling Parameter Notes JEDEC equivalent Not Registered Drawing No C04 126 Revised 04 24 05 2005 Microchip Technology Inc Preliminary DS41 262A page 243 PIC16F685 687 689 690 NOTES EEE ERA RE REA EAR SR REGE EE EEE EE DS41262A page 244 Preliminary O 2005 Microchip Technology Inc PIC16F685 687 689 690 APPENDIX A DATA SHEET APPENDIK B MIGRATING FROM REVISION HISTORY OTHER PICmicro SE DEVICES Revision A ao This discusses some of the
75. Memory 105 Associated Registers 112 Code Protection 111 Reading 108 Writing 108 Data Memory cuz cesciesccssectdeccadecedeccssseevietosntvedasdiseesttevieesencrend 16 Data Address bit DA 156 DC Characteristics Extended e aA a E aaa a a Naas daia 214 elt EE 212 Industrial and Extended sessnenaenneeeeneaeeean 211 216 Demonstration Boards PIC DEM AAA 206 PIGDEM AZ usinas nes Tola E Akawa 207 PICDEM ABR EE 207 PICDEM 2 Plus 206 PICDEM 3 206 PICDEM 4 206 PICDEM LIN ssa sas inss re chas ta E 207 PICDEM USB cassia sem ensaiar orar eet 207 PICDEM net Internet Ethernet 206 Development Support 203 Device Overview wwwesemaanammaanwaaaniwanami naniii azima 5 E ECCP See Enhanced Capture Compare PWM ECCP ECCPAS Register secccessecsssseseesssescerevsnsseceecsseesseeesees 127 EEADR Register ssccccsseceseesecsseresnesensseseessseeesetesees EEADR Registers EEADRH Registers o 105 106 EECONT Register ar e lean 105 107 EECON2 Register sikeee siinide niania sine 105 EEDAT Register napaa aaea AENA AEEA 106 EEDATH Register iia 106 EEPROM Data Memory Avoiding Spurious Wrte 111 Write VI wa dkivesteesecesseca Anara E iiaea sani 111 Electrical Specifications 209 Enhanced Capture Compare PWM ECCP 113 Associated registers
76. PIC16F685 687 689 690 144 Context Saving During Interrupts During an interrupt only the return PC value is saved on the stack Typically users may wish to save key registers during an interrupt e g W and Status registers This must be implemented in software Since the upper 16 bytes of all GPR banks are common in the PIC16F685 687 689 690 see Figures 2 1 and 2 2 temporary holding registers W_TEMP and STATUS_TEMP should be placed in here These 16 locations do not require banking and therefore make it easier to context save and restore The same code shown in Example 14 1 can be used to Store the W register Store the Status register Execute the ISR code Restore the Status and Bank Select Bit register e Restore the W register Note The PIC16F685 687 689 690 normally does not require saving the PCLATH However if computed GOTO s are used in the ISR and the main code the PCLATH must be saved and restored in the ISR EXAMPLE 14 1 SAVING STATUS AND W REGISTERS IN RAM MOVWF W TEMP Copy W to TEMP register SWAPF STATUS W Swap status to be saved into W CLRF STATUS bank 0 regardless of current bank Clears IRP RP1 RPO MOVWF STATUS TEMP Save status to bank zero STATUS TEMP register ISR Insert user code here SWAPF STATUS TEMP W Swap STATUS_TEMP register into W sets bank to original state MOVWF STATUS Move W into Status regis
77. PIC16F685 687 689 690 REGISTER 12 1 TKSTA TRANSMIT STATUS AND CONTROL REGISTER ADDRESS 98h R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 1 R W 0 CSRC TX9 TXEN SYNC SENB BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC Clock Source Select bit Asynchronous mode Don t care Synchronous mode 1 Master mode clock generated internally from BRG 0 Slave mode clock from external source bit 6 TX9 9 bit Transmit Enable bit 1 Selects 9 bit transmission 0 Selects 8 bit transmission bit 5 TXEN Transmit Enable bit 1 Transmit enabled 0 Transmit disabled Note SREN CREN overrides TXEN in Sync mode bit 4 SYNC EUSART Mode Select bit 1 Synchronous mode 0 Asynchronous mode bit 3 SENB Send Break Character bit Asynchronous mode 1 Send Sync Break on next transmission cleared by hardware upon completion 0 Sync Break transmission completed Synchronous mode Don t care bit 2 BRGH High Baud Rate Select bit Asynchronous mode 1 High speed 0 Low speed Synchronous mode Unused in this mode bit 1 TRMT Transmit Shift Register Status bit 1 TSR empty 0 TSR full bit 0 TX9D 9th bit of Transmit Data Can be address data bit or a parity bit Note 1 PIC16F687 PIC16F689 PIC16F690 only Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown DS41262A page 132 Preliminary
78. PORTB will end the mismatch condition and allow flag bit RABIF to be cleared The latch holding the last read value is not affected by a MCLR nor Brown out Reset After these Resets the RABIF flag will continue to be set if a mismatch is present Note If a change on the UO pin should occur when the read operation is being executed start of the Q2 cycle then the RABIF interrupt flag may not get set Furthermore since a read or write on a port affects all bits of that port care must be taken when using multiple pins in Interrupt on change mode Changes on one pin may not be seen while servicing changes on another pin DS41262A page 56 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 REGISTER 4 5 PORTB PORTB REGISTER ADDRESS 06h OR 106h RWx RWx DW DW U 0 U 0 U 0 U 0 RB7 RB6 RB5 RB4 bit 7 bit 0 bit 7 4 RB lt 7 4 gt PORTB I O Pin bits 1 Port pin is gt VIH 0 Port pin is lt VIL bit 3 0 Unimplemented Read as oi Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown REGISTER 4 6 TRISB TRI STATE PORTB REGISTER ADDRESS 86h OR 186h R W 1 R W 1 R W 1 R W 1 U 0 U 0 U 0 U 0 TRISB7 TRISB6 TRISB5 TRISB4 bit 7 bit 0 bit 7 4 TRISB lt 7 4 gt PORTB Tri State Control bits 1 P
79. R W 0 P1M1 P1MO DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 bit 7 6 P1M lt 1 0 gt PWM Output Configuration bits If CCP1M lt 3 2 gt s 00 01 10 xx P1A assigned as Capture Compare input P1B P1C P1D assigned as port pins If CCP M lt 3 2 gt 11 00 Single output P1A modulated P1B P1C P1D assigned as port pins 01 Full bridge output forward P1D modulated P1A active P1B P1C inactive 10 Half bridge output P1A P1B modulated with dead band control P1C P1D assigned as port pins 11 Full bridge output reverse P1B modulated P1C active PIA P1D inactive bit 5 4 DC1B lt 1 0 gt PWM Duty Cycle Least Significant bits Capture mode Unused Compare mode Unused PWM mode These bits are the two LSbs of the PWM duty cycle The eight MSbs are found in CCPR1L bit 3 0 CCP1M lt 3 0 gt ECCP Mode Select bits 0000 Capture Compare PWM off resets ECCP module 0001 Unused reserved 0010 Compare mode toggle output on match CCP1IF bit is set 0011 Unused reserved 0100 Capture mode every falling edge 0101 Capture mode every rising edge 0110 Capture mode every 4th rising edge 0111 Capture mode every 16th rising edge 1000 Compare mode set output on match CCP1IF bit is set 1001 Compare mode clear output on match CCP1IF bit is set 1010 Compare mode generate software interrupt on match CCP1IF bit is set CCP1 pin is unaffected 1011 Compare mode tri
80. RAO xx xxxx uu uuuu 07h 107h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RCO XXXX xxxx UUUU uuuu OBh 8Bh INTCON GIE PEIE TOIE INTE RABIE TOIF INTF RABIF 0000 000x 0000 000x 10Bh 18Bh OCh PIR1 ADIF RCIF TXIF SSPIF CCPI1IF TMR2IF TMRIIF 000 0000 000 0000 8Ch PIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 000 0000 000 0000 85h 185h TRISA TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 11 1111 11 1111 87h 187h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISCO 1111 1111 1111 1111 118h VRCON C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VRO 0000 0000 0000 0000 119h CM1CONO C1ON C10UT C1OE C1POL CR C1CH1 C1CHO 0000 0000 0000 000 11Ah CM2CONO C20N C20UT C2OE C2POL C2R C2CH1 C2CHO 0000 0000 0000 000 11Bh CM2CON1 MC10UT MC2OUT TiGSS C2SYNC 00 10 00 10 11Eh ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANSO 1111 1111 1111 1111 19Eh SRCON SR1 SRO C1SEN C2SEN PULSS PULSR 0000 00 0000 00 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used by the Capture Compare or Timer1 module O 2005 Microchip Technology Inc Preliminary DS41262A page 91 PIC16F685 687 689 690 NOTES a wwwww vv w vw www wv x v www v wvw wvwwww awwvww wwwwww wv ww xwww ww wwwvwwvvwwwvwwwwv vv DS41262A page 92 Preliminary 2005 Microchip Technology Inc PIC16F68
81. RC6 AN8 SS OSCUGLKI Power on 8 Gul RC7 AN9 SDO Timing nesel OSC2 CLKO Generation Kl Watchdog W Reg Timer Brown out Reset Internal Oscillator Block MCLR VDD Vss E SDI SCK TOCKI TIG CH a ME p4B PIC PID bR SDA i x zi i Synchronous imer0 Timer1 Timer2 EUSART ECCP Serial Port AN8 AN9 AN10 AN11 a A A d i A v Vi 2 Ce Analog To Digital Converter Analog Comparators EEDAT and Reference 8 256 Bytes E HIS LL Dal EEPROM Gd DD M D P X Less VREF ANO AN1 ANS AN3 ANA ANS AN6 AN7 C1IN C1IN C1OUT C2IN C2IN C2OUT EEADR 2005 Microchip Technology Inc Preliminary DS41262A page 7 PIC16F685 687 689 690 TABLE 1 1 PINOUT DESCRIPTION PIC16F685 Name Function Input Oulput Description Type Type RAO ANO C1IN ICSPDAT RAO TTL General purpose UO Individually controlled interrupt on ULPWU change Individually enabled pull up ANO AN A D Channel O input C1IN AN Comparator 1 positive input ICSPDAT TTL CMOS ICSP Data I O ULPWU AN Ultra Low Power Wake up input RA1 AN1 C12IN VREF ICSPCLK HAT TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up AN1 AN A D Channel 1 input C12IN AN Comparator 1 or 2 negative input VREF AN External Voltage Reference for A D ICSPCLK ST ICSPTM clock RA2 AN2
82. SR Latch Configuration bits 2 00 SR latch is disabled 01 SR latch is enabled C1OUT pin is the latch non inverting output C2OUT pin is the C2 comparator output 10 SR latch is enabled C1OUT pin is the C1 comparator output C2OUT pin is the latch inverting output 11 SR latch is enabled C1OUT pin is the latch non inverting output C2OUT pin is the latch inverting output bit 5 C1SEN C1 Set Enable bit 1 C1 comparator output sets SR latch 0 C1 comparator output has no effect on SR latch bit 4 C2REN C2 Reset Enable bit 1 C2 comparator output resets SR latch o C2 comparator output has no effect on SR latch bit 3 PULSS Pulse the SET Input of the SR Latch bit 1 Pulse input 0 Always reads back o bit 2 PULSR Pulse the Reset Input of the SR Latch bit 1 Pulse input 0 Always reads back o bit 1 0 Unimplemented Read as o Note 1 The C1OUT or C2OUT bits in the CM1CONO and CM2CONO registers respectively will always reflect the actual comparator outputs not the pins regardless the SR latch operation 2 To enable the SR Latch output to the pins the appropriate C1OE C20E TRISA2 and TRISC4 bits CM1CON0 CM2CONO TRISA and TRISC registers respec tively must be properly configured Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown DS41262A page 86 Prel
83. T Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 25 PIC16F685 687 689 690 2 2 2 3 INTCON Register The INTCON register is a readable and writable register which contains the various enable and flag bits for TMRO register overflow PORTA change and external RA2 AN2 TOCKI INT C1OUT pin interrupts Note Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit GIE INTCON lt 7 gt User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt REGISTER 2 3 INTCON INTERRUPT CONTROL REGISTER ADDRESS OBh 8Bh 10Bh OR 18Bh R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 RW x GIE PEIE TOIE INTE RABIE 3 rop INTF RABIF bit 7 bit 0 bit 7 GIE Global Interrupt Enable bit 1 Enables all unmasked interrupts 0 Disables all interrupts bit 6 PEIE Peripheral Interrupt Enable bit 1 Enables all unmasked peripheral interrupts 0 Disables all peripheral interrupts bit 5 TOIE TMRO Overflow Interrupt Enable bit 1 Enables the TMRO interrupt o Disables the TMRO interrupt bit 4 INTE RA2 INT External Interrupt Enable bit 1 Enables the RA2 INT external interrupt 0 Disables the RA2 INT external interrupt bit 3 RABIE PORTA PORTB Change Interrupt Enable bit 3 1 Enables the P
84. TOCKI INT C10UT RA2 ST CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up AN2 AN A D Channel 2 input TOCKI ST Timer0 clock input INT ST External interrupt pin C10UT CMOS Comparator 1 output RA3 MCLR VPP RA3 TTL General purpose input Individually controlled interrupt on change MCLR ST Master Clear with internal pull up VPP HV Programming voltage RA4 AN3 T1G OSC2 CLKOUT RA4 TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up AN3 AN A D Channel 3 input TIG ST Timer1 gate input OSC2 XTAL Crystal Resonator CLKOUT CMOS Fosc 4 output RA5 T1CKI OSC1 CLKIN RA5 TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up T1CKI ST Timer1 clock input OSC1 XTAL Crystal Resonator CLKIN ST External clock input RC oscillator connection RB4 AN10 RB4 TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up AN10 AN A D Channel 10 input RB5 AN11 RB5 TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up AN11 AN A D Channel 11 input RB6 RB6 TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up RB7 RB7 TTL CMOS General purpose I O Individually controlled interrupt on change Indiv
85. TXIF SSPIF CCP1IF TMR2IF TMRIIF 000 0000 000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X 19h TXREG EUSART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG EUSART Receive Data Register 0000 0000 0000 0000 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 1111 8Ch PIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMRIIE 000 0000 000 0000 98h TXSTA CSRC TX9 TXEN SYNC SENB BRGH TRMT TX9D 0000 0010 0000 0010 99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRGO 0000 0000 0000 0000 9Ah SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 9Bh BAUDCTL ABDOVF RCIDL SCKP BRG16 WUE ABDEN 01 0 0 00 01 0 0 00 Legend x unknown unimplemented locations read as 0 Shaded cells are not used for Asynchronous Transmission Note 1 PIC16F687 PIC16F689 PIC16F690 only O 2005 Microchip Technology Inc Preliminary DS41262A page 143 PIC16F685 687 689 690 12 3 2 EUSART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 12 5 The data is received on the RB5 AN11 RX DT pin and drives the data recovery block The data recovery block is actually a high speed shifter operating at 16 times the baud rate whereas the main receive serial shifter operates at the bit rate or at Fosc This mode would typically be used in RS 232 systems To set up an Asynchronous Reception 2 1 Initialize the SPBRGH SPBRG registers for the appropriate baud rate Set or clear the BRGH 3
86. The EUSART receive buffer is full cleared by reading RCREG os The EUSART receive buffer is not full bit 4 TXIF EUSART Transmit Interrupt Flag bit 1 The EUSART transmit buffer is empty cleared by writing to TXREG os The EUSART transmit buffer is full bit 3 SSPIF Synchronous Serial Port SSP Interrupt Flag bit 1 The Transmission Reception is complete must be cleared in software 0 Waiting to Transmit Receive bit 2 CCP1IF CCP1 Interrupt Flag bit Capture mode 1 A TM register capture occurred must be cleared in software o No TMR1 register capture occurred Compare mode 1 A TMR1 register compare match occurred must be cleared in software o No TMR1 register compare match occurred PWM mode Unused in this mode bit 1 TMR2IF TMR2 to PR2 Interrupt Flag bit 2 1 A TMR2 to PR2 match occurred must be cleared in software o No TMR2 to PR2 match occurred bit 0 TMRI1IF TMR1 Overflow Interrupt Flag bit 1 The TMR1 register overflowed must be cleared in software os The TMR register did not overflow Note 1 PIC16F687 PIC16F689 PIC 16F690 only 2 PIC16F685 PIC16F690 only Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 29 PIC16F685 687 689 690 2 2 2 7 PIR2 Register The PIR2 register contains the interrupt flag bits
87. Time No Prescaler 0 5TcY 20 ns With Prescaler 20 ns 51 TecH CCP1 Input High Time No Prescaler 0 5TCY 20 ns With Prescaler 20 ns 52 TecP CCP1 Input Period 3Tcy 40 ns IN prescale N value 1 4 or 16 53 Tech CCP1 Output Rise Time 10 25 ns 54 TecF CCP1 Output Fall Time 10 25 ns These parameters are characterized but not tested t Dalta in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 2005 Microchip Technology Inc Preliminary DS41262A page 225 PIC16F685 687 689 690 TABLE 17 7 COMPARATOR SPECIFICATIONS Comparator Specifications Standard Operating Conditions unless otherwise stated p p Operating temperature 40 C lt TA lt 125 C ai Sym Characteristics Min Typ Max Units Comments CO Vos Input Offset Voltage 5 0 10 mV 02 VCM Input Common Mode Voltage 0 VDD 1 5 V C03 CMRR Common Mode Rejection 55 db Ratio C04 TRT Response Time 150 400 ns 05 Tmc2coV Comparator Mode Change to 10 us Output Valid These parameters are characterized but not tested Note 1 Response time measured with one comparator input at VDD 1 5 2 while the other input transitions from Vss to VDD 1 5V TABLE 17 8 COMPARATOR VOLTAGE REFERENCE CVREF SPECIFICATIONS
88. Transmit Shift Reg Empty Flag fio 2005 Microchip Technology Inc Preliminary DS41262A page 147 PIC16F685 687 689 690 124 EUSART Synchronous Master Mode The Synchronous Master mode is entered by setting the CSRC bit TKSTA lt 7 gt In this mode the data is transmitted in a half duplex manner i e transmission and reception do not occur at the same time When transmitting data the reception is inhibited and vice versa Synchronous mode is entered by setting bit SYNC TXSTA lt 4 gt In addition enable bit SPEN RCSTA lt 7 gt is set in order to configure the RB6 SCK SCL and RB7 TX CK or RB5 AN11 RX DT I O pins to CK clock and DT data lines respectively The Master mode indicates that the processor transmits the master clock on the CK line Clock polarity is selected with the SCKP bit BAUDCTL lt 4 gt setting SCKP sets the IDLE state on CK as high while clearing the bit sets the IDLE state low This option is provided to support Microwire devices with this module 12 4 1 EUSART SYNCHRONOUS MASTER TRANSMISSION The EUSART transmitter block diagram is shown in Figure 12 2 The heart of the transmitter is the Transmit serial Shift Register TSR The shift register obtains its data from the read write transmit buffer register TXREG The TXREG register is loaded with data in software The TSR register is not loaded until the last bit has been transmitted from the previous load A
89. Transmitter e SPEN RCSTA lt 7 gt bit must be set 1 e TRISB lt 6 gt bit must be set 1 and TRISB lt 7 gt bit must be set 1 Note The EUSART control will automatically reconfigure the I O pin from input to output as needed The operation of the EUSART module is controlled through three registers Transmit Status and Control TXSTA Receive Status and Control RCSTA e Baud Rate Control BAUDCTL e Baud Rate registers SPBRGH SPBRG See Registers 12 1 12 2 and 12 3 for more detail 12 1 Clock Accuracy With Asynchronous Operation The factory calibrates the internal oscillator block output INTOSC for 8 MHz However this frequency may drift as VDD or temperature changes and this directly affects the asynchronous baud rate generator Two methods may be used to adjust the baud rate clock but both require a reference clock source of some kind The first preferred method uses the OSCTUNE register to adjust the INTOSC output back to 8 MHz Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source see Section 3 4 Internal Clock Modes for more information The other method adjusts the value in the baud rate generator There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency 2005 Microchip Technology Inc Preliminary DS41262A page 131
90. a NOP is executed instead making it a two cycle instruction GOTO Unconditional Branch Syntax label GOTO k Operands 0 lt k lt 2047 Operation k PC lt 10 0 gt PCLATH lt 4 3 gt PC lt 12 11 gt Status Affected None Description GOTO is an unconditional branch The eleven bit immediate value is loaded into PC bits lt 10 0 gt The upper bits of PC are loaded from PCLATH lt 4 3 gt GOTO s a two cycle instruction INCF Increment f Syntax label INCF fd Operands 0 lt f lt 127 de 0 1 Operation f 1 destination Status Affected Z Description The contents of register f are incremented If d is o the result is placed in the W register If d is 1 the result is placed back in register f INCFSZ Increment f Skip if 0 Syntax label INCFSZ fd Operands 0 lt f lt 127 de 0 1 Operation f 1 destination skip if result 0 Status Affected None Description The contents of register f are incremented If d is 0 the result is placed in the W register If d is T the result is placed back in register f If the result is 1 the next instruction is executed If the result is 0 a NOP is executed instead making ita two cycle instruction IORLW Inclusive OR literal with W Syntax label IORLW k Operands 0 lt k lt 255 Operation W OR k gt W Status Affected Z Description The contents of the W re
91. accessed by reading or writing to SSPADD register with bits SSPM lt 3 0 gt 1001 See Registers 13 2 and 13 3 for more details 3 Maintain these bits clear DS41262A page 172 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 14 0 SPECIAL FEATURES OF THE CPU The PIC16F685 687 689 690 have a host of features intended to maximize system reliability minimize cost through elimination of external components provide power saving features and offer code protection These features are e Reset Power on Reset POR Power up Timer PWRT Oscillator Start up Timer OST Brown out Reset BOR Interrupts e Watchdog Timer WDT Oscillator selection Sleep Code protection e ID Locations In Circuit Serial Programming The PIC16F685 687 689 690 have two timers that offer necessary delays on power up One is the Oscillator Start up Timer OST intended to keep the chip in Reset until the crystal oscillator is stable The other is the Power up Timer PWRT which provides a fixed delay of 64 ms nominal on power up only designed to keep the part in Reset while the power supply stabilizes There is also circuitry to reset the device if a brown out occurs which can use the Power up Timer to provide at least a 64 ms Reset With these three functions on chip most applications need no external Reset circuitry The Sleep mode is designed to offer a very low current Power down mode The user can wak
92. additional power savings by minimizing the latency between external oscillator start up and code execution In applications that make heavy use of the Sleep mode Two Speed Start up will remove the external oscillator start up time from the time spent awake and can reduce the overall power consumption of the device This mode allows the application to wake up from Sleep perform a few instructions using the INTOSC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable Note Executing a SLEEP instruction will abort the oscillator start up time and will cause the OSTS bit OSCCON lt 3 gt to remain clear When the PIC16F685 687 689 690 is configured for LP XT or HS modes the Oscillator Start up Timer OST is enabled see Section 3 3 1 Oscillator Start up Timer OST The OST timer will suspend program execution until 1024 oscillations are counted Two Speed Start up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting When the OST count reaches 1024 and the OSTS bit OSCCON lt 3 gt is set program execution switches to the external oscillator 3 6 1 TWO SPEED START UP MODE CONFIGURATION Two Speed Start up mode is configured by the following settings e IESO 1 CONFIG lt 105 Internal External Switchover bit e SCS 0 e FOSC configured for LP XT or HS mode Two Speed Start up mode is entered after P
93. amabe Comparator 2 Eu EUSART Receive EUSART Transmit Gs Fail Safe Clock Monitor ESCH In Circuit Serial Programming Connections Interrupt LOGIC ia tawi EEN dEN vg On Chip Reset Circuit eseseeseeseeeieereernerrerrrerrerereene PIC16F685 PIC16F687 689 PIC16F690 PWM Enhanced secssssecsseeseetseeseeessesseaeeosees 116 RAO Pi RA1 Pi RA2 Pi RAS Pi RA4 Pi RA5 Pi RB4 Pi RB5 Pi RB6 Pi RB7 Pi RC0 and Re len Bel 65 RC2 and RCS Pin AA 65 RC4 Pin RC5 Pin RC6 Pin RC7 Pin o Resonator Operation 37 SE RE Mole see wa ahaa 164 SSP SPI Mode 155 Timer wits RI TEE 78 TMRO WDT Prescaler 69 Watchdog Timer WDT 187 Break Character 12 bit Transmit and Receive 147 Brown out Reset BOR amazi 177 ee e EE 178 Specifications aeee 223 Timing and Characteristics eeeeeeeeeeee eneee 222 Cc C Compilers MPLAB Tee ii i ee 204 MPLAB 618 motio hontai etahi aa hia 204 MPLAB C30 irira n a 204 Capture Module See Enhanced Capture Compare PWM ECCP CCPICON Register CCPRTH Register CCPRIL Register AAA AA tin ions LEI SE Clock Accuracy with Asynchronous Operation H GM1CONO ege onna e CM2CONO Register CM2CON1 Register vssm amwnamanzanzwaamanzwanmaanzanzaaiaza Code Examples Assigning Prescaler to Time 71
94. and MPLAB C18 C Compilers MPLINK Object Linker MPLIB Object Librarian MPLAB C30 C Compiler MPLAB ASM30 Assembler Linker Library Simulators MPLAB SIM Software Simulator MPLAB dsPIC30 Software Simulator e Emulators MPLAB ICE 2000 In Circuit Emulator MPLAB ICE 4000 In Circuit Emulator In Circuit Debugger MPLAB ICD 2 e Device Programmers PRO MATER II Universal Device Programmer PICSTART Plus Development Programmer MPLAB PM3 Device Programmer Low Cost Demonstration Boards PICDEM M 1 Demonstration Board PICDEM net Demonstration Board PICDEM 2 Plus Demonstration Board PICDEM 3 Demonstration Board PICDEM 4 Demonstration Board PICDEM 17 Demonstration Board PICDEM 18R Demonstration Board PICDEM LIN Demonstration Board PICDEM USB Demonstration Board e Evaluation Kits KEELOQ Evaluation and Programming Tools PICDEM MSC microlD Developer Kits CAN PowerSmart Developer Kits Analog 16 1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8 16 bit micro controller market The MPLAB IDE is a Windows based application that contains An interface to debugging tools simulator programmer sold separately emulator sold separately in circuit debugger sold separately A full featured editor with color coded context A multiple project manager e Customizable data w
95. apply in Synchronous Master mode internally gener ated clock Given the desired baud rate and Fosc the nearest integer value for the SPBRGH SPBRG registers can be calculated using the formulas in Table 12 1 From this the error in baud rate can be determined An example calculation is shown in Example 12 1 Typical baud rates and error values for the various asynchronous modes are shown in Table 12 2 It may be advantageous to use the high baud rate BRGH 1 or the 16 bit BRG to reduce the baud rate error or achieve a slow baud rate for a fast oscillator frequency Writing a new value to the SPBRGH SPBRG registers causes the BRG timer to be reset or cleared This ensures the BRG does not wait for a timer overflow before outputting the new baud rate If the system clock is changed during an active receive operation a receive error or data loss may result To avoid this problem check the status of the RCIDL bit and make sure that the receive operation is IDLE before changing the system clock Note When BRGH 1 and BRG16 1 then 12 2 1 SAMPLING The data on the RB5 AN11 RX DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin EXAMPLE 12 1 CALCULATING BAUD RATE ERROR For a device with Fosc of 16 MHz desired baud rate of 9600 Asynchronous mode 8 bit BRG Fosc 64 SPBRGH SPBRG 1 Solving for SPBRGH SPBRG Desired Baud Rate FOSC
96. as Note Interrupt flag bits are set when an interrupt shown in Register 2 7 condition occurs regardless of the state of its corresponding enable bit or the global enable bit GIE INTCON lt 7 gt User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt REGISTER 2 7 PIR2 PERIPHERAL INTERRUPT REQUEST REGISTER 2 ADDRESS 0Dh R W 0 R W 0 R W 0 R W 0 U 0 U 0 U 0 U 0 OSFIF C2IF CIE EEIF bit 7 bit 0 bit 7 OSFIF Oscillator Fail Interrupt Flag bit 1 System oscillator failed clock input has changed to INTOSC must be cleared in software o System clock operating bit 6 C2IF Comparator 2 Interrupt Flag bit 1 Comparator output C2OUT bit has changed must be cleared in software 0 Comparator output C2OUT bit has not changed bit 5 C1IF Comparator 1 Interrupt Flag bit 1 Comparator output C1OUT bit has changed must be cleared in software o Comparator output C1OUT bit has not changed bit 4 EEIF EE Write Operation Interrupt Flag bit 1 Write operation completed must be cleared in software 0 Write operation has not completed or has not started bit 3 0 Unimplemented Read as oi Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown DS41262A page 30 Preliminary 2005 Microchip Techno
97. be read Control bits RD and WR initiate read and write respectively These bits cannot be cleared only set in software They are cleared in hardware at completion of the read or write operation The inability to clear the WR bit in software prevents the accidental premature termination of a write operation The WREN bit when set will allow a write operation to data EEPROM On power up the WREN bit is clear The WRERR bit is set when a write operation is interrupted by a MCLR or a WDT Time out Reset during normal operation In these situations following Reset the user can check the WRERR bit and rewrite the location The data and address will be unchanged in the EEDAT and EEADR registers Interrupt flag bit EEIF PIR2 lt 4 gt is set when write is complete It must be cleared in the software EECON2 is not a physical register Reading EECON2 will read all oe The EECON2 register is used exclusively in the data EEPROM write sequence 2005 Microchip Technology Inc Preliminary DS41262A page 105 PIC16F685 687 689 690 REGISTER 10 1 EEDAT EEPROM DATA REGISTER ADDRESS 10Ch R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDATO bit 7 bit 0 bit 7 0 EEDATn Byte value to Write to or Read from data EEPROM bits Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit i
98. configurable to function as one of the following a general purpose UO an analog input for the A D e a PWM output Note 1 PIC is available on PIC16F685 PIC16F690 only FIGURE 4 12 BLOCK DIAGRAM OF RC2 AND RC3 Data Bus CCPOUT Enable Analog Input Ei el To A D Converter Available on PIC16F685 PIC16F690 only Note 1 ANSEL determines Analog Input mode 2005 Microchip Technology Inc Preliminary DS41262A page 65 PIC16F685 687 689 690 4 5 5 RC4 C2OUT P1B The RC4 C20UT P1B 2 is configurable to function as one of the following a general purpose UO a digital output from Comparator 2 e a PWM output Note 1 Enabling both C2OUT and P1B will cause a conflict on RC4 and create unpredictable results Therefore if C2OUT is enabled the ECCP can not be used in Half bridge or Full bridge mode and vise versa 2 P1B is available on PIC16F685 PIC16F690 only FIGURE 4 13 BLOCK DIAGRAM OF RC4 C20UT EN CCPOUT EN C2OUT EN 4 20UT gt CCPOUT EN oho 2 Data Bus O Pin WR CK PORTET PX H ZE RD lt a PORTC Available on PIC16F685 PIC16F690 only 4 5 6 RC5 CCP1 P1A The RCS5 CCP1 P1A is configurable to function as one of the following a general purpose I O a digital input output for the Enhanced CCP e a PWM output Note 1 CCP1 a
99. delay is available to avoid shoot through current from destroying the bridge power switches The delay occurs at the signal transition from the non active state to the active state See Figure 11 6 for illustration The lower seven bits of the PWM1COM register Register 11 3 sets the delay period in terms of microcontroller instruction cycles TCY or 4 Tosc REGISTER 11 3 PWM1CON ENHANCED PWM CONFIGURATION REGISTER ADDRESS 1Ch R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDCO bit 7 bit 0 bit 7 PRSEN PWM Restart Enable bit 1 Upon auto shutdown the ECCPASE bit clears automatically once the shutdown event goes away the PWM restarts automatically 0 Upon auto shutdown ECCPASE must be cleared in software to restart the PWM bit 6 0 PDC lt 6 0 gt PWM Delay Count bits PDCn Number of Fosc 4 4 Tosc cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active Note 1 PIC16F685 PIC16F690 only Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown DS41262A page 126 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 11 3 8 ENHANCED PWM When a shutdown occurs the output pins are AUTO SHUTDOWN asynchronously placed in their shutdown states specified by
100. determines Analog Input mode 2005 Microchip Technology Inc Preliminary DS41262A page 59 PIC16F685 687 689 690 4 4 3 2 RB5 AN11 RX DT FIGURE 4 8 BLOCK DIAGRAM OF RB5 Figure 4 8 shows the diagram for this pin The RB5 Analogt AN11 RX DT pin is configurable to function as one Data Bus input Mode b VDD of the following WR CK 5 WPUB Px Q Weak a general purpose UO an analog input for the A D an asynchronous serial input RD lt 1 RABPU WPUB e asynchronous serial data I O SYNC Note 1 RX and DT are available on PIC16F687 SPER PIC16F689 PIC16F690 only Jio G SEH Vpp DTI O Pin TRISET PSS q vss Analog RD td nput Mode TRISE J RD PORTB oD IOCB EN LL a3 RD OCH Qa D Ve d sN aa EN nterrupt on fa Change bee RD PORTB To EUSART RX DT To A D Converter Available on PIC16F687 PIC16F689 PIC16F690 only Note 1 ANSEL determines Analog Input mode DS41262A page 60 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 4 4 3 3 RB6 SCK SCL FIGURE 4 9 BLOCK DIAGRAM OF RB6 Figure 4 9 shows the diagram for this pin The RB6 ne
101. enabled 0 Internal External Switchover mode is disabled bit 9 8 BOREN lt 1 0 gt Brown out Reset Selection bits 1 1 BOR enabled o BOR enabled during operation and disabled in Sleep 01 BOR controlled by SBOREN bit PCON lt 4 gt 00 BOR disabled bit 7 CPD Data Code Protection bit Data memory code protection is disabled 0 Data memory code protection is enabled bit 6 CP Code Protection bit 3 Program memory code protection is disabled 0 Program memory code protection is enabled bit 5 MCLRE RA3 MCLR VPP pin function select bit RA3 MCLR VPP pin function is MCLR 0 RA3 MCLR VPP pin function is digital input MCLR internally tied to VDD bit 4 PWRTE Power up Timer Enable bit PWRT disabled 0 PWRT enabled bit 3 WDTE Watchdog Timer Enable bit 1 WDT enabled 0 WDT disabled and can be enabled by SWDTEN bit WDTCON lt 0 gt bit 2 0 FOSC lt 2 0 gt Oscillator Selection bits SR 111 RC oscillator CLKOUT function on RA4 AN3 T1G OSC2 CLKOUT pin RC on RA5 T1CKI OSC1 CLKIN 110 RCIO oscillator I O function on RA4 AN3 T1G OSC2 CLKOUT pin RC on RA5 T1CKI OSC1 CLKIN 101 INTOSC oscillator CLKOUT function on RA4 AN3 T1G OSC2 CLKOUT pin I O function on RA5 T1CKI 0SC1 CLKIN Ee 100 INTOSCIO oscillator I O function on RA4 AN3 T1G 0SC2 CLKOUT pin I O function on RA5 TICKI OSCI CLKIN _ 011 EC I O function on RA4 AN3 T1G OSC2 CLKOUT pin CLKIN on RA5 T1CKI OSC1 CLKIN 010 HS oscillator
102. external VREF or VDD pin whichever is selected as reference input 3 When A D is off it will not consume any current other than leakage current The power down current specification includes any such leakage from the A D module O 2005 Microchip Technology Inc Preliminary DS41262A page 233 PIC16F685 687 689 690 FIGURE 17 17 Note 1 PIC16F685 687 689 690 A D CONVERSION TIMING NORMAL MODE BSF ADCONO coX 134 Tosc 2 1 131 m 1 Toy Q4 i E 180 e oo mu TLL LIL gf LLL A D Data ae EE 8 Ee E gt o A sn ADRES RR OLD DATA k KNEW DATA TT J 1 k ADIF cc Toy k JI 1 s E GO DONE Sampling Stopped Sample 132 SLEEP instruction to be executed 55 If the A D clock source is selected as RC a time of TCY is added before the A D clock starts This allows the 40 C lt TA lt 125 C TABLE 17 16 PIC16F685 687 689 690 A D CONVERSION REQUIREMENTS Standard Operating Conditions unless otherwise stated Operating Temperature Fe Sym Characteristic Min Typt Max Units Conditions 130 TaD A D Clock Period 1 5 us Tosc based VREF 2 2 5V 3 0 us Tosc based VREF full range 130 TaD A D Internal RC ADCS lt 1 0 gt 11 RC mode Oscillator Period 3 0 6 0 9 0 us At VDD 2 5V 2 0 4 0 6 0 us At Vpp 5 0V 131 TCNv Conve
103. f label SWAPF fd 0 lt f lt 127 de 0 1 f lt 3 0 gt destination lt 7 4 gt f lt 7 4 gt destination lt 3 0 gt None The upper and lower nibbles of register f are exchanged If d is o the result is placed in the W register If d is 1 the result is placed in register f Exclusive OR literal with W label XORLW k 0 lt k lt 255 W XOR k gt W 7 The contents of the W register are XOR ed with the eight bit literal k The result is placed in the W register Exclusive OR W with f label XORWF fd 0 lt f lt 127 de 0 1 W XOR f destination Z Exclusive OR the contents of the W register with register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f 2005 Microchip Technology Inc Preliminary DS41262A page 201 PIC16F685 687 689 690 NOTES I w w x w wwwwwwvwv vv x x wv www w wvwwwv avw vww wwwwvwx wv aww v w wwwvwwv vwwwwwvwww wv DS41262A page 202 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 16 0 DEVELOPMENT SUPPORT The PICmicro microcontrollers are supported with a full range of hardware and software development tools Integrated Development Environment MPLAB IDE Software e Assemblers Compilers Linkers MPASM Assembler MPLAB C17
104. handle error Yes continue BCF STATUS RP1 Bank 0 10 2 1 USING THE DATA EEPROM The data EEPROM is a high endurance byte addressable array that has been optimized for the storage of frequently changing information The maximum endurance for any EEPROM cell is specified as D120 and D120A D120 or D120A specify a maximum number of writes to any EEPROM location before a refresh is required of infrequently changing memory locations 10 2 2 EEPROM ENDURANCE A hypothetical data EEPROM is 64 bytes long and has an endurance of 1M writes It also has a refresh param eter of 10M writes If every memory location in the cell were written the maximum number of times the data EEPROM would fail after 64M write cycles If every memory location save one were written the maximum number of times the data EEPROM would fail after 63M write cycles but the one remaining location could fail after 10M cycles If proper refreshes occurred then the lone memory location would have to be refreshed six times for the data to remain correct 103 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory To protect against spurious EEPROM writes various mechanisms have been built in On power up WREN is cleared Also the Power up Timer 64ms duration prevents EEPROM write The write initiate sequence and the WREN bit together help prevent an accidental write during e Brown out
105. if the brown out circuit is disabled BOREN lt 1 0 gt 00 in the Configuration Word register Bit 1 is POR Power on Reset It is a o on Power on Reset and unaffected otherwise The user must write a 1 to this bit following a Power on Reset On a subsequent Reset if POR is o it will indicate that a Power on Reset has occurred e VDD may have gone too low ial ist hile Table 14 4 sh the Reset For more information see Section 4 2 3 Ultra SE Kee g a Se e SE Low Power Wake up and Section 14 2 4 SES Brown Out Reset BOR TABLE 14 1 TIME OUT IN VARIOUS SITUATIONS Power up Brown out Reset E Oscillator Configuration II III WEE PWRTE 0 PWRTE 1 PWRTE 0 PWRTE 1 eep XT HS LP TPWRT 1024 Tosc TPWRT 1024 Tosc 1024 e Tosc 1024 Tosc 1024 Tosc LP T1OSCIN 1 TPWRT TPWRT RC EC INTOSC TPWRT TPWRT TABLE 14 2 STATUS PCON BITS AND THEIR SIGNIFICANCE POR BOR TO PD Condition 0 u 1 1 Power on Reset 1 0 1 1 Brown out Reset u u 0 u WDT Reset u u 0 0 WDT Wake up u u u u MCLR Reset during normal operation u u 1 0 MCLR Reset during Sleep Legend u unchanged x unknown TABLE 14 3 SUMMARY OF REGISTERS ASSOCIATED WITH BROWN OUT Value on Addr Name Bit7 Bit6 Bit 5 Bit 4 Bits Bit2 Biti Bit 0 us all other Resets 03h 83h STATUS IRP RP1 RPO TO PD 7 DC Cc 0001
106. is busy enabling the SSP Interrupt will generate the interrupt when the Stop condition occurs In Multi Master operation the SDA line must be monitored to see if the signal level is the expected output level This check only needs to be done when a high level is output If a high level is expected and a low level is present the device needs to release the SDA and SCL lines set TRISB lt 6 4 gt There are two stages where this arbitration can be lost these are e Address Transfer e Data Transfer When the slave logic is enabled the slave continues to receive If arbitration was lost during the address transfer stage communication to the device may be in progress If addressed an ACK pulse will be generated If arbitration was lost during the data transfer stage the device will need to re transfer the data at a later time 13 14 1 CLOCK SYNCHRONIZATION AND THE CKP BIT When the CKP bit is cleared the SCL output is forced to 0 however setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low Therefore the CKP bit will not assert the SCL line until an external IC master device has already asserted the SCL line The SCL output will remain low until the CKP bit is set and all other devices on the DC bus have deasserted SCL This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL see Figure 13 12 2005 Microchip Technology Inc
107. is still full 4 ACK is not sent DS41262A page 166 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 13123 SSP MASK REGISTER An SSP Mask SSPMSK register is available in ke Slave mode as a mask for the value held in the SSPSR register during an address comparison operation A zero o bit in the SSPMSK register has the effect of making the corresponding bit in the SSPSR register a don t care This register is reset to all 1 s upon any Reset condition and therefore has no effect on standard SSP operation until written with a mask value REGISTER 13 3 This register must be initiated prior to setting SSPM lt 3 0 gt bits to select the IC Slave mode 7 bit or 10 bit address This register can only be accessed when the appropriate mode is selected by bits SSPM lt 3 0 gt of SSPCON The SSP Mask register is active during e 7 bit Address Mode address compare of A lt 7 1 gt e 10 bit Address Mode address compare of A lt 7 0 gt only The SSP mask has no effect during the reception of the first high byte of the address SSPMSK SSP MASK REGISTER ADDRESS 93h R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSKO bit 7 bit 0 bit 7 1 MSK lt 7 1 gt Mask bits 1 The received address bit n is compared to SSPADD lt n gt to detect DC address match 0 The received address bit n i
108. kHz The system clock speed can be selected via software using the Internal Oscillator Frequency Select IRCF bits The system clock can be selected between external or internal clock sources via the System Clock Selection SCS bit see Section 3 5 Clock Switching 3 4 1 INTOSC AND INTOSCIO MODES The INTOSC and INTOSCIO modes configure the internal oscillators as the system clock source when the device is programmed using the Oscillator Selec tion FOSC bits in the Configuration Word register Register 14 1 In INTOSC mode the OSC1 pin is available for general purpose I O The OSC2 CLKOUT pin outputs the selected internal oscillator frequency divided by 4 The CLKOUT signal may be used to provide a clock for external circuitry synchronization calibration test or other application requirements In INTOSCIO mode the OSC1 and OSC2 pins are available for general purpose I O 3 4 2 HFINTOSC The High Frequency Internal Oscillator HFINTOSC is a factory calibrated 8 MHz internal clock source The frequency of the HFINTOSC can be altered approximately 12 via software using the OSCTUNE register Register 3 1 The output of the HFINTOSC connects to a postscaler and multiplexer see Figure 3 1 One of seven frequencies can be selected via software using the IRCF bits see Section 3 4 4 Frequency Select Bits IRCF The HFINTOSC is enabled by selecting any freguency between 8 MHz and 125 kHz IRCF 000 as
109. kHz 011 500 kHz 100 1MHz 101 2 MHz 110 4 MHz default 111 8 MHz bit 3 OSTS Oscillator Start up Time out Status bit 1 Device is running from the external clock defined by FOSC lt 2 0 gt 0 Device is running from the internal oscillator HFINTOSC or LFINTOSC bit 2 HTS HFINTOSC High Frequency 8 MHz to 125 kHz Status bit 1 HFINTOSC is stable o HFINTOSC is not stable bit 1 LTS LFINTOSC Low Frequency 31 kHz Stable bit 1 LFINTOSC is stable o LFINTOSC is not stable bit 0 SCS System Clock Select bit 1 Internal oscillator is used for system clock 0 Clock source defined by FOSC lt 2 0 gt Note 1 Bit resets to 0 with Two Speed Start up and LP XT or HS selected as the Oscillator mode or Fail Safe mode is enabled Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown Val e on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR BOR 1 Resets OCh PIR1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR IF opp 0000 000 0000 8Ch PIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR IE 000 0000 000 0000 8Fh OSCCON IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS 110 x000 110 x000 90h OSCTUNE TUN4 TUN3 TUN2 TUN1 TUNO o 0000 u uuuu 2007h CONFIG CPD CP MCLRE PWRTE W
110. large memory devices and incorpo rates an SD MMC card for file storage and secure data applications 2005 Microchip Technology Inc Preliminary DS41262A page 205 PIC16F685 687 689 690 16 14 PICSTART Plus Development Programmer The PICSTART Plus development programmer is an easy to use low cost prototype programmer It con nects to the PC via a COM RS 232 port MPLAB Integrated Development Environment software makes using the programmer simple and efficient The PICSTART Plus development programmer supports most PICmicro devices up to 40 pins Larger pin count devices such as the PIC16C92X and PIC17C76X may be supported with an adapter socket The PICSTART Plus development programmer is CE compliant 16 15 PICDEM 1 PiCmicro Demonstration Board The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X PIC16C54 to PIC16C58A PIC16C61 PIC16C62X PIC16C71 PIC16C8X PIC17C42 PIC17C43 and PIC17C44 All necessary hardware and software is included to run basic demo programs The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device program mer or a PICSTART Plus development programmer The PICDEM 1 demonstration board can be connected to the MPLAB ICE in circuit emulator for testing A prototype area extends the circuitry for additional appli cation components Features include an RS 232 interface a potentiometer for simulated a
111. lt 3 0 gt allow one of the following DC modes to be selected I2C Slave mode 7 bit address I2C Slave mode 10 bit address I2C Slave mode 7 bit address with Start and Stop bit interrupts enabled to support Firmware Master mode I2C Slave mode 10 bit address with Start and Stop bit interrupts enabled to support Firmware Master mode I2C Start and Stop bit interrupts enabled to support Firmware Master mode Slave is idle Selection of any DC mode with the SSPEN bit set forces the SCL and SDA pins to be open drain provided these pins are programmed to inputs by setting the appropriate TRISB bits Pull up resistors must be provided externally to the SCL and SDA pins for proper operation of the DC module 13 12 Slave Mode In Slave mode the SCL and SDA pins must be configured as inputs TRISB lt 6 4 gt are set The SSP module will override the input state with the output data when required slave transmitter When an address is matched or the data transfer after an address match is received the hardware automatically will generate the Acknowledge ACK pulse and then load the SSPBUF register with the received value currently in the SSPSR register There are certain conditions that will cause the SSP module not to give this ACK pulse They include either or both a The buffer full bit BF SSPSTAT lt 0 gt was set before the transfer was received b The overflow bit SSPOV SSPCON lt 6 gt was set
112. module Clears the GO DONE bit Sets the ADIF flag PIR1 lt 6 gt Generates an interrupt if enabled If the conversion must be aborted the GO DONE bit can be cleared in software The ADRESH ADRESL registers will not be updated with the partially complete FIGURE 9 2 A D CONVERSION TaD CYCLES A D conversion sample Instead the ADRESH ADRESL registers will retain the value of the previous conversion After an aborted conversion a 2 TAD delay is required before another acquisition can be initiated Following the delay an input acquisition is automatically started on the selected channel The GO DONE bit should not be set in the same instruction that turns on the A D Note Tey to IAD TAD1 TAD2 TAD3 TAD4 TADS TAD6 TAD7 TAD8 TAD9 TAdio TAD t b9 b8 b7 b6 Conversion Starts Set GO DONE bit Holding Capacitor is Disconnected from Analog Input typically 100 ns ADRESH and ADRESL registers are loaded GO bit is cleared ADIF bit is set Holding capacitor is connected to analog input 9 1 6 CONVERSION OUTPUT The A D conversion can be supplied in two formats left or right justified The ADFM bit ADCONO lt 7 gt controls the output format Figure 9 3 shows the output formats FIGURE 9 3 10 BIT A D RESULT FORMAT ADRESH ADRESL ADFM 0 MSB LSB bit 7 bit 0 bit 7 bit 0 TI a 10 bit A D Result
113. of the SLEEP instruction bit 2 Z Zero bit 1 The result of an arithmetic or logic operation is zero 0 The result of an arithmetic or logic operation is not zero bit 1 DC Digit Carry Borrow bit ADDWF ADDLW SUBLW SUBWF instructions 1 Acarry out from the 4th low order bit of the result occurred 0 No carry out from the 4th low order bit of the result bit 0 C Carry Borrow bit ADDWF ADDLW SUBLW SUBWF instructions 1 A carry out from the Most Significant bit of the result occurred 0 No carry out from the Most Significant bit of the result occurred Note 1 For Borrow the polarity is reversed A subtraction is executed by adding the two s complement of the second operand For rotate RRF RLF instructions this bit is loaded with either the high or low order bit of the source register Legend R Readable bit n Value at POR W Writable bit 1 Bit is set U Unimplemented bit read as 0 0 Bit is cleared x Bit is unknown DS41262A page 24 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 2 2 2 2 OPTION Register The OPTION register is a readable and writable register which contains various control bits to configure e TMRO WDT prescaler Note To achieve a 1 1 prescaler assignment for TMRO assign the prescaler to the WDT by setting PSA bit to 1 OPTION REG lt 3 gt See Section 5 4 Prescaler e External RA2 INT interrupt
114. only 2005 Microchip Technology Inc Preliminary DS41262A page 93 PIC16F685 687 689 690 9 1 A D Configuration and Operation 9 1 3 VOLTAGE REFERENCE There are four registers available to control the There are two options for the voltage reference to the functionality of the A D module A D converter either VDD is used or an analog voltage applied to VREF is used The VCFG bit ADCONO lt 6 gt 1 ANSEL Register 9 1 controls the voltage reference selection If VCFG is set 2 ANSELH Register 9 2 then the voltage on the VREF pin is the reference 3 ADCONO Register 9 3 otherwise VDD is the reference EES Eet 9 1 4 CONVERSION CLOCK 9 1 1 ANALOG PORT PINS The A D conversion cycle requires 11 TAD The source The ANS lt 11 0 gt bits ANSEL lt 7 0 gt and of the conversion clock is software selectable via the ANSELH lt 3 0 gt and the TRISA lt 4 2 0 gt TRISB lt 5 4 gt ADCS bits ADCON1 lt 6 4 gt There are seven possible and TRISC lt 7 6 3 0 gt gt bits control the operation of the clock options A D port pins Set the corresponding TRISx bits to 1 to Fosc 2 set the pin output driver to its high impedance state Fosc 4 Likewise set the corresponding ANSx bit to disable the Fosc 8 digital input buffer e Fosc 16 BEEN Deem buffer to conduct excess current GE ji e FRC dedicated internal oscillator 9 1 2 CHANNEL SELECTION For correct conversion the A D conversion clock The
115. overflow sets the TOIF bit INTCON lt 2 gt The interrupt can be masked by clearing the TOIE bit INTCON lt 5 gt The TOIF bit must be cleared in software by the Timer0 module Interrupt Service Routine before re enabling this interrupt The TimerO interrupt cannot wake the processor from Sleep since the timer is shut off during Sleep rising edge FIGURE 5 1 BLOCK DIAGRAM OF THE TIMERO WDT PRESCALER CLKOUT Fosc 4 Data Bus 8 TOSE TOCS 8 bit Set Flag bit TOIF Prescaler PSA on Overflow 8 WDTE PSA SWDTEN PS lt 2 0 gt WDT 16 bit ey Time out Prescaler 16 31 kHz Watchdog INTOSC Timer PSA WDTPS lt 3 0 gt Note 1 TOSE TOCS PSA PS lt 2 0 gt are bits in the OPTION register WDTPS lt 3 0 gt are bits in the WDTCON register TMRO 2005 Microchip Technology Inc Preliminary DS41262A page 69 PIC16F685 687 689 690 5 3 Using Timer0 with an External Clock When no prescaler is used the external clock input is the same as the prescaler output The synchronization of TOCKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks Therefore it is necessary for TOCKI to be high for at least 2 Tosc and a small RC delay of 20 ns and low for at least 2 Tosc and a small RC delay of 20 ns Refer to_the electrical specification of the desire
116. page 5 PIC16F685 687 689 690 FIGURE 1 2 PIC16F687 PIC16F689 BLOCK DIAGRAM INT Configuration e 13 8 Data Bus PORTA K Program Counter K Flash RAO ANO C1IN ICSPDAT ULPWU 2k 1 4k x 14 RA1 AN1 C12IN VREF ICSPCLK Program RAM Ce RA2 AN2 TOCKI INT C1OUT MBirioty 8 Level Stack 13 bit 1280 256 bytes RA3 MCLR VPP File RA4 AN3 T1G OSC2 CLKOUT Registers RA5 T1CKI OSC1 CLKIN Program 14 Bus d RAM Addr 9 PORTB V Addr MUX Instruction Reg Direct Addr Indirect lt gt x RB4 AN10 SDI SDA Addr I l gt S RB5 AN11 RX DT Xl RB6 SCK SCL FSR Re 9 ES gt X RB7 TX CK r gt StatusReg KE PORTC ja RCO AN4 C2IN 3 e Sd RC1 AN5 C12IN V Power up ex RC2 AN6 Timer Rh Lee Ei RC3 AN7 Instruction gt Decode and k gt Oscillator RC4 C2OUT Control Start up Timer ALU X RC5 CCP1 ESTE X RC6 AN8 SS Ge e Ge 8 j RC7 AN9 SDO Timing V OSC2 CLKO Generation Kal Watchdog W Reg Timer Brown out Reset Interna Oscillator Block MCLR VDD Vss TX CK RX DT ee ee TOCKI TIG TICKI E x E i Synchronous Timer0 Timeri EUSART Serial Port AN8 AN9 AN10 AN11 AS dh i LS Analog To Digital Converter
117. the special event trigger sets the GO DONE bit starts a conversion If the A D module is not enabled ADON is cleared then the special event trigger will be ignored by the A D module but will still reset the Timer1 counter See Section 11 0 Enhanced Capture Compare PWM ECCP Module for more information set starting the A D conversion and the Timer1 counter TABLE 9 3 SUMMARY OF A D REGISTERS Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR Ster Resets 05h 105h PORTA RA5 RA4 RA3 RA2 RA1 RAO XX Xxxx uu uuuu 06h 106h PORTB RB7 RB6 RB5 RB4 xxxx uuuu 07h 107h_ PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RCO XXXX XxXxx uuuu uuuu OBh 8Bh INTCON GIE PEIE TOIE INTE RABIE TOIF INTF RABIF 0000 000x 0000 000x 10Bh 18Bh OCh PIR1 ADIF RCIF TKIF SSPIF CCP1IF TMR2IF TMRIIF 000 0000 000 0000 11Eh ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANSO 1211 1111 11Fh ANSELH ANS11 ANS10 ANS9 ANS8 1Eh ADRESH A D Result Register High Byte XXXX Xxxx UUUU uuuu 1Fh ADCONO ADFM VCFG CHS3 CHS2 CHS1 CHSO GO DONE ADON 0000 0000 0000 0000 85h 185h TRISA TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 11 11 86h 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 1111 87h 187h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 T
118. the system clock source SCS 1 or when Two Speed Start up is enabled IESO 1 and IRCF 000 The HF Internal Oscillator HTS bit OSCCON lt 2 gt indicates whether the HFINTOSC is stable or not DS41262A page 38 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 3 4 2 1 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register Register 3 1 The OSCTUNE register has a tuning range of 12 The default value of the OSCTUNE register is 0 The value is a 5 bit two s complement number Due to process variation the monotonicity and frequency step cannot be specified When the OSCTUNE register is modified the HFINTOSC frequency will begin shifting to the new frequency The HFINTOSC clock will stabilize within 1 ms Code execution continues during this shift There is no indication that the shift has occurred OSCTUNE does not affect the LFINTOSC frequency Operation of features that depend on the LFINTOSC clock source frequency such as the Power up Timer PWRT Watchdog Timer WDT Fail Safe Clock Monitor FSCM and peripherals are not affected by the change in frequency REGISTER 3 1 OSCTUNE OSCILLATOR TUNING RESISTOR ADDRESS 90h U 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 TUN4 TUN3 TUN2 TUN1 TUNO bit 7 bit 0 bit 7 5 Unimplemented Read as oi bit 4 0 TUN lt 4 0 gt F
119. the INTE control bit INTCON lt 4 gt The INTF bit must be cleared in software in the Interrupt Service Routine before re enabling this interrupt The RA2 INT interrupt can wake up the processor from Sleep if the INTE bit was set prior to going into Sleep The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake up 0004h See Section14 6 Power Down Mode Sleep for details on Sleep and Figure 14 9 for timing of wake up from Sleep through RA2 INT interrupt Note The ANSEL 11Eh and CM2CONO 11Ah registers must be initialized to configure an analog channel as a digital input Pins configured as analog inputs will read o 14 3 2 TMRO INTERRUPT An overflow FFh 00h in the TMRO register will set the TOIF INTCON lt 2 gt bit The interrupt can be enabled disabled by setting clearing TOIE INTCON lt 5 gt bit See Section 5 0 Timer0 Module for operation of the Timer0 module 2005 Microchip Technology Inc Preliminary DS41262A page 183 PIC16F685 687 689 690 14 3 3 PORTA PORTB INTERRUPT An input change on PORTA or PORTB change sets the RABIF INTCON lt 0 gt bit The interrupt can be enabled disabled by setting clearing the RABIE INTCON lt 3 gt bit Plus individual pins can be configured through the IOCA or IOCB registers Note Ifa change on the I O pin should occur when the read operation is being executed start of the Q
120. the PSSAC lt 3 2 gt and PSSBD lt 1 0 gt bits ECCPAS lt 3 0 gt Each pin pair P1A P1C and P1B P1D may be set to drive high drive low or be tri stated not driving The ECCPASE bit ECCPAS lt 7 gt is also set to hold the enhanced PWM outputs in their shutdown states The ECCPASE bit is set by hardware when a shutdown event occurs If Auto restarts are not enabled the ECCPASE bit is cleared by firmware when the cause of the shutdown clears If Auto restarts are enabled the ECCPASE bit is automatically cleared when the cause of the auto shutdown has cleared See Section 11 3 8 1 Auto shutdown and Auto restart for more information When the ECCP is programmed for any of the enhanced PWM modes the active output pins may be configured for auto shutdown Auto shutdown immediately places the enhanced PWM output pins into a defined shutdown state when a shutdown event occurs A shutdown event can be caused by either of the two comparators or the INT pin or any combination of these three sources The comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit If the voltage exceeds a threshold the comparator switches state and triggers a shutdown Alternatively a digital signal on the INT pin can also trigger a shutdown The auto shutdown feature can be disabled by not selecting any auto shut down sources The auto shutdown sources to be used are selected using the ECC
121. the various status conditions EXAMPLE 13 1 LOADING THE SSPBUF SSPSR REGISTER BSF STATUS RPO Bank 1 BCF STATUS RP1 LOOP BTFSS SSPSTAT BF Das data been received transmit complete GOTO LOOP No BCF STATUS RPO Bank 0 MOVF SSPBUF W WREG reg contents of SSPBUF MOVWF RXDATA Save in user RAM if data is meaningful MOVF TXDATA W W reg contents of TXDATA MOVWF SSPBUF New data to xmit DS41262A page 158 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 13 3 Enabling SPI UO To enable the serial port SSP Enable bit SSPEN SSPCON lt 5 gt must be set To reset or reconfigure SPI mode clear the SSPEN bit re initialize the SSPCON registers and then set the SSPEN bit This configures the SDI SDO SCK and SS pins as serial port pins For the pins to behave as the serial port function some must have their data direction bits in the TRISB and TRISC registers appropriately programmed That is SDI is automatically controlled by the SPI module SDO must have TRISC lt 7 gt bit cleared SCK Master mode must have TRISB lt 6 gt bit cleared SCK Slave mode must have TRISB lt 6 gt bit set SS must have TRISC lt 6 gt bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction TRISB and TRISC registers to the opposite value FIGURE 13 2 SPI Master SSPM lt 3 0 gt 00xxb SDO Serial Input Bu
122. to the EEADR and EEADRH registers set the EEPGD control bit EECON1 lt 7 gt and then set control bit RD EECON1 lt 0 gt Once the read control bit is set the program memory Flash controller will use the second instruction cycle to read the data This causes the second instruction immediately following the BsF EECON1 RD instruction to be ignored The data is available in the very next cycle in the EEDAT and EEDATH registers therefore it can be read as two bytes in the following instructions EXAMPLE 10 3 FLASH PROGRAM READ EEDAT and EEDATH registers will hold this value until another read or until it is written to by the user during a write operation Note 1 The two instructions following a program memory read are required to be NOP s This prevents the user from executing a two cycle instruction on the next instruction after the RD bit is set 2 If the WR bit is set when EEPGD 1 it will be immediately reset to o and no operation will take place BCF STATUS RPO Bank 2 BSF STATUS RP1 MOVLW MS PROG EE ADDR MOVWF EEADRH MOVLW LS PROG EE ADDR MOVWF EEADR MS Byte of Program Address to read LS Byte of Program Address to read BSF STATUS RPO Bank 3 BSF EECON1 EEPGD Point to PROGRAM memory ve BSF EECON1 RD EE Read 5 SS First instruction after BSF EECON1 RD executes normally TV NOP NOP Any instructions here are ignored as program memory is read in second cyc
123. 0 TABLE 11 5 PWM STEERING OPERATION WHEN CCP1M lt 3 2 gt 11 AND P1M lt 1 0 gt 00 CCP1CON REGISTER STRD STRC STRB STRA P1D P1C P1B P1A 0 0 0 0 Port Port Port Port 0 0 0 1 Port Port Port P1A 0 0 il 0 Port Port P1B Port 0 0 1 1 Port Port P1B P1A 0 1 0 0 Port P1C Port Port 0 1 0 1 Port P1C Port P1A 0 1 a 0 Port P1C P1B Port 0 1 1 1 Port P1C P1B P1A 1 0 0 0 P1D Port Port Port 1 0 0 1 P1D Port Port P1A 1 0 1 0 P1D Port P1B Port 1 0 1 1 P1D Port P1B P1A 1 1 0 0 P1D P1C Port Port 1 1 0 1 P1D P1C Port P1A 1 1 1 0 P1D P1C P1B Port 1 1 1 1 P1D P1C P1B P1A Note Port as described when NOT in PWM mode DS41262A page 124 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 11 3 6 1 Steering Synchronization The STRSYNC bit gives the user two selections of when the steering event will happen When the STRSYNC bit is o the steering event will happen at the end of the instruction that writes to the STRCON register In this case the output signal at the P1 lt D A gt pins may be an incomplete PWM waveform This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin FIGURE 11 12 STEERING EVENT AT END OF INSTRUCTION STRSYNC 0 When the STRSYNC bit is 1 the effective steering update will happen at the beginning of the next PWM period In this case steering on off th
124. 0 Channel 06 AN6 0111 Channel 07 AN7 1000 Channel 08 AN8 1001 Channel 09 AN9 1010 Channel 10 AN10 1011 Channel 11 AN11 1100 CVREF 1101 VP6 1110 Reserved Do not use 1111 Reserved Do not use bit 1 GO DONE A D Conversion Status bit 1 A D conversion cycle in progress Setting this bit starts an A D conversion cycle This bit is automatically cleared by hardware when the A D conversion has completed 0 A D conversion completed not in progress bit 0 ADON A D Enable bit 1 A D converter module is enabled 0 A D converter is shut off and consumes no operating current Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 97 PIC16F685 687 689 690 REGISTER 9 4 ADCON1 A D CONTROL REGISTER 1 ADDRESS 9Fh U 0 R W 0 RW0 RAN O U 0 U 0 U 0 U 0 ADCS2 ADCS1 ADCSO bit 7 bit 0 bit 7 Unimplemented Read as oi bit 6 4 ADCS lt 2 0 gt A D Conversion Clock Select bits 000 Fosc 2 001 Fosc 8 010 Fosc 32 x11 FRC clock derived from a dedicated internal oscillator 500 kHz max 100 Fosc 4 101 Fosc 16 110 Fosc 64 bit 3 0 Unimplemented Read as 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n
125. 0 No framing error OERR Overrun Error bit 1 Overrun error can be cleared by clearing bit CREN o No overrun error RX9D 9th bit of Received Data This can be address data bit or a parity bit and must be calculated by user firmware Note 1 PIC16F687 PIC16F689 PIC16F690 only Legend R Readable bit W Writable bit n Value at POR 1 Bit is set U Unimplemented bit read as 0 0 Bit is cleared X Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 133 PIC16F685 687 689 690 REGISTER 12 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BAUDCTL BAUD RATE CONTROL REGISTER ADDRESS 9Bh R 0 R 1 U 0 R W 0 R W 0 U 0 R W 0 R W 0 ABDOVF RCIDL SCKP BRG16 WUE ABDEN bit 7 bit 0 ABDOVF Auto Baud Detect Overflow bit Asynchronous mode 1 Auto baud timer overflowed 0 Auto baud timer did not overflow Synchronous mode Don t care RCIDL Receive IDLE Flag bit Asynchronous mode 1 Receiver is IDLE 0 Start bit has been received and the receiver is receiving Synchronous mode Don t care Unimplemented Read as 0 SCKP Synchronous Clock Polarity Select bit Asynchronous mode 1 Transmit inverted data to the RB7 TX CK pin 0 Transmit non inverted data to the RB7 TX CK pin Synchronous mode 1 Data is clocked on rising edge of the clock 0 Data is clocked on falling edge of t
126. 0 TBD uA 3 0 EC Oscillator mode 580 TBD uA 5 0 DO15E TBD TBD uA 2 0 Fosc 31 kHz TBD TBD UA 3 0 INTOSC mode TBD TBD mA 5 0 DO16E 340 TBD uA 2 0 Fosc 8 MHz 500 TBD uA 3 0 INTOSC mode 0 8 TBD mA 5 0 D017E 180 TBD uA 2 0 Fosc 4 MHz 320 TBD UA 3 0 EXTRC mode 580 TBD LA 5 0 DO18E 2 1 TBD mA 4 5 Fosc 20 MHz 24 TBD mA 5 0 HS Oscillator mode Legend TBD To Be Determined Data in Typ column is at 5 0V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all I O pins tri stated pulled to VDD MCLR VDD WDT disabled 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as 1 0 pin loading and switching rate oscillator type internal code execution pattern and temperature also have an impact on the current consumption 3 The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled The peripheral A current can be determined by subtracting the base IDD or IPD current from this limit Max values should be used when calculating total current consumption 4 The power down current in Sleep mode does not depend on the oscillator type Power down current is measured with the part in
127. 0 kHz mode 4 7 us Only relevant for setup time 400 kHz mode 0 6 us Repeated Start condition 91 THD STA Start condition hold 100 kHz mode 4 0 us After this period the first time 400 kHz mode 0 6 us clock pulse is generated 106 THD DAT Data input hold time 100 kHz mode 0 ns 400 kHz mode 0 0 9 HS 107 Tsu DAT Data input setup 100 kHz mode 250 ns Note 2 time 400 kHz mode 100 ns 925 Tsu sTo Stop condition 100 kHz mode 4 7 us setup time 400 kHz mode 0 6 us 109 TAA Output valid from 100 kHz mode 3500 ns Note 1 clock 400 kHz mode ns 110 TBUF Bus free time 100 kHz mode 4 7 us Time the bus must be free 400 kHz mode 1 3 gt us before a new transmission can start CB Bus capacitive loading 400 pF These parameters are characterized but not tested Note 1 Asa transmitter the device must provide this internal minimum delay time to bridge the undefined region min 300 ns of the falling edge of SCL to avoid unintended generation of Start or Stop conditions 2 A Fast mode 400 kHz DC bus device can be used in a Standard mode 100 kHz DC bus system but the requirement TSU DAT gt 250 ns must then be met This will automatically be the case if the device does not stretch the low period of the SCL signal If such a device does stretch the low period of the SCL signal it must output the next data bit to the SDA line TR max TSU DAT 1000 250 1250 ns according to the Standar
128. 00 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used by the Timer1 module DS41262A page 76 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 7 0 TIMER2 MODULE The Timer2 module timer has the following features e 8 bit timer TMR2 register e 8 bit period register PR2 Readable and writable both registers Software programmable prescaler 1 1 1 4 1 16 Software programmable postscaler 1 1 to 1 16 Interrupt on TMR2 match with PR2 Timer2 has a control register shown in Register 7 1 TMR2 can be shut off by clearing control bit TMR2ZON T2CON lt 2 gt to minimize power consumption Figure 7 1 is a simplified block diagram of the Timer2 module The prescaler and postscaler selection of Timer2 are controlled by this register 7 1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the ECCP module The TMR2 register is readable and writable and is cleared on any device Reset The input clock Fosc 4 has a prescale option of 1 1 1 4 or 1 16 selected by control bits T2CKPS lt 1 0 gt T2CON lt 1 0 gt The match output of TMR2 goes through a 4 bit postscaler which gives a 1 1 to 1 16 scaling inclusive to generate a TMR2 interrupt latched in flag bit TMR2IF PIR1 lt 1 gt The prescaler and postscaler counters are cleared when any of the following occurs A write to the TMR2 register Awrite to the T2
129. 1 Measurements are taken in RC mode where CLKOUT output is 4 x Tosc 2005 Microchip Technology Inc Preliminary DS41262A page 221 PIC16F685 687 689 690 FIGURE 17 5 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER AND POWER UP TIMER TIMING VDD beet g SES E EE i 30 Internal POR 2 33 _PWRT Time out 32 OSC s Time out Internal i se Reset i Watchdog o Timer Red O pins gt 5 FIGURE 17 6 BROWN OUT RESET TIMING AND CHARACTERISTICS VDD BVDD A Device not in Brown out Reset Device in Brown out Reset 35 gt Reset due to BOR 64 ms Time out 1 Note 1 64 ms delay only if PWRTE bit in the Configuration Word is programmed to o DS41262A page 222 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 TABLE 17 4 AND BROWN OUT RESET REGUIREMENTS RESET WATCHDOG TIMER OSCILLATOR START UP TIMER POWER UP TIMER Standard Operating Conditions unless otherwise stated Operating Temperature 40 C lt TA lt 125 C Se Sym Characteristic Min Typt Max Units Conditions 30 TMCL MCLR Pulse Width low 2 HS VDD 5V 40 C to 85 C 11 18 24 ms Extended temperature 31 Twpr Watchdog Timer Time out 7 18 33 ms VDD 5V 40 C to 85 C Period No Prescaler 10
130. 111 111 3 55 8 DS41262A page 138 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 12 2 2 AUTO BAUD DETECT The EUSART module supports the automatic detection and calibration of baud rate This feature is active only in Asynchronous mode and while the WUE bit is clear The automatic baud rate measurement sequence Figure 12 1 begins whenever a Start bit is received and the ABDEN bit is set The calculation is self averaging In the Auto Baud Detect ABD mode the clock to the BRG is reversed Rather than the BRG clocking the incoming RX signal the RX signal is timing the BRG In ABD mode the internal baud rate generator is used as a counter to time the bit period of the incoming serial byte stream If the BRG counter rolls over the ABDOVF BAUDCTL lt 7 gt and the RCIF bits are set to indicate BRG has overflowed The ABDOVF bit is set by hardware and can only be cleared by the user When an overflow occurs Auto baud Detect remains active and the ABDEN BAUDCTL lt 0 gt bit remains set The ABDOVF will remain set and not able to be cleared until the ABDEN is reset to o The RCIF must be cleared by reading the RCREG or clearing the SPEN bit Once the ABDEN bit is set the state machine will clear the BRG and look for a Start bit The Auto Baud Detect must receive a byte with the value 55h ASCII U which is also the LIN bus Sync character in order to calculate the
131. 14 RC2 AN6 RC6 AN8 SS lt gt 8 als RB4 AN10 SDI SDA RC7 AN9 SDO A 119 1211 lt gt RB5 AN11 RX DT RB7 TX CK lt 110 11 gt RB6 SCK SCL E sh VDD gt 111 a 20 Vss RA5 T1CKI OSC1 CLKIN 2 19 lt RAO ANO C1IN ICSPDAT ULPWU RA4 AN3 T1G OSC2 CLKOUT 3 18 lt RA1 AN1 C12IN VREF ICSPCLK RA3 MCLR VpP gt 4 S zs RA2 AN2 TOCKI INT C1OUT RC5 CCPI PIA gt 5 16 RCO AN4 C2IN RC4 C20UT P1B lt gt 116 5 IB RC1 AN5 C12IN RC3 AN7 P1C sl 14 lt gt RC2 AN6 P1D RC6 AN8 SS gt 178 13 RB4 AN10 SDI SDA RC7 AN9 SDO 19 12 RB5 AN11 RX DT RB7 TX CK a 110 11 RB6 SCK SCL DS41262A page 2 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 Pin Diagrams Continued 20 pin OFN 20 RA4 AN3 T1G OSC2 CLKOUT 19 RA5 T1CKI OSC1 CLKIN 16 _ RAO ANO C1IN ICSPDAT ULPWU a 0 a 0 gt gt O co N RA3 MCLR Vpp 1 15 I RA1 AN1 C12IN VREF ICSPCLK RC5 CCP1 P1A 1 _ 2 14 lt gt RA2 AN2 TOCKI INT C1OUT 1 PIC16F685 687 RC4 C2OUT PIBO sa w 3 689 690 13 I RCO AN4 C2IN RC3 AN7 P1C 1 4 42 lt gt RC1 AN5 C12IN RC6 AN8 SS 415 11 lt RC2 AN6 P1D 1 co N co o 2 mg aa a 9292525263 o gs H zs S eo Z E H e st m VV e x D c 4 9 O m lt L 2 cc cog 3 ao Note
132. 16 LCD display a piezo speaker an on board temperature sensor four LEDs and sample PIC18F452 and PIC16F877 Flash microcontrollers 16 18 PICDEM 3 PIC16C92X Demonstration Board The PICDEM 3 demonstration board supports the PIC16C923 and PIC16C924 in the PLCC package All the necessary hardware and software is included to run the demonstration programs 16 19 PICDEM 4 8 14 18 Pin Demonstration Board The PICDEM 4 can be used to demonstrate the capa bilities of the 8 14 and 18 pin PIC16XXXX and PIC18XXXX MCUs including the PIC16F818 819 PIC16F87 88 PIC16F62XA and the PIC18F1320 family of microcontrollers PICDEM 4 is intended to showcase the many features of these low pin count parts including LIN and Motor Control using ECCP Special provisions are made for low power operation with the supercapacitor circuit and jumpers allow on board hardware to be disabled to eliminate current draw in this mode Included on the demo board are pro visions for Crystal RC or Canned Oscillator modes a five volt regulator for use with a nine volt wall adapter or battery DB 9 RS 232 interface ICD connector for programming via ICSP and development with MPLAB ICD 2 2 x 16 liquid crystal display PCB footprints for H Bridge motor driver LIN transceiver and EEPROM Also included are header for expansion eight LEDs four potentiometers three push buttons and a proto typing area Included with the kit is a PIC16F627A and a PIC18F1320 Tutorial fi
133. 163 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip s PIC17CXXX and PIC18CXXX family of microcontrollers These compilers provide powerful integration capabilities superior code optimization and ease of use not found with other compilers For easy source level debugging the compilers provide symbol information that is optimized to the MPLAB IDE debugger 16 4 MPLINK Object Linker MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers It can link relocatable objects from precompiled libraries using directives from a linker script The MPLIB object librarian manages the creation and modification of library files of precompiled code When a routine from a library is called from a source file only the modules that contain that routine will be linked in with the application This allows large libraries to be used efficiently in many different applications The object linker library features include Efficient linking of single libraries instead of many smaller files e Enhanced code maintainability by grouping related modules together Flexible creation of libraries with easy module listing replacement deletion and extraction 16 5 MPLAB C30 C Compiler The MPLAB C30 C compiler is a full featured ANSI compliant optimizing compiler that tr
134. 2 cycle then the RABIF interrupt flag may not get set See Section 4 2 2 Interrupt on change for more information FIGURE 14 6 INTERRUPT LOGIC IOC RAO 4 IOCAO gt IOC RA1 4 IOCA1 IOC RA2 4 IOCA2 gt IOC RA3 IOCA3 SE SSPIF IOC RA43 IOCA4 E IOC RAS IOCAS e SE TMR2IF3 D TOIF TOE I gt Interrupt to CPU Wake up If in Sleep mode CCPI1IF 4 CCP1IE TMR2IE 1 IOC RB5 INE IOCB5 TMRIIF INTE __ TMR1IE RABIE IOC RB6 RABIE ED OSPR ele CIE E SE IOCB7 Car GIE ADIF DEAL EEIE gt EEIEA Note 1 Some peripherals depend upon the system clock for operation Since the system clock is suspended during Sleep these peripherals will not wake the part from Sleep See Section 14 6 1 Wake up from Sleep DS41262A page 184 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 FIGURE OSC1 snas E SR na 14 7 INT PIN INTERRUPT TIMING Q1 Q2 Q3 a4 01 Q2 Q3 04 Qt Q2 Q3 04 01 Q2 Q3 o4 Q1 Q2 Q3 04 ASAA NE NEP Va RENEE EN Nal NE NEE NE et NE APN INT pin Sd 1 1 T T y INTF flag eow im 5 Interrupt Latency 2 INTCON lt 1 gt is i 7 db i GIEbL I INTCON lt 7 gt i i r r 1 INSTRUCTION FLOW PC PC K PC i 3 PCI X 0004h X Donen Instruction
135. 3 572 6459 EUROPE Austria Weis Tel 43 7242 2244 399 Fax 43 7242 2244 393 Denmark Ballerup Tel 45 4450 2828 Fax 45 4485 2829 France Massy Tel 33 1 69 53 63 20 Fax 33 1 69 30 90 79 Germany Ismaning Tel 49 89 627 144 0 Fax 49 89 627 144 44 Italy Milan Tel 39 0331 742611 Fax 39 0331 466781 Netherlands Drunen Tel 31 416 690399 Fax 31 416 690340 England Berkshire Tel 44 118 921 5869 Fax 44 118 921 5820 03 01 05 Preliminary DS41262A page 256 2005 Microchip Technology Inc
136. 36 Preliminary O 2005 Microchip Technology Inc PIC16F685 687 689 690 18 0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs are not available at this time EEE ERRAR EAR EE a REAR ARRAES DE SO O 2005 Microchip Technology Inc Preliminary DS41262A page 237 PIC16F685 687 689 690 NOTES KEE EE EECH AN DS41262A page 238 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 19 0 PACKAGING INFORMATION 19 1 Package Marking Information 20 Lead PDIP Example XXXXXXXXXXXXXXXXX PIC16F685 I P ez XXXXXXXXXXXXXXXXX D AN 0510017 AS YYWWNNN 20 Lead SOIC 300 Example XXXXXXXXXXXXXX PIC16F685 I XXXXXXXXXXXXXX SO ez XXXXXXXXXXXXXX AN 0510017 E YYWWNNN a 20 Lead SSOP Example XXXXXXXXXXX PIC16F687 XXXXXXXXXXX V SSe3 AS YYWWNNN AS 0510017 O O 20 Lead QFN Example 2 e EN XXXXXXX 16F690 XXXXXXX I ML ei YYWWNNN 0510017 Legend XX X Customer specific information Y Year code last digit of calendar year YY Year code last 2 digits of calendar year WW Week code week of January 1 is week OI NNN Alphanumeric traceability code 3 Pb free JEDEC designator for Matte Tin Sn This package is Pb free The Pb free JEDEC designator ez can be found on the outer packaging for this package Note In the event the full Microchip part number cannot be marked on one line it will be carried o
137. 4 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 8 2 Comparator Outputs The comparator outputs are read through the CM1CON0 COM2CON0 or CM2CON1 registers CM1CONO and CM2CONO each contain the individual comparator output of Comparator 1 and Comparator 2 respectively CM2CON1 contains a mirror copy of both comparator outputs facilitating a simultaneous read of both comparators These bits are read only The comparator outputs may also be directly output to the RA2 AN2 TOCKI INT C10UT and RC4 C20UT P1B I O pins When enabled multiplexers in the output path of the RA2 AN2 TOCKI INT C1OUT and RC4 C20OUT P1B pins will switch and the output of each pin will be the unsynchronized output of the comparator The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications Figure 8 1 and Figure 8 2 show the output block diagrams for Comparators 1 and 2 respectively The TRIS bits will still function as an output enable disable for the RA2 AN2 TOCKI INT C1OUT and RC4 C2OUT P1B pins while in this mode The polarity of the comparator outputs can be changed using the C1POL and C2POL bits CMxCONO lt 4 gt Timer1 gate source can be configured to use the T1G pin or Comparator 2 output as selected by the T1GSS bit CM2CON1 lt 1 gt The Timer1 gate feature can be used to time the duration or interval of analog events The output of Comparator 2 c
138. 4h If GIE is clear the next instruction is executed If the A D interrupt is not enabled ADIE and PEIE bits set the A D module is turned off although the ADON bit remains set When the A D clock source is something other than RC a SLEEP instruction causes the present conversion to be aborted and the A D module is turned off The ADON bit remains set Full Scale Range A D Output Code I 1 LSB ideal 1 LSB ideal A A Zero Scale Transition A Full Scale Transition gt Analog Input Voltage A VREF DS41262A page 102 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 9 4 Effects of Reset A device Reset forces all registers to their Reset state Thus the A D module is turned off and any pending conversion is aborted The ADRESH ADRESL registers are unchanged 9 5 Use of the CCP Trigger An A D conversion can be started by the special event trigger of the CCP module This requires that the CCP1M lt 3 0 gt bits CCP1CON lt 3 0 gt be programmed as 1011 and that the A D module is enabled ADON bit is set When the trigger occurs the GO DONE bit will be will be reset to zero Timer1 is reset to automatically repeat the A D acquisition period with minimal software overhead moving the ADRESH ADRESL to the desired location The appropriate analog input channel must be selected and the minimum acquisition done before
139. 5 687 689 690 9 0 ANALOG TO DIGITAL CONVERTER A D MODULE The analog to digital converter A D allows conversion of an analog input signal to a 10 bit binary representation of that signal The PIC16F685 687 689 690 has twelve analog I O inputs plus two internal inputs multiplexed into one sample and hold circuit The output of the sample and hold is connected to the input of the converter The converter generates a binary result via successive approximation and stores the resulting or remaining 10 bits of data into ADRESL 9Eh and ADRESH 1Eh The voltage reference used in the conversion is software selectable to either VDD or a voltage applied by the VREF pin Figure 9 1 shows the block diagram of the A D on the PIC16F685 687 689 690 FIGURE 9 1 A D BLOCK DIAGRAM VREF VDD VCFG 0 e VCFG 1 RAO ANO C1IN ICSPDAT ULPWU RA1 AN1 C12IN VREF ICSPCLK RA2 AN2 TOCKI INT C1OUT RA4 AN3 T1G OSG2 CLKOUT RCO AN4 C2IN RC1 AN5 C121N1 RC2 AN6 P1D 2 RC3 AN7 P1C 2 RC6 AN8 SS RC7 AN9 SDO RB4 AN10 SDI SDA RB5 AN11 RX DT O CVREF VP6 Reference 13 RODADA a CHS lt 3 0 gt A D GO DONE ADON E Ves JL Note 1 When ADON 0 all input channels are disconnected from ADC no loading 2 P1C and P1D available on PIC16F685 PIC16F690 only 3 SS SDO SDA RX and DT available on PIC16F687 PIC16F689 PIC16F690
140. 5 EUSART Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit CSRC TXSTA lt 7 gt This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the RB7 TX CK pin instead of being supplied internally in Master mode This allows the device to transfer or receive data while in any Low power mode 12 5 1 EUSART SYNCHRONOUS SLAVE TRANSMIT The operation of the Synchronous Master and Slave modes are identical except in the case of the Sleep mode If two words are written to the TXREG and then the SLEEP instruction is executed the following will occur To set up a Synchronous Slave Transmission 1 Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC Clear bits CREN and SREN If interrupts are desired set enable bit TXIE If 9 bit transmission is desired set bit TX9 Enable the transmission by setting enable bit TXEN 6 If 9 bit transmission is selected the ninth bit should be loaded in bit TX9D 7 Load data to TXREG register 8 TXREG data will be transmitted synchronous to the master clock 9 If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON lt 7 6 gt are set aaron a The first word will immediately transfer to the TSR register b The second word will remain in TXREG register c Flag bit TXIF wil
141. 687 689 690 NOTES m wwwwwww wwww www wwv amp xv wwwv v w wwwwww aw vww www ww w wx wv xwww v w wwwvwwv vvwwwwvwwwwv v v DS41262A page 72 Preliminary 2005 Microchip Technology Inc PI C16F685 687 689 690 TIMER1 MODULE WITH GATE CONTROL The Timer1 module has the following features e 16 bit timer counter TMR1H TMR1L e Readable and writable Internal or external clock selection Synchronous or asynchronous operation Interrupt on overflow from FFFFh to 0000h Wake up upon overflow Asynchronous mode Optional external enable input Selectable gate source T1G or C2 output TIGSS Selectable gate polarity T1GINV Optional LP oscillator 6 0 FIGURE 6 1 TIMER1 BLOCK DIAGRAM Figure 6 1 shows the block diagram of the Timert module The Timer1 Control register T1CON shown in Register 6 1 is used to enable disable Timert and select the various features of the Timer1 module osc2 T1G X Set flag bit TMRIIF on To C2 Comparator Module Overflow 1 TMR1 Clock if TMR1 Synchronized TMRIH TMRIL i clock input E KEE TISYNC oscimicki D Prescaler Synchronize FOSC 000 TIOSCEN T1CKI gt x Note 1 Timer1 register increments on rising edge TICS T1OSCEN Le ST Buffer is low power type when using LP osc or high speed type when using T1CKI
142. 689 690 12 5 2 EUSART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception RECEPTION 1 Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits SYNC and SPEN and clearing bit modes is identical except in the case of Sleep or any CSRC IDLE mode and bit SREN which is a don t care in 2 lf interrupts are desired set enable bit RCIE Slave mode 3 If 9 bit reception is desired set bit RX9 If receive is enabled by setting the CREN bit prior to 4 To enable reception set enable bit CREN entering Sleep then a word may be received Once the 5 Flag bit RCIF will be set when reception is word is received the RSR register will transfer the data complete An interrupt will be generated if to the RCREG register if the RCIE enable bit is set the enable bit RCIE was set interrupt generated will wake the chip from Sleep If the 6 Read the RCSTA register to get the 9th bit if global interrupt is enabled the program will branch to enabled and determine if any error occurred the interrupt vector during reception 7 Read the 8 bit received data by reading the RCREG register 8 lf any error occurred clear the error by clearing bit CREN 9 Ifusing interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON lt 7 6 gt are set TABLE 12 10 REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
143. 90 17 5 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats 1 TppS2ppS 2 TppS T F Freguency T Time Lowercase letters pp and their meanings pp cc RC osc OSC1 ck CLKOUT rd RD cs cs rw RD or WR di SDI sc SCK do SDO ss ss dt Data in t0 TOCKI io I O port ti T1CKI mc MCLR wr WR Uppercase letters and their meanings S F Fall P Period H High R Rise I Invalid High impedance V Valid L Low Z High impedance FIGURE 17 2 LOAD CONDITIONS Load Condition 1 VDD 2 OC e Pin CL vss RL 46040 CL 50pF forall pins 15pF for OSC2 output Pin Load Condition 2 DS41262A page 218 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 17 6 AC Characteristics PIC16F685 687 689 690 Industrial Extended FIGURE 17 3 EXTERNAL CLOCK TIMING a4 i at o a3 a4 ai i i i l OSC1 IRE a Er e NL Ee ki e E 2 gt CLKOUT TABLE 17 1 EKTERNAL CLOCK TIMING REGUIREMENTS Standard Operating Conditions unless otherwise stated Operating Temperature 40 C lt TA lt 125 C ZI Sym Characteristic Min Typt Max Units Conditions Fosc External CLKIN Frequency DC 37 kHz LP Oscillator mode DC 4 MHz XT Oscillator mode DC 20 MHz HS Oscillator mode DC 20 MHz EC Oscillator mode Oscillator Frequency 8 MHz INTOSC Oscillator mode T
144. ATUS RP1 CLRWDT Clear WDT CLRF TMRO Clear TMRO and prescaler BSF STATUS RPO Bank 1 MOVLW b 00101111 Required if desired MOVWF OPTION REG PS lt 2 0 gt is CLRWDT 7000 or 001 Set postscaler to desired WDT rate Bank 0 MOVLW b 00101xxx MOVWF OPTION REG BCF STATUS RPO To change prescaler from the WDT to the TMRO module use the sequence shown in Example 5 2 This precaution must be taken even if the WDT is disabled EXAMPLE 5 2 CHANGING PRESCALER WDT TIMERO Clear WDT and prescaler BSF STATUS RPO Bank 1 BCF STATUS RP1 H MOVLW b xxxx0xxx Select TMRO prescale and clock source MOVWF OPTION_REG BCF STATUS RPO Bank 0 CLRWDT TABLE 5 1 REGISTERS ASSOCIATED WITH TIMERO val Address Name Bit7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 POR FOR all other 01h 101h TMRO TimerO Module Register XXXX XXXX uuuu uuuu OBh 8Bh INTCON GIE PEIE TOIE INTE RABIE TOIF INTF RABIF 0000 000x 0000 000x 10Bh 18Bh 81h 181h OPTION REG RABPU INTEDG TOCS TOSE PSA PS2 PS1 PSO 1111 1111 1111 1111 85h 185h TRISA TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 11 1111 11 1111 Legend Unimplemented locations read as 0 u unchanged x unknown Shaded cells are not used by the Timer0 module 2005 Microchip Technology Inc Preliminary DS41262A page 71 PIC16F685
145. Always verify oscillator performance over the VDD and temperature range that is expected for the application FIGURE 3 4 CERAMIC RESONATOR OPERATION XT OR HS MODE PIC16F685 687 689 690 Es CC e C1 To Internal ahs Sa logic E iS pp i Re Ne Sleep E osc2 ts rs Le C2 Ceramic Resonator Note 1 A series resistor RS may be reguired for ceramic resonators with low drive level 2 The value of RF varies with the Oscillator mode selected typically between 2 MA to 10 MO 3 An additional parallel feedback resistor RP may be reguired for proper ceramic resonator operation typical value 1 MO 2005 Microchip Technology Inc Preliminary DS41262A page 37 PIC16F685 687 689 690 3 3 4 EXTERNAL RC MODES The External Resistor Capacitor RC modes support the use of an external RC circuit This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required There are two modes RC and RCIO In RC mode the RC circuit connects to the OSC1 pin The OSC2 CLKOUT pin outputs the RC oscillator frequency divided by 4 This signal may be used to provide a clock for external circuitry synchronization calibration test or other application requirements Figure 3 5 shows the RC mode connections FIGURE 3 5 RC MODE Vo RextS DD l Internal OSC1 l e
146. Assigning Prescaler to WDT Changing Between Capture Prescalers 114 Indirect Addressing s eessseersesieeieerrerinsrrerrerresrrereens 32 Initializing A D Initializing PORTA Initializing PORTB Initializing PORTC e Loading the SSPBUF SSPSR Register Saving Status and W Registers in RAM n se Ultra Low Power Wake up Initialization vz Write Verity EE Code Protection sisser diare itakaa Comparator Module a C1 Output State Versus Input Conditions C2 Output State Versus Input Conditions Comparator Voltage Reference CVREF Ve Accuracy Error Associated registers Configuring Effects of a Reset Response Time Gs Specifications asma patente el EE ag Comparators Associated Registers C2OUT as T1 Gate Effects of a Reset Operation During Sleep i Response Time icseeeeeereeeeeseeseessseseesseeeesseessessess SPEECH CHOMA AA 2005 Microchip Technology Inc Preliminary DS41262A page 247 PIC16F685 687 689 690 Compare Module See Enhanced Capture Compare PWM ECCP CONFIG Register 174 Configuration Dit 174 CPU Fealtiives e geseet ege de 173 Customer Change Notification Service 253 Customer Notification Service 253 Customer SUpport tea 253 D D A ia sito a seo Bo saia ao nein a E 156 Data EEPROM
147. BD 4 MHz RC Oscillator mode 32 kHz LP Oscillator mode 0 1 4 MHz XT Oscillator mode 1 20 MHz HS Oscillator mode 1 Tosc External CLKIN Period 27 co us LP Oscillator mode 50 co ns HS Oscillator mode 50 co ns EC Oscillator mode 250 co ns KT Oscillator mode Oscillator Period 31 us LP Oscillator mode 125 ns INTOSC Oscillator mode 250 TBD ns RC Oscillator mode 250 10 000 ns KT Oscillator mode 50 1 000 ns HS Oscillator mode 2 Tcy Instruction Cycle Time 200 Tey co ns Tcy 4 Fosc 3 TosL External CLKIN OSCH High 2 us LP oscillator Tosc L H duty cycle TosH External CLKIN Low 20 SS ns HS oscillator Tosc L H duty cycle 100 ns XT oscillator Tosc L H duty cycle 4 TosR External CLKIN Rise 50 ns LP oscillator TosF External CLKIN Fall 25 ns XT oscillator 15 ns HS oscillator Legend TBD To Be Determined These parameters are characterized but not tested Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 Instruction cycle period TCY eguals four times the input oscillator time base period All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code Exceeding these specified limits may result in an
148. C16F685 PIC16F690 only DS41262A page 130 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 12 0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER EUSART The Enhanced Universal Synchronous Asynchronous Receiver Transmitter EUSART module is the serial I O module available for PIC16F685 687 689 690 EUSART is also known as a Serial Communications Interface or SCI The EUSART can be configured in full duplex Asynchronous mode that can communicate with peripheral devices such as CRT terminals and personal computers or it can also be configured as a half duplex Synchronous mode which can communicate with peripheral devices such as A D or D A integrated circuits serial EEPROMs etc The EUSART module implements additional features including automatic baud rate detection and calibration automatic wake up on Break reception and 13 bit Break character transmit These features make the EUSART ideally suited for use in Local Interconnect Network LIN bus systems The EUSART can be configured in the following modes Asynchronous full duplex with Auto wake up on Break Auto baud calibration 13 bit Break character transmission Synchronous Master half duplex with selectable clock polarity e Synchronous Slave half duplex with selectable clock polarity In order to configure pins RB6 SCK SCL and RB7 TX CK as the Universal Synchronous Asynchronous Receiver
149. CCP1CON register will force the RC5 CCP1 P1A compare output latch to the default low level This is not the PORTC HO data latch 11 2 2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchronized Counter mode if the ECCP module is using the compare feature In Asynchronous Counter mode the compare operation may not work 11 2 3 SOFTWARE INTERRUPT MODE When Generate Software Interrupt mode is chosen CCP1M lt 3 0 gt 1010 the CCP1 pin is not affected The CCP1IF PIR1 lt 2 gt bit is set causing a ECCP interrupt if enabled See Register 11 1 11 2 4 SPECIAL EVENT TRIGGER In this mode CCP1M lt 3 0 gt 1011 an internal hardware trigger is generated which may be used to initiate an action See Register 11 1 The special event trigger output of the CCP occurs immediately upon a match between the TMR1H TMRI1L register pair and CCPR1H CCPR1L register pair The TMR1H TMRIL register pair is not reset until the next rising edge of the TMR1 clock This allows the CCPR1H CCPRIL register pair to effectively provide a 16 bit programmable period register for Timer1 The special event trigger output also starts an A D conversion provided that the A D module is enabled Note 1 The special event trigger from the CCP module will not set interrupt flag bit TMR1IF PIR1 lt 0 gt 2 Removing the match condition by changing the contents of the CCPR1H and CCPRI1L register pair between the clock edge that ge
150. CK 5 RD lt L RABPU WAUA Oscillator 4 Circuit OSC1 CLKOUT SE Enable Fosc 4 D Q WR CK O Pin PORTA PY Q 1 CLKOUT Enable e R Vss SD Q A WR RC EC GES SK q CLKOUT Ro Esc Enable TRISA Analog nput Mode RD te PORTA WR 0 Dre IOCA EN Q3 RD lt IOCA Q D EN Interrupt on Change RD PORTA To T1G To A D Converter Note 1 CLK modes are XT HS LP LPTMR1 and CLKOUT Enable 2 With CLKOUT option 3 ANSEL determines Analog Input mode 2005 Microchip Technology Inc Preliminary DS41262A page 53 PIC16F685 687 689 690 4 2 4 6 RA5 T1CKI OSC1 CLKIN Figure 4 6 shows the diagram for this pin The RA5 T1CKI OSC1 CLKIN pin is configurable to function as one of the following a general purpose UO e a TMR1 clock input a crystal resonator connection e a clock input FIGURE 4 6 BLOCK DIAGRAM OF RA5 INTOSC Mode TMR1LPEN Data Bus 5 o Von WR yCK 5 a Weak wPUATP H ro GE WPUA Circuit OSCH e D Q ype WR CK gt PORTATP X Q vr VO Pin e D Q e WR TRISATP SS a Vss INTOSC RD 4 Mode TRISA Z 2 RD PORTA d D q oca EN a3 ap Lee IOCA Q D a EN Interrupt on f Change RD PORTA 4 To TMR1 or CLKGEN Note 1 Timeri LP Oscillator enabled 2 Whe
151. CON register Any device Reset Power on Reset MCLR Reset Watchdog Timer Reset or Brown out Reset TMR2 is not cleared when T2CON is written T2CON TIMER2 CONTROL REGISTER ADDRESS 12h R W 0 R W 0 R W 0 R W 0 R W 0 rouress roue TOUTS TOUTPSO TRZON T2CKPST T2CKPSO REGISTER 7 1 U 0 R W 0 R W 0 bit 7 bit 7 Unimplemented Read as oi bit 0 bit 6 3 TOUTPS lt 3 0 gt Timer2 Output Postscale Select bits 0000 1 1 postscale 0001 1 2 postscale 1111 1 16 postscale bit 2 TMR2ON Timer2 On bit 1 Timer2 is on 0 Timer2 is off bit 1 0 T2CKPS lt 1 0 gt Timer2 Clock Prescale Select bits 00 Prescaler is 1 01 Prescaler is 4 1x Prescaler is 16 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 77 PIC16F685 687 689 690 7 2 Timer2 Interrupt The Timer2 module has an 8 bit period register PR2 Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle PR2 is a readable and writable register The PR2 register is initialized to FFh upon Reset FIGURE 7 1 TIMER2 BLOCK DIAGRAM Sets Flag TMBe bit TMR2IF Output A Fosc 4 Prescaler Tops 1 1 1 4 1 16 2 V Po
152. Clear ADIF bit PIR1 lt 6 gt Pw Ro OR d BTFSC ADCONO GO Is conversion done e Set ADIE bit PIE1 lt 6 gt coro 1 No t st again e Set PEIE and GIE bits INTCON lt 7 6 gt MOVF ADRESH W Read upper 2 bits 3 Wait the required acquisition time MORE RESULIHA 4 Start SOA BSF STATUS RPO Bank 1 i Ar CONVETSION MOVF ADRESL W Read lower 8 bits e Set GO DONE bit ADCONO lt 1 gt BCF STATUS RPO Bank 0 5 Wait for A D conversion to complete by either MOVWF RESULTLO Polling for the GO DONE bit to be cleared with interrupts disabled OR e Waiting for the A D interrupt 6 Read A D Result register pair ADRESH ADRESL clear bit ADIF if required 7 For next conversion go to step 1 or step 2 as required The A D conversion time per bit is defined as TAD A minimum wait of 2 TAD is required before the next acquisition starts 2005 Microchip Technology Inc Preliminary DS41262A page 99 PIC16F685 687 689 690 9 2 A D Acguisition Reguirements To calculate the minimum acquisition time ji H Eguation 9 1 may be used This eguation assumes that For the A D converter to meet its specified accuracy the 1 2 LSb error is used 1024 steps for the A D The 1 2 charge holding capacitor CHOLD must be allowed to LSb error is the maximum error allowed for the A D to fully charge to the input channel voltage level The meet its specified resolution analog input model is shown in Figure 9 4 The source impedance RS
153. D gt Clock ENT ze e Vss PIC16F685 687 689 690 a 0SC2 CLKOUT Fosc 4 Recommended values 3 kQ lt REXT lt 100 kQ CEXT gt 20 pF In RCIO mode the RC circuit is connected to the OSC1 pin The OSC2 pin becomes an additional general purpose I O pin The I O pin becomes bit 4 of PORTA RA4 Figure 3 6 shows the RCIO mode connections FIGURE 3 6 RCIO MODE Vo Rext OSCH Internal e D gt Clock CEXT eel Vss Ei PIC16F685 687 689 690 RA4 UO OSC2 Recommended values 3 kQ lt RExT lt 100 kQ CEXT gt 20 pF The RC oscillator frequency is a function of the supply voltage the resistor REXT and capacitor CEXT values and the operating temperature Other factors affecting the oscillator frequency are threshold voltage variation component tolerances packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used 3 4 Internal Clock Modes The PIC16F685 687 689 690 has two independent internal oscillators that can be configured or selected as the system clock source 1 The HFINTOSC High Frequency Internal Oscillator is factory calibrated and operates at 8 MHz The frequency of the HFINTOSC can be user adjusted 12 via software using the OSCTUNE register Register 3 1 2 The LFINTOSC Low Frequency Internal Oscillator is uncalibrated and operates at approximately 31
154. DTE FOSC2 FOSC1 FOSCO Legend x unknown u unchanged unimplemented locations read as o Shaded cells are not used by oscillators Note 1 Other non Power up Resets include MCLR Reset and Watchdog Timer Reset during normal operation 2 See Register 14 1 for operation of all Configuration Word register bits 2005 Microchip Technology Inc Preliminary DS41262A page 45 PIC16F685 687 689 690 NOTES EAR ARA RE a i a a EE EEE EE DS41262A page 46 Preliminary O 2005 Microchip Technology Inc PIC16F685 687 689 690 4 0 1 0 PORTS There are as many as eighteen general purpose I O pins available Depending on which peripherals are enabled some or all of the pins may not be available as general purpose I O In general when a peripheral is enabled the associated pin may not be used as a general purpose I O pin 4 1 PORTA and the TRISA Registers PORTA is a 6 bit wide bidirectional port The corresponding data direction register is TRISA Register 4 2 Setting a TRISA bit 1 will make the corresponding PORTA pin an input e put the corresponding output driver in a High impedance mode Clearing a TRISA bit 0 will make the corresponding PORTA pin an output e put the contents of the output latch on the selected pin The exception is RA3 which is input only and its TRIS bit will always read as 1 Example 4 1 shows how to initialize PORTA Reading the PORTA register Register 4 1 reads the
155. E TxIE SSPIE CCP1IE TMR2IE TMRIIE bit 7 bit O bit 7 Unimplemented Read as oi bit 6 ADIE A D Converter Interrupt Enable bit 1 Enabled 0 Disabled bit 5 RCIE EUSART Receive Interrupt Enable bit 1 Enabled o Disabled bit 4 TXIE EUSART Transmit Interrupt Enable bit 1 Enabled 0 Disabled bit 3 SSPIE Synchronous Serial Port SSP Interrupt Enable bit 2 1 Enabled 0 Disabled bit 2 CCP1IE CCP1 Interrupt Enable bit 1 Enabled 0 Disabled bit 1 TMR2IE TMR2 to PR2 Match Interrupt Enable bit 1 Enabled o Disabled bit 0 TMRI1IE TMR1 Overflow Interrupt Enable bit 1 Enabled 0 Disabled Note 1 PIC16F685 PIC16F690 only 2 PIC16F687 PIC16F689 PIC16F690 only Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 27 PIC16F685 687 689 690 2 2 2 5 PIE2 Register The PIE2 register contains the interrupt enable bits as Note Bit PEIE INTCON lt 6 gt must be set to shown in Register 2 5 enable any peripheral interrupt REGISTER 2 5 PIE2 PERIPHERAL INTERRUPT ENABLE REGISTER 2 ADDRESS 8Dh R W 0 R W 0 R W 0 R W 0 U 0 U 0 U 0 U 0 OSFIE C2IE CHE EEIE bit 7 bit O bit 7 OSFIE Oscillator Fail Interrupt Enable bit 1 Enabled 0 Disabled bit 6 C2IE
156. E bit must also be set If any of these bits are cleared the interrupt is not enabled though the CxIF bits will still be set if an interrupt condition occurs The comparator interrupt of the PIC16F685 687 689 690 differs from previous designs in that the interrupt flag is set by the mismatch edge and not the mismatch level This means that the interrupt flag can be reset without the additional step of reading or writing the CMxCONO register to clear the mismatch registers When the mismatch registers are not cleared an interrupt will not occur when the comparator output returns to the previous state When the mismatch registers are cleared an interrupt will occur when the comparator returns to the previous state Note 1 If a change in the CMxCONO register CxOUT should occur when a read Operation is being executed start of the Q2 cycle then the CxIF PIR2 lt 5 6 gt interrupt flag may not get set 2 When either comparator is first enabled bias circuitry in the comparator module may cause an invalid output from the comparator until the bias circuitry is sta ble Allow about 1 us for bias settling then clear the mismatch condition and inter rupt flags before enabling comparator interrupts 2005 Microchip Technology Inc Preliminary DS41262A page 85 PIC16F685 687 689 690 8 3 SR Latch Output An SR latch is connected to the comparator outputs C1OUT and C2OUT Upon any Reset the SR latch is alw
157. ECCPAS values without regard to CCP1M lt 3 0 gt An Auto Shutdown event will only affect pins that have PWM outputs enabled PSTRCON PULSE STEERING CONTROL REGISTER 2 ADDRESS 19Dh U 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 1 STRSYNC STRD STRC STRB STRA bit 7 bit 0 Unimplemented Read as 0 STRSYNC Steering Sync bit 1 Output steering update occurs on next PWM period 0 Output steering update occurs at the beginning of the instruction cycle boundary STRD Steering Enable bit D 1 P1D pin has the PWM waveform with polarity control from CCPM lt 1 0 gt 0 P1D pin is assigned to port pin STRC Steering Enable bit C 1 P1C pin has the PWM waveform with polarity control from CCPM lt 1 0 gt 0 P1C pin is assigned to port pin STRB Steering Enable bit B 1 P1B pin has the PWM waveform with polarity control from CCPM lt 1 0 gt 0 P1B pin is assigned to port pin STRA Steering Enable bit A 1 PIA pin has the PWM waveform with polarity control from CCPM lt 1 0 gt 0 P1A pin is assigned to port pin Note 1 PIC16F685 PIC16F690 only 2 The PWM Steering is available only when the CCP1M lt 3 2 gt 11 and P1M lt 1 0 gt 00 CCP1CON register Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 123 PIC16F685 687 689 69
158. EDG TOCS TOSE PSA PS2 PS1 PSO 111 122 111 RELA 82h PCL Program Counter s PC Least Significant Byte 0000 0000 0000 0000 83h STATUS IRP RP1 RPO TO PD Z DC C 0001 1xxx 000g guuu 84h FSR Indirect Data Memory Address Pointer XXXX XXXX uuuu uuuu 85h TRISA TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 1 111 11 1111 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 1111 87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISCO 111 111 1111 1111 88h Unimplemented 89h Unimplemented 8Ah PCLATH Write Buffer for the upper 5 bits of the Program Counter 0 0000 0 0000 8Bh INTCON GIE PEIE TOIE INTE RABIE TOIF INTF RABIF 0000 ooox 0000 000x 8Ch PIE1 ADIE RCIE TXIE SSPIE CCP11E TMR2IE TMRIIE 000 0000 000 0000 8Dh PIE2 OSFIE C2IE C1IE EEIE 0000 0000 8Eh PCON ULPWUE SBOREN POR BOR 01 qq 0u uu 8Fh OSCCON IRCF2 IRCF1 IRCFO OSTS HTS LTS SCS 110 q000 110 x000 90h OSCTUNE TUN4 TUN3 TUN2 TUN1 TUNO 0 0000 u uuuu 9th Unimplemented 92h PR2 4 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port C mode Address Register 0000 0000 0000 0000 93h SSPMSK8 9 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSKO 1111 1111 1111 1111 94h SSPSTAT SMP CKE D A P s R W UA BF 0000 0000 0000 0000 95h WPUAG WPUA5 WPUA4 WPUA2 WPUA1
159. F SsPIF CCP1IF TMR2IF TMRIIF 000 0000 000 0000 ODh PIR2 OSFIF C2IF C1IF EEIF 0000 0000 DER TMRIL Holding Register for the Least Significant Byte of the 16 bit TMR1 XXXX XXXX uuuu uuuu DER TMR1H Holding Register for the Most Significant Byte of the 16 bit TMR1 XXXX XXXX uuuu uuuu 10h TICON TIGINV TMR GE TICKPS1 TICKPSO TIOSCEN TISYNC TMRICS TMRION 0000 0000 uuuu uuuu dih TMR2 Timer2 Module Register 0000 0000 0000 0000 12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPSO TMR2ON T2CKPS1 T2CKPSO 000 0000 000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON 5 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO 0000 0000 0000 0000 15h CCPRIL S Capture Compare PWM Register 1 LSB XXXX XXXX uuuu uuuu 16h CCPR1H Capture Compare PWM Register 1 MSB XXXX Xxxx uuuu uuuu 17h CCP1CON P1IM1 P1M0 DC1B1 DC1BO CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19h TXREG EUSART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG EUSART Receive Data Register 0000 0000 0000 0000 1Bh Unimplemented Es os 1Ch PWMICON prsen PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDCO 0000 0000 oooo 0000 1Dh ECCPAS gccPASE ECCPAS2 ECCPAS1 ECCPASO PSSAC1 PSSACO PSSBD1 PSSBDO oooo 0000 oooo 0000
160. F CCP1IF TMR2IF TMRIIF 000 0000 ong 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X 19h TXREG EUSART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG EUSART Receive Data Register 0000 0000 0000 0000 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 1111 8Ch PIE1 ADIE RCIE TXIE SSPIE CCPIE TMR2IE TMR1IE 000 0000 000 0000 98h TXSTA CSRC TX9 TXEN SYNC SENB BRGH TRMT TX9D 0000 0010 0000 0010 99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRGO 0000 0000 0000 0000 9Ah SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 9Bh BAUDCTL ABDOVF RCIDL SCKP BRG16 WUE ABDEN 01 0 0 00 01 0 0 00 Legend x unknown unimplemented locations read as 0 Shaded cells are not used for Asynchronous Reception Note 1 PIC16F687 PIC16F689 PIC16F690 only O 2005 Microchip Technology Inc Preliminary DS41262A page 149 PIC16F685 687 689 690 12 4 2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected reception is enabled by setting either the Single Receive Enable bit SREN RCSTA lt 5 gt or the Continuous Receive Enable bit CREN RCSTA lt 4 gt Data is sampled on the 7 RB5 AN11 RX DT pin on the falling edge of the clock If enable bit SREN is set only a single word is received If enable bit CREN is set the reception is continuous 8 until CREN is cleared If both bits are set then CREN takes precedence oa Po To set up a Synchronou
161. F690 only 2005 Microchip Technology Inc Preliminary DS41262A page 163 PIC16F685 687 689 690 13 11 SSP IC Operation The SSP module in DC mode fully implements all slave functions except general call support and provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions The SSP module implements the standard mode specifications as well as 7 bit and 10 bit addressing Two pins are used for data transfer These are the RB6 SCK SCL pin which is the clock SCL and the RB4 AN10 SDI SDA pin which is the data SDA The SSP module functions are enabled by setting SSP enable bit SSPEN SSPCON lt 5 gt FIGURE 13 7 SSP BLOCK DIAGRAM CTM MODE Internal Data Bus Read E Write RB6 SC SSPBUF reg x L NZ RB4 AN10 SDI SDA Match Detect rs Addr Match ZN SSPMSK reg A SSPADD reg Start and Set Reset Stop bit Detect S P bits SSPSTAT reg The SSP module has six registers for the DC operation which are listed below e SSP Control register SSPCON e SSP Status register SSPSTAT Serial Receive Transmit Buffer SSPBUF e SSP Shift register SSPSR Not directly accessible e SSP Address register SSPADD e SSP Mask register SSPMSK The SSPCON register allows control of the I2C operation Four mode selection bits SSPCON
162. Fosc 4 MHz 320 TBD UA ap EXTRC mode 580 TBD uA 5 0 D018 2 1 TBD mA Ab Fosc 20 MHz no 24 TBD mA 5 0 HS Oscillator mode Legend TBD To Be Determined Data in Typ column is at 5 0V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all I O pins tri stated pulled to VDD MCLR VDD WDT disabled 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as 1 0 pin loading and switching rate oscillator type internal code execution pattern and temperature also have an impact on the current consumption 3 The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled The peripheral A current can be determined by subtracting the base IDD or IPD current from this limit Max values should be used when calculating total current consumption 4 The power down current in Sleep mode does not depend on the oscillator type Power down current is measured with the part in Sleep mode with all I O pins in high impedance state and tied to VDD DS41262A page 212 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 17 2 DC Characteristics PIC16F685 687 689 690 I Industrial Continued
163. I O Individually controlled interrupt on change Individually enabled pull up AN3 AN A D Channel 3 input TIG ST Timer1 gate input OSC2 XTAL Crystal Resonator CLKOUT CMOS Fosc 4 output RA5 T1CKI OSC1 CLKIN RA5 TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up T1CKI ST Timer clock input OSC1 XTAL Crystal Resonator CLKIN ST External clock input RC oscillator connection RB4 AN10 SDI SDA RB4 TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up AN10 AN A D Channel 10 input SDI ST SC SPI data input SDA ST OD IC data input output RB5 AN11 RX DT RB5 TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up AN11 AN A D Channel 11 input RX ST EUSART asynchronous input DT ST CMOS EUSART synchronous data Legend AN Analog input or output CMOS CMOS compatible input or output OD Open Drain TTL TTL compatible input ST Schmitt Trigger input with CMOS levels HV High Voltage XTAL Crystal DS41262A page 10 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 TABLE 1 2 PINOUT DESCRIPTION PIC16F687 PIC16F689 CONTINUED Name Function tse a oe Description RB6 SCK SCL RB6 TTL CMOS General purpose I O Individuall
164. IE PIE2 lt 7 gt bit is also set The device firmware can then take steps to mitigate the problems that may arise from a failed clock The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation The internal clock source chosen by the FSCM is determined by the IRCF bits OSCCON lt 6 4 gt This allows the internal oscillator to be configured before a failure occurs 3 7 3 FAIL SAFE CONDITION CLEARING The Fail Safe condition is cleared after a Reset executing a SLEEP instruction or toggling the SCS bit OSCCON lt 0 gt When the SCS bit is toggled the OST is restarted While the OST is running the device continues to operate from the INTOSC selected in OSCCON When the OST times out the Fail Safe condition is cleared and the device will be operating from the external clock source The Fail Safe condition must be cleared before the OSFIF flag can be cleared 3 7 4 RESET OR WAKE UP FROM SLEEP The FSCM is designed to detect an oscillator failure after the Oscillator Start up Time OST has expired The OST is used after waking up from Sleep and after any type of Reset The OST is not used with the EC or RC clock modes so the FSCM will be active as soon as the Reset or wake up have completed When the FSCM is enabled the Two Speed Start up is also enabled Therefore the device will always be executing c
165. ME BASE PWM period PR2 1 e4esTosce TMR2 prescale value PWM frequency is defined as 1 PWM period When TMR2 is equal to PR2 the following three events occur on the next increment cycle e TMR2 is cleared The appropriate PWM pin toggles In Dual PWM mode this occurs after the dead band delay expires exception if PWM duty cycle 0 the pin will not be set The PWM duty cycle is latched from CCPR1L into CCPR1H Note The Timer2 postscaler see Section 7 1 Timer2 Operation is not used in the determination of the PWM frequency The postscaler could be used to have a servo update rate at a different frequency than the PWM output 11 3 3 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPRiL register and to the DC1B lt 1 0 gt CCP1CON lt 5 4 gt bits Up to 10 bits of resolution is available The CCPR1L contains the eight MSbs and the DC1B lt 1 0 gt contains the two LSbs CCPR1L and DC1B lt 1 0 gt can be written to at any time In PWM mode CCPR1H is a read only register This 10 bit value is represented by CCPR1L CCP1CON lt 5 45 The following equation is used to calculate the PWM duty cycle in time EQUATION 11 2 PWM DUTY CYCLE TIME PWM duty cycle CCPRIL CCPICON lt 5 4 gt o Tosc e TMR2 prescale value When the CCPR1H and 2 bit latch match TMR2 concatenated with an internal 2 bit Q clock or 2 bits of the TMR2 prescaler the appropr
166. MICROCHIP PIC16F685 687 689 690 Data Sheet 20 Pin Flash Based 8 Bit CMOS Microcontrollers with nanoWatt Technology GERE a ARE ARE O 2005 Microchip Technology Inc Preliminary DS41262A Note the following details of the code protection feature on Microchip devices Microchip products meet the specification contained in their particular Microchip Data Sheet Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge reguire using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets Most likely the person doing so is engaged in theft of intellectual property Microchip is willing to work with the customer who is concerned about the integrity of their code Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as unbreakable Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of our products Attempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright Act If such acts allow unautho
167. MPLAB ICE 2000 universal in circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PiCmicro microcontrollers Software control of the MPLAB ICE 2000 in circuit emulator is advanced by the MPLAB Integrated Development Environment which allows editing building downloading and source debugging from a single environment The MPLAB ICE 2000 is a full featured emulator sys tem with enhanced trace trigger and data monitoring features Interchangeable processor modules allow the system to be easily reconfigured for emulation of differ ent processors The universal architecture of the MPLAB ICE in circuit emulator allows expansion to support new PICmicro microcontrollers The MPLAB ICE 2000 in circuit emulator system has been designed as a real time emulation system with advanced features that are typically found on more expensive development tools The PC platform and Microsoft Windows 32 bit operating system were chosen to best make these features available in a simple unified application 16 10 MPLAB ICE 4000 High Performance Universal In Circuit Emulator The MPLAB ICE 4000 universal in circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high end PICmicro microcontrollers Software control of the MPLAB ICE in circuit emulator is provided by the MPLAB Integrated Development Environment which all
168. N 97h 0 1000 0 1000 u uuuu TXSTA 98h 0000 0010 0000 0010 uuuu uuuu SPBRG 99h 0000 0000 0000 0000 uuuu uuuu SPBRGH 9Ah 0000 0000 0000 0000 uuuu uuuu BAUDCTL 9Bh 01 0 0 00 01 0 0 00 uu u u uu ADRESL 9Eh XXXX XXXX uuuu uuuu uuuu uuuu ADCON1 9Fh 000 000 uuu EEDAT 10Ch 0000 0000 0000 0000 uuuu uuuu EEADR 10Dh 0000 0000 0000 0000 uuuu uuuu EEDATH 10Eh 00 0000 00 0000 uu uuuu EEADRH 10Fh 0000 0000 uuuu WPUB 115h 1111 1111 uuuu IOCB 116h 0000 0000 uuuu VRCON 118h 0000 0000 0000 0000 uuuu uuuu CM1CONO 119h 0000 000 0000 000 uuuu uuu CM2CONO 11Ah 0000 000 0000 000 uuuu uuu CM2CON1 11Bh 00 00 00 10 uu uu ANSEL 11Eh 1111 1111 11111121 uuuu uuuu ANSELH 11Fh 1111 1111 uuuu EECON1 18Ch x x000 u q000 uuuu EECON2 18Dh Aa were PSTRCON 19Dh 0 0001 0 0001 u uuuu SRCON 19EH 0000 00 0000 00 uuuu uu Legend u unchanged x unknown unimplemented bit reads as 0 q value depends on condition Note 1 If VDD goes too low Power on Reset will be activated and registers will be affected differently 2 One or more bits in INTCON and or PIR1 will be affected to cause wake up When the wake up is due to an interrupt and the GIE bit is set the PC is loaded with the interrupt vector 0004h See Table 14 5 for Reset value for specific condition If Reset was due to brown out then bit O 0 All other Resets will c
169. NG EDGE T1CKI 1 when TMR1 Enabled A A A A T1CKI o when TMR1 I Enabled A A A A Note 1 Arrows indicate counter increments 2 In Counter mode a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock DS41262A page 74 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 REGISTER 6 1 T1CON TIMER1 CONTROL REGISTER ADDRESS 10h R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 TIGINV TMR1GE T1CKPS1 TACKPS0 TIOSCEN TISYNC TMRICS TMR1ON bit 7 bit 0 bit 7 T1GINV Timer1 Gate Invert bit 1 Timer1 gate is inverted 0 mer gate is not inverted bit 6 TMRI1GE Timer1 Gate Enable bit If TMRION 0 This bit is ignored If TMR1ION 1 1 Timer1 is on if Timer gate is not active o Timer1 is on bit 5 4 T1CKPS lt 1 0 gt Timer1 Input Clock Prescale Select bits 11 1 8 Prescale Value 10 1 4 Prescale Value 01 1 2 Prescale Value 00 1 1 Prescale Value bit 3 T1OSCEN LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active 1 LP oscillator is enabled for Timer1 clock 0 LP oscillator is off Else This bit is ignored bit 2 TISYNC Timer1 External Clock Input Synchronization Control bit TMR1CS 1 1 Do not synchronize external clock input 0 Synchronize external clock input TMR1GS 0 This bit is ignored Timer1 uses the internal clock bit 1 TMRICS Timer1 Clock Sourc
170. O ANO C1IN ICSPDAT ULPWU DIAGRAMS Figure 4 2 shows the diagram for this pin The RAO Each PORTA pin is multiplexed with other functions The ANO C1IN ICSPDAT ULPWU pin is configurable pins and their combined functions are briefly described to function as one of the following here For specific information about individual functions a general purpose I O such as the comparator or the A D Converter refer to the e SE log i for the A D appropriate section in this data sheet arranalog inputorhe an analog input to Comparator 1 e In Circuit Serial Programming data an analog input for the Ultra Low Power Wake up FIGURE 4 1 BLOCK DIAGRAM OF RAO Analog Input Mode Data Bus e e D Q a Weak wn ASK a WPUDA LH _ RABPU WPUDA VDD WR 4 Ck I O Pin PORTA ol y Vss ULPWUE TRISA Analog Input Mode PORTA XS Q3 L WEE EN Interrupt on Change RD PORTA To Comparator aa To A D Converter Note 1 ANSEL determines Analog Input mode 2005 Microchip Technology Inc Preliminary DS41262A page 51 PIC16F685 687 689 690 4 2 4 2 RA1 AN1 C12IN VREF ICSPCLK Figure 4 2 shows the diagram for this pin The RA1 AN1 C12IN VREF ICSPCLK pin is configurable to function as one of the following a general pur
171. ORTA PORTB change interrupt 0 Disables the PORTA PORTB change interrupt bit 2 TOIF TMRO Overflow Interrupt Flag bit 1 TMRO register has overflowed must be cleared in software 0 TMRO register did not overflow bit 1 INTF RA2 INT External Interrupt Flag bit 1 The RA2 INT external interrupt occurred must be cleared in software o The RA2 INT external interrupt did not occur bit 0 RABIF PORTA PORTB Change Interrupt Flag bit 1 When at least one of the PORTA or PORTB general purpose UO pins changed state must be cleared in software o None of the PORTA or PORTB general purpose I O pins have changed state Note 1 IOCA or IOCB register must also be enabled 2 TOIF bit is set when Timer0 rolls over Timer0 is unchanged on Reset and should be initialized before clearing TOIF bit 3 Includes ULPWU interrupt Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown DS41262A page 26 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 2 2 2 4 PIE1 Register The PIE1 register contains the interrupt enable bits as Note Bit PEIE INTCON lt 6 gt must be set to shown in Register 2 4 enable any peripheral interrupt REGISTER 2 4 PIE1 PERIPHERAL INTERRUPT ENABLE REGISTER 1 ADDRESS 8Ch U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 ADIE RCI
172. ORTB pin configured as an input tri stated 0 PORTB pin configured as an output bit 3 0 Unimplemented Read as 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown REGISTER 4 7 WPUB WEAK PULL UP PORTB REGISTER ADDRESS 115h R W 1 R W 1 R W 1 R W 1 U 0 U 0 U 0 U 0 WPUB7 WPUB6 WPUBS WPUB4 bit 7 bit 0 bit 7 4 WPUB lt 7 4 gt Weak Pull up Register bits 1 Pull up enabled 0 Pull up disabled bit 3 0 Unimplemented Read as oi Note 1 Global RABPU must be enabled for individual pull ups to be enabled 2 The weak pull up device is automatically disabled if the pin is in Output mode TRISB lt 7 4 gt 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 57 PIC16F685 687 689 690 REGISTER 4 8 IOCB INTERRUPT ON CHANGE PORTB REGISTER ADDRESS 116h R W 0 RWO RW 0 BW U 0 U 0 U 0 U 0 IOCB7 IOCB6 IOCB5 IOCB4 bit 7 bit 0 bit 7 4 IOCB lt 7 4 gt Interrupt on Change bits 1 Interrupt on change enabled 0 Interrupt on change disabled bit 3 0 Unimplemented Read as oi Legend R Readable bit W Writable bit U Unimplemented b
173. OSC Specifications eseeeeeeeeeneenerenereerrerinerrernnrreene 220 IOCA Register f IOCB Register L Load lo e LEE 218 M NIGER EE 176 Neel EE Microchip Internet Web Site ve Migrating from other PICmicro Devices 245 MPLAB ASM30 Assembler Linker Librarian 204 MPLAB ICD 2 In Circuit Debugger sesscssseeeereerrerrneeen 205 MPLAB ICE 2000 High Performance Universal In Circuit Emulator 205 MPLAB ICE 4000 High Performance Universal In Circuit Emulator cece os 205 MPLAB Integrated Development Environment Software 203 MPLAB PM3 Device Programmer 205 MPLINK Object Linker MPLIB Object Librarian 204 O OPCODE Field Descriptions 193 OPTION Register iihi We Rh a eed 25 70 OSCCON Register lt lt nswanmanzanzmnamannmanzanzanzmaamaamzaza 45 Oscillator Associated registers as 45 Oscillator Configurations Se Oscillator Gpechications eee eee eee eeeeeeeeeeeneeeeees Oscillator Start up Timer OST ee We TEE 223 Oscillator Switching Fail Safe Clock Monitor 43 Two Speed Clock Start up wmmemmmammmmamwnza 41 P P Stopy NA Kai oan ae 156 P1A P1B P1C P1D See Enhanced Capture Compare PWM US EE 116 Packaging Marking KAA AKAA Taea MAE ais 239 PDIP Dai AK 240 PCON Register i PICkit 1 Flash Starter Kit 207 PICSTART Plus Development Programmer 206 PIET Register hreinan PIE2 Regis
174. PAS lt 2 0 gt bits ECCPAS lt 6 4 gt REGISTER 11 4 ECCPAS ENHANCED CAPTURE COMPARE PWM AUTO SHUTDOWN CONTROL REGISTER ADDRESS 1Dh R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 ECCPASE ECCPAS2 ECCPAS1 ECCPASO PSSAC1 PSSACO PSSBD1 PSSBDO bit 7 bit 0 bit 7 ECCPASE ECCP Auto shutdown Event Status bit 1 A shutdown event has occurred ECCP outputs are in shutdown state 0 ECCP outputs are operating bit 6 4 ECCPAS lt 2 0 gt ECCP Auto shutdown Source Select bits 000 Auto shutdown is disabled 001 Comparator 1 output change 010 Comparator 2 output change 011 Either Comparator 1 or 2 change 100 VIL on INT pin 101 VIL on INT pin or Comparator 1 change 110 VIL on INT pin or Comparator 2 change 111 VIL on INT pin or Comparator 1 or Comparator 2 change bit 3 2 PSSACn Pin P1A and P1C Shutdown State Control bits 00 Drive Pins P1A and P1C to o 01 Drive Pins PIA and P1C to 1 1x Pins P1A and P1C tri state bit 1 0 PSSBDn Pin P1B and P1D Shutdown State Control bits 00 Drive Pins P1B and P1D to o 01 Drive Pins P1B and P1D to 1 1x Pins P1B and P1D tri state Note 1 PIC16F685 PIC16F690 only Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 127 PIC16F685 687 689 690 11 3 8 1
175. PGK or AA EH LSb RB7 TX CK Pin Pin Buffer 10 Ee i and Control x Laie GE TSR Register iii Interrupt bi TXEN Baud Rate CLK oe SES E TRMT SPEN BRG16 SPBRGH SPBRG fie Po wee Oe ee eee A TX9 Baud Rate Generator TX9D FIGURE 12 3 ASYNCHRONOUS TRANSMISSION Write to TXREG 1 d Word 1 BRG Output Shift Clock RB7 TX CK os 7 i pin N Startbit X b X biti X a bit 7 8 Stop bit i W 1 L gt TXIF bit ora Transmit Buffer gt 1 Toy Reg Empty Flag wa P Z T T Aa Write to TXREG BRG Output Shift Clock RB7 TX CK pin TXIF bit Interrupt Reg Flag TRMT bit Transmit Shift Reg Empty Flag Note This ti CC Word 1 Word 2 Il Tee Eege mo Ee l el T3 N Statbit K D X btt X f X bit7 8 7 Stopbit NStart bit K Dn 1 Toy he word 1 Word 1 Toy 5 Wordi Transmit Shift Reg Word 3 Transmit Shift Reg ming diagram shows two consecutive transmissions DS41262A page 142 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 TABLE 12 5 REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION V i x 1 b A V Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR all other Resets OCh PIR1 ADIF RCIF
176. Preliminary DS41262A page 171 PIC16F685 687 689 690 FIGURE 13 12 CLOCK SYNCHRONIZATION TIMING Q1 oe os as Q1 och 64 01 oe os as Q1 ca aalas Q1 co Q1 vo 0401 oz os os I I 5 I SDA DX b DX 1 CC 1 SCL I r Se ny Ths EA cois I i J Master device CKP asserts clock Master device deasserts clock SSPCON I d E TABLE 13 4 REGISTERS ASSOCIATED WITH I2C OPERATION Addr Name Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Ve ali other esets OBh 8Bh INTCON GE PEE TOE INTE RABIE TOF INTF RABIF 0000 ooox 0000 ooox 10Bh 18Bh DCH PIRI ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 000 0000 000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer Transmit Register XXXX XXXX uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM8 SSPM2 SSPM1 SSPMO 0000 0000 0000 0000 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 1111 93h SSPMSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSKO 1111 1111 1111 1111 94h SSPSTAT SMP CKE D A P s R W UA BF 0000 0000 0000 0000 8Ch PIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IF TMRIIF ooo 0000 000 0000 Legend Unimplemented locations read as 0 u unchanged x unknown Shaded cells are not used by the SSP module Note 1 PIC16F687 PIC16F689 PIC16F690 only 2 SSPMSK register Register 13 3 can be
177. REGISTERS ASSOCIATED WITH PORTB Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 S other POR BOR Resets 06h 106h PORTB RB7 RB6 RB5 RB4 xxxx uuuu 86h 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 1111 OBh 8Bh INTCON GIE PEIE TOIE INTE RABIE TOIF INTF RABIF 0000 000x 0000 000x 10Bh 18Bh 115h WPUB WPUB7 WPUB6 WPUB5 WPUB4 1111 1111 116h IOCB IOCB7 IOCB6 IOCB5 IOCB4 0000 0000 Legend x unknown u unchanged unimplemented locations read as 0 Shaded cells are not used by PORTB 2005 Microchip Technology Inc Preliminary DS41262A page 63 PIC16F685 687 689 690 4 5 PORTC and TRISC Registers The TRISC register controls the direction of the PORTC pins even when they are being used as analog inputs The user must ensure the bits in the TRISC register are maintained set when using them as analog inputs I O pins configured as analog input always read 0 PORTC is a 8 bit wide bidirectional port The corresponding data direction register is TRISC Register 4 10 Setting a TRISC bit 1 will make the corresponding PORTC pin an input e put the corresponding output driver in a High impedance mode Note The ANSEL 11Eh and ANSELH 11Fh Clearing a TRISC bit 0 will make the corresponding registers must be initialized to configur
178. RISCO 1111 1111 8Ch PIE1 ADIE RCIE TXIE SSPIE CCPI1IE TMR2IE TMRIIE 000 0000 000 0000 9Eh ADRESL A D Result Register Low Byte XXXX Xxxx uuuu uuuu 9Fh ADCON1 ADCS2 ADCS1 ADCSO 000 000 Legend x unknown u unchanged unimplemented read as o Shaded cells are not used for A D module 2005 Microchip Technology Inc Preliminary DS41262A page 103 PIC16F685 687 689 690 NOTES KEE SAR EG EE ERES DS41262A page 104 Preliminary O 2005 Microchip Technology Inc PIC16F685 687 689 690 10 0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL Data EEPROM memory is readable and writable and the Flash program memory is readable during normal operation full Vpp range These memories are not directly mapped in the register file space Instead they are indirectly addressed through the Special Function Registers There are six SFRs used to access these memories e EECON1 e EECON2 EEDAT e EEDATH e EEADR e EEADRH When interfacing the data memory block EEDAT holds the 8 bit data for read write and EEADR holds the address of the EEDAT location being accessed This device has 256 bytes of data EEPROM with an address range from Oh to OFFh When interfacing the program memory block the EEDAT and EEDATH registers form a 2 byte word that holds the 14 bit data for read write and the EEADR and EEADRH registers form a 2 byte word that holds the 12 bit address of the EEPROM location being accessed Th
179. Readable bit n Value at POR W Writable bit T Bit is set U Unimplemented bit read as 0 0 Bit is cleared x Bit is unknown WPUA WEAK PULL UP PORTA REGISTER ADDRESS 95h U 0 U 0 R W 1 R W 1 U 0 R W 1 R W 1 R W 1 WPUAS WPUA4 WPUA2 WPUA1 WPUAO bit 7 Unimplemented Read as oi WPUA lt 5 4 gt Weak Pull up Register bit 1 Pull up enabled 0 Pull up disabled Unimplemented Read as oi WPUA lt 2 0 gt Weak Pull up Register bit 1 Pull up enabled 0 Pull up disabled Note 1 2 bit 0 Global RABPU must be enabled for individual pull ups to be enabled The weak pull up device is automatically disabled if the pin is in Output mode TRISA 0 The RAS pull up is enabled when configured as MCLR and disabled as an I O in the Configuration Word WPUA lt 5 4 gt always reads 1 in XT HS and LP OSC modes Legend R Readable bit n Value at POR W Writable bit 1 Bit is set U Unimplemented bit read as 0 0 Bit is cleared X Bit is unknown DS41262A page 48 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 4 2 2 INTERRUPT ON CHANGE Each of the PORTA pins is individually configurable as an interrupt on change pin Control bits IOCAx enable or disable the interrupt function for each pin Refer to Register 4 4 The inter
180. S 119h R W 0 R 0 R W 0 R W 0 U 0 R W 0 R W 0 R W 0 C1ON C1O0UT C1OE C1POL CIR C1CH1 C1CHO bit 7 bit 0 bit 7 C1ON Comparator C1 Enable bit 1 C1 Comparator is enabled 0 C1 Comparator is disabled bit 6 C1OUT Comparator C1 Output bit If C1POL 1 inverted polarity C1OUT 1 CIVP lt C1VN C1OUT 0 CIVP gt CIVN If C1POL 0 non inverted polarity C1OUT 1 C1VP gt CIVN C1OUT 0 C1VP lt CIVN bit 5 C10E Comparator C1 Output Enable bit 1 C10UT is present on the RA2 AN2 TOCKI INT C10UT pin 0 C1OUT is internal only bit 4 C1POL Comparator C1 Output Polarity Select bit 1 C1OUT logic is inverted 0 C1OUT logic is not inverted bit 3 Unimplemented Read as o bit 2 C1R Comparator C1 Reference Select bit non inverting input 1 C1VP connects to C1VREF output o C1VP connects to RAO ANO C1IN ICSPDAT ULPWU bit 1 0 C1CH lt 1 0 gt Comparator C1 Channel Select bit 00 C1VN of C1 connects to RA1 AN1 C12IN VREF ICSPCLK 01 C1VN of C1 connects to RC1 AN5 C12IN 10 C1VN of C1 connects to RC2 AN6 P1D 11 C1VN of C1 connects to RC3 AN7 P1C Note 1 C1OUT will only drive RAZ AN2 TOCKI INT C1OUT if C10E 1 CION 1 and TRISA lt 2 gt 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 81
181. SART SYNCHRONOUS TRANSMISSION MASTER SLAVE TIMING RB7 TX CK E NM pin eia 121 e a 121 o RB5 AN11 RX DT SD pin X Did 120 e ja Note Refer to Figure 17 2 for load conditions TABLE 17 10 EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions unless otherwise stated Operating Temperature 40 C lt TA lt 125 C boi Symbol Characteristic Min Max Units Conditions 120 TCKH2DTV SYNC XMIT Master amp Slave 40 ns Clock high to data out valid 121 TCKRF Clock out rise time and fall time Master mode 20 ns 122 TDTRF Data out rise time and fall time 20 ns FIGURE 17 10 EUSART SYNCHRONOUS RECEIVE MASTER SLAVE TIMING RC4C20UT TX CK DN pin l 125 RC5 RX DT i pin Da Ka a 126 gt Note Refer to Figure 17 2 for load conditions TABLE 17 11 EUSART SYNCHRONOUS RECEIVE REGUIREMENTS Standard Operating Conditions unless otherwise stated Operating Temperature 40 C lt TA lt 125 C Param No Symbol Characteristic Min Max Units Conditions 125 TDTV2cKL SYNC RCV Master amp Slave Data hold before CK J DT hold time 10 ns 126 TckL2DTL Data hold after CK J DT hold time 15 ns 2005 Microchip Technology Inc Preliminary DS41262A page 227 PIC16F685 687 689 690 FIGURE 17 11 SPI MASTER MODE TIMING CKE 0 SMP 0
182. SPM 157 Synchronous Serial Port See SSP T Baler ei Rer EEN Time out Seguence s wssmanzwnsnanzwaamanamanzanizanzanemanana Deen UA Ee EE Associated Registers External Cloche External Clock Requirements eieseeseeereesnesreasseea 224 Inte LA KAA sanar sao 69 Operation i erdera eva eee 69 TOCK Anka canteens DAN aan EA DS UM EE Associated registers ka Asynchronous Counter Mode seeeeseeeeeeeereree 76 Reading and Writing eesesessseeeereerrerenrreereerren 76 External Clock Requirements a JC let EE 74 Modes of Operations essesseseeeieerrereseerrerrnereerrerrse 74 Operation During Sleep e Oscillator 76 PresCal fi AA WAA La ESG AGM e 74 Timer1 Gate Inverting Gate wie f4 Selecting Source wi 74 TMR1H Register n 73 TMRIL Register wi 79 Timer wwwwmmmmammmaza we 77 Associated Registers 78 Oporto ssa ses a a de saves tere Postscaler hh WK ET Eeer AE AE e EN MAC TMR2 Register TMR2 to PR2 Match Interrupt lt w ww wwwa 77 78 Timing Diagrams A D Conversion ssssssssessiesssissriserinresinernnsrensrrenen A D Conversion Sleep Mode Asynchronous Hecepntion Asynchronous Transmission Asynchronous Transmission Back to Back Automatic Baud Rate Calculator Auto Wake up Bit WUE During Normal Opera
183. Sleep mode with all I O pins in high impedance state and tied to VDD DS41262A page 214 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 173 DC Characteristics PIC16F685 687 689 690 E Extended Standard Operating Conditions unless otherwise stated DC CHARACTERISTICS Operating mais 40 C a lt 125 C for Malin Sa Device Characteristics Min Typt Max Units eee VDD Note D020E Power down Base 0 1 TBD uA 2 0 WDT BOR Comparators VREF and Current Ipp 4 0 4 TBD UA ao MOSC disabled 08 TBD HA 5 0 D021E 08 TBD HA 2 0 WDT Current 18 TBD HA 3 0 84 TBD LA 5 0 D022E 58 TBD uA 3 0 BOR Current 109 TBD uA 5 0 D023E 3 3 TBD uA 2 0 Comparator Current 6 1 TBD HA 3 0 11 5 TBD HA 5 0 D024E 58 TBD HA 2 0 CVREF Current 85 TBD HA 3 0 138 TBD HA 5 0 D025E 4 0 TBD uA 2 0 TIOSC Current 46 TBD HA 3 0 60 TBD HA 5 0 D026E 12 TBD nA 3 0 A D Current 22 TBD nA 5 0 D027E TBD TBD uA 3 0 VP6 Current TBD TBD uA 5 0 Legend TBD To Be Determined t Data in Typ column is at 5 0V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from r
184. T Asynchronous Mode azma 12 bit Break Transmit and Receive Associated Registers Receive Associated Registers Transmit Auto Wake Up on Falling Edge Receive AA Ee ged Setting up 9 bit Mode with Address Detect 144 Baud Rate Generator BRG Auto Baud Detect seseeeeseserreereerrerreereereens Baud Rate Error Calculating Baud Rates Asynchronous Modes FOLMUIAS paio erena ee deine aaea High Baud Rate Select BRGH Bit Sampling aiina ra pehea iie Serial Port Enable SPEN Bit Synchronous Master Mode Associated Registers Reception Associated Registers Transmit Reception erer ENEE Reguirements Synchronous Receive Reguirements Synchronous Transmission 227 Timing Diagram Synchronous Receive 227 Timing Diagram Synchronous Transmission 227 TILANSMISSION wa a e daan a aada ai 148 Synchronous Slave Mode 152 Associated Registers Receive 153 Associated Registers Transmit 152 Reception eeeeeeescreeeesereseeseseesssensesseeesesssesse Transmission as Evaluation and Programming Tools 207 F Fail Safe Clock Monitor Fail Safe Condition Clearing Fail Safe Detection cee eenecseeeseeesaeenaes Fai
185. TDOR SDO data output rise time 3 0 5 5V 10 25 ns 2 0 5 5V 25 50 ns 76 TDOF SDO data output fall time 10 25 ns 77 TssH2po7 SST to SDO output high impedance 10 50 ns 78 TSCR SCK output rise time 3 0 5 5V 10 25 ns Master mode 2 0 5 5V 25 50 ns 79 TSCF SCK output fall time Master mode 10 25 ns DU TscH2DOV SDO data output valid after 3 0 5 5V 50 ns TscL2DOV SCK edge 2 0 5 5V 145 ns 817 TDOV2SCH SDO data output setup to SCK edge Tcy ns TpoV2scL 82 TssL2poV SDO data output valid after SS edge 50 ns 83 TscH2ssH SS 7 after SCK edge 1 5TcY 40 ns TscL2ssH These parameters are characterized but not tested t Data in Typ column is at 5 0V 25 C unless otherwise stated These parameters are for design guidance only and are not tested FIGURE 17 15 CTM BUS START STOP BITS TIMING SCL Start Stop Condition Condition Note Refer to Figure 17 2 for load conditions DS41262A page 230 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 TABLE 17 13 2CTM BUS START STOP BITS REQUIREMENTS b s Symbol Characteristic Min Typ Max Units Conditions 905 Tsu sTA Start condition 100 kHz mode 4700 ns Only relevant for Repeated Setup time 400kHzmode 600 Start condition 915 THDISTA Star
186. TRISC4 TRISC3 TRISC2 TRISC1 TRISCO bit 7 bit 0 bit 7 0 TRISC lt 7 0 gt PORTC Tri State Control bit 1 PORTC pin configured as an input tri stated 0 PORTC pin configured as an output Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown DS41262A page 64 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 4 5 1 RC0 AN4 C2IN The RCO is configurable to function as one of the following a general purpose UO an analog input for the A D an analog input to Comparator 2 4 5 2 RC1 AN5 C12IN The RC1 is configurable to function as one of the following a general purpose UO an analog input for the A D an analog input to Comparator 1 or 2 FIGURE 4 11 BLOCK DIAGRAM OF RCO AND RC1 Data Bus Ale Q VDD WR CK gt PORTCT H lt UO Pin eD Q WR Es K misc gt 9 Analog Input o lt Mode RD 4 TRISC RD PORTC To Comparators lt e To A D Converter ken Note 1 ANSEL determines Analog Input mode 4 5 3 RC2 AN6 P1D The RC2 AN6 PID D is configurable to function as one of the following a general purpose I O an analog input for the A D e a PWM output Note 1 PID is available on PIC16F685 PIC16F690 only 4 5 4 RC3 AN7 P1C The RC3 AN7 P1C is
187. The assembler will generate code with x 0 It is the recommended form of use for compatibility with all Microchip software tools a Destination select d 0 store result in W d 1 store result in file register f Default is d 1 Pc Program Counter TO Time out bit PD Power down bit FIGURE 15 1 GENERAL FORMAT FOR INSTRUCTIONS Byte oriented file register operations 13 8 7 6 0 OPCODE d f FILE d 0 for destination W d 1 for destination f f 7 bit file register address Bit oriented file register operations 13 10 9 7 6 0 OPCODE b BIT f FILE 3 bit bit address b f 7 bit file register address Literal and control operations General 13 8 7 0 OPCODE k literal k 8 bit immediate value CALL and GOTO instructions only 13 11 10 0 OPCODE k literal k 11 bit immediate value 2005 Microchip Technology Inc Preliminary DS41262A page 193 PIC16F685 687 689 690 TABLE 15 2 PIC16F685 687 689 690 INSTRUCTION SET Mnemonic mam 14 Bit Opcode Status Description Cycles Notes Operands MSb Lsp Affected BYTE ORIENTED FILE REGISTER OPERATIONS ADDWF fd Add W and f 1 00 0111 afff ffff C DC Z 1 2 ANDWF fd AND W with f 1 00 0101 dfff ffff Z 1 2 CLRF f Clear f 1 00 0001 1 fff ffff Z 2 CLRW Clear W 1 00 0001 0xxx XXXX Z COMF fd Complement f 1 00 1001 dfff
188. Unimplemented Read as oi ADFM 1 MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented Read as oi 10 bit A D Result 2005 Microchip Technology Inc Preliminary DS41262A page 95 PIC16F685 687 689 690 REGISTER 9 1 ANSEL ANALOG SELECT REGISTER ADDRESS 11Eh R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANSO bit 7 bit 0 bit 7 0 ANS lt 7 0 gt Analog Select bits Select between analog or digital function on pins AN lt 7 0 gt respectively 1 Analog input Pin is assigned as analog input 0 Digital I O Pin is assigned to port or special function Note 1 Setting a pin to an analog input automatically disables the digital input circuitry weak pull ups and interrupt on change if available The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown REGISTER 9 2 ANSELH ANALOG SELECT HIGH REGISTER ADDRESS 11Fh U 0 U 0 U 0 U 0 R W 1 R W 1 R W 1 R W 1 ANS11 ANS10 ANS9 ANS8 bit 7 bit 0 bit 7 4 Unimplemented Read as o bit 3 0 ANS lt 11 8 gt Analog Select bits Select between analog or digital function on pins AN lt 11 8 gt respectively
189. WPUAO 11 111 11 111 96h IOCA IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCAO 00 0000 00 0000 97h WDTCON WDTPS3 WDTPS2 WDTPS1 WDTPSO SWDTEN o 1000 0 1000 98h TXSTA CSRC TX9 TXEN SYNC SENB BRGH TRMT TX9D 0000 0010 0000 0010 99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRGO 0000 0000 0000 0000 9Ah SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 9Bh BAUDCTL ABDOVF RCIDL SCKP BRG16 WUE ABDEN 01 0 0 00 01 0 0 00 9Ch Unimplemented 9Dh Unimplemented 9Eh ADRESL A D Result Register Low Byte XXXX XXXX uuuu uuuu 9Fh ADCON1 ADCS2 ADCS1 ADCSO 000 000 Legend Unimplemented locations read as 0 u unchanged x unknown q value depends on condition shaded unimplemented Note 1 Other non Power up Resets include MCLR Reset and Watchdog Timer Reset during normal operation 2 MCLR and WDT Reset do not affect the previous value data latch The RABIF bit will be cleared upon Reset but will set again if the mismatched exists PIC16F687 PIC16F689 PIC16F690 only PIC16F685 PIC16F690 only RAS pull up is enabled when pin is configured as MCLR in Configuration Word Accessible only when SSPM lt 3 0 gt 1001 Siss 2005 Microchip Technology Inc Preliminary DS41262A page 21 PIC16F685 687 689 690 TABLE 2 3 PIC16F685 687 689 690 SPECIAL REGISTERS SUMMARY BANK 2
190. X uuuu uuuu uuuu uuuu INDF 00h 80h XXXX XXX XXXX XXX uuuu uuuu 100h 180h TMRO 01h 101h XXXX XXX uuuu uuuu uuuu uuuu PCL 02h 82h 0000 0000 0000 0000 pc 10 102h 182h STATUS 03h 83h 0001 1xxx 000q quuu uuug quuu4 103h 183h FSR 04h 84h XXXX XXXX uuuu uuuu uuuu uuuu 104h184h PORTA 05h 105h XX XXXX 00 0000 uu uuuu PORTB 06h 106h XXXX 0000 uuuu PORTC 07h 107h XXXX XXXX 0000 0000 uuuu uuuu PCLATH 0Ah 8Ah 0 0000 0 0000 u uuuu 10Ah 18Ah INTCON OBh 8Bh 0000 000x 0000 000x uuuu uuuul 10Bh 18Bh PIR1 0Ch 000 0000 000 0000 uuu uuuul PIR2 ODh 0000 0000 uuuu TMRIL 0Eh XXXX XXXX uuuu uuuu uuuu uuuu TMRTH OFh XXXX XXXX uuuu uuuu uuuu uuuu T1CON 10h 0000 0000 uuuu uuuu uuuu uuuu TMR2 1h 0000 0000 0000 0000 uuuu uuuu T2CON 12h 000 0000 000 0000 uuu uuuu SSPBUF 13h XXXX XXX XXXX XXXX uuuu uuuu SSPCON 14h 0000 0000 0000 0000 uuuu uuuu CCPRIL 15h XXXX XXXX uuuu uuuu uuuu uuuu CCPR1H 16h XXXX XXXX uuuu uuuu uuuu uuuu CCP1CON 17h 0000 0000 0000 0000 uuuu uuuu RCSTA 18h 0000 000x 0000 000x uuuu uuuu TXREG 19h 0000 0000 0000 0000 uuuu uuuu RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu PWM1CON 1Ch 0000 0000 0000 0000 uuuu uuuu ECCPAS 1Dh 0000 0000 0000 0000 uuuu uuuu ADRESH 1Eh XXXX XXXX uuuu uuuu uuuu uuuu ADCONO 1Fh 0000 0000 0000 0000 uuuu uuuu OPTION_REG 81h 181h 1111 1111 1111 1111 uuuu uuuu TRISA 85h 185h 11 1111 11 1111 uu uuuu Legend u unchanged x unknown unimplemented bit read
191. a 1 MHz system clock 3 3 2 EC MODE The External Clock EC mode allows an externally generated logic level as the system clock source When operating in this mode an external clock source is connected to the OSC1 pin and the RA4 AN3 T1G OSC2 CLKOUT pin is available for general purpose 1 0 Figure 3 2 shows the pin connections for EC mode The Oscillator Start up Timer OST is disabled when EC mode is selected Therefore there is no delay in operation after a Power on Reset POR or wake up from Sleep Because the PIC16F685 687 689 690 design is fully static stopping the external clock input will have the effect of halting the device while leaving all data intact Upon restarting the external clock the device will resume operation as if no time had elapsed FIGURE 3 2 EXTERNAL CLOCK EC MODE OPERATION Clock from SE OSC1 CLKIN Ext System PIC16F685 687 689 690 RA4 AN3 T1G OSC2 CLKOUT O OSC2 DS41262A page 36 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 3 3 3 LP XT HS MODES The LP KT and HS modes support the use of guartz crystal resonators or ceramic resonators connected to the OSC1 and OSC2 pins Figure 3 3 The mode selects a low medium or high gain setting of the internal inverter amplifier to support various resonator types and speed LP Oscillator mode selects the lowest gain setting of the internal inverter amplifier LP mode current consu
192. ail to rail all I O pins tri stated pulled to VDD MCLR VDD WDT disabled 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as 1 0 pin loading and switching rate oscillator type internal code execution pattern and temperature also have an impact on the current consumption 3 The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled The peripheral A current can be determined by subtracting the base IDD or IPD current from this limit Max values should be used when calculating total current consumption 4 The power down current in Sleep mode does not depend on the oscillator type Power down current is measured with the part in Sleep mode with all I O pins in high impedance state and tied to VDD 2005 Microchip Technology Inc Preliminary DS41262A page 215 PIC16F685 687 689 690 174 DC Characteristics PIC16F685 687 689 690 I Industrial PIC16F685 687 689 690 E Extended DC CHARACTERISTICS Standard Operating Conditions unless otherwise stated 40 C lt TA lt 85 C for industrial Operating temperature 40 C lt TA lt 125 C for extended is Sym Characteristic Min Typt Max Units Conditions Vu Input Low Voltage I O port D030 with TTL buffer Vss 0 8 V 4 5V lt VDD lt 5 5V D030A Vss 0 15 VDD V Otherwise D031 with Sch
193. an also be synchronized with Timer1 by setting the C2SYNC bit CM2CON1 lt 0 gt When enabled the output of Comparator 2 is latched on the falling edge of Timer1 clock source If a prescaler is used with Timer1 Comparator 2 is latched after the prescaler To prevent a race condition the Comparator 2 output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source See the Comparator 2 Block Diagram Figure 8 2 and the Timer1 Block Diagram Figure 6 1 for more information It is recommended to synchronize Comparator 2 with Timer1 by setting the C2SYNC bit when Comparator 2 is used as the Timer1 gate source This ensures Timer1 does not miss an increment if Comparator 2 changes during an increment 8 2 1 COMPARATOR INTERRUPT OPERATION The comparator interrupt flags are set whenever there is a change in the output value of its respective comparator Software will need to maintain information about the status of the output bits as read from CM2CONO lt 7 6 gt to determine the actual change that has occurred The CxIF bits PIR2 lt 6 5 gt are the Comparator Interrupt Flags Each comparator interrupt bit must be reset in software by clearing it to o Since it is also possible to write a 1 to this register a simulated interrupt may be initiated The CxIE bits PIE2 lt 6 5 gt and the PEIE bit INTCON lt 6 gt must be set to enable the interrupts In addition the GI
194. anslates standard ANSI C programs into dsPIC30F assembly language source The compiler also supports many command line options and language extensions to take full advantage of the dsPIC30F device hardware capabili ties and afford fine control of the compiler code generator MPLAB C30 is distributed with a complete ANSI C standard library All library functions have been vali dated and conform to the ANSI C library standard The library includes functions for string manipulation dynamic memory allocation data conversion time keeping and math functions trigonometric exponential and hyperbolic The compiler provides symbolic information for high level source debugging with the MPLAB IDE 16 6 MPLAB ASM30 Assembler Linker and Librarian MPLAB ASM30 assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices MPLAB C30 compiler uses the assembler to produce it s object file The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file Notable features of the assembler include Support for the entire dsPIC30F instruction set Support for fixed point and floating point data Command line interface Rich directive set e Flexible macro language e MPLAB IDE compatibility 16 7 MPLAB SIM Software Simulator The MPLAB SIM software simulator allows code devel opment in a PC hosted enviro
195. as the resumption of normal operation TO and PD bits are set or cleared differently in different Reset situations as indicated in Table 14 2 These bits are used in software to determine the nature of the Reset See Table 14 4 for a full description of Reset states of all registers A simplified block diagram of the On Chip Reset Circuit is shown in Figure 14 1 The MCLR Reset path has a noise filter to detect and ignore small pulses See Section 17 0 Electrical Specifications for pulse width specifications FIGURE 14 1 SIMPLIFIED BLOCK DIAGRAM OF ON CHIP RESET CIRCUIT External Reset gt MCLR VPP pin mas Sleep WDT WDT Module Time out Reset VDD Rise Detect VDD Power on Reset Brown out Reset BOREN SBOREN OST PWRT OST GI gt 10 bit Ripple Counter OSCH CLKI pin Ts Chip Reset R Q EE PWRT LFINTOsCH gt 11 bit Ripple Counter Enable PWRT Enable OST Note 1 Referto the Configuration Word register Register 14 1 2005 Microchip Technology Inc Preliminary DS41262A page 175 PIC16F685 687 689 690 14 2 1 POWER ON RESET POR The on chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation A maximum rise time for VDD is required See Section 17 0 Electrical Specifications
196. at the incoming character baud rate is within the range of the selected BRG clock source Some combinations of oscillator frequency and EUSART baud rates are not possible due to bit error rates Overall system timing and communication baud rates must be taken into consideration when using the Auto Baud Detect feature TABLE 12 4 BRG COUNTER CLOCK RATES BRG16 BRGH BRG Counter Clock 0 0 Fosc 512 0 1 Fosc 128 1 0 Fosc 128 1 1 Fosc 32 Note During the ABD sequence SPBRG and SPBRGH are both used as a 16 bit counter independent of BRG16 setting 2005 Microchip Technology Inc Preliminary DS41262A page 139 PIC16F685 687 689 690 FIGURE 12 1 AUTOMATIC BAUD RATE CALCULATION UUUUUUUU BRG Clock EL Set by User ABDEN bit RCIDL RCIF bit I BRGVaus 20001 3 00001 YO OCO ONO mee y Edge 1 e Edge 2 Edge 3 Edge 4 Edge 5 RX pin j Start Bit0 Biti Bt2 Bit3 Bit4 Bit5 Bite Bit7 Stop Bit Auto Cleared sT Interrupt E Read RCREG XXXXh SPBRG 1Ch SPBRGH XXXXh 00h Note 1 DS41262A page 140 Preliminary The ABD sequence requires the EUSART module to be configured in Asynchro
197. ause bit O u Accessible only when SSPM lt 3 0 gt 1001 GM EES 2005 Microchip Technology Inc Preliminary DS41262A page 181 PIC16F685 687 689 690 TABLE 14 5 INITIALIZATION CONDITION FOR SPECIAL REGISTERS Condition Program Status PCON Counter Register Register Power on Reset 000h 0001 1xxx 01 0x MCLR Reset during normal operation 000h 000u uuuu 0u uu MCLR Reset during Sleep 000h 0001 Ouuu 0u uu WDT Reset 000h 0000 uuuu 0u uu WDT Wake up PC 1 uuu0 Ouuu uu uu Brown out Reset 000h 0001 luuu 01 10 Interrupt Wake up from Sleep PC 100 uuul Ouuu uu uu Legend u unchanged x unknown unimplemented bit reads as o Note 1 When the wake up is due to an interrupt and Global Interrupt Enable bit GIE is set the PC is loaded with the interrupt vector 0004h after execution of PC 1 DS41262A page 182 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 14 3 Interrupts The PIC16F685 687 689 690 have multiple sources of interrupt External Interrupt RA2 INT e TMRO Overflow Interrupt e PORTA PORTB Change Interrupts e 2 Comparator Interrupts e A D Interrupt Timer1 Overflow Interrupt Timer2 Match Interrupt e EEPROM Data Write Interrupt Fail Safe Clock Monitor Interrupt Enhanced CCP Interrupt EUSART Receive and Transmit interrupts The Interrupt Control register INTCON and Peri
198. ave an impact on the current consumption 3 The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled The peripheral A current can be determined by subtracting the base IDD or IPD current from this limit Max values should be used when calculating total current consumption 4 The power down current in Sleep mode does not depend on the oscillator type Power down current is measured with the part in Sleep mode with all I O pins in high impedance state and tied to VDD 2005 Microchip Technology Inc Preliminary DS41262A page 213 PIC16F685 687 689 690 173 DC Characteristics PIC16F685 687 689 690 E Extended Standard Operating Conditions unless otherwise stated DC CHARACTERISTICS Operating temperature 40 C lt TA lt 125 C for extended Conditions ea Device Characteristics Min Typt Max Units 9 VDD Note DO10E Supply Current IDD 9 TBD uA 2 0 Fosc 32kHz 18 TBD uA ao LP Oscillator mode 35 TBD uA 5 0 D011E 110 TBD uA 2 0 Fosc 1 MHz 190 TBD uA 3 0 XT Oscillator mode 330 TBD uA 5 0 D012E 220 TBD uA 2 0 Fosc 4 MHz 370 TBD uA 3 0 XT Oscillator mode 0 6 TBD mA 5 0 D013E 70 TBD uA 2 0 Fosc 1 MHz 140 TBD UA 3 0 EC Oscillator mode 260 TBD UA 5 0 DO14E 180 TBD uA 2 0 Fosc 4 MHz 32
199. ay flow through power devices QC and QD see Figure 11 9 for the duration of t The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward If changing PWM direction at high duty cycle is required for an application one of the following requirements must be met 1 Reduce PWM duty cycle for one PWM period before changing directions 2 Use switch drivers that can drive the switches off faster than they can drive them on Other options to prevent shoot through current may exist 2005 Microchip Technology Inc Preliminary DS41262A page 121 PIC16F685 687 689 690 FIGURE 11 10 PWM DIRECTION CHANGE Signal Period gt Period P1A Active High P1B Active High P1C Active High i P1D Active High mem z Note 1 The direction bit in the ECCP Control register CCP1CON lt 7 gt is written any time during the PWM cycle 2 When changing directions the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 Tosc 16 Tosc or 64 Tosc depending on the Timer2 prescaler value The modulated P1B and P1D signals are inactive at this time FIGURE 11 11 PWM DIRECTION CHANGE AT NEAR 100 DUTY CYCLE Forward Period ti Reverse Period a YA Aa gt PIA D ot 4 P1B ita DC gt Pic i PiD is DC gt i
200. ays disabled As a result the latch output must be initialized before the outputs are made available to the output pins Additionally the applicable TRIS bits of the corresponding ports must be set to output 0 and the respective comparator output enable bits C1OE and or C2OE must be initialized in order to make the latch outputs available on the output pins The four different configurations available for the SR latch are shown in Figure 8 5 and the SR lt 1 0 gt bits in the SRCON register Register 8 4 control whether or not the latch is enabled The latch enable state is completely independent of the enable state for the comparators REGISTER 8 4 R W 0 R W 0 R W 0 The SR latch is a Reset dominant latch that does not depend on a clock source Each of the Set and Reset inputs are active high The Set input is driven by the C1 comparator output following the inversion gate which is accounted for with the C1INV bit If the effective com parator output signal is low then the latch can be set by writing 1 to the PULSS bit Conversely the Reset input is driven by the C1 comparator output following the inversion gate which is accounted for with the C2INV bit If the comparator output signal is low then the latch can be reset by writing 1 to the PULSR bit SRCON SR LATCH CONTROL REGISTER ADDRESS 19Eh R W 0 R W 0 R W 0 U 0 U 0 SR10 sro C1SEN bit 7 C2REN PULSS PULSR bit 7 6 SR lt 1 0 gt
201. before the transfer was received In this case the SSPSR register value is not loaded into the SSPBUF but bit SSPIF PIR1 lt 3 gt is set Table 13 3 shows the results of when a data transfer byte is received given the status of bits BF and SSPOV The shaded cells show the condition where user software did not properly clear the overflow condition Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software The SCL clock input must have a minimum high and low for proper operation For high and low times of the CC specification as well as the reguirements of the SSP module see Section 17 0 Electrical Specifications DS41262A page 164 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 13 12 1 ADDRESSING Once the SSP module has been enabled it waits for a Start condition to occur Following the Start condition the 8 bits are shifted into the SSPSR register All incoming bits are sampled with the rising edge of the clock SCL line The value of register SSPSR lt 7 1 gt is compared to the value of the SSPADD register The address is compared on the falling edge of the eighth clock SCL pulse If the addresses match and the BF and SSPOV bits are clear the following events occur a The SSPSR register value is loaded into the SSPBUF register b The buffer full bit BF is set c An ACK pulse is generated d SSP interrupt flag bit SSPIF PIR1 lt 3
202. ber is the version number eg DS30000A is version A of document DS30000 Errata An errata sheet describing minor operational differences from the data sheet and recommended workarounds may exist for current devices As device documentation issues become known to us we will publish an errata sheet The errata will specify the revision of silicon and revision of document to which it applies To determine if an errata sheet exists for a particular device please check with one of the following Microchip s Worldwide Web site http www microchip com Your local Microchip sales office see last page When contacting a sales office please specify which device revision of silicon and data sheet include literature number you are using Customer Notification System Register on our web site at www microchip com to receive the most current information on all of our products DS41262A page 4 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 1 0 DEVICE OVERVIEW Block Diagrams and pinout descriptions of the devices are as follows The PIC16F685 687 689 690 devices are covered by this data sheet They are available in 20 pin PDIP O 1 1 Table 121 SOIC TSSOP and OFN packages e PIC16F687 PIC16F689 Figure 1 2 Table 1 2 e PIC16F690 Figure 1 3 Table 1 3
203. ced back in register f Register f aa gt C SLEEP Syntax Operands Operation Status Affected Description SUBLW Syntax Operands Operation Status Affected Description SUBWF Syntax Operands Operation Status Affected Description Enter Sleep mode label SLEEP None 00h WDT 0 WDT prescaler 15TO 0 PD TO PD The power down Status bit PD is cleared Time out Status bit TO is set Watchdog Timer and its prescaler are cleared The processor is put into Sleep mode with the oscillator stopped Subtract W from literal label SUBLW k 0 lt k lt 255 k W W C DC 7 The W register is subtracted 2 s complement method from the eight bit literal kK The result is placed in the W register Subtract W from f label SUBWF fd 0 lt f lt 127 de 0 1 f W gt destination C DC Z Subtract 2 s complement method W register from register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f DS41262A page 200 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 SWAPF Syntax Operands Operation Status Affected Description XORLW Syntax Operands Operation Status Affected Description XORWF Syntax Operands Operation Status Affected Description Swap Nibbles in
204. cept when Address to m ad updating EEPROM The WREN bit is not cleared BSF STATUS RPO Bank 3 by hardware BCF EECON1 EEPGD Point to DATA After a write sequence has been initiated clearing the Memory WREN bit will not affect this write cycle The WR bit will BEE ECON Es BD FEE Read be inhibited from being set unless the WREN bit is set BCF STATUS RP1 Bank 2 MOVF EEDAT W W EEDAT At the completion of the write cycle the WR bit is BCF STATUS RPO Bank 0 cleared in hardware and the EE Write Complete Interrupt Flag bit EEIF is set The user can either enable this interrupt or poll this bit EEIF must be cleared by software EXAMPLE 10 2 DATA EEPROM WRITE BCF STATUS RPO Bank 2 BSF STATUS RP1 i MOVLW DATA EE ADDR E MOVWF EEADR Data Memory Address to write MOVLW DATA EE DATA S MOVWE EEDAT Data Memory Value to write BSE STATUS RPO Bank 3 BCF EECON1 EEPGD Point to DATA memory BSF EECON1 WREN Enable writes BCF INTCON GIE Disable INTs o 8 MOVLW 55h E 25 MOVWF EECON2 Write 55h 33 wun AA too MOVWE EECON2 Write AAh BSF EECON1 WR Set WR bit to begin write BSF INTCON GIE Enable INTs SLEEP Wait for interrupt to signal write complete BCF EECON1 WREN Disable writes BCF STATUS RPO Bank 0 DS41262A page 108 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 10 1 4 READING THE FLASH PROGRAM MEMORY To read a program memory location the user must write two bytes of the address
205. d device Note The ANSEL 11Eh register must be initialized to configure an analog channel as a digital input Pins configured as analog inputs will read o REGISTER 5 1 OPTION_REG OPTION REGISTER ADDRESS 81h OR 181h R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 RABPU INTEDG TOCS TOSE PSA PS2 PS1 PSO bit 7 bit 0 bit 7 RABPU PORTA PORTB Pull up Enable bit 1 PORTA PORTB pull ups are disabled 0 PORTA PORTB pull ups are enabled by individual port latch values bit 6 INTEDG Interrupt Edge Select bit 1 Interrupt on rising edge of RA2 AN2 TOCKI INT C10UT pin 0 Interrupt on falling edge of RA2 AN2 TOCKI INT C10UT pin bit 5 TOCS TMRO Clock Source Select bit 1 Transition on RA2 AN2 TOCKI INT C1OUT pin 0 Internal instruction cycle clock CLKOUT bit 4 TOSE TMRO Source Edge Select bit 1 Increment on high to low transition on RA2 AN2 TOCKI INT C1O0UT pin 0 Increment on low to high transition on RA2 AN2 TOCKI INT C1OUT pin bit 3 PSA Prescaler Assignment bit 1 Prescaler is assigned to the WDT 0 Prescaler is assigned to the Timer0 module bit 2 0 PS lt 2 0 gt Prescaler Rate Select bits BIT VALUE TMRO RATE WDT RATE 000 1 2 1 1 001 1 4 1 2 010 1 8 1 4 011 1 16 1 8 100 1 32 1 16 101 1 64 1 32 110 1 128 1 64 111 1 256 1 128 Note 1 A dedicated 16 bit WDT postscaler is available See Section 14 5 Watchdog Timer WDT for more i
206. d mode DC bus specification before the SCL line is released DS41262A page 232 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 TABLE 17 15 PIC16F685 687 689 690 A D CONVERTER CHARACTERISTICS Standard Operating Conditions unless otherwise stated Operating Temperature 40 C lt TA lt 125 C Fail Sym Characteristic Min TypT Max Units Conditions A01 NR Resolution o 10 bits bit AOS EIL Integral Error o o 1 LSb VREF 5 0V A04 EpL Differential Error 1 LSb No missing codes to 10 bits VREF 5 0V A05 EFs Full scale Range 2 2 5 5 V A06 Eorr Offset Error 1 LSb VREF 5 0V A07 EGN Gain Error SC 1 LSb VREF 5 0V A10 Monotonicity guaranteed Vss lt VAIN lt VREF A20 VREF Reference Voltage 2 0 VDD 40 3 V A25 VAIN Analog Input Vss VREF V Voltage A30 ZAIN Recommended 10 kQ Impedance of Analog Voltage Source A50 IREF VREF Input E E 5 uA During VAIN acquisition Current 150 uA During A D conversion cycle These parameters are characterized but not tested t Data in Typ column is at 5 0V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 The A D conversion result never decreases with an increase in the input voltage and has no missing codes 2 VREF current is from
207. derations Using Auto Wake Up The auto wake up function is edge sensitive To prevent data errors or framing errors the data following the Break should be all o s until the baud clock is stable If the LP XT or HS oscillators are used the oscillator start up time will affect the amount of time the application must wait before receiving valid data FIGURE 12 7 AUTO WAKE UP BIT WUE TIMINGS DURING NORMAL OPERATION 01 02 0304 01 02 0304 Q1 Q2 Q3 Q4 01 02 03104 01 02 0304 01 02 03104 01 02103 04 01 02 0304 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 GE Bit Set by User Auto Cleared WUE bit a N RX DT Line RCIF 1 1 1 1 S 1 4 1 F D D i S I i Cleared due to User Read of RCREG f i Note The EUSART remains in IDLE while the WUE bit is set FIGURE 12 8 AUTO WAKE UP BIT WUE TIMINGS DURING SLEEP OO 01 02 0304 COOC Q1 lo2 0310401 02 03104 01 02 03 0401 02103104 0 1102103104 OCT UU UU LVI UI UV Di Set by User 1 i rod Pa Leen Aut Cleared WUE bit i ina RX DT Line Za BS i RCIF 1 1 1 1 L L A 1 i A Cleared due to User Read of RCREG Sleep Command Executed Sleep Ends DS41262A page 146 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 12 3 5 BREAK CHARACTER SEOUENCE The EUSART module has the capability of sending the special Break character seguences that are reguired by the LIN bus standard
208. different than intended For example CLRF STATUS will clear the upper three bits and set the Z bit This leaves the Status register as 000u uluu where u unchanged It is recommended therefore that only BCF BSF SWAPF and MOVWF instructions are used to alter the Status register because these instructions do not affect any Status bits For other instructions not affecting any DC or C bits then the write to these three bits is disabled These bits are set or cleared according to the device logic Furthermore the TO and PD bits are not Note 1 The C and DC bits operate as a Borrow and Digit Borrow out bit respectively in subtraction See the SUBLW and SUBWF instructions for examples Status bits see the Instruction Set Summary REGISTER 2 1 STATUS STATUS REGISTER ADDRESS 03h 83h 103h OR 183h R W 0 R W 0 R W 0 R 1 R 1 R W x R W x R W x IRP D I RPO TO PD Z bc c bit 7 bit 0 bit 7 IRP Register Bank Select bit used for indirect addressing 1 Bank 2 3 100h 1FFh 0 Bank 0 1 00h FFh bit 6 5 RP lt 1 0 gt Register Bank Select bits used for direct addressing 00 Bank 0 00h 7Fh 01 Bank 1 80h FFh 10 Bank 2 100h 17Fh 11 Bank 3 180h 1FFh bit 4 TO Time out bit 1 After power up CLRWDT instruction or SLEEP instruction 0 AWDT time out occurred bit 3 PD Power down bit 1 After power up or by the CLRWDT instruction 0 By execution
209. ding on the application Note 1 When the SPI is in Slave mode with SS pin control enabled SSPCON lt 3 0 gt 0100 the SPI module will reset if the SS pin is set to VDD 2 If the SPI is used in Slave Mode with CKE set then the SS pin control must be enabled When the SPI module resets the bit counter is forced to 0 This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit To emulate two wire communication the SDO pin can be connected to the SDI pin When the SPI needs to operate as a receiver the SDO pin can be configured as an input This disables transmissions from the SDO The SDI can always be left as an input SDI function since it cannot create a bus conflict FIGURE 13 4 SLAVE SYNCHRONIZATION WAVEFORM se ds J SCK sS CKP 0 CKE 0 i i i SCK l i i i CKP 1 CKE 0 l ie Write to i i SSPBUF J l SDO SE SMP 0 ae e DADE KD SSPSR to i bit7 bit7 Sample At E E SE i i SSPIF Interrupt l i Flag SSPBUF 4 Next O4 Cycle after Q24 2005 Microchip Technology Inc Preliminary DS41262A page 161 PIC16F685 687 689 690 FIGURE 13 5 SPI MODE WAVEFORM SLAVE MODE WITH CKE 0 ee Ss
210. e By selecting BOREN lt 1 0 gt the BOR is automatically disabled in Sleep to conserve power and enabled on wake up In this mode the SBOREN bit is disabled See Register 14 1 for the Configuration Word definition If Vpp falls below VBOR for greater than parameter TBOR see Section 17 0 Electrical Specifications the Brown out situation will reset the device This will occur regardless of VDD slew rate A Reset is not insured to occur if VDD falls below VBOR for less than parameter TBOR On any Reset Power on Brown out Reset Watchdog Timer etc the chip will remain in Reset until VDD rises above VBOR see Figure 14 2 The Power up Timer will now be invoked if enabled and will keep the chip in Reset an additional 64 ms Note The Power up Timer is enabled by the PWRTE bit in the Configuration Word register If VDD drops below VBOR while the Power up Timer is running the chip will go back into a Brown out Reset and the Power up Timer will be re initialized Once VDD rises above VBorR the Power up Timer will execute a 64 ms Reset FIGURE 14 2 BROWN OUT SITUATIONS VDD EE Z VBOR i Internal E Reset 64 ms VDD e Ee a SE VBOR EC Internal lt 64 ms Reset 64 mst VDD I I Internal L Reset 64 ms Note 1 64 ms delay only if PWRTE bit is programmed to o 2005 Microchip Technology Inc Preliminary DS41262A page 177
211. e PORTC pin an output i e put the contents of the output an analog channel as a digital input Pins latch on the selected pin Example 4 4 shows how to configured as analog inputs will read o initialize PORTC Reading the PORTC register Register 4 9 reads the status of the pins whereas writing to it will EXAMPLE 4 4 INITIALIZING PORTC write to the port latch All write operations are read k BCF STATUS RPO Bank 0 modify write operations Therefore a write to a port BCF STATUS RP1 implies that the port pins are read this value is modified CLRF PORTC Init PORTC and then written to the port data latch BSF STATUS RP1 Bank 2 CLRF ANSEL digital I O BSF STATUS RPO Bank 1 BCF STATUS RP1 e MOVLW och Set RC lt 3 2 gt as inputs MOVWF TRISC jand set RC lt 5 4 1 0 gt as outputs BCF STATUS RPO Bank 0 REGISTER 4 9 PORTC PORTC REGISTER ADDRESS 07h OR 107h R W x R W x R W x R W x R W x R W x R W x R W x RC7 RC6 RC5 RC4 RC3 RC2 RC1 RCO bit 7 bit 0 bit 7 0 RC lt 7 0 gt PORTC General Purpose I O Pin bits 1 Port pin is gt VIH 0 Port pin is lt VIL Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown REGISTER 4 10 TRISC TRI STATE PORTC REGISTER ADDRESS 87h OR 187h R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 TRISC7 TRISC6 TRISC5
212. e SSPBUF is empty Transmit CC mode only 1 Transmit in progress SSPBUF is full 0 Transmit complete SSPBUF is empty Note 1 PIC16F687 PIC16F689 PIC16F690 only Legend R Readable bit W Writable bit n Value at POR 1 Bit is set 0 Bit is cleared U Unimplemented bit read as 0 x Bit is unknown DS41262A page 156 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 REGISTER 13 2 SSPCON SYNC SERIAL PORT CONTROL REGISTER ADDRESS 14h R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 WCOL SSPOV SSPEN CKP SSPM3t2 sspm2 sen ssPmo bit 7 bit 0 bit 7 WCOL Write Collision Detect bit 1 The SSPBUF register is written while it is still transmitting the previous word must be cleared in software 0 No collision bit 6 SSPOV Receive Overflow Indicator bit In SPI mode 1 Anew byte is received while the SSPBUF register is still holding the previous data In case of overflow the data in SSPSR is lost Overflow can only occur in Slave mode The user must read the SSPBUF even if only transmitting data to avoid setting overflow In Master mode the overflow bit is not set since each new reception and transmission is initiated by writing to the SSPBUF register 0 No overflow In 2CTM mode 1 Abyteis received while the SSPBUF register is still holding the previous byte SSPOV is a don t care in Tra
213. e SSPBUF register Then the Buffer Full Status bit BF SSPSTAT lt 0 gt and the interrupt flag bit SSPIF are set This double buffering of the received data SSPBUF allows the next byte to start reception before reading the data that was just received Any write to the SSPBUF register during transmission reception of data will be ignored and the Write Collision Detect bit WCOL SSPCON lt 7 gt will be set User software must clear the WCOL bit so that it can be determined if the following write s to the SSPBUF register completed successfully When the application software is expecting to receive valid data the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF Buffer Full bit BF SSPSTAT lt 0 gt indicates when SSPBUF has been loaded with the received data transmission is complete When the SSPBUF is read the BF bit is cleared This data may be irrelevant if the SPI is only a transmitter Generally the SSP interrupt is used to determine when the transmission reception has completed The SSPBUF must be read and or written If the interrupt method is not going to be used then software polling can be done to ensure that a write collision does not occur Example 13 1 shows the loading of the SSPBUF SSPSR for data transmission The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register Additionally the SSP Status register SSPSTAT indicates
214. e the SDO output could be disabled programmed as an input The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate As each byte is received it will be loaded into the SSPBUF register as if a normal received byte interrupts and Status bits appropriately set This could be useful in receiver applications as a Line Activity Monitor mode FIGURE 13 3 Write to The clock polarity is selected by appropriately programming the CKP bit SSPCON lt 4 gt This then would give waveforms for SPI communication as shown in Figure 13 3 Figure 13 5 and Figure 13 6 where the MSB is transmitted first In Master mode the SPI clock rate bit rate is user programmable to be one of the following e Fosc 4 or Toy e Fosc 16 or 4 Toy e Fosc 64 or 16 Toy e Timer output 2 This allows a maximum data rate at 40 MHz of 10 Mbps Figure 13 3 shows the waveforms for Master mode When the CKE bit is set the SDO data is valid before there is a clock edge on SCK The change of the input sample is shown based on the state of the SMP bit The time when the SSPBUF is loaded with the received data is shown SPI MODE WAVEFORM MASTER MODE SSPBUF J SCK 1 a m CKP 0 SCK CKE 0 RR Ly LH LH CKP 1 CKE 0 4 Clock Modes SCK CKP 0 CKE 1 SCK CKP 1 CKE 1 SE X bit7 X bite X bit
215. e Bis SCK SCL pin is configurable to function as one of the D Q Von following WR T K a J m Weak a general purpose UO OE ESS Ewes e a SPI clock RD ee L RABPU an IC clock WPUB Note 1 SCK and SCL are available on PIC16F687 PIC16F689 PIC16F690 only Lie a SSPEN VDD WR 1 PORTETP S a d D Lag I O Pin ID Q e Vss Q D h EN Q3 Q D N Interrupt EN nterrupt on Change ae RD PORTB To SSPSR Aa Available on PIC16F687 PIC16F689 PIC16F690 only 2005 Microchip Technology Inc Preliminary DS41262A page 61 PIC16F685 687 689 690 44 34 RB7 TX CK FIGURE 4 10 BLOCK DIAGRAM OF RB7 Figure 4 10 shows the diagram for this pin The RB7 TX CK D pin is configurable to function as one of the Data BUS J WA following T WR CK amp e a general purpose I O WPUB TP gt SE Neat an asynchronous serial output Se a asynchronous clock I O WPUB SPEN Note 1 TX and CK are available on PIC16F687 men PIC16F689 PIC16F690 only a RABPU SYNC EUSART CKN EUSART TX 0 VDD amp D o e UO Pin Vss EN Q3 EN Interrupt on Change RD PORTB Available on PIC16F687 PIC16F689 PIC 16F690 only DS41262A page 62 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 TABLE 4 2 SUMMARY OF
216. e PIC16F685 687 689 690 The voltage referred to as the comparator reference CVREF is a variable voltage based on VDD The voltage referred to as the VP6 reference is a fixed voltage derived from a stable band gap source Each source may be individually routed internally to the comparators The VRCON register Register 8 5 controls the voltage reference module shown in Figure 8 5 8 4 1 CONFIGURING THE VOLTAGE REFERENCE The voltage reference can output 32 distinct voltage levels 16 in a high range and 16 in a low range The following eguation determines the output voltages EQUATION 8 1 VOLTAGE REFERENCE OUTPUT VOLTAGE VRR 1 low range CVREF VR lt 3 0 gt 24 x VDD VRR 0 high range CVREF VDD 4 VR lt 3 0 gt X VDD 32 8 4 2 VOLTAGE REFERENCE ACCURACY ERROR The full range of Vss to VDD cannot be realized due to the construction of the module The transistors on the top and bottom of the resistor ladder network Figure 8 5 keep CVREF from approaching Vss or VDD The exception is when the module is disabled by clearing CIVREN and C2VREN bits VRCON lt 7 6 gt When disabled the reference voltage is Vss when VR lt 3 0 gt is 0000 and the VRR VRCON lt 5 gt bit is set This allows the comparators to detect a zero crossing and not consume CVREF module current The voltage reference is VDD derived and therefore the CVREF output changes with fluctuations in VDD The tested absolute accuracy of
217. e PWM output will always produce a complete PWM waveform Figures 11 12 and 11 13 illustrates the timing diagrams of the PWM steering depending on the STRSYNC set ting lt PWM Period gt P1 lt D A gt Port Data y X Port Data Pin PWM FIGURE 11 13 STEERING EVENT AT BEGINNING OF INSTRUCTION STRSYNC 1 L LI P1 lt D A gt Port Data 1 1 1 Port Data Pin PWM 2005 Microchip Technology Inc Preliminary DS41262A page 125 PIC16F685 687 689 690 11 3 7 PROGRAMMABLE DEAD BAND DELAY In half bridge applications where all power switches are modulated at the PWM freguency at all times the power switches normally reguire more time to turn off than to turn on lf both the upper and lower power switches are switched at the same time one turned on and the other turned off both switches may be on for a short period of time until one switch completely turns off During this brief interval a very high current shoot through current may flow through both power switches shorting the bridge supply To avoid this potentially destructive shoot through current from flowing during switching turning on either of the power switches is normally delayed to allow the other switch to completely turn off In the Half bridge Output mode a digitally programmable dead band
218. e Power Glitch Software Malfunction 10 4 Data EEPROM Operation During Code Protect Data memory can be code protected by programming the CPD bit in the Configuration Word register Register 14 1 to o When the data memory is code protected the CPU is able to read and write data to the data EEPROM It is recommended to code protect the program memory when code protecting data memory This prevents anyone from programming zeroes over the existing code which will execute as NOPs to reach an added routine programmed in unused program memory which outputs the contents of data memory Programming unused locations in program memory to 0 will also help prevent data memory code protection from becoming breached 2005 Microchip Technology Inc Preliminary DS41262A page 111 PIC16F685 687 689 690 TABLE 10 1 REGISTERS BITS ASSOCIATED WITH DATA EEPROM Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR BOR Resets OBh 8Bh INTCON GIE PEIE TOIE INTE RABIE TOIF INTF RABIF 0000 000x 0000 000x 10Bh 18Bh ODh PIR2 OSFIF C2IF C1IF EEIF 0000 0000 8Dh PIE2 OSFIE C2IE C1IE EEIE 0000 0000 10Eh EEDATH EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATHO 00 0000 00 0000 10Fh EEADRH 1 EEADRH3 EEADRH2 EEADRH1 EEADRHO 0000
219. e Select bit 1 External clock from T1CKI pin on the rising edge 0 Internal clock Fosc 4 bit 0 TMRION Timer1 On bit 1 Enables Timer1 0 Stops Timer1 Note 1 T1GINV bit inverts the Timer1 gate logic regardless of source 2 TMRIGE bit must be set to use either T1G pin or C2OUT as selected by the T1GSS bit CM2CON1 lt 1 gt as a Timer1 gate source Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 75 PIC16F685 687 689 690 6 5 Timer1 Operation in Asynchronous Counter Mode If control bit TISYNC T1CON lt 2 gt is set the external clock input is not synchronized The timer continues to increment asynchronous to the internal phase clocks The timer will continue to run during Sleep and can generate an interrupt on overflow which will wake up the processor However special precautions in software are needed to read write the timer see Section 6 5 1 Reading and Writing Timeri in Asynchronous Counter Mode Note The ANSEL 11Eh register must be initialized to configure an analog channel as a digital input Pins configured as analog inputs will read o 6 5 1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensu
220. e TMR1IF bit in the Interrupt Service Routine Note The TMR1H TTMRI1L register pair and the TMRIIF bit should be cleared before enabling interrupts 6 3 Timer1 Prescaler Timer1 has four prescaler options allowing 1 2 4 or 8 divisions of the clock input The TICKPS bits T1CON lt 5 4 gt control the prescale counter The prescale counter is not directly readable or writable however the prescaler counter is cleared upon a write to TMR1H or TMRIL 6 4 Timer1 Gate Timeri gate source is software configurable to be the T1G pin or the output of Comparator 2 This allows the device to directly time external events using T1G or analog events using Comparator 2 See CM2CON1 Register 8 3 for selecting the Timer1 gate source This feature can simplify the software for a Delta Sigma A D converter and many other applications For more information on Delta Sigma A D converters see the Microchip web site www microchip com Note TMRI1GE bit T1CON lt 6 gt must be set to use either T1G or C2OUT as the Timer gate source See Register 8 3 for more information on selecting the Timer1 gate source Timer1 gate can be inverted using the T1GINV bit T1CON lt 7 gt whether it originates from the T1G pin or Comparator 2 output This configures Timer1 to measure either the active high or active low time between events FIGURE 6 2 TIMER1 INCREMENTI
221. e derived from the HFINTOSC via the postscaler and multiplexer DS41262A page 40 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 3 5 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select SCS bit 3 5 1 SYSTEM CLOCK SELECT SCS BIT The System Clock Select SCS bit OSCCON lt 0 gt selects the system clock source that is used for the CPU and peripherals When SCS 0 the system clock source is determined by configuration of the FOSC lt 2 0 gt bits in the Configuration Word register CONFIG When SCS 1 the system clock source is chosen by the internal oscillator frequency selected by the IRCF bits After a Reset SCS is always cleared Note Any automatic clock switch which may occur from Two Speed Startup or Fail Safe Clock Monitor does not update the SCS bit The user can monitor the OSTS OSCCON lt 3 gt to determine the current system clock source 3 5 2 OSCILLATOR START UP TIME OUT STATUS BIT The Oscillator Start up Time out Status OSTS bit OSCCON lt 3 gt indicates whether the system clock is running from the external clock source as defined by the FOSC bits or from internal clock source In particular OSTS indicates that the Oscillator Start up Timer OST has timed out for LP XT or HS modes 3 6 Two Speed Clock Start up Mode Two Speed Start up mode provides
222. e up from Sleep through e External Reset e Watchdog Timer Wake up An interrupt Several oscillator options are also made available to allow the part to fit the application The INTOSC option saves system cost while the LP crystal option saves power A set of configuration bits are used to select various options see Register 14 1 O 2005 Microchip Technology Inc Preliminary DS41262A page 173 PIC16F685 687 689 690 14 1 Configuration Bits Note Address 2007h is beyond the user program memory space It belongs to the special configuration memory space 2000h 3FFFh which can be accessed only during programming See PIC12F6XX 16FEXX Memory Programming Specification DS41 204 for more information The configuration bits can be programmed read as o or left unprogrammed read as 1 to select various device configurations as shown in Register 14 1 These bits are mapped in program memory location 2007h REGISTER 14 1 CONFIG CONFIGURATION WORD ADDRESS 2007h Reserved Reserved FCMEN IESO BOREN1 D BORENO D CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSCO bit 13 bit O bit 13 12 Reserved Reserved bits Do Not Use bit 11 FCMEN Fail Safe Clock Monitor Enabled bit 1 Fail Safe Clock Monitor is enabled o Fail Safe Clock Monitor is disabled bit 10 IESO Internal External Switchover bit Internal External Switchover mode is
223. ed into the SPI Transmit Receive Shift register 0 0 6 ii When all 8 bits have been received the SSP interrupt flag bit will be set and if enabled will wake the device 0 1 2 q from Sleep 1 0 1 1 REN 1 0 13 9 Effects of a Reset There is also a SMP bit which controls when the data is A Reset disables the SSP module and terminates the sampled current transfer TABLE 13 2 REGISTERS ASSOCIATED WITH SPI OPERATION Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR all other BOR Resets OBh 8Bh INTCON GIE PEIE TOIE INTE RABIE TOIF INTF RABIF 0000 000x 0000 000x 10Bh 18Bh 0Ch PIRI ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 000 0000 000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer Transmit Register XXXX XXXX uuuu UUUU 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO 0000 0000 0000 0000 86h 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 1111 87h 187h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISCO 1111 1111 1111 1111 8Ch PIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR11E 000 0000 000 0000 94h SSPSTAT SMP CKE D A P S RW UA BF 0000 0000 0000 0000 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used by the SSP in SPI mode Note 1 PIC16F687 PIC16F689 PIC16
224. ed x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 107 PIC16F685 687 689 690 10 1 2 MEMORY To read a data memory location the user must write the address to the EEADR register clear the EEPGD control bit EECON1 lt 7 gt and then set control bit RD EECON1 lt 0 gt The data is cycle in the EEDAT register in the next instruction EEDAT will hold this value until another read or until it is written to by the user during a write operation EXAMPLE 10 1 READING THE DATA EEPROM DATA EEPROM READ 10 1 3 WRITING TO THE DATA EEPROM MEMORY To write an EEPROM data location the user must first write the address to the EEADR register and the data to the EEDAT register Then the user must follow a available in the very next specific seguence to initiate the write for each byte therefore it can be read The write will not initiate if the above seguence is not followed exactly write 55h to EECON2 write AAh to EECON2 then set WR bit for each byte Interrupts should be disabled during this code segment Additionally the WREN bit in EECON1 must be set to enable write This mechanism prevents accidental BSP STATUS REL iBank 2 writes to data EEPROM due to errant unexpected BEF STATUS REO i code execution i e lost programs The user should MOVLW DATA EE ADDR E d kee eege E Data Memory keep the WREN bit clear at all times ex
225. eeeeeeeeeeegueeseeedseseeeeeeeneneseeeeseseeeeeeseneees 300 mA Maximum current into VDD Din 250 mA Input clamp current lik Vi lt O or VI gt VDD ssessssessssesessissssesessesessceseseuessesessosssseseostsrscescoscsesessesseseososestesrssrsesesseseeses 20 mA Output clamp current IOK Vo lt 0 or VO zNDD 20 mA Maximum output current sunk by any I O gin 25 mA Maximum output current sourced by any I O pin cere eaeeeneeseeeeseaeeeeesaeeeaeeseeeeeaeeeeeeees 25 mA Maximum current sunk by PORTA PORTB and PORTC combined 200 mA Maximum current sourced PORTA PORTB and PORTC combined 200 mA Note 1 Power dissipation is calculated as follows PDIS VDD x IDD lOH VDD VOH x IOH X VOL x IOL NOTICE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Note Voltage spikes below Vss at the MCLR pin inducing currents greater than 80 mA may cause latch up Thus a series resistor of 50 100 should be used when applying a low level to the MCLR pin rather than pulling this pin directly to Vss 2005 Microchip Technology Inc P
226. egister 1 Comparator 2 has one additional feature its output can be synchronized to the Timer1 clock input Setting C2SYNC CM2CON1 lt 0 gt synchronizes the output of Comparator 2 to the falling edge of Timer1 s clock input see Figure 8 2 and Register 8 3 The CM2CON1 register also contains mirror copies of both comparator outputs MC1OUT and MC2OUT CM2CON1 lt 7 6 gt The ability to read both outputs simultaneously from a single register eliminates the timing skew of reading separate registers Note 1 Obtaining the status of C1OUT or COOUT by reading CM2CON1 does not affect the comparator interrupt mismatch registers REGISTER 8 3 CM2CON1 COMPARATOR 2 CONTROL REGISTER 1 ADDRESS 11Bh R 0 HO U 0 U 0 U 0 U 0 R W 1 R W 0 MC10UT MC2OUT TIGSS C2SYNC bit 7 bit O bit 7 MC10UT Mirror Copy of C1OUT bit CMICONO lt 6 gt bit 6 MC20OUT Mirror Copy of C2OUT bit CM2CONO lt 6 gt bit 5 2 Unimplemented Read as oi bit 1 T1GSS Timer1 Gate Source Select bit 1 Timer1 gate source is RA4 AN3 T1G OSC2 CLKOUT 0 Timer1 gate source is C2OUT bit 0 C2SYNC C2 Output Synchronous Mode bit 1 C2 output is synchronous to falling edge of TMR1 clock 0 C2 output is asynchronous Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown DS41262A page 8
227. eived SSPSR SSPBUF aida SSP Interrupt occurs BF SSPOV if enabled 0 0 Yes Yes Yes 1 0 No No Yes T 1 No No Yes 0 1 No No Yes Note Shaded cells show the conditions where the user software did not properly clear the overflow condition 2005 Microchip Technology Inc Preliminary DS41262A page 165 PIC16F685 687 689 6 13 122 RECEPTION When the R W bit of the address byte is clear and an address match occurs the R W bit of the SSPSTAT register is cleared The received address is loaded into the SSPBUF register When the address byte overflow condition exists then no Acknowledge ACK pulse is given An overflow condition is defined as either bit BF SSPSTAT lt 0 gt is set or bit SSPOV SSPCON lt 6 gt is set This is an error condition due to the user s firmware An SSP interrupt is generated for each data transfer byte Flag bit SSPIF PIR1 lt 3 gt must be cleared in software The SSPSTAT register is used to determine the status of the byte 90 FIGURE 13 8 2CTM WAVEFORMS FOR RECEPTION 7 BIT ADDRESS RW 0 Receiving Address ACK Receiving Data ACK Receiving Data ACK BF SSPSTAT lt 0 gt I SSPBU SCL EA PIA SIA Sie A MAIA ASIA fa JAAA PAIN SAIA I P ke ol i SSPIF PIR1 lt 3 gt lt Cleared in software 1 i Bus Master I terminates I transfer F register is read SSPOV SSPCON lt 6 gt Bit SSPOV is set because the SSPBUF register
228. er 4 3 Each weak pull up is automatically turned off when the port pin is configured as an output The pull ups are disabled on a Power on Reset by the RABPU bit OPTION_REG lt 7 gt A weak pull up is automatically enabled for RA3 when configured as MCLR and disabled when RA3 is an I O There is no software control of the MCLR pull up REGISTER 4 1 PORTA PORTA REGISTER ADDRESS 05h OR 105h U 0 U 0 R W x R W x R W x R W x R W x R W x RA5 RA4 RA3 RA2 RA1 RAO bit 7 bit 0 bit 7 6 Unimplemented Read as o bit 5 0 RA lt 5 0 gt PORTA I O Pin bit 1 Port pin is gt VIH 0 Port pin is lt VIL Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 47 PIC16F685 687 689 690 REGISTER 4 2 REGISTER 4 3 bit 7 6 bit 5 4 bit 3 bit 2 0 TRISA PORTA TRI STATE PORTA REGISTER ADDRESS 85h OR 185h U 0 U 0 R W 1 R W 1 R 1 R W 1 R W 1 R W 1 TRISAS TRISA4 TRISA3 TRISA2 TRISA1 TRISAO bit 7 Unimplemented Read as oi TRISA lt 5 0 gt PORTA Tri State Control bit 1 PORTA pin configured as an input tri stated 0 PORTA pin configured as an output Note bit 0 TRISA lt 5 4 gt always reads 1 in XT HS and LP OSC modes Legend R
229. erface used to communicate with other peripheral or Internal microcontroller devices These peripheral devices may Data Bus be serial EEPROMs shift registers display drivers noe ae Write A D converters etc The SSP module can operate in one of two modes SSPBUF reg mu Serial Peripheral Interface SPITM R E eet I2C TM RB4 AN10 Inter Integrated Circuit ICC TM SDISDA Refer to Application Note AN578 Use of the SSP gt mas SSPSR Module in the Multi Master Environment DS00578 E bro e Shift I RA Clock 13 1 SPI Mode AN SS 5 UWA A RC7 AN9 Peripheral OE This section contains register definitions and operational SDO characteristics of the SPI module The SPI mode allows 8 bits of data to be synchronously SS Gi transmitted and received simultaneously To accomplish RCEJANS communication typically three pins are used SS Edge Serial Data Out SDO RC7 AN9 SDO gt Select Serial Data In SDI RB4 AN10 SDI SDA 2 Serial Clock SCK RB6 SCK SCL Clock Select Additionally a fourth pin may be used when in a Slave SSPM lt 3 0 gt mode of operation at TMR2 Output Slave Select SS RC6 AN8 SS Is Edge Select TRISB lt 6 gt Note 1 When the SPI is in Slave mode with SS pin control enabled SSPCON lt 3 0 gt RB6 SCK 0100 the SPI module will reset if the SS SCL pin is set to VDD Prescaler
230. ers with nanoWatt Technology High Performance RISC CPU Only 35 instructions to learn All single cycle instructions except branches e Operating speed DC 20 MH oscillator clock input DC 200 ns instruction cycle Interrupt capability 8 level deep hardware stack Direct Indirect and Relative Addressing modes Special Microcontroller Features Precision Internal Oscillator Factory calibrated to 1 Software selectable frequency range of 8 MHz to 32 kHz Software tunable Two Speed Start up mode Crystal fail detect for critical applications Clock mode switching during operation for power savings Power saving Sleep mode Wide operating voltage range 2 0V 5 5V Industrial and Extended Temperature range Power on Reset POR Power up Timer PWRTE and Oscillator Start up Timer OST Brown out Reset BOR with software control option Enhanced low current Watchdog Timer WDT with on chip oscillator software selectable nominal 268 seconds with full prescaler with software enable Multiplexed Master Clear Input pin Programmable code protection High Endurance Flash EEPROM cell 100 000 write Flash endurance 1 000 000 write EEPROM endurance Flash Data EEPROM retention gt 40 years Enhanced USART Module Supports RS 485 RS 232 and LIN 2 0 Auto Baud Detect Auto wake up on Start bit Low Power Features Standby Current 1nA 2 0V typical e Operating Current 20 uA O 32 kH
231. esign boards and filter design software e PowerSmart battery charging evaluation calibration kits IrDA development kit e microlD development and rfLab development software e SEEVAL designer kit for memory evaluation and endurance calculations PICDEM MSC demo boards for Switching mode power supply high power IR driver delta sigma ADC and flow rate sensor Check the Microchip web page and the latest Product Selector Guide for the complete list of demonstration and evaluation kits 2005 Microchip Technology Inc Preliminary DS41262A page 207 PIC16F685 687 689 690 NOTES aa w wwwww wwwwwwwwww w wwww ww wwv x xv wwwv vw wwvv wwvv vvwavvvw vww wwwwww xv v awv ww wwwwww vwvvwwwwvwwwwvw wvw DS41262A page 208 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 17 0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Ambient temperature under Dee catrina a a a den 40 to 125 C Storage lemperal re eie a siaa a a e a e E Na e edt ra E e au uu 65 C to 150 C Voltage on VDD with respect tO KEE 0 3V to 6 5V Voltage on MCLR with respect to VSS EEN 0 3V to 13 5V Voltage on all other pins with respect tO VSS eeeeeeeeneeeeeeeeeeaeeeeeeeeeesneeeseaaeeesneaeeesaeetees 0 3V to VDD 0 3V Total power iss alone Aenean eine ap Ne 800 mW Maximum current out Of VSS pin kk cence cecece sence eesaneeeesgeaesa
232. f the RC circuit on RAO See Example 4 2 for initializing the Ultra Low Power Wake up module The series resistor provides overcurrent protection for the RAO ANO C1IN ICSPDAT ULPWU pin and can allow for software calibration of the time out see Figure 4 1 A timer can be used to measure the charge time and discharge time of the capacitor The charge time can then be adjusted to provide the desired interrupt delay This technique will compensate for the affects of temperature voltage and component accuracy The Ultra Low Power Wake up peripheral can also be configured as a simple Programmable Low Voltage Detect or temperature sensor Note For more information refer to AN879 Using the Microchip Ultra Low Power Wake up Module Application Note DS00879 EXAMPLE 4 2 ULTRA LOW POWER WAKE UP INITIALIZATION BCF STATUS RPO Bank 0 BCF STATUS RP1 BSF PORTA 0 Set RAO data latch BSF STATUS RP1 BANK 2 BCF ANSEL 0 RAO to digital I O BSF STATUS RPO BANK 1 BCF STATUS RP1 BCF TRISA 0 Output high to CALL CapDelay charge capacitor BSF PCON ULPWUE Enable ULP Wake up BSF OCA 0 Select RAO IOC BSF TRISA 0 RAO to input MOVLW B 10001000 Enable interrupt MOVWF INTCON and clear flag BCF STATUS RPO BANK 0 SLEEP Wait for IOC DS41262A page 50 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 4 2 4 PIN DESCRIPTIONS AND 4 2 4 1 RA
233. ffer SSPBUF ae i oo SSPSR i MSb LSb I Processor 1 Shift Register SDI a Serial Clock 13 4 Typical Connection Figure 13 2 shows a typical connection between two microcontrollers The master controller Processor 1 initiates the data transfer by sending the SCK signal Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock Both processors should be programmed to the same Clock Polarity CKP then both controllers would send and receive data at the same time Whether the data is meaningful or dummy data depends on the application software This leads to three scenarios for data transmission Master sends data Slave sends dummy data Master sends data Slave sends data Master sends dummy data Slave sends data SPI MASTER SLAVE CONNECTION SDI I I Serial Input Buffer SSPBUF I I SDO Shift Register i SSPSR MSb LSb 2005 Microchip Technology Inc Preliminary DS41262A page 159 PIC16F685 687 689 690 13 5 Master Mode The master can initiate the data transfer at any time because it controls the SCK The master determines when the slave Processor 2 Figure 13 2 is to broadcast data by the software protocol In Master mode the data is transmitted received as soon as the SSPBUF register is written to If the SPI is only going to receiv
234. ffff Z 1 2 DECF fd Decrement f 1 00 0011 afff ffff Z 1 2 DECFSZ fd Decrement f Skip if 0 1 2 00 1011 dfff ffff 1 2 3 INCF fd Increment f 1 00 1010 dfff ffff Z 1 2 INCFSZ fd Increment f Skip if O 1 2 00 1111 dfff ffff 1 2 3 IORWF fd Inclusive OR W with f 1 00 0100 dfff ffff Z 1 2 MOVF fd Move f 1 00 1000 dfff ffff 2 1 2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP No Operation 1 00 0000 0xx0 0000 RLF fd Rotate Left f through Carry 1 00 1101 Afff ffff C 1 2 RRF td Rotate Right f through Carry 1 00 1100 dfff ffff C 1 2 SUBWF f d Subtract W from f 1 00 0010 dfff ffff C DC Z 1 2 SWAPF f d Swap nibbles in f 1 00 1110 dfff ffff 1 2 XORWF fd Exclusive OR W with f 1 00 0110 dfff ffff Z 1 2 BIT ORIENTED FILE REGISTER OPERATIONS BCF f b Bit Clear f 1 01 00bb bfff ffff 1 2 BSF f b Bit Set f 1 01 Olbb bfff ffff 1 2 BTFSC f b Bit Test f Skip if Clear 1 2 01 10bb bfff ffff 3 BTFSS f b Bit Test f Skip if Set 1 2 01 1lbb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C DC Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call Subroutine 2 10 Okkk kkkk Kkkkk _ CLRWDT Clear Watchdog Timer 1 00 0000 0110 0100 TO PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 KKKK kkkk 2 MOVLW k Move literal to W 1 11 OOxx kkkk kkkk RETFIE Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 Olxx kkkk kkkk RETURN Return from Subroutine
235. g data to the TXREG register 8 If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON lt 7 6 gt are E ON E set FIGURE 12 10 SYNCHRONOUS TRANSMISSION i Gloden Datt Ga pin BE BET XX BIZ X lt br XBOX TX X lt w X t7 Word 1 gt a Word 2 ma RB7 I gt i TX CK pin I I d l l 4 SCKP 0 i RB7 i TX CK pin amp SCKP 1 i i H Write to d i TXREGRe9 WriteWordt Write Word 2 TXIF bit ha 1 Interrupt Flag d d J TRMT bit i Ir E TXEN bit i i i ct Ex Note Sync Master mode SPBRG 0 continuous transmission of two 8 bit words DS41262A page 148 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 FIGURE 12 11 SYNCHRONOUS TRANSMISSION THROUGH TXEN RB5 AN11 RX DT pin X bio X mi CA X bite X bit 7 RB7 TX CK pin asa E Write to TXREG Reg TXIF bi bit yi TRMTbit TXEN bit 2 TABLE 12 7 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FOR BCE Stee Resets och PR AD RCF TXF SSPI
236. ge 31 PIC16F685 687 689 690 2 3 PCL and PCLATH The Program Counter PC is 13 bits wide The low byte comes from the PCL register which is a readable and writable register The high byte PC lt 12 8 gt is not directly readable or writable and comes from PCLATH On any Reset the PC is cleared Figure 2 6 shows the two situations for the loading of the PC The upper example in Figure 2 6 shows how the PC is loaded on a write to PCL PCLATH lt 4 0 gt PCH The lower example in Figure 2 6 shows how the PC is loaded during a CALL or GOTO instruction PCLATH lt 4 3 gt PCH FIGURE 2 6 LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL Instruction with 12 8 7 0 PCL as PC i Destination l A PCLATH lt 4 0 gt 8 5 ALU Result PCLATH PCH PCL 12 1110 8 7 0 PC i GOTO CALL 7 PCLATH lt 4 3 gt 11 2 OPCODE lt 10 0 gt PCLATH 2 3 1 COMPUTED coro A computed GOTO is accomplished by adding an offset to the program counter ADDWF PCL When performing a table read using a computed GOTO method care should be exercised if the table location crosses a PCL memory boundary each 256 byte block Refer to the Application Note AN556 Implementing a Table Read DS00556 2 3 2 STACK The PIC16F685 687 689 690 devices have an 8 level x 13 bit wide hardware stack see Figures 2 1 and 2 2 The stack space is not part of either
237. ge Selection bit 1 Low Range 0 High Range VP6EN 0 6V Reference Enable bit 1 enabled 0 disabled VR lt 3 0 gt Comparator Voltage Reference CVREF Value Selection 0 lt VR lt 3 0 gt lt 15 When VRR 1 CVREF VR lt 3 0 gt 24 VDD When VRR 0 CVREF VDD 4 VR lt 3 0 gt 32 VDD Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 89 PIC16F685 687 689 690 FIGURE 8 5 COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD NN eee 8R I VRR 16 1 Analog MUX CVREF s VR lt 3 0 gt C1VREN C1VREF to Comparator 1 a Input eem VP6EN ji C2VREN ee Sip m HFINTOSC enable C2VREF to 1 EN Comparator 2 a 0 6V Input 0 VP6 Reference A D Converter Module DS41262A page 90 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 8 5 Comparator Response Time power consumption while in Sleep mode turn off the SS ji comparator CMxCONO lt 7 gt 0 and voltage reference Response time is the minimum time after selecting a VRCON lt 7 6 gt 00 new reference voltage or input source before the comparator output is ensured to have a valid level If the internal reference i
238. gend x unknown u unchanged unimplemented locations read as 0 Shaded cells are not used by PORTC Note 1 PIC16F687 PIC16F689 PIC16F690 only 2 PIC16F685 PIC16F690 only DS41262A page 68 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 5 0 TIMER0 MODULE The Timer0 module timer counter has the following features 8 bit timer counter Readable and writable 8 bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Figure 5 1 is a block diagram of the Timer0 module and the prescaler shared with the WDT 5 1 Timer0 Operation Timer mode is selected by clearing the TOCS bit OPTION REG lt 5 gt In Timer mode the Timer0 module will increment every instruction cycle without prescaler If TMRO is written the increment is inhibited for the following two instruction cycles The user can work around this by writing an adjusted value to the TMRO register Counter mode is selected by setting the TOCS bit OPTION REG lt 5 gt In this mode the Timer0 module will increment either on every rising or falling edge of pin RA2 AN1 TOCKI INT C10UT The incrementing edge is determined by the source edge TOSE control bit OPTION REG lt 4 gt Clearing the TOSE bit selects the 5 2 Timer0 Interrupt A Timer0 interrupt is generated when the TMRO register timer counter overflows from FFh to 00h This
239. gger special event CCP1IF bit is set CCP1 resets TMR1or TMR2 and starts an A D conversion if the A D module is enabled 1100 PWM mode PIA P1C active high P1B P1D active high 1101 PWM mode PIA P1C active high P1B P1D active low 1110 PWM mode P1A P1C active low P1B P1D active high 1111 PWM mode PIA P1C active low P1B P1D active low Note 1 PIC16F685 PIC16F690 only Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 113 PIC16F685 687 689 690 111 Capture Mode In Capture mode CCPR1H CCPRIL captures the 16 bit value of the TMR1 register when an event occurs on pin RC5 CCP1 P1A An event is defined as one of the following and is configured by CCP1CON lt 3 0 gt Every falling edge e Every rising edge e Every 4th rising edge e Every 16th rising edge When a capture is made the interrupt request flag bit CCP1IF PIR1 lt 2 gt is set The interrupt flag must be cleared in software If another capture occurs before the value in register CCPR1 is read the old captured value is overwritten by the new captured value 11 1 1 CCP1 PIN CONFIGURATION In Capture mode the RC5 CCP1 P1A pin should be configured as an input by setting the TRISC lt 5 gt bit Note If the RC5 CCP1 P1A pin is configured as an output
240. gister are OR ed with the eight bit literal k The result is placed in the W register IORWF Inclusive OR W with f Syntax label IORWF fd Operands 0 lt f lt 127 dc 0 1 Operation W OR f destination Status Affected Z Description Inclusive OR the W register with register f If d is o the result is placed in the W register If d is 1 the result is placed back in register f 2005 Microchip Technology Inc Preliminary DS41262A page 197 PIC16F685 687 689 690 MOVF Syntax Operands Operation Status Affected Description Words Cycles Example MOVLW Syntax Operands Operation Status Affected Description Words Cycles Example DS41262A page 198 Move f label MOVF fd 0 lt f lt 127 de 0 1 f gt dest Z The contents of register f is moved to a destination dependent upon the status of d If d 0 destination is W register If d 1 the destination is file register f itself d 1 is useful to test a file register since Status flag Z is affected 1 1 MOVF FSR O After Instruction W valueinFSR register Z 1 Move literal to W label MOVLW k 0 lt k lt 255 k gt W None The eight bit literal K is loaded into W register The don t cares will assemble as 0 s 4 4 MOVLW Ox5A After Instruction W Ox5A MOVWF Syntax Operands Operation Status Affected De
241. gt is set interrupt is generated if enabled on the falling edge of the ninth SCL pulse In 10 bit Address mode two address bytes need to be received by the slave Figure 13 8 The five Most Significant bits MSbs of the first address byte specify if this is a 10 bit address Bit R W SSPSTAT lt 2 gt must specify a write so the slave device will receive the second address byte For a 10 bit address the first byte would equal 1111 0 A9 Ag 0 where A9 and Ag are the two MSbs of the address The sequence of events for 10 bit address is as follows with steps 7 9 for slave transmitter 1 Receive first high byte of address bits SSPIF BF and bit UA SSPSTAT lt 1 gt are set 2 Update the SSPADD register with second low byte of address clears bit UA and releases the SCL line 3 Read the SSPBUF register clears bit BF and clear flag bit SSPIF 4 Receive second low byte of address bits SSPIF BF and UA are set 5 Update the SSPADD register with the first high byte of address if match releases SCL line this will clear bit UA 6 Read the SSPBUF register clears bit BF and clear flag bit SSPIF 7 Receive repeated Start condition 8 Receive first high byte of address bits SSPIF and BF are set 9 Read the SSPBUF register clears bit BF and clear flag bit SSPIF TABLE 13 3 DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Set bit SSPIF Transfer is Rec
242. h frequency calibrated oscillator The LFINTOSC is a low frequency uncalibrated oscillator PIC16F685 687 689 690 CLOCK SOURCE BLOCK DIAGRAM External Oscillator FOSC lt 2 0 gt Configuration Word scs OSCCON lt 0 gt NL LP XT HS RC RCIO EC gt gt 8 MHz Internal Oscillator 4 MHz __ 2 MHz gt 1 MHz 500 kHz Lk 250 kHz ml 125 kHz 31 kHz gt HFINTOSC 8 MHz Postscaler LFINTOSC 31 kHz IRCF lt 2 0 gt OSCCON lt 6 4 gt MUX m System Clock CPU and Peripherals MUX INTOSC Power up Timer PWRT Watchdog Timer WDT Fail Safe Clock Monitor FSCM 2005 Microchip Technology Inc Preliminary DS41262A page 35 PIC16F685 687 689 690 3 2 Clock Source Modes Clock Source modes can be classified as external or internal External Clock modes rely on external circuitry for the clock source Examples are oscillator modules EC mode guartz crystal resonators or ceramic resonators LP XT and HS modes and Resistor Capacitor RC mode circuits Internal clock sources are contained internally within the PIC16F685 687 689 690 The PIC16F685 687 689 690 has two internal oscillators the 8 MHz High Frequency Internal Oscillator HFINTOSC and 31 kHz Low Frequency Internal Oscillator LFINTOSC The system clock can be selected between external or inte
243. he ANSEL register Setting CIR CM1CONO0 lt 2 gt selects the C1VREF output of the comparator voltage reference module as the reference voltage for the comparator Clearing C1R selects the C1IN input on the RAO ANO C1IN ICSPDAT ULPWU pin The output of the comparator is available internally via the C1OUT flag CM1CONO0 lt 6 gt To make the output available for an external connection the C1OE bit CM1CONO lt 5 gt must be set The polarity of the comparator output can be inverted by setting the C1POL bit CM1CONO lt 4 gt Clearing C1POL results in a non inverted output 2005 Microchip Technology Inc Preliminary DS41262A page 79 PIC16F685 687 689 690 FIGURE 8 1 COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH lt 1 0 gt Sioi To D Q s Data Bus RA1 AN1 C12IN VREF ICSPCLK X Q1 ten RD_CM1CONO RC1 AN5 C12IN1 _ Xi Set C1IF RC2 ANG P1D X D Q IS G3 RD CMICONO N RC3 AN7 P1 ch CL To PWM Logic CIONO NRESET C1R C10E N I RAO ANO C1IN ICSPDAT ULPWU ci C1OUT Em AA E 3 x C1VREF RA2 AN2 TOCKI INT C10UT C1POL Note 1 When C1ON 0 the C1 comparator will produce a 0 output to the KOR Gate 2 Output shown for reference only For more detail see Figure 4 3 DS41262A page 80 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 REGISTER 8 1 CM1CON0 COMPARATOR C1 CONTROL REGISTER 0 ADDRES
244. he TSR register is not mapped in data memory so it is not available to the user 2 Flag bit TXIF is set when enable bit TXEN is set To set up an Asynchronous Transmission 1 Initialize the SPBRGH SPBRG registers for the appropriate baud rate Set or clear the BRGH and BRG16 bits as required to achieve the desired baud rate 2 Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN 3 If interrupts are desired set enable bit TXIE 4 If 9 bit transmission is desired set transmit bit TX9 Can be used as address data bit 5 Enable the transmission by setting bit TXEN which will also set bit TXIF 6 If 9 bit transmission is selected the ninth bit should be loaded in bit TX9D 7 Load data to the TXREG register starts transmission If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON lt 7 6 gt are set 2005 Microchip Technology Inc Preliminary DS41262A page 141 PIC16F685 687 689 690 FIGURE 12 2 EUSART TRANSMIT BLOCK DIAGRAM TRMT bit Transmit Shift FIGURE 12 4 Wordi gt Transmit Shift Reg Reg Empty Flag I ASYNCHRONOUS TRANSMISSION BACK TO BACK Data Bus TXIF TXREG Register TXIE 7 8
245. he clock BRG16 16 bit Baud Rate Generator bit 1 16 bit baud rate generator is used 0 8 bit baud rate generator is used Unimplemented Read as 0 WUE Wake up Enable bit 1 Next falling RX DT edge will set RCIF and wake up device if it is asleep automatically cleared on next rising edge after falling edge 0 RX DT edges do not generate interrupts ABDEN Auto Baud Detect Enable bit Asynchronous mode 1 Auto Baud mode is enabled clears when auto baud is complete 0 Auto Baud mode is disabled Synchronous mode Don t care Note 1 PIC16F687 PIC16F689 PIC16F690 only Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared X Bit is unknown DS41262A page 134 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 12 2 EUSART Baud Rate Generator BRG The BRG is a dedicated 8 bit or 16 bit generator that supports both the Asynchronous and Synchronous modes of the EUSART By default the BRG operates in 8 bit mode setting the BRG16 bit BAUDCTL lt 3 gt selects 16 bit mode The SPBRGH SPBRG register pair controls the period of a free running timer In Asynchronous mode bits BRGH TXSTA lt 2 gt and BRG16 also control the baud rate In Synchronous mode bit BRGH is ignored Table 12 1 shows the formula for computation of the baud rate for different EUSART modes which only
246. i X DS41262A pag e6 Note 1 PIC16F687 only Preliminary y f 1 2 Analog Comparators EEDAT and Reference 8 256 Bytes eae a eee Ss E F x E x A EEPROM VREF ANO AN1 AN2 AN3 AN4 ANS AN6 AN7 C1IN C1IN C1OUT C2IN C2IN C2OUT EEADR 2005 Microchip Technology Inc PIC16F685 687 689 690 FIGURE 1 3 PIC16F690 BLOCK DIAGRAM INT Configuration i fa Data Bus 8 PORTA Program Counter kG L Flash RAO ANO C1IN ICSPDAT ULPWU 4kx 14 X RA1 AN1 C12IN VREF ICSPCLK IN RA2 AN2 TOCKI INT G1 OUT Program 8 Level Stack 13 bit RAM gt DAAT Ener Memory 256 bytes IA File lt gt X RA4 AN3 T1G OSC2 CLKOUT Registers RA5 T1CKI OSC1 CLKIN Program 14 Bus d RAM Addr 9 PORTB V Addr MUX Instruction Reg Direct Addr T Indirect a RB4 AN10 SDI SDA sl Adi II aS RB5 AN11 RX DT gt RB6 SCK SCL FSR Re g Km A RB7 TX CK Status Reg LIL 8 e E PORTC lt gt X RCO AN4 C2IN 3 gt RC1 AN5 C12IN VZ eee gt RC2 AN6 P1D imer d L RC3 AN7 P1C Instruction D gt Decode and kK Oscillator x RC4 C20UT P1B Control Start up Timer X RC5 CCP1 P1A K sch lt gt X
247. iate PWM pin is toggled In Dual PWM mode the pin will be toggled after the dead band time has expired The polarity active high or active low and mode of the signal are configured by the P1M lt 1 0 gt CCP1CON lt 7 6 gt and CCP1M lt 3 0 gt CCP1CON lt 3 0 gt bits The maximum PWM resolution for a given PWM frequency is given by the formula EQUATION 11 3 MAX PWM RESOLUTION PER FREQUENCY lo ef 5 FPWM e TMR2 Prescaler o Resolution I bits log 2 All control registers are double buffered and are loaded at the beginning of a new PWM cycle the period boundary when Timer2 resets in order to prevent glitches on any of the outputs The exception is the PWM delay register which is loaded at either the duty cycle boundary or the period boundary whichever comes first Because of the buffering the module waits until the timer resets instead of starting immediately This means that enhanced PWM waveforms do not exactly match the standard PWM waveforms but are instead offset by one full instruction cycle 4 TOSC Note If the PWM duty cycle value is longer than the PWM period the assigned PWM pin s will remain unchanged TABLE 11 4 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS Fosc 20 MHz PWM Frequency 1 22 kHz D 4 88kHz D 19 53kHz 78 12kHz 156 3kHz 208 3 kHz Timer Prescale 1 4 16 16 4 1 1 1 1 PR2 Value OxFF OxFF OxFF 0x3F Ox1F 0x17 Maximum Resolution bits 10 10
248. idually enabled pull up RCO AN4 C2IN RCO ST CMOS General purpose I O AN4 AN A D Channel 4 input C2IN AN Comparator 2 positive input Legend AN Analog input or output CMOS CMOS compatible input or output TTL TTL compatible input ST Schmitt Trigger input with CMOS levels HV High Voltage XTAL Crystal DS41262A page 8 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 TABLE 1 1 PINOUT DESCRIPTION PIC16F685 CONTINUED Name Function ts Ss e Description RC1 AN5 C12IN RC1 ST CMOS General purpose 1 0 AN5 AN A D Channel 5 input C12IN AN Comparator 1 or 2 negative input RC2 AN6 P1D RC2 ST CMOS General purpose 1 0 AN6 AN A D Channel 6 input P1D CMOS PWM output RC3 AN7 P1C RC3 ST CMOS General purpose 1 0 AN7 AN A D Channel 7 input P1C CMOS PWM output RC4 C2OUT P1B RC4 ST CMOS General purpose 1 0 C20UT CMOS Comparator 2 output P1B CMOS PWM output RC5 CCP1 P1A RC5 ST CMOS General purpose 1 0 CCP1 ST CMOS Capture Compare input P1A ST CMOS PWM output RC6 AN8 RC6 ST CMOS General purpose 1 0 AN8 AN A D Channel 8 input RC7 AN9 RC7 ST CMOS General purpose 1 0 AN9 AN A D Channel 9 input Vss Vss Power Ground reference VDD VDD Power Positive supply Legend AN Analog input or output CMOS CMOS compatible input or output TTL TTL compatible inp
249. iminary 2005 Microchip Technology Inc PIC16F685 687 689 690 FIGURE 8 3 SR LATCH CONFIGURATIONS SR lt 1 0 gt 00 SR lt 1 0 gt 11 PULSS Pulse Cep E T ER s C1 C10UT eee es a Hd A VIN RC1 AN5 C12IN _ C2our lt lt A VIN C2 Q x C20UT RCO AN4 C2IN A R b4 p PULSR Gan SR lt 1 0 gt 01 SR lt 1 0 gt 10 Pul pulss Gen pulss Gen TF C10UT RA1 AN1 C12IN A vw gt E Jur S VREF ICSPCLK Q ES a o lt RAO ANO C1IN A Vine j El ga ICSPDAT ULPWU WS RC1 AN5 C12IN A VIN C20UT t TY R HI RCO AN4 C2IN A Vin E rn a Pulse Pulse PULSR Gen PULSR WA Note Pulse Generator causes a 1 2 O state 1 Tosc pulse width FIGURE 8 4 SR LATCH SIMPLIFIED BLOCK DIAGRAM SR lt 1 0 gt PULSS to RA2 port logic C1 S Des a C1SEN ma E Reset C2REN Jj Dominant to RC4 port logic PULSR Do SR lt 1 0 gt Note 1 IfR 1andS 1 simultaneously Q 0 0 1 O 2005 Microchip Technology Inc Preliminary DS41262A page 87 PIC16F685 687 689 690 8 4 Comparator Reference The comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs There are two voltage references available in th
250. iminary O 2005 Microchip Technology Inc PIC16F685 687 689 690 2 0 MEMORY ORGANIZATION FIGURE 2 2 PROGRAM MEMORY MAP AND STACK FOR THE 2 1 Program Memory Organization PIC16F687 The PIC16F685 687 689 690 has a 13 bit program counter capable of addressing an 8k x 14 program PC lt 12 0 gt memory space Only the first 2k x 14 0000h 07FFh for CALL RETURN YA the PIC16F687 is physically implemented and first 4k x RETFIE RETLW Ge 14 0000h 0FFFh for the PIC16F685 PIC16F689 PIC16F690 Accessing a location above these z Stack Level 1 boundaries will cause a wrap around The Reset vector Stack Level 2 is at 0000h and the interrupt vector is at 0004h see Q Figures 2 1 and 2 2 Stack Level 8 FIGURE 2 1 PROGRAM MEMORY MAP AND STACK FOR THE Reset Vector 0000h PIC16F685 689 690 E Interrupt Vector 0004h 0005h PC lt 12 0 gt CALL RETURN 13 On chip Program RETFIE RETLW Memory 07FFh Stack Level 1 0800h Stack Level 2 ka Access 0 7FFh e Stack Level 8 1FFFh Reset Vector 0000h e Is Interrupt Vector 0004h 0005h On chip Program Memory OFFFh 1000h Access 0 FFFh 1FFFh 2005 Microchip Technology Inc Preliminary DS41262A page 15 PIC16F685 687 689 690 2 2 Data Memory Organization The data memory see Figures 2 3 2 4 and 2 5 is partitioned into four banks which co
251. in 2 Watchdog Timer wake up if WDT was enabled 3 Interrupt from RA2 INT pin PORTA change or a peripheral interrupt The first event will cause a device Reset The two latter events are considered a continuation of program execution The TO and PD bits in the Status register can be used to determine the cause of device Reset The PD bit which is set on power up is cleared when Sleep is invoked TO bit is cleared if WDT wake up occurred The following peripheral interrupts can wake the device from Sleep 1 TMR1 interrupt Timer1 must be operating as an asynchronous counter 2 ECCP Capture mode interrupt 3 Special event trigger Timer1 in Asynchronous mode using an external clock A D conversion when A D clock source is RC EEPROM write operation completion Comparator output changes state Interrupt on change External Interrupt from INT pin EUSART Break detect I C slave So No a E Other peripherals cannot generate interrupts since during Sleep no on chip clocks are present When the SLEEP instruction is being executed the next instruction PC 1 is prefetched For the device to wake up through an interrupt event the corresponding interrupt enable bit must be set enabled Wake up is regardless of the state of the GIE bit If the GIE bit is clear disabled the device continues execution at the instruction after the SLEEP instruction If the GIE bit is set enabled the device executes the instruct
252. indows with direct edit of contents High level source code debugging e Mouse over variable inspection Extensive on line help The MPLAB IDE allows you to Edit your source files either assembly or C One touch assemble or compile and download to PICmicro emulator and simulator tools automatically updates all project information e Debug using source files assembly or C mixed assembly and C machine code MPLAB IDE supports multiple debugging tools in a single development paradigm from the cost effective simulators through low cost in circuit debuggers to full featured emulators This eliminates the learning curve when upgrading to tools with increasing flexibility and power 16 2 MPASM Assembler The MPASM assembler is a full featured universal macro assembler for all PICmicro MCUs The MPASM assembler generates relocatable object files for the MPLINK object linker Intel standard HEX files MAP files to detail memory usage and symbol ref erence absolute LST files that contain source lines and generated machine code and COFF files for debugging The MPASM assembler features include Integration into MPLAB IDE projects User defined macros to streamline assembly code Conditional assembly for multi purpose source files Directives that allow complete control over the assembly process 2005 Microchip Technology Inc Preliminary DS41262A page 203 PIC16F685 687 689 690
253. inth SCL input pulse If the SDA line was high not ACK then the data transfer is complete When the ACK is latched by the slave the slave logic is reset resets SSPSTAT register and the slave then monitors for another occurrence of the Start bit If the SDA line was low ACK the transmit data must be loaded into the SSPBUF register which also loads the SSPSR register Then pin RB6 SCK SCL should be enabled by setting bit CKP CTM WAVEFORMS FOR TRANSMISSION 7 BIT ADDRESS Receiving Address RW 1 SDA A A7 X AGX ASX A4X A3XA2XA1Y N ACK Transmitting Data ACK D7X D6 D5 X D4X D3 X D2X DI XDOY NE em WA alla rui WA aman Data in sampled SSPIF PIR1 lt 3 gt BF SSPSTAT lt 0 gt CKP SSPCON lt 4 gt ee held low e CPU responds to SSPIF Cleared in software eon SSP Interrupt SSPBUF is written in software Service Routine Set bit after writing to SSPBUF the SSPBUF must be written to before the CKP bit can be set 2005 Microchip Technology Inc Preliminary DS41262A page 169 PIC16F685 687 689 690 IC SLAVE MODE TIMING TRANSMISSION 10 BIT ADDRESS FIGURE 13 11 ques JOU S MOV IN INS S 4NGdSS esneseq 195 SI AOdSS 7 o NIS USUM 0 0 JOSd JOU SBOP JO HD palepdn aq 01 speeu GAVASS UL Buneoilpu jas S YN ssaippe Jo og ssaippe Jo S Q MOJ UJIM peyepdn sq yBiy yum peyepdn s JO YdSS pajepdn si qq
254. ion after the SLEEP instruction then branches to the interrupt address 0004h In cases where the execution of the instruction following SLEEP is not desirable the user should have a NOP after the SLEEP instruction Note If the global interrupts are disabled GIE is cleared but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set the device will immediately wake up from Sleep The SLEEP instruction is completely executed The WDT is cleared when the device wakes up from Sleep regardless of the source of wake up 14 6 2 WAKE UP USING INTERRUPTS When global interrupts are disabled GIE cleared and any interrupt source has both its interrupt enable bit and interrupt flag bit set one of the following will occur If the interrupt occurs before the execution of a SLEEP instruction the SLEEP instruction will complete as a NoP Therefore the WDT and WDT prescaler and postscaler if enabled will not be cleared the TO bit will not be set and the PD bit will not be cleared If the interrupt occurs during or after the execution of a SLEEP instruction the device will immediately wake up from Sleep The SLEEP instruction will be completely executed before the wake up Therefore the WDT and WDT prescaler and postscaler if enabled will be cleared the TO bit will be set and the PD bit will be cleared Even if the flag bits were checked before executing a SLEEP instruc
255. is device has 4K words of program EEPROM with an address range from Oh to OFFFh The program memory allows one word reads The EEPROM data memory allows byte read and write A byte write automatically erases the location and writes the new data erase before write The write time is controlled by an on chip timer The write erase voltages are generated by an on chip charge pump rated to operate over the voltage range of the device for byte or word operations When the device is code protected the CPU may continue to read and write the data EEPROM memory and read the program memory When code protected the device programmer can no longer access data or program memory 10 1 EEADR and EEADRH Registers The EEADR and EEADRH registers can address up to a maximum of 256 bytes of data EEPROM or up toa maximum of 4K words of program EEPROM When selecting a program address value the MSB of the address is written to the EEADRH register and the LSB is written to the EEADR register When selecting a data address value only the LSB of the address is written to the EEADR register 10 1 1 EECON1 AND EECON2 REGISTERS EECON1 is the control register for EE memory accesses Control bit EEPGD determines if the access will be a program or data memory access When clear as it is when reset any subsequent operations will operate on the data memory When set any subsequent operations will operate on the program memory Program memory can only
256. is modulated These are illustrated in Figure 11 8 P1A P1B P1C and P1D outputs are multiplexed with the PORTC lt 5 2 gt data latches The TRISC lt 5 2 gt bits must be cleared to make the P1A P1B P1C and P1D pins output FIGURE 11 8 FULL BRIDGE PWM OUTPUT Forward Mode Period P1A 2 Duty Cycle I P1B 2 l I I I Pic I Pip Reverse Mode 2 Output signal is shown as active high S Period gt hi i Duty Cycle i P1A 2 I I I EIA O AS 0 I PiB ___ I I PIC O I I I I P1p i I Note 1 Atthis time the TMR2 register is egual to the PR2 register ia DS41262A page 120 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 FIGURE 11 9 EXAMPLE OF FULL BRIDGE APPLICATION V FET QA Qc FET Driver Driver P1A gt 4 amp di P1B Load FET FET PIC16F685 690 Driver Driver a4 A KN A P1C QB Top V P1D gt 11 3 5 1 Direction Change in Full Bridge Figure 11 11 shows an example where the PWM Mode In the Full bridge Output mode the P1M1 bit CCP1CON lt 7 gt allows user to control the Forward Reverse direction When the application firmware changes this direction control bit the module will assume the new direction on the next PWM cycle Ju
257. issues in migrating from This is a new data sheet other PICmicro devices to the PIC16F6XX Family of devices B 1 PIC16F676 to PIC16F685 TABLE B 1 FEATURE COMPARISON Feature PIC16F676 PIC16F685 Max Operating Speed 20 MHz 20 MHz Max Program 1024 4096 Memory Words SRAM bytes 64 128 A D Resolution 10 bit 10 bit Data EEPROM 128 256 Bytes Timers 8 16 bit 1 1 2 1 Oscillator Modes 8 8 Brown out Reset Y Y Internal Pull ups RAO 1 2 4 5 RAO 1 2 4 5 MCLR Interrupt on change RA0 1 2 3 4 5 RAO 1 2 3 4 5 Comparator 1 2 ECCP N Y Ultra Low Power N Y Wake Up Extended WDT N Y Software Control N Y Option of WDT BOR INTOSC Frequencies 4 MHz 31 kHz 8 MHz Clock Switching N Y Note This device has been designed to perform to the parameters of its data sheet It has been tested to an electrical specification designed to determine its conformance with these parameters Due to process differences in the manufacture of this device this device may have different performance characteristics than its earlier version These differences may cause this device to perform differently in your application than the earlier version of this device O 2005 Microchip Technology Inc Preliminary DS41262A page 245 PIC16F685 687 689 690 NOTES D wwwwwww ww wvv amp xwww v w w w vwww v avwwvww wwwww wx ww vwww v www vwwwvwwvvwwwvww
258. it read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown DS41262A page 58 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 4 4 3 PIN DESCRIPTIONS AND DIAGRAMS Each PORTB pin is multiplexed with other functions The pins and their combined functions are briefly described here For specific information about individual functions such as the SSP IC or interrupts refer to the appropriate section in this data sheet 4 4 3 1 RB4 AN10 SDI SDA Figure 4 7 shows the diagram for this pin The RB4 AN10 SDI SDA pin is configurable to function as one of the following a general purpose I O an analog input for the A D e a SPI data I O an I2C data I O Note 1 SDI and SDA are available on PIC16F687 PIC16F689 PIC16F690 only FIGURE 4 7 BLOCK DIAGRAM OF RB4 Analog Data Bus Input Mode D Q VDD WR CK e WPUETP AS H L Weak RD ch RABPU WPUB SSPEN ID Q E WR CK 7 PORTB PN H O Pin D a WR SE TRISB gt cK Q Vss Analog RD lt lt Input Mode TRISB RD T lt PORTB D Q WR CK 5 CH DM ocs T H EN Q3 ro Lee tlle IOCB Q D ST EN Interrupt on Change RD PORTB w To SSPSR s To A D Converter ET Available on PIC16F687 PIC16F689 PIC16F690 only Note 1 ANSEL
259. ith the appropriate values Select one of the available output configurations and direction with the P1M lt 1 0 gt bits Select the polarities of the PWM output signals with the CCP1M lt 3 0 gt bits 4 Set the PWM duty cycle by loading the CCPR1L register and CCP1CON lt 5 4 gt bits 5 For Half bridge Output mode set the dead band delay by loading PWM1CON lt 6 0 gt with the appropriate value 6 If auto shutdown operation is required load the ECCPAS register Select the auto shutdown sources using the ECCPAS lt 2 0 gt bits Select the shutdown states of the PWM output pins using PSSAC lt 3 2 gt and PSSBD lt 1 0 gt bits Set the ECCPASE bit ECCPAS lt 7 gt Configure the comparators using the CM1CONO and CM2CONO registers Registers 8 1 and 8 2 Configure the comparator inputs as analog inputs 7 If auto restart operation is required set the PRSEN bit PWM1ICON lt 7 gt 8 Configure and start TMR2 Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit PIR1 lt 1 gt Set the TMR2 prescale value by loading the T2CKPS bits T2CON lt 1 0 gt Enable Timer2 by setting the TMR2ON bit T2CON lt 2 gt 9 Enable PWM outputs after a new PWM cycle has started e Wait until TMR2 overflows TMR2IF bit is set e Enable the CCP1 P1A P1B P1C and or P1D pin outputs by clearing the respective TRISC bits e Clear the ECCPASE bit ECCPAS lt 7 gt 2005 Microchip Technology Inc Preli
260. itor CHOLD is not discharged after each conversion 3 The maximum recommended impedance for analog sources is 10 KO This is reguired to meet the pin leakage specification FIGURE 9 4 ANALOG INPUT MODEL Yap Sampling re VT 0 6V ee Rs ANx Ric lt 1k SS Rss MI me i po Goines ees eae Or e l AG it 1 1 aly L capacitance 28 SET kene Wee E be s Vss 6v 5V Rss Legend CPIN Input Capacitance VoiD 4V gt VT Threshold Voltage So LEAKAGE Leakage current at the pin due to T various junctions Ric Interconnect Resistance 567891011 SS Sampling Switch Sampling Switch CHOLD Sample Hold Capacitance from DAC kQ 2005 Microchip Technology Inc Preliminary DS41262A page 101 PIC16F685 687 689 690 9 3 A D Operation During Sleep The A D converter module can operate during Sleep This reguires the A D clock source to be set to the FRC option When the RC clock source is selected the A D waits one instruction before starting the conversion This allows the SLEEP instruction to be executed thus eliminating much of the switching noise from the conversion When the conversion is complete the GO DONE bit is cleared and the result is loaded into the ADRESH ADRESL registers lf the A D interrupt is FIGURE 9 5 A D TRANSFER FUNCTION enabled the device awakens from Sleep lf the GIE bit INTCON lt 7 gt is set the program counter is set to the interrupt vector 000
261. l IOCA Interrupt on change PORTA IR IOCB Interrupt on change PORTB OPTION REG san am EEN OSCCON Oscillator Control PCON Power Control PIE1 Peripheral Interrupt Enable 1 PIE2 Peripheral Interrupt Enable Register 2 iia PIR1 Peripheral Interrupt Request Register 1 29 PIR2 Peripheral Interrupt Request Register 2 30 PORTA PSTRCON Pulse Steering Control PWM1CON Enhanced PWM Configuration RCSTA Receive Status and Control 133 Reset VAalues s w sswanmnamaanzanzwaa 180 Reset Values special registers 182 Special Function Register Map len LIT PIC16F687 689 PIC16F690 Special Function Registers A 16 Special Register Summary EE SRCON SR Latch Control SSPCON Sync Serial Port Control Register 157 SSPMSK SSP Mask bens SSPSTAT Sync Serial Port Status Register 156 STATUS assi essi gae qa espe aaa narra cagada T1CON Timer1 Control s T2CON Timer2 Control TRISA Tri state PORTA TRISB Tri state PORTB e TRISC Tri state PORT DS41262A page 250 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 TXSTA Transmit Status and Control VRCON Voltage Reference Control
262. l No elei o frt A AOV AOV SSSJppy JO 91 g puodas eAl999H 0 5 WH see aula eoejd use SSSJPpy Jo 9149 15114 3A189094 sey GAVASS Jo ajepdn sey GdVdSs jo ajepdn JUN MO pleu S 420 0 HUN MO pleu S 490 D alg eyeq anla0ay 2005 Microchip Technology Inc iminary Prel DS41262A page 168 PIC16F685 687 689 690 13 12 5 TRANSMISSION When the R W bit of the incoming address byte is set and an address match occurs the R W bit of the SSPSTAT register is set The received address is loaded into the SSPBUF register The ACK pulse will be sent on the ninth bit and pin RB6 SCK SCL is held low The transmit data must be loaded into the SSPBUF register which also loads the SSPSR register Then pin RB6 SCK SCL should be enabled by setting bit CKP SSPCON lt 4 gt The master must monitor the SCL pin prior to asserting another clock pulse The slave devices may be holding off the master by stretching the clock The eight data bits are shifted out on the falling edge of the SCL input This ensures that the SDA signal is valid during the SCL high time Figure 13 10 FIGURE 13 10 An SSP interrupt is generated for each data transfer byte Flag bit SSPIF must be cleared in software and the SSPSTAT register is used to determine the status of the byte Flag bit SSPIF is set on the falling edge of the ninth clock pulse As a slave transmitter the ACK pulse from the master receiver is latched on the rising edge of the n
263. l Function Registers associated with the core are described in this section Registers related to the operation of peripheral features are described in the section of that peripheral feature DS41262A page 16 Preliminary 2005 Microchip Technology Inc FIGURE 2 3 Indirect addr 1 TMRO PCL STATUS FSR PORTA PORTB PORTC PCLATH INTCON PIRI PIR2 TMRIL TMR1H T1CON TMR2 T2CON CCPRIL CCPRTH CCP1CON PWM1CON ECCPAS ADRESH ADCONO General Purpose Register 96 Bytes Bank 0 Note 1 PIC16F685 SPECIAL FUNCTION REGISTERS File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah OBh OCh ODh OEh OFh 10h 1th 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 7Fh Indirect addr 1 OPTION_REG PCL STATUS FSR TRISA TRISB TRISC PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE PR2 WPUA IOCA WDTCON ADRESL ADCON1 General Purpose Register 80 Bytes accesses 70h 7Fh Bank1 File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h EFh FOh FFh PIC16F685 687 689 690 Indirect addr
264. l Safe Operation cssecscscccsseesecsseeseeeseaeeesees Reset or Wake up from Sleep as Firmware Instructions eeeeeeeeseeseieerieerreesrirssrrreernesne Flash Program Memory Fuses See Configuration Bits G General Purpose Register File 16 DS41262A page 248 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 l IC Mode Addreseing serranas Associated Registers E Master Mode lt vsw nsmanzannwanzanzwanzaniwanaazimanaazzwaza Mode Selection ii Multi Master Mode dus Operation AA AOA ATAKA ae IA SA UA AAA Slave Mode SCL and SDA pins 164 Transmission renan 169 ID Locations se In Circuit Serial Programming CP 190 Indirect Addressing INDF and FSR registers 32 Instruction Format ae Instruction Set eee eee rear INTCON Register 26 Inter Integrated Circuit C See C Mode Internal Oscillator Block INTOSC Dpechticailons 220 Internal Sampling Switch Rss Impedance 100 Internet Address 253 Interrupts 183 M BASATA WAA eee ae eee RO PE 99 Associated Registers 185 Cap Wa cuas SER RR 114 eu 114 Context Saving Interrupt on Change 49 Interrupt on change cee eset eeeeeeeeeeeeeeees 56 PORTA PORTB Interrupt on Change 184 RA2 INT TMR2 to PR2 Match DWMI 77 INT
265. l not be set d When the first word has been shifted out of TSR the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set e If enable bit TXIE is set the interrupt will wake the chip from Sleep If the global interrupt is enabled the program will branch to the interrupt vector TABLE 12 9 REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR AOR aranes Resets oCh PIR1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF ooo 0000 000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X 19h TXREG EUSART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG EUSART Receive Data Register 0000 0000 0000 0000 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TT e 1111 SCH PIE1 ADIE RCIE TXIE SSPIE CCPIE TMR2IE TMR1IE 000 0000 000 0000 98h TXSTA CSRC TX9 TXEN SYNC SENB BRGH TRMT TX9D 0000 0010 0000 0010 99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRGO 0000 0000 0000 0000 9Ah SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRGY BRG8 0000 0000 0000 0000 9Bh BAUDCTL ABDOVF RCIDL SCKP BRG16 WUE ABDEN 01 0 0 00 01 0 0 00 Legend x unknown unimplemented locations read as 0 Shaded cells are not used for Asynchronous Reception Note 1 PIC16F687 PIC16F689 PIC16F690 only DS41262A page 152 Preliminary 2005 Microchip Technology Inc PIC16F685 687
266. l register 2 Address 93h also accesses the SSP Mask SSPMSK register under certain conditions See Registers 13 2 and 13 3 for more details 2005 Microchip Technology Inc Preliminary DS41262A page 19 PIC16F685 687 689 690 TABLE 2 1 PIC16F685 687 689 690 SPECIAL REGISTERS SUMMARY BANK 0 Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR all other Reset Resets Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory not a physical register XXXX XXXX XXXX XXXX 01h TMRO TimerO Module Register XXXX XXXX uuuu uuuu 02h PCL Program Counter s PC Least Significant Byte 0000 0000 0000 0000 03h STATUS IRP RP1 RPO TO PD 7 DC C 0001 1xxx 000q quuu 04h FSR Indirect Data Memory Address Pointer XXXX XXXX uuuu uuuu 05h PORTA RA5 RA4 RA3 RA2 RA1 RAO XX XXXX uu uuuu 06h PORTB RB7 RB6 RB5 RB4 XXXX uuuu 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RCO XXXX XXXX uuuu uuuu 08h Unimplemented 09h Unimplemented OAh PCLATH Write Buffer for upper 5 bits of Program Counter 0 0000 0 0000 OBh INTCON GIE PEIE TOIE INTE RABIE TOIF INTF RABIF 0000 000x 0000 000x OCh PIR1 ADIF RCIF TXI
267. le after BSF EECON1 RD BCF STATUS RPO Bank 2 MOVF EEDAT W W LS Byte of Program EEDAT MOVF EEDATH W W MS Byte of Program EEDAT BCF STATUS RP1 Bank 0 2005 Microchip Technology Inc Preliminary DS41262A page 109 PIC16F685 687 689 690 FIGURE 10 1 FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 102 as os Q1 02 as ou Q1 02 as os Q1 02 as as Q1 02 as as Q1 02 as os Flash ADDR PC PC 1 EEADRH EEADR PC 3 PC 4 X PC 5 Flash Data i INSTR PC X INSTR PC 1 X EEDATH EEDAT X INSTR PC 3 X INSTR PC 4 Y INSTR PC 1 BSF EECON1 RD INSTR PC 1 Forced NOP INSTR PC 3 INSTR PC 4 executed here executed here executed here executed here executed here executed here RD bit EEDATH EEDAT X Register EERHLT x DS41262A page 110 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 10 2 Write Verify Depending on the application good programming practice may dictate that the value written to the data EEPROM should be verified see Example 10 4 to the desired value to be written EXAMPLE 10 4 WRITE VERIFY DCH STATUS RPO Bank 2 BSF STATUS RP1 E EEDAT not changed from previous write BSF STATUS RPO Bank 3 BSF EECON1 RD YES Read the value written BCF STATUS RPO Bank 2 XORWF EEDAT W BTFSS STATUS Z Is data the same GOTO WRITE ERR No
268. lear In Master mode the SCL and SDA lines are manipulated by clearing the corresponding TRISB lt 6 4 gt bit s The output level is always low irrespective of the value s in PORTB lt 6 4 gt So when transmitting data a 1 data bit must have the TRISB lt 4 gt bit set input and a o data bit must have the TRISB lt 4 gt bit cleared output The same scenario is true for the SCL line with the TRISB lt 6 gt bit Pull up resistors must be provided externally to the SCL and SDA pins for proper operation of the DC module The following events will cause the SSP Interrupt Flag bit SSPIF to be set SSP Interrupt will occur if enabled Start condition Stop condition e Data transfer byte transmitted received Master mode of operation can be done with either the Slave mode idle SSPM lt 3 0 gt 1011 or with the Slave active When both Master and Slave modes are enabled the software needs to differentiate the source s of the interrupt 13 14 Multi master Mode In Multi Master mode the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free The Stop P and Start S bits are cleared from a Reset or when the SSP module is disabled The Stop P and Start S bits will toggle based on the Start and Stop conditions Control of the IC bus may be taken when bit P SSPSTAT lt 4 gt is set or the bus is idle and both the S and P bits clear When the bus
269. lls are not used by oscillators Note 1 PIC16F687 PIC16F689 PIC16F690 only DS41262A page 136 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 TABLE 12 3 BAUD RATES FOR ASYNCHRONOUS MODES SYNC 0 BRGH 0 BRG16 0 Se Fosc 20 000 MHz Fosc 10 000 MHz Fosc 8 000 MHz O95 Ee s Ros vale nate oe ane hate so io ebe K Error decimal K Error decimal K Error decimal 0 3 12 1221 1 73 255 1 202 016 129 1201 0 16 103 24 2404 016 129 2404 0 16 64 2403 0 16 51 ae 9 766 1 73 31 9766 1 73 15 9615 0 16 12 19 2 19 531 1 73 15 19531 1 73 7 57 6 62 500 8 51 4 52 083 9 58 2 115 2 104 167 9 58 2 78125 32 18 1 SYNC 0 BRGH 0 BRG16 0 Se Fosc 4 000 MHz Fosc 2 000 MHz Fosc 1 000 MHz tO Re ote ua crate n Dote leese SE et kg FOY decimal K Error decimal K Error decimal 03 0300 016 207 300 0 16 103 300 0 16 51 12 1202 0 16 51 1201 0 16 25 1201 0 16 12 24 2404 0 16 25 2403 0 16 12 96 8 929 6 99 6 19 2 20 833 851 2 57 6 62 500 851 0 115 2 62 500 45 75 0 SYNC 0 BRGH 1 BRG16 0 ENTE FOSC 20 000 MHz Fosc 10 000 MHz Fosc 8 000 MHz Sara vm K Error decimal K Error decimal K Error decimal 2 4 2441 1 73 255 2403 0 16 207 96 9615 016 129 9615 0 16 64 9615 0 16 51 19 2 19 231
270. logy Inc PIC16F685 687 689 690 2 2 2 8 PCON Register The Power Control PCON register see Register 2 8 contains flag bits to differentiate between a Power on Reset POR e Brown out Reset BOR e Watchdog Timer Reset WDT External MCLR Reset The PCON register also controls the Ultra Low Power Wake up and software enable of the BOR REGISTER 2 8 PCON POWER CONTROL REGISTER ADDRESS 8Eh U 0 U 0 R W 0 R W 1 U 0 U 0 R W 0 R W x ULPWUE SBOREN POR BOR bit 7 bit 0 bit 7 6 Unimplemented Read as oi bit 5 ULPWUE Ultra Low Power Wake up Enable bit 1 Ultra Low Power Wake up enabled 0 Ultra Low Power Wake up disabled bit 4 SBOREN Software BOR Enable bit 1 BOR enabled 0 BOR disabled bit 3 2 Unimplemented Read as 0 bit 1 POR Power on Reset Status bit 1 No Power on Reset occurred 0 A Power on Reset occurred must be set in software after a Power on Reset occurs bit 0 BOR Brown out Reset Status bit 1 No Brown out Reset occurred 0 A Brown out Reset occurred must be set in software after a Brown out Reset occurs Note 1 BOREN lt 1 0 gt 01 in the Configuration Word register for this bit to control the BOR Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A pa
271. minary DS41262A page 129 PIC16F685 687 689 690 TABLE 11 6 REGISTERS ASSOCIATED WITH PWM AND TIMER2 Addr Name Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SOR BOR aoa Resets 0Bh 8Bh INTCON GIE PEIE TOIE INTE RABIE TOIF INTF RABIF 0000 000x 0000 000x 10Bh 18Bh OCh PIR1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 000 0000 000 0000 dih TMR2 Timer2 Module Register 0000 0000 0000 0000 12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPSO TMR2ON T2CKPS1 T2CKPSO 000 0000 000 0000 15h CCPRIL Capture Compare PWM Register1 Low Byte XXXX XXXX UUUU uuuu 16h CCPR1H Capture Compare PWM Register1 High Byte XXXX XXXX UUUU uuuu 17h CCP1CON P1M1 P1MO DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 1Ch PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDCO 0000 0000 0000 0000 1Dh ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBDO 0000 0000 0000 0000 87h 187h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISCO 1111 1111 1111 1111 8Ch PIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IF TMRIIF 000 0000 000 0000 92h PR2 Timer2 Module Period Register 1111 1111 1111 1111 19Dh PSTRCON STRSYNC STRD STRC STRB STRA 0 0001 0 0001 Legend ed ee locations read as 0 u unchanged x unknown Shaded cells are not used by the Capture Compare or Timer1 module Note 1 PI
272. mington Hills MI Tel 248 538 2250 Fax 248 538 2260 Kokomo Kokomo IN Tel 765 864 8360 Fax 765 864 8387 Los Angeles Mission Viejo CA Tel 949 462 9523 Fax 949 462 9608 San Jose Mountain View CA Tel 650 215 1444 Fax 650 961 0286 Toronto Mississauga Ontario Canada Tel 905 673 0699 Fax 905 673 6509 ASIA PACIFIC Australia Sydney Tel 61 2 9868 6733 Fax 61 2 9868 6755 China Beijing Tel 86 10 8528 2100 Fax 86 10 8528 2104 China Chengdu Tel 86 28 8676 6200 Fax 86 28 8676 6599 China Fuzhou Tel 86 591 8750 3506 Fax 86 591 8750 3521 China Hong Kong SAR Tel 852 2401 1200 Fax 852 2401 3431 China Shanghai Tel 86 21 5407 5533 Fax 86 21 5407 5066 China Shenyang Tel 86 24 2334 2829 Fax 86 24 2334 2393 China Shenzhen Tel 86 755 8203 2660 Fax 86 755 8203 1760 China Shunde Tel 86 757 2839 5507 Fax 86 757 2839 5571 China Qingdao Tel 86 532 502 7355 Fax 86 532 502 7205 ASIA PACIFIC India Bangalore Tel 91 80 2229 0061 Fax 91 80 2229 0062 India New Delhi Tel 91 11 5160 8631 Fax 91 11 5160 8632 Japan Kanagawa Tel 81 45 471 6166 Fax 81 45 471 6122 Korea Seoul Tel 82 2 554 7200 Fax 82 2 558 5932 or 82 2 558 5934 Singapore Tel 65 6334 8870 Fax 65 6334 8850 Taiwan Kaohsiung Tel 886 7 536 4818 Fax 886 7 536 4803 Taiwan Taipei Tel 886 2 2500 6610 Fax 886 2 2508 0102 Taiwan Hsinchu Tel 886 3 572 9526 Fax 886
273. mitt Trigger buffer Vss 0 2 VDD V Entire range D032 MCLR OSC1 RC mode Vss 02Vpp V D033 OSC1 XT and HS modes Vss 03Vpp V D033A OSC1 LP mode Vss 06VDD vV 1 0 D0033B OCS1 ER mode Vss 01VDD V VIH Input High Voltage I O port D040 with TTL buffer 2 0 VDD V 4 5V lt VDD lt 5 5V DO40A 0 25 VDD 0 8 VDD V Otherwise D041 with Schmitt Trigger buffer 0 8 VDD VDD V Entire range D042 MCLR PORTA 0 8 VDD VDD V D043 OSC1 XT HS and LP modes 0 7 VDD VDD V Note 1 DO43A OSC1 ER mode 0 9 VDD a VDD V Note 1 D070 IPUR PORTA Weak Pull up Current 50 250 400 UA VDD 5 0V VPIN VSS PORTB Weak Pull up Current 50 250 400 uA liL Input Leakage Current D060 I O port 1 UA Vss lt VPIN lt VDD Pin at high impedance D061 MCLR uA Vss lt VPIN lt VDD D063 OSC1 5 UA Vss lt VPIN lt VDD XT HS and LP osc configuration VOL Output Low Voltage D080 I O port 0 6 V IOL 8 5 mA VDD 4 5V D083 OSC2 CLKOUT 0 6 V IoL 1 6mA VDD 4 5V Note 1 These parameters are characterized but not tested Data in Typ column is at 5 0V 25 C unless otherwise stated These parameters are for design guidance only and are not tested In RC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended to use an external clock in RC mode Negative current is defined as current sourced by the pin The leakage cur
274. modes but shown here for timing reference 14 7 Code Protection This allows customers to manufacture boards with ji unprogrammed devices and then program the micro If the code protection bit s have not been controller just before shipping the product This also programmed the on chip program memory can be allows the most recent firmware or a custom firmware read out using ICSP for verification purposes to be programmed Note The entire data EEPROM and Flash The device is placed into a Program Verify mode by program memory will be erased when the holding the RAO ANO C1IN ICSPDAT ULPWU and code protection is switched from on to off RA1 AN1 C12IN VREF ICSPCLK pins low while rais See the PIC12F6XX 16F6XX Memory ing the MCLR VPP pin from VIL to VIHH See the Programming Specification DS41204 PIC12F6XX 16F6XX Memory Programming Specifi for more information cation DS41204 for more information RAO becomes the programming data and RA1 becomes the 14 8 ID Locations programming clock Both RAO and RA1 are Schmitt Trigger inputs in this mode Four memory locations 2000h 2003h are designated as ID locations where the user can store checksum or other code identification numbers These locations are not accessible during normal execution but are readable and writable during Program Verify mode Only the Least Significant 7 bits of the ID locations are After Reset to place the device into Program Verify mode
275. mption is the least of the three modes This mode is best suited to drive resonators with a low drive level specification for example tuning fork type crystals XT Oscillator mode selects the intermediate gain setting of the internal inverter amplifier XT mode current consumption is the medium of the three modes This mode is best suited to drive resonators with a medium drive level specification for example low frequency AT cut quartz crystal resonators HS Oscillator mode selects the highest gain setting of the internal inverter amplifier HS mode current consumption is the highest of the three modes This mode is best suited for resonators that require a high drive setting for example high frequency AT cut guarta crystal resonators or ceramic resonators Figure 3 3 and Figure 3 4 show typical circuits for quartz crystal and ceramic resonators respectively FIGURE 3 3 QUARTZ CRYSTAL OPERATION LP XT OR HS MODE PIC16F685 687 689 690 OSCH Quartz ES TI Crystal zz Rr as Sleep osc2 e Rs i Note 1 A series resistor Rs may be required for quartz crystals with low drive level 2 The value of RF varies with the Oscillator mode selected typically between 2 MQ to 10 MQ Note 1 Quartz crystal characteristics vary according to type package and manufacturer The user should consult the manufacturer data sheets for specifications and recommended application 2
276. n by setting the CREN bit The RCIF bit will be set when reception is complete The interrupt will be acknowledged if the RCIE and GIE bits are set Read the RCSTA register to determine if any error occurred during reception as well as read bit 9 of data if applicable Read RCREG to determine if the device is being addressed If any error occurred clear the CREN bit If the device has been addressed clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU x64 Baud Rate CLK i 64 BRG16 j SPBRGH SPBRG or i 16 KE EE EE EE or Baud Rate Generator 4 RB5S AN11 RX DT Pin Pin Buffer Data x gt and Control gt Recovery CREN SPEN Interrupt a RX9 RX9D RCREG Register FIFO 8 RCIF Data Bus RCIE DS41262A page 144 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 FIGURE 12 6 ASYNCHRONOUS RECEPTION RB5 AN11 Start Start Start RX DT Pin bit bito Y bit 1 bit 7 8 Stop N bit bit 0 bit 7 8 Stop N bit 4 Ver 7 8 Stop Bt Co ERT E7 Stop wit EAR EE WAA Rcv Shift peg e i f 5 i Rov Buffer Reg J3 i Word 1 Word 2 RCREG RCREG RCIDL T3 l Read Rcv i i Buffer Reg
277. n using Timert with LP oscillator the Schmitt Trigger is bypassed DS41262A page 54 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 TABLE 4 1 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA f d E i f Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR all other Resets 05h 105h PORTA RA5 RA4 RA3 RA2 RA1 RAO XX XXXX uu uuuu 0Bh 8Bh INTCON GIE PEIE TOIE INTE RABIE TOIF INTF RABIF 0000 000x 0000 000x 10Bh 18Bh 10h T1CON TIGINV TMR GE T1CKPS1 TICKPSO TIOSCEN TISYNC TMR1CS TMRION 0000 0000 uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO 0000 0000 0000 0000 1Fh ADCONO ADFM VCFG CHS3 CHS2 CHS1 CHSO GO DONE ADON 0000 0000 0000 0000 81h 181h OPTION REG RABPU INTEDG TOCS TOSE PSA PS2 PS1 PSO 1111 1111 1111 1111 85h 185h TRISA TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 11 1111 11 1111 95h WPUA WPUAS WPUA4 WPUA2 WPUA1 WPUAO 11 111 11 111 96h IOCA IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCAO 00 0000 00 0000 119h CM1CONO C1ON C10UT C1OE C1POL CID C1CH1 C1CHO oooo 000 0000 000 11Eh ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANSO 1111 1111 1111 1111 Legend x unknown u unchanged unimplemented locations read as 0 Shaded cells are not used by PORTA 2005 Microchip Technol
278. nal Q clock or 2 bits of the prescaler to create the 10 bit 11 3 1 PWM OUTPUT CONFIGURATIONS The P1M lt 1 0 gt bits in the CCP1CON register allows one of four configurations Single Output e Half bridge Output Full bridge Output Forward mode Full bridge Output Reverse mode The general relationship of the outputs in all configurations is summarized in Figure 11 3 Note Clearing the CCP1CON register will force the PWM output latches to their default inactive levels This is not the PORTC I O data latch TABLE 11 3 PIN ASSIGNMENTS FOR VARIOUS ENHANCED CCP MODES CCP1CON ECCP Mode Configuration RC5 RC4 RC3 RC2 Compatible CCP 00xx11xx CCP1 RC4 C20UT RC3 AN7 RC2 AN6 Dual PWM 10xx11xx P1A P1B RC3 AN7 RC2 AN6 Quad PWM x1xx11xx P1A P1B P1C P1D Legend x Don t care Shaded cells indicate pin assignments not used by ECCP in a given mode Note 1 TRIS register values must be configured appropriately 2 With ECCP in Dual or Quad PWM mode the C2OUT output control of PORTC must be disabled DS41262A page 116 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 11 3 2 PWM PERIOD A PWM output Figure 11 4 and Figure 11 5 has a time base period and a time that the output is active duty cycle The PWM period is specified by writing to the PR2 register The PWM period can be calculated using the following formula EOUATION 11 1 PWM PERIOD TI
279. nalog input push button switches and eight LEDs 16 16 PICDEM net Internet Ethernet Demonstration Board The PICDEM net demonstration board is an Inter net Ethernet demonstration board using the PIC18F452 microcontroller and TCP IP firmware The board supports any 40 pin DIP device that conforms to the standard pinout used by the PIC16F877 or PIC18C452 This kit features a user friendly TCP IP stack web server with HTML a 24L256 Serial EEPROM for Xmodem download to web pages into Serial EEPROM ICSP MPLAB ICD 2 interface con nector an Ethernet interface RS 232 interface and a 16 x 2 LCD display Also included is the book and CD ROM TCP IP Lean Web Servers for Embedded Systems by Jeremy Bentham 16 17 PICDEM 2 Plus Demonstration Board The PICDEM 2 Plus demonstration board supports many 18 28 and 40 pin microcontrollers including PIC16F87X and PIC18FXX2 devices All the neces sary hardware and software is included to run the dem onstration programs The sample microcontrollers provided with the PICDEM 2 demonstration board can be programmed with a PRO MATE II device program mer PICSTART Plus development programmer or MPLAB ICD 2 with a Universal Programmer Adapter The MPLAB ICD 2 and MPLAB ICE in circuit emulators may also be used with the PICDEM 2 demonstration board to test firmware A prototype area extends the circuitry for additional application components Some of the features include an RS 232 interface a 2 x
280. nce CVREF Voltage References VP6 Gtabillzatlon 89 VRCON Register iieii nktan adnate iieii 90 VREF SEE A D Reference Voltage W Wake up Using Interrupts 0 0 0 eee eee tree eeeees Watchdog Timer WDT 0 cee ee eee eee eeee tees teeeereaeenaeens Associated registers WDTCON Register oe VUNENEE TEE WPUB Register 2012 2e0d EKNEERRNER SEENEN EEN Ee Write Collision Detect bit WCOL ees WWW Address feces dee dee WWW On Line Support ssesssssesssseesrssresiierrerrnrrnerinrrnernerresns DS41262A page 252 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www microchip com This web site is used as a means to make files and information easily available to customers Accessible by using your favorite Internet browser the web site contains the following information Product Support Data sheets and errata application notes and sample programs design resources user s guides and hardware support documents latest software releases and archived software General Technical Support Frequently Asked Questions FAQ technical support requests online discussion groups Microchip consultant program member listing e Business of Microchip Product selector and ordering guides latest Microchip press releases listing of seminars and events listings of Microchip sales offices distribu
281. ncorporated in the U S A Analog for the Digital Age Application Maestro dsPICDEM dsPICDEM net dsPICworks ECAN ECONOMONITOR FanSense FlexROM fuzzyLAB In Circuit Serial Programming ICSP ICEPIC MPASM MPLIB MPLINK MPSIM PICkit PICDEM PICDEM net PICLAB PICtail PowerCal Powerlnfo PowerMate PowerTool rfLAB rfPICDEM Select Mode Smart Serial SmartTel Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U S A and other countries SQTP is a service mark of Microchip Technology Incorporated in the U S A All other trademarks mentioned herein are property of their respective companies 2005 Microchip Technology Incorporated Printed in the U S A All Rights Reserved LI Printed on recycled paper Microchip received ISO TS 16949 2002 quality system certification for its worldwide headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona and Mountain View California in October 2003 The Company quality system processes and procedures are for its PICmicro 8 bit MCUs KEELOQ code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchip s quality system for the design and manufacture of development systems is ISO 9001 2000 certified DS41262A page ii Preliminary 2005 Microchip Technology Inc MICROCHIP PIC16F685 687 689 690 20 Pin Flash Based 8 Bit CMOS Microcontroll
282. nd PIA are available on PIC16F685 PIC16F690 only FIGURE 4 14 BLOCK DIAGRAM OF RC5 Data bus poi CCP10UT Enable eiD Q WR porrg P S 3 ccP our O Pin TRIS TP X Q vss RD lt TRISC RD PORTC To Enhanced CCP Available on PIC16F685 PIC16F690 only DS41262A page 66 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 4 5 7 RC6 AN8 SS The RC6 AN8 SS is configurable to function as one of the following a general purpose UO an analog input for the A D e a slave select input 4 5 8 RC7 AN9 SDO The RC7 AN9 SDO is configurable to function as one of the following a general purpose I O an analog input for the A D a serial data output Note 1 SS is available on PIC16F687 PIC16F689 Note 1 SDO is available on PIC16F687 PIC16F690 only PIC16F689 PIC16F690 only FIGURE 4 15 BLOCK DIAGRAM OF RC6 FIGURE 4 16 BLOCK DIAGRAM OF RC7 Data Bus PORT SDO Select e D Q see Data Bus J SDO WR CK gt PORTCT PX H x lt D Q WR CK Lia vo Pin PORTCTP X H WR a E tais S a vss lo G ZER Analog Input Mode Q WR fo misc SS Analog eet RD lt RD eK geg PORTC TRISC To SS Input RD D To A D Converter PORTC To A D Converter Available on PIC16F685 PIC16F690 only e
283. nerates the special event trigger and the clock edge that generates the TMR1 Reset will preclude the Reset from occurring TABLE 11 2 REGISTERS ASSOCIATED WITH CAPTURE COMPARE AND TIMER1 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR lh othe Resets OBh 8Bh INTCON GIE PEIE TOIE INTE RABIE TOIF INTF RABIF 0000 000x 0000 000x 10Bh 18Bh OCh PIR1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 000 0000 000 0000 0Eh TMRIL Holding Register for the Least Significant Byte of the 16 bit TMR1 Register XXXX XXXX uuuu uuuu OFh TMR1H Holding Register for the Most Significant Byte of the 16 bit TMR1 Register XXXX XXXX uuuu uuuu 10h T1CON TIGINV TMR1GE T1CKPS1 TICKPSO TIOSCEN T1SYNC TMR1CS TMRION 0000 0000 uuuu uuuu 11Bh CM2CON1 MC1OUT MC2OUT T1GSS C2SYNC 00 10 00 10 15h CCPRIL Capture Compare PWM Register 1 Low Byte XXXX XXXX UUUU uuuu 16h CCPR1H Capture Compare PWM Register 1 High Byte XXXX Xxxx UUUU uuuu 17h CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 87h 187h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISCO 1111 1111 1111 1111 8Ch PIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMRIIE 000 0000 000 0000 Legend ee locations read as 0 u unchanged x unknown Shaded cells are not used by the Capture Compare or Timer1 m
284. nformation Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown DS41262A page 70 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 5 4 Prescaler An 8 bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer For simplicity this counter will be referred to as prescaler throughout this data sheet The prescaler assignment is controlled in software by the control bit PSA OPTION REG lt 3 gt Clearing the PSA bit will assign the prescaler to Timer0 Prescale values are selectable via the PS lt 2 0 gt bits OPTION REG lt 2 0 gt The prescaler is not readable or writable When assigned to the Timer0 module all instructions writing to the TMRO register e g CLRF 1 MOVWF 1 BSF 1 x etc will clear the prescaler When assigned to WDT a CLRWDT instruction will clear the prescaler along with the Watchdog Timer 5 4 1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control e it can be changed on the fly during program execution To avoid an unintended device Reset the following instruction sequence Example 5 1 and Example 5 2 must be executed when changing the prescaler assignment from Timer0 to WDT EXAMPLE 5 1 CHANGING PRESCALER TIMERO gt WDT BCF STATUS RPO Bank 0 BCF ST
285. nment by simulating the PiCmicro series microcontrollers on an instruction level On any given instruction the data areas can be examined or modified and stimuli can be applied from a file or user defined key press to any pin The execu tion can be performed in Single Step Execute Until Break or Trace mode The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and MPLAB C18 C Compilers as well as the MPASM assembler The software simulator offers the flexibility to develop and debug code outside of the laboratory environment making it an excellent economical software development tool 16 8 MPLAB SIM30 Software Simulator The MPLAB SIM30 software simulator allows code development in a PC hosted environment by simulating the dsPIC30F series microcontrollers on an instruction level On any given instruction the data areas can be examined or modified and stimuli can be applied from a file or user defined key press to any of the pins The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB ASM30 assembler The simulator runs in either a Command Line mode for automated tasks or from MPLAB IDE This high speed simulator is designed to debug analyze and optimize time intensive DSP routines DS41262A page 204 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 169 MPLAB ICE 2000 High Performance Universal In Circuit Emulator The
286. normal instruction execution time of 1 us All instructions are executed within a single instruction cycle unless a conditional test is true or the program counter is changed as a result of an instruction When this occurs the execution takes two instruction cycles with the second cycle executed as a NOP Note To maintain upward compatibility with future products do not use the OPTION and TRIS instructions All instruction examples use the format oxhh to represent a hexadecimal number where h signifies a hexadecimal digit 151 Read Modify Write Operations Any instruction that specifies a file register as part of the instruction performs a Read Modify Write RMW operation The register is read the data is modified and the result is stored according to either the instruc tion or the destination designator d A read operation is performed on a register even if the instruction writes to that register For example a CLRF PORTA instruction will read PORTA clear all the data bits then write the result back to PORTA This example would have the unintended result of clearing the condition that set the RABIF flag TABLE 15 1 OPCODE FIELD DESCRIPTIONS Field Description Register file address 0x00 to 0x7F w Working register accumulator b Bit address within an 8 bit file register k Literal field constant data or label NW Don t care location 0 or 1
287. nous mode and WUE 0 2005 Microchip Technology Inc PIC16F685 687 689 690 12 3 EUSART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit TXSTA lt 4 gt In this mode the EUSART uses standard non return to zero NRZ for mat one Start bit eight or nine data bits and one Stop bit The most common data format is 8 bits An on chip dedicated 8 bit 16 bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator The EUSART transmits and receives the LSb first The EUSART s transmitter and receiver are functionally independent but use the same data format and baud rate The baud rate generator produces a clock either x16 or x64 of the bit shift rate depending on the BRGH and BRG16 bits TXSTA lt 2 gt and BAUDCTL lt 3 gt Parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit Asynchronous mode is available in all times It is available in Sleep mode only when auto wake up on Sync Break is enabled The baud rate generator values may need to be adjusted if the clocks are changed When operating in Asynchronous mode the EUSART module consists of the following important elements Baud Rate Generator Sampling Circuit Asynchronous Transmitter e Asynchronous Receiver Auto wake up on Sync Break Character 13 bit Break Character Transmit e Auto Baud Detection 12 3 1 EUSART
288. nsmit mode SSPOV must be cleared in software in either mode o No overflow bit 5 SSPEN Synchronous Serial Port Enable bit In SPI mode 1 Enables serial port and configures SCK SDO and SDI as serial port pins 0 Disables serial port and configures these pins as I O port pins In 2C mode 1 Enables the serial port and configures the SDA and SCL pins as serial port pins 0 Disables serial port and configures these pins as I O port pins In both modes when enabled these pins must be properly configured as input or output bit 4 CKP Clock Polarity Select bit In SPI mode 1 Idle state for clock is a high level Microwire default 0 Idle state for clock is a low level Microwire alternate In 2C mode SCK release control 1 Enable clock 0 Holds clock low clock stretch Used to ensure data setup time bit 3 0 SSPM lt 3 0 gt Synchronous Serial Port Mode Select bits 0000 SPI Master mode clock Fosc 4 0001 SPI Master mode clock Fosc 16 0010 SPI Master mode clock Fosc 64 0011 SPI Master mode clock TMR2 output 2 0100 SPI Slave mode clock SCK pin SS pin control enabled 0101 SPI Slave mode clock SCK pin ss pin control disabled SS can be used as I O pin 0110 DC Slave mode 7 bit address 0111 I2C Slave mode 10 bit address 1000 Reserved 1001 Load SSPMSK register at SSPADD SFR address 1010 Reserved 1011 DC Firmware Controlled Master mode slave IDLE 1100 Reserved 1101 Reserved
289. ntain the General Purpose Registers GPR and the Special Function Registers SFR The Special Function Registers are located in the first 32 locations of each bank Register locations 20h 7Fh in Bank O and AOh EFh AO BF PIC16F687 only in Bank 1 are General Purpose Registers implemented as static RAM Register locations FOh FFh in Bank 1 170h 17Fh in Bank 2 and 1FOh 1FFh in Bank 3 point to addresses 70h 7Fh in Bank 0 Other General Purpose Resisters GPR are also available in Bank 1 and Bank 2 depending on the device Details are shown in Figures 2 3 2 4 and 2 5 All other RAM is unimplemented and returns 0 when read RP lt 1 0 gt STATUS lt 6 5 gt are the bank select bits DPI RPO 0 0 Bank 0 is selected 0 1 Bank 1 is selected 1 0 Bank 2 is selected 1 1 Bank 3 is selected 2 2 1 GENERAL PURPOSE REGISTER FILE The register file is organized as 128 x 8 in the PIC16F687 and 256 x 8 in the PIC16F685 PIC16F689 PIC16F690 Each register is accessed either directly or indirectly through the File Select Register FSR see Section 2 4 Indirect Addressing INDF and FSR Registers 2 2 2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device see Tables 2 1 2 2 2 3 and 2 4 These registers are static RAM The special registers can be classified into two sets core and peripheral The Specia
290. nterrupt Read RXREG Note Timing diagram demonstrates Sync Master mode with bit SREN 1 and bit BRGH 0 DS41262A page 150 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 TABLE 12 8 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION P F r F Value on Value ori Addr Name Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O POR BOR all other Resets OCh PIR1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 000 0000 000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X 19h TXREG EUSART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG EUSART Receive Data Register 0000 0000 0000 0000 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 1111 8Ch PIE1 ADIE RCIE TXIE SSPIE CCPIE TMR2IE TMRIIE 000 0000 000 0000 98h TXSTA CSRC TX9 TXEN SYNC SENB BRGH TRMT TX9D 0000 0010 0000 0010 99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRGO 0000 0000 0000 0000 9Ah SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 9Bh BAUDCTL ABDOVF RCIDL SCKP BRG16 WUE ABDEN 01 0 0 00 01 0 0 00 Legend x unknown unimplemented locations read as 0 Shaded cells are not used for Asynchronous Reception Note 1 PIC16F687 PIC16F689 PIC16F690 only O 2005 Microchip Technology Inc Preliminary DS41262A page 151 PIC16F685 687 689 690 12
291. nterrupt EXAMPLE 11 1 CHANGING BETWEEN CAPTURE PRESCALERS BCF STATUS RPO Bank 0 BCF STATUS RP1 CLRF CCP1CON Turn ECCP module off MOVLW NEW CAPT PS Load the W reg with ithe new prescaler move value and ECCP ON Load CCP1CON with this value MOVWF CCP1CON 11 2 Compare Mode In Compare mode the 16 bit CCPR1 register value is constantly compared against the TMR1 register pair value When a match occurs the RC5 CCP1 P1A pin is Driven high e Driven low e Remains unchanged The action on the pin is based on the value of control bits CCP1M lt 3 0 gt CCP1CON lt 3 0 gt At the same time interrupt flag bit CCP1IF PIR1 lt 2 gt is set FIGURE 11 2 COMPARE MODE OPERATION BLOCK DIAGRAM CCP1CON lt 3 0 gt Mode Select Set Flag bit CCP1IF PIR1 lt 2 gt RC5 CCP1 P1A am pin CCPR1H CCPRIL ES Qa S Output V Logic Maich Comparator i R atc ZX TMRTH TMRIL TRISC lt 5 gt Output Enable Special Event Trigger Special Event Trigger will clear TMR1H and TMR1L registers NOT set interrupt flag bit TMR1IF PIR1 lt 0 gt set the GO DONE bit ADCONO lt 1 gt DS41262A page 114 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 11 2 1 CCP1 PIN CONFIGURATION The user must configure the RC5 CCP1 P1A pin as an output by clearing the TRISC lt 5 gt bit Note Clearing the
292. nterrupt The return address is pushed onto the stack The PC is loaded with 0004h For external interrupt events such as the INT pin PORTA PORTB change interrupts the interrupt latency will be three or four instruction cycles The exact latency depends upon when the interrupt event occurs see Figure 14 7 The latency is the same for one or two cycle instructions Once in the Interrupt Service Routine the source s of the interrupt can be determined by polling the interrupt flag bits The interrupt flag bit s must be cleared in software before re enabling interrupts to avoid multiple interrupt requests Note 1 Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit 2 When an instruction that clears the GIE bit is executed any interrupts that were pending for execution in the next cycle are ignored The interrupts which were ignored are still pending to be serviced when the GIE bit is set again For additional information on Timert Timer2 comparators A D data EEPROM EUSART SSP or Enhanced CCP modules refer to the respective peripheral section 14 3 1 RA2 INT INTERRUPT External interrupt on RA2 INT pin is edge triggered either rising if the INTEDG bit OPTION REG lt 6 gt is set or falling if the INTEDG bit is clear When a valid edge appears on the RAZ INT pin the INTF bit INTCON lt 1 gt is set This interrupt can be disabled by clearing
293. ode while the OST is operating Note Due to the wide range of oscillator start up times the Fail Safe circuit is not active during oscillator start up i e after exiting Reset or Sleep After an appropriate amount of time the user should check the OSTS bit OSCCON lt 3 gt to verify the oscillator start up and system clock switchover has successfully completed 2005 Microchip Technology Inc Preliminary DS41262A page 43 PIC16F685 687 689 690 FIGURE 3 9 FSCM TIMING DIAGRAM Sample Clock je ed EE edi bt a System i Oscillator i Clock Failure i i Output Ja _ _ i i _ i CM Output i i i i Q WI l l i Failure i k i i i Detected OSCFIF i A A A CM Test i CM Test i CM Test Note The system clock is normally at a much higher frequency than the sample clock The relative frequencies in this example have been chosen for clarity DS41262A page 44 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 REGISTER 3 2 OSCCON OSCILLATOR CONTROL REGISTER ADDRESS 8Fh TABLE 3 2 SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES U 0 R W 1 R W 1 R W 0 R 1 R 0 R 0 R W 0 IRCF2 IRCF1 IRCFO osts HTS LTS SCS bit 7 bit 0 bit 7 Unimplemented Read as oi bit 6 4 IRCF lt 2 0 gt Internal Oscillator Frequency Select bits 000 31 kHz 001 125 kHz 010 250
294. odule Note 1 PIC16F685 PIC16F690 only 2005 Microchip Technology Inc Preliminary DS41262A page 115 PIC16F685 687 689 690 11 3 Enhanced PWM Mode The Enhanced CCP module produces up to a 10 bit resolution PWM output and may have up to four outputs depending on the selected operating mode These outputs designated P1A through P1D are multiplexed with I O pins on PORTC The pin assignments are summarized in Table 11 3 FIGURE 11 3 Figure 11 3 shows a simplified block diagram of PWM operation To configure I O pins as PWM outputs the proper PWM mode must be selected by setting the PiM lt 1 0 gt and CCP1M lt 3 0 gt bits CCP1CON lt 7 6 gt and CCP1CON lt 3 0 gt respectively The appropriate TRISC bits must also be set as outputs SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON lt 5 4 gt Duty Cycle Registers Bon P1M lt 1 0 gt E CCP1M lt 3 0 gt pes CCPR1L CCP1 P1A Es X RC5 CCP1 P1A WO TRISC lt 5 gt PR1H Slave X lt cc Slave P1B gt RC4 C20UT P1B TRISC lt 4 gt Comparator R Q Controller PIC gt x RC3 AN7 P1C 1 TMR2 1 s TRISC lt 3 gt P1D x RC2 AN6 P1D Comparator Clear Timer2 ear limere toggle PWM pin and ZN TRISC lt gt latch duty cycle PWM1CON Note 1 time base The 8 bit timer TMR2 register is concatenated with the 2 bit inter
295. ogy Inc Preliminary DS41262A page 55 PIC16F685 687 689 690 4 3 PORTB and TRISB Registers PORTB is a 4 bit wide bidirectional port The corresponding data direction register is TRISB Register 4 6 Setting a TRISB bit 1 will make the corresponding PORTB pin an input ie put the corresponding output driver in a High impedance mode Clearing a TRISB bit 0 will make the corresponding PORTB pin an output i e put the contents of the output latch on the selected pin Example 4 3 shows how to initialize PORTB Reading the PORTB register Register 4 5 reads the status of the pins whereas writing to it will write to the port latch All write operations are read modify write operations Therefore a write to a port implies that the port pins are read this value is modified and then written to the port data latch The TRISB register controls the direction of the PORTB pins even when they are being used as analog inputs The user must ensure the bits in the TRISB register are maintained set when using them as analog inputs I O pins configured as analog input always read o EXAMPLE 4 3 INITIALIZING PORTB BCF STATUS RPO Bank 0 BCF STATUS RP1 CLRF PORTB Init PORTB BSF STATUS RPO Bank 1 MOVLW FFh Set RB lt 7 4 gt as inputs MOVWF TRISB H BCF STATUS RPO Bank 0 Note The ANSELH 11Fh register must be initialized to configure an analog channel as a digital input Pins configured as analog inp
296. on Word register When MCLRE 0 the Reset signal to the chip is generated internally When the MCLRE 1 the RA3 MCLR pin becomes an external Reset input In this mode the RA3 MCLR pin has a weak pull up to VDD 14 2 3 POWER UP TIMER PWRT The Power up Timer provides a fixed 64 ms nominal time out on power up only from POR or Brown out Reset The Power up Timer operates from the 31 kHz LFINTOSC oscillator For more information see Section 3 4 Internal Clock Modes The chip is kept in Reset as long as PWRT is active The PWRT delay allows the VDD to rise to an acceptable level A configuration bit PWRTE can disable if set or enable if cleared or programmed the Power up Timer The Power up Timer should be enabled when Brown out Reset is enabled although it is not required The Power up Timer delay will vary from chip to chip and vary due to e VDD variation Temperature variation e Process variation See DC parameters for details Section 17 0 Electrical Specifications DS41262A page 176 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 14 2 4 BROWN OUT RESET BOR The BOREN0 and BORENI bits in the Configuration Word register select one of four BOR modes Two modes have been added to allow software or hardware control of the BOR enable When BOREN lt 1 0 gt 01 the SBOREN bit PCON lt 4 gt enables disables the BOR allowing it to be controlled in softwar
297. ower on Reset POR and if enabled after PWRT has expired or e Wake up from Sleep If the external clock oscillator is configured to be anything other than LP XT or HS mode then Two Speed Start up is disabled This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep 3 6 2 TWO SPEED START UP SEQUENCE 1 Wake up from Power on Reset or Sleep 2 Instructions begin execution by the internal oscillator at the frequency set in the IRCF bits OSCCON lt 6 4 gt 3 OST enabled to count 1024 clock cycles 4 OST timed out wait for falling edge of the internal oscillator 5 OSTS is set 6 System clock held low until the next falling edge of new clock LP XT or HS mode 7 System clock is switched to external clock source 2005 Microchip Technology Inc Preliminary DS41262A page 41 PIC16F685 687 689 690 3 6 3 CHECKING EXTERNAL INTERNAL CLOCK STATUS Checking the state of the OSTS bit OSCCON lt 3 gt will confirm if the PIC16F685 687 689 690 is running from the external clock source as defined by the FOSC bits in the Configuration Word register CONFIG or the internal oscillator FIGURE 3 7 TWO SPEED START UP Qro ara qr 92 93 ng OH NTS NIIP TOST OSC1 ry 0 X 1 Oe CE aoe osce d de qu SR E Program Counter 4 PC X PC XPC 2 E KA Wa NI
298. ows editing building downloading and source debugging from a single environment The MPLAB ICD 4000 is a premium emulator system providing the features of MPLAB ICE 2000 but with increased emulation memory and high speed perfor mance for dsPIC30F and PIC18XXXX devices Its advanced emulator features include complex triggering and timing up to 2 Mb of emulation memory and the ability to view variables in real time The MPLAB ICE 4000 in circuit emulator system has been designed as a real time emulation system with advanced features that are typically found on more expensive development tools The PC platform and Microsoft Windows 32 bit operating system were chosen to best make these features available in a simple unified application 16 11 MPLAB ICD 2 In Circuit Debugger Microchip s In Circuit Debugger MPLAB ICD 2 is a powerful low cost run time development tool connecting to the host PC via an RS 232 or high speed USB interface This tool is based on the Flash PlCmicro MCUs and can be used to develop for these and other PlCmicro microcontrollers The MPLAB ICD 2 utilizes the in circuit debugging capability built into the Flash devices This feature along with Microchip s In Circuit Serial Programming ICSP protocol offers cost effective in circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment This enables a designer to develop and debug source code by setting b
299. pheral Interrupt Request Register 1 PIR1 record individual interrupt requests in flag bits The INTCON register also has individual and global interrupt enable bits A Global Interrupt Enable bit GIE INTCON lt 7 gt enables if set all unmasked interrupts or disables if cleared all interrupts Individual interrupts can be disabled through their corresponding enable bits in the INTCON PIE1 and PIE2 registers respectively GIE is cleared on Reset The Return from Interrupt instruction RETFIE exits the interrupt routine as well as sets the GIE bit which re enables unmasked interrupts The following interrupt flags are contained in the INTCON register e INT Pin Interrupt e PORTA PORTB Change Interrupts e TMRO Overflow Interrupt The peripheral interrupt flags are contained in the special registers PIR1 and PIR2 The corresponding interrupt enable bits are contained in special registers PIE1 and PIE2 The following interrupt flags are contained in the PIR1 register e A D Interrupt EUSART Receive and Transmit Interrupts e Timer1 Overflow Interrupt Synchronous Serial Port SSP Interrupt Enhanced CCP1 Interrupt Timer1 Overflow Interrupt Timer2 Match Interrupt The following interrupt flags are contained in the PIR2 register Fail Safe Clock Monitor Interrupt e 2 Comparator Interrupts e EEPROM Data Write Interrupt When an interrupt is serviced The GIE is cleared to disable any further i
300. pose UO an analog input for the A D an analog input to Comparator 1 or 2 e a voltage reference input for the A D In Circuit Serial Programming clock 4 2 4 3 RA2 AN2 TOCKI INT C10OUT Figure 4 3 shows the diagram for this pin The RA2 AN2 TOCKI INT C1 OUT pin is configurable to function as one of the following a general purpose I O an analog input for the A D the clock input for TMRO an external edge triggered interrupt a digital output from Comparator 1 FIGURE 4 2 BLOCK DIAGRAM OF RA FIGURE 4 3 BLOCK DIAGRAM OF RA2 Analog Analog Data Bus Input Mode Data Bus D Q put Mode D Q Von VDD WR CK a WR CK a gt Q Weak WPUATP XO Weak WPUA TPN wea RD ES RABPU RD c RABPU WPUA WPUA C10UT Enable ein Q VDD eD Q VDD WR K x WR CK amp PORTATP S a PORTA P H C10UT4 1 rr UO Pin 9 VO Pin D Q e D Qe WR x WR S TRISAT SK Vss TRISATP SK G vss Analog Analog RD Input Mode RD La Input Mode TRISA TRISA d RD SSES RD lt PORTA PORTA D Q e1D Q WR Ik CK 5 40 DES WA le ea Dp oca PA H loca TP Q EN Q3 EN Q3 RD RD IOCA Q D IOCA a DpH EN
301. program or data space and the Stack Pointer is not readable or writable The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch The stack is POPed in the event of a RETURN RETLW Or a RETFIE instruction execution PCLATH is not affected by a PUSH or POP operation The stack operates as a circular buffer This means that after the stack has been PUSHed eight times the ninth push overwrites the value that was stored from the first push The tenth push overwrites the second push and so on Note 1 There are no Status bits to indicate stack overflow or stack underflow conditions 2 There are no instructions mnemonics called PUSH or POP These are actions that occur from the execution of the CALL RETURN RETLW and RETFIE instructions or the vectoring to an interrupt address 2 4 Indirect Addressing INDF and FSR Registers The INDF register is not a physical register Addressing the INDF register will cause indirect addressing Indirect addressing is possible by using the INDF register Any instruction using the INDF register actually accesses data pointed to by the File Select Register FSR Reading INDF itself indirectly will produce 00h Writing to the INDF register indirectly results in a no operation although Status bits may be affected An effective 9 bit address is obtained by concatenating the 8 bit FSR and the IRP bit STATUS lt 7 gt as shown in Figure 2 7
302. proper bit rate The measurement is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal After a Start bit the SPBRG begins counting up using the preselected clock source on the first rising edge of RX After eight bits on the RX pin or the fifth rising edge an accumulated value totalling the proper BRG period is left in the SPBRGH SPBRG registers Once the 5th edge is seen should correspond to the Stop bit the ABDEN bit is automatically cleared While calibrating the baud rate period the BRG registers are clocked at 1 8th the pre configured clock rate Note that the BRG clock will be configured by the BRG16 and BRGH bits Independent of the BRG16 bit setting both the SPBRG and SPBRGH will be used as a 16 bit counter This allows the user to verify that no carry occurred for 8 bit modes by checking for 00h in the SPBRGH register Refer to Table 12 4 for counter clock rates to the BRG While the ABD sequence takes place the EUSART state machine is held in IDLE The RCIF interrupt is set once the fifth rising edge on RX is detected The value in the RCREG needs to be read to clear the RCIF inter rupt RCREG content should be discarded Note 1 If the WUE bit is set with the ABDEN bit auto baud rate detection will occur on the byte following the Break character see Section 12 3 4 Auto Wake up on RX Pin Falling Edge 2 It is up to the user to determine th
303. pt on change Individually enabled pull up TX CMOS EUSART asynchronous output CK ST CMOS EUSART synchronous clock RC0 AN4 C2IN RC0 ST CMOS General purpose I O AN4 AN A D Channel 4 input C2IN AN Comparator 2 positive input RC1 AN5 C12IN RC1 ST CMOS General purpose 1 0 AN5 AN A D Channel 5 input C12IN AN Comparator 1 or 2 negative input RC2 AN6 P1D RC2 ST CMOS General purpose 1 0 AN6 AN A D Channel 6 input P1D CMOS PWM output RC3 AN7 P1C RC3 ST CMOS General purpose 1 0 AN7 AN A D Channel 7 input P1C CMOS PWM output RC4 C2OUT P1B RC4 ST CMOS General purpose 1 0 C20UT CMOS Comparator 2 output P1B CMOS PWM output RC5 CCP1 P1A RC5 ST CMOS General purpose 1 0 CCP1 ST CMOS Capture Compare input P1A ST CMOS PWM output RC6 AN8 SS RC6 ST CMOS General purpose 1 0 AN8 AN A D Channel 8 input ss ST Slave Select input RC7 AN9 SDO RC7 ST CMOS General purpose I O AN9 AN A D Channel 9 input SDO CMOS SPI data output Vss Vss Power Ground reference VDD VDD Power Positive supply Legend AN Analog input or output CMOS CMOS compatible input or output OD Open Drain TTL TTL compatible input ST Schmitt Trigger input with CMOS levels HV High Voltage XTAL Crystal 2005 Microchip Technology Inc Preliminary DS41262A page 13 PIC16F685 687 689 690 NOTES EEE EEE REAR RE REA EAR SAR EG EE EEE EE DS41262A page 14 Prel
304. rammable Dead Band Delay for more details of the dead band delay operations FIGURE 11 7 Standard Half bridge Circuit Push Pull Since the P1A and P1B outputs are multiplexed with the PORTC lt 5 4 gt data latches the TRISC lt 5 4 gt bits must be cleared to configure P1A and P1B as outputs FIGURE 11 6 HALF BRIDGE PWM OUTPUT Period D s Period o Duty Cycle i PAR ais ASA rtd La WEE I pipe K L WI td Dead Band Delay Note 1 At this time the TMR2 register is egual to the PR2 register 2 Output signals are shown as active high EXAMPLES OF HALF BRIDGE APPLICATIONS PIA gt PIC16F685 690 FET Driver P1B gt Half bridge Output Driving a Full bridge Circuit V T EN 4 SR Load T1 al Ki SE V FET Driver P1A PIC16F685 690 FET Driver P1B FET Driver NI amp OI I Load FET Driver 2005 Microchip Technology Inc Preliminary DS41262A page 119 PIC16F685 687 689 690 11 3 5 FULL BRIDGE MODE In Full bridge Output mode four pins are used as outputs however only two outputs are active at a time In the Forward mode pin RC5 CCP1 P1A is continuously active and pin RC2 AN6 P1D is modulated In the Reverse mode RC3 AN7 P1C pin is continuously active and RC4 C2OUT P1B pin
305. rawing No C04 094 2005 Microchip Technology Inc Preliminary DS41262A page 241 PIC16F685 687 689 690 20 Lead Plastic Shrink Small Outline SS 209 mil Body 5 30 mm SSOP E gt I EI SS i I D B O 2 n 1 oy c i LI vd dd E Sr L A1 Units INCHES MILLIMETERS Dimension Limits MIN NOM MAY MIN NOM MAX Number of Pins n 20 20 Pitch p 026 0 65 Overall Height A 079 2 00 Molded Package Thickness A2 065 069 073 1 65 1 75 1 85 Standoff A1 002 0 05 Overall Width E 291 307 323 7 40 7 80 8 20 Molded Package Width E1 197 209 220 5 00 5 30 5 60 Overall Length D 272 283 289 295 7 20 7 50 Foot Length L 022 030 037 0 55 0 75 0 95 Lead Thickness c 004 010 0 09 0 25 Foot Angle f 0 4 8 0 4 8 Lead Width B 009 015 0 22 S 0 38 Controlling Parameter Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Eguivalent MO 150 Drawing No C04 072 Revised 11 03 03 DS41262A page 242 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 20
306. re a valid read taken care of in hardware However the user should keep in mind that reading the 16 bit timer in two 8 bit values itself poses certain problems since the timer may overflow between the reads For writes it is recommended that the user simply stop the timer and write the desired values A write contention may occur by writing to the timer registers while the register is incrementing This may produce an unpredictable value in the timer register 6 6 Timer1 Oscillator A crystal oscillator circuit is built in between pins OSC1 input and OSC2 amplifier output It is enabled by setting control bit TIOSCEN T1CON lt 3 gt The oscillator is a low power oscillator rated up to 32 kHz It will continue to run during Sleep It is primarily intended for a 32 kHz crystal Table 3 1 shows the capacitor selection for the Timer1 oscillator The Timer oscillator is shared with the system LP oscillator Thus Timer1 can use this mode only when the primary system clock is derived from the internal oscillator As with the system LP oscillator the user must provide a software time delay to ensure proper oscillator start up TRISA5 and TRISA4 bits are set when the Timer1 oscillator is enabled RA5 and RA4 bits read as o and TRISA5 and TRISA4 bits read as 1 Note The oscillator requires a start up and stabilization time before use Thus T1OSCEN should be set and a suitable delay observed prior to enabling Timer1
307. re alternate 0 Data transmitted on falling edge of SCK SPI mode CKP 1 1 Data transmitted on falling edge of SCK Microwire default 0 Data transmitted on rising edge of SCK 2C mode This bit must be maintained clear D A Data Address bit I2C mode only 1 Indicates that the last byte received or transmitted was data 0 Indicates that the last byte received or transmitted was address P Stop bit C mode only This bit is cleared when the SSP module is disabled or when the Start bit is detected last SSPEN is cleared 1 Indicates that a Stop bit has been detected last this bit is 0 on Reset 0 Stop bit was not detected last S Start bit IPC mode only This bit is cleared when the SSP module is disabled or when the Stop bit is detected last SSPEN is cleared 1 Indicates that a Start bit has been detected last this bit is o on Reset 0 Start bit was not detected last RW Read Write bit Information I2C mode only This bit holds the R W bit information following the last address match This bit is only valid from the address match to the next Start bit Stop bit or ACK bit 1 Read 0 Write UA Update Address bit 10 bit C mode only 1 Indicates that the user needs to update the address in the SSPADD register 0 Address does not need to be updated BF Buffer Full Status bit Receive SPI and DC modes 1 Receive complete SSPBUF is full 0 Receive not complet
308. re are fourteen analog channels on 1 TAD must be selected to ensure a minimum TAD of PIC16F685 687 689 690 The CHS lt 3 0 gt bits 1 6 us Table 9 1 shows a few TAD calculations for ADCONO lt 5 2 gt control which channel is connected to selected frequencies the sample and hold circuit TABLE 9 1 TaD VS DEVICE OPERATING FREQUENCIES A D Clock Source TAD Device Frequency Operation ADCS lt 2 0 gt 20 MHz 5 MHz 4 MHz 1 25 MHz 2 Tosc 000 100 ns 400 ns 500 ns 1 6 us 4 Tosc 100 200 ns 800 ns 1 0 us 3 2 us 8 Tosc 001 400 pel 1 6 us 2 0 us 6 4 us 16 Tosc 101 800 ns 3 2 us 4 0 us 12 8 us 32 Tosc 010 1 6 us 6 4 us 8 0 us 25 6 usi 64 Tosc 110 3 2 us 12 8 us 16 0 us 51 2 us A D RC x11 2 6 us 1 4 2 6 us 1 4 2 6 us 1 4 2 6 us 1 4 Legend Shaded cells are outside of recommended range Note 1 The A D RC source has a typical TAD time of 4 us for VDD gt 3 0V 2 These values violate the minimum required TAD time 3 For faster conversion times the selection of another clock source is recommended 4 When the device frequency is greater than 1 MHz the A D RC clock source is only recommended if the conversion will be performed during Sleep DS41262A page 94 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 9 1 5 STARTING A CONVERSION The A D conversion is initiated by setting the GO DONE bit ADCONO lt 1 gt When the conversion is complete the A D
309. reakpoints single stepping and watching variables CPU status and peripheral registers Running at full speed enables testing hardware and applications in real time MPLAB ICD 2 also serves as a development programmer for selected PICmicro devices 16 12 PRO MATE Il Universal Device Programmer The PRO MATE II is a universal CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability It features an LCD display for instructions and error messages and a modular detachable socket assembly to support various package types In Stand Alone mode the PRO MATE II device programmer can read verify and program PlCmicro devices without a PC connection It can also set code protection in this mode 16 13 MPLAB PM3 Device Programmer The MPLAB PMS is a universal CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability It features a large LCD display 128 x 64 for menus and error messages and a modular detachable socket assembly to support various package types The ICSP cable assembly is included as a standard item In Stand Alone mode the MPLAB PM3 device program mer can read verify and program PlCmicro devices without a PC connection It can also set code protection in this mode MPLAB PM3 connects to the host PC via an RS 232 or USB cable MPLAB PM has high speed communications and optimized algorithms for quick programming of
310. reliminary DS41262A page 209 PIC16F685 687 689 690 FIGURE 17 1 PIC16F685 687 689 690 VOLTAGE FREGUENCY GRAPH 40 C lt TA lt 125 C 5 5 VDD Volts F 0 4 8 10 12 16 20 Frequency MHz Note 1 The shaded region indicates the permissible combinations of voltage and frequency DS41262A page 210 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 17 1 DC Characteristics PIC16F685 687 689 690 1 Industrial PIC16F685 687 689 690 E Extended Standard Operating Conditions unless otherwise stated DC CHARACTERISTICS Operating temperature 40 C lt TA lt 85 C for industrial 40 C lt TA lt 125 C for extended he Sym Characteristic Min Typt Max Units Conditions VDD Supply Voltage D001 2 0 5 5 V Fosc lt 4 MHz D001C 3 0 5 5 V Fosc lt 10 MHz D001D 4 5 5 5 V Fosc lt 20 MHz D002 VDR RAM Data Retention 14 55 V Device in Sleep mode Voltage D003 VPOR_ VDD Start Voltage to Vss V See Section 14 2 1 Power On Reset ensure internal Power on POR for details Reset signal D004 SvDD VDD Rise Rate to ensure 0 05 V ms See Section 14 2 1 Power On Reset internal Power on Reset POR for details signal D005 VBOR VDD Voltage Required to 2 025 12175 V initiate a Brown Out Reset These parameters are characte
311. rent on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages See Section 10 0 Data EEPROM and Flash Program Memory Control for additional information DS41262A page 216 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 174 DC Characteristics PIC16F685 687 689 690 I Industrial PIC16F685 687 689 690 E Extended Continued DC CHARACTERISTICS Standard Operating Conditions unless otherwise stated 40 C lt TA lt 85 C for industrial 40 C lt TA lt 125 C for extended Operating temperature Se Sym Characteristic Min Typt Max Units Conditions VOH Output High Voltage D090 I O port Vpp 0 7 V IOH 3 0 mA VDD 4 5V D092 OSC2 CLKOUT Vpp 0 7 V loH 1 3 mA VDD 4 5V D100 IULP Ultra Low Power Wake up 200 nA Current Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin 15 pF In XT HS and LP modes when external clock is used to drive OSC1 D101 Cio All I O pins 50 pF Data EEPROM Memory D120 Ep Byte Endurance 100K 1M E W 40 C lt TA lt 85 C D120A ED Byte Endurance 10K 100K E W 85 C lt TA lt 125 C D121 VDRW VDD for Read Write VMIN 5 5 V Using EECON1 to read write VMIN Minimum operating voltage D122 TDEW Erase Write Cycle Time
312. requency Tuning bits 01111 Maximum frequency 01110 00001 00000 Oscillator module is running at the calibrated frequency 11111 10000 Minimum frequency Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 39 PIC16F685 687 689 690 3 4 3 LFINTOSC The Low Freguency Internal Oscillator LFINTOSC is an uncalibrated approximate 31 kHz internal clock source The output of the LFINTOSC connects to a postscaler and multiplexer see Figure 3 1 31 kHz can be selected via software using the IRCF bits see Section 3 4 4 Frequency Select Bits IRCF The LFINTOSC is also the frequency for the Power up Timer PWRT Watchdog Timer WDT and Fail Safe Clock Monitor FSCM The LFINTOSC is enabled by selecting 31 kHz IRCF 000 as the system clock source SCS 1 or when any of the following are enabled Two Speed Start up IESO 1 and IRCF 000 e Power up Timer PWRT e Watchdog Timer WDT Fail Safe Clock Monitor FSCM The LF Internal Oscillator LTS bit OSCCON lt 1 gt indicates whether the LFINTOSC is stable or not 3 4 4 FREQUENCY SELECT BITS IRCF The output of the 8 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer see Figure 3 1 The Internal Oscillator Frequency selec
313. ridge P1B Inactive a i 01 Forward i P1C Inactive i i P1D Modulated PIA Inactive a Full bridge P1B Modulated l 11 Reverse _ i P1C Active a Wa gs P1D Inactive i f Relationships Period 4 Tosc PR2 1 TMR2 prescale value Duty Cycle Tosc CCPR1L lt 7 0 gt CCP1CON lt 5 4 gt TMR2 prescale value Delay 4 Tosc PWM1CON lt K lt 6 0 gt Note 1 Dead band delay is programmed using the PWM1CON register Section 11 3 7 Programmable Dead Band Delay DS41262A page 118 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 11 3 4 HALF BRIDGE MODE In the Half bridge Output mode two pins are used as outputs to drive push pull loads The PWM output signal is output on the RC5 CCP1 P1A pin while the complementary PWM output signal is output on the RC4 C20UT P1B pin Figure 11 6 This mode can be used for half bridge applications as shown in Figure 11 7 or for full bridge applications where four power switches are being modulated with two PWM signals In Half bridge Output mode the programmable dead band delay can be used to prevent shoot through current in half bridge power devices The value of bits PDC lt 6 0 gt PWM1CON lt 6 0 gt sets the number of instruction cycles before the output is driven active If the value is greater than the duty cycle the corresponding output remains inactive during the entire cycle See Section 11 3 7 Prog
314. rized access to your software or other copyrighted work you may have a right to sue for relief under that Act Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates It is your responsibility to ensure that your application meets with your specifications MICROCHIP MAKES NO REPRESENTATIONS OR WAR RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED WRITTEN OR ORAL STATUTORY OR OTHERWISE RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ITS CONDITION QUALITY PERFORMANCE MERCHANTABILITY OR FITNESS FOR PURPOSE Microchip disclaims all liability arising from this information and its use Use of Microchip s products as critical components in life support systems is not authorized except with express written approval by Microchip No licenses are conveyed implicitly or otherwise under any Microchip intellectual property rights QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV ISO TS 16949 2002 Trademarks The Microchip name and logo the Microchip logo Accuron dsPIC KEELOQ microID MPLAB PIC PICmicro PICSTART PRO MATE PowerSmart rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U S A and other countries AmpLab FilterLab Migratable Memory MXDEV MXLAB PICMASTER SEEVAL SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology I
315. rized but not tested Data in Typ column is at 5 0V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 This is the limit to which VDD can be lowered in Sleep mode without losing RAM data 2005 Microchip Technology Inc Preliminary DS41262A page 211 PIC16F685 687 689 690 17 2 DC Characteristics PIC16F685 687 689 690 I Industrial Standard Operating Conditions unless otherwise stated DC CHARACTERISTICS Operating temperature 40 C lt TA lt 85 C for industrial Conditions ea Device Characteristics Min Typt Max Units 9 VDD Note DO10 Supply Current pp 2 9 TBD pA 2 0 Fosc 32 kHz ans 18 TBD UA ap LP Oscillator mode 35 TBD uA 5 0 D011 110 TBD uA 2 0 Fosc 1 MHz 190 TBD UA ao XT Oscillator mode 330 TBD HA 5 0 D012 220 TBD HA 2 0 Fosc 4 MHz 370 TBD uA ao XT Oscillator mode 0 6 TBD mA 5 0 D013 70 TBD uA 2 0 Fosc 1 MHz 140 TBD UA 3 0 EC Oscillator mode 260 TBD uA 5 0 D014 180 TBD uA 2 0 Fosc 4 MHz SS 320 TBD UA 3 9 EC Oscillator mode 580 TBD uA 5 0 D015 TBD TBD uA 2 0 Fosc 31 kHz TBD TBD UA 3 0 INTOSC mode TBD TBD mA 5 0 D016 340 TBD uA 2 0 Fosc 8 MHz 500 TBD uA 3 0 INTOSC mode 0 8 TBD mA 5 0 D017 180 TBD uA 2 0
316. rmware is included along with the User s Guide DS41262A page 206 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 16 20 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers including PIC17C752 PIC17C756A PIC17C762 and PIC17C766 A pro grammed sample is included The PRO MATE II device programmer or the PICSTART Plus development pro grammer can be used to reprogram the device for user tailored application development The PICDEM 17 demonstration board supports program download and execution from external on board Flash memory A generous prototype area is available for user hardware expansion 16 21 PICDEM 18R PIC18C601 801 Demonstration Board The PICDEM 18R demonstration board serves to assist development of the PIC18C601 801 family of Microchip microcontrollers It provides hardware implementation of both 8 bit Multiplexed Demultiplexed and 16 bit Memory modes The board includes 2 Mb external Flash memory and 128 Kb SRAM memory as well as serial EEPROM allowing access to the wide range of memory types supported by the PIC18C601 801 16 22 PICDEM LIN PIC16C43X Demonstration Board The powerful LIN hardware and software kit includes a series of boards and three PICmicro microcontrollers The small footprint PIC16C432 and PIC16C433 are used as slaves in the LIN communication and feat
317. rnal clock sources via the System Clock Selection SCS bit see Section 3 5 Clock Switching 3 3 External Clock Modes 3 3 1 OSCILLATOR START UP TIMER OST If the PIC16F685 687 689 690 is configured for LP XT or HS modes the Oscillator Start up Timer OST counts 1024 oscillations from the OSC1 pin following a Power on Reset POR and the Power up Timer PWRT has expired if configured or a wake up from Sleep During this time the program counter does not increment and program execution is suspended The OST ensures that the oscillator circuit using a quartz crystal resonator or ceramic resonator has started and is providing a stable system clock to the PIC16F685 687 689 690 When switching between clock sources a delay is required to allow the new clock to stabilize These oscillator delays are shown in Table 3 1 In order to minimize latency between external oscillator start up and code execution the Two Speed Clock Start up mode can be selected see Section 3 6 Two Speed Clock Start up Mode TABLE 3 1 OSCILLATOR DELAY EXAMPLES Switch From Switch To Frequency Oscillator Delay Slee Eon BE 125 ae i 8 MHz Sleep POR EC RC DC 20 MHz 5 us 10 us approx CPU Start up LFINTOSC 31 kHz EC RC DC 20 MHz Sleep POR LP XT HS 32 kHz to 20 MHz 1024 Clock Cycles OST LFINTOSC 31 kHz HFINTOSC 125 kHz to 8 MHz 1 us approx Note 1 The 5us to 10 us start up delay is based on
318. rnational Locations 2005 Microchip Technology Inc Preliminary DS41262A page 253 PIC16F685 687 689 690 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod uct If you wish to provide your comments on organization clarity subject matter and ways in which our documentation can better serve you please FAX your comments to the Technical Publications Manager at 480 792 4150 Please list the following information and use this outline to provide us with your comments about this document To Technical Publications Manager Total Pages Sent RE Reader Response From Name Company Address City State ZIP Country Telephone FAX z Application optional Would you like a reply Y N Device PIC16F685 687 689 690 Literature Number DS41262A Ouestions 1 What are the best features of this document 2 How does this document meet your hardware and software development needs 3 Do you find the organization of this document easy to follow If not why 4 What additions to the document do you think would enhance the structure and subject 5 What deletions from the document could be made without affecting the overall usefulness 6 Is there any incorrect or misleading information what and where 7 How would you improve this document DS41262A page 254 Prelimina
319. rsion Time 11 TAD Set GO bit to new data in A D Result not including register Acquisition Time 132 Taco Acquisition Time 11 5 us 5 us The minimum time is the amplifier settling time This may be used if the new input voltage has not changed by more than 1 LSb i e 4 1 mV 4 096V from the last sampled voltage as stored on CHOLD 134 Teo Q4 to A D Clock Tosc 2 lf the A D clock source is selected as Start RC a time of TCY is added before the A D clock starts This allows the SLEEP instruction to be executed These parameters are characterized but not tested Data in Typ column is at 5 0V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 ADRESH and ADRESL registers may be read on the following Tcy cycle 2 See Table 9 1 for minimum conditions DS41262A page 234 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 FIGURE 17 18 PIC16F685 687 689 690 A D CONVERSION TIMING SLEEP MODE BSF ADCONO coX 134 Tosc 2 Tey izi te 1 Toy Q4 130 ae A D CLK At A D Data XONCENO KEK E E COX ADRES OLD DATA X NEW DATA ADIF cc KEN GO 55 DONE al Sampling Stopped 2 Sample Note 1 If the A D clock source is selected as RC a time of Tcy is added before the A D clock starts This allows the
320. rupt on change is disabled on a Power on Reset For enabled interrupt on change pins the values are compared with the old value latched on the last read of PORTA The mismatch outputs of the last read are OR d together to set the PORTA Change Interrupt Flag bit RABIF in the INTCON register Register 2 3 REGISTER 4 4 This interrupt can wake the device from Sleep The user in the Interrupt Service Routine clears the interrupt by a Any read or write of PORTA This will end the mismatch condition then b Clear the flag bit RABIF A mismatch condition will continue to set flag bit RABIF Reading PORTA will end the mismatch condition and allow flag bit RABIF to be cleared The latch holding the last read value is not affected by a MCLR nor BOR Reset After these Resets the RABIF flag will continue to be set if a mismatch is present Note If a change on the I O pin should occur when the read operation is being executed start of the Q2 cycle then the RABIF interrupt flag may not get set IOCA INTERRUPT ON CHANGE PORTA REGISTER ADDRESS 96h U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCAO bit 7 bit 0 bit 7 6 Unimplemented Read as oi bit 5 0 IOCA lt 5 0 gt Interrupt on change PORTA Control bit 1 Interrupt on change enabled 0 Interrupt on change disabled Note 1 Global Interrupt Enable GIE must be enabled for indi
321. ry 2005 Microchip Technology Inc PIC16F685 687 689 690 PRODUCT IDENTIFICATION SYSTEM To order or obtain information e g on pricing or delivery refer to the factory or the listed sales office PART NO X XX XXX T T gig Examples Device Temperature Package Pattern a PIC16F685 I ML 301 Industrial temp QFN Range package QTP pattern 301 b PIC16F689 I SO Industrial temp SOIC package KC 1 1 1 o PIC16F690T T E SS Extended temp Device PIC16F685 1 PIC16F687 1 PIC16F689 SSOP package PIC16F690 VDD range 4 2V to 5 5V Temperature Range 40 C to 85 C Industrial 40 C to 125 C Extended Package ML QFN Quad Flat no lead P PDIP SO SOIC ss SSOP Note 1 Te intape and reel SSOP SOIC and Pattern QTP SQTP Code or Special Requirements QFN packages only blank otherwise O 2005 Microchip Technology Inc Preliminary DS41262A page 255 MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 480 792 7200 Fax 480 792 7277 Technical Support http support microchip com Web Address www microchip com Atlanta Alpharetta GA Tel 770 640 0034 Fax 770 640 0307 Boston Westborough MA Tel 774 760 0087 Fax 774 760 0088 Chicago Itasca IL Tel 630 285 0071 Fax 630 285 0075 Dallas Addison TX Tel 972 818 7423 Fax 972 818 2924 Detroit Far
322. s soon as the last bit is transmitted the TSR is loaded with new data from the TXREG if available Once the TXREG register transfers the data to the TSR register occurs in one TCYCLE the TXREG is empty and interrupt bit TXIF PIR1 lt 4 gt is set The interrupt can be enabled disabled by setting clearing enable bit TXIE PIE1 lt 4 gt Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software It will reset only when new data is loaded into the TXREG register While flag bit TXIF indicates the status of the TXREG register another bit TRMT TXSTA lt 1 gt shows the status of the TSR register TRMT is a read only bit which is set when the TSR is empty No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty The TSR is not mapped in data memory so it is not available to the user To set up a Synchronous Master Transmission 1 Initialize the SPBRGH SPBRG registers for the appropriate baud rate Set or clear the BRGH and BRG16 bits as required to achieve the desired baud rate 2 Enable the synchronous master serial port by setting bits SYNC SPEN and CSRC If interrupts are desired set enable bit TXIE If 9 bit transmission is desired set bit TX9 Enable the transmission by setting bit TXEN If 9 bit transmission is selected the ninth bit should be loaded in bit TX9D 7 Start transmission by loadin
323. s Master Reception 9 1 Initialize the SPBRGH SPBRG registers for the appropriate baud rate Set or clear the BRGH and BRG16 bits as required to achieve the desired baud rate 11 2 Enable the synchronous master serial port by setting bits SYNC SPEN and CSRC 10 Ensure bits CREN and SREN are clear If interrupts are desired set enable bit RCIE If 9 bit reception is desired set bit RX9 If a single reception is required set bit SREN For continuous reception set bit CREN Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set Read the RCSTA register to get the 9th bit if enabled and determine if any error occurred during reception Read the 8 bit received data by reading the RCREG register If any error occurred clear the error by clearing bit CREN If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON lt 7 6 gt are set FIGURE 12 12 SYNCHRONOUS RECEPTION MASTER MODE SREN adasjadajazjasiadaijaziasjagjarjagiagiagiaraziagiagarjajasjadiayjagiagjagjajjaziasjadiaijagasiagjat azlasjagaijagiasja4 Gran Xi bito KT biti Si H XK bits XK RB7 bita YA bits X bite gt C DI TX CK pin SCKP 0 RB7 TX CK pin Write to SCKP 1 i Lo Kai Le he El ET e OR bit SREN La SREN bit CRENbit 0 RCIF bit I
324. s XK bit 4 oe 1 bit 7 Nv bit 6 X bit 5 XK bit 4 si HO on E GE SMP 0 SDI SMP 1 lt Teas t t t SMP 1 SSPIF a SSPSR to SSPBUF A Next Q4 Cycle after Q24 DS41262A page 160 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 13 6 Slave Mode In Slave mode the data is transmitted and received as the external clock pulses appear on SCK When the last bit is latched the SSPIF interrupt flag bit is set While in Slave mode the external clock is supplied by the external clock source on the SCK pin This external clock must meet the minimum high and low times as specified in the electrical specifications While in Sleep mode the slave can transmit receive data When a byte is received the device will wake up from Sleep 13 7 Slave Select Synchronization The SS pin allows a Synchronous Slave mode The SPI must be in Slave mode with SS pin control enabled SSPCON lt 3 0 gt 04h The pin must not be driven low for the SS pin to function as an input The data latch must be high When the SS pin is low transmission and reception are enabled and the SDO pin is driven When the SS pin goes high the SDO pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output External pull up pull down resistors may be desirable depen
325. s as 0 q value depends on condition Note 1 If VDD goes too low Power on Reset will be activated and registers will be affected differently y D ao One or more bits in INTCON and or PIR1 will be affected to cause wake up When the wake up is due to an interrupt and the GIE bit is set the PC is loaded with the interrupt vector 0004h See Table 14 5 for Reset value for specific condition If Reset was due to brown out then bit 0 0 All other Resets will cause bit 0 u Accessible only when SSPM lt 3 0 gt 1001 DS41262A page 180 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 TABLE 14 4 INITIALIZATION CONDITION FOR REGISTER CONTINUED MCLR Reset Kee Register Address Power on Reset MARIA sein a Wake up from Sleep through WDT Time out TRISB 86h 186h 1111 1111 uuuu TRISC 87h 187h 1111 1111 1111 1111 uuuu uuuu PIE1 8Ch 000 0000 000 0000 uuu uuuu PIE2 8Dh 0000 0000 uuuu uuuu PCON 8Eh 01 qq ou uult 5 uu uu OSCCON 8Fh 110 g000 110 x000 uuu uuuu OSCTUNE 90h 0 0000 u uuuu u uuuu PR2 92h 1111 1111 1111 1111 1111 1111 SSPADD 93h 0000 0000 1111 1111 uuuu uuuu SSPMSK 93h 1111 1111 uuuu uuuu SSPSTAT 94h 0000 0000 1111 1111 uuuu uuuu WPUA 95h 11 111 11 111 uuuu uuuu IOCA 96h 00 0000 00 0000 uu uuuu WDTCO
326. s changed the maximum delay of the internal voltage reference must be considered when using the comparator outputs Otherwise the maximum delay of the comparators should be used Table 17 8 While the comparator is enabled during Sleep an interrupt will wake up the device If the GIE bit INTCON lt 7 gt is set the device will jump to the interrupt vector 0004h and if clear continues execution with the next instruction If the device wakes up from Sleep the contents of the CMTCONO CM2CONO and VRCON registers are not affected 8 6 Operation During Sleep 8 7 Effects of a Reset A device Reset forces the CM1CONO CM2CONO and VRCON registers to their Reset states This forces the comparator module to be in the Comparator Reset mode CMxCONO lt 7 gt 0 and the voltage reference to its OFF state Thus all potential inputs are analog The comparators and voltage reference if enabled before entering Sleep mode remain active during Sleep This results in higher Sleep currents than shown in the power down specifications The additional current consumed by the comparator and the voltage reference is shown separately in the specifications To minimize TABLE 8 3 REGISTERS ASSOCIATED WITH COMPARATOR MODULE i R d d i 3 F Value on value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR E other esets 05h 105h PORTA gt RAS RA4 RAB RA2 RAI
327. s not used to detect DC address match bit 0 MSK lt 0 gt Mask bit for DC Slave Mode 10 bit Address I2C Slave Mode 10 bit Address SSPM lt 3 0 gt 0111 1 The received address bit O is compared to SSPADD lt 0 gt to detect DC address match o The received address bit 0 is not used to detect DC address match Note 1 When SSPCON bits SSPM lt 3 0 gt 1001 any reads or writes to the SSPADD SFR address are accessed through the SSPMSK register 2 In all other SSP modes this bit has no effect Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown 13 12 4 HALT ON ADDRESS DETECT In some applications it is necessary to acknowledge multiple addresses or blocks of addresses The Halt on Address Detect feature allows software to check the address and perform validation Address Detect is enabled when the ADDEN bit of SSPCON1 register is set to 1 The SSPIF flag and the CLKSTR bit are both set after the A1 last bit of address is clocked into the SSPSR and loaded into the SSPBUF but before the address comparator result is read or the ACK pulse is generated This allows the software to read the SSPBUF and validate the received address If the address is determined to be valid the software will copy the SSPBUF into SSPADD thus setting the result of the comparator to true The CLKSTR is then cleared 0 wri
328. s set 0 Bit is cleared x Bit is unknown REGISTER 10 2 EEADR EEPROM DATA REGISTER ADDRESS 10Dh R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 EEDAR7 EEDAR6 EEDAR5 EEDAR4 EEDAR3 EEDAR2 EEDAR1 EEDARO bit 7 bit 0 bit 7 0 EEDARn Byte value to Write to or Read from data EEPROM bits Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown REGISTER 10 3 EEDATH EEPROM DATA HIGH BYTE REGISTER ADDRESS 10Eh U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 EEDATHS EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATHO bit 7 bit 0 bit 5 0 EEDATH lt 5 0 gt Byte value to Write to or Read from data EEPROM bits or to Read from program memory Note 1 PIC16F685 PIC16F689 PIC16F690 only Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown REGISTER 10 4 EEADRH EEPROM ADDRESS HIGH BYTE REGISTER ADDRESS 10Fh U 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 EEADRH3 EEADRH2 EEADRH1 EEADRHO bit 7 bit 0 bit 3 0 EEADRH lt 3 0 gt Specifies one of 256 locations for EEPROM Read Write Operation bits or high bits for program memory reads Note 1 PIC16F685 PIC16F689 PIC 16F690 only Legend R
329. scription COMF Syntax Operands Operation Status Affected Description DECF Syntax Operands Operation Status Affected Description Clear Watchdog Timer label CLRWDT None 00h WDT 0 WDT prescaler 15TO 1 PD TO PD CLRWDT instruction resets the Watchdog Timer It also resets the prescaler of the WDT Status bits TO and PD are set Complement f label COMF fd 0 lt f lt 127 de 0 1 f destination Z The contents of register f are complemented If d is 0 the result is stored in W If d is 1 the result is stored back in register f Decrement f label DECF fd 0 lt f lt 127 de 0 1 f 1 destination Z Decrement register f If d is o the result is stored in the W register If d is 1 the result is stored back in register f DS41262A page 196 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 DECFSZ Decrement f Skip if 0 Syntax label DECFSZ fd Operands 0 lt f lt 127 de 0 1 Operation f 1 destination skip if result 0 Status Affected None Description The contents of register f are decremented If d is o the result is placed in the W register If d is 1 the result is placed back in register f If the result is 1 the next instruction is executed If the result is 0 then
330. scription Words Cycles Example NOP Syntax Operands Operation Status Affected Description Words Cycles Example Preliminary Move W to f label MOVWF 0 lt f lt 127 W f None Move data from W register to register f 4 4 MOVW OPTION F Before Instruction OPTION WwW After Instruction OPTION W No Operation label NOP None No operation None No operation NOP 2005 Microchip Technology Inc OxFF Ox4F Ox4F Ox4F PIC16F685 687 689 690 RETFIE Syntax Operands Operation Status Affected Description Words Cycles Example Return from Interrupt label RETFIE None TOS 5 PC 1 GIE None Return from Interrupt Stack is POPed and Top of Stack TOS is loaded in the PC Interrupts are enabled by setting Global Interrupt Enable bit GIE INTCON lt 7 gt This is a two cycle instruction 2 RETFIE After Interrupt PC TOS GIE 1 RETLW Syntax Operands Operation Status Affected Description Words Cycles Example TABLE RETURN Syntax Operands Operation Status Affected Description Return with literal in W label RETLW k 0 lt k lt 255 k gt W TOS PC None The W register is loaded with the eight bit literal k The program counter is loaded from the top of the stack the return address This is a two cycle instruction 4 2 CALL TABLE W contains table offset
331. se to the device as possible 0 1 uF and 0 01 uF values in parallel are recommended DS41262A page 220 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 se Mass me emos ans TABLE 17 3 CLKOUT AND I O TIMING REQUIREMENTS Standard Operating Conditions unless otherwise stated Operating Temperature 40 C lt TA lt 125 C Ga Sym Characteristic Min Typt Max Units Conditions 10 TosH2ckL OSC1T to CLOUTL 75 200 ns Note 1 11 TosH2ckH OSC1T to CLOUTT 75 200 ns Note 1 12 TCKR CLKOUT Rise Time 35 100 ns Note 1 13 TCKF CLKOUT Fall Time 35 100 ns Note 1 14 TCKL2IOV CLKOUT to Port Out Valid 20 ns Note 1 15 TioV2ckH Port In Valid before CLKOUTT Tosc 200 ns ns Note 1 16 TCKH2IO Pont In Hold after CLKOUTT 0 ns Note 1 17 TosH210V OSC1T Q1 cycle to Port Out Valid 50 150 ns 300 ns 18 TosH2i0l OSC1 Q2 cycle to Port Input 100 ns Invalid I O in hold time 19 TIOV20SH Port Input Valid to OSC1T 0 ns I O in setup time 20 TIOR Port Output Rise Time 10 40 ns 21 TIOF Port Output Fall Time 10 40 ns 22 TINP INT Pin High or Low Time 25 ns 23 TRBP PORTA change INT high or low TCY ns time These parameters are characterized but not tested Data in Typ column is at 5 0V 25 C unless otherwise stated Note
332. seenses SPI Mode Slave Mode with CKE 0 2005 Microchip Technology Inc Preliminary DS41262A page 251 PIC16F685 687 689 690 SPI Mode Slave Mode with CKE 1 162 SPI Slave Mode CKE 0 229 SPI Slave Mode CKE Il 229 Synchronous Reception Master Mode SREN 150 Synchronous Transmlssion 148 Synchronous Transmission Through TXEN 149 Time out Sequence Gase tia ee Aik be bh delet Aes ve keete A 179 CaSO NA AA KAA 179 UA AAA ee RR RR a Ra 179 Timer0 and Timer1 External Clock 224 Timer1 Incrementing Edge we 74 Two Speed Start up Wake up from Interrupt ssesseseeseeeseerrerrerrsrrerneree 190 Timing Parameter Symbology cee eee eeeeeeeeeees 218 Timing Requirements BC Bus Datani aa 232 12C Bus Start Stop Bits s eeeeeeeeeeeereeeeernererneeeee 231 SPM nrar niaan aa a N ec 230 TRISA Register Sinanu nean UA N A 47 TRISA Ne ET 48 TRISB MS SA EA UA AAA AAA 56 TISHA AI 57 TRISC SIE TRISC Register eegene Dana ps ee Two Speed Clock Start up Mode TXRE Gin eashainta ainn id adia Ania Wel aa a a TXSTA Register ia asi BRGH Bi AN aa a a e R U WA n a ee ep he MU Mha 156 Ultra Low Power W ke up 12 47 50 Ultra Low power Wake ump amana 8 10 Update Address bit UA 156 V Voltage Reference VR Specifications ra 226 Voltage Reference See Comparator Voltage Refere
333. sh or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MS 001 Drawing No C04 019 DS41262A page 240 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 20 Lead Plastic Small Outline SO Wide 300 mil Body SOIC B te A1 Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 20 20 Pitch p 050 1 27 Overall Height A 093 099 104 2 36 2 50 2 64 Molded Package Thickness A2 088 091 094 2 24 2 31 2 39 Standoff A1 004 008 012 0 10 0 20 0 30 Overall Width E 394 407 420 10 01 10 34 10 67 Molded Package Width E1 291 295 299 7 39 7 49 7 59 Overall Length D 496 504 512 12 60 12 80 13 00 Chamfer Distance h 010 020 029 0 25 0 50 0 74 Foot Length L 016 033 050 0 41 0 84 1 27 Foot Angle 0 4 8 0 4 8 Lead Thickness c 009 011 013 0 23 0 28 0 33 Lead Width B 014 017 020 0 36 0 42 0 51 Mold Draft Angle Top a 0 12 15 0 12 15 Mold Draft Angle Bottom B 0 12 15 0 12 15 Controlling Parameter Significant Characteristic Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MS 013 D
334. st before the end of the current PWM period the modulated outputs P1B and P1D are placed in their inactive state while the unmodulated outputs P1A and P1C are switched to drive in the opposite direction This occurs in a time interval of 4 Tosc Timer2 Prescale value before the next PWM period begins The Timer2 prescaler will be either 1 4 or 16 depending on the value of the T2CKPS lt 1 0 gt bits T2CON lt 1 0 gt During the interval from the switch of the unmodulated outputs to the beginning of the next period the modulated outputs P1B and P1D remain inactive This relationship is shown in Figure 11 10 Note that in the Full bridge Output mode the ECCP module does not provide any dead band delay In general since only one output is modulated at all times dead band delay is not required However there is a situation where a dead band delay might be required This situation occurs when both of the following conditions are true 1 The direction of the PWM output changes when the duty cycle of the output is at or near 100 2 The turn off time of the power switch including the power device and driver circuit is greater than the turn on time direction changes from forward to reverse at a near 100 duty cycle At time t1 the output PIA and P1D become inactive while output P1C becomes active In this example since the turn off time of the power devices is longer than the turn on time a shoot through current m
335. stscaler Comparator Go EO 1 1 to 1 16 T2CKPS lt 1 0 gt PR2 4 TOUTPS lt 3 0 gt TABLE 7 1 REGISTERS ASSOCIATED WITH TIMER2 Value on Addr Name Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR LOR all other Resets OBh 8Bh INTCON GIE PEIE TOIE INTE RABIE TOIF INTF RABIF 0000 000x 0000 000x 10Bh 18Bh OCh PIR1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 000 0000 000 0000 11h TMR2 Holding Register for the 8 bit TMR2 Register 0000 0000 0000 0000 12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPSO TMR2ON T2CKPS1 T2CKPSO 000 0000 000 0000 8Ch PIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMRIIE 000 0000 000 0000 92h PR2 Timer2 Module Period Register 1111 1111 1111 1111 Legend x unknown u unchanged unimplemented read as o Shaded cells are not used by the Timer2 module DS41262A page 78 Preliminary O 2005 Microchip Technology Inc PIC16F685 687 689 690 8 0 COMPARATOR MODULE A complete table showing the output state versus input conditions and the polarity bit is shown in Table 8 1 The comparator module has two separate voltage comparators Comparator C1 and Comparator C2 Each comparator offers the following list of features TABLE SI O L OUTPUT STATE VS INPUT CONDITIONS Control and configuration register Input Condition C1POL C1OUT Comparator output available externally e Programmable output polarity C1VN gt C1VP 0 0 Interrupt on change flags C1VN lt
336. t bits IRCF lt 2 0 gt OSCCON lt 6 4 gt select the frequency output of the internal oscillators One of eight frequencies can be selected via software 8 MHz e 4 MHz Default after Reset e 2 MHz e 1 MHz e 500 kHz e 250 kHz e 125 kHz e 31 kHz Note Following any Reset the IRCF bits are set to 110 and the frequency selection is set to 4 MHz The user can modify the IRCF bits to select a different frequency 3 4 5 HF AND LF INTOSC CLOCK SWITCH TIMING When switching between the LFINTOSC and the HFINTOSC the new oscillator may already be shut down to save power If this is the case there is a 10 us delay after the IRCF bits are modified before the frequency selection takes place The LTS HTS bits will reflect the current active status of the LFINTOSC and the HFINTOSC oscillators The timing of a frequency selection is as follows 1 IRCF bits are modified 2 Ifthe new clock is shut down a 10 us clock start up delay is started 3 Clock switch circuitry waits for a falling edge of the current clock 4 CLKOUT is held low and the clock switch circuitry waits for a rising edge in the new clock 5 CLKOUT is now connected with the new clock HTS LTS bits are updated as required 6 Clock switch is complete If the internal oscillator speed selected is between 8 MHz and 125 kHz there is no start up delay before the new frequency is selected This is because the old and the new frequencies ar
337. t condition 100 kHz mode 4000 ns After this period the first Hold time 400kHzmode 600 clock pulse is generated 925 Tsu sTO Stop condition 100 kHz mode 4700 ns Setup time 400 kHz mode 600 93 THD STO Stop condition 100 kHz mode 4000 ns Hold time 400 kHz mode 600 These parameters are characterized but not tested FIGURE 17 16 IC BUS DATA TIMING 103 Note Refer to Figure 17 2 for load conditions 2005 Microchip Technology Inc Preliminary DS41262A page 231 PIC16F685 687 689 690 TABLE 17 14 I C BUS DATA REQUIREMENTS Param No Symbol Characteristic Min Max Units Conditions 100 THIGH Clock high time 100 kHz mode 4 0 us Device must operate at a minimum of 1 5 MHz 400 kHz mode 0 6 us Device must operate at a minimum of 10 MHz SSP Module 1 5Tcy 101 TLOW Clock low time 100 kHz mode 4 7 us Device must operate ata minimum of 1 5 MHz 400 kH2 mode 1 3 us Device must operate at a minimum of 10 MHz SSP Module 1 5TcY 102 ITR SDA and SCL rise 100 kHz mode 1000 ns time 400 kHz mode 20 0 1CB 300 ns ICB is specified to be from 10 400 pF 1403 TF SDA and SCL fall 100 kHz mode 300 ns time 400 kHz mode 20 0 1CB 300 ns Cg is specified to be from 10 400 pF 90 TSU STA Start condition 10
338. ter Pin Diagram PIR1 Register ee le ER EE PORTA Additional Pin Functions seseseeseseeereerrerrerrrererne 47 2005 Microchip Technology Inc Preliminary DS41262A page 249 PIC16F685 687 689 690 Irterrupt on Change 49 Ultra Low Power Wake up 47 50 Weak Pull up Associated Registers 55 Pin Descriptions and Diagorams 51 Registers Sa Specification Ssnin r a ia 221 PORTA Ragistor arinaren ari EEE 47 PORTB Additional Pin Functions Weak Pull up WA Associated Registers w swwmmmemmnamimamamzmzza Interrupt on change ssesseserseriserrerresrrsrrerrrrrnerrerrners Pin Descriptions and Diagrams ROgISterS e cssserssraes eat iien a anssi N PORTB Register Associated Registers Associated registers P1A P1B P1C P1D See Enhanced Capture Compare EW ECG leede a 64 Register PRN RR PR RR RR RR RARE 64 Specifications 221 PORTC Register 64 Power Down Mode Geen 189 Power on Reset POR 176 Power up Timer PWRT 176 Specifications re 223 Precision Internal Oscillator Parameters 220 Prescaler Shared WDT Timero cee eee eeereeeeeeeseeeeaeeees 71 Switching Prescaler Assignment 71 PRO MATE II Universal Device Programmer
339. ter SWAPF W_TEMP F Swap W_TEMP SWAPF W TEMP W Swap W TEMP into W DS41262A page 186 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 145 Watchdog Timer WDT The new WDT is functionally compatible with previously designed WDT modules from other PICmicro microcontrollers Besides being backwards compatible the WDT module has added capabilities to control a 16 bit prescaler through software This allows the user to modify the prescale value for the WDT and TMRO independently Additionally the WDT time out value can be extended to 268 seconds because of the 16 bit prescaler The WDT is cleared under certain conditions which are described in Table 14 7 14 5 1 WDT OSCILLATOR The WDT derives its time base from the 31 kHz LFINTOSC oscillator and on any Reset the value of WDTCON is 0 1000 The resultant Reset value for WDTCON yields a nominal time base of 16 ms for the WDT The new prescaler that was added to the path between the LFINTOSC oscillator and the multiplexers is used to divide the LFINTOSC oscillator by values between 32 and 65536 As a result of the combination of prescalers a nominal range of 1 ms to 268s time out period for the WDT can be achieved Figure 14 8 shows a block diagram of the WDT circuitry and where the new prescaler was designed into the circuit 14 5 2 WDT CONTROL When the WDTE bit CONFIG lt 3 gt is set it enables the WDT and will continuousl
340. the I O pins with the proper signal levels or activates the PWM output s The CCP1M lt 1 0 gt bits CCP 1CON lt 1 0 gt allow the user to choose whether the PWM output signals are active high or active low for each pair of PWM output pins P1A P1C and P1B P1D The PWM output polarities must be selected before the PWM pins are configured as outputs Changing the polarity configuration while the PWM pins are configured as outputs is not recommended since it may result in damage to the application circuits The P1A P1B P1C and P1D output latches may not be in the proper states when the PWM module is initialized Enabling the PWM pins for output at the same time as the ECCP module may cause damage to the application circuit The ECCP module must be enabled in the proper Output mode and complete a full PWM cycle before configuring the PWM pins as outputs The completion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins PWM AUTO SHUTDOWN PRSEN 1 AUTO RESTART ENABLED at Shutdown Event ECCPASE bit PWM Period gt i d PWM Activity ES A se wi Start of Shutdown Shutdown PWM PWM Period Event Occurs Event Clears Resumes FIGURE 11 15 PWM AUTO SHUTDOWN PRSEN 0 AUTO RESTART DISABLED e PWM Perod Shutdown Event ECCPASE bit PWM Activity i LA A a Normal PWM
341. the comparator voltage Reference can be found in Section 17 0 Electrical Specifications 8 4 3 VP6 REFERENCE The VP6 reference has a constant voltage output of 0 6V nominal This reference can be enabled by setting the VP6EN bit to 1 VRCON lt 4 gt This reference is always enabled when the HFINTOSC oscillator is active 8 4 4 VP6 STABILIZATION PERIOD When the voltage reference module is enabled it will require some time for the reference and its amplifier circuits to stabilize The user program must include a small delay routine to allow the module to settle See the electrical specifications section for the minimum delay requirement DS41262A page 88 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 REGISTER 8 5 bit 7 bit 6 bit 5 bit 4 bit 3 0 VRCON VOLTAGE REFERENCE CONTROL REGISTER ADDRESS 118h R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VRO bit 7 bit 0 C1VREN Comparator 1 Voltage Reference Enable bit 1 CVREF circuit powered on and routed to C1VREF input of Comparator 1 0 0 6 Volt constant reference routed to C1 VREF input of Comparator 1 C2VREN Comparator 2 Voltage Reference Enable bit 1 CVREF circuit powered on and routed to C2VREF input of Comparator 2 0 0 6 Volt constant reference routed to C2VREF input of Comparator 2 VRR Comparator Voltage Reference CVREF Ran
342. tion 146 Auto Wake Up Bit WUE During Sleep 146 Brown out Reset BOR Brown out Reset Situations CEKOUT and O ges raca andas Clock Synchronization seseseeeeeeeereeeieerrnrreerrerrenne Enhanced Capture Compare PWM ECCP 225 EUSART Synchronous Receive Master Slave 227 EUSART Synchronous Transmission Master Slave 227 External Clock 2 ects sinew ag ee 219 Fail Safe Clock Monitor FSCM 44 Full Bridge PWM Output 120 Half Bridge PWM Output 119 BU seas ad passas 231 IC Bus Start Stop BiS iiseeeiieeeeeiererirereerreeeeereen 230 IC Reception 7 bit Address 166 IC Slave Mode Transmission 10 bit Address 170 IC Slave Mode with SEN 0 Reception 10 bit Address IC Transmission 7 bit Address INT Pin Interrupt sseseeeseeseserisrensrnrenereerraernerensrnsrneees PWM Auto shutdown Auto restart Disabled eee eee eee eee 128 Auto restart Enabled gt sw mmmmwa 128 PWM Direction Change 122 PWM Direction Change at Near 100 Duty Cycle 122 PWM Output Active High 0 0 00 eee eee ii PWM Output Active LOW eee eee eeee ener eeee Reset WDT OST and Power up Timer Send Break Character Sequence Slave Synchronization sseeseeseeseereerrrereerrerrerrrere SPI Master Mode CKE 1 SMP 1 SPI Mode Master Mode isseeseeeeeereeeeeeeesree
343. tion it may be possible for flag bits to become set before the SLEEP instruction completes To determine whether a SLEEP instruction executed test the PD bit If the PD bit is set the SLEEP instruction was executed as a NOP To ensure that the WDT is cleared a CLRWDT instruction should be executed before a SLEEP instruction 2005 Microchip Technology Inc Preliminary DS41262A page 189 PIC16F685 687 689 690 FIGURE 14 9 WAKE UP FROM SLEEP THROUGH INTERRUPT 01 02 03 o4 Q1 Q2 Q3 Q4 oi i 61 o2 oa as Q1 o2 Q3 o4 01 02 03 o4 0102103104 osci VV UV UY UV V Or PPP CLKOUT d i Tost d d d 7 INT pin 1 1 i 1 1 1 1 INTF flag i Di INTCON lt 1 gt is Interrupt Latency R GIE bit i INTCON lt 7 gt i Processor in l i Sleep 1 1 1 4 Instruction Flow X oooh X 0005h PC Y PC __PC t y PC 2 X PC 2 PC 2 Instruction f Inst PC Sleep Inst PC 1 Inst PC 2 Inst 0004h Inst 0005h Instruction Inst PC 1 Sleep Inst PC 1 Dummy Cycle Dummy Cycle Inst 0004h Note 1 XT HS or LP Oscillator mode assumed 2 TosT 1024 Tosc drawing not to scale This delay does not apply to EC and RC Oscillator modes 3 GIE 1 assumed In this case after wake up the processor jumps to 0004h If GIE 0 execution will continue in line 4 CLKOUT is not available in XT HS LP or EC Oscillator
344. tors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip s customer notification service helps keep customers current on Microchip products Subscribers will receive e mail notification whenever there are changes updates revisions or errata related to a specified product family or development tool of interest To register access the Microchip web site at www microchip com click on Customer Change Notification and follow the registration instructions CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels e Distributor or Representative Local Sales Office Field Application Engineer FAE Technical Support Development Systems Information Line Customers should contact their distributor representative or field application engineer FAE for support Local sales offices are also available to help customers A listing of sales offices and locations is included in the back of this document Technical support is available through the web site at http support microchip com In addition there is a Development Systems Information Line which lists the latest versions of Microchip s development systems software products This line also provides information on how customers can receive currently available upgrade kits The Development Systems Information Line numbers are 1 800 755 2345 United States and most of Canada 1 480 792 7302 Other Inte
345. tten the SSP engine is allowed to continue Since the address compare is now true an ACK pulse will be generated back to the master If the software decides that the address is not to be acknowledged the SSPADD is written with any value not equal to SSPBUF This will set the compare to false and an ACK will be suppressed when CLKSTR is cleared 2005 Microchip Technology Inc Preliminary DS41262A page 167 PIC16F685 687 689 690 IC SLAVE MODE TIMING RECEPTION 10 BIT ADDRESS FIGURE 13 9 ques JOU S MOV II INS S 4NGdSS esneseq 19S SI AOdSS j 0 NIS USUM D 0 J9Sa4 JOU S90P JO ANO palepdn aq 0 Spoo AAVASS WUL Bunesipu jas S YN ssaippe Jo elAg SSSJPpe Jo 9149 moj UUM pajepdn sq Ubiy ulim pojepdn si qqvdSS pelepdn si qqvdSs Uu 0 spasu GAVSS eu yeu u ym asempsey Aq Daat 3 asempiey q poJesjo a fm Buileoipu jes S YN lt gt IVISASS vn Deu 4g 129 9 0 Heen Jo slualuo9 UJIM ANadss Jo peas Awwng a VORMS INGdSS lt 9 gt NOOdSS AOdSS Jesugn s euiw1 taa Jojseu sng 3 d JeMmYosS ul palea o q aJeMYOS ul pasea o t SJEMYOS UI poses 9 JEMYOS U pelea HOS u p D q lt 0 gt 1VLSdSS 49 lt g gt LHId dldSs Weed ed yew ewe ey Peewee eww ewe ey S Ae _foaXra zaXea ra saXsa za lt as MOV alg EISC 2 94 MOV oa raXza ea ra sa sa za 7 L LU Le ev ev ov lol zv
346. unstable oscillator operation and or higher than expected current consumption All devices are tested to operate at min values with an external clock applied to OSC1 pin When an external clock input is used the max cycle time limit is DC no clock for all devices 2005 Microchip Technology Inc Preliminary DS41262A page 219 PIC16F685 687 689 690 TABLE 17 2 PRECISION INTERNAL OSCILLATOR PARAMETERS Standard Operating Conditions unless otherwise stated Operating Temperature 40 C lt TA lt 125 C Gert Sym Characteristic Sin Min Typt Max Units Conditions F10 Fosc Internal Calibrated 1 8 00 TBD MHz VDD and Temperature TBD INTOSC Frequency 2 800 TBD MHz 2 5V lt VpD lt 5 5V 0 C lt TA lt 85 C 5 8 00 TBD MHz 2 0V lt VDD lt 5 5V 40 C lt TA lt 85 C Ind 40 C lt TA lt 125 C Ext F14 TioscsT Oscillator Wake up from TBD TBD us VDD 2 0V 40 C to 85 C Sleep Start up Time TBD TBD us Vpp 3 0V 40 C to 85 C TBD TBD HS VDD 5 0V 40 C to 85 C Legend TBD To Be Determined These parameters are characterized but not tested Data in Typ column is at 5 0V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 To ensure these oscillator frequency tolerances VDD and Vss must be capacitively decoupled as clo
347. ure on board LIN transceivers A PIC16F874 Flash microcontroller serves as the master All three micro controllers are programmed with firmware to provide LIN bus communication 16 23 PICkit 1 Flash Starter Kit A complete development system in a box the PICkit Flash Starter Kit includes a convenient multi section board for programming evaluation and development of 8 14 pin Flash PIC microcontrollers Powered via USB the board operates under a simple Windows GUI The PICkit 1 Starter Kit includes the User s Guide on CD ROM PICkit 1 tutorial software and code for various applications Also included are MPLAB IDE Integrated Development Environment software software and hardware Tips n Tricks for 8 pin Flash PIC Microcontrollers Handbook and a USB interface cable Supports all current 8 14 pin Flash PIC microcontrollers as well as many future planned devices 16 24 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers This board provides the basis for future USB products 16 25 Evaluation and Programming Tools In addition to the PICDEM series of circuits Microchip has a line of evaluation kits and demonstration software for these products e KEELOQ evaluation and programming tools for Microchip s HCS Secure Data Products e CAN developers kit for automotive network applications Analog d
348. ured from external oscillators quartz crystal resonators ceramic resonators and Resistor Capacitor RC circuits In addition the system clock source can be configured from one of two internal oscillators with a choice of speeds selectable via software Additional clock features include Overview Selectable system clock source between external or internal via software Two Speed Clock Start up mode which minimizes latency between external oscillator start up and code execution Fail Safe Clock Monitor FSCM designed to detect a failure of the external clock source LP XT HS EC or RC modes and switch to the internal oscillator FIGURE 3 1 The PIC16F685 687 689 690 can be configured in one of eight clock modes 1 EC External clock with I O on RA4 2 LP 32 kHz low power Crystal mode 3 XT Medium gain Crystal or Ceramic Resonator Oscillator mode HS High gain Crystal or Ceramic Resonator mode 5 RC External Resistor Capacitor RC with Fosc 4 output on RA4 6 RCIO External Resistor Capacitor with I O on RA4 7 INTOSC Internal oscillator with Fosc 4 output on RA4 and I O on RAS 8 INTOSCIO Internal oscillator with I O on RA4 and RAS Clock Source modes are configured by the FOSC lt 2 0 gt bits in the Configuration Word register see Section 14 0 Special Features of the CPU The internal clock can be generated from two internal oscillators The HFINTOSC is a hig
349. ut ST Schmitt Trigger input with CMOS levels HV High Voltage XTAL Crystal 2005 Microchip Technology Inc Preliminary DS41262A page 9 PIC16F685 687 689 690 TABLE 1 2 PINOUT DESCRIPTION PIC16F687 PIC16F689 Name Function o Es ex Description RAO ANO C1IN ICSPDAT RAO TTL General purpose I O Individually controlled interrupt on ULPWU change Individually enabled pull up ANO AN A D Channel 0 input C1IN AN Comparator 1 positive input ICSPDAT TTL CMOS ICSP Data I O ULPWU AN Ultra Low Power Wake up input RA1 AN1 C12IN VREF ICSPCLK HAT TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up AN1 AN A D Channel 1 input C12IN AN Comparator 1 or 2 negative input VREF AN External Voltage Reference for A D ICSPCLK ST ICSPTM clock RA2 AN2 TOCKI INT C1OUT RA2 ST CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up AN2 AN A D Channel 2 input TOCKI ST Timer0 clock input INT ST External Interrupt C10OUT CMOS Comparator 1 output RA3 MCLR VPP RA3 TTL General purpose input Individually controlled interrupt on change MCLR ST Master Clear with internal pull up VPP HV Ge Programming voltage RA4 AN3 T1G OSC2 CLKOUT RA4 TTL CMOS General purpose
350. uts will read o 4 4 Additional PORTB Pin Functions PORTB pins RB lt 7 4 gt on the PIC16F685 687 689 690 have an interrupt on change option and a weak pull up option The following three sections describe these PORTB pin functions 4 4 1 WEAK PULL UPS Each of the PORTB pins has an individually configurable internal weak pull up Control bits WPUB lt 7 4 gt enable or disable each pull up Refer to Register 4 7 Each weak pull up is automatically turned off when the port pin is configured as an output The pull ups are disabled on a Power on Reset by the RABPU bit OPTION_REG lt 7 gt 4 4 2 INTERRUPT ON CHANGE Four of the PORTB pins are individually configurable as an interrupt on change pin Control bits IOCB lt 7 4 gt enable or disable the interrupt function for each pin Refer to Register 4 8 The interrupt on change feature is disabled on a Power on Reset For enabled interrupt on change pins the values are compared with the old value latched on the last read of PORTB The mismatch outputs of the last read are OR d together to set the PORTB Change Interrupt flag bit RABIF in the INTCON register Register 2 3 This interrupt can wake the device from Sleep The user in the Interrupt Service Routine clears the interrupt by a Any read or write of PORTB This will end the mismatch condition b Clear the flag bit RABIF A mismatch condition will continue to set flag bit RABIF Reading or writing
351. value W now has table value ADDWF PC W offset RETLW k1 Begin table RETLWk2 RETLW kn End of table Before Instruction W 0x07 After Instruction W value of k8 Return from Subroutine label RETURN None TOS PC None Return from subroutine The stack is POPed and the top of the stack TOS is loaded into the program counter This is a two cycle instruction 2005 Microchip Technology Inc Preliminary DS41262A page 199 PIC16F685 687 689 690 RLF Syntax Operands Operation Status Affected Description Words Cycles Example RRF Syntax Operands Operation Status Affected Description Rotate Left f through Carry label RLF fd 0 lt f lt 127 de 0 1 See description below C The contents of register f are rotated one bit to the left through the Carry flag If d is 0 the result is placed in the W register If d is 1 the result is stored back in register f pee Registerf pe 1 1 RLF REG1 0 Before Instruction REG1 a 1110 0110 Ei 0 After Instruction REG1 1110 0110 wW 1100 1100 ei ya Rotate Right f through Carry label RRF fd 0 lt f lt 127 de 0 1 See description below C The contents of register f are rotated one bit to the right through the Carry flag If d is 0 the result is placed in the W register If d is 1 the result is pla
352. vdSs Uu 0 spasu GdVdSs eu eu u ym asempsey Aq Daat F asempiey q poJesjo 7 fm Bunesipu jes S YN lt 1 gt IVISdSS vn Bel Ag 12919 Oo tHsdass Jo slualuo9 UJIM ANadss 40 peas Awwng A E uSumsianadss lt 9 gt NOOdSS AOdSS Jesugn Soyeuse Jojseu sng Sa F Jemyos ul paseaj E aJeEMYOS UI paseaj JJEMIJOS u peses o JEMYOS UI posea MYOS UI p 19 q hu lt 0 gt LVLSdSS 49 t lt g gt LHld www PEN Wee We wu wee Perey eye Tel viele id el S os dldSs IV foaftafzajeayrajsayoajra Voa Ya Yaa Teo fale foot za 7 Joy re ev Lef oe oeh el To Ve ie orl lt as NOV a1 g q anla0ey NOV AOV AOV Mag eq awa SSeJppy jo 91 g pu096S anla0ey o my SSePpy Jo 91 g 15114 9419094 opd uaye eoeld usye sey GdvdSs Jo eyepdn HUN MO pleu S OO sey GdVWdSS jo ajepdn UN MO PISY si 49019 2005 Microchip Technology Inc iminary Prel DS41262A page 170 PIC16F685 687 689 690 13 13 Master Mode Master mode of operation is supported in firmware using interrupt generation on the detection of the Start and Stop conditions The Stop P and Start S bits are cleared from a Reset or when the SSP module is disabled The Stop P and Start S bits will toggle based on the Start and Stop conditions Control of the DC bus may be taken when the P bit is set or the bus is idle and both the S and P bits are c
353. ver to the next line thus limiting the number of available characters for customer specific information 2005 Microchip Technology Inc Preliminary DS41262A page 239 PIC16F685 687 689 690 19 2 Package Details The following sections give the technical details of the packages 20 Lead Plastic Dual In line P 300 mil Body PDIP E1 d a E d HE nn ES On a fe E as A D A2 al Al i B B1 Ha eB B p Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 20 20 Pitch p 100 2 54 Top to Seating Plane A 140 155 170 3 56 3 94 4 32 Molded Package Thickness A2 115 130 145 2 92 3 30 3 68 Base to Seating Plane Al 015 0 38 Shoulder to Shoulder Width E 295 310 2325 7 49 7 87 8 26 Molded Package Width E1 240 250 260 6 10 6 35 6 60 Overall Length D 1 025 1 033 1 040 26 04 26 24 26 42 Tip to Seating Plane L 120 130 140 3 05 3 30 3 56 Lead Thickness c 008 012 015 0 20 0 29 0 38 Upper Lead Width B1 055 060 065 1 40 1 52 1 65 Lower Lead Width B 014 018 022 0 36 0 46 0 56 Overall Row Spacing eB 310 370 430 7 87 9 40 10 92 Mold Draft Angle Top a 5 10 15 5 10 15 Mold Draft Angle Bottom B 5 10 15 5 10 15 Controlling Parameter Significant Characteristic Notes Dimensions D and E1 do not include mold flash or protrusions Mold fla
354. vidual interrupts to be recognized Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown 2005 Microchip Technology Inc Preliminary DS41262A page 49 PIC16F685 687 689 690 4 2 3 ULTRA LOW POWER WAKE UP The Ultra Low Power Wake up ULPWU on RAO allows a slow falling voltage to generate an interrupt on change on RAO without excess current consumption The mode is selected by setting the ULPWUE bit PCON lt 5 gt This enables a small current sink which can be used to discharge a capacitor on RAO To use this feature the RA0O ANO C1IN ICSPDAT ULPWU pin is configured to output 1 to charge the capacitor interrupt on change for RAO is enabled and RAO is configured as an input The ULPWUE bit is set to begin the discharge and a SLEEP instruction is per formed When the voltage on RAO drops below VIL an interrupt will be generated which will cause the device to wake up Depending on the state of the GIE bit INTCON lt 7 gt the device will either jump to the interrupt vector 0004h or execute the next instruction when the interrupt event occurs See Section 4 2 2 Interrupt on change and Section 14 3 3 PORTA PORTB Interrupt for more information This feature provides a low power technique for periodically waking up the device from Sleep The time out is dependent on the discharge time o
355. wv v v DS41262A page 246 Preliminary 2005 Microchip Technology Inc PIC16F685 687 689 690 A Na AA KA E 93 Acquisition Requirements eseesseeeseereerrerreerrerene 100 Analog Port Pins Associated regisierg 103 Block Diagram isnin 93 Calculating Acguisition Time ae Channel Selection lt lt lt swasmwa mwanana nwanzaamaanaa 94 Configuration and Operation 94 Configuring Configuring Interrupt ssseseesssessereerreeresrrerrrerrerrnrrnere 99 Conversion Clock Effects of a Reset te Internal Sampling Switch Rss Impedance 100 Operation During Sleep A 102 Output Format Reference Voltage VE 94 Source Impedance cesses eeeeeteeeneeees Special Event Trigger Specifications ded dad eai Starting a Conversion Using the CCP Trigger Absolute Maximum Ratings AC Characteristics Industrial and Extended A 219 Load Conditions 218 ACK pulse 164 ADCONO Register naimani wawi 97 ADCONI Hegtster 98 Analog to Digital Converter See A D ANSEL Register i cvs covcesetscecsveevesrvessteseocssceveav srcessacostceseeey 96 ANSELH Register ssscssccceseesscsserecssessseseseesesessenesesees 96 Assembler MPASM Aesembler 203 Auto Wake Up on RX Pin Falling Edge 146 B Analog Input Model o Capture Mode Operation 114 Comparator lawa Baka aaa
356. x A Data Sheet Revision HISIO Y s ccccccccecosssesseteseccssevcctsvsieesasetssecevesevsrsoeecoccteceverssavenies seccesedesbendatyncaeedecodasbesdatenceesbaavieveveoass Appendix B Migrating from other PICmicro8 Devices erre nanunua numaniaawanuaanwanumaniaama nza namanu nazani 245 The Microchip Wep RE Customer Change Notification Service Customer SUPPO Tineia AU AA NEEE EE E DE EAA NE Ka BAA EE EE Product Identification System assess ans ses ENEE dee aaa Usa nara o ENEE SEENEN ENEE Dali cas TO OUR VALUED CUSTOMERS Itis our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products To this end we will continue to improve our publications to better suit your needs Our publications will be refined and enhanced as new volumes and updates are introduced lf you have any questions or comments regarding this publication please contact the Marketing Communications Department via E mail at docerrors microchip com or fax the Reader Response Form in the back of this data sheet to 480 792 4150 We wel come your feedback Most Current Data Sheet To obtain the most up to date version of this data sheet please register at our Worldwide Web site at http Awww microchip com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page The last character of the literature num
357. y controlled interrupt on change Individually enabled pull up SCK ST CMOS SPI clock SCL ST OD CTM clock RB7 TX CK RB7 TTL CMOS General purpose I O Individually controlled interrupt on change Individually enabled pull up TX CMOS EUSART asynchronous output CK ST CMOS EUSART synchronous clock RC0 AN4 C2IN RC0 ST CMOS General purpose I O AN4 AN A D Channel 4 input C2IN AN Comparator 2 positive input RC1 AN5 C12IN RC1 ST CMOS General purpose 1 0 AN5 AN A D Channel 5 input C12IN AN Comparator 1 or 2 negative input RC2 AN6 RC2 ST CMOS General purpose 1 0 AN6 AN A D Channel 6 input RC3 AN7 RC3 ST CMOS General purpose 1 0 AN7 AN A D Channel 7 input RC4 C2OUT RC4 ST CMOS General purpose 1 0 C20UT CMOS Comparator 2 output RC5 CCP1 RC5 ST CMOS General purpose 1 0 CCP1 ST CMOS Capture Compare input RC6 AN8 SS RC6 ST CMOS General purpose I O AN8 AN A D Channel 8 input ss ST Slave Select input RC7 AN9 SDO RC7 ST CMOS General purpose I O AN9 AN A D Channel 9 input SDO CMOS SPI data output Vss Vss Power Ground reference VDD VDD Power Positive supply Legend AN Analog input or output CMOS CMOS compatible input or output OD Open Drain TTL TTL compatible input ST Schmitt Trigger input with CMOS levels HV High Voltage XTAL Crystal 2005 Microchip Technology Inc Preliminary DS41262A page 11 PIC16F685 687 689 690
358. y run When the bit is clear the WDT is disabled but can be controlled through software in program memory and then SWDTEN bit WDTCON lt 0 gt has no effect If WDTE is clear the SWDTEN bit can be used to enable and disable the WDT through software in program memory The PSA lt 3 gt and PS lt 2 0 gt bits in the OPTION register Register 2 2 have the same function as the WDT modules previously designed for PlCmicro microcontrollers See Section 5 0 Timer0 Module for more information about the OPTION register Note When the Oscillator Start up Timer OST is invoked the WDT is held in Reset because the WDT Ripple Counter is used by the OST to perform the oscillator delay count When the OST count has expired the WDT will begin counting if enabled FIGURE 14 8 WATCHDOG TIMER BLOCK DIAGRAM From TMRO Clock Source Prescalert 16 bit WDT Prescaler fps ai Khe WDTPS lt 3 0 gt e ToTMRO LFINTOSC Clock DD SWDTEN from WDTCON WDTE from the Configuration Word Register Note 1 This is the shared Timer0 WDT prescaler See Section 5 4 Prescaler for more information WDT Time out TABLE 14 7 WDT STATUS Conditions WDT WDTE 0 Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep System Clock T1OSC EXTRC INTOSC EXTCLK Exit Sleep System Clock XT HS LP Cleared until the end of OST
359. z 2 0V typical lt 1 mA O 4 MHz 5 5V typical e Watchdog Timer Current lt 1 uA O 2 0V typical Peripheral Features e 17 I O pins and 1 input only pin High current source sink for direct LED drive Interrupt on pin change Individually programmable weak pull ups Ultra Low Power Wake up ULPWU e Analog comparator module with Two analog comparators Programmable on chip voltage reference CVREF module of VDD Comparator inputs and outputs externally accessible SR Latch mode Timer 1 Gate Sync Latch A D Converter 10 bit resolution and 12 channels e Timer0 8 bit timer counter with 8 bit programmable prescaler Enhanced Timeri 16 bit timer counter with prescaler External Gate Input mode Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator if INTOSC mode selected Timer2 8 bit timer counter with 8 bit period register prescaler and postscaler Enhanced Capture Compare PWM module 16 bit Capture max resolution 12 5 ns Compare max resolution 200 ns 10 bit PWM with 1 2 or 4 output channels programmable dead time max frequency 20 kHz PWM output steering control Synchronous Serial Port SSP SPITM mode Master and Slave I2CTM Master Slave modes I2CTM address mask In Circuit Serial Programming ICSP via two pins 2005 Microchip Technology Inc Preliminary DS41262A page 1 PIC16F685 687 689 690

MICROCHIP PIC16F685/687/689/690 Data Sheet Manual

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