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TEXAS INSTRUMENTS - TPS54319 handbook

1. lt 3 3 V falling x 50 25 0 25 50 75 100 125 150 50 25 0 25 50 75 100 125 150 T Junction Temperature C Figure 9 EN PIN CURRENT vs TEMPERATURE T Junction Temperature C Figure 10 EN PIN CURRENT vs TEMPERATURE T Junction Temperature C Figure 13 Submit Documentation Feedback Product Folder Link s TPS54319 M lt BV L Ven Threshold 50 mV Metis 1 o0 my lt t o 5 o a ul 50 25 0 25 50 75 100 125 150 50 25 0 25 50 75 100 125 150 T Junction Temperature C T Junction Temperature C Figure 11 Figure 12 CHARGE CURRENT vs TEMPERATURE INPUT VOLTAGE vs TEMPERATURE 1 4 3 1 6 2 9 1 8 2 8 gt UVLO Start Switching 2 o 2 7 o S 22 26 VS BV 2 MS UVLO Stop Switchin 24 E 25 ji gt 2 6 24 2 8 2 3 3 22 50 30 10 10 30 50 70 90 110 130 150 on DE 9 25 56 75 fog DE 7 T Junction Temperature C Figure 14 Copyright 2010 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com TPS54319 SLVSA83 JUNE 2010 TYPICAL CHARACTERISTICS CURVES continued SHUTDOWN SUPPLY CURRENT vs TEMPERATURE Shutdown Supply Current pA
2. 50 25 0 25 50 75 100 125 150 T Junction Temperature C Figure 15 VIN SUPPLY CURRENT vs JUNCTION TEMPERATURE 400 Vj 233V Ivin Supply Current yA wo a o 50 25 0 25 50 75 100 125 150 T Junction Temperature C Figure 17 PWRGD THRESHOLD vs TEMPERATURE Vsense Rising V 5 V Vsense Falling Vref PWRGD Threshold Vsense Rising Vsense Falling 50 25 0 25 50 75 100 125 150 T Junction Temperature C Figure 19 Copyright O 2010 Texas Instruments Incorporated Shutdown Supply Current LA A SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE 3 Tj 2 25 C 2 5 1 5 0 5 3 3 5 4 4 5 5 5 5 6 Vj Input Voltage V Figure 16 VIN SUPPLY CURRENT vs INPUT VOLTAGE Ivin Supply Current RDSON Static Drain Source On State Resistance Q 3 3 5 4 4 5 5 5 5 6 V Input Voltage V Figure 18 PWRGD ON RESISTANCE vs TEMPERATURE 50 25 0 25 50 75 100 125 150 T Junction Temperature C Figure 20 Submit Documentation Feedback Product Folder Link s TPS54319 9 TPS54319 eas SLVSA83 JUNE 2010 www ti com TYPICAL CHARACTERISTICS CURVES continued SS TR to VSENSE OFFSET vs TEMPERATURE 80 70 60 50 40
3. RDS Where Voutmin minimum achievable output voltage Ontimemin minimum controllable on time 65 ns typical 120 nsec no load Fsmax maximum switching frequency including tolerance Vinmax maximum input voltage loutmin minimum load current RDS minimum high side MOSFET on resistance 45 64 mQ RL series resistance of output inductor 34 There is also a maximum achievable output voltage which is limited by the minimum off time The maximum output voltage is given by Equation 35 Voutmax 1 Offtimemax x Fsmax x Vinmin loutmax x 2 x RDS loutmax x RL RDS Where Voutmax maximum achievable output voltage Offtimeman maximum off time 60 nsec typical Fsmax maximum switching frequency including tolerance Vinmin minimum input voltage loutmax maximum load current RDS maximum high side MOSFET on resistance 81 110 mQ RL series resistance of output inductor 35 Copyright 2010 Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Link s TPS54319 TPS54319 P I UMEN SLVSA83 JUNE 2010 www ti com COMPENSATION There are several industry techniques used to compensate DC DC regulators The method presented here is easy to calculate and yields high phase margins For most conditions the regulator has a phase margin between 60 and 90 degrees The method presented here ignores the effects of the slope compensation that is internal to the TPS54319 Since the s
4. capacitor must also be located close to the device The sensitive analog ground connections for the feedback Copyright 2010 Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Link s TPS54319 TPS54319 Peas SLVSA83 JUNE 2010 www ti com voltage divider compensation components slow start capacitor and frequency set resistor should be connected to a separate analog ground trace as shown The RT CLK pin is particularly sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace The additional external components can be placed approximately as shown It may be possible to obtain acceptable performance with alternate PCB layouts however this layout has been shown to produce good results and is meant as a guideline UVLO SET RESISTORS VIN N Q g BOOT AM BR CAPACITOR INPUT Sn 557 NM e Y Y Y EXPOSED OUTPUT POWERPAD FILTER AREA PH CAPACITOR S SLOW START D CAPACITOR 1 OOO FEEDBACK ANALOG OOO RESISTORS GROUND TRACE FREQUENCY SET RESISTOR COMPENSATION NETWORK TOPSIDE GROUND AREA O VIA to Ground Plane Figure 48 PCB Layout Example 28 Submit Documentation Feedback Copyright O 2010 Texas Instruments Incorporated Product Folder Link s TPS54319 PACKAGE OPTION ADDENDUM 14 TEXAS INSTRUMENTS www ti com 17 Jun 2010 PACKAGING INFORMATION Orderable Device St
5. 10 Output Current A Output Current A Figure 36 Figure 37 EFFICIENCY EFFICIENCY vs vs LOAD CURRENT LOAD CURRENT 1 MHz 3 3 VIN T 25 C 1 MHz 5 VIN TA 25 C 9 Efficience Efficience 0 0 5 1 1 5 2 2 5 3 r 0 5 1 1 5 2 2 5 3 lo Output Current A lo Output Current A Figure 38 Figure 39 TRANSIENT RESPONSE 1 5 A STEP POWER UP VOUT VIN Vout lt 100 mV div ac coupled imwe eT lout 1 A div 0 A to 1 5 A load step PWRGD 5 V div LOT TF T Gd Time 200 usec div Time 5 msec div Figure 40 Figure 41 Copyright O 2010 Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Link s TPS54319 TPS54319 ne SLVSA83 JUNE 2010 www ti com POWER UP VOUT EN OUTPUT RIPPLE 3A Vin 5 V div Vout 20 mV div ac coupled 3 M e eee e Vout 2 V div PH lt 2V div Pp EN 2V div rm em el 2 PWRGD 5 V div Time 5 msec div Time 500 nsec div Figure 42 Figure 43 INPUT RIPPLE 3 A CLOSED LOOP RESPONSE VIN 5 V 3 A Vin 100 mV div ac coupled PAVIA PH 2V div trp te diuuu Time 500 nsec div Gain dB Phase Degrees Frequency Hz Figure 44 Figure 45 LOAD REGULATION REGULATION VS vs LOAD CURRENT
6. 30 SS TR Vsense Offset mV 20 50 25 0 25 50 75 100 125 150 T Junction Temperature C Figure 21 OVERVIEW The TPS54319 is a 6 V 3 A synchronous step down buck converter with two integrated n channel MOSFETs To improve performance during line and load transients the device implements a constant frequency peak current mode control which reduces output capacitance and simplifies external frequency compensation design The wide switching frequency of 300 kHz to 2000 kHz allows for efficiency and size optimization when selecting the output filter components The switching frequency is adjusted using a resistor to ground on the RT CLK pin The device has an internal phase lock loop PLL on the RT CLK pin that is used to synchronize the power switch turn on to a falling edge of an external system clock The TPS54319 has a typical default start up voltage of 2 6 V The EN pin has an internal pull up current source that can be used to adjust the input voltage under voltage lockout UVLO with two external resistors In addition the pull up current provides a default condition when the EN pin is floating for the device to operate The total operating current for the TPS54319 is typically 360 uA when not switching and under no load When the device is disabled the supply current is less than 5 pA The integrated 45 mO MOSFETs allow for high efficiency power supply designs with continuous output curre
7. 98 normal 1 1 V SS TR discharge voltage Overload VSENSE 0 V 46 mV SS TR discharge current Overload VSENSE 0 V V SS TR 0 4 V 325 UA POWER GOOD PWRGD PIN VSENSE falling Fault 91 Vref VSENSE rising Good 93 Vref VSENSE threshold RE VSENSE rising Fault 107 96 Vref VSENSE falling Good 105 Vref Hysteresis VSENSE falling 2 Vref Output high leakage VSENSE VREF V PWRGD 5 5 V 2 nA On resistance 100 200 Q Output low I PWRGD 3 0 mA 0 3 0 6 V Minimum VIN for valid output V PWRGD lt 0 5 V at 100 pA 1 2 1 6 V 4 Submit Documentation Feedback Copyright 2010 Texas Instruments Incorporated Product Folder Link s TPS54319 1 TEXAS INSTRUMENTS www ti com TPS54319 SLVSA83 JUNE 2010 DEVICE INFORMATION PIN CONFIGURATION QFN16 RTE PACKAGE TOP VIEW VIN VIN PowerPAD 17 GND GND PIN FUNCTIONS PIN DESCRIPTION NAME NO AGND 5 Analog Ground should be electrically connected to GND close to the device BOOT 13 A bootstrap capacitor is required between BOOT and PH If the voltage on this capacitor is below the minimum required by the BOOT UVLO the output is forced to switch off until the capacitor is refreshed COMP 7 Error amplifier output and input to the output switch current comparator Connect frequency compensation components to this pin EN 15 Enable pin internal pull up current source Pull below 1 2 V to disable
8. Figure 26 Schematic for Ratio metric Start Up Figure 27 Ratio metric Startup with Vout1 Leading Sequence Vout2 Ratio metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 28 to the output of the power supply that needs to be tracked or another voltage reference source Using Equation 5 and Equation 6 the tracking resistors can be calculated to initiate the Vout2 slightly before after or at the same time as Vouti Equation 7 is the voltage difference between Vouti and Vout2 The AV variable is zero volts for simultaneous sequencing To minimize the effect of the inherent SS TR to VSENSE offset Vssoffset in the slow start circuit and the offset created by the pullup current source Iss and tracking resistors the Vssoffset and Iss are included as variables in the equations To design a ratio metric start up in which the Vout2 voltage is slightly greater than the Vouti voltage when Vout2 reaches regulation use a negative number in Equation 5 through Equation 7 for AV Equation 7 will result in a positive number for applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved Since the SS TR pin must be pulled below 40mV before starting after an EN UVLO or thermal shutdown fault careful selection of the tracking resistors is needed to ensure the device will restart after a fault Make sure the calculated R1 value from Equation 5 is greater than t
9. MOSFETs and 360uA typical supply current Using the enable pin shutdown supply current is reduced to 2 pA by entering a shutdown mode Under voltage lockout is internally set at 2 6 V but can be increased by programming the threshold with a resistor network on the enable pin The output voltage startup ramp is controlled by the slow start pin An open drain power good signal indicates the output is within 9396 to 10796 of its nominal voltage Frequency fold back and thermal shutdown protects the device during an over current condition The TPS54319 is supported in the SwitcherPro Software Tool at www ti com switcherpro For more SWIFT documentation see the Tl website at www ti com swift 100 3 3 Vin 1 8 Vout 1 8 Vout Efficiency 96 0 0 5 1 1 5 2 2 5 3 Output Current A L Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet SWIFT SwitcherPro are trademarks of Texas Instruments PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Copyright 2010 Texas Instruments Incorporated TPS54319 PI UMEN
10. SLVSA83 JUNE 2010 www ti com These devices have limited built in ESD protection The leads should be shorted together or the device placed in conductive foam hid during storage or handling to prevent electrostatic damage to the MOS gates ORDERING INFORMATION Ty PACKAGE PART NUMBER 40 C to 150 C 3 x 3mm QFN TPS54319RTE 1 For the most current package and ordering information see the Package Option Addendum at the end of this document or see the TI website at www ti com ABSOLUTE MAXIMUM RATINGS VALUE UNIT MIN MAX Input voltage VIN 0 3 7 EN 0 3 7 BOOT PH 7 VSENSE 0 3 3 V COMP 0 3 3 PWRGD 0 3 7 SS TR 0 3 3 RT CLK 0 3 6 Output voltage BOOT PH 7 PH 0 6 7 V PH 10 ns Transient 2 10 Source current EN 100 UA RT CLK 100 UA Sink current COMP 100 UA PWRGD 10 mA SS TR 100 UA Electrostatic discharge HBM QSS 009 105 JESD22 A1 14A 1 kV Electrostatic discharge CDM QSS 009 147 JESD22 C101B 01 500 V Temperature Tj 40 150 C Tstg 65 150 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ELECTRICAL SPECIFICATIONS is not implied Exposure to absolute maximum rated conditions for extended periods
11. Shutdown 165 C Hysteresis 15 C Copyright 2010 Texas Instruments Incorporated Product Folder Link s TPS54319 Submit Documentation Feedback 3 TPS54319 ies SLVSA83 JUNE 2010 www ti com ELECTRICAL CHARACTERISTICS continued T 40 C to 150 C VIN 2 95 to 6 V unless otherwise noted DESCRIPTION CONDITIONS MIN TYP MAX UNIT TIMING RESISTOR AND EXTERNAL CLOCK RT CLK PIN Switching frequency range using RT mode 300 2000 kHz Switching frequency Rt 400 kO 400 500 600 kHz Switching frequency range using CLK mode 300 2000 kHz Minimum CLK pulse width 75 ns RT CLK voltage R RT CLK 400kQ 0 5 V RT CLK high threshold 1 6 2 2 V RT CLK low threshold 0 4 0 6 V RT CLK falling edge to PH rising edge delay Measure at 500 kHz with RT resistor in series 90 ns PLL lock in time Measure at 500 kHz 14 US PH PH PIN Minimum On time Measured at 50 points on PH IOUT 3 A 65 Measured at 50 points on PH VIN 5 V 120 ns IOUT 0 A Minimum Off time Prior to skipping off pulses BOOT PH 2 95 V 60 ns IOUT 3 A Rise Time 2 5 Fall Time VIN 5V 3A lt V ns BOOT BOOT PIN BOOT Charge Resistance VIN 5 V 16 Q BOOT PH UVLO VIN 2 95 V 2 2 V SLOW START AND TRACKING SS TR PIN Charge Current V SS TR 0 4 V 2 2 uA SS TR to VSENSE matching V SS TR 0 4 V 35 mV SS TR to reference crossover
12. a high impedance clock input to the internal PLL If clocking edges stop the internal amplifier is re enabled and the mode returns to the frequency set by the resistor The square wave amplitude at this pin must transition lower than 0 6 V and higher than 1 6 V typically The synchronization frequency range is 300 kHz to 2000 kHz The rising edge of the PH is synchronized to the falling edge of RT CLK pin TPS54319 SYNC Clock 2 V div ADOPTION PH 2V div RT CLK Clock R T Source m Time 500 nsec div Figure 30 Synchronizing to a System Clock Figure 31 Plot of Synchronizing to System Clock POWER GOOD PWRGD PIN The PWRGD pin output is an open drain MOSFET The output is pulled low when the VSENSE voltage enters the fault condition by falling below 9196 or rising above 10796 of the nominal internal reference voltage There is a 296 hysteresis on the threshold voltage so when the VSENSE voltage rises to the good condition above 93 or falls below 105 of the internal voltage reference the PWRGD output MOSFET is turned off It is recommended to use a pull up resistor between the values of 1kO and 100kQ to a voltage source that is 6 V or less The PWRGD is in a valid state once the VIN input voltage is greater than 1 2 V OVERVOLTAGE TRANSIENT PROTECTION The TPS54319 incorporates an overvoltage transient protection OVTP circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload tr
13. deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such al
14. may affect device reliability 2 The human body model is a 100 pF capacitor discharged through a 1 5 kO resistor into each pin The machine model is a 200 pF capacitor discharged directly into each pin 2 Submit Documentation Feedback Copyright 2010 Texas Instruments Incorporated Product Folder Link s TPS54319 1 TEXAS INSTRUMENTS www ti com THERMAL INFORMATION TPS54319 SLVSA83 JUNE 2010 TPS54319 THERMAL METRIC UNITS RTE 16 PINS OJA Junction to ambient thermal resistance standard board 51 7 OJA Junction to ambient thermal resistance custom board 9 37 0 WoT Junction to top characterization parameter 0 8 VJB Junction to board characterization parameter 19 2 C W Jc top Junction to case top thermal resistance 69 3 JC bottom Junction to case bottom thermal resistance 6 2 0p Junction to board thermal resistance 22 1 For more information about traditional and new thermal metrics see the IC Package Thermal Metrics application report SPRA953 2 Power rating at a specific ambient temperature Ta should be determined with a junction temperature of 150 C This is the point where distortion starts to substantially increase See power dissipation estimate in application section of this data sheet for more information 3 Test boards conditions a 2 inches x 2 inches 4 layers thickness 0 062 inch b 2 oz copper traces located on the top of the PCB c
15. plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DLP Products www dlp com Communications and www ti com communications Telecom DSP dsp ti com Computers and www ti com computers Peripherals Clocks and Timers www ti com clocks Consumer Electronics www ti com consumer apps Interface interface ti com Energy www ti com energy Logic logic ti com Industrial www ti com industrial Power Mgmt power ti com Medical www ti com medical Microcontrollers microcontroller ti com Security www ti com security RFID www ti rf
16. the offset increases as the effective system reference transitions from the SS TR voltage to the internal voltage reference SEQUENCING Many of the common power supply sequencing methods can be implemented using the SS TR EN and PWRGD pins The sequential method can be implemented using an open drain or collector output of a power on reset pin of another device Figure 24 shows the sequential method The power good is coupled to the EN pin on the TPS54319 which enables the second power supply once the primary supply reaches regulation Ratio metric start up can be accomplished by connecting the SS TR pins together The regulator outputs ramp up and reach regulation at the same time When calculating the slow start time the pull up current source must be doubled in Equation 4 The ratio metric method is illustrated in Figure 26 TPS54319 L f eee r Ch1 20V L z0v M 1 0ms 5 a ra A Chi os TES Figure 24 Sequential Start Up Sequence Figure 25 Sequential Startup using EN and PWRGD Copyright O 2010 Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link s TPS54319 I TEXAS TPS54319 INSTRUMENTS SLVSA83 JUNE 2010 www ti com ers T T TPS54319 EN1 SS TR1 PWRGD1 TPS54319 EN2 Las du 4 L 1 4 1 TPS 1 SS TR2 Chi 20v cr 10 M 1 0ms 5 0MS s 200ns pt ha ov ra A Ch amp 680mV PWRGD2
17. to the amount of ripple current they can handle without failing or producing excess heat An output capacitor that can support the inductor ripple current must be specified Some capacitor data sheets specify the RMS Root Mean Square value of the maximum ripple current Equation 29 can be used to calculate the RMS ripple current the output capacitor needs to support For this application Equation 29 yields 333 mA Resr KG Iripple T Icorms Vout x Vinmax Vout J12 x Vinmax x L1 x fsw o5 INPUT CAPACITOR The TPS54319 requires a high quality ceramic type X5R or X7R input decoupling capacitor of at least 4 7 uF of effective capacitance and in some applications a bulk capacitance The effective capacitance includes any DC bias effects The voltage rating of the input capacitor must be greater than the maximum input voltage The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54319 The input ripple current can be calculated using Equation 30 The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature The output capacitor
18. 2 oz copper ground planes on the 2 internal layers and bottom layer d 4 thermal vias 10mil located under the device package ELECTRICAL CHARACTERISTICS T 40 C to 150 C VIN 2 95 to 6 V unless otherwise noted DESCRIPTION CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE VIN PIN Operating input voltage 2 95 6 V Internal under voltage lockout threshold 2 6 2 8 V Shutdown supply current EN 0 V 25 C 2 95 V lt VINSs6V 2 5 uA Quiescent Current lg VSENSE 0 9 V VIN 5 V 25 C RT 400 kQ 360 575 uA ENABLE AND UVLO EN PIN Enable threshold Rising 1 25 V Falling 1 18 Enable threshold 50 mV 4 6 Input current uA Enable threshold 50 mV 1 2 VOLTAGE REFERENCE VSENSE PIN Voltage Reference 2 95 V lt VIN x 6 V 0 C T lt 85 C 0 802 0 827 0 852 V MOSFET BOOT PH 5V 45 81 High side switch resistance mQ BOOT PH 2 95 V 64 110 Low side switch resistance ee a A mQ VIN 2 95 V 59 110 ERROR AMPLIFIER Input current 7 nA Error amplifier transconductance gm 2 uA lt I COMP lt 2 nA V COMP 1 V 245 umhos Error amplifier transconductance gm during 2 uA lt I COMP lt 2 uA V COMP 1 V 79 umhos slow start Vsense 0 4 V Error amplifier source sink V COMP 1 V 100 mV overdrive 20 uA 20 COMP to Iswitch gm 18 AN CURRENT LIMIT Current limit threshold 3V 4 2 6 6 A THERMAL SHUTDOWN Thermal
19. Float to enable Can be used to set the on off threshold adjust UVLO with two additional resistors GND 3 4 Power Ground This pin should be electrically connected directly to the power pad under the IC PH 10 11 The source of the internal high side power MOSFET and drain of the internal low side synchronous rectifier 12 MOSFET PowerPAD 17 GND pin should be connected to the exposed power pad for proper operation This power pad should be connected to any internal PCB ground plane using multiple vias for good thermal performance PWRGD 14 An open drain output asserts low if output voltage is low due to thermal shutdown overcurrent over under voltage or EN shut down RT CLK Resistor Timing or External Clock input pin SS TR Slow start and tracking An external capacitor connected to this pin sets the output voltage rise time This pin can also be used for tracking VIN 1 2 16 Input supply voltage 2 95 V to 6 V VSENSE 6 Inverting node of the transconductance gm error amplifier Copyright 2010 Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link s TPS54319 TPS54319 PI UMEN SLVSA83 JUNE 2010 www ti com FUNCTIONAL BLOCK DIAGRAM PWRGD EN VIN i i A Ow Shutdown E y Enable Comparator tye Enable Shutdown Threshold Voltage Reference Minimum Current Vv COMP Clamp Sense ERROR CD AMPLIFIER PWM VSENSE e 1 e Comparator BOOT SSITR Fee e Ea Logic and PWM Latch Shutdow
20. IA TEXAS INSTRUMENTS www ti com TPS54319 SLVSA83 JUNE 2010 2 95 V to 6 V Input 3 A Output 2 MHz Synchronous Step Down Switcher With Integrated FETs SWIFT Check for Samples TPS54319 FEATURES Two 45 mO typical MOSFETs for High Efficiency at 3 A Loads e 300kHz to 2MHz Switching Frequency 0 8V 3 0 Voltage Reference Over Temperature 0 C to 85 C e Synchronizes to External Clock Adjustable Slow Start Sequencing e UV and OV Power Good Output e 40 C to 150 C Operating Junction Temperature Range e Thermally Enhanced 3mm x 3mm 16 pin QFN Pin Compatible to TPS54318 APPLICATIONS Low Voltage High Density Power Systems Point of Load Regulation for Consumer Applications such as Set Top Boxes LCD Displays CPE Equipment SIMPLIFIED SCHEMATIC BOOT TPS54319 DESCRIPTION The TPS54319 device is a full featured 6 V 3 A synchronous step down current mode converter with two integrated MOSFETs The TPS54319 enables small designs by integrating the MOSFETs implementing current mode control to reduce external component count reducing inductor size by enabling up to 2 MHz switching frequency and minimizing the IC footprint with a small 3mm x 3mm thermally enhanced QFN package The TPS54319 provides accurate regulation for a variety of loads with an accurate 3 0 Voltage Reference VREF over temperature Efficiency is maximized through the integrated 45mO
21. INPUT VOLTAGE DA YF D 0 3 lout 2A 02 Output Voltage Deviation o Output Voltage Deviation 0 1 0 2 0 3 04 tt 0 0 5 1 15 2 25 3 3 3 5 4 4 5 5 5 5 6 Output Current A Input Voltage V Figure 46 Figure 47 26 Submit Documentation Feedback Copyright 2010 Texas Instruments Incorporated Product Folder Link s TPS54319 T ONNE TPS54319 www ti com SLVSA83 JUNE 2010 POWER DISSIPATION ESTIMATE The following formulas show how to estimate the IC power dissipation under continuous conduction mode CCM operation The power dissipation of the IC Ptot includes conduction loss Pcon dead time loss Pd switching loss Psw gate drive loss Pgd and supply current loss Pq Pcon lo x Ros on Temp Pd fy x lo x 0 7 x 40 x 10 Psw 1 2 x Vin x lo x faux 8 x 107 Pgd 2 x Vi x faux 2 x 10 Pq Vin x 360 x 107 Where lo is the output current A Hons on Temp is the on resistance of the high side MOSFET with given temperature Q Vi is the input voltage V fs is the switching frequency Hz So Ptot Pcon Pd Psw Pgd Pq For given TA TJ TA Rth x Ptot For given TJMAX 150 C TAmax TJ max Rth x Ptot Where Ptot is the total device power dissipation W TA is the ambient temperature C TJ is the junction temperature C Rth is the thermal resistance of the package C
22. KHz 100 I a 400 500 600 700 800 900 1000 RT Resistance kQ Figure 5 SWITCHING FREQUENCY vs VSENSE Vsense Falli bc a G Nominal Switching Frequency N 22 Vsense Rising 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 Vsense V Figure 7 Copyright O 2010 Texas Instruments Incorporated 0 858 0 848 o Oo GO e oo D 0 818 Vier Voltage Reference V 0 808 0 798 50 25 0 25 50 75 100 125 150 T Junction Temperature C Figure 4 SWITCHING FREQUENCY vs RT RESISTANCE HIGH FREQUENCY RANGE 1600 1300 fs Switching Frequency KHz a eo 80 100 120 140 160 180 200 RT Resistance kQ Figure 6 TRANSCONDUCTANCE vs TEMPERATURE N a o N o N o EA Transconductance pA V e cx EN en o 50 25 0 25 50 75 100 125 150 T Junction Temperature C Figure 8 Submit Documentation Feedback Product Folder Link s TPS54319 7 TPS54319 SLVSA83 JUNE 2010 EN Pin Current LA EA Transconductance LA V Iss tr Charge Current pA I TEXAS INSTRUMENTS www ti com TYPICAL CHARACTERISTICS CURVES continued TRANSCONDUCTANCE SLOW START vs JUNCTION TEMPERATURE EN PIN VOLTAGE vs TEMPERATURE Vj 3 3 V rising
23. Materials Page 2 MECHANICAL DATA RTE S PQFP N16 PLASTIC QUAD FLATPACK PIN 1 INDEX AREA TOP AND BOTTOM 0 20 REF H H H Ly SEATING PLANE mii 0 0 10 M 4205254 B 11 04 A All linear dimensions are in millimeters Dimensioning and tolerancing per ASME Y14 5M 1994 B This drawing is subject to change without notice C Quad Flatpack No leads QFN package configuration The package thermal pad must be soldered to the board for thermal and mechanical performance See the Product Data Sheet for details regarding the exposed thermal pad dimensions E Falls within JEDEC MO 220 3 TEXAS INSTRUMENTS www ti com THERMAL PAD MECHANICAL DATA RTE S PWQFN N16 PLASTIC QUAD FLATPACK NO LEAD THERMAL INFORMATION This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink The thermal pad must be soldered directly to the printed circuit board PCB After soldering the PCB can be used as a heatsink In addition through the use of thermal vias the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device or alternatively can be attached to a special heatsink structure designed into the PCB This design optimizes the heat transfer from the integrated circuit IC For information on the
24. Quad Flatpack No Lead QFN package and its advantages refer to Application Report QFN SON PCB Attachment Texas Instruments Literature No SLUA271 This document is available at www ti com The exposed thermal pad dimensions for this package are shown in the following illustration 1 4 J U U U Exposed Thermal Pad 16 amp C 5 1 7040 10 E2 lt en Y Tor C48 NANN 2 9 EM Bottom View NOTE All linear dimensions are in millimeters Exposed Thermal Pad Dimensions 4206446 3 F 07 10 A TEXAS INSTRUMENTS www ti com LAND PATTERN RTE S PWQFN N16 Example Board Layout Example Stencil Design Note E Note D I i i L i cue U R0 115 o l m M dem 0 230 y Q 4x0 7 21 5 HU 0 2 ii c erus ji RE 3 75 68 solder coverage on center pad Non Solder Mask Defined Pad Example Via Layout Design Via pattern may vary due to layout constraints Example Note D F Solder Mask Opening 5x60 3 17 Note F i Or 1 7 Q Pad Geometry Note C O CH 4209446 2 A 04 08 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Publication IPC 7351 is recommended for alternate designs D This package is designed to be so
25. Ro and capacitor Co model the open loop gain and frequency response of the amplifier The 1 mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements Plotting a c shows the small signal response of the frequency compensation Plotting a b shows the small signal response of the overall loop The dynamic loop response can be checked by replacing the R with a current source with the appropriate load step amplitude and step rate in a time domain analysis Power Stage 18 0 A V T 0 827 V VSENSE gm 245 A V R2 Figure 32 Small Signal Model for Loop Response SIMPLE SMALL SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL Figure 32 is a simple small signal model that can be used to understand how to design the frequency compensation The TPS54319 power stage can be approximated to a voltage controlled current source duty cycle modulator supplying current to the output capacitor and load resistor The control to output transfer function is shown in Equation 11 and consists of a dc gain one dominant pole and one ESR zero The quotient of the change in switch current and the change in COMP pin voltage node c in Figure 32 is the power stage transconductance The gm for the TPS54319 is 18 0 A V The low frequency gain of the power stage frequency response is the product of the transconductance and the load resistance as shown in Equation 12 As the load current increases and dec
26. The bandgap and scaling circuits produce 0 827 V at the non inverting input of the error amplifier ADJUSTING THE OUTPUT VOLTAGE The output voltage is set with a resistor divider from the output node to the VSENSE pin It is recommended to use divider resistors with 1 tolerance or better Start with a 100 KQ for the R1 resistor and use the Equation 1 to calculate R2 To improve efficiency at very light loads consider using larger value resistors If the values are too high the regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable 0 827 V R2 R1 x _ Vo 0 827 V 1 Copyright O 2010 Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link s TPS54319 TPS54319 PI UNS SLVSA83 JUNE 2010 www ti com TPS54319 Vo R1 VSENSE Figure 22 Voltage Divider Circuit ENABLE AND ADJUSTING UNDER VOLTAGE LOCKOUT The TPS54319 is disabled when the VIN pin voltage falls below 2 6 V If an application requires a higher under voltage lockout UVLO use the EN pin as shown in Figure 23 to adjust the input voltage UVLO by using two external resistors The EN pin has an internal pull up current source that provides the default condition of the TPS54319 operating when the EN pin floats Once the EN pin voltage exceeds 1 25 V an additional 3 4 uA of hysteresis is added When the EN pin is pulled below 1 18 V the 3 4 uA is removed This additional
27. W TJMAX is maximum junction temperature C TAMAX is maximum ambient temperature C There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace resistance that impact the overall efficiency of the regulator LAYOUT Layout is a critical portion of good power supply design There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance Care should be taken to minimize the loop area formed by the bypass capacitor connections and the VIN pins See Figure 48 for a PCB layout example The GND pins and AGND pin should be tied directly to the power pad under the IC The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC Additional vias can be used to connect the top side ground area to the internal planes near the input and output capacitors For operation at full rated load the top side ground area along with any additional internal ground planes must provide adequate heat dissipating area Locate the input bypass capacitor as close to the IC as possible The PH pin should be routed to the output inductor Since the PH connection is the switching node the output inductor should be located very close to the PH pins and the area of the PCB conductor minimized to prevent excessive capacitive coupling The boot
28. ack Copyright 2010 Texas Instruments Incorporated Product Folder Link s TPS54319 T ONNE TPS54319 www ti com SLVSA83 JUNE 2010 The design guidelines for TPS54319 loop compensation are as follows 1 The modulator pole fomod and the esr zero fz1 must be calculated using Equation 15 and Equation 16 Derating the output capacitor Cour may be needed if the output voltage is a high percentage of the capacitor rating Use the capacitor manufacturer information to derate the capacitor value Use Equation 17 and Equation 18 to estimate a starting point for the crossover frequency fc Equation 17 is the geometric mean of the modulator pole and the esr zero and Equation 18 is the mean of modulator pole and the switching frequency Use the lower value of Equation 17 or Equation 18 as the maximum crossover frequency fp mod loutmax 2n x Vout x Cout 15 1 fzmod 2n x Resr x Cout 16 fe 4 fp modx fz mod 17 fc fo moa I 2 18 2 R3 can be determined by R3 2n x fc x Vo x Cour gmMea x Vref x gmp 19 Where is the gmea amplifier gain 245 A V gmp is the power stage gain 18 A V fp 3 Place a compensation zero at the dominant pole Cour x RL x 21 C1 can be determined by C1 RL x Cour R3 20 4 C2 is optional It can be used to cancel the zero from Cos ESR C2 Resr x Cour R3 21 Copyright 2010 Texas Instruments Incorporated Submit Documentation Feedback 19 Produc
29. ansients The OVTP feature minimizes the output overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold which is 10796 of the internal voltage reference If the VSENSE pin voltage is greater than the OVTP threshold the high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot When the VSENSE voltage drops lower than the OVTP threshold the high side MOSFET is allowed to turn on the next clock cycle THERMAL SHUTDOWN The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 165 C The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold Once the die temperature decreases below 150 C the device reinitiates the power up sequence by discharging the SS pin to below 40 mV The thermal shutdown hysteresis is 15 C 16 Submit Documentation Feedback Copyright O 2010 Texas Instruments Incorporated Product Folder Link s TPS54319 T ONNE TPS54319 www ti com SLVSA83 JUNE 2010 SMALL SIGNAL MODEL FOR LOOP RESPONSE Figure 32 shows an equivalent model for the TPS54319 control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response The error amplifier is a transconductance amplifier with a gm of 245 up A V The error amplifier can be modeled using an ideal voltage controlled current source The resistor
30. atus Package Type Package Pins Package Qty Eco Plan Lead MSL Peak Temp Samples Drawing Ball Finish Requires Login TPS54319RTER ACTIVE WQFN RTE 16 3000 Green RoHS CU NIPDAU Level 2 260C 1 YEAR Purchase Samples amp no Sb Br TPS54319RTET ACTIVE WQFN RTE 16 250 Green RoHS CU NIPDAU Level 2 260C 1 YEAR Request Free Samples amp no Sb Br M The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS Pb Free RoHS Exempt or Green RoHS amp no Sb Br please check http www ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS Tl s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high
31. ck Copyright O 2010 Texas Instruments Incorporated Product Folder Link s TPS54319 T ONNE TPS54319 www ti com SLVSA83 JUNE 2010 DETAILED DESCRIPTION FIXED FREQUENCY PWM CONTROL The TPS54319 uses an adjustable fixed frequency peak current mode control The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin An internal oscillator initiates the turn on of the high side power switch The error amplifier output is compared to the high side power switch current When the power switch current reaches the COMP voltage level the high side power switch is turned off and the low side power switch is turned on The COMP pin voltage increases and decreases as the output current increases and decreases The device implements a current limit by clamping the COMP pin voltage to a maximum level and also implements a minimum clamp for improved transient response performance SLOPE COMPENSATION AND OUTPUT CURRENT The TPS54319 adds a compensating ramp to the switch current signal This slope compensation prevents sub harmonic oscillations as duty cycle increases The available peak inductor current remains constant over the full duty cycle range BOOTSTRAP VOLTAGE BOOT AND LOW DROPOUT OPERATION The TPS54319 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and PH pin to provide the gate drive voltage for the
32. current facilitates input voltage hysteresis TPS54319 Figure 23 Adjustable Under Voltage Lock Out RI 0 944 x Vstart VsroP Q 3 47 x10 8 2 Bs 1 18 R1 0 Vstop 1 18 4 6x10 R1 3 SLOW START TRACKING PIN The TPS54319 regulates to the lower of the SS TR pin and the internal reference voltage A capacitor on the SS TR pin to ground implements a slow start time The TPS54319 has an internal pull up current source of 2 2uA which charges the external slow start capacitor Equation 4 calculates the required slow start capacitor value where Tss is the desired slow start time in ms Iss is the internal slow start charging current of 2 2 uA and Vref is the internal voltage reference of 0 827 V Tss mS x Iss pA Css nF Vref V 4 12 Submit Documentation Feedback Copyright O 2010 Texas Instruments Incorporated Product Folder Link s TPS54319 T UMENT TPS54319 www ti com SLVSA83 JUNE 2010 If during normal operation the VIN goes below the UVLO EN pin pulled below 1 2 V or a thermal shutdown event occurs the TPS54319 stops switching When the VIN goes above UVLO EN is released or pulled high or a thermal shutdown is exited then SS TR is discharged to below 40 mV before reinitiating a powering up sequence The VSENSE voltage will follow the SS TR pin voltage with a 35mV offset up to 85 of the internal voltage reference When the SS TR voltage is greater than 85 on the internal reference voltage
33. he following steps 1 Set up the anticipated cross over frequency Use Equation 40 to calculate the compensation network s resistor value In this example the anticipated cross over frequency fc is 56 kHz The power stage gain gmps is 18 A V and the error amplifier gain JMea is 245 A V 2n x fc x Vo x Co Gm x Vref x Vla R3 40 2 Place compensation zero at the pole formed by the load resistor and the output capacitor The compensation network s capacitor can be calculated from Equation 41 C3 Ro x Co R3 41 3 An additional pole can be added to attenuate high frequency noise In this application it is not necessary to add it From the procedures above the compensation network includes a 7 68 kO resistor and a 3300 pF capacitor 24 Submit Documentation Feedback Copyright O 2010 Texas Instruments Incorporated Product Folder Link s TPS54319 T ONNE TPS54319 www ti com APPLICATION CURVES SLVSA83 JUNE 2010 EFFICIENCY EFFICIENCY vs vs LOAD CURRENT LOAD CURRENT 100 3 3 Vin 1 8 Vout 100 90 90 80 5 Vin 1 8 Vout 80 y 7 70 70 c ES 3 60 3 3 Vin 1 8 Vout b 5 Vin 1 8 Vout a 60 gt N y 9 2 50 g 50 E 2 S 40 40 30 i 20 ui 20 ld 10 nad 10 of 0 05 05 1 15 2 25 3 0 001 0 01 0 1 1
34. he value calculated in Equation 8 to ensure the device can recover from a fault As the SS TR voltage becomes more than 85 of the nominal reference voltage the Vssoffset becomes larger as the slow start circuits gradually handoff the regulation reference to the internal voltage reference The SS TR pin voltage needs to be greater than 1 1 V for a complete handoff to the internal voltage reference as shown in Figure 27 Vout2 AV Vssoffset R1 x Vref Iss 5 Ro Vref x R1 Vout2 AV Vref 6 AV Vout1 Vout2 7 R1 2930 x Vout1 145x AV 8 14 Submit Documentation Feedback Copyright O 2010 Texas Instruments Incorporated Product Folder Link s TPS54319 T UMENT TPS54319 www ti com SLVSA83 JUNE 2010 TPS54319 EN1 SS TR1 PWRGD1 TPS54319 a ss 200ns pt LA 1 P E lo ss Laii Laa ra L Ch1 2 0 che Tov M 1 0ms 5 0NIS S TO 0 na 4 Ch 136V Figure 28 Ratio metric and Simultaneous Startup Figure 29 Ratio metric Start Up using Coupled Sequence SS TR Pins CONSTANT SWITCHING FREQUENCY and TIMING RESISTOR RT CLK Pin The switching frequency of the TPS54319 is adjustable over a wide range from 300 kHz to 2000 kHz by placing a maximum of 700 kQ and minimum of 85 KQ respectively on the RT CLK pin An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency The RT CLK
35. high side MOSFET The value of the ceramic capacitor should be 0 1 uF A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of the stable characteristics over temperature and voltage To improve drop out the TPS54319 is designed to operate at 100 duty cycle as long as the BOOT to PH pin voltage is greater than 2 2 V The high side MOSFET is turned off using an UVLO circuit allowing for the low side MOSFET to conduct when the voltage from BOOT to PH drops below 2 2 V Since the supply current sourced from the BOOT pin is very low the high side MOSFET can remain on for more switching cycles than are required to refresh the capacitor thus the effective duty cycle of the switching regulator is very high ERROR AMPLIFIER The TPS54319 has a transconductance amplifier The error amplifier compares the VSENSE voltage to the lower of the SS TR pin voltage or the internal 0 827 V voltage reference The transconductance of the error amplifier is 245HA V during normal operation When the voltage of VSENSE pin is below 0 827 V and the device is regulating using the SS TR voltage the gm is typically greater than 79 uA V but less than 245 n A V The frequency compensation components are placed between the COMP pin and ground VOLTAGE REFERENCE The voltage reference system produces a precise 3 0 voltage reference over temperature by scaling the output of a temperature stable bandgap circuit
36. iciency operation Using Equation 9 R5 is calculated to be 180 kO A standard 1 182 kO value was chosen in the design U1 L1 VIN 3 6V TPS54319RTE 1 5 uH VOUT 1 8 V 3A VIN 4 10 SNVY 2 VOUT Let Lez cs c8 C9 2 RE A io Q 1uF 22 uF 22 uF 11 8k E Z R7 10 0k C5 7 68k O1uF A wd tek 9879 JA NOT INSTALLED 3300pF Figure 35 High Frequency 1 8 V Output Power Supply Design with Adjusted UVLO OUTPUT INDUCTOR SELECTION The inductor selected works for the entire TPS54319 input voltage range To calculate the value of the output inductor use Equation 22 Knp is a coefficient that represents the amount of inductor ripple current relative to the maximum output current The inductor ripple current is filtered by the output capacitor Therefore choosing high inductor ripple currents impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current In general the inductor ripple value is at the discretion of the designer however Ki is normally from 0 1 to 0 3 for the majority of applications 20 Submit Documentation Feedback Copyright O 2010 Texas Instruments Incorporated Product Folder Link s TPS54319 T ONNE TPS54319 www ti com SLVSA83 JUNE 2010 For this design example use Knp 0 3 and the inductor value is calculated to be 1 36 uH For this design a
37. id com Space Avionics amp www ti com space avionics defense Defense RF IF and ZigBee Solutions www ti com lprf Video and Imaging www ti com video Wireless www ti com wireless apps Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2010 Texas Instruments Incorporated
38. is typically 0 5 V To determine the timing resistance for a given switching frequency use the curve in Figure 5 and Figure 6 or Equation 9 311890 RT kQ 1 0793 Fsw kHz 133870 7 RT kQ 9325 10 To reduce the solution size one would typically set the switching frequency as high as possible but tradeoffs of the efficiency maximum input voltage and minimum controllable on time should be considered The minimum controllable on time is typically 65 ns at full current load and 120 ns at no load and limits the maximum operating input voltage or output voltage OVERCURRENT PROTECTION The TPS54319 implements a cycle by cycle current limit During each switching cycle the high side switch current is compared to the voltage on the COMP pin When the instantaneous switch current intersects the COMP voltage the high side switch is turned off During overcurrent conditions that pull the output voltage low the error amplifier responds by driving the COMP pin high increasing the switch current The error amplifier output is clamped internally This clamp functions as a switch current limit FREQUENCY SHIFT To operate at high switching frequencies and provide protection during overcurrent conditions the TPS54319 implements a frequency shift If frequency shift was not implemented during an overcurrent condition the low side MOSFET may not be turned off long enough to reduce the current in the inductor causing a current runaway With fre
39. ldered to a thermal pad on the board Refer to Application Note Quad Flat Pack Packages Texas Instruments Literature No SCBAQ17 SLUA271 and also the Product Data Sheets for specific thermal information via requirements and recommended board layout These documents are available at www ti com http www ti com gt E Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release Customers should contact their board assembly site for stencil design recommendations Refer to IPC 7525 for stencil design considerations F Customers should contact their board fabrication site for minimum solder mask web tolerances between signal pads 35 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI
40. lope compensation is ignored the actual cross over frequency is usually lower than the cross over frequency used in the calculations Use SwitcherPro software for a more accurate design To get started the modulator pole fpmod and the esr zero fz1 must be calculated using Equation 36 and Equation 37 For Cout derating the capacitor is not needed as the 1 8 V output is a small percentage of the 10 V capacitor rating If the output is a high percentage of the capacitor rating use the capacitor manufacturer information to derate the capacitor value Use Equation 38 and Equation 39 to estimate a starting point for the crossover frequency fc For the example design fpmod is 6 03 kHz and fzmod is 1210 kHz Equation 38 is the geometric mean of the modulator pole and the esr zero and Equation 39 is the mean of modulator pole and the switching frequency Equation 38 yields 85 3 kHz and Equation 39 gives 54 9 kHz Use the lower value of Equation 38 or Equation 39 as the approximate crossover frequency For this example fc is 56 kHz Next the compensation components are calculated A resistor in series with a capacitor is used to create a compensating zero A capacitor in parallel to these two components forms the compensating pole if needed loutmax fp mod 2n x Vout x Cout 36 1 fzmod 2n x Resr x Cout 37 fe fp modx fz mod 38 fc fp mod x SV 2 39 The compensation design takes t
41. must also be selected with the DC bias taken into account The capacitance value of a capacitor decreases as the DC bias across a capacitor increases For this example design a ceramic capacitor with at least a 10 V voltage rating is required to support the maximum input voltage For this example one 10 uF and one 0 1 uF 10 V capacitors in parallel have been selected The input capacitance value determines the input ripple voltage of the regulator The input voltage ripple can be calculated using Equation 31 Using the design example values loutmax 3 A Cin 10 uF Fsw 1 MHz yields an input voltage ripple of 76 mV and a rms input ripple current of 1 47 A Vout Vinmin Vout Icirms lout x Xx _ Vinmin Vinmin 30 AVin loutmax x 0 25 Cin x fsw 31 SLOW START CAPACITOR The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its 22 Submit Documentation Feedback Copyright 2010 Texas Instruments Incorporated Product Folder Link s TPS54319 T ONNE TPS54319 www ti com SLVSA83 JUNE 2010 nominal programmed value during power up This is useful if a load requires a controlled voltage slew rate This is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level The large currents necessary to charge the capacitor may make the TPS54319 reach the current limit or excessive current dra
42. n Logic Slope Compensation Shutdown COMP PH Frequency Shift Maximum Clamp A d GND TPS54319RTE Block Diagram AGND POWERPAD RT CLK TYPICAL CHARACTERISTICS CURVES HIGH SIDE AND LOW SIDE Rdson vs TEMPERATURE FREQUENCY vs TEMPERATURE 0 08 High Side Rdson Vy 3 3 V 0 07 Low Side Rd 0 06 0 05 0 04 fs Switching Frequency kHz Low Side Rdsol 0 03 RDSON Static Drain Source On State Resistance Q 50 25 0 25 50 75 100 125 150 50 25 0 25 50 75 100 125 150 l T Junction Temperature C T Junction Temperature C Figure 1 Figure 2 6 Submit Documentation Feedback Copyright 2010 Texas Instruments Incorporated Product Folder Link s TPS54319 1 TEXAS INSTRUMENTS www ti com TPS54319 SLVSA83 JUNE 2010 TYPICAL CHARACTERISTICS CURVES continued VOLTAGE REFERENCE vs TEMPERATURE HIGH SIDE CURRENT LIMIT vs TEMPERATURE High Side Switch Current A 50 25 0 25 50 75 100 125 150 T Junction Temperature C Figure 3 SWITCHING FREQUENCY vs RT RESISTANCE LOW FREQUENCY RANGE e o E cx o o e eo 7 a Q cy f Switching Frequncy
43. n load current The output capacitance needs to be selected based on the more stringent of these three criteria The desired response to a large change in the load current is the first criteria The output capacitor needs to supply the load with current when the regulator can not This situation would occur if there are desired hold up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed The regulator is temporarily not able to supply sufficient output current if there is a large fast increase in the current needs of the load such as transitioning from no load to a full load The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage Equation 26 shows the minimum output capacitance necessary to accomplish this For this example the transient load response is specified as a 5 change in Vout for a load step from 0 A no load to 1 5 A 50 load For this example Alout 1 5 0 1 5 A and AVout 0 05 x 1 8 0 090 V Using these number
44. nearest standard value was chosen 1 5 uH For the output filter inductor it is important that the RMS current and saturation current ratings not be exceeded The RMS and peak inductor current can be found from Equation 24 and Equation 25 For this design the RMS inductor current is 3 01 A and the peak inductor current is 3 72 A The chosen inductor is a Coilcraft XLA4020 152ME_ It has a saturation current rating Of 9 6 A and a RMS current rating of 7 5 A The current flowing through the inductor is the inductor ripple current plus the output current During power up faults or transient load conditions the inductor current can increase above the calculated peak inductor current level calculated above In transient conditions the inductor current can increase up to the switch current limit of the device For this reason the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current L1 Vinmax Vout x Vout lo x Kind Vinmax x fsw 22 Vinmax Vout Vout lripple Ke L1 Vinmax x fsw 23 2 mE je 4 i x e x Vinmax sa 2 Vinmax x L1 x fsw 24 ILpeak lout tipple 25 OUTPUT CAPACITOR There are three primary considerations for selecting the value of the output capacitor The output capacitor determines the modulator pole the output voltage ripple and how the regulator responds to a large change i
45. nts up to 3 amperes The TPS54319 reduces the external component count by integrating the boot recharge diode The bias voltage for the integrated high side MOSFET is supplied by a capacitor between the BOOT and PH pins The boot capacitor voltage is monitored by an UVLO circuit and turns off the high side MOSFET when the voltage falls below a preset threshold This BOOT circuit allows the TPS54319 to operate approaching 10096 The output voltage can be stepped down to as low as the 0 827 V reference The TPS54319 has a power good comparator PWRGD with 296 hysteresis The TPS54319 minimizes excessive output over voltage transients by taking advantage of the over voltage power good comparator When the regulated output voltage is greater than 107 of the nominal voltage the over voltage comparator is activated and the high side MOSFET is turned off and masked from turning on until the output voltage is lower than 105 The SS TR slow start tracking pin is used to minimize inrush currents or provide power supply sequencing during power up A small value capacitor should be coupled to the pin for slow start The SS TR pin is discharged before the output power up to ensure a repeatable restart after an over temperature fault UVLO fault or disabled condition The use of a frequency fold back circuit reduces the switching frequency during startup and over current fault conditions to help limit the inductor current 10 Submit Documentation Feedba
46. o event shall Tl s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 ip TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 20 Jul 2010 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS Reel Diameter Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness y Overall width of the carrier tape Y Pitch between successive cavity centers t Reel Width W1 QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes User Direction of Feed All dimensions are nominal Device Package Package Pins l SPQ Reel Reel AO BO KO P1 W Pin1 Type Drawing Diameter Width mm mm mm mm mm Quadrant mm W1 mm TPS54319RTER WQFN RTE 16 3000 330 0 12 4 3 3 3 3 1 1 8 0 12 0 Q2 TPS54319RTET WQFN RTE 16 250 180 0 12 4 3 3 3 3 1 1 8 0 12 0 Q2 Pack Materials Page 1 ip TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 20 Jul 2010 TAPE AND REEL BOX DIMENSIONS All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm TPS54319RTER WQFN RTE 16 3000 346 0 346 0 29 0 TPS54319RTET WQFN RTE 16 250 190 5 212 7 31 8 Pack
47. quency shift during an overcurrent condition the switching frequency is reduced from 100 then 50 then 25 then 12 5 as the voltage decreases from 0 827 to 0 volts on VSENSE pin to allow the low side MOSFET to be off long enough to decrease the current in the inductor During start up the switching frequency increases as the voltage on VSENSE increases from 0 to 0 827 volts See Figure 7 for details Copyright 2010 Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Link s TPS54319 TPS54319 P I UMS SLVSA83 JUNE 2010 www ti com REVERSE OVERCURRENT PROTECTION The TPS54319 implements low side current protection by detecting the voltage across the low side MOSFET When the converter sinks current through its low side FET the control circuit turns off the low side MOSFET if the reverse current is typically more than 2 A By implementing this additional protection scheme the converter is able to protect itself from excessive current during power cycling and start up into pre biased outputs SYNCHRONIZE USING THE RT CLK PIN The RT CLK pin is used to synchronize the converter to an external system clock See Figure 30 To implement the synchronization feature in a system connect a square wave to the RT CLK pin with an on time of at least 75ns If the pin is pulled above the PLL upper threshold a mode change occurs and the pin becomes a synchronization input The internal amplifier is disabled and the pin is
48. reases the low frequency gain decreases and increases respectively This variation with load may seem problematic at first glance but the dominant pole moves with load current see Equation 13 The combined effect is highlighted by the dashed line in the right half of Figure 33 As the load current decreases the gain increases and the pole frequency lowers keeping the 0 dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation Copyright 2010 Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Link s TPS54319 TPS54319 PI UMS SLVSA83 JUNE 2010 www ti com Figure 33 Simple Small Signal Model and Frequency Response for Peak Current Mode Control S x fz vo anges E vc S 1 2n x fp 11 Adc gmy x R 12 fp Cour x RL x 27 13 1 z Cour Resp x 27 14 SMALL SIGNAL MODEL FOR FREQUENCY COMPENSATION The TPS54319 uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits The compensation circuits are shown in Figure 34 The Type 2 circuits are most likely implemented in high bandwidth power supply designs using low ESR output capacitors In Type 2A one additional high frequency pole is added to attenuate high frequency noise vo R12 VSENSE Figure 34 Types of Frequency Compensation 18 Submit Documentation Feedb
49. s gives a minimum capacitance of 33 uF This value does not take the ESR of the output capacitor into account in the output voltage change For ceramic capacitors the ESR is usually small enough to ignore in this calculation Equation 27 calculates the minimum output capacitance needed to meet the output voltage ripple specification Where fsw is the switching frequency Vripple is the maximum allowable output voltage ripple and Iripple is the inductor ripple current In this case the maximum output voltage ripple is 30 mV Under this requirement Equation 27 yields 2 3 uF 2 x Alout ce f Sw x AVout 26 Copyright O 2010 Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Link s TPS54319 TPS54319 nee SLVSA83 JUNE 2010 www ti com 1 1 8 x fsw Voripple Irip ple Where Alout is the change in output current Fsw is the regulators switching frequency and AVout is the allowable change in the output voltage 27 Co gt Equation 28 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification Equation 28 indicates the ESR should be less than 55 mQ In this case the ESR of the ceramic capacitor is much less than 55 mQ Additional capacitance de ratings for aging temperature and DC bias should be factored in which increases this minimum value For this example two 22 uF 10 V X5R ceramic capacitors with 3 mQ of ESR are used Capacitors generally have limits
50. t Folder Link s TPS54319 I TEXAS TPS54319 INSTRUMENTS SLVSA83 JUNE 2010 www ti com APPLICATION INFORMATION DESIGN GUIDE STEP BY STEP DESIGN PROCEDURE This example details the design of a high frequency switching regulator design using ceramic output capacitors This design is available as the HPA375 evaluation module EVM A few parameters must be known in order to start the design process These parameters are typically determined on the system level For this example we start with the following known parameters Output Voltage 1 8V Transient Response 1 to 2A load step AVout 5 Maximum Output Current 3A Input Voltage 5Vnom 3Vto5V Output Voltage Ripple lt 30 mV p p Switching Frequency Fsw 1000 kHz SELECTING THE SWITCHING FREQUENCY The first step is to decide on a switching frequency for the regulator Typically you want to choose the highest switching frequency possible since this produces the smallest solution size The high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency However the highest switching frequency causes extra switching losses which hurt the converter s performance The converter is capable of running from 300 kHz to 2 MHz Unless a small solution size is an ultimate goal a moderate switching frequency of 1MHz is selected to achieve both a small solution size and a high eff
51. temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents Tl s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In n
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53. w from the input power supply may cause the input voltage rail to sag Limiting the output voltage slew rate solves both of these problems The slow start capacitor value can be calculated using Equation 32 For the example circuit the slow start time is not too critical since the output capacitor value is 44 uF which does not require much current to charge to 1 8 V The example circuit has the slow start time set to an arbitrary value of 4ms which requires a 10 nF capacitor In TPS54319 Iss is 2 2 nA and Vref is 0 827 V Css nF Tss ms x Iss uA BOOTSTRAP CAPACITOR SELECTION A 0 1 uF ceramic capacitor must be connected between the BOOT to PH pin for proper operation It is recommended to use a ceramic capacitor with X5R or better grade dielectric The capacitor should have 10 V or higher voltage rating OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION For the example design 100 kO was selected for R6 Using Equation 33 R7 is calculated as 80 kO The nearest standard 1 resistor is 80 5 kO R7 Vref Vo Vref 33 Due to the internal design of the TPS54319 there is a minimum output voltage limit for any given input voltage The output voltage can never be lower than the internal voltage reference of 0 827 V Above 0 827 V the output voltage may be limited by the minimum controllable on time The minimum output voltage in this case is given by Equation 34 Voutmin Ontimemin x Fsmax x Vinmax loutmin x 2 x RDS loutmin x RL

TEXAS INSTRUMENTS - TPS54319 handbook

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