MICREL - MICRF620 434MHz ISM Band Transceiver Module
Contents
1. The Frequency Error Estimator FEE uses information from the demodulator to calculate the frequency offset between the receive frequency and the transmitter frequency The output of the FEE can be used to tune the XCO frequency both for production calibration and for compensation for crystal temperature drift and aging The input to the FEE circuit are the up and down pulses from the demodulator Every time a 1 is updated an UP pulse is coming out of the demodulator and the same with the DN pulse every time the 0 is updated The expected no of pulses for every received symbol is 2 times the modulation index A July 2006 MICRF620 MICRF620Z The FEE can operate in three different modes counting only UP pulses only DN pulses or counting UP DN pulses The no of received symbols to be counted is either 8 16 32 or 64 This is set by the FEEC O FEEC 3 control bit as follows FEEC 1 FEEC 0 FEE Mode 0 0 Off 0 1 Counting UP pulses 1 0 Counting DN pulses 1 1 Counting UP and DN pulses UP increments the counter DN decrements it FEEC 3 FEEC 2 No of symbols used for the measurement 0 0 8 0 1 16 1 0 32 1 1 65 Table 8 FEEC Control Bit The result of the measurement is the FEE value this can be read from register with address 0010110b Negative values are stored as a binary no between 0000000 and 1111111 To calculate the negative value a2. RF circuitry is sensitive to voltage supply and therefore caution should be taken when choosing power circuitry To achieve the best performance July 2006 20 MICRF620 MICRF620Z low noise LDO s with high PSSR should be chosen What is present on the voltage supply will be directly modulated to the RF spectrum causing degradation and regulatory issues To make sure you have the right selection please contact local sales for the latest Micrel offerings in power management and guidance To avoid pickup from other circuitry on the VDD lines it is recommended to route the VDD in a star configuration with decoupling at each circuitry and at the common connection point see above layout If there are noisy circuitry in the design it is strongly recommended to use a separate power supply and or place low value resistors 10ohms inductors in series with the power supply line into these circuitry Digital high speed logic or noisy circuitry should must be at a safe distance from RF circuitry or RF VDD as this might will cause degradation of sensitivity and create spurious emissions Example of such circuitry is LCD display charge pumps RS232 clock data bus etc M9999 120205 Micrel Inc MICRF620 MICRF620Z Package Dimensions 182 Na A Qm A N MICRF620 E L_ E o FO H amp rel FR Tal DI I 3 0 0 2mm 4 0 71 0 02mm k 114 1 0 1mm gt k 13 22mm _ g
3. gt lt Data to write into register 1 RW Data to write into register i Address of first register to write to register i i Internal load pulse made here Figure 2 How to write to many Control Registers July 2006 MICRF620 MICRF620Z Reading from the Control Registers in MICRF620 The read sequence is 1 Enter address and R W bit 2 Change direction of IO line 3 Read out a number of octets and change lO direction back again It is possible to read all 1 or n registers The address to read from or the first address to read from can be any valid address 0 22 Reading is not destructive i e values are not changed The IO line is output from the MICRF620 input to user for a part of the read sequence Refer to procedure description below A read sequence is described for reading n registers where n is number 1 23 Reading n Registers from MICRF620 JO OY MODE gt lt Bat Address of register i RWData read from reg i Simple time IO Input IO Output Figure 3 How to read from many Control Registers In Figure 3 1 register is read The address is A6 A5 AO A6 msb The data read out is D7 D6 DO The value of the R W bit is always 1 for reading SCLK and IO together form a serial interface SCLK is applied externally for reading as well as for writing e Bring CS active e Enter address to read from or the first address to read from 7 bits a
4. MICREL General Description The MICRF620 is a self contained frequency shift keying FSK transceiver module intended for use in half duplex bidirectional RF links The multi channeled FSK transceiver module is intended for UHF radio equipment in compliance with the European Telecommunication Standard Institute ETSI specification EN300 220 The transmitter consists of a fully programmable PLL frequency synthesizer and power amplifier The frequency synthesizer consists of a voltage controlled oscillator VCO a crystal oscillator dual modulus prescaler programmable frequency dividers and a phase detector The output power of the power amplifier can be programmed to seven levels A lock detect circuit detects when the PLL is in lock In receive mode the PLL synthesizer generates the local oscillator LO signal The N M and A values that give the LO frequency are stored in the NO MO and AO registers The receiver is a zero intermediate frequency IF type that makes channel filtering possible with low power integrated low pass filters The receiver consists of a low noise amplifier LNA that drives a quadrature mix pair The mixer outputs feed two identical signal channels in phase quadrature Each channel includes a pre amplifier a third order Sallen Key RC low pass filter that protects the following switched capacitor filter from strong adjacent channel signals and a limiter The main channel filter is a switched ca
5. each register holding 8 bits There are 23 control registers in total in the MICRF620 and they have addresses ranging from 0 to 22 The user can read all the control registers The user can write to the first 22 registers 0 to 21 the register 22 is a read only register All control registers hold 8 bits and all 8 bits must be written to when accessing a control register or they will be read Some of the registers do not utilize all 8 bits The value of an unused bit is don t care The control register with address O is referred to as ControlRegisterO the control register with address 1 is ControlRegister1 and so on A summary of the control registers is given in the table below In addition to the unused bits marked with there are a number of fixed bits marked with 0 or 1 Always maintain these as MICRF620 MICRF620Z shown in the table The control registers in MICRF620 are accessed through a 3 wire interface clock data and chip select These lines are referred to as SCLK IO and CS respectively This 3 wire interface is dedicated to control register access and is referred to as the control interface Received data via RF and data to transmit via RF are handled by the DatalXO and DataClk if enabled lines this is referred to as the data interface The SCLK line is applied externally access to the control registers are carried out at a rate determined by the user The MICRF620 will ignore tran
6. 3 wire Programming Interface July 2006 10 M9999 120205 Micrel Inc Power on Reset When applying voltage to the MICRF620 a power on reset state is entered During the time period of power on reset the MICRF620 should be considered to be in an unknown state and the user should wait until completed See Table 6 The power on reset timing given in table 6 is covering all conditions and should be treated as a maximum delay time In some application it might be beneficial to minimize the power on reset time In these cases we recommend to follow below procedure Program address 0x00 0x03 Read back programmed byte Value 0x03 End of Power on Reset July 2006 MICRF620 MICRF620Z Programming Summary 11 Use CS SCLK and IO to get access to the control registers in MICRF620 SCLK is user controlled Write to the MICRF620 at positive edges MICRF620 reads at negative edges Read from the MICRF620 at negative edges MICRF620 writes at positive edges After power on Write to the complete set of control registers Address field is 7 bits long Enter msb first R W bit is 1 bit long 1 for read 0 for write Address and R W bit together make 1 octet All control registers are 8 bits long Enter read msb in every octet first Always write 8 bits to read 8 bits from a control register This is the case for registers with less than 8 used programming bits as well Writing Bring CS high write
7. D2 D1 DO 0001000 d xd ScCIk5 ScClk4 ScClk3 ScClk2 ScCIk1 ScCIkO The main channel filter is a switched capacitor implementation of a six pole elliptic low pass filter The elliptic filter minimized the total capacitance required for a given selectivity and dynamic range The cut off frequency of the switched capacitor filter is adjustable by changing the clock frequency The clock frequency is designed to be 20 times the cut off frequency The clock frequency is derived from the reference crystal oscillator A programmable 6 bit divider divides the frequency of the crystal oscillator The cut off frequency of the filter is given by fxco fcur 40 ScCIk fcur Filter cutoff frequency fxco Crystal oscillator frequency ScCLK Switched capacitor filter clock bits ScCIk5 0 1 order RC lowpass filters are connected to the output of the SC filter to filter the clock frequency The lowest cutoff frequency in the pre and the main channel filter must be set so that the received signal is passed with no attenuation that is frequency deviation plus modulation If there are any frequency offset between the transmitter and the receiver this must also be taken into consideration A formula for the receiver bandwidth can be summarized as follows few foFFSET fDev Baudrate 2 where few Needed receiver bandwidth fcut above should not be smaller than few Hz forse Total frequency offset between receiver and transm
8. EAE eH EE SE dt ge res 17 Application Circuit Ildstratiori aree ER re EO HG D A ite 18 Assemblingahie MIGREO20 tcr e ete mede FER e e Dr REND Aia aaa 19 Recommended Reflow Temperature Profile oooooooconnninococccnnnnncncononcnncnnnnnnnnnnnononncnnnnnnnnnnn nn nn cnn cnn nnn nnnm nne t enn n nennen nnns 19 Shock Vibration during ROO Wicca Pe E Y Pe Cos beer Re e EE e e alte Ee EP Ee eu XE Pe EE eee 19 Handassembling the MIGERE620 1 tert erg es tete pede pen esce ed podia ci ed reditibus 19 E yLE n 19 Recommended Land Patterm tete A O otii iet eodem itta Donius 19 Layout Considerations naeron ena i dme oom PO escorts pte tee co Mei PEERS 20 Package DIMENSIONS n Poder he nete Teo POIL E EE ER POI HEC P o de Po HEC eed eodein 21 Tape DImenslons ier ee f Ln lt acted aeu ERES ARE a UERBO Te pes UE RP ada aae e Hou aaa 21 July 2006 2 M9999 120205 Micrel Inc RadioWire RF Module Selection Guide MICRF620 MICRF620Z Frequency Supply Modulation Device Range Data Rate Receive Voltage Transmit Type Package MICRF600 902 928 MHz 20 kbps 13 5mA 2 0 2 5 v 28 mA FSK 11 5x14 1 mm MICRF600Z Lead free MICRF600 MICRF610 868 870 MH
9. address and R W bit followed by the new values to fill into the addressed control register s and bring CS low for loading i e activation of the new control register values Reading Bring CS high write address and R W bit set lO as an input read present contents of the addressed control register s bring CS low and set IO an output M9999 120205 Micrel Inc Frequency Synthesizer A6 AO D7 D6 D5 D4 D3 D2 D1 DO 0001010 A05 A04 A03 A02 A01 A00 0001011 NO 11 NO 10 NO 9 NO 8 0001100 NO7 NO6 NO5 No4 NO3 NO2 NO1 NOO 0001101 M0 11 M0 10 MO_9 MO 8 0001110 M07 M96 M05 M04 MOo3 Mo2 MO 1 MOO 0001111 Ais A14 A13 A12 A14 AO 0010000 NT T1 N1_10 N19 N18 0010001 Ni_7 N16 N15 N14 NI3 Niz2 N11 N10 0010010 Mi_11 M110 M19 M18 0010011 M17 M16 M15 M4 Mi_3 M12 M1 M0 The frequency synthesizer consists of a voltage controlled oscilator VCO a crystal oscillator phase select prescaler programmable frequency dividers and a phase detector The length of the N M and A registers are 12 12 and 6 respectively The N M and A values can be calculated from the formula fo n xco _ fvco __ fae x2 PhD O M t6xN A x2 16xN A M 0 1 lt A lt N fpup Phase detector comparison frequency fxco Crystal oscillator frequency fvco Voltage control
10. can be turned off by setting PA2 PAO 0 For all other combinations the PA is on and has maximum July 2006 power when PA2 PAO 1 The PA will be bypassed if PA_by 1 Output power will drop 22dB It is still possible to control the power by PA2 PAO Frequency Modulation FSK modulation is applied by switching between two sets of dividers M N A The formula for calculating the M N and A values is given in chapter Frequency synthesizer The divider values stored in the MO NO and AO0 registers will be used when transmitting a 0 and the M1 N1 and A1 registers will be used to transmit a 1 The difference between the two carrier frequencies corresponds to the double sided frequency deviation The data to be transmitted shall be applied to pin DatalXO see chapter Transceiver sync non synchronous mode on how to use the pin DataClk The DatalXO pin is set as input in transmit mode and output in receive mode Using the XCO tune Bits The module has a built in mechanism for tuning the frequency of the crystal oscillator and is often used in combination with the Frequency Error Estimator FEE The XCO tuning is designed to eliminate or reduce initial frequency tolerance of the crystal and or the frequency stability over temperature A procedure for using the XCO tuning feature in combination with the FEE is given below The MICRF620 measures the frequency offset between the receivers LO frequency and
11. the frequency of the transmitter The receiver XCO frequency can be tuned until the receiver and transmitter frequencies are equal A procedure like this can be called during production storing the calibrated XCO tune value at regular intervals or implemented in the communication protocol when the frequency has changed The MICRF620 development system can test this feature Example In FEE count up down pulses counting 8 bits A perfect case gt FEE 0 If FEE gt 0 LO is too low increase LO by decreasing XCO tune value v v for FEE lt 0 FEE field holds a number in the range 128 127 However it keeps counting above below the range which is 17 M9999 120205 Micrel Inc If FEE 128 and still counting dwn pulses 1 22 129 127 2 126 3 125 To avoid this situation always make sure max count is between limits Application Circuit Illustration MICRF620 4004 Figure 11 Circuit illustration of MICRF620 LDO and MCU Figure 12 shows a typical set up with the MICRF620 a Low Drop Out voltage regulator LDO and a mikro controller MCU When the MICRF620 and the MCU runs on the same power supply min 2 0 max 2 5V the IO can be connected directly to the MCU If the MCU needs a higher VDD than the max specified VDD of the MICRF620 2 5V voltage dividers need to be added on the IO lines not to override the max input voltage Figure 11 shows a recommended voltage divider circuit f
12. 9 2 kbps f 8 SC 200 kHz 107 dBm 19 2 kbps B 2 SC 67 kHz 105 dBm Receiver Maximum Input Power 19 2 kbps 8 8 10 dBm Receiver Sensitivity Tolerance Edel ts 2 o Over power supply range 1 dB Receiver Bandwidth 50 350 kHz Co Channel Rejection 19 2 kbps B 6 SC 133 kHz 8 dB 200 kHz spacing Adjacent Channel Rejection 500 kHz spacing 1 MHz spacing Offset 1MHz 61 dB Desired signal Offset 2MHz 58 dB Blocking MC NA md Offset 5MHz 46 dB SC 133 kHz Offset 10MHz 62 dB Offset 30MHz 75 dB 1dB Compression 35 dB Input IP3 2 tones with 1MHz separation 25 dBm Input IP2 dBm LO Leakage 90 dBm Spurious Emission 1GHz 57 dBm ETSI 300 220 Spurious Emission gt 1GHz 47 dBm Input Impedance 374j18 Q RSSI Dynamic Range 50 dB RSSI Output Range S SEE Pin 60 dBm 1 9 V Digital Inputs Outputs Logic Input High 0 7Vpp Vpp V Logic Input Low 0 0 3Vpp V Clock Data Frequency 10 MHz Clock Data Duty Cycle 45 55 Notes Exceeding the absolute maximum rating may damage the device The device is not guaranteed to function outside its operating rating Devices are ESD sensitive Handling precautions recommended Human body model 1 5k in series with 100pF 1 2 3 4 Guaranteed by design July 2006 M9999 120205 Micrel Inc Programming General The MICRF620 functions are enabled through a number of programming bits The programming bits are organized as a set of addressable control registers
13. N1 3 N12 N1 1 N1 0 0010010 M1 11 M1 10 M1 9 M1 8 0010011 M1 7 M1 6 M1 5 M1 4 M1 3 M1 2 M1 1 M1 0 0010100 A 0 q q 0 q 0 a 0010101 FEEC 3 FEEC_2 FEEC 1 FEEC 0 0010110 FEE 7 FEE 6 FEE 5 FEE 4 FEE 3 FEE 2 FEE 1 FEE 0 July 2006 Table 1 Control Registers in MICRF620 M9999 120205 Micrel Inc Writing to the Control Registers in MICRF620 Writing A number of octets are entered into MICRF620 followed by a load signal to activate the new setting Making these events is referred to as a write sequence It is possible to update all 1 or n control registers in a write sequence The address to write to or the first address to write to can be any valid address 0 21 The IO line is always an input to the MICRF620 output from user when writing What to write e The address of the control register to write to or if more than 1 control register should be written to the address of the 1 control register to write to e A bit to enable reading or writing of the control registers This bit is called the R W bit e The values to write into the control register s Field Comments Address A 7 bit field ranging from 0 to 21 MSB is written first R W bit A 1 bit field O for writing Values A number of octets 1 22 octets MSB in every octet is written first The first octet is written to the control register with the specified address Address The nex
14. O tune value then the start up time will be longer To save current in the crystal oscillator start up period the XCO is turned on before any other circuit block When the XCO has settled rest of the circuit will be turned on No programming should be made during this period The current consumption during the prestart period is approximately 280pA VCO A6 A0 D7 D6 D5 D4 D3 D2 D1 DO 0000011 T v 0 VCO_IB2 VCO IB1 VCO IBO VCO freq1 VCO_fregO The VCO has no external components It has three bit to set the bias current and two bit to set the VCO frequency These five bits are set by the RF frequency as follows RF freq VCO IB2 VCO IB1 VCO IBO VCO freq1 VCO freqO 410MHz 1 0 1 0 1 434MHz 1 0 0 1 0 450MHz 0 1 1 1 1 Table 7 VCO Bit Setting The bias bit will optimize the phase noise and the frequency bit will control a capacitor bank in the VCO The tuning range the RF frequency versus varactor voltage is dependent on the VCO frequency setting and can be shown in Figure 6 12 M9999 120205 Micrel In C 480 VCO frequency gain Vdd 2 5V 460 440 420 Freq MHz 400 380 0 4 0 8 1 2 1 6 2 V varactor V 2 4 1 10 01 00 Figure 6 RF Frequency vs Varactor Voltage and VCO Frequency bit Vpp 2 5V Lock Det
15. RefClk_K1 RefClk_KO a aca Ea Commens The data interface is defined in such a way that all user 0 io MM oft Transparent reception of data actions should take place on falling edge and is illustrated Transparent transmission of 0 Tx DataClk pin off data Rx Bit synchronization on Bit clock is generated by 1 transceiver Bit clock is generated by 1 Tx DataClk pin on a transceiver When Sync_en 1 it will enable the bit synchronizer in receive mode The bit synchronizer clock needs to be programmed see chapter Bit synchronizer The synchronized clock will be set out on pit DataClk In transmit mode when Sync en 1 the clock signal on pin DataCik is a programmed bit rate clock Now the transceiver controls the actual data rate The data to be transmitted will be sampled on rising edge of DataClk The micro controller can therefore use the negative edge to change the data to be transmitted The clock used for this purpose BitRate clock is programmed in the same way as the modulator clock and the bit synchronizer clock fxco Refclk K x 2 BITRATE cIkS fBITRATE_CL K where feirrare cu The clock frequency used to control the bit rate should be equal to the bit rate bit rate of 20 kbit sec requires a clock frequency of 20kHz fxco Crystal oscillator frequency Refclk K 6 bit divider values between 1 and 63 BitRate_clkS Bit rate setting values between 0 and 6 Data Interfac
16. Totally 2 octets are clocked into the MICRF620 How to write e Bring CS high e Use SCLK and IO to clock in the 2 octets e Bring CS low sx Tis aun rq mn JD PCENA I CE CIP ACE Data to write into register i Internal load pulse made here e gt Address of register i RW Figure 1 How to write to a single Control Register In Figure 1 IO is changed at positive edges of SCLK The MICRF620 samples the IO line at negative edges The value of the R W bits is always 0 for writing Writing to All Registers After a power on all writable registers must be written This is described here Writing to all register can be done at any time To get the simplest firmware always write to all registers The price to pay for the simplicity is increased write time which leads to increased time for changing the way the MICRF620 works What to write Field Comments Address 000000 address of the first register to write to which is 0 R W bit 0 for writing Values 1 Octet wanted values for ControlRegister0 2 Octet wanted values for ControlRegister1 and so on for all of the octets So the 22 octet wanted values for ControlRegister21 Refer to the specific sections of this document for actual values Table 4 Address and R W bit together make 1 octet In total 23 octets are clocked into the MICRF620 8 M9999 120205 Micrel Inc How to write e Bring CS hi
17. XO 1 0 Data receive transmit bi directional 7 DATACLK O Data clock receive transmit 8 LD O Lock detect 9 RSSI O Receive signal strength indicator 10 GND Ground 11 GND Ground 12 GND Ground 13 ANT y o RF In Out 14 GND Ground 15 VDD VDD 2 0 2 5V 16 GND Ground July 2006 M9999 120205 Micrel Inc Absolute Maximum Ratings Supply Voltage Vpp Voltage on any pin GND OV 0 3V to 2 7V Lead Temperature soldering 5 sec 225 C Storage Temperature GIS E E 30 C to 85 C ESD Rating rain aida 2kV Electrical Characteristics Operating Ratings dec dons tte ded das 2 V Supply voltage Vin RF Frequencies Data Rate NRZ Ambient Temperature T4 MICRF620 MICRF620Z 2 0V to 2 5V 410MHz to 450MHz 20 kbps 20 C to 75 C frr 434MHz Data rate 20kbps Vpp 2 5V T4 25 C bold values indicate 20 C lt Ta lt 75 C unless noted Parameter Condition Min Typ Max Units Power Supply 2 0 2 5 V Power Down Current 0 3 uA Standby Current 280 uA VCO and PLL Section Tunable with on chip cap bank 16 MHz Crystal Oscillator Frequency Tuning range 30 40 ppm Crystal Initial Tolerance 10 10 ppm Crystal Temperature Tolerance 10 10 ppm Rx 433 4MHz Rx 434MHz 300 us Rx Tx same fr
18. ataClk The micro controller should therefore sample the symbol bit on falling edge of DataClk The bit synchronizer uses a clock that needs to be programmed according to the bit rate The clock frequency should be 16 times the actual bit rate a bit rate of 20 kbit sec needs a bit synchronizer clock with frequency of 320 kHz The clock frequency is set by the following formula fxco fBITSYNC_CLK E Refclk K x 2 7 BITSYNC clkS where feitsync_cik The bit synchronizer clock frequency 16 times higher than the bit rate fxco Crystal oscillator frequency Refclk K 6 bit divider values between 1 and 63 BitSync clkS Bit synchronizer setting between 0 and 7 values Refclk K is also used to derive the modulator clock and the bit rate clock At the beginning of a received data package the bit synchronizer clock frequency is not synchronized to the bit rate When these two are maximum offset to each other it takes 22 bit symbols before synchronization is achieved Transmitter Power Amplifier A6 A0 D7 D6 D5 D4 D3 D2 D1 DO 0000000 LNA by PA2 PA1 PAO Sync_en Mode1 ModeO a 0000001 T o 0 o RSSI_en LD_en PF_FC1 PF_FCO The maximum output power is approximately 10dBm for a 500 load The output power is programmable in seven steps with approximately 3dB between each step Bits PA2 PAO control this PA2 PAO 1 give the maximum output power The power amplifier
19. ation of a six pole elliptic lowpass filter The elliptic filter minimizes the total capacitance required for a given selectivity and dynamic range The cut off frequency of the Sallen Key RC filter can be programmed to four different frequencies 100kHz 150kHz 230kHz and 340kHz The demodulator demodulates the and Q channel outputs and produces a digital data output If detects the relative phase of the and Q channel signal If the channel signal lags the Q channel the FSK tone frequency lies above the LO frequency data 1 If the channel leads the Q channel the FSK tone lies below the LO frequency data 0 The output of the receiver is available on the DatalXO pin A RSSI circuit receive signal strength indicator indicates the received signal level 14 M9999 120205 Micrel Inc Front End A6 A0 D7 D6 D5 D4 D3 D2 D1 DO 0000000 LNA_by PA2 PA1 PAO Mode1 ModeO W Sync en A low noise amplifier in RF receivers is used to boost the incoming signal prior to the frequency conversion process This is important in order to prevent mixer noise from dominating the overall front end noise performance The LNA is a two stage amplifier and has a nominal gain of approximately 23dB at 434MHz The front end has a gain of about 33dB to 35dB The gain varies by 1 1 5dB over a 2 0V to 2 5V variation in power supply The LNA can be bypassed by setting bit LNA by to 1 This can
20. be useful for very strong input signal levels The front end gain with the LNA bypassed is about 9 10dB The mixers have a gain of about 10dB at 434MHz The input impedance is shown in Figure 9 Pl Reflection Smith 1 U FS c D2 0ff 433 928 MHz 37 490 Meas 1 Mkr2 Start 300 008 MHz Mkr MHz Ohm Ohm 2 Mkr MHz dB 1 433 058 36 81 18 22 25 433 928 37 49 17 95 3 434 798 38 33 iy AP Y d Figure 9 Input Impedance Stop 688 2088 MHz Sallen Key Filters A6 A0 D7 D6 D5 D4 D3 D2 D1 DO 0000001 Y 0 K o RSSI_en LD_en PF FC1 PF FCO Each channel includes a pre amplifier and a prefilter which is a three pole Sallen Key lowpass filter It protects the following switched capacitor filter from strong adjacent channel signals and it also works as an anti aliasing filter The preamplifier has a gain of 22 23dB The maximum output voltage swing is about 1 4Vpp for a 2 25V power supply In addition the IF amplifier also performs offset cancellation Gain varies by less than 0 5dB over a 2 0 2 5V variation in power supply The third order Sallen Key lowpass filter is programmable to four different cut off frequencies according to the table below PF FC1 PF FCO Cut off Freq kHz July 2006 MICRF620 MICRF620Z 0 0 100 0 1 150 1 0 230 1 1 340 Switched Capacitor Filter A6 A0 D7 D6 D5 D4 D3
21. e The MICRF620 interface can be divided in to two separate interfaces a programming interface and a Data interface The programming interface has a three wire serial programmable interface and is described in chapter Programming The data interface can be programmed to sync non synchronous mode In synchronous mode the MICRF620 is defined as Master and provides a data clock that allows users to utilize low cost micro controller reference frequency July 2006 Figure 7 and 8 The two figures illustrate the relationship between DATACLK and DATAIXO in receive mode and transmit mode MICRF620 will present data on rising edge and the USER sample data on falling edge in receive mode DATACLK Figure 7 Data interface in Receive Mode The User presents data on falling edge and MICRF620 samples on rising edge in transmit mode DATAIXO DATACLK J al m Figure 8 Data interface in Transmit Mode Receiver The receiver is a zero intermediate frequency IF type in order to make channel filtering possible with low power integrated low pass filters The receiver consists of a low noise amplifier LNA that drives a quadrature mixer pair The mixer outputs feed two identical signal channels in phase quadrature Each channel includes a pre amplifier a third order Sallen Key RC lowpass filter from strong adjacent channel signals and finally a limiter The main channel filter is a switched capacitor implement
22. ect A6 A0 D7 D6 D5 D4 D3 D2 D1 po 0000001 ZU 0 O 0 RSSI_en LD_en PF FCI PF_FCO A lock detector can be enabled by setting LD_en 1 When pin LD is high it indicates that the PLL is in lock When entering TX the procedure is first to load the TX word and then turn on the PA stage During the PA ramp up time the LD signal may indicate out of lock It is first when the PA stage is fully on that the LD signal will indicate in Lock During transmission the Lock Detect signal will have transitions and the user should therefore ignore the Lock detect signal Modes of Operation A6 A0 D7 D6 D5 D4 D3 D2 Di DO 0000000 LNA by PA2 PA1 PAO Sync en Mode Mode0 t Mode1 ModeO State Comments 0 0 Power down Keeps register configuration 0 1 Standby Only crystal oscillator running 1 0 Receive Full receive 1 1 Transmit Full transmit ex PA state July 2006 13 MICRF620 MICRF620Z M9999 120205 Micrel Inc Transceiver Sync Non Synchronous Mode MICRF620 MICRF620Z A6 A0 D7 D6 D5 D4 D3 D2 D1 DO 0000000 LNA_by PA2 PA1 PAO Sync en Mode1 ModeO q 0000110 0 0 0 BitSync_clkS2 BitSync_clkS1 BitSync cIkSO BitRate_clkS2 0000111 BitRate_cikS1 BitRate_clkSO RefClk_K5 RefCIk K4 RefClk_K3 RefClk_K2
23. equency measured 200 us frequency offset 10kHz Switch Time Tx Rx same frequency time to good 350 us data Standby Rx 1 1 ms Standby Tx 1 1 ms Crystal Oscillator Start Up Time XCO_tune 13 750 us Transmit Section Rioap 500 Pa2 O0 111 10 dBm Output Power Roan 500 Pa2_0 001 8 dBm Over temperature range dB Output Power Tolerance Over power supply range dB gt Rioap 50Q PA2_0 111 23 mA Tx Current Consumption RioaD 500 PA2 O0 001 10 mA Tx Current Consumption Variation Rioap 500 PA2 0 111 2 5 mA Binary FSK Frequency Separation Limited by receiver BW 20 400 kHz Data Rate NRZ 0 20 kbps gt 19 2kbps p 9 85kHz 36dBm Occupied bandwidth RBW 10kHz kHz Harmonics 434 36 dBm Spurious Emission in Restricted b4 dBm bands 1GHz ETSI EN300 220 Spurious Emission 1GHz 36 dBm Spurious Emission gt 1GHz 30 dBm July 2006 M9999 120205 Micrel Inc MICRF620 MICRF620Z Parameter Condition Min Typ Max Units Receive Section All functions on 12 mA Rx Current Consumption NA RYP s me Switch cap filter bypass with LNA 9 6 mA Bypass of Switch cap and LNA mA Rx Current Consumption Variation Over temperature 3 mA 2 4 kbps p 16 SC 50 kHz 110 dBm 4 8 kbps B 16 SC 50 kHz 109 dBm Receiver Sensitivity BER 10 4 8 kbps p 4 SC 31 kHz 108 dBm 1
24. fax 1 408 474 1000 http www micrel com July 2006 M9999 120205 Micrel Inc MICRF620 MICRF620Z Contents General Description zia e nie beide d a t deed ede etus 1 EGatUI6s ots eit dite e diee dde e ode da eaa di tede i NN 1 Applications con erede retos ede dos ud eren eue de rodea Baro aded Maratea ta secre dane a id 1 CONS eot em cel it ed S d eoe ede dio ce dt o e ent es 2 RadioWire RF Module Selection Guide ds eii Str hse da dd aea rude M qa Rt s 3 Ordering Information coco ceto e a o cede ed id eos de e eee Sera duh rk du 3 Block Diagram o OP ee MP 3 PIN CONTIQUEAION cm 4 Pin Descrip 0 TL 4 Absolute Maximum Ratings esee deir rain eeu t et ciem rain Ee RE Repeat Aie e m needed a 5 Operating Ratings ces rne cec Cod iQ ML I CM MMC Lun d EM RPM E 5 Electrical Characteristics eu Rd RUE vu 5 Programimiliqgo ode a ME ME me eii e LN ELE 7 Generals ndo ated bonded ced E m M E 7 Writing to the Control Registers in MICRF620 aaaeei eKA A AARTE OEE EEKE AEAEE EEA EEEE 8 Writing to a SIngle REGIO ae NEA E E EET tU n IDEE 8 Writing to AllReglsters 3 e e REPRE er DE A e MUR 8 Writing to n Registers Having Incremental Addresses ssssssssssseseeeeeen nenne ener en nennen nennen 9 Reading from the Control Registers in MICRF620 sssssssssseseseeeeeenen eene enne nrnnen enne esent inen 9 Reading n Registers from MIGRF620 i inde arcas 9 Programming Iriterface Titlrig s tio et erret re e re RR e r
25. gh e Use SCLK and IO to clock in the 23 octets e Bring CS low Refer to the figure in the next section Writing to n registers having incremental addresses Writing to n Registers Having Incremental Addresses In addition to entering all bytes it is also possible to enter a set of n bytes starting from address i A6 A5 AO Typical example Clock in a new set of frequency dividers i e change the RF frequency Incremental addresses Registers to be written are located in i i 1 i 2 What to write Field Comments Address 7 bit A6 A5 A0 A6 msb AO Isb address of first byte to write to R W bit 0 for writing n 8 bits D7 D6 DO D7 msb DO Isb written to control reg with address i D7 D6 DO D7 msb DO Isb written to control reg with address i 1 D7 D6 DO D7 msb DO Isb written to control reg with Values address i n 1 Table 5 Address and R W bit together make 1 octet In addition n octets with programming bits are entered Totally 1 n octets are clocked into the MICRF620 How to write e Bring CS high e Use SCLK and IO to clock in the 1 n octets e Bring CS low In Figure 1 IO is changed at positive edges of SCLK The MICRF620 samples the lO line at negative edges The value of the R W bits is always 0 for writing cs 7 N six NN YT TCnc Ju 10 OXON KAO BW COT DC X D DT DO gt a a
26. ground pad on the bottom side the module will be assembled most efficient if the heat is being subjected to the bottom side of the PCB The heat will be transferred trough the PCB due the ground vias under the module see Layout Considerations In addition it is recommended to use a solder tip on the signal and power pads to make sure the solder points are properly melted July 2006 19 M9999 120205 Micrel Inc Layout Considerations Except for the antenna input output signal only digital and low frequency signals need to interface with the module There is therefore no need of years of RF expertise to do a successful layout as long as the following few points are being followed Proper ground is needed If the PCB is 2 layer the bottom layer should be kept only for ground Avoid signal traces that split the ground plane For a 4 layer PCB it is recommended to keep the second layer only for ground A ground via should be placed close to all the ground pins The bottom ground pad should be penetrated with 4 16 ground vias The antenna has an impedance of 50 ohm The antenna trace should be kept to 50 ohm to avoid signal reflection and loss of performance Any transmission line calculator can be used to find the needed trace width given a board build up Ex A trace width of 44 mil 1 12 mm gives 50 impedance on a FR4 board dielectric cons 4 4 with copper thickness of 35um and height layer 1 layer 2 spacing of 0 61 mm
27. itter Hz foev Single sided frequency deviation Baudrate The baud rate given is bit sec In battery operated applications that do not need very high selectivity the main channel filter can be bypassed by SC byz1 This will reduce the Rx current consumption with 2mA 15 M9999 120205 Micrel Inc RSSI A6 A0 D7 D6 D5 D4 D3 D2 D1 DO 0000001 1 0 o 0 RSSI en LD en PF FC1 PF FCO RSSI 33kohm 1nF 20kbps BW 200kHz Vdd 2 5V 2 25 2 E 1 75 gt 8 15 o 2 125 A iid 1 0 75 0 5 t t t i 120 110 100 90 80 70 60 50 Input power dBm Figure 10 RSSI Voltage A Typical plot of the RSSI voltage as function of input power is shown in Figure 10 The RSSI has a dynamic range of about 50dB from about 110dBm to 60dBm input power The RSSI can be used as a signal presence indicator When a RF signal is received the RSSI output increases This could be used to wake up circuitry that is normally in a sleep mode configuration to conserve battery life Another application for which the RSSI could be used is to determine if transmit power can be reduced in a system If the RSSI detects a strong signal it could tell the transmitter to reduce the transmit power to reduce current consumption A6 A0 D7 D6 D5 D4 D3 D2 Di DO 0010101 FEEC 3 FEEC2 FEEC1 FEECO 0010110 FEE 7 FEE 6 FEES FEE4 FEES FEE 2 FEE 1 FEE 0
28. led oscillator frequency fre Input output RF frequency There are two sets of each of the divide factors i e AO and A1 Storing the 0 and the 1 frequency in the 0 and the 1 registers respectively does the 2 FSK The receive frequency must be stored in the 0 registers Crystal Oscillator XCO Adr D7 D6 D5 D4 D3 D2 D1 DO 0001001 0 0 p XCOtune4 XCOtune3 XCOtune2 XCOtune1 XCOtuneO The crystal oscillator is a reference for the RF output frequency and the LO frequency in the receiver It is possible to tune the internal crystal oscillator by switching in internal capacitance using 5 tune bits XCOtune4 XCOtunO The benefit of tuning the crystal oscillator is to eliminate the initial tolerance and the tolerance over temperature and aging By using the crystal tuning feature the noise bandwidth of the receiver can be reduced and a higher sensitivity is achieved When XCOtune4 XCOtuneO 0 no internal capacitors are connected to the crystal pins When XCOtune4 XCOtuneO 1 all of the internal capacitors are connected to the crystal pins Figure 5 shows the tuning range July 2006 MICRF620 MICRF620Z ppm a o 8 12 16 20 24 28 32 XCO_tune value 0 4 Figure 5 XCO Tuning The typical start up time for the crystal oscillator default XCO_tune 13 is 750us If more capacitance is added higher XC
29. nd e The R W bit 1 to enable reading e Make the IO line an input to the user set pin in tristate e Read n octets The first rising edge of SCLK will set the lO as an output from the MICRF620 MICRF will change the IO line at positive edges The user should read the IO line at the negative edges e Make the IO line an output from the user again 9 M9999 120205 Micrel Inc MICRF620 MICRF620Z Programming Interface Timing Figure 4 and Table 6 show the timing specification for the 3 wire serial programming interface Tesr traise Tper Thigh Tread Twrite Tscl tfall Tlow SCLK cs E JAIVAS Address Register Data Register LOAD Figure 4 Programming Interface Timing Values Symbol Parameter Min Typ Max Units Tper Min period of SCLK Voltage dividers on IO lines will slow down the 50 ns write read frequency Thigh Min high time of SCLK 20 ns Tlow Min low time of SCLK 20 ns tfall Max time of falling edge of SCLK 1 us trise Max time of rising edge of SCLK 1 us Tcsr Max time of rising edge of CS to falling edge of SCLK 0 ns Tcsf Min delay from rising edge of CS to rising edge of SCLK 5 ns Twrite Min delay from valid IO to falling edge of SCLK during a write operation 0 ns Tread Min delay from rising edge of SCLK to valid IO during a read operation 75 ns assuming load capacitance of IO is 25pF Table 6 Timing Specification for the
30. or a MCU running at 3 0V and the MICRF620 at 2 5V July 2006 MICRF620 MICRF620Z MICRF6xx MCU cs SCLK DATAIXO lt gt DATACLK Figure 12 How to connect MICRF620 2 5V and MCU 3 0V 18 M9999 120205 Micrel Inc MICRF620 MICRF620Z Assembling the MICRF620 Layout Recommended Reflow Temperature Profile Recommended Land Pattern When the MICRF620 module is being automatically Figure 14 shows a recommended land pattern that assembled to a PCB care must be taken not to expose facilitates both automatic and hand assembling the module for temperature above the maximum specified Figure 13 shows the recommended reflow temperature d 10 50 mm profile m feed 4 50 mn C c 8 9 10 CON Peak temp E E 5 E 250 210 225 C 5sec 14 1 mm wn E dE 2 E 8 mM E Pre heat temp 72 4 187 E a 140 170 C 60 120sec T 1 80 mm 11 5 mm 5 08 mm Figure 14 Recommended Land Pattern TOP VIEW Figure 13 Recommended Reflow Temperature Reflow Shock Vibration during Reflow The module has several components inside which are assembled in a reflow process These components may reflow again when the module is assembled onto a PCB It is therefore important that the module is not subjected to any mechanical shock or vibration during this process Handassembling the MICRF620 It is recommended to use solder paste also during hand assembling of the module Because of the module
31. pacitor implementation of a six pole elliptic low pass filter The cut off frequency of the Sallen Key RC filter can be programmed to four different frequencies 100kHz 150kHz 230kHz and 350kHz The and Q channel outputs are demodulated and produce a digital data output The demodulator detects the relative phase of the and the Q channel signal If the channel signal lags behind the Q channel the FSK tone frequency is above the LO frequency data 1 If the channel leads the Q channel then the FSK tone is below the LO frequency data 0 The output of the receiver is available on the DatalXO pin A receive signal strength indicator RSSI circuit indicates the received signal level All support documentation can be found on Micrel s web site at www micrel com RadioWire is a trademark of Micrel Inc MICRF620 434MHz ISM Band Transceiver Module e RadioWire Module Features e Drop in RF solution e Small size 11 5x14 1mm e RF tested e Low Power e Surface Mountable e Tape amp Reel e Digital Bit Synchronizer e Received Signal Strength Indicator RSSI e RX and TX power management e Power down function e Register read back function Applications e Telemetry e Remote metering e Wireless controller e Remote data repeater e Remote control systems e Wireless modem e Wireless security system Micrel Inc 2180 Fortune Drive San Jose CA 95131 USA tel 1 408 944 0800
32. sitions on the SCLK line if the CS line is inactive The MICRF620 can be put on a bus sharing clock and data lines with other devices All control registers should be written to after a battery reset During operation it is sufficient to write to one register only The MICRF620 will automatically enter power down mode after a battery reset Address Data A6 A0 D7 D6 D5 D4 D3 D2 D1 DO 0000000 LNA by PA2 PA1 PAO Sync_en Mode1 ModeO q 0000001 al 0 0 0 RSSI en LD en PF FC1 PF FCO 0000010 0 SC_by 0 PA_by 0 0 0 0 0000011 q eL 0 VCO_IB2 VCO_IB1 VCO_IBO VCO freq1 VCO freqo 0000100 0 0 0 0 0 0 0 0 0000101 0 4 o 0 0 o 0000110 0 0 o BitSync clkS2 BitSync clkS1 BitSync clkSO BitRate_clkS2 0000111 BitRate cIkS1 BitRate clkSO RefCIk K5 RefClk_K4 RefCIk K3 RefClk_K2 RefCIk K1 RefCIk KO 0001000 4 Zu 0 ScClk4 ScClk3 ScClk2 ScCIk1 ScCIkO 0001001 0 0 4 XCOtune4 XCOtune3 XCOtune2 XCOtune1 XCOtuneO 0001010 A0 5 A0 4 A0 3 A0 2 AO 1 A0 0 0001011 NO 11 NO 10 NO 9 NO 8 0001100 NO 7 NO 6 NO 5 NO 4 NO 3 NO 2 NO 1 NO 0 0001101 MO 11 MO 10 MO 9 MO 8 0001110 MO 7 MO 6 MO 5 MO 4 MO 3 MO 2 MO 1 MO 0 0001111 A1 5 A14 A1 3 A12 A1 1 A1 0 0010000 N1 11 N1 10 N1 9 N1 8 0010001 N1 7 N1 6 N1 5 N1 4
33. t Figure 15 Package Dimensions Tape Dimensions 0005 Figure 16 Tape Dimensions MICREL INC 2180 FORTUNE DRIVE SAN JOSE CA 95131 USA TEL 1 408 944 0800 FAX 1 408 474 1000 WEB http www micrel com The information furnished by Micrel in this data sheet is believed to be accurate and reliable However no responsibility is assumed by Micrel for its use Micrel reserves the right to change circuitry and specifications at any time without notification to the customer Micrel Products are not designed or authorized for use as components in life support appliances devices or systems where malfunction of a product can reasonably be expected to result in personal injury Life support devices or systems are devices or systems that a are intended for surgical implant into the body or b support or sustain life and whose failure to perform can be reasonably expected to result in a significant injury to the user A Purchaser s use or sale of Micrel Products for use in life support appliances devices or systems is a Purchaser s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale O 2005 Micrel Incorporated July 2006 21 M9999 120205
34. t octet if there is one is written to the control register with address Address 1 and so on Table 2 Writing to the Control Registers How to write Bring CS active to start a write sequence The active state of the CS line is high Use the SCLK IO serial interface to clock Address and R W bit and Values into the MICRF620 MICRF620 will sample the IO line at negative edges of SCLK Make sure to change the state of the IO line before the negative edge Refer to figures below Bring CS inactive to make an internal load signal and complete the write sequence The two different ways to program the chip are e Write to a number of control registers 0 22 when the registers have incremental addresses write to 1 all or n registers e Write to a number of control registers when the registers have non incremental addresses Writing to a Single Register Writing to a control register with address A6 A5 A0 is described here During operation writing to 1 register is sufficient to change the way the transceiver works Typical example Change from receive mode to power down July 2006 MICRF620 MICRF620Z Field Comments Address 7 bit A6 A5 A0 A6 msb AO Isb R W bit 0 for writing Values 8 bits D7 D6 DO D7 msb DO Isb Table 3 Address and R W bit together make 1 octet In addition 1 octet with programming bits is entered
35. te ae Rte RPM 10 Power on Reset e de e et eet db t dec ies c e veiba Made tee e a Mee edv Med qute e qui a be inal 11 Programming Summiary 1 cete eee pete os eee Page de eee dt undies v Maece e ede es A ati sot pde de eee tib ende et eee ede ecd 11 Frequency SyntheSiZer EU 12 Crystal Oscillator XCO J sscec cc asccecet tices ce etu ee bigot ce tav bu v ende en ce eee ure ec iia ce ee abu dae ah aene nee 12 VEO ws EET 12 Lock Detect aos te ee e petes lee dies te O A laden a pee epe es Icey ind xe e dee bee v dented 13 Modes of OperatloD 2 Ln ur ebd Lee ad e bee eese a E ee ue ve epe t va du eL Bde ena uv lade ee 13 Transceiver Sync Non Synchronous Mode sssssssssssese eene eene en rra r enne en nennen nennen nns 14 Data Interface sis iie eerte eie ee ben a ecc tue eee ev obl wld dae epe Ve be e v ed dex Dd d e d ee t t e Head 14 ROGCIVER avi EE 14 Front Ehqd uit ete eee ben a oec ned e e e t wi ee ann wad Aedes wld wid 15 Sallen Key Filters iet eet ce ee nt ce etu diu e ence ve dne ceca et aed Devi eve diua e a deduce 15 Switched Capacltor FIlter ctt ete ardet te Rede Rt tte a b e tite redet dede EO ies 15 REEE EAA ete ah att Alana al ace lett a ates Lats cain dme A ce ln tania ence Ses acm tee 16 gl 16 Bit Synehronizer ene is 17 BIDUO TEE 17 Power Ampli o dee o ect t atte eiie De cedo mere 17 Frequency Modulationg ime Der Rute aee t cage lcm ce mio ini 17 Using the XCO tune BIIS in A EG eH Ee DE
36. two s complement of this value must be performed Only FEE modes where DN pulses are counted 10 and 11 will give a negative value When the FEE value has been read the frequency offset can be calculated as follows Mode UP Foffset R 2P x FEE AFp Mode DN Foffset R 2P x FEE AFp Mode UP DN Foffset R 4P x FEE where FEE is the value stored in the FEE register Fp is the single sided frequency deviation P is the no of symbols data bit counted and R is the symbol data rate A positive Foffset means that the received signal has a higher frequency than the receiver frequency To compensate for this the receivers XCO frequency should be increased It is recommended to use Mode UP DN for two reasons you do not need to know the actual frequency deviation and this mode gives the best accuracy 16 M9999 120205 Micrel Inc Bit Synchronizer MICRF620 MICRF620Z A6 A0 D7 D6 D5 D4 D3 D2 D1 DO 0000110 0 0 0 BitSync_clkS2 BitSync_clkS1 BitSync clkSO BitRate_clkS2 0000111 BitRate_clkS1 BitRate_clkSO RefCIk K5 RefClk_K4 RefClk_K3 RefClk_K2 RefClk_K1 RefClk_KO A bit synchronizer can be enabled in receive mode by selecting the synchronous mode Sync_en 1 The DataClk pin will output a clock with twice the frequency of the bit rate a bit rate of 20 kbit sec gives a DataClk of 20 kHz A received symbol bit on DatalXO will be output on rising edge of D
37. z 15 kbps 13 5mA 2 0 2 5 v 28 mA FSK 11 5x14 1 mm MICRF610Z Lead free MICRF610 MICRF620 430 440 MHz 20 kbps 12 0 mA 2 0 2 5 v 24 mA FSK 11 5x14 1 mm MICRF620Z Lead free MICRF620 RFB433B 430 440 MHz 19 2 kbaud 8 mA 2 5 3 4 V 42 mA FSK 1x1 RFB868B 868 870 MHz 19 2 kbaud 10 mA 2 5 3 4 V 50 mA FSK 1x1 RFB915B 902 928 MHz 19 2 kbaud 10 mA 2 5 3 4 V 50 mA FSK 1x1 Ordering Information Part Number Junction Temp Range Package MICRF620 TR 20 to 75 C 11 5 x 14 1mm MICRF620Z TR 20 to 75 C 11 5 x 14 1mm Block Diagram EM B Nes SCLK p Sallen key iter gt gt TA gt _ lt 194 EN LA zd o E d AE os l Si g 3 gt Sallen key an gt poa gt 5 Es LA oe 9 DATAIXO 8 9 p 3 amp ANT S tt m RSSI LDATACLK lt lt A we Ele gs Ee lt lt 5 E EE i POS _ lt la ID PS w Frequency Synthesiser Hf pe X YN Bias f X J AL y A QUE MICRF620 July 2006 3 M9999 120205 Micrel Inc Pin Configuration J NC i MICRF620 MICRF620Z VDD i CS GND f O SCLK ANT AJ lo GND I O DatalXO GND I DataCk e eh e Z US zi c MICRF620 TR 11 5 x 14 1 mm Top view Pin Description Pin Number Pin Name Type Pin Function 1 NC Not connected 2 NC Not connected 3 CS l Chip select three wire programming interface 4 SCLK l Clock three wire programming interface 5 IO 1 0 Data three wire programming interface 6 DATAI
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MICREL MICRF620 434MHz ISM Band Transceiver Module