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ATMEL 8-bit Flash Microcontroller with Full Speed USB Device AT89C5131A-L Manual

1. Polling Interrupt Interrupt Vector Number Priority Source Request Address 0 0 Reset 0000h 1 1 INTO IEO 0003h 2 2 Timer 0 TFO 000Bh 3 3 INT1 IE1 0013h 4 4 Timer 1 IF1 001Bh 5 6 UART RI TI 0023h 6 7 Timer 2 TF2 EXF2 002Bh 7 5 PCA 0 4 0033h 8 8 Keyboard KBDIT 003Bh 9 9 TWI TWIIT 0043h 10 10 SPI SPIIT 004Bh 11 11 0053h 12 12 005Bh 13 13 0063h 14 14 USB UEPINT USBINT 006Bh 15 15 0073h 4338F USB 08 07 189 5131 1 Keyboard Interface Introduction Description Interrupt 4338F USB 08 07 The AT89C5131A L implements a keyboard interface allowing the connection of a 8 x n matrix keyboard It is based on 8 inputs with programmable interrupt capability on both high or low level These inputs are available as an alternate function of P1 and allow to exit from idle and power down modes The keyboard interface communicates with the C51 core through 3 special function reg isters KBLS the Keyboard Level Selection register Table 70 KBE The Keyboard interrupt Enable register Table 69 and KBF the Keyboard Flag register Table 68 The keyboard inputs are considered as 8 independent interrupt sources sharing the same interrupt vector An interrupt enable bit KBD in IE1 allows global enable or dis able of the keyboard interrupt see Figure 40 As detailed in Figure 41 each keyboard input has the capability to detect a programmable level
2. 189 5131 1 4338F USB 08 07 Table 64 IEN1 Register IEN1 Interrupt Enable Register B1h 7 6 5 4 3 2 1 0 EUSB ESPI ETWI EKB Bit Bit Number Mnemonic Description 7 Reserved USB Interrupt Enable bit 6 EUSB Cleared to disable USB interrupt Set to enable USB interrupt 5 Reserved 4 Reserved 3 Reserved SPI interrupt Enable bit 2 ESPI Cleared to disable SPI interrupt Set to enable SPI interrupt TWI interrupt Enable bit 1 ETWI Cleared to disable TWI interrupt Set to enable TWI interrupt Keyboard interrupt Enable bit 0 EKB Cleared to disable keyboard interrupt Set to enable keyboard interrupt Reset Value XOXX X000b Not bit addressable ATMEL 81 82 AMEL Table 65 IPL1 Register IPL1 Interrupt Priority Register B2h 7 6 5 4 3 2 1 0 PUSBL PSPIL PTWIL PKBDL Bit Bit Number Mnemonic Description 7 _ Reserved The value read from this bit is indeterminate Do not set this bit USB Interrupt Priority bit PUSBL Refer to PUSBH for priority level 5 _ Reserved The value read from this bit is indeterminate Do not set this bit 4 5 Reserved The value read from this bit is indeterminate Do not set this bit 3 _ Reserved The value read from this bit is indeterminate Do not set this bit SPI Interrupt Priority bit FPE Re
3. 156 ONCE Mode ON Chip Emulation ee eeeeeen 157 EMI siae a 158 Electrical CharacteristiCsS 0cccccccsssssssssscssssssssssssensenseesssenneeees 159 Absolute Maximum Ratings tisnin iA a 159 DG Paratmelters 2 RN 159 USB DC 1 162 AC P rameterS 2 0 c 163 USB 173 SPI Interface AC Parameters 173 elei yiii 177 Packaging Information esee nevera sn da Saco ee vu cxUs 178 64 18 178 SPEI JRoeoT LM DEM 179 184 AT89C5131A L memm 189 5131 1 28 1884 50 180 Document Revision 181 Changes from 4338D 09 05 to 4338E 06 06 181 Changes from 4338E 06 06 to 4338F 08 07 181 AIMEL 185 4338F USB 08 07 AIMEL Atmel Corporation 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41
4. CRO CR1 and CR2 have no effect in the slave mode SSIE must be set to enable the TWI The AA bit must be set to enable the own slave address or the general call address acknowledgement STA STO and SI must be cleared When SSADR and SSCON have been initialised the TWI module waits until it is addressed by its own slave address followed by the data direction bit which must be at logic 0 W for the TWI to operate in the slave receiver mode After its own slave address and the W bit have been received the serial interrupt flag is set and a valid sta tus code can be read from SSCS This status code is used to vector to an interrupt service routine The appropriate action to be taken for each of these status code is detailed in Table The slave receiver mode may also be entered if arbitration is lost while TWI is in the master mode states 68h and 78h If the AA bit is reset during a transfer TWI module will return a not acknowledge logic 1 to SDA after the next received data byte While AA is reset the TWI module does not respond to its own slave address However the 2 wire bus is still monitored and address recognition may be resume at any time by setting AA This means that the AA bit may be used to temporarily isolate the module from the 2 wire bus In the slave transmitter mode a number of data bytes are transmitted to a master receiver Figure 55 Data transfer is initialized as in the slave receiver mode When
5. 36 gulis Em 36 Flash Programming and 36 Flash Registers and Memory 37 Flash Memory 40 Memory Organization nennen nennen ns 40 EEPROM Data 41 Bree Mte 41 Write Data in the Column 0 4000 41 Programming 41 lead re 41 42 In System Programming ISP 43 182 AT89C51 31 A L SSS eae 4338F USB 08 07 es 189 5131 1 Flash Programming and 43 2101616 s 44 Application Programming Intertace 2 enne 45 XROW Byles TEE 45 Hardware 45 On chip Expanded RAM 47 Dp goce 50 Auto reload Mode 50 Programmable Clock Output 51 Programmable Counter Array PCA 55 Capture M
6. Pulse Width Modulator Mode Before enabling ECOM bit CCAPnL and CCAPnH should be set with a non zero value otherwise an unwanted match could happen Once ECOM set writing CCAPnL will clear ECOM so that an unwanted match doesn t occur while modifying the compare value Writing to CCAPnH will set ECOM For this reason user software should write CCAPnL first and then CCAPnH Of course the ECOM bit can still be controlled by accessing to CCAPMnh register All of the PCA modules be used as PWM outputs Figure 33 shows the PWM func tion The frequency of the output depends on the source for the PCA timer All of the modules will have the same frequency of output because they all share the PCA timer The duty cycle of each module is independently variable using the module s capture register CCAPLn When the value of the PCA CL SFR is less than the value in the mod ule s CCAPLn SFR the output will be low when it is equal to or greater than the output will be high When CL overflows from FF to 00 CCAPLn is reloaded with the value in This allows updating the PWM without glitches The PWM and ECOM bits in the module s CCAPMn register must be set to enable the PWM mode 4338F USB 08 07 AT89C5131A L Figure 33 PCA PWM Mode CCAPnH Overflow CCAPnL g Enable M lt gt 8 bit Comparator gt f q
7. AMEL n Functional Description Operating Modes AMEL Figure 43 shows a detailed structure of the SPI module Figure 43 SPI Module Block Diagram Internal Bus Shift Register PERIPH Divider Fin MOSI 64 Control MISO Logic gt Clock gt IM Logic S SCK Clock gt SS A m nd M f SPR2 5 55015 MSTR CPOL CPHA SPR1 SPRO SPCON p SPI 8 bit bus SPI Interrupt Request Control 1 bit signal L SPSTA v SPIF WCOL SSERRMODF E 2 The Serial Peripheral Interface can be configured as one of the two modes Master mode or Slave mode The configuration and initialization of the SPI module is made through one register The Serial Peripheral CONtrol register SPCON Once the SPI is configured the data exchange is made using SPCON The Serial Peripheral STAtus register SPSTA The Serial Peripheral DATa register SPDAT During an SPI transmission data is simultaneously transmitted shifted out serially and received shifted in serially A serial clock line SCK synchronizes shifting and sam pling on the two serial
8. AT89C5131A L 1024 00h 3FFh The AT89C5131A L has on chip data memory which is mapped into the following four separate segments 1 The Lower 128 bytes of RAM addresses 00h to 7Fh are directly and indirectly addressable 2 The Upper 128 bytes of RAM addresses 80h to FFh are indirectly addressable only 3 The Special Function Registers SFRs addresses 80h to FFh are directly addressable only 4 The expanded RAM bytes are indirectly accessed by MOVX instructions and with the EXTRAM bit cleared in the AUXR register see Table 44 The lower 128 bytes can be accessed by either direct or indirect addressing The Upper 128 bytes can be accessed by indirect addressing only The Upper 128 bytes occupy the same address space as the SFR That means they have the same address but are physically separate from SFR space Figure 25 Internal and External Data Memory Address OFFh or 3FFh 00 4338F USB 08 07 OFFh OFFh OFFFFh Upper 128b tes Special External y F unction Dat Internal egister M direct accesses indirect accesses ERAM 80h 80h suh 7Fh ana e Lower 128 bytes Internal RAM direct or indirect accesses OOFFh up to OSFFh 7 00 0000 Depends on XRS1 0 AMEL 48 AMEL When an instruction accesses an internal location above address 7Fh the CPU knows whether the access is to the up
9. Table 23 Baud Rate Generator SFR s Mnemonic Add Name 7 6 5 4 3 2 1 0 BRL 9Ah Baud Rate Reload BDRCON 9Bh Baud Rate Control BRR TBCK RBCK SPD SRC AMEL n 4338F USB 08 07 Table 24 PCA 5 5 AMEL Mnemo nic Add Name 7 6 5 4 3 2 1 0 CCON D8h PCA Timer Counter Control CF CR 4 2 1 CCFO CMOD D9h PCA Timer Counter Mode CIDL WDTE CPS1 CPSO ECF CL E9h PCA Timer Counter Low byte CH F9h PCA Timer Counter High byte CCAPMO DAh PCA Timer Counter Mode 0 ECOMO CAPPO CAPNO MATO TOGO PWMO ECCFO CCAPM1 DBh PCA Timer Counter Mode 1 ECOM1 CAPP1 CAPN1 MAT1 TOG1 1 ECCF1 2 DCh Timer Counter Mode 2 ECOM2 CAPP2 CAPN2 MAT2 TOG2 PWM2 ECCF2 DDh Timer Counter Mode ECOM3 CAPP3 CAPN3 MAT3 TOG3 PWM3 ECCF3 CCAPM4 DEh PCA Timer Counter Mode 4 ECOM4 CAPP4 CAPN4 MAT4 TOG4 PWM4 ECCF4 CCAPOH PCA Compare Capture Module 0 H CCAPOH7 6 5 4 CCAPOH2 1 CCAPOHO CCAP1H FBh PCA Compare Capture Module 1 H CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP1H2 CCAP1H1 1 CCAP2H FCh PCA Compare Capture Module 2 H CCAP2H7 CCAP2H6 2 5 2 4 2 2 2 CCAP2H
10. 1 2the peripheral clock frequency e Timer 0 overflow e input on the pin P1 2 AMEL s Figure 28 Timer Counter AMEL To PCA modules 2 4 overflow It CLK PERIPH ore CH CL oe gt TO OVF 1 2 16 Bit Up Counter CMOD CIDL WDTE CPS1 50 0 09 Idle Y CR CCF4 CCF3 CCF2 CCF1 Table 48 CMOD Register CMOD PCA Counter Mode Register D9h 7 6 5 4 3 2 1 0 CIDL WDTE CPS1 CPSO ECF Bit Bit Number Mnemonic Description Counter Idle Control 7 CIDL Cleared to program the PCA Counter to continue functioning during idle Mode Set to program PCA to be gated off during idle Watchdog Timer Enable 6 WDTE Cleared to disable Watchdog Timer function on PCA Module 4 Set to enable Watchdog Timer function on PCA Module 4 5 2 Reserved The value read from this bit is indeterminate Do not set this bit 4 _ Reserved The value read from this bit is indeterminate Do not set this bit 3 _ Reserved The value read from this bit is indeterminate Do not set this bit 2 CPS1 PCA Count Pulse Select CPS1CPSO Selected PCA input 0 0 Interna
11. MOSI from Master MSB bit6 bit5 bit4 bit3 bit2 LSB MISO from Slave MSB 56 bit5 bit4 bit3 bit2 bit LSB T T T T f f f T k to Slave 1214 1 A 1 1 1 Capture point Figure 47 CPHA SS Timing MISO MOSI Byte 1 Byte 2 Bye3 X Master SS Slave SS CPHA 0 ES As shown in Figure 46 the first SCK edge is the MSB capture strobe Therefore the Slave must begin driving its data before the first SCK edge and a falling edge on the SS pin is used to start the transmission The SS pin must be toggled high and then low between each byte transmitted Figure 43 Figure 47 shows SPI transmission in which is 1 In this case the Master begins driving its MOSI pin on the first SCK edge Therefore the Slave uses the first SCK edge as a start transmission signal The SS pin can remain low between transmis sions Figure 42 This format may be preferable in systems having only one Master and only one Slave driving the MISO data line 189 5131 1 Error Conditions Mode Fault MODF Write Collision WCOL Overrun Condition Interrupts 4338F USB 08 07 The following flags in the SPSTA signal SPI error conditions Mode Fault error in Master mode SPI indicates that the level on the Slave Select SS pin is inconsistent with the actual mode of the device MODF is set to warn that there may have a multi m
12. CF CR CCF3 CCF2 CCF1 CCFO uos Xx PCA IT PCA Counter Timer Cex n CH CL Capture X i amp m CCAPnH CCAPnL ECOMn CAPPn CAPNn TOGn PWMn 0 to 4 OxDA to OxXDE 16 bit Software Timer Compare Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMnh register The PCA timer will be compared to the module s capture registers and when a match occurs an interrupt will occur if the CCFn CCON SFR and the ECCFn CCAPMn SFR bits for the module are both set see Figure 31 4338F USB 08 07 AT89C5131A L Figure 31 PCA Compare Mode and PCA Watchdog Timer Write to CCAPnL Reset Write to CCAPnH CCON CF CR CCF4 2 CCF1 CCFO 0 08 A PCA IT dt CCAPnH CCAPnL 1 0 Enable u y Match 16 bit Comparator RESET CH CL 25 gt PCA Counter Timer CCAPMn n 0 to 4 OxDA to OxDE MATn TOGn PWMn ECCFn High Speed Output Mode 4338F USB 08 07 CMOD OxD9
13. 40 to 485 C Vss OV Vec 3 3V RE 10 Load Capacitance for port 0 ALE and PSEN 60 pF Load for all other outputs 60 pF Table 114 Table 117 and Table 120 give the description of each AC symbols Table 115 Table 119 and Table 121 give for each range the AC parameter Table 116 Table 119 and Table 122 give the frequency derating formula of the AC parameter for each speed range description To calculate each AC symbols take the x value and use this value in the formula Example and 20 MHz Standard clock x 30ns 50 4T 170 ns Table 114 Symbol Description Symbol Parameter T Oscillator Clock Period ALE Pulse Width Tavel Address Valid to ALE TLLAX Address Hold after ALE ALE to Valid Instruction In ALE to PSEN Tepi PSEN Pulse Width Tay PSEN to Valid Instruction In Input Instruction Hold after PSEN Tpyiz Input Instruction Float after PSEN Address to Valid Instruction In PSEN Low to Address Float A MEL 163 164 AMEL Table 115 AC Parameters for a Fix Clock F 40 MHz Symbol Min Max Units T 25 ns Tiu 40 ns Tayi 10 ns Tu 10 ns Tuy 70 ns 15 ns 55 ns 35 ns 0 ns Tpxiz 18 ns
14. Read one byte Accumulator by executing MOVC A A DPTR with A 0 amp DPTR 0000h to FFFFh The following procedure is used to read the Extra Row space and is summarized in Figure 20 Map the Extra Row space by writing 02h in FCON register Read one byte Accumulator by executing MOVC A A DPTR with A 0 amp DPTR FF80h to FFFFh The following procedure is used to read the Hardware Security space and is summa rized in Figure 20 the Hardware Security space by writing 04h in FCON register Read the byte Accumulator by executing MOVC A A DPTR with A 0 amp DPTR 0000h Figure 20 Reading Procedure Flash Spaces Reading Flash Spaces Mapping FCON 00000xx0b Data Read DPTR Address ACC 0 Exec MOVC A A DPTR Erase Mode FCON 00h 4338F USB 08 07 X 189 5131 1 Registers 4338F USB 08 07 Table 36 FCON S D1h Flash Control Register 7 6 5 4 3 2 1 0 FPL3 FPL2 FPL1 FPLO FPS FMOD1 FMODO FBUSY Bit Bit Number Mnemonic Description Programming Launch Command Bits 7 4 FPL3 0 Write 5Xh followed by AXh to launch the programming according to FMOD1 0 see Table 35 Flash Map Program Space 3 FPS Set to map the column latch space in the data memory space Clear to re map the data memory space Flash Mode
15. Vioap 0 1 V Vioap 0 1 V A MEL 169 4338F USB 08 07 AMEL For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded Vop VoL level occurs gt 20 mA 170 89 5131 A L LUIHLLLEOLOG LLOL GLLEaeCLLh COCOULLLUALALAOLOL AOe OA O O V L L PLOOe 189 5131 1 Clock Waveforms Valid in normal clock mode In X2 mode XTAL2 must be changed to XTAL2 2 STATE4 STATES STATE6 STATE1 STATE2 STATES 5 4 STATES INTERNAL OCK 2 2 Pi 2 2 2 2 2 1 2 LI LILI LIU LU ee ALE THESE SIGNALS ARE NOT ACTIVATED DURING THE EXTERNAL PROGRAM MEMORY FETCH EXECUTION OF A MOVX INSTRUCTION PSEN PO 2110 2 7 2227 FLOA FLOAT 4 FLOAT P2 EXT INDICATES ADDRESS TRANSITIDNS READ CYCLE RD PCL OUT PROGRAM MEMORY 1 EXTERNAL WRITE CYCLE WR PCL OUT EYEN IF PROGRAM MEMORY 1 INTERNAL PO PCL OUT PROGRAM MEMORY 1 EXTERNAL P2 NDICATES DPH OR P2 SFR TO PCH TRANSITION PORT OPERATION MOV PORT SRC OLD DAT NEW DATA PO PINS SAMPLED PINS SAMPLED MOV DEST DEST PORT P1 P2 P1 P2 P3 PINS SAMPLED P1 P2 P3 PINS SAMPLED INCLUDES
16. 1 00 PERIPH O2 1 SPRO 10 1 peRIPH O4 110F 1k 128 1 11Reserved Reset Value 0001 0100b Not bit addressable The Serial Peripheral Status Register contains flags to signal the following conditions Data transfer complete Write collision Inconsistent logic level on SS pin mode fault error Table 75 describes the SPSTA register and explains the use of every bit in the register Table 75 SPSTA Register SPSTA Serial Peripheral Status and Control register 0 4 Table 1 7 6 5 4 3 2 1 0 SPIF WCOL SSERR MODF Bit Bit Number Mnemonic Description Serial Peripheral data transfer flag 7 SPIF Cleared by hardware to indicate data transfer is in progress or has been approved by a clearing sequence Set by hardware to indicate that the data transfer has been completed Write Collision flag Cleared by hardware to indicate that no collision has occurred or has been 6 WCOL approved by a clearing sequence Set by hardware to indicate that a collision has been detected Synchronous Serial Slave Error flag EGER Set by hardware when SS is de asserted before the end of a received data Cleared by disabling the SPI clearing SPEN bit in SPCON Mode Fault Cleared by hardware to indicate that the SS pin is at appropriate logic level or 4 MODF has been approved by a clearing sequence Set by hardware to indicate that the SS
17. CIDL CPS1 CPSO ECF 1 Only for Module 4 Before enabling ECOM bit CCAPnL and CCAPnH should be set with a non zero value otherwise an unwanted match could happen Writing to CCAPnH will set the ECOM bit Once ECOM set writing CCAPnL will clear ECOM so that an unwanted match doesn t occur while modifying the compare value Writing to CCAPnH will set ECOM For this reason user software should write CCAPnL first and then CCAPnH Of course the ECOM bit can still be controlled by accessing to CCAPMnh register In this mode the CEX output on port 1 associated with the PCA module will toggle each time a match occurs between the PCA counter and the module s capture registers To activate this mode the TOG MAT and ECOM bits in the module s CCAPMn SFR must be set see Figure 32 A prior write must be done to CCAPnL and CCAPnH before writing the bit AMEL Figure 32 PCA High speed Output Mode Write to CCAPnL Reset Write to CCAPnH Enable SUE Match 16 bit Comparator eee CF CR CCF4 CCF3 CCF2 CCF1 CCFO CCAPnH CCAPnL 0 0 CH CL CEXn PCA counter timer CCAPMn n 0 to 4 ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn OxDA to OxDE 1
18. USBE SUSPCLK SDRMWUP DETACH UPRSM RMWUPE CONFG FADDEN Bit Number Bit Mnemonic Description USBE USB Enable Set this bit to enable the USB controller Clear this bit to disable and reset the USB controller to disable the USB transceiver an to disable the USB controller clock inputs SUSPCLK Suspend USB Clock Set this bit to disable the 48 MHz clock input Resume Detection is still active Clear this bit to enable the 48 MHz clock input SDRMWUP Send Remote Wake Up Set this bit to force an external interrupt on the USB controller for Remote Wake UP purpose An upstream resume is send only if the bit RMWUPE is set all USB clocks are enabled AND the USB bus was in SUSPEND state for at least 5 ms See UPRSM below This bit is cleared by software DETACH Detach Command Set this bit to simulate a Detach on the USB line The Vgge pin is then floating state Clear this bit to maintain at high level UPRSM Upstream Resume read only This bit is set by hardware when SDRMWUP has been set and if RMWUPE is enabled This bit is cleared by hardware after the upstream resume has been sent RMWUPE Remote Wake Up Enable Set this bit to enabled request an upstream resume signaling to the host Clear this bit otherwise Note Do not set this bit if the host has not set the DEVICE REMOTE WAKEUP feature for the device CONFG Configured
19. will leave port floating AIMEL 153 Registers AMEL Table 108 PCON Register PCON S 87h Power Control Register SMOD1 1 GFO PD IDL Bit Number Bit Mnemonic Description SMOD1 Serial Port Mode bit 1 Set to select double baud rate in mode 1 2 or 3 SMODO Serial Port Mode bit 0 Set to select FE bit in SCON register Clear to select SMO bit in SCON register Reserved The value read from this bit is always 0 Do not set this bit POF Power Off Flag Set by hardware when rises from 0 to its nominal voltage Can also be set by software Clear to recognize next reset type GF1 General purpose Flag 1 Set by software for general purpose usage Cleared by software for general purpose usage GFO General purpose Flag 0 Set by software for general purpose usage Cleared by software for general purpose usage PD Power down mode bit Set this bit to enter in power down mode Cleared by hardware when reset occurs IDL Idle mode bit Set this bit to enter in Idle mode Cleared by hardware when interrupt or reset occurs Reset Value 10h 154 AT89C5131 A L 4338F USB 08 07 189 5131 1 Hardware Watchdog Timer Using the WDT 4338F USB 08 07 The WDT is intended as a recovery method in situations where the CPU may be sub jected to software upset The WDT consists of a 14 bit co
20. 7 TF2 Must be cleared by software Set by hardware on Timer 2 overflow if RCLK 0 and TCLK 0 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2 1 6 EXF2 When set causes the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt is enabled Must be cleared by software EXF2 doesn t cause an interrupt in Up down counter mode DCEN 1 Receive Clock bit for UART 5 RCLK Cleared to use Timer 1 overflow as receive clock for serial port in mode 1 or 3 Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3 Transmit Clock bit for UART 4 TCLK Cleared to use Timer 1 overflow as transmit clock for serial port in mode 1 or 3 Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3 Timer 2 External Enable bit 3 EXEN2 Cleared to ignore events on T2EX pin for Timer 2 operation Set to cause a capture or reload when a negative transition on T2EX pin is detected if Timer 2 is not used to clock the serial port Timer 2 Run control bit 2 TR2 Cleared to turn off Timer 2 Set to turn on Timer 2 Timer Counter 2 select bit 1 2 Cleared for timer operation input from internal clock system Foi Set for counter operation input from T2 input pin falling edge trigger Must be 0 for clock out mode Timer 2 Capture Reload bit If RCLK 1 or TCLK 1 CP RL2 is ignored and timer is forced to Auto reload on Timer 2 ove
21. Idle Mode Power down Mode AMEL An instruction that sets 0 indicates that it is the last instruction to be executed before going into the Idle mode In the Idle mode the internal clock signal is gated off to the CPU but not to the interrupt Timer and Serial Port functions The CPU status is preserved in its entirety the Stack Pointer Program Counter Program Status Word Accumulator and all other registers maintain their data during Idle The port pins hold the logical states they had at the time Idle was activated ALE and PSEN hold at logic high level There are two ways to terminate the Idle mode Activation of any enabled interrupt will cause 0 to be cleared by hardware terminating the Idle mode The interrupt will be serviced and following RETI the next instruction to be executed will be the one fol lowing the instruction that put the device into idle The flag bits GFO and GF1 can be used to give an indication if an interrupt occurred dur ing normal operation or during an Idle For example an instruction that activates Idle can also set one or both flag bits When Idle is terminated by an interrupt the interrupt service routine can examine the flag bits The other way of terminating the Idle mode is with a hardware reset Since the clock oscillator is still running the hardware reset needs to be held active for only two machine cycles 24 oscillator periods to complete the reset To save maximum pow
22. Power Fail Detect 20200150 Voltage Regulator 8 XTAL1 tr 1 RST pin gt Internal Reset PCA Hardware Watchdog Watchdog Note 1 Once XTAL1 High and low levels reach above and below VIH VIL 1024 clock period delay will extend the reset coming from the Power Fail Detect If the power falls below the Power Fail Detect threshold level the Reset will be applied immediately The Voltage regulator generates a regulated internal supply for the CPU core the mem ories and the peripherals Spikes on the external Vcc are smoothed by the voltage regulator 150 AT89C5131 A L 4338F USB 08 07 189 5131 1 The Power fail detect monitor the supply generated by the voltage regulator and gener ate a reset if this supply falls below a safety threshold as illustrated in the Figure 76 below Figure 76 Power Fail Detect Vcc Reset When the power is applied the Power Monitor immediately asserts a reset Once the internal supply after the voltage regulator reach a safety level the power monitor then looks at the XTAL clock input The internal reset will remain asserted until the Xtal1 lev els are above and below VIH and VIL Further more An internal counter will count 1024 clock periods before the reset is de asserted If the internal power supply falls below a safety level a reset is immediately asserted 4338F USB 08 07 A MEL 151 Power Management
23. Table 121 AC Parameters for a Fix Clock F 40 MHz Symbol Min Max Units Tax 300 ns Tavux 200 ns 30 ns 0 ns 117 ns Table 122 AC Parameters for a Variable Clock Standard X Parameter Symbol Type Clock X2 Clock for M Range Units Tx Min 12T 6T ns Tavux Min 10T x 5T x 50 ns 2 T x 20 ns Min X 0 ns Txupv Max 10T x 5T x 133 ns 168 AT89C5131 A L ULCUIUILL LA ROOOBLUL A L OULOOO L L 2 1RI 9 4338F USB 08 07 AT89C5131A L Shift Register Timing Waveform INSTRUCTION 9 1 2 3 4 5 6 7 8 ALE CLOCK OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI External Clock Drive Table 123 AC Parameters Characteristics XTAL1 Symbol Parameter Min Max Units Oscillator Period 21 ns Teucx High Time 5 ns Low Time 5 ns Teich Rise Time 5 ns TeucL Fall Time 5 ns Cyclic ratio in X2 mode 40 60 External Clock Drive Waveforms 0 5 0 45 Testing Input Output Waveforms Voc 0 5V INPUT OUTPUT 0 2 Voc 0 9 0 2 0 1 AC inputs during testing are driven at 0 5 for a logic 1 and 0 45V for a logic 0 Timing measurement are made at Vj min for a logic 1 and Vi max for a logic 0 Float Waveforms
24. This bit will be set by the device firmware after a SET CONFIGURATION request with a non zero value has been correctly processed It will be cleared by the device firmware when a SET CONFIGURATION request with a zero value is received It is cleared by hardware on hardware reset or when an USB reset is detected on the bus SEO state for at least 32 Full Speed bit times typically 2 7 us FADDEN Function Address Enable This bit will be set by the device firmware after a successful status phase of a SET ADDRESS transaction It will not be cleared afterwards by the device firmware It is cleared by hardware on hardware reset or when an USB reset is received see above When this bit is cleared the default function address is used 0 Reset Value 00h 136 AT89C5131 A L ULCUIUILL LA ROOOBLUL A L OULOOO L L 2 1RI 9 4338F USB 08 07 4338F USB 08 07 189 5131 1 Table 93 USBINT Register USBINT S BDh USB Global Interrupt Register 7 6 5 4 3 2 1 0 WUPCPU EORINT SOFINT SPINT Bit Bit Number Mnemonic Description 7 6 _ Reserved The value read from these bits is always 0 Do not set these bits Wake Up CPU Interrupt This bit is set by hardware when the USB controller is in SUSPEND state and is 5 WUPCPU re activated by a non idle signal FROM USB line not by an upstream resume
25. 400Kbit s SPI Interface Master Slave Mode 34 Pins 4 Direct drive LED Outputs with Programmable Current Sources 2 6 10 mA Typical 4 level Priority Interrupt System 11 sources Idle and Power down Modes 0 to 32 MHz On chip Oscillator with Analog PLL for 48 MHz Synthesis Industrial Temperature Range Low Voltage Range Supply 2 7V to 3 6V 3 0V to 3 6V required for USB Packages 5028 PLCC52 64 CERTIFIED Rev 4338F USB 08 07 AMEL Description AMEL AT89C5131A L is a high performance Flash version of the 80 51 single chip 8 bit microcontrollers with full speed USB functions AT89C5131A L features a full speed USB module compatible with the USB specifica tions Version 1 1 and 2 0 This module integrates the USB transceivers with a 3 3V voltage regulator and the Serial Interface Engine SIE with Digital Phase Locked Loop and 48 MHz clock recovery USB Event detection logic Reset and Suspend Resume and FIFO buffers supporting the mandatory control Endpoint EPO and up to 6 versatile Endpoints EP1 EP2 EP3 EP4 EP5 EP6 with minimum software overhead are also part of the USB module AT89C5131A L retains the features of the Atmel 80C52 with extended Flash capacity 32 Kbyte 256 bytes of internal RAM a 4 level interrupt system two 16 bit timer counters TO T1 a full duplex enhanced UART EUART and an on chip oscillator In addition AT89C5131A L has an on chip expanded RAM of 1024 bytes ERAM dua
26. 85 ns 10 ns Table 116 AC Parameters for a Variable Clock Standard Symbol Type Clock X2 Clock X Parameter Units Tiu Min 2T x T x 10 ns Tavel Min T x 0 5T x 15 ns TLLax Min T x 0 5 15 ns 4T x 2T x 30 ns T x 0 5T x 10 ns 3 1 5 20 ns 3 1 5T x 40 ns X 0 ns Tpxiz Max T x 0 5T x 7 ns 5 2 5 40 ns 10 ns 4338F USB 08 07 External Program Memory Read Cycle AT89C5131A L 12 Tie ALE 12125 E PSEN gt 2 gt ADDRESS PORLA OR SFR P2 ADDRESS 8 15 lt ADDRESS 8 15 External Data Memory Characteristics Symbol Table 117 Symbol Description Parameter LRH RD Pulse Width LWH WR Pulse Width LDV RD to Valid Data In Data Hold After RD Data Float After RD ALE to Valid Data In Address to Valid Data In ALE to WR or RD Address to WR or RD Data Valid to WR Transition Data set up to WR High Data Hold After WR RD Low to Address Float RD or WR High to ALE high 4338F USB 08 07 AMEL 165 166 Table 118 AC Parameters for a Variable Clock F 40 MHz AMEL Symbol Min Max Units TRL
27. AMEL Interrupt System Overview The AT89C5131A L has a total of 11 interrupt vectors two external interrupts INTO and INT1 three timer interrupts timers 0 1 and 2 the serial port interrupt SPI interrupt Keyboard interrupt USB interrupt and the PCA global interrupt These interrupts are shown in Figure 39 Figure 39 Interrupt Control System High priority 0 interrupt ITO 0 INTO IEO i TFO 2 1 5 0 Interrupt INT1 IE1 Polling Sequence Decreasing From High to Low Priority TF1 PCA IT RI nl gt TF2 EXF2 MC KBD IT TWI IT SPI IT USBINT UEPINT 19 Low Priority Individual Enable lobal Disable Interrupt 4338F USB 08 07 189 5131 1 Registers 4338F USB 08 07 Each of the interrupt sources can be individually enabled or disabled by setting or clear ing a bit in the Interrupt Enable register Table 61 This register also contains a global disable bit which must be cleared to disable all interrupts at once Each interrupt source can also be individually programmed to one out of four priority lev els by setting or clearing a bit in the Interrupt Priority register Table 62 and in the Interrupt Priority High register Table 63 Table 60 shows the bit values and priority lev els associated with each combination The PCA interrupt vector is located at
28. Case Postale 80 CH 1705 Fribourg Switzerland Tel 41 26 426 5555 Fax 41 26 426 5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Atmel Operations Memory 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 436 4314 Microcontrollers 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 436 4314 La Chantrerie BP 70602 44306 Nantes Cedex 3 France Tel 33 2 40 18 18 18 Fax 33 2 40 18 19 60 ASIC ASSP Smart Cards Zone Industrielle 13106 Rousset Cedex France Tel 33 4 42 53 60 00 RF Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn Germany Tel 49 71 31 67 0 Fax 49 71 31 67 2340 1150 East Cheyenne Mtn Blvd Colorado Springs CO 80906 USA Tel 1 719 576 3300 Fax 1 719 540 1759 Biometrics Imaging Hi Rel MPU High Speed Converters RF Datacom Avenue de Rochepleine BP 123 38521 Saint Egreve Cedex France Tel 33 4 76 58 30 00 Fax 33 4 76 58 34 80 Tel 852 2721 9778 Fax 33 4 42 53 60 01 Fax 852 2722 1369 1150 East Cheyenne Mtn Blvd Japan Colorado Springs CO 80906 USA 9F Tonetsu Shinkawa Bldg Tel 1 719 576 3300 1 24 8 Shinkawa Fax 1 719 540 1759 Chuo ku Tokyo 104 0033 Japan Scottish Enterprise Technology Park Tel 81 3 3523 3551 Building 81 3 3523 7581 East Kilbride G75 Scotland Tel 44 1355 803 0
29. It generates a square wave signal the PLL clock Figure 9 PLL Block Diagram and Symbol 14 OSC CLOCK _ PLLCON 1 PLLF PLLEN N divider Y Y U Vref PFLD gt VCO USB Clock r3 Down PLOCK R divider PLLCON O R3 0 lt USB CLOCK OSCcIk x 1 USBclk 1 USB Clock Symbol Figure 10 PLL Filter Connection PLLF D R e VSS NSS The typical values are 100 C1 10 nf 2 2 2 nF 4338F USB 08 07 189 5131 1 PLL Programming Divider Values 4338F USB 08 07 The PLL is programmed using the flow shown in Figure 11 As soon as clock generation is enabled user must wait until the lock indicator is set to ensure the clock output is stable Figure 11 PLL Programming Flow PLL Programming gt Configure Dividers N3 0 xxxxb R3 0 xxxxb Y Enable PLL PLLEN 1 PLL Locked LOCK 1 To generate a 48 MHz clock using the PLL the divider values have to be configured fol lowing the oscillator frequency The typical divider values are shown in Table 13 Table 13 Typical Divider Values Oscillator Frequency R 1 N 1 PLLDIV 3 MHz 16 1 6 2 8 1 70h 8 MHz 6 1 50h 12 MHz 4 1 30h 16 MHz 3 1 20h 18 MHz 8 3 72h 20 MHz 12 5 B4h 24 MHz 2 1
30. Pata byte will be transmitted and will be returned pac pyte received Last data byte will be transmitted and NOT ACK Data byte in SSDAT has been Load data byte or X 0 0 0 Will be E B8h transmitted NOT ACK has Data byte will be t itted and ACK will b been received Load data byte X 0 0 1 ata yte will be transmitted an will be received 112 AT89C5131 A L lt lt O 55 4338F USB 08 07 X 189 5131 1 Table 84 Status in Slave Transmitter Mode Continued Application Software Response Status Code SSCS Status of the 2 wire bus and 2 wire hardware To from SSDAT To SSCON STA STO SI AA Next Action Taken By 2 wire Software COh Data byte in SSDAT has been transmitted NOT ACK has been received No SSDAT action or 0 No SSDAT action or 0 No SSDAT action or 1 No SSDAT action 1 Switched to the not addressed slave mode no recognition of own SLA or GCA Switched to the not addressed slave mode own SLA will be recognised GCA will be recognised if GC logic 1 Switched to the not addressed slave mode no recognition of own SLA or GCA A START condition will be transmitted when the bus becomes free Switched to the not addressed slave mode own SLA will be recognised GCA will be recognised if GC logic 1 A START cond
31. SSADR and SSCON have been initialized the TWI module waits until it is addressed by its own slave address followed by the data direction bit which must be at logic 1 R for TWI to operate in the slave transmitter mode After its own slave address and the R bit A MEL 103 Miscellaneous States Notes AMEL have been received the serial interrupt flag is set and a valid status code can be read from SSCS This status code is used to vector to an interrupt service routine The appro priate action to be taken for each of these status code is detailed in Table The slave transmitter mode may also be entered if arbitration is lost while the TWI module is in the master mode If the AA bit is reset during a transfer the TWI module will transmit the last byte of the transfer and enter state COh or C8h the TWI module is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer Thus the mas ter receiver receives all 1 5 as serial data While AA is reset the TWI module does not respond to its own slave address However the 2 wire bus is still monitored and address recognition may be resume at any time by setting AA This means that the AA bit may be used to temporarily isolate the TWI module from the 2 wire bus There are two SSCS codes that do not correspond to a define TWI hardware state Table 85 These codes are discuss hereafter Status F8h indicates that no relevant information is avai
32. This triggers a USB interrupt when EWUPCPU is set in Table 94 on page 138 When receiving this interrupt user has to enable all USB clock inputs This bit will be cleared by software USB clocks must be enabled before End Of Reset Interrupt This bit is set by hardware when a End Of Reset has been detected by the USB 4 EORINT controller This triggers a USB interrupt when EEORINT is set see Figure 94 on page 138 This bit will be cleared by software Start of Frame Interrupt This bit is set by hardware when an USB Start of Frame PID SOF has been 3 SOFINT detected This triggers a USB interrupt when ESOFINT is set see Table 94 on page 138 This bit will be cleared by software 2 _ Reserved The value read from this bit is always 0 Do not set this bit 1 _ Reserved The value read from this bit is always 0 Do not set this bit Suspend Interrupt This bit is set by hardware when USB Suspend Idle bus for three frame 0 SPINT periods a J state for 3 ms is detected This triggers a USB interrupt when ESPINT is set in see Table 94 on page 138 This bit will be cleared by software BEFORE any other USB operation to re activate the macro Reset Value 00h AMEL 137 AMEL Table 94 USBIEN Register USBIEN S BEh USB Global Interrupt Enable Register 7 6 5 4 3 2 1 0 EWUPCPU EEORINT ESPINT ESOFINT Bit Number Bit Mnemonic Description Reserved s The value r
33. Two clock sources are available for CPU Crystal oscillator on X1 and X2 pins Up to 32 MHz External 48 MHz clock on X1 pin In order to optimize the power consumption the oscillator inverter is inactive when the PLL output is not selected for the USB device AMEL PLL PLL Description AMEL Figure 8 Crystal Connection The AT89C5131A L PLL is used to generate internal high frequency clock the USB Clock synchronized with an external low frequency the Peripheral Clock The PLL clock is used to generate the USB interface clock Figure 9 shows the internal structure of the PLL The PFLD block is the Phase Frequency Comparator and Lock Detector This block makes the comparison between the reference clock coming from the N divider and the reverse clock coming from the R divider and generates some pulses on the Up or Down signal depending on the edge position of the reverse clock The PLLEN bit in PLLCON register is used to enable the clock generation When the PLL is locked the bit PLOCK in PLLCON register see Figure 9 is set The CHP block is the Charge Pump that generates the voltage reference for the VCO by injecting or extracting charges from the external filter connected on PLLF pin see Figure 10 Value of the filter components are detailed in the Section DC Characteristics The VCO block is the Voltage Controlled Oscillator controlled by the voltage pro duced by the charge pump
34. f needed loop the three last instructions until the page is completely loaded Figure 17 Column Latches Loading Procedure Column Latches Loading Y Column Latches Mapping PS 1 Y Data Load DPTR Address ACC Data Exec MOVX QDPTR A Last Byte to load Data memory Mapping F Programming the Flash Spaces User The following procedure is used to program the User space and is summarized in Figure 18 Load data the column latches from address 0000h to 7 Disable the interrupts Launch the programming by writing the data sequence 50h followed by AOh in FCON register The end of the programming indicated by the FBUSY flag cleared Enable the interrupts Note 1 The last page address used when loading the column latch is the one used to select the page programming address AMEL 4338F USB 08 07 AMEL Extra Row The following procedure is used to program the Extra Row space and is summarized in Figure 18 Load data in the column latches from address FF80h to FFFFh Disable the interrupts Launch the programming by writing the data sequence 52h followed by A2h FCON register The end of the programming indicated by the FBUSY flag cleared Enable the interrupts Figure 18 Flash and Extra Row Programming Procedure Flash Spaces Programming Column Latches Loading see Figure 17 Y Dis
35. 1 2 Capacitance of I O Buffer 10 pF 25 lep Power down Current 100 3 0V lt Voc lt 3 6 V 0 4 2 5 Power Supply Current 22d 0 3 2 5 3 3V 00 lccwrite 0 8 2 15 Verpp Power Fail High Level Threshold 3 0 V 4338F USB 08 07 ATMEL 159 AMEL Symbol Parameter Min Typ Max Unit Test Conditions VerpM Power Fail Low Level Threshold 2 2 V Power fail hysteresis Vprpp 0 15 V Notes Operating is measured with all output pins disconnected XTALT driven with 5 ns see Figure 81 Vi Vss 0 5V Vin 0 5 XTAL2 N C EA RST Port 0 Vec lcc would be slightly higher if a crystal oscillator used see Figure 78 2 Idle is measured with all output pins disconnected XTAL1 driven with To 5 ns Vi Vss 0 5V Vin Voc 0 5V XTAL2 N C Port 0 Voc EA RST Vss see Figure 79 _ 3 Power down is measured with all output pins disconnected EA PORT 0 Voc XTAL2 NC RST Vss see Fig ure 80 In addition the WDT must be inactive and the POF flag must be set 4 Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vo s of ALE and Ports 1 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pi
36. 101 c 104 gie c C EE 114 A MEL 183 4338F USB 08 07 USB Controllef e EP scc 116 Brie 116 101010 119 Read Write Data FIFO 121 Bulk Interrupt 122 Control Transactiolls iet teet e epe Re 126 Isochronous nnn nnn nnn 127 MiSCellaneOUs ME 129 Suspend Resume 130 Detach Simulation sccis 133 USB Interrupt Systemi teers date toc aree De rh cu d dp ree state 133 USB Registers cornrne 136 121 2 1 Me 148 ecc E 148 EE 148 Reset Output tra arat 149 150 150 Power 152 VAS em 152 Power down 152 gie 154 Hardware Watchdog Timer 155 Using the WOT Em 155 WDT During Power down and Idle
37. 20 acknowledge bits From slave to master This number contained in SSCS corresponds to a defined state of the 2 wire bus A MEL 107 4338F USB 08 07 AMEL Table 82 Status in Master Receiver Mode Application software response Status Status of the Two To SSCON Code wire Bus and Two SSSTA wire Hardware To From SSDAT SSSTA SSSTO SSI SSAA Next Action Taken by Two wire Hardware ogh A START condition has Write SLA R X 0 0 X SLA R will be transmitted been transmitted A repeated START Write SLA R 0 0 X SLA R will be transmitted 10h condition has been transmitted Write SLA W X 0 0 X SLA W will be transmitted Logic will switch to master transmitter mode Two wire bus will be released and not addressed 38h 2 x slave mode will be entered bit No SSDAT action 1 0 0 X A START condition will be transmitted when the bus becomes free SLA R has been No SSDAT action 0 0 0 0 Data byte will be received and NOT ACK will be 40h transmitted ACK has returned been received No SSDAT action 0 0 0 1 Data byte will be received and ACK will be returned SLA R has b 5 dies n E 2 d SSSTO fl R has been condition will be transmitted an ag 48h transmitted NOT SSDAT action o 0 X will be reset has been received STOP condition followed by a START condition will No SSDAT action L be transmitted a
38. Bits 20095 Decoder i SSCS Status Register 100 AT89C5131 A L 189 5131 1 Description 4338F USB 08 07 The CPU interfaces to the 2 wire logic via the following four 8 bit special function regis ters the Synchronous Serial Control register SSCON Table 86 the Synchronous Serial Data register SSDAT Table 87 the Synchronous Serial Control and Status reg ister SSCS Table 88 and the Synchronous Serial Address register SSADR Table 89 SSCON is used to enable the TWI interface to program the bit rate see Table 79 to enable slave modes to acknowledge or not a received data to send a START or a STOP condition on the 2 wire bus and to acknowledge a serial interrupt A hardware reset disables the TWI module SSCS contains a status code which reflects the status of the 2 wire logic and the 2 wire bus The three least significant bits are always zero The five most significant bits con tains the status code There are 26 possible status codes When SSCS contains F8h no relevant state information is available and no serial interrupt is requested A valid sta tus code is available in SSCS one machine cycle after SI is set by hardware and is still present one machine cycle after SI has been reset by software to Table 85 give the status for the master modes and miscellaneous states SSDAT contains a byte of serial data to be tra
39. Defined but generally the MSB of the character which has just been received Figure 85 SPI Slave Waveforms 1 5 input SCK CPOL 0 input SCK CPOL 1 input MISO output MOSI input Note 1 Not Defined but generally the LSB of the character which has just been received A MEL 175 4338F USB 08 07 AMEL Figure 86 SPI Master Waveforms SSCPHA 0 55 output SCK aH Torch CPOL 0 output SCK CPOL 1 output MISO output Port Data Port Data Note 1 SShandled by software using general purpose port pin Figure 87 SPI Master Waveforms SSCPHA 1 ss output SCK CPOL 0 output SCK CPOL 1 output MOSI input MISO Port Data MSB OUT are LSB OUT Port Data SS handled by software using general purpose port pin 176 AT89C5131A L X 189 5131 1 Ordering Information Table 129 Possible Order Entries Part Number Memory Size Kbytes Supply Voltage Temperature Range Package Packing AT89C5131A RDTIL 32 3 0 to 3 6V Industrial VQFP64 Tray AT89C5131A S3SIL 32 3 0 to 3 6V Industrial PLCC52 Stick AT89C5131A TISIL 32 3 0 to 3 6V Industrial 028 Stick AT89C5131A RDTUL 32 3 0 to 3 6V Industrial amp Green VQFP64
40. P3 6 RST Vo Reset Holding this pin low for 64 oscillator periods while the oscillator is running resets the device The Port pins are driven to their reset conditions when a voltage lower than is applied whether or not the oscillator is running This pin has an internal pull up resistor which allows the device to be reset by connecting a capacitor between this pin and VSS Asserting RST when the chip is in Idle mode or Power down mode returns the chip to normal operation This pin is set to 0 for at least 12 oscillator periods when an internal reset occurs hardware watchdog or Power monitor ALE Address Latch Enable Output The falling edge of ALE strobes the address into external latch This signal is active only when reading or writing external memory using MOVX instructions PSEN Program Strobe Enable Hardware conditions Input for ISP Used as input under reset to detect external hardware conditions of ISP mode External Access Enable This pin must be held low to force the device to fetch code from external program memory starting at address 0000h It is latched during reset and cannot be dynamically changed during operation AMEL 10 AMEL Table 12 Power Signal Description Signal Alternate Name Type Description Function Alternate Ground AVSS GND avgs is used to supply the on chip PLL and the USB PAD Alternate Supply Voltage AVDD PWR
41. P3 6 and P3 7 as write and read timing signals Accesses to ERAM above OFFH can only be done by the use of DPTR e With EXTRAM 1 MOVX Ri MOVX DPTR will be similar to the standard 80C51 MOVX at Ri will provide an eight bit address multiplexed with data on Porto and any output port pins can be used to output higher order address bits This is to provide the external paging capability MOVX DPTR will generate a sixteen bit address Port2 outputs the high order eight address bits the contents of DPH while 0 multiplexes the low order eight address bits DPL with data MOVX at Ri and MOVX DPTR will generate either read or write signals on P3 6 WR and P3 7 RD The stack pointer SP may be located anywhere in the 256 bytes RAM lower and upper RAM internal data memory The stack may not be located in the ERAM The MO bit allows to stretch the ERAM timings if MO is set the read and write pulses are extended from 6 to 30 clock periods This is useful to access external slow peripherals es 189 5131 1 4338F USB 08 07 Table 45 AUXR Register AUXR Auxiliary Register BEh 7 6 5 4 3 2 1 0 DPU MO XRS1 XRSO EXTRAM AO Bit Bit Number Mnemonic Description Disable Weak Pull Up 7 DPU Cleared to enabled weak pull up on standard Ports Set to disable weak pull up on standard Ports 2 Reserved The value read from this bit is indeterminate Do not
42. PLOCK Bit Bit Number Mnemonic Description 7 3 Reserved The value read from this bit is always 0 Do not set this bit External 48 MHz Enable Bit 2 EXT48 Set this bit to bypass the PLL and disable the crystal oscillator Clear this bit to select the PLL output as USB clock and to enable the crystal oscillator PLL Enable Bit 1 Setto enable the PLL Clear to disable the PLL PLL Lock Indicator 0 PLOCK Set by hardware when PLL is locked Clear by hardware when PLL is unlocked Reset Value 0000 00006 Table 17 PLLDIV S A4h PLL Divider Register 7 6 5 4 3 2 1 0 R3 R2 R1 RO N3 N2 N1 NO Bit Bit Number Mnemonic Description 7 4 R3 0 PLL R Divider Bits 3 0 N3 0 PLL N Divider Bits Reset Value 0000 0000 AMEL SFR Mapping 18 AMEL The Special Function Registers SFRs of the 89 5131 1 fall into the following categories C51 core registers ACC B DPH DPL PSW SP I O port registers PO P2 P4 Timer registers T2CON T2MOD TCON THO TH1 TH2 TMOD TLO TL1 TL2 RCAP2L RCAP2H Serial I O port registers SADDR SADEN SBUF SCON PCA Programmable Counter Array registers CCON CMOD CL CH CCAPXL x 0 to 4 Power and clock control registers PCON Hardware Watchdog Timer registers WDTRST WDTPRG Interrupt system registers IENO IPLO I
43. Packet see Bulk Interrupt IN Transactions in Standard Mode on page 124 To send a STALL handshake see STALL Handshake on page 129 e Control Read transaction the status stage consists of a OUT Zero Length Packet see Bulk Interrupt OUT Transactions in Standard Mode on page 122 126 AT89C5131 A L 4338F USB 08 07 189 5131 1 Isochronous Transactions Isochronous OUT Transactions in Standard Mode Isochronous OUT Transactions in Ping pong Mode 4338F USB 08 07 An endpoint will be first enabled and configured before being able to receive Isochro nous packets When a OUT packet is received on an endpoint the RXOUTBO bit is set by the USB controller This triggers an interrupt if enabled The firmware has to select the corre sponding endpoint store the number of data bytes by reading the UBYCTLX and UBYCTHX registers If the received packet is ZLP Zero Length Packet the UBYCTLX and UBYCTHX register values are equal to 0 and no data has to be read The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in FIFO has a corrupted CRC This bit is updated after each new packet receipt When all the endpoint FIFO bytes have been read the firmware will clear the RXOUTBO bit to allow the USB controller to store the next OUT packet data into the endpoint FIFO Until the RXOUTBO bit has been cleared by the firmware the data sent by the Host at each OUT tran
44. SCK SPI Serial Clock SCK 10 16 SCK outputs clock to the slave peripheral or receive clock from the master lO MOSI SPI Master Output Slave Input line MOSI When SPI is in master mode MOSI outputs data to the slave peripheral P1 7 When SPI is in slave mode MOSI receives data from the master controller 7 4338F USB 08 07 AMEL AMEL Table 8 Ports Signal Description Signal Name Type Description Alternate Function Port 0 is an 8 bit open drain bidirectional port Port 0 7 lO pins that have 1s written to them float and can be used AD 7 0 as high impedance inputs To avoid any parasitic current consumption Floating PO inputs must be pulled to Vpp or Vas KIN 7 0 Pond T2 1 V9 P1 is 8 bit bidirectional I O port with internal pull ups jor CEX 4 0 Port 2 2 7 0 VO po is 8 bit bidirectional l O port with internal pull ups 5 8 LED 3 0 RxD TxD 3 0 7 0 VO 55isan8 bit bidirectional l O port with internal pull ups INTI TO Ti WR RD Port 4 SCL P4 1 0 nm P4 is an 2 bit open port SDA Table 9 Clock Signal Description Signal Alternate Name Type Description Function Input to the on chip inverting oscillator amplifier XTAL1 To use the internal oscillator crystal resonator circuit is connected to this pin If an external oscillator is used its output is connected to this pin Out
45. Start of Frame Interrupt See USBIEN Register USBIEN S BEh USB Global Interrupt Enable Register on page 138 This bit is set by hardware when a USB Start of Frame packet has been received WUPCPU Wake Up CPU Interrupt See USBIEN Register USBIEN S BEh USB Global Interrupt Enable Register on page 138 This bit is set by hardware when a USB resume is detected on the USB bus after a SUSPEND state SPINT Suspend Interrupt See USBIEN Register USBIEN S BEh USB Global Interrupt Enable Register on page 138 This bit is set by hardware when USB suspend is detected on the USB bus 4338F USB 08 07 AT89C5131A L Figure 71 USB Interrupt Control Block Diagram Endpoint X X 0 6 TXCMP 0 RXOUTBO UEPSTAX 1 1 UEPSTAX 6 RXSETUP 2 STLCRC UEPSTAX 3 WUPCPU USBINT 5 22 WUPCP etg USBIEN 5 ED EPXINT ra UEPINT X 4 Hi E o EORINT USBINT 4 EEORINT 4 RE T SOFINT 3 ESOFINT USBIEN 3 SPINT USBINT O ESPINT 0 AIMEL 135 4338F USB 08 07 USB Registers AMEL Table 92 USBCON Register USBCON S BCh USB Global Control Register 7 6 5 4 3 2 1 0
46. The firmware has to select the cor responding endpoint store the number of data bytes by reading the UBYCTLX and UBYCTHX registers If the received packet is a ZLP Zero Length Packet the UBYCTLX and UBYCTHX register values are equal to 0 and no data has to be read When all the endpoint FIFO bytes have been read the firmware will clear the RXOUTBO bit to allow the USB controller to accept the next OUT packet on this endpoint Until the RXOUTBO bit has been cleared by the firmware the USB controller will answer a NAK handshake for each OUT requests If the Host sends more bytes than supported by the endpoint FIFO the overflow data won t be stored but the USB controller will consider that the packet is valid if the CRC is correct and the endpoint byte counter contains the number of bytes sent by the Host 122 AT89C5131 A L ULCUIUILL LA ROOOBLUL A L OULOOO L L 2 1RI 9 4338F USB 08 07 189 5131 1 Bulk Interrupt OUT Transactions in Ping pong Mode 4338F USB 08 07 Figure 63 Bulk Interrupt OUT Transactions in Ping pong Mode HOST O UR C51 OUT n Bytes ACK RXOUTBO Endpoint FIFO Bank 0 Read Byte 1 Endpoint FIFO Bank 0 Read Byte 2 OUT m Bytes ACK Endpoint FIFO Bank
47. This number contained SSCS corresponds to a defined state of the 2 wire bus AMEL Any number of data bytes and their associated AT89C5131A L 109 AMEL Table 83 Status in Slave Receiver Mode Application Software Response Status To from SSDAT To SSCON Code Status of the 2 wire bus and SSCS 2 wire hardware STA STO SI AA Next Action Taken By 2 wire Software Own SLA W has been No SSDAT action or 0 0 0 7 will be received and will be 60h received ACK has been returned No SSDAT action x 0 0 1 Data byte will be received will be returned Arbitration lost in SLA R W as No SSDAT action or X 0 0 0 Data byte will be received and NOT ACK will be 68h master own SLA W has been returned received ACK has been Data byte will be received will be returned No SSDAT action X 0 0 1 returned Data byte will b ived and NOT ACK will b General call address has been SSDAT action or X 0 0 0 ud eye 70h received ACK has been returned No SSDAT action 0 0 1 Data byte will be received will be returned Arbitration lost in SLA R W as No SSDAT action X 0 0 0 Data byte will be received and NOT ACK will be 78h master general call address returned has been received ACK has Data byte will be received and ACK will be been returned No SSDAT action x 0 9 1 returned Previously addressed with No SSDAT
48. USB controller will store only the remaining bytes into the FIFO When new OUT packet is received on the endpoint bank 1 the RXOUTB 1 bit is set by the USB controller This triggers an interrupt if enabled The firmware empties the bank 1 endpoint FIFO before clearing the RXOUTB1 bit Until the RXOUTB1 bit has been cleared by the firmware the data sent by the Host on the bank 1 endpoint FIFO will be lost The RXOUTBO RXOUTB1 bits are alternatively set by the USB controller at each new packet receipt The firmware has to clear one of these two bits after having read all the data FIFO to allow a new packet to be stored in the corresponding bank A MEL 127 Isochronous Transactions in Standard Mode Isochronous IN Transactions in Ping pong Mode AMEL If the Host sends more bytes than supported by the endpoint FIFO the overflow data won t be stored but the USB controller will consider that the packet is valid if the CRC is correct An endpoint will be first enabled and configured before being able to send Isochronous packets The firmware will fill the FIFO with the data to be sent and set the TXRDY bit in the UEP STAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning this endpoint If the TXRDY bit is not set when the IN request occurs nothing will be sent by the USB controller When the IN packet has been sent the TXCMPL bit in the UEPSTAX register is set
49. USBINT BDh USB Global Interrupt WUPCPU EORINT SOFINT SPINT USBIEN BEh 22 Interrupt EWUPCPU EEORINT ESOFINT ESPINT UEPNUM C7h USB Endpoint Number EPNUM3 EPNUM2 EPNUM1 EPNUMO UEPCONX D4h USB Endpoint X Control EPEN DTGL EPDIR EPTYPE1 EPTYPEO UEPSTAX CEh USB Endpoint X Status DIR RXOUTB1 STALLRQ TXRDY STLCRC RXSETUP RXOUTBO TXCMP UEPRST D5h USB Endpoint Reset EP6RST EP5RST EP4RST EP3RST EP2RST EP1RST EPORST UEPINT F8h USB Endpoint Interrupt EP6INT EPAINT EPSINT EP2INT EP1INT EPOINT 4338F USB 08 07 AMEL 23 AMEL Table 30 USB SFR s Mnemonic Add 7 6 5 4 3 2 1 0 UEPIEN EP4INTE EP2INTE EPOINTE UEPDATX USB Endpoint X FIFO Data FDAT7 FDAT6 5 FDAT3 FDAT2 FDAT1 FDATO UBYCTLX E2h 7 Byte Counter Low EP savory BYCT6 BYCT5 BYCT4 BYCT3 BYCT2 BYCTO UBYCTHX E3h Counter nigh BYCT10 9 8 UFNUML BAh USB Frame Number Low 7 FNUM6 FNUMS 4 FNUM3 FNUM2 FNUM1 FNUMO UFNUMH BBh USB Frame Number High 3 CRCOK CRCERR FNUM10 FNUM9 8 Table 31 Other 5 5 Mnemonic Add Name 7 6 5 4 3 2 1 0 PCON 87h Power Control SMOD 1 SMODO POF GF1 GFO PD IDL AUXR 8Eh Auxiliary Register 0 DPU 0 XRS1 XRS2 EX
50. Value 00h A MEL 145 4338F USB 08 07 146 AMEL Table 104 UEPIEN Register UEPIEN S C2h USB Endpoint Interrupt Enable Register 6 5 4 3 2 1 0 EP6INTE EPSINTE EP4INTE 2 EP1INTE EPOINTE Bit Number Bit Mnemonic Description Reserved The value read from this bit is always 0 Do not set this bit EP6INTE Endpoint 6 Interrupt Enable Set this bit to enable the interrupts for th Clear this bit to disable the interrupts for is endpoint this endpoint EPSINTE Endpoint 5 Interrupt Enable Set this bit to enable the interrupts for thi Clear this bit to disable the interrupts for s endpoint this endpoint EP4INTE Endpoint 4 Interrupt Enable Set this bit to enable the interrupts for thi Clear this bit to disable the interrupts for s endpoint this endpoint Endpoint 3 Interrupt Enable Set this bit to enable the interrupts for thi Clear this bit to disable the interrupts for s endpoint this endpoint EP2INTE Endpoint 2 Interrupt Enable Set this bit to enable the interrupts for thi Clear this bit to disable the interrupts for s endpoint this endpoint EP1INTE Endpoint 1 Interrupt Enable Set this bit to enable the interrupts for thi Clear this bit to disable the interrupts for s endpoint this endpoint EPOINTE E
51. When set causes the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt is enabled Must be cleared by software EXF2 doesn t cause an interrupt in Up down counter mode DCEN 1 Receive Clock bit 5 RCLK Cleared to use Timer 1 overflow as receive clock for serial port in mode 1 or 3 Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3 Transmit Clock bit 4 TCLK Cleared to use Timer 1 overflow as transmit clock for serial port in mode 1 or 3 Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3 Timer 2 External Enable bit 3 EXEN2 Cleared to ignore events on T2EX pin for Timer 2 operation Set to cause a capture or reload when a negative transition on T2EX pin is detected if Timer 2 is not used to clock the serial port Timer 2 Run control bit 2 TR2 Cleared to turn off Timer 2 Set to turn on Timer 2 Timer Counter 2 select bit 1 2 Cleared for timer operation input from internal clock system Set for counter operation input from T2 input pin falling edge trigger Must be 0 for clock out mode Timer 2 Capture Reload bit If RCLK 1 or TCLK 1 2 is ignored and timer is forced to Auto reload on Timer 2 overflow 9 Dew Cleared to Auto reload on Timer 2 overflows or negative transitions on T2EX pin if 2 1 Set to capture on negative transitions on T2EX pin if EXEN2 1 Reset Value 0000 0000b Bit addre
52. and F400h when bit ENBOOT is set in 32 Kbytes AUXR1 register Flash Memory User Space FMO 0000h The Flash memory is made up of 4 blocks see Figure 16 1 The memory array user space 32 Kbytes 2 The Extra Row 3 The Hardware security bits 4 The column latch registers This space is composed of a 32 Kbytes Flash memory organized in 256 pages of 128 bytes It contains the user s application code This row is a part of FMO and has a size of 128 bytes The extra row contains informa tion for bootloader usage see Table 39 Software Registers page 39 The hardware security space is a part of FMO and has a size of 1 byte The 4 MSB can be read written by software The 4 LSB can only be read by software and written by hardware in parallel mode The column latches also part of FMO have a size of full page 128 bytes The column latches are the entrance buffers of the three previous memory locations user array XRow and Hardware security byte The CPU interfaces to the Flash memory through the FCON register and AUXR1 register These registers are used to Map the memory spaces in the adressable space Launch the programming of the memory spaces Get the status of the Flash memory busy not busy e Select the Flash memory FMO FM1 By default the user space is accessed by MOVC instruction for read only The column latches space is made accessible by setting the FPS bit in FCON register Writing is possible f
53. by the USB controller This triggers a USB interrupt if enabled The firmware will clear the TXCMPL bit before filling the endpoint FIFO with new data The firmware will never write more bytes than supported by the endpoint FIFO An endpoint will be first enabled and configured before being able to send Isochronous packets The firmware will fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning the endpoint The FIFO banks are automatically switched and the firmware can immediately write into the endpoint FIFO bank 1 If the TXRDY bit is not set when the IN request occurs nothing will be sent by the USB controller When the IN packet concerning the bank 0 has been sent the TXCMPL bit is set by the USB controller This triggers a USB interrupt if enabled The firmware will clear the TXC MPL bit before filling the endpoint FIFO bank 0 with new data The FIFO banks are then automatically switched When the IN packet concerning the bank 1 has been sent the TXCMPL bit is set by the USB controller This triggers a USB interrupt if enabled The firmware will clear the TXC MPL bit before filling the endpoint FIFO bank 1 with new data The bank switch is performed by the USB controller each time the TXRDY bit is set by the firmware Until the TXRDY bit has been set by the firmware for an endpoint bank the USB contr
54. chip EEPROM memory block is located at addresses 0000h to OSFFh of the ERAM memory space and is selected by setting control bits in the EECON register A read in the EEPROM memory is done with a MOVX instruction A physical write in the EEPROM memory is done in two steps write data in the column latches and transfer of all data latches into an EEPROM memory row programming The number of data written on the page may vary from 1 to 128 bytes the page size When programming only the data written in the column latch is programmed and a ninth bit is used to obtain this feature This provides the capability to program the whole mem ory by bytes by page or by a number of bytes in a page Indeed each ninth bit is set when the writing the corresponding byte in a row and all these ninth bits are reset after the writing of the complete EEPROM row Write Data in the Column Data is written by byte to the column latches as for an external RAM memory Out of the Latches 11 address bits of the data pointer the 4 MSBs are used for page selection row and 7 are used for byte selection Between two EEPROM programming sessions all the addresses in the column latches must stay on the same page meaning that the 4 MSB must not be changed The following procedure is used to write to the column latches Set bit EEE of EECON register Load with the address to write Store A register with the data to be written e Execute a MOVX DPTR A f ne
55. e FMOD1 0 See Table 34 or Table 35 Flash Busy Set by hardware when programming is in progress 0 FBUSY EM Clear by hardware when programming is done Can not be cleared by software Reset Value 0000 0000b ATMEL 5 AMEL Flash EEPROM Memory General Description Features Flash Programming and Erasure The Flash memory increases EPROM functionality with in circuit electrical erasure and programming It contains 32 Kbytes of program memory organized in 256 pages of 128 bytes respectively This memory is both parallel and serial In System Programmable ISP ISP allows devices to alter their own program memory in the actual end product under software control A default serial loader bootloader program allows ISP of the Flash The programming does not require 12V external programming voltage The necessary high programming voltage is generated on chip using the standard Voc pins of the microcontroller Flash EEPROM internal program memory Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space This configuration provides flexibility to the user Default loader in Boot EEPROM allows programming via the serial port without the need of a user provided loader Up to 64K bytes external program memory if the internal program memory is disabled EA 0 Programming and erase voltage with standard power supply Read Program Erase Byte wise read w
56. edges on which the output data are shifted Figure 45 and Figure 46 The clock phase and polarity should be identical for the Master SPI device and the com municating Slave device 1 The SPI module should be configured as a Master before it is enabled SPEN set Also the Master SPI should be configured before the Slave SPI 2 The SPI module should be configured as a Slave before it is enabled SPEN set 3 The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed 4 Before writing to the CPOL and bits the SPI should be disabled SPEN 0 AMEL Figure 45 Data Transmission Format 0 SCK cycle number 1 2 3 4 5 6 7 8 SPEN internal 211 SCK CPOL 0 N SCK CPOL 1 MOSI from Master MSB bit6 bit5 bit4 bit3 bit2 bit SB MISO from Slave bits bit4 bit3 bit2 bit SB 55 to Slave ES T y A4 C d C d Capture Figure 46 Data Transmission Format CPHA 1 SCK cycle number 1 2 3 4 5 6 7 8 SPEN internal SCK CPOL 0 1 1 1 1 1 1 1 SCK CPOL 1 IN
57. has Write SLA W X 0 0 X SLA W will be transmitted A repeated START Write SLA W x 0 0 X SLA W will be transmitted SLA R will be transmitted Wile SEARA 9 9 Logic will switch to master receiver mode Write data byte 0 0 0 X Data byte will be transmitted 51 Ad has been No SSDAT action 1 0 0 X Repeated START will be transmitted 18h transmitted has No SSDAT action 0 1 0 X STOP condition will be transmitted and SSSTO flag uM a ine followed by a START cond ll condition followed by condition wi 1 be transmitted and SSSTO flag will be reset Write data byte 0 0 0 X Data byte will be transmitted BAGNI been No SSDAT action 1 0 0 X Repeated START will be transmitted 20h transmitted No SSDAT action 0 1 0 STOP condition will be transmitted and SSSTO flag followed by a START conditi ill condition followed by condition wi No SSDAT 9 5 be transmitted and SSSTO flag will be reset Write data byte 0 0 0 X Data byte will be transmitted Data byte h s been No SSDAT action 1 0 0 X Repeated START will be transmitted 28h transmitted has No SSDAT action 0 1 0 X STOP condition will be transmitted and SSSTO flag id followed by a START conditi ill condition followed by condition wi 9 be transmitted and SSSTO flag will be reset Write data byte 0 0 0 X Data byte will be transmitted Daia byte has No SSD
58. is set again and a number of 102 AT89C5131 A L erieLLLLSLELLLL OAOeOO l P PP AAA 4338F USB 08 07 189 5131 1 Slave Receiver Mode Slave Transmitter Mode 4338F USB 08 07 status code in SSCS are possible There are 40h 48h or 38h for the master mode and also 68h 78h or BOh if the slave mode was enabled 1 The appropriate action to be taken for each of these status code is detailed in Table This scheme is repeated until a STOP condition is transmitted SSIE CR2 1 and are not affected by the serial transfer and are referred to Table 7 to Table 11 After a repeated START condition state 10h the TWI module may switch to the master transmitter mode by loading SSDAT with SLA W In the slave receiver mode a number of data bytes are received from a master transmit ter Figure 54 To initiate the slave receiver mode SSADR and SSCON must be loaded as follows Table 78 SSADR Slave Receiver Mode Initialization A6 5 4 2 1 0 GC own slave address The upper 7 bits are the address to which the TWI module will respond when addressed by a master If the LSB GC is set the TWI module will respond to the general call address 00h otherwise it ignores the general call address Table 79 SSCON Slave Receiver Mode Initialization CR2 SSIE STA STO SI AA CR1 CRO bit rate 1 0 0 0 1 bit rate bit rate
59. is set by the USB controller This triggers a USB interrupt if enabled The firmware will clear the TXCMPL bit before filling the endpoint FIFO bank 1 with new data The bank switch is performed by the USB controller each time the TXRDY bit is set by the firmware Until the TXRDY bit has been set by the firmware for an endpoint bank the USB controller will answer a NAK handshake for each IN requests concerning this bank Note that in the example above the firmware clears the Transmit Complete bit TXC MPL before setting the Transmit Ready bit TXRDY This is done in order to avoid the firmware to clear at the same time the TXCMPL bit for bank 0 and the bank 1 The firmware will never write more bytes than supported by the endpoint FIFO A MEL 125 4338F USB 08 07 Control Transactions Setup Stage Data Stage Control Endpoint Direction Status Stage AMEL The DIR bit in the UEPSTAX register will be at 0 Receiving Setup packets is the same as receiving Bulk Out packets except that the RXSETUP bit in the UEPSTAX register is set by the USB controller instead of the RXOUTBO bit to indicate that an Out packet with a Setup PID has been received on the Control endpoint When the RXSETUP bit has been set all the other bits of the UEP STAX register are cleared and an interrupt is triggered if enabled The firmware has to read the Setup request stored in the Control endpoint FIFO before clearing the RXSETUP bit to free the
60. line 1 Level Selection bit Cleared to enable a low level detection on Port line 1 Set to enable a high level detection on Port line 1 KBLSO Keyboard line 0 Level Selection bit Cleared to enable a low level detection on Port line 0 Set to enable a high level detection on Port line 0 Reset Value 0000 00000 189 5131 1 Programmable LED 4338F USB 08 07 AT89C5131A L have up to 4 programmable LED current sources configured by the register LEDCON Table 71 LEDCON Register LEDCON S F1h LED Control Register 7 6 5 4 3 2 1 0 LED3 LED2 LED1 LEDO Bit Bit Number Mnemonic Description PortLED3Configuration 0 OStandard C51 Port 7 6 LED3 0 12 current source when P3 7 is low 1 04 mA current source when P3 7 is low 1 110 current source when P3 7 is low Port LED2Configuration 0 OStandard C51 Port 5 4 LED2 0 12 current source when P3 6 is low 1 04 mA current source when P3 6 is low 1 110 mA current source when P3 6 is low Port LED1Configuration 0 OStandard C51 Port 3 2 LED1 0 12 current source when P3 5 is low 1 04 mA current source when P3 5 is low 1 110 current source when P3 5 is low Port LEDOConfiguration 0 OStandard C51 Port 1 0 LEDO 0 12 current source when P3 3 is low 1 04 mA current source when P3 3 is low 1 110 mA current source when P3 3 is low Reset Value 00h ATMEL Serial Peripheral In
61. mode e The TOG bit CCAPMn 2 when set causes the output associated with the module to toggle when there is a match between the PCA counter and the module s capture compare register match bit MAT CCAPMn 3 when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module s capture compare register next two bits CAPN CCAPMn 4 and CAPP CCAPMn 5 determine the edge that a capture input will be active on The CAPN bit enables the negative edge and 4338F USB 08 07 189 5131 1 the CAPP bit enables the positive edge If both bits are set both edges will be enabled and a capture will occur for either transition The last bit in the register ECOM CCAPMn 6 when set enables the comparator function Table 51 shows the settings for the various functions Table 50 CCAPMn Registers n 0 4 CCAPMO PCA Module 0 Compare Capture Control Register ODAh 1 Module 1 Compare Capture Control Register ODBh 2 PCA Module 2 Compare Capture Control Register ODCh Module 3 Compare Capture Control Register ODDh CCAPM4 PCA Module 4 Compare Capture Control Register ODEh 7 6 5 4 3 2 1 0 ECOMn CAPPn CAPNn MATn TOGn Bit Bit Number Mnemonic Description Reserved The value read from this bit is indeterminate D
62. package A MEL 181 4338F USB 08 07 POU vi 1 192160121479 P A 2 Block E 3 m 4 4 rs cs 6 P 11 Recommended External 11 Recommandations 12 Glock vessciascsssvarsiusseressssiivssctdeateriseladneuddaisssstubundsd tivandasddavines 13 mtr EE 13 5 13 pim tie ere 14 aij c 16 SFR 18 Dual Data Pointer Register 25 Program Code Memory ecce reser rere eee a eaae anna neas nnn nnn ru annua 27 External Code Memory Access nennen enne 27 Flash Memory 28 Overview of FMO Operations esssssssssesesee eene 29 35 Flash 36 General 4
63. rates Configure the SPI module as Master or Slave Selects serial clock polarity and phase Enables the SPI module Frees the SS pin for a general purpose Table 74 describes this register and explains the use of each bit Table 74 SPCON Register 7 6 5 4 3 2 1 0 SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPRO Bit Number Bit Mnemonic Description 7 SPR2 Serial Peripheral Rate 2 Bit with SPR1 and SPRO define the clock rate Serial Peripheral Enable 6 SPEN Cleared to disable the SPI interface Set to enable the SPI interface SS Disable 5 SSDIS Cleared to enable SS in both Master and Slave modes Set to disable SS in both Master and Slave modes In Slave mode this bit has no effect if CPHA 0 Serial Peripheral Master 5 MSTR Cleared to configure the SPI as a Slave Set to configure the SPI as a Master Clock Polarity 4 CPOL Cleared to have the SCK set to 0 in idle state Set to have the SCK set to 1 in idle state Clock Phase Cleared to have the data sampled when the SCK leaves the idle state see 3 CPHA CPOL Set to have the data sampled when the SCK returns to idle state see CPOL 4338F USB 08 07 X 189 5131 1 Serial Peripheral Status Register SPSTA 4338F USB 08 07 Number Bit Mnemonic Description SPR2 SPR1 SPRO Serial Peripheral Rate 2 SPR1 000 001 PERIPH 010 Ferk PERIPH 011 1 1 6
64. set this bit Pulse length Cleared to stretch MOVX control the RD and the WR pulse length is 6 clock 5 MO periods default Set to stretch MOVX control the RD and the WR pulse length is 30 clock periods d Reserved The value read from this bit is indeterminate Do not set this bit 3 XRS1 ERAM Size XRS1XRSO ERAM size 0 0 256 bytes 2 XRSO 0 1 512 bytes 1 0 768 bytes 1 1 1024 bytes default EXTRAM bit EN 1 EXTRAM Cleared to access internal ERAM using MOVX at Ri at DPTR Set to access external memory ALE Output bit AO Cleared ALE is emitted at a constant rate of 1 6 the oscillator frequency or 0 1 3 if X2 mode is used default Set ALE is active only when a MOVX or MOVC instruction is used Reset Value 0 0 1100b Not bit addressable AMEL 49 2 Auto reload Mode AMEL The Timer 2 in the AT89C5131A L is the standard C52 Timer 2 It is a 16 bit timer counter the count is maintained by two cascaded eight bit timer registers TH2 and TL2 It is controlled by T2CON Table 46 2 Table 47 registers Timer 2 operation is similar to Timer 0 and Timer 1 C T2 selects Fosc 12 timer operation or external pin T2 counter operation as the timer clock input Setting TR2 allows TL2 to be incremented by the selected input Timer 2 has 3 operating modes capture auto reload and Baud Rate Generator These modes are selected by the combination of RCLK TCLK and CP RL2 T2CO
65. triggers an interrupt if enabled The firmware empties the bank 1 endpoint FIFO before clearing the RXOUTB1 bit Until the RXOUTB 1 bit has been cleared by the firmware the USB controller will answer a NAK handshake for each OUT requests on the bank 1 endpoint FIFO The RXOUTBO and RXOUTB1 bits are alternatively set by the USB controller at each new valid packet receipt The firmware has to clear one of these two bits after having read all the data FIFO to allow a new valid packet to be stored in the corresponding bank handshake is sent by the USB controller only if the banks 0 and 1 has not been released by the firmware If the Host sends more bytes than supported by the endpoint FIFO the overflow data won t be stored but the USB controller will consider that the packet is valid if the CRC is correct AIMEL 123 AMEL Bulk Interrupt IN Transactions Figure 64 Bulk Interrupt IN Transactions in Standard Mode in Standard Mode HOST UFI C51 Endpoint FIFO Write Byte 1 IN Endpoint FIFO Write Byte 2 i Endpoint FIFO Write Byte Set TXRDY DATAO n Bytes ACK TXCMPL Bp Clear TXCMPL Endpoint FIFO Write Byte 1 An endpoint will be first enabled and configured before being able to send Bulk or Inter rupt packets The firmware will fill the FIFO with t
66. warm reset doesn t affect the value of this bit 4338F USB 08 07 es 189 5131 1 4338F USB 08 07 Table 59 BDRCON Register BDRCON Baud Rate Control Register 9Bh 6 5 4 3 2 1 0 BRR TBCK RBCK SPD SRC Bit Mnemonic Description Reserved The value read from this bit is indeterminate Do not set this bit Reserved The value read from this bit is indeterminate Do not set this bit Reserved The value read from this bit is indeterminate Do not set this bit BRR Baud Rate Run Control bit Cleared to stop the internal Baud Rate Generator Set to start the internal Baud Rate Generator TBCK Transmission Baud rate Generator Selection bit for UART Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator Set to select internal Baud Rate Generator RBCK Reception Baud Rate Generator Selection bit for UART Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator Set to select internal Baud Rate Generator SPD Baud Rate Speed Control bit for UART Cleared to select the SLOW Baud Rate Generator Set to select the FAST Baud Rate Generator SRC Baud Rate Source select bit in Mode 0 for UART Cleared to select Fosc 12 as the Baud Rate Generator in X2 mode Set to select the internal Baud Rate Generator for UARTs in mode 0 Reset Value XXX0 0000b Not bit addressable ATMEL 75
67. 0 Read Byte i Clear RXOUTB1 OUT DATAO p Bytes ____ Endpoint FIFO Bank 1 Read Byte 1 ACK Endpoint FIFO Bank 1 Read Byte 2 i Endpoint FIFO Bank 1 Read Byte m Clear RXOUTB1 RXOUTBO Endpoint FIFO Bank 0 Read Byte 1 Endpoint FIFO Bank 0 Read Byte 2 Endpoint FIFO Bank 0 Read Byte p Clear RXOUTBO An endpoint will be first enabled and configured before being able to receive Bulk or Interrupt packets When a valid OUT packet is received on the endpoint bank 0 the RXOUTBO bit is set by the USB controller This triggers an interrupt if enabled The firmware has to select the corresponding endpoint store the number of data bytes by reading the UBYCTLX and UBYCTHX registers If the received packet is ZLP Zero Length Packet the UBYCTLX UBYCTHX register values are equal to 0 and no data has to be read When all the endpoint FIFO bytes have been read the firmware will clear the RXOUBO bit to allow the USB controller to accept the next OUT packet on the endpoint bank 0 This action switches the endpoint bank 0 and 1 Until the RXOUTBO bit has been cleared by the firmware the USB controller will answer a NAK handshake for each OUT requests on the bank 0 endpoint FIFO When a new valid OUT packet is received on the endpoint bank 1 the RXOUTB1 bit is set by the USB controller This
68. 00 Fax 44 1355 242 743 Literature Requests www atmel com literature Disclaimer The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI TIONS OF SALE LOCATED ON ATMEL S WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically providedot herwise Atmel products are not suitable for and shall not be used in automotive applications Atmel sAtmel s produ
69. 1 2 FDh Compare Capture Module 3 H CCAP3H7 CCAP3H6 5 4 CCAP3H2 1 PCA Compare Capture Module 4 H CCAP4H7 CCAP4H6 CCAP4H5 CCAP4H4 2 CCAP4H1 4 CCAPOL EAh PCA Compare Capture Module 0 L CCAPOL7 CCAPOL6 CCAPOLS5 CCAPOL4 CCAPOL3 CCAPOL2 CCAPOL1 CCAPOLO CCAP1L PCA Compare Capture Module 11 CCAP1L7 CCAP1L6 CCAP1L5 CCAP1L4 CCAP1L3 CCAP1L2 CCAP1L1 CCAP1LO CCAP2L PCA Compare Capture Module 2 L CCAP2L7 216 215 214 CCAP2L3 CCAP2L2 CCAP2L1 CCAP2L0 CCAP3L EDh PCA Compare Capture Module 3 L CCAP3L7 6 CCAP3L5 CCAP3L4 CCAP3L2 CCAP3L1 CCAP4L EEh PCA Compare Capture Module 4 L CCAP4L7 CCAP4L6 CCAP4L5 CCAP4L4 CCAP4L3 CCAP4L2 CCAP4L1 CCAP4LO Table 25 Interrupt SFR s Mnemo nic Add Name 7 6 5 4 3 2 1 0 IENO A8h Interrupt Enable Control 0 EA EC 2 5 1 IEN1 Bih Interrupt Enable Control 1 EUSB ESPI ETWI EKB IPLO B8h Interrupt Priority Control Low 0 PPCL PT2L PSL PT1L PX1L PTOL PXOL IPHO B7h Interrupt Priority Control High 0 PPCH PT2H PSH PT1H PX1H PTOH PXOH IPL1 B2h Interrupt Priority Control Low 1 PUSBL PSPIL PTWIL PKBL IPH1 B3h Interrupt Priority Control High 1 PUSBH PSPIH PTWIH PKBH Table 26 PLL SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 PLL
70. 10h 32 MHz 3 2 21h 40 MHz 12 10 B9h AMEL AMEL Registers Table 14 CKCONO S 8Fh Clock Control Register 0 7 6 5 4 3 2 1 0 TWIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Bit Number Mnemonic Description TWI Clock This control bit is validated when the CPU clock X2 is set When X2 is low 7 TWIX2 this bit has no effect Clear to select 6 clock periods per peripheral clock cycle Set to select 12 clock periods per peripheral clock cycle Watchdog Clock This control bit is validated when the CPU clock X2 is set When X2 is low 6 WDX2 this bit has no effect Clear to select 6 clock periods per peripheral clock cycle Set to select 12 clock periods per peripheral clock cycle Programmable Counter Array Clock This control bit is validated when the CPU clock X2 is set When X2 is low 5 2 this bit has no effect Clear to select 6 clock periods per peripheral clock cycle Set to select 12 clock periods per peripheral clock cycle Enhanced UART Clock Mode 0 and 2 This control bit is validated when the CPU clock X2 is set When X2 is low 4 SIX2 this bit has no effect Clear to select 6 clock periods per peripheral clock cycle Set to select 12 clock periods per peripheral clock cycle Timer2 Clock This control bit is validated when the CPU clock X2 is set When X2 is low 3 T2X2 this bit has no effect Clear to select 6 clock periods per periphera
71. 2 114 AT89C5131A L 4338F USB 08 07 189 5131 1 Bit Bit Number Mnemonic Description 1 SD1 Address bit 1 or Data bit 1 0 SDO Address bit 0 R W or Data bit 0 Table 88 SSCS 094h Read Synchronous Serial Control and Status Register 7 6 5 4 3 2 1 0 504 503 502 561 5 0 0 0 0 Bit Bit Number Mnemonic Description 0 0 Always zero 1 0 Always zero 2 0 Always zero Status Code bit 0 3 See Table 81 to Table 85 it 1 4 SC1 Status Code bit See Table 81 to Table 85 Status Code bit 2 See Table 81 to Table 85 Status Code bit 3 9 See Table 81 to Table 85 Status Code bit 4 f PET See Table 81 to Table 85 Table 89 SSADR 096h Synchronous Serial Address Register read write 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 Bit Bit Number Mnemonic Description 7 7 Slave address bit 7 6 A6 Slave address bit 6 5 A5 Slave address bit 5 4 A4 Slave address bit 4 3 Slave address bit 3 2 A2 Slave address bit 2 1 A1 Slave address bit 1 General call bit 0 GC Clear to disable the general call address recognition Set to enable the general call address recognition 4338F USB 08 07 AMEL 115 USB Controller Description AMEL The USB devi
72. 2 1 0 Reset Value 0000 0000b SBUF Serial Buffer Register for UART 99h 7 6 5 4 3 2 1 0 Reset Value XXXX XXXXb AMEL Example of computed value when X2 1 SMOD1 1 SPD 1 16 384 MHz 24 MHz Baud Rates BRL Error BRL Error 115200 247 1 23 243 0 16 57600 238 1 23 230 0 16 38400 229 1 23 217 0 16 28800 220 1 23 204 0 16 19200 203 0 63 178 0 16 9600 149 0 31 100 0 16 4800 43 1 23 Example of computed value when X2 0 SMOD1 0 SPD 0 16 384 MHz 24 MHz Baud Rates BRL Error BRL Error 4800 247 1 23 243 0 16 2400 238 1 23 230 0 16 1200 220 1 23 202 3 55 600 185 0 16 152 0 16 The baud rate generator can be used for mode 1 or 3 refer to Figure 37 but also for mode 0 for UART thanks to the bit SRC located in BDRCON register Table 59 4338F USB 08 07 4338F USB 08 07 189 5131 1 BRL Baud Rate Reload Register for the internal baud rate generator UART 9Ah 7 6 5 4 3 2 1 0 Reset Value 0000 0000b Table 57 T2CON Register T2CON Timer 2 Control Register C8h 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 Bit Bit Number Mnemonic Description Timer 2 overflow Flag
73. 2L registers Enter a 16 bit initial value in timer registers TH2 TL2 It can be the same as the reload value or a different one depending on the application e start the timer set TR2 run control bit in T2CON register AMEL s 4338F USB 08 07 52 AMEL It is possible to use Timer 2 as a baud rate generator and a clock generator simulta neously For this configuration the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers Figure 27 Clock out Mode C T2 0 6 Ferk PERIPH 1109 2 H TR2 T2CON TL2 TH2 8 bit 8 bit OVERFLOW RCAP2L RCAP2H 8 bit 8 bit Toggle lt 2 T2MOD Timer 2 p EXF2 gt INTERRUPT T2CON T2CON 4338F USB 08 07 es 189 5131 1 Table 46 T2CON Register T2CON Timer 2 Control Register C8h 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 Bit Bit Number Mnemonic Description Timer 2 overflow Flag 7 TF2 Must be cleared by software Set by hardware on Timer 2 overflow if RCLK 0 and TCLK 0 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2 1 6 EXF2
74. 338F USB 08 07 As detailed in Section Hardware Watchdog Timer page 155 the WDT generates a 96 clock period pulse on the RST pin In order to properly propagate this pulse to the rest of the application in case of external capacitor or power supply supervisor circuit a 1 resistor must be added as shown Figure 74 Figure 74 Recommended Reset Output Schematic VDD RST gt RST HE g 89 5131 To other VSS on board circuitry A MEL 149 Power Monitor Description AMEL The POR PFD function monitors the internal power supply of the CPU core memories and the peripherals and if needed suspends their activity when the internal power sup ply falls below a safety threshold This is achieved by applying an internal reset to them By generating the Reset the Power Monitor insures a correct start up when 89 5131 is powered up In order to startup and maintain the microcontroller in correct operating mode has to be stabilized in the operating range and the oscillator has to be stabilized with a nominal amplitude compatible with logic level VIH VIL These parameters are controlled during the three phases power up normal operation and power going down See Figure 75 Figure 75 Power Monitor Block Diagram VCC __ CPU core ___ Regulated Power On Reset Supply Memories
75. 69 Disconnect Timing D V yz min A Vi 2 SS gt 2 5 Disconnected Detected USB Interrupt System Interrupt System Priorities Figure 70 USB Interrupt Control System 00 D 1 USB 01 10 D O Controller 4 5 6 7 IPH L Interrupt Enable Priority Enable Lowest Priority Interrupts A MEL 133 4338F USB 08 07 USB Interrupt Control System 134 AMEL Table 91 Priority Levels IPHUSB IPLUSB USB Priority Level 0 0 0 Lowest 0 1 1 1 0 2 1 1 3 Highest As shown in Figure 71 many events can produce a USB interrupt TXCMPL Transmitted In Data see Table 98 on page 141 This bit is set by hardware when the Host accept a In packet RXOUTBO Received Out Data Bank 0 see Table 98 on page 141 This bit is set by hardware when an Out packet is accepted by the endpoint and stored in bank 0 RXOUTB1 Received Out Data Bank 1 only for Ping pong endpoints see Table 98 on page 141 This bit is set by hardware when an Out packet is accepted by the endpoint and stored in bank 1 RXSETUP Received Setup see Table 98 on page 141 This bit is set by hardware when an SETUP packet is accepted by the endpoint STLCRC STALLED only for Control Bulk and Interrupt endpoints see Table 98 on page 141 This bit is set by hardware when a STALL handshake has been sent as requested by STALLRQ and is reset by hardware when a SETUP packet is received SOFINT
76. A Interrupt System CCON CF CR 4 CCF2 1 CCFO 0xD8 PCA Timer Counter Module 0 Module 1 4 25 Interrupt priority decoder e ove gt Module 2 4 7 Module 3 7 Module 4 7 CMOD 0 ECCFn CCAPMn 0 ES E PCA Modules each one of the five compare capture modules has six possible func tions It can perform 16 bit capture positive edge triggered e 16 bit capture negative edge triggered e 16 bit capture both positive and negative edge triggered e 16 bit Software Timer e 16 bit High speed Output e 8 bit Pulse Width Modulator In addition module 4 can be used as a Watchdog Timer Each module in the PCA has a special function register associated with it These regis ters are CCAPMO for module 0 CCAPM1 for module 1 etc see Table 50 The registers contain the bits that control the mode that each module will operate in bit CCAPMn 0 where n 0 1 2 3 or 4 depending on the module enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module e CCAPMn 1 enables the pulse width modulation
77. AT action 1 0 0 X Repeated START wili be 30h transmitted No SSDAT action 0 1 0 X STOP condition will be transmitted and SSSTO flag iia 2 followed by a START cond ll condition followed by condition wi SSDATaction L 9 be transmitted and SSSTO flag will be reset Two wire bus will be released and not addressed 38h Arbitration lost in d 0 0 x slave mode will be entered SLA W or data bytes START condition will be transmitted when the bus No SSDAT action 1 0 0 X becomes fre 106 89 5131 A L e 11 1 UM 2 4338F USB 08 07 AT89C5131A L Figure 53 Format and State in the Master Receiver Mode MR Successfull transmission S SLA R A Data A Data P MEE 7 08h 40h 50h 58h Next transfer Y started with a repeated start S SLA R condition Not acknowledge received after the slave address gt Arbitration lost in slave AorA Other master Other master address or acknowledge bit OF AY continues continues 38h 38h Arbitration lost and i A Other master addressed as slave i continues To corresponding 68h states in slave mode From master to slave Any number of data bytes and their associated Data
78. AVDD is used to supply the on chip PLL and the USB PAD Digital Ground GND VSS is used to supply the buffer ring and the digital core Digital Supply Voltage VDD PWR VDD is used to supply the buffer ring on all versions of the device It is also used to power the on chip voltage regulator of the Standard versions or the digital core of the Low Power versions USB pull up Controlled Output VREF VREF is used to control the USB 1 5 pull up The Vref output is in high impedance when the bit DETACH is set in the USBCON register 4338F USB 08 07 189 5131 1 Typical Application Recommended External components the external components described in the figure below must be implemented as close as possible from the microcontroller package The following figure represents the typical wiring schematic Figure 4 Typical Application gt lt 1 5 USB VBUS AT89C5131A L 27R D D 27R _ GND ET 22pF il VSS 100R 2 2nF 10nF 5755 vss VSS AMEL 4338F USB 08 07 11 AMEL PCB Recommandations Figure 5 USB Pads Components must be Wires must be routed in Parallel and Close to the must be as short as possible microcontroller 2 lt If possible isolate and D signals from other signals with ground wires Figure 6 USB PLL A
79. C 050 BSC 04 56 0 51 020 i 33 J 53 013 je Vol 3 13 5 STANDARD NOTES FOR PLCC 1 CONTROLLING DIMENSIONS INCHES 2 DIMENSIONING AND TOLERANCING PER ANSI Y 14 5M 1982 3 D AND E1 DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0 20 mm 008 INCH PER SIDE A MEL 179 4338F USB 08 07 AMEL 28 lead SO 7 SEATING PLANE MM INCH e 159 2 65 093 104 1 0 10 0 30 004 012 B 0 35 0 49 014 019 0 2 0 009 013 D 17 70 18 10 692 713 E 7 40 7 60 299 1 27 BSC Quot BSC H 10 00 10 65 394 419 h 0 25 0 75 010 029 0 40 016 050 28 28 0 82 180 89 5131 A L 189 5131 1 Document Revision History Changes from 1 Correction to Figure 4 on page 11 4338D 09 05 to 4338E 06 06 Changes from 1 Hardware Conditions section Page 45 changed to recommend the use of 1K 4338E 06 06 to pull up between PSEN and GND in ISP mode 4338F 08 07 2 Updated 52 lead PLCC
80. C logic 1 A START condition will be transmitted when the bus becomes free 4338F USB 08 07 ATMEL 111 AMEL Figure 55 Format and State in the Slave Transmitter Mode Reception of the 6 SLA R own slave address and one or more data bytes Arbitration lost as master i and addressed as slave Data Data PorS A8h B8h COh BOh Y Last data byte transmitted Switched to not addressed slave 0 15 Pors C8h From master to slave Table 84 Status in Slave Transmitter Mode From slave to master Any number of data bytes and their associated acknowledge bits This number contained in SSCS corresponds to a defined state of the 2 wire bus Application Software Response Status To from SSDAT To SSCON Code Status of the 2 wire bus and SSCS 2 wire hardware STA STO SI AA Next Action Taken By 2 wire Software Own SLA R has been Load data byte or X 0 0 0 4 be transmitted and A8h received ACK has been Data byte will be transmitted and will b returned Load data byte X 0 0 1 5 received Arbitration lost in SLA R W as Load data byte or X 0 0 0 Last data byte will be transmitted and NOT ACK BOh master own SLA R has been will be received received ACK has been byi X 0 0
81. CON A3h Control 48 PLLEN PLOCK PLLDIV A4h PLL Divider R3 R2 R1 RO N3 N2 N1 NO 22 4338F USB 08 07 189 5131 1 Table 27 Keyboard SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 KBF ggn KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBFO Register KBE 9Dh Slay KBE6 5 4 2 KBE1 KBEO KBLS gch Keyboard Level KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLSO Selector Register Table 28 TWI SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 SSCON ggh Synchronous Serial CR2 SSIE STA STO Si AA CR1 CRO Control SSCS g4h Synchronous Serial SC4 SC3 SC2 SC1 Sco 5 Control Status SSDAT 95h 2 Seral SD7 06 05 04 03 02 SD1 00 SSADR gsh Synchronous Serial A7 A6 A5 A4 A3 A2 A1 0 Address Table 29 SPI SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 SPCON C3h oo SPR2 SPEN SSDIS MSTR CPOL SPRI SPRO SPSTA pap SPIF WCOL SSERR MODF Status Control SPDAT C5h Serial Peripheral Data R7 R6 R5 R4 R2 R1 RO Table 30 USB SFR s Mnemonic Add 7 6 5 4 3 2 1 0 USBCON BCh USB Global Control USBE SUSPCLK SDRMWUP DETACH UPRSM RMWUPE CONFG FADDEN USBADDR C6h USB Address FEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADDO
82. D3 P2 6 A14 42 vss 41 P2 7 A15 VQFP64 40 Po 4 AD4 39 1 Ps ziRD LED3 38 P0 5 AD5 371 Po 6 AD6 36 P0 7 AD7 35 P3 6 WR LED2 15 34 INC 16 L 1 ETE EE SS 22 2 5 26 9 Enz c lt su gt a 8 5 e e 6 Figure 3 AT89C5131A L 28 SO Pinout P1 5 CEX2 KINS MISO 1 P1 6 CEX3 KIN6 SCK 2 P1 7 CEX4 KIN7 MOSI 3 P4 0 SCL 4 P4 1 SDA 5 28 P1 4 CEX1 KIN4 27 P1 3 CEXO KIN3 26 P1 2 ECI KIN2 25 P1 1 T2EX KIN1 SS 24 P1 0 T2 KINO XTAL2 6 23 RST XTAL1 7 22 VSS VDD 8 21 P3 7 RD LED3 9 P3 6 WR LED2 19 P3 5 T1 LED1 11 18 P3 4 TO B 17 P3 3 INT1 LEDO D 13 16 P3 2 INTO VREF 14 15 P3 1 TxD P3 0 RxDL 10 AMEL s 4338F USB 08 07 Signals 6 AMEL All the AT89C5131A L signals are detailed by functionality on Table 1 through Table 12 Table 1 Keypad Interface Signal Description Signal Alternate Name Type Description Function Keypad Input Lines KIN 7 0 Holding one of these pins high or low for 24 oscillator periods triggers P1 7 0 keypad interrupt if enabled Held line is reported in the KBCON register Table 2 Programmable Counter Array Signal Description Signal Alternate Name Description Functi
83. DTGL EPDIR EPTYPE1 EPTYPEO Bit Bit Number Mnemonic Description Endpoint Enable Set this bit to enable the endpoint according to the device configuration 7 EPEN Endpoint 0 will always be enabled after a hardware or USB bus reset and participate in the device configuration Clear this bit to disable the endpoint according to the device configuration 6 _ Reserved The value read from this bit is always 0 Do not set this bit 5 _ Reserved The value read from this bit is always 0 Do not set this bit 4 _ Reserved The value read from this bit is always 0 Do not set this bit Data Toggle Read only This bit is set by hardware when a valid DATAO packet is received and 3 DTGL accepted This bit is cleared by hardware when a valid DATA1 packet is received and accepted Endpoint Direction Set this bit to configure IN direction for Bulk Interrupt and Isochronous 2 EPDIR endpoints Clear this bit to configure OUT direction for Bulk Interrupt and Isochronous endpoints This bit has no effect for Control endpoints Endpoint Type Set this field according to the endpoint configuration Endpoint 0 will always be configured as control 1 0 EPTYPE 1 0 OOControl endpoint 011 endpoint 10Bulk endpoint 11Interrupt endpoint Note 1 EPNUM set in UEPNUM Register UEPNUM S C7h USB Endpoint Number Reset Value 80h when UEPNUM 0 default Control Endpoint Reset Value 00h otherwise for all other endpoints 4338
84. F USB 08 07 189 5131 1 Table 98 UEPSTAX S CEh USB Endpoint X Status Register 7 6 5 4 3 2 1 0 DIR RXOUTB1 STALLRQ TXRDY STL CRC RXSETUP RXOUTBO TXCMP Bit Bit Number Mnemonic Description Control Endpoint Direction This bit is used only if the endpoint is configured in the control type seeSection UEPCONX Register UEPCONX S D4h USB Endpoint X Control Register f P This bit determines the Control data and status direction The device firmware will set this bit ONLY for the IN data stage before any other USB operation Otherwise the device firmware will clear this bit Received OUT Data Bank 1 for Endpoints 4 5 and 6 Ping pong mode This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 1 only in Ping pong mode 6 RXOUTB1 Then the endpoint interrupt is triggered if enabled see UEPINT Register UEPINT S F8h read only USB Endpoint Interrupt Register on page 145 and all the following OUT packets to the endpoint bank 1 are rejected NAK ed until this bit has been cleared excepted for Isochronous Endpoints This bit will be cleared by the device firmware after reading the OUT data from the endpoint FIFO Stall Handshake Request 5 STALLRQ Set this bit to request STALL answer to the host for the next handshake Clear this bit otherwise For CONTROL endpoints cleared by hardware when a valid SETUP PID is received TX Packet
85. FFh no user boot loader in FMO To read or modify this byte the APIs are used Extra Byte EB amp Boot Status Byte BSB These Bytes are reserved for customer use To read or modify these Bytes the APIs are used Figure 23 Hardware Boot Process Algorithm RESET Is Initialized with BLJB Inverted bit ENBOOT in AUXR1 Register Example if BLJB 0 ENBOOT is set 21 during reset thus the bootloader is executed after the E ENBOOT 0 reset PC 0000h 1 PC F400h 5 Application Bootloader 5 FM1 4338F USB 08 07 189 5131 1 Application Programming Interface XROW Bytes Hardware Conditions High Pin Count Hardware Conditions PLCC52 QFP64 4338F USB 08 07 Several Application Program Interface API calls are available for use by an application program to permit selective erasing and programming of Flash pages All calls are made by functions All these APIs are described in detail in the following document on the Atmel web site Datasheet Bootloader USB AT89C5131 The EXTRA ROW XROW includes 128 bytes Some of these bytes are used for spe cific purpose in conjonction with the bootloader Table 43 XROW Mapping Description Default Value Address Copy of the Manufacturer Code 58h 30h Copy of the Device ID 1 Family code D7h 31h Copy of the Device 10 2 Memories size and ty
86. FO Data Endpoint X X EPNUM set in UEPNUM Register UEPNUM S C7h 7 6 5 4 3 2 1 0 FDAT7 FDAT6 FDAT5 FDAT4 FDAT3 FDAT2 FDAT1 FDATO Bit Bit Number Mnemonic Description Endpoint X FIFO data 7 0 7 01 Data byte to be written to FIFO or data byte to be read from the FIFO for the Endpoint X see EPNUM USB Endpoint Number Reset Value XXh Table 100 UBYCTLX Register UBYCTLX S E2h USB Byte Count Low Register X X EPNUM set in UEPNUM Register UEPNUM 7 6 5 4 3 2 1 0 BYCT7 BYCT6 5 BYCTA 2 Bit Bit Number Mnemonic Description Byte Count LSB Least Significant Byte of the byte count of a received data packet The most 7 0 BYCT 7 0 significant part is provided by the UBYCTHX Register UBYCTHX S E3h USB Byte Count High Register X X EPNUM set in UEPNUM Register UEPNUM S C7h USB Endpoint Number see Figure 100 on page 142 This byte count is equal to the number of data bytes received after the Data PID S C7h USB Endpoint Number Reset Value 00h 4338F USB 08 07 XX 189 5131 1 4338F USB 08 07 Table 101 UBYCTHX Register UBYCTHX S E3h USB Byte Count High Register X X EPNUM set in UEPNUM Register UEPNUM 7 6 5 1 0 BYCT9 8 Bit Number Bit Mnemonic Description 7 2 1 Reserv
87. Features 80C52X2 Core 6 Clocks per Instruction Maximum Core Frequency 48 MHz in X1 Mode 24 MHz in X2 Mode Dual Data Pointer Full duplex Enhanced UART EUART Three 16 bit Timer Counters TO T1 and T2 8 es 24 a5 5 256 Bytes of Scratchpad RAM 16 32 Kbyte On chip Flash EEPROM In System Programming through USB Byte and Page 128 bytes Erase and Write 100k Write Cycles 1 8 bit Flash Del Microcontroller 1 2 Wile Ciclos bytes Erase and Write with Full Speed 1 Internal Power Supply U S B Devi ce USB 1 1 and 2 0 Full Speed Compliant Module with Interrupt on Transfer Completion Endpoint 0 for Control Transfers 32 byte FIFO 6 Programmable Endpoints with In or Out Directions and with Bulk Interrupt or Isochronous Transfers AT89C51 31 A L Endpoint 1 2 3 32 byte FIFO Endpoint 4 5 2 x 64 byte FIFO with Double Buffering Ping pong Mode Endpoint 6 2 x 512 byte FIFO with Double Buffering Ping pong Mode Suspend Resume Interrupts Power on Reset and USB Bus Reset 48 MHz DPLL for Full speed Bus Operation USB Bus Disconnection on Microcontroller Request 5 Channels Programmable Counter Array PCA with 16 bit Counter High speed Output Compare Capture PWM and Watchdog Timer Capabilities Programmable Hardware Watchdog Timer One time Enabled with Reset out 50 ms to 6s at 4 MHz Keyboard Interrupt Interface on Port P1 8 Bits TWI Two Wire Interface
88. I will be the one following the instruction that put AT89C5131A L into power down mode 152 AT89C5131 A L ULCUIUILL LA ROOOBLUL A L OULOOO L L 2 1RI 9 4338F USB 08 07 189 5131 1 Figure 77 Power down Exit Waveform 4338F USB 08 07 INTO INT1 Active Phase gt lt Power down Phase gt lt Oscillator restart Phase gt lt Active Phase Exit from power down by reset redefines all the SFRs exit from power down by external interrupt does no affect the SFRs Exit from power down by either reset or external interrupt does not affect the internal RAM content Note If idle mode is activated with power down mode IDL and PD bits set the exit sequence is unchanged when execution is vectored to interrupt PD and IDL bits are cleared and idle mode is not entered This table shows the state of ports during idle and power down modes Table 107 State of Ports Program Mode Memory ALE PSEN PORTO PORT1 PORT2 PORTS PORTI2 Port Port Port Idle Internal 1 1 Data Data Port Data Port Data Data Idle External 1 1 Floating PANE Address Port Data Por Data Data Port Port Port Power down Internal 0 0 Data Data Port Data Port Data Data Power down External 0 0 Floating Port Port Data Port Data Data Data Note 1 PortO can force a 0 level
89. INTO INT1 TO 1 SERIAL PORT SHIFT CLOCK TXD MODE 0 RXD SAMPLED RXD SAMPLED This diagram indicates when signals are clocked internally The time it takes the signals to propagate to the pins however ranges from 25 to 125 ns This propagation delay is dependent on variables such as temperature and pin loading Propaga tion also varies from output to output and component Typically though T4 25 fully loaded RD and WR propagation delays are approximately 50 ns The other signals are typically 85 ns Propagation delays are incorporated in the AC specifications A MEL 171 4338F USB 08 07 Flash EEPROM Memory and Data EEPROM Memory AMEL Table 124 Timing Symbol Definitions Signals Conditions S Hardware Condition PSEN EA L Low R RST V Valid B FBUSY Flag X No Longer Valid Table 125 Memory AC Timing VDD 3 3V 10 40 to 85 Symbol Parameter Min Typ Max Unit Input PSEN Valid to RST Edge 50 ns Trisx Input PSEN Hold after RST Edge 50 ns Flash EEPROM Internal Busy Programming Time 0 20 EEPROM Data Internal Busy 10 20 m Programming Time Flash EEPROM program memory write cycles 100K Cycles Configuration bits fuses bits memory write cycles BLJB X2 OSCONO OSCON1 1K Cycles EEPROM Data memory write cycles 100K Cycles Figu
90. N Refer to the Atmel 8 bit microcontroller hardware documentation for the description of Capture and Baud Rate Generator Modes Timer 2 includes the following enhancements Auto reload mode with up or down counter Programmable Clock output The Auto reload mode configures Timer 2 as a 16 bit timer or event counter with auto matic reload If DCEN bit in T2MOD is cleared Timer 2 behaves as in 80C52 refer to the Atmel 8 bit microcontroller hardware description If DCEN bit is set Timer 2 acts as an Up down timer counter as shown in Figure 26 In this mode the T2EX pin controls the direction of count When T2EX is high Timer 2 counts up Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request The overflow also causes the 16 bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2 When T2EX is low Timer 2 counts down Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers The underflow sets TF2 flag and reloads FFFFh into the timer registers The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of the count EXF2 does not generate any interrupt This bit can be used to provide 17 bit resolution 4338F USB 08 07 AT89C5131A L Figure 26 Auto reload Mode Up Down Counter DCEN 1 PERIPH 6 0 T2 C T2 TR2 T2CON
91. N Synchronous Serial Control Register 93h 7 6 5 4 3 2 1 0 CR2 SSIE STA STO SI AA CR1 CRO Bit Bit Number Mnemonic Description 7 CR2 Control Rate bit 2 See Synchronous Serial Interface Enable bit 6 SSIE Clear to disable SSLC Set to enable SSLC Start flag SIA Set to send a START condition on the bus Stop flag STO Set to send a STOP condition on the bus Synchronous Serial Interrupt flag 3 SI Set by hardware when a serial interrupt is requested Must be cleared by software to acknowledge interrupt Assert Acknowledge flag Clear in master and slave receiver modes to force a not acknowledge high level on SDA Clear to disable SLA or GCA recognition 2 AA Set to recognise SLA or GCA if GC set for entering slave receiver or transmitter modes Set in master and slave receiver modes to force an acknowledge low level on SDA This bit has no effect when in master transmitter mode Control Rate bit 1 GRI See Table 80 Control Rate bit 0 9 CRO See Table 80 Table 87 SSDAT 095h Synchronous Serial Data Register read write SD7 SD6 SD5 SD4 503 02 501 00 7 6 5 4 3 2 1 0 Bit Bit Number Mnemonic Description 7 SD7 Address bit 7 or Data bit 7 6 SD6 Address bit 6 or Data bit 6 5 SD5 Address bit 5 or Data bit 5 4 04 Address bit 4 or Data bit 4 3 SD3 Address bit 3 or Data bit 3 2 SD2 Address bit 2 or Data bit
92. O is performed by setting to 1 and resetting to 0 the corresponding bit in the UEPRST register For example in order to reset the Endpoint number 2 FIFO write 0000 0100b then 0000 0000b in the UEPRST register Note that the endpoint reset doesn t reset the bank number for ping pong endpoints Depending on the selected endpoint through the UEPNUM register the UEPDATX reg ister allows to access the corresponding endpoint data fifo Figure 61 Endpoint FIFO Configuration Read Data FIFO Write Data FIFO 4338F USB 08 07 Endpoint 0 Endpoint 6 UEPSTAO UEPCONO UEPDATO M9 0 UBYCTHO UBYCTLO SFR registers 1 5 UEPDATX amp 3 4 UBYCTHX UBYCTLX 5 UEPSTA6 UEPCONe UEPDATs gt 6 UBYCTH6 UBYCTL6 The read access for each OUT endpoint is performed using the UEPDATX register After a new valid packet has been received on an Endpoint the data are stored into the FIFO and the byte counter of the endpoint is updated UBYCTLX and UBYCTHX regis ters The firmware has to store the endpoint byte counter before any access to the endpoint FIFO The byte counter is not updated when reading the FIFO To read data from an endpoint select the correct endpoint number in UEPNUM and read the UEPDATX registe
93. P programmed or zero level 3 WARNING Security level 2 and 3 should only be programmed after Flash and code verification AT89C5131A L parts are delivered with the ISP boot in the Flash memory After ISP or parallel programming the possible contents of the Flash memory are summarized in Figure 21 Figure 21 Flash Memory Possible Contents gt 7FFFh AT89C5131A M Virgin 0000h Application Virgin Application Virgin Virgin or Application Application Application Dedicated Dedicated ISP ISP Default Memory Organization After parallel After parallel After parallel After ISP After ISP programming programming programming In the AT89C5131A L the lowest 32K of the 64 Kbyte program memory address space is filled by internal Flash When the EA is pin high the processor fetches instructions from internal program Flash Bus expansion for accessing program memory from 32K upward is automatic since external instruction fetches occur automatically when the program counter exceeds 7FFFh 32K If the EA pin is tied low all program memory fetches are from external memory If all storage is on chip then byte location 7FFFh 32K should be left vacant to prevent and undesired pre fetch from external program memory address 8000h 32K 4338F USB 08 07 189 5131 1 EEPROM Data Memory Description The 1 Kbyte on
94. P or STLCRC A USB interrupt is triggered when the bit in the UEPIEN register is set This bit is cleared by hardware when all the endpoint interrupt sources are cleared Endpoint 2 Interrupt This bit is set by hardware when an endpoint interrupt source has been detected on the 2 EP2INT endpoint 2 The endpoint interrupt sources are in the UEPSTAX register and can be TXCMP RXOUTBO 1 RXSETUP or STLCRC A USB interrupt is triggered when the EP2IE bit in the UEPIEN register is set This bit is cleared by hardware when all the endpoint interrupt sources are cleared Endpoint 1 Interrupt This bit is set by hardware when an endpoint interrupt source has been detected on the 1 EP1INT endpoint 1 The endpoint interrupt sources are in the UEPSTAX register and can be TXCMP RXOUTBO 1 RXSETUP or STLCRC USB interrupt is triggered when the EP1IE bit in the UEPIEN register is set This bit is cleared by hardware when all the endpoint interrupt sources are cleared Endpoint 0 Interrupt This bit is set by hardware when an endpoint interrupt source has been detected on the 0 EPOINT endpoint 0 The endpoint interrupt sources are in the UEPSTAX register and can be TXCMP RXOUTBO 1 RXSETUP or STLCRC A USB interrupt is triggered when the EPOIE bit in the UEPIEN register is set This bit is cleared by hardware when all the endpoint interrupt sources are cleared Reset
95. PCON is set This kind of configuration can be found when only one Master is driving the network and there is no way that the SS pin could be pulled low Therefore the MODF flag in the SPSTA will never be set The Device is configured as a Slave with and SSDIS control bits set This kind of configuration can happen when the system comprises one Master and one Slave only Therefore the device should always be selected and there is no reason that the Master uses the SS pin to select the communicating Slave device Notes 1 Clearing SSDIS control bit does not clear MODF 2 Special care should be taken not to set SSDIS control bit when 0 because in this mode the SS is used to start the transmission In Master mode the baud rate can be selected from a baud rate generator which is con trolled by three bits in the SPCON register SPR2 SPR1 and SPRO The Master clock is chosen from one of seven clock rates resulting from the division of the internal clock by 2 4 8 16 32 64 or 128 Table 72 gives the different clock rates selected by SPR2 SPR1 SPRO Table 72 SPI Master Baud Rate Selection SPR2 SPR1 SPRO Clock Rate Baud Rate Divisor BD 0 0 0 Don t Use No BRG 0 0 1 4 4 0 1 0 8 8 0 1 1 16 16 1 0 0 32 32 1 0 1 64 64 1 1 0 128 128 1 1 1 Don t Use No BRG
96. PHO IEN1 IPL1 IPH1 Keyboard Interface registers KBE KBF KBLS LED register LEDCON Two Wire Interface TWI registers SSCON SSCS SSDAT SSADR Serial Port Interface SPI registers SPCON SPSTA SPDAT USB registers Uxxx 17 registers PLL registers PLLCON PLLDIV BRG Baud Rate Generator registers BRL BDRCON Flash register FCON FCON access is reserved for the Flash API and ISP software EEPROM register EECON Others AUXR AUXR1 CKCONO 1 4338F USB 08 07 189 5131 1 Table 18 SFR Descriptions The table below shows all SFRs with their address and their reset value Bit Addressable Non Bit Addressable 0 8 1 9 2 A 3 B 4 5 D 6 E 7 F F8h UEPINT CH CCAPOH CCAP1H CCAP2H CCAP3H FFh 0000 0000 0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX B LEDCON 0000 0000 0000 0000 m E8h CL CCAPOL CCAP1L CCAP2L CCAP3L CCAP4L EFh 0000 0000 UBYCTLX UBYCTHX E7h 0000 0000 0000 0000 0000 0000 D8h CCON CMOD CCAPMO 1 2 CCAPM4 DFh 00 0 0000 00XX X000 X000 0000 X000 0000 X000 0000 X000 0000 X000 0000 DOh PSW FCON 1 EECON UEPCONX UEPRST D7h 0000 0000 XXXX 0000 XXXX XX00 1000 0000 0000 0000 C8h T2CON T2MOD RCAP2L RCAP2H TL2 TH2 UEPSTAX UEPDATX CFh 0000 0000 XXX
97. RH 130 ns TwiwH 130 ns Tripv 100 ns 0 Tnupz 30 ns Tupv 160 ns 165 ns 50 100 ns TavwL 75 ns Tovwx 10 ns TovwH 160 ns Twuox 15 ns 0 ns 10 40 ns 4338F USB 08 07 es 189 5131 1 Table 119 AC Parameters for a Variable Clock Standard Symbol Type Clock X2 Clock X Parameter Units TRLRH Min 6T x 3T x 20 ns TwiwH Min 6 3 20 ns Trepov Max 5T x 2 5 25 ns Taupx Min 0 ns 7 2 T x 20 ns 8 4 40 ns 9 4 5T x 60 ns TuwL Min 3 1 5 25 ns Tuwe Max 1 5 25 ns 4T x 2T x 25 ns Tavwx Min T x 0 5T x 15 ns Min 7T x 3 5T x 25 ns T x 0 5T x 10 ns 0 ns TWHLH Min T x 0 5T x 15 ns TWHLH Max 0 5 15 ns External Data Memory Write Cycle SFR P2 ADDRESS A8 A15 OR SFR P2 4 MEL 167 4338F USB 08 07 External Data Memory Read Cycle Serial Port Timing Shift Table 120 Symbol Description F 40 MHz Register Mode Symbol Parameter T Dax Serial port clock cycle time Output data set up to clock rising edge Output data hold after clock rising edge Txupx Input data hold after clock rising edge Clock rising edge to input data valid
98. Ready Set this bit after a packet has been written into the endpoint FIFO for IN data transfers Data will be written into the endpoint FIFO only after this bit has been cleared Set this bit without writing data to the endpoint FIFO to send a Zero 4 TXRDY Length Packet This bit is cleared by hardware as soon as the packet has been sent for Isochronous endpoints or after the host has acknowledged the packet for Control Bulk and Interrupt endpoints When this bit is cleared the endpoint interrupt is triggered if enabled see UEPINT Register UEPINT S F8h read only USB Endpoint Interrupt Register on page 145 Stall Sent CRC error flag For Control Bulk and Interrupt Endpoints This bit is set by hardware after a STALL handshake has been sent as requested by STALLRQ Then the endpoint interrupt is triggered if enabled see UEPINT Register UEPINT S F8h read only USB Endpoint Interrupt Register on 3 STLCRC 145 It will be cleared by the device firmware For Isochronous Endpoints Read Only This bit is set by hardware if the last received data is corrupted CRC error on data This bit is updated by hardware when a new data is received Received SETUP This bit is set by hardware when a valid SETUP packet has been received from the host Then all the other bits of the 2 RXSETUP register are cleared by hardware and the endpoint interrupt is triggered if enabled see UEPINT Register UEPINT S F8h read only USB En
99. SM1 0 1 1 8 bit UARTVariable 1 0 2 9 bit UARTFopyperipy 32 01 16 1 1 3 9 bit UART Variable Serial port Mode 2 bit Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature Set to enable multiprocessor communication feature in mode 2 and 3 and eventually mode 1 This bit should be cleared in mode 0 5 SM2 Reception Enable bit 4 REN Clear to disable serial reception Set to enable serial reception Transmitter Bit 8 Ninth bit to Transmit in Modes 2 and 3 3 TB8 Clear to transmit a logic 0 in the 9th bit Set to transmit a logic 1 in the 9th bit Receiver Bit 8 Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0 Set by hardware if 9th bit received is a logic 1 In mode 1 if SM2 0 RB8 is the received stop bit In mode 0 RB8 is not used 2 RB8 Transmit Interrupt flag Clear to acknowledge interrupt Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes Receive Interrupt flag Clear to acknowledge interrupt Set by hardware at the end of the 8th bit time in mode 0 see Figure 35 and Figure 36 in the other modes Reset Value 0000 0000b Bit addressable AMEL 4338F USB 08 07 UART Registers SADEN Slave Address Mask Register for UART B9h 7 6 5 4 3 2 1 0 Reset Value 0000 0000b SADDR Slave Address Register for UART A9h 7 6 5 4 3
100. SPINT is set by hardware when an idle state is detected for more than 3 ms This triggers a USB interrupt if enabled In order to reduce current consumption the firmware can put the USB PAD in idle mode stop the clocks and put the C51 in Idle or Power down mode The Resume detection is still active The USB PAD is put in idle mode when the firmware clear the SPINT bit In order to avoid a new suspend detection 3ms later the firmware has to disable the USB clock input using the SUSPCLK bit in the USBCON Register The USB PAD automatically exits of idle mode when a wake up event is detected The stop of the 48 MHz clock from the PLL should be done in the following order 1 Clear suspend interrupt bit in USBINT required to allow the USB pads to enter power down mode 2 Enable USB resume interrupt 3 Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUS PCLK bit in the USBCON register 4 Disable the PLL by clearing the PLLEN bit in the PLLCON register 5 Make the CPU core enter power down mode by setting PDOWN bit in PCON When the USB controller is in Suspend state the Resume detection is active even if all the clocks are disabled and if the C51 is in Idle or Power down mode The WUPCPU bit is set by hardware when a non idle state occurs on the USB bus This triggers an inter rupt if enabled This interrupt wakes up the CPU from its Idle or Power down state and the interrupt function is then executed The fi
101. T2CON DOWN COUNTING RELOAD VALUE T2EX FFh FFh if DCEN 1 1 UP 8 bit 8 bit if DCEN 1 0 DOWN if DCEN 0 up counting TOGGLE T2CON e X Hex TH2 TF2 Timer 2 gt INTERRUPT T2CON RCAP2L RCAP2H 8 bit 8 bit UP COUNTING RELOAD VALUE Programmable Clock In the Clock out mode Timer 2 operates as 50 duty cycle programmable clock gen Output erator See Figure 27 The input clock increments TL2 at frequency Ferk 2 The timer repeatedly counts to overflow from a loaded value At overflow the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2 In this mode Timer 2 overflows do not generate interrupts The following formula gives the Clock out fre quency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers Clock OutFrequency For 16 MHz system clock Timer 2 has a programmable frequency range of 61 Hz 2 to 4 MHz 4 The generated clock signal is brought out to T2 pin P1 0 Timer 2 is programmed for the Clock out mode as follows Set T2OE bit in T2MOD register Clear C T2 bit in T2CON register e Determine the 16 bit reload value from the formula and enter it in RCAP2H RCAP
102. TRAM AO AUXR1 A2h Auxiliary Register 1 ENBOOT GF3 DPS CKCONO 8Fh Clock Control 0 TWIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 TOX2 X2 CKCON 1 AFh Clock Control 1 SPIX2 LEDCON Fih LED Control LED3 LED2 LED1 LEDO FCON Dih Flash Control FPL3 FPL2 FPL1 FPLO FPS FMOD1 FMODO FBUSY EECON D2h EEPROM Contol EEPL3 EEPL2 EEPL1 EEPLO EEE EEBUSY 4338F USB 08 07 189 5131 1 Dual Data Pointer Register Figure 12 Use of Dual Pointer 4338F USB 08 07 AUXR1 A2H The additional data pointer can be used to speed up code execution and reduce code size The dual DPTR structure is a way by which the chip will specify the address of an exter nal data memory location There are two 16 bit DPTR registers that address the external memory and a single bit called DPS AUXR1 0 see Table 32 that allows the program code to switch between them see Figure 12 DPH 83H DPL 82H External Data Memory d RE m Table 32 AUXR1 Register AUXR1 Auxiliary Register 1 0A2h 7 6 5 4 3 2 1 0 ENBOOT 0 DPS Bit Bit Number Description 7 Reserved The value read from this bit is indeterminate Do not set this bit 6 Reserved The value read from this bit is indeterminate Do not set this bit Enable Boot Flash 5 ENBOOT Cleared to disable boot ROM Set to map the boot ROM between F800h OFFFFh 4 Reserved The value read fr
103. The Flash memory enters a busy state as soon as programming is launched In this state the memory is not available for fetching code Thus to avoid any erratic execution during programming the CPU enters Idle mode Exit is automatically performed at the end of programming Note Interrupts that may occur during programming time must be disabled to avoid any spuri ous exit of the idle mode The bit FBUSY in FCON register is used to indicate the status of programming FBUSY is set when programming is in progress The bit ENBOOT in AUXR1 register is used to choose between FMO and FM1 mapped up to F800h 4338F USB 08 07 189 5131 1 Loading the Column Latches number of data from 1 byte to 128 bytes can be loaded in the column latches This provides the capability to program the whole memory by byte by page or by any number of bytes in a page When programming is launched an automatic erase of the locations loaded in the col umn latches is first performed then programming is effectively done Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page The following procedure is used to load the column latches and is summarized in Figure 17 the column latch space by setting FPS bit Load the with the address to load Load Accumulator register with the data to load Execute the MOVX DPTR A instruction
104. Tray AT89C5131A S3SUL 32 3 0 to 3 6V Industrial amp Green PLCC52 Stick AT89C5131A TISUL 32 3 0 to 3 6V Industrial amp Green 5028 Stick Note 1 Optional Packing and Package options please consult Atmel sales representative Tape and Reel Dry Pack Known good dice 177 4338F USB 08 07 ATMEL AMEL Packaging Information 64 lead VQFP Dl 64 c I 1 E El i5 ja c 1 L f r i Cy 6 T d 1 0 102 MAX LEAD COPLANARI TY MM INCH Min Max Mi n 1 60 063 1 0 64 025 REF Ac 0 64 REF 025 REF 1 39 1 45 05 05 D 11 75 2 29 463 483 Dl 9 30 0 10 390 398 11 75 Prea 463 483 El 9 90 0 10 390 398 J 0 05 zi 002 L 0 45 D 29 018 030 0 50 BSC 0197 BSC f 0 25 BSC 010 BSC 178 AT89C5131 A L LA LIU LUULLu ILLOLFEELLLULL OEDLDLE LLLAA LO Kj 4338F USB 08 07 189 5131 1 52 lead PLCC NS VO c Z pR x 5 i 7 Ne 7222 2 x E 1 2 1 1 1 INC 20 es 80 eu P 3 3 09 3 gt t 2 LUE in 2 9 2 2 2 05 730 756 De 53 2 690 30 S 9 35 E E 8 4 69 2 BS
105. Vss PLLF Components must be close to the microcontroller Isolate filter components with a ground wire 189 5131 1 Clock Controller Introduction The AT89C5131A L clock controller is based on an on chip oscillator feeding an on chip Phase Lock Loop PLL All the internal clocks to the peripherals and CPU core are gen erated by this controller The AT89C5131A L X1 and X2 pins are the input and the output of a single stage on chip inverter see Figure 7 that can be configured with off chip components as a Pierce oscillator see Figure 8 Value of capacitors and crystal characteristics are detailed in the section DC Characteristics The X1 pin can also be used as input for an external 48 MHz clock The clock controller outputs three different clocks as shown in Figure 7 e a clock for the CPU core aclock for the peripherals which is used to generate the Timers PCA WD and Port sampling clocks aclock for the USB controller These clocks are enabled or disabled depending on the power reduction mode as detailed in Section Power Management page 152 Figure 7 Oscillator Block Diagram Oscillator 4338F USB 08 07 dis Peripheral 1 Clock CPU Core Clock 2 0 0 gt gt USB 1 Clock 48 PLLCON 2 1
106. Writing to the SPDAT will cause an overflow 4338F USB 08 07 189 5131 1 Two Wire Interface TWI 4338F USB 08 07 This section describes the 2 wire interface The 2 wire bus is a bi directional 2 wire serial communication standard It is designed primarily for simple but efficient integrated circuit IC control The system is comprised of two lines SCL Serial Clock and SDA Serial Data that carry information between the ICs connected to them The serial data transfer is limited to 100 Kbit s in standard mode Various communication configuration can be designed using this bus Figure 49 shows a typical 2 wire bus configuration All the devices connected to the bus can be master and slave Figure 49 2 wire Bus Configuration device1 device2 device3 SCL SDA ATMEL s AMEL Figure 50 Block Diagram SSADR Address Register Input Comparator Filter SDA 4 9 Output SEM Shift Register 12 Input Arbitration amp ink Logi Fitar Sale ied 5 Control g 4 logic Output Serial clock r 3nterrupt Stage generator Timer 1 1 overflow 55 Control Register Status Status
107. X XX00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4 UEPIEN SPCON SPSTA SPDAT USBADDR UEPNUM 1111 0000 0000 0001 0100 0000 0000 XXXX XXXX 1000 0000 0000 0000 B8h IPLO SADEN UFNUML UFNUMH USBCON USBINT USBIEN BFh X000 000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 BR P3 IEN1 IPL1 IPHO ER 1111 1111 XOXX X000 XOXXX000 X000 X000 0000 IEN ADDR 1 A8h i 2 0000 0000 0000 0000 0000 0000 AOh P2 AUXR1 PLLCON PLLDIV WDTRST WDTPRG 1111 1111 XXXX XOXO XXXX XX00 0000 0000 XXXX XXXX XXXX X000 98h SCON SBUF BRL BDRCON KBLS KBE KBF 9Fh 0000 0000 XXXX XXXX 0000 0000 0000 0000 0000 0000 0000 0000 0000 90h P1 SSCON SSCS SSDAT SSADR 97h 1111 1111 0000 0000 1111 1000 1111 1111 1111 1110 TCON TMOD TLO TL1 THO TH1 AUXR CKCONO 88h 8Fh 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Bon SP DPL DPH PCON 1111 1111 0000 0111 0000 0000 0000 0000 00X1 0000 0 8 1 9 2 A 3 B 4 5 D 6 E 7IF Note 1 FCON access is reserved for the Flash and ISP software Reserved 19 4338F USB 08 07 AMEL 20 AMEL The Special Function Registers SFRs of the AT89C5131 fall into the following categories Table 19 C51 Core SFRs Mnemonic Add 1 0 EOh Accumulator B FOh B Register Program Status PSW DOh Word k P
108. able IT 0 Launch Programming FCON 5xh FCON Axh FBusy Cleared Erase Mode FCON 00h End Programming Enable IT EA 1 X 189 5131 1 Hardware Security 4338F USB 08 07 The following procedure is used to program the Hardware Security space and is sum marized in Figure 19 Set FPS and map Hardware byte FCON 0 0 Disable the interrupts Load DPTR at address 0000h Load Accumulator register with the data to load Execute the MOVX A instruction Launch the programming by writing the data sequence 54h followed by 4 in FCON register The end of the programming indicated by the FBusy flag cleared Enable the interrupts Figure 19 Hardware Programming Procedure Flash Spaces Programming FCON 0Ch Data Load DPTR 00h ACC Data Exec MOVX Y Disable IT 0 Y Launch Programming FCON 54h FCON A4h FBusy Cleared Erase Mode FCON 00h Y End Programming Enable IT EA 1 Y AMEL Reading the Flash Spaces User Extra Row Hardware Security AMEL The following procedure is used to read the User space and is summarized in Figure 20 Map the User space by writing 00h register
109. according to KBLS x bit value Level detection is then reported in interrupt flags KBF x that can be masked by software using KBE x bits This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allow usage of P1 inputs for other purpose Figure 40 Keyboard Interface Block Diagram Input Circuitry P1 1 gt Input Circuitry P1 2 Input Circuitry Input Circuitry Input Circuitry P1 5 1 Input Circuitry P1 6 gt Input Circuitry P1 7 1 Input Circuitry Figure 41 Keyboard Input Circuitry KBDIT Keyboard Interface Interrupt Request AMEL 85 Power Reduction Mode Registers AMEL P1 inputs allow exit from idle and power down modes as detailed in section Power down Mode Table 68 KBF Register KBF Keyboard Flag Register 9Eh 7 6 5 4 3 2 1 0 7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBFO Bit Bit Number Mnemonic Description Keyboard line 7 flag Set by hardware when the Port line 7 detects a programmed level It generates a Keyboard interrupt request if the KBKBIE 7 bit in KBIE register is set Cleared by hardware when reading KBF SFR by software 7 KBF7 Keyboard line 6 flag Set by hardware when the Port line 6 detects a progra
110. action or X 0 0 0 Data byte will be received and NOT ACK will be 80h own SLA W data has been returned received ACK has been Data byte will be received and ACK will be returned No SSDAT action X 0 0 1 ratumod Switched to the not addressed slave mode no Read data byte or 0 0 0 0 recognition of own SLA Switched to the not addressed slave mode own Re d data 0 0 0 1 SLA will be recognised GCA will be recognised if GC logic 1 Previously addressed with own SLA W data has been Switched to the not addressed slave mode no 88h received NOT ACK has been Read data byte or 1 0 0 0 recognition of own SLA or GCA A START returned condition will be transmitted when the bus becomes free Switched to the not addressed slave mode own SLA will be recognised GCA will be recognised if Read dat byte 1 0 0 GC logic 1 A START condition will be transmitted when the bus becomes free Previously addressed with Data byte will be received and NOT ACK will be X 0 0 0 90h general call data has been Read data Or returned received ACK has been Read data byte X 0 0 q4 Data byte will be received and will be returned returned 110 AT89C5131 A L re neg i LLLCLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLZT ZILLLLZ ISLLLICIOQOUu hLEIEBUEUEZZZN 4338F USB 08 07 189 5131 1 Table 83 Status Slave Receiver Mode Continued Application Software Response Status Code SSCS Sta
111. address 0033H the SPI interrupt vector is located at address 004BH and Keyboard interrupt vector is located at address 003 All other vectors addresses are the same as standard C52 devices Table 60 Priority Level Bit Values IPH x IPL x Interrupt Level Priority 0 0 0 Lowest 0 1 1 1 0 2 1 1 3 Highest A low priority interrupt can be interrupted by a high priority interrupt but not by another low priority interrupt A high priority interrupt can t be interrupted by any other interrupt source If two interrupt requests of different priority levels are received simultaneously the request of higher priority level is serviced If interrupt requests of the same priority level are received simultaneously an internal polling sequence determines which request is serviced Thus within each priority level there is a second priority structure determined by the polling sequence ATMEL 78 AMEL Table 61 IENO Register IENO Interrupt Enable Register A8h 7 6 5 4 3 EA EC ET2 ES ET1 EX1 ETO Bit Number Bit Mnemonic Description EA Enable All interrupt bit Cleared to disable all interrupts Set to enable all interrupts EC PCA interrupt enable bit Cleared to disable Set to enable ET2 Timer 2 overflow interrupt Enable bit Cleared to disable Timer 2 overflow interrupt Set to enable Timer 2 overflow in
112. aster conflict for system control In this case the SPI system is affected in the following ways e An SPI receiver error CPU interrupt request is generated e The SPEN bit in SPCON is cleared This disable the SPI The MSTR bit in SPCON is cleared When SS DiISable SSDIS bit in the SPCON register is cleared the MODF flag is set when the SS signal becomes 0 However as stated before for a system with one Master if the SS pin of the Master device is pulled low there is no way that another Master attempt to drive the network In this case to prevent the MODF flag from being set software can set the SSDIS bit in the SPCON register and therefore making the SS pin as a general purpose pin Clearing the MODF bit is accomplished by a read of SPSTA register with bit set followed by a write to the SPCON register SPEN Control bit may be restored to its orig inal set state after the MODF bit has been cleared A Write Collision WCOL flag in the SPSTA is set when a write to the SPDAT register is done during a transmit sequence WCOL does not cause an interruption and the transfer continues uninterrupted Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an access to SPDAT An overrun condition occurs when the Master device tries to send several data bytes and the Slave devise has not cleared the SPIF bit issuing from the previous data byte transmitted In this case the receiver buffer
113. ce controller provides the hardware that the 89 5131 needs to inter face a USB link to a data flow stored in a double port memory DPRAM The USB controller requires a 48 MHz 0 25 reference clock which is the output of the AT89C5131 PLL see Section PLL page 14 divided by a clock prescaler This clock is used to generate a 12 MHz Full speed bit clock from the received USB differen tial data and to transmit data according to full speed USB device tolerance Clock recovery is done by a Digital Phase Locked Loop DPLL block which is compliant with the jitter specification of the USB bus The Serial Interface Engine SIE block performs NRZI encoding and decoding bit stuff ing CRC generation and checking and the serial parallel data conversion The Universal Function Interface UFI realizes the interface between the data flow and the Dual Port RAM Figure 56 USB Device Controller Block Diagram 116 48 MHz 0 2596 C51 Microcontroller D D USB D D D D Buffer Interface Up to 48 MHz UC sysclk 4338F USB 08 07 189 5131 1 Serial Interface Engine SIE Figure 57 SIE Block Diagram End of Packet Detection YNC D i gt Start of Packet Detection 1 gt Detection NRZI NRZ gt PID Decoder og Bit Un stuffing 4 u
114. contains the byte sent after the SPIF bit was last cleared A read of the SPDAT returns this byte All others bytes are lost This condition is not detected by the SPI peripheral Two SPI status flags can generate a CPU interrupt requests Table 73 SPI Interrupts Flag Request SPIF SP Data Transfer SPI Transmitter Interrupt request MODF Mode Fault SPI Receiver Error Interrupt Request if SSDIS 0 Serial Peripheral data transfer flag SPIF This bit is set by hardware when a transfer has been completed SPIF bit generates transmitter CPU interrupt requests Mode Fault flag MODF This bit becomes set to indicate that the level on the SS is inconsistent with the mode of the SPI MODF with SSDIS reset generates receiver error CPU interrupt requests Figure 48 gives a logical view of the above statements AMEL s AMEL Figure 48 SPI Interrupt Requests Generation SPF n SPI Transmitter CPU Interrupt Request CPU Interrupt Request MODF L SPI Receiver Error O CPU Interrupt Request SSDIS Registers There are three registers in the module that provide control status and data storage functions These registers are describes in the following paragraphs Serial Peripheral Control The Serial Peripheral Control Register does the following Register SPCON Selects one of the Master clock
115. cts are not intended authorized or warranted for use as components in applications intended to support or sustain life Atmel Corporation 2007 All rights reserved Atmel logo and combinations thereof are registered trademarks and Everywhere You Are are the trademarks of Atmel Corporation or its subsidiaries Other terms and product names may be trademarks of others Printed on recycled paper 4338F USB 08 07 xM
116. d Packet Bit Counter 4338F USB 08 07 The SIE performs the following functions NRZI data encoding and decoding Bit stuffing and un stuffing CRC generation and checking Handshakes TOKEN type identifying Address checking Clock generation via DPLL Address Decoder DataOut Serial to 8 Parallel Conversion 7 o gt Clock SysClk Recovery gt 12 MHz 2 Clk48 eneration Chec 48 MHz USB Pattern Generator Parallel to Serial Converter Bit Stuffing 8 NRZI Converter gt Dataln 7 0 CRC16 Generator 7 0 AMEL 117 Function Interface Unit FIU AMEL The Function Interface Unit provides the interface between the 89 5131 and the SIE It manages transactions at the packet level with minimal intervention from the device firmware which reads and writes the endpoint FIFOs Figure 58 UFI Block Diagram DPLL SIE OUT Transactions HOST UFI C51 OUT IN Transactions HOST UFI IN FIU Asynchronous Information C51 Transfer Microcontroller lt lt Transfer Interface Control i 6 R
117. data lines MOSI and MISO A Slave Select line SS allows individual selection of a Slave SPI device Slave devices that are not selected do not interfere with SPI bus activities When the Master device transmits data to the Slave device via the MOSI line the Slave device responds by sending data to the Master device via the MISO line This implies full duplex transmission with both data out and data in synchronized with the same clock Figure 44 4338F USB 08 07 es 189 5131 1 Master Mode Slave Mode Transmission Formats 4338F USB 08 07 Figure 44 Full duplex Master Slave Interconnection 8 bit Shift Register MISO MISO 8 bit Shift Register B 1 MOSI MOSS ii SPI SCK SCK Clock Generator 58400 88 Master MCU Slave MCU The SPI operates in Master mode when the Master bit MSTR in the SPCON register is set Only one Master SPI device can initiate transmissions Software begins the trans mission from a Master SPI module by writing to the Serial Peripheral Data Register SPDAT If the shift register is empty the byte is immediately transferred to the shift register The byte begins shifting out on MOSI pin under the control of the serial clock SCK Simultaneously another byte shifts in from the Slave on the Master s MISO pin The transmission ends when the Serial Peripheral transfer data flag SPIF in SPSTA becomes set At the same time t
118. ddressed separately For slave A bit the LSB is a don t care bit for slaves and C bit 0 is a 1 To commu nicate with slave A only the master must send an address where bit 0 is clear e g 1111 00005 For slave A bit 1 is a 1 for slaves C bit 1 is a don t care bit To communicate with slaves B and C but not slave A the master must send an address with bits O and 1 both set e g 1111 00110 To communicate with slaves A B and C the master must send an address with bit O set bit 1 clear and bit 2 clear e g 1111 00010 A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don t care bits e g SADDRO0101 01100 SADEN1111 11000 Broadcast SADDR OR 1111 111Xb The use of don t care bits provides flexibility in defining the broadcast address in most applications a broadcast address is FFh The following is an example of using broad cast addresses Slave A SADDR1111 00016 1111 10106 Broadcast1111 1X11b Slave B SADDR1111 0011b 1111 10016 Broadcast1111 1X11B Slave C SADDR 1111 0011b SADEN1111 11016 Broadcast1111 11110 For slaves A and B bit 2 is a don t care bit for slave C bit 2 is set To communicate with all of the slaves the master must send an address FFh To communicate with slaves A and B but not slave C the master can send and address FBh On reset the SADDR and SADEN registers are init
119. dpoint FIFO Bank 1 Write Byte 2 NEC Endpoint FIFO Bank 1 Write Byte m TXCMPL DATAO n Bytes ACK gt Clear TXCMPL Set TXRDY Endpoint FIFO Bank 0 Write Byte 1 Endpoint FIFO Bank 0 Write Byte 2 Endpoint FIFO Bank 0 Write Byte p TXCMPL DATA1 m Bytes ACK gt Clear TXCMPL IN Set TXRDY DATAO p Bytes Endpoint FIFO Bank 1 Write Byte 1 ACK An endpoint will be first enabled and configured before being able to send Bulk or Inter rupt packets The firmware will fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning the endpoint The FIFO banks are automatically switched and the firmware can immediately write into the endpoint FIFO bank 1 When the IN packet concerning the bank 0 has been sent and acknowledged by the Host the TXCMPL bit is set by the USB controller This triggers a USB interrupt if enabled The firmware will clear the TXCMPL bit before filling the endpoint FIFO bank 0 with new data The FIFO banks are then automatically switched When the IN packet concerning the bank 1 has been sent and acknowledged by the Host the TXCMPL bit
120. dpoint Interrupt Register on page 145 It will be cleared by the device firmware after reading the SETUP data from the endpoint FIFO Received OUT Data Bank 0 see also RXOUTB1 bit for Ping pong Endpoints This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 0 Then the endpoint interrupt is triggered if enabled see UEPINT Register UEPINT S F8h read only USB Endpoint Interrupt Register on 1 RXOUTBO 145 and all the following OUT packets to the endpoint bank 0 are rejected NAK ed until this bit has been cleared excepted for Isochronous Endpoints However for control endpoints an early SETUP transaction may overwrite the content of the endpoint FIFO even if its Data packet is received while this bit is set This bit will be cleared by the device firmware after reading the OUT data from the endpoint FIFO Transmitted IN Data Complete This bit is set by hardware after an IN packet has been transmitted for Isochronous endpoints and after it has been 0 TXCMPL accepted ACK ed by the host for Control Bulk and Interrupt endpoints Then the endpoint interrupt is triggered if enabled see UEPINT Register UEPINT S F8h read only USB Endpoint Interrupt Register on page 145 This bit will be cleared by the device firmware before setting TXRDY Reset Value 00h A MEL 141 4338F USB 08 07 142 AMEL Table 99 UEPDATX Register UEPDATX S CFh USB FI
121. e modules Its clock input can be programmed to count any one of the following signals e Peripheral clock frequency periph 6 e Peripheral clock frequency 2 Timer 0 overflow e External input on P1 2 Each compare capture modules can be programmed in any one of the following modes rising and or falling edge capture Software timer high speed output or pulse width modulator Module 4 can also be programmed as a watchdog timer see Section PCA Watchdog Timer page 65 When the compare capture modules are programmed in the capture mode software timer or high speed output mode an interrupt can be generated when the module exe cutes its function All five modules plus the PCA timer overflow share one interrupt vector The PCA timer counter and compare capture modules share Port 1 for external I O These pins are listed below If the port pin is not used for the PCA it can still be used for standard I O PCA Component External I O Pin 16 bit Counter P1 2 ECI 16 bit Module 0 P1 3 CEXO 16 bit Module 1 P1 4 CEX1 16 bit Module 2 P1 5 CEX2 16 bit Module 3 P1 6 CEX3 16 bit Module 4 P1 7 CEX4 The PCA timer is a common time base for all five modules see Figure 28 The timer count source is determined from the CPS1 and CPSO bits in the CMOD register Table 48 and can be programmed to run at e 1 6 the peripheral clock frequency
122. e three methods for programming the Flash memory Erasure The Atmel bootloader located in 1 is activated by the application Low level routines located in FM1 will be used to program FMO The interface used for serial downloading to FMO is the USB API can be called also by user s bootloader located FMO at SBV OOh A further method exist in activating the Atmel boot loader by hardware activation See the Section Hardware Registers FMO can be programmed also by the parallel mode using a programmer Figure 22 Flash Memory Mapping FFFFh 3K Bytes IAP Bootloader F400h FM 7FFFh FM1 Mapped between F400h FFFFh Custom when API Called Bootloader SBV O0Oh 32K Bytes Flash Memory FMO 0000h AMEL 4338F USB 08 07 AMEL Boot Process Software Boot Process Many algorithms can be used for the software boot process Below are descriptions of Example the different flags and Bytes Boot Loader Jump bit BLJB This bit indicates if on RESET the user wants to jump to this application at address 0000h on FMO or execute the boot loader at address F400h on 1 BLJB 0 i e bootloader FM1 executed after a reset is the default Atmel factory pro gramming To read or modify this bit the APIs are used Boot Vector Address SBV This byte contains the MSB of the user boot loader address in FMO The default value of SBV is
123. ead from these bits is always 0 Do not set these bits Enable Wake Up CPU Interrupt Set this bit to enable Wake Up CPU Interrupt See USBIEN Register USBIEN S BEh USB Global Interrupt Enable Register on page 138 Clear this bit to disable Wake Up CPU Interrupt 5 EWUPCPU Enable End Of Reset Interrupt Set this bit to enable End Of Reset Interrupt See USBIEN Register USBIEN S BEh USB Global Interrupt Enable Register on page 138 This bit is set after reset Clear this bit to disable End Of Reset Interrupt 4 EEOFINT Enable SOF Interrupt Set this bit to enable SOF Interrupt See USBIEN Register USBIEN S BEh USB Global Interrupt Enable Register on page 138 Clear this bit to disable SOF Interrupt 3 ESOFINT Reserved The value read from these bits is always 0 Do not set these bits Enable Suspend Interrupt Set this bit to enable Suspend Interrupts see the USBIEN Register USBIEN S BEh USB Global Interrupt Enable Register on page 138 Clear this bit to disable Suspend Interrupts 0 ESPINT Reset Value 10h Table 95 USBADDR Register USBADDR S C6h USB Address Register 7 6 5 4 3 2 1 0 FEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADDO Bit Bit Number Mnemonic Description Function Enable 7 FEN Set this bit to enable the address filtering function Cleared this bit to disable the function USB Address 6 0 UADDI6 0 This field c
124. eared and the ISP is enabled The three lock bits provide different levels of protection for the on chip code and data when programmed as shown in Table 38 AMEL Default Values Software Registers AMEL Table 38 Program Lock bits Program Lock Bits Security level LBO LB1 LB2 Protection Description 1 U U U No program lock features enabled MOVC instruction executed from external program memory is disabled from fetching code bytes from any internal memory EA is sampled 2 P U U and latched on reset and further parallel programming of the Flash and of the EEPROM boot and Xdata is disabled ISP and software programming with API are still allowed Same as 2 also verify through parallel 3 X P U programming interface is disabled and serial programming ISP is still allowed 4 X X P Same as 3 also external execution is disabled Notes 1 U unprogrammed or one level 2 P programmed or zero level 3 X don t 4 WARNING Security level 2 and 3 should only be programmed after verification These security bits protect the code access through the parallel programming interface They are set by default to level 4 The code access through the ISP is still possible and is controlled by the software security bits which are stored in the extra Flash memory accessed by the ISP firmware To load a new application with the parallel programmer a chip erase must be d
125. ed The value read from these bits is always 0 Do not set these bits Byte Count MSB Most Significant Byte of the byte count of a received data packet The Least 2 0 BYCT 10 8 significant part is provided by UBYCTLX Register UBYCTLX S E2h USB Byte Count Low Register X X EPNUM set in UEPNUM Register UEPNUM S C7h USB Endpoint Number see Figure 100 on page 142 S C7h USB Endpoint Number Reset Value 00h ATMEL 143 144 AMEL Table 102 UEPRST Register UEPRST S D5h USB Endpoint FIFO Reset Register 7 6 5 4 3 2 1 0 EP6RST EP5RST EP4RST EP3RST EP2RST EP1RST EPORST Bit Bit Number Mnemonic Description 7 Reserved The value read from this bit is always 0 Do not set this bit Endpoint 6 FIFO Reset 6 5 Set this bit and reset the endpoint FIFO prior to any other operation upon hardware reset or when an USB bus reset has been received Then clear this bit to complete the reset operation and start using the FIFO Endpoint 5 FIFO Reset 5 EPSRST Set this bit and reset the endpoint FIFO prior to any other operation upon hardware reset or when an USB bus reset has been received Then clear this bit to complete the reset operation and start using the FIFO Endpoint 4 FIFO Reset 4 EPARST Set this bit and reset the endpoint FIFO prior to any other operation upon hardware reset or when an USB bus reset has been received Then clear this bit to com
126. eded loop the three last instructions until the end of a 128 bytes page Programmin The EEPROM programming consists on the following actions g 9 Writing one or more bytes of one page in the column latches Normally all bytes must belong to the same page if not the first page address will be latched and the others discarded e Launching programming by writing the control sequence 52h followed by A2h to the EECON register e EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading The end of programming is indicated by a hardware clear of the EEBUSY flag Read Data The following procedure is used to read the data stored in the EEPROM memory Set bit EEE of EECON register Stretch the MOVX to accommodate the slow access time of the column latch Set bit MO of AUXR register Load DPTR with the address to read Execute a MOVX A AMEL n 4338F USB 08 07 AMEL Registers Table 42 EECON S 0D2h EECON Register 7 6 5 4 3 2 1 0 EEPL3 EEPL2 EEPL1 EEPLO EEE EEBUSY Bit Bit Number Mnemonic Description 74 EEPL3 0 Programming Launch command bits Write 5Xh followed by AXh to EEPL to launch the programming 3 Reserved The value read from this bit is indeterminate Do not set this bit 2 Reserved The value read from this bit is indeterminate Do not set t
127. egative x 0 0 9 0 trigger CEXn 16 bit capture by a transition on X 1 1 0 0 0 X CEXn 1 0 0 1 0 0 X 16 bit Software Timer Compare mode 1 0 0 1 1 0 X 16 bit High Speed Output 1 0 0 0 0 1 0 8 bit PWM 1 0 0 1 X 0 X Watchdog Timer module 4 only There are two additional registers associated with each of the PCA modules They are CCAPnH and CCAPnL and these are the registers that store the 16 bit count when a capture occurs or a compare should occur When a module is used in the PWM mode these registers are used to control the duty cycle of the output see Table 52 and Table 53 4338F USB 08 07 189 5131 1 Table 52 CCAPnH Registers 0 4 CCAPOH PCA Module 0 Compare Capture Control Register High OFAh CCAP1H PCA Module 1 Compare Capture Control Register High OFBh CCAP2H PCA Module 2 Compare Capture Control Register High OFCh Module 3 Compare Capture Control Register High OFDh CCAP4H PCA Module 4 Compare Capture Control Register High OFEh 7 6 5 4 3 2 1 0 Bit Bit Number Mnemonic Description 7 0 _ Module Compare Capture Control CCAPnH Value Reset Value 2 XXXX XXXXb Not bit addressable Table 53 CCAPnL Registers n 0 4 CCAPOL PCA Module 0 Compare Capture Control Register Low OEAh CCAP1L PCA Module 1 Compare Capture Control Register Low OEBh CCAP2L PCA Module 2 Compare Capture Con
128. egisters Endpoint 5 Bank Endpoint 4 lt Endpoint 3 Endpoint 2 DPR Control Endpoint 1 DPR Control Up to 48 MHz USB Side Endpoint 0 lt mP side 4 UC sysclk User DPRAM Figure 59 Minimum Intervention from the USB Device Firmware DATAO n bytes OUT DATAT OUT 1 ACK interrupt C51 NACK ACK Lp Endpoint FIFO read n bytes IN IN ACK NACK DATA1 DATA1 interrupt C51 Endpoint FIFO write Endpoint FIFO write 118 C51 4338F USB 08 07 X 189 5131 1 Configuration General Configuration Endpoint Configuratio n Figure 60 Endpoint Selection USB controller enable Before any USB transaction the 48 MHz required by the USB controller must be correctly generated See Clock Controller on page 13 The USB controller will be then enabled by setting the EUSB bit in the USBCON register Set address After a Reset or a USB reset the software has to set the FEN Function Enable bit in the USBADDR register This action will allow the USB controller to answer to the requests sent at the address 0 When a SET ADDRESS request has been received the USB controller must only answer to the address defined by the request The new address will be stored in the USBADDR register The FEN bit and the FADDEN bit in the USBCON register will be set to allow the USB controller to answer only to requests sent at the new address S
129. endpoint FIFO for the next transaction The data stage management is similar to Bulk management A Control endpoint is managed by the USB controller as a full duplex endpoint IN and OUT All other endpoint types are managed as half duplex endpoint IN or OUT The firmware has to specify the control endpoint direction for the data stage using the DIR bit in the UEPSTAX register The firmware has to use the DIR bit before data IN in order to meet the data toggle requirements If the data stage consists of INs the firmware has to set the DIR bit in the UEPSTAX register before writing into the FIFO and sending the data by setting to 1 the TXRDY bit in the UEPSTAX register The IN transaction is complete when the TXCMPL has been set by the hardware The firmware will clear the bit before any other transaction Ifthe data stage consists of OUTS the firmware has to leave the DIR bit at 0 The RXOUTBO bit is set by hardware when a new valid packet has been received on the endpoint The firmware must read the data stored into the FIFO and then clear the RXOUTBO bit to reset the FIFO and to allow the next transaction To send a STALL handshake see STALL Handshake on page 129 The DIR bit in the UEPSTAX register will be reset at 0 for IN and OUT status stage The status stage management is similar to Bulk management e Control Write transaction or a No Data Control transaction the status stage consists of a IN Zero Length
130. er a power down mode can be invoked by software refer to Table 13 PCON register In power down mode the oscillator is stopped and the instruction that invoked power down mode is the last instruction executed The internal RAM and SFRs retain their value until the power down mode is terminated can be lowered to save further power Either a hardware reset or an external interrupt can cause an exit from power down To properly terminate power down the reset or external interrupt should not be executed before is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize Only e external interrupt INTO e external interrupt INT1 Keyboard interrupt and USB Interrupt are useful to exit from power down For that interrupt must be enabled and configured as level or edge sensitive interrupt input When Keyboard Interrupt occurs after a power down mode 1024 clocks are necessary to exit to power down mode and enter in oper ating mode Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 77 When both interrupts are enabled the oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first input is released In this case the higher priority interrupt service routine is executed Once the interrupt is serviced the next instruction to be executed after RET
131. erate an interrupt request KBEO Keyboard line 0 Enable bit Cleared to enable standard pin Set to enable KBF 0 bit in KBF register to generate an interrupt request Reset Value 0000 0000b ATMEL 87 88 AMEL Table 70 KBLS Register KBLS Keyboard Level Selector Register 9Ch 7 5 4 3 2 KBLS7 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLSO Bit Number Bit Mnemonic Description KBLS7 Keyboard line 7 Level Selection bit Cleared to enable a low level detection on Port line 7 Set to enable a high level detection on Port line 7 KBLS6 Keyboard line 6 Level Selection bit Cleared to enable a low level detection on Port line 6 Set to enable a high level detection on Port line 6 KBLS5 Keyboard line 5 Level Selection bit Cleared to enable a low level detection on Port line 5 Set to enable a high level detection on Port line 5 KBLS4 Keyboard line 4 Level Selection bit Cleared to enable a low level detection on Port line 4 Set to enable a high level detection on Port line 4 KBLS3 Keyboard line 3 Level Selection bit Cleared to enable a low level detection on Port line 3 Set to enable a high level detection on Port line 3 KBLS2 Keyboard line 2 Level Selection bit Cleared to enable a low level detection on Port line 2 Set to enable a high level detection on Port line 2 KBLS1 Keyboard
132. et configuration The CONFG bit in the USBCON register has to be set after a SET CONFIGURATION request with a non zero value Otherwise this bit has to be cleared Selection of an Endpoint The endpoint register access is performed using the UEPNUM register The registers UEPSTAX UEPCONX UEPDATX UBYCTLX UBYCTHX These registers correspond to the endpoint whose number is stored in the UEP NUM register To select an Endpoint the firmware has to write the endpoint number in the UEPNUM register UEPSTAO UEPCONO UEPDATO 9 0 Endpoint 0 UBYCTHO UBYCTLO SFR registers gt 1 X UEPCONX UEPDATX 4 UBYCTHX UBYCTLX 5 Endpoint 6 6 UEPCONe UEPDATe gt 6 UBYCTHe UBYCTL6 4338F USB 08 07 A MEL 119 120 AMEL Endpoint enable Before using an endpoint this one will be enabled by setting the EPEN bit in the UEPCONX register An endpoint which is not enabled won t answer to any USB request The Default Control Endpoint Endpoint 0 will always be enabled in order to answer to USB standard requests Endpoint type configuration All Standard Endpoints can be configured in Control Bulk Interrupt or Isochronous mode The Ping pong Endpoints be configured in Bulk Interrupt or Is
133. fer to PSPIH for priority level TWI Interrupt Priority bit Refer to PTWIH for priority level 0 PKBL Keyboard Interrupt Priority bit Refer to PKBH for priority level Reset Value XOXX X000b Not bit addressable 4338F USB 08 07 4338F USB 08 07 Table 66 IPH1 Register IPH1 Interrupt Priority High Register B3h 189 5131 1 7 6 5 4 3 2 1 0 PUSBH PSPIH PTWIH PKBH Bit Bit Number Mnemonic Description 7 _ Reserved The value read from this bit is indeterminate Do not set this bit USB Interrupt Priority High bit PUSBHPUSBLPriority Level 6 PUSBH 0 OLowest 0 1 1 0 1 1Highest 5 _ Reserved The value read from this bit is indeterminate Do not set this bit 4 _ Reserved The value read from this bit is indeterminate Do not set this bit 3 _ Reserved The value read from this bit is indeterminate Do not set this bit SPI Interrupt Priority High bit PSPIHPSPILPriority Level 2 PSPIH 0 OLowest 0 1 1 0 1 1Highest TWI Interrupt Priority High bit PTWIHPTWILPriority Level 1 PTWIH 0 OLowest 0 1 1 0 1 1Highest Keyboard Interrupt Priority High bit PKBHPKBLPriority Level 0 PKBH 0 OLowest 0 1 1 0 1 1Highest Reset Value XOXX X000b Not bit addressable AMEL 83 Interrupt Sources and Vector Addresses 84 AMEL Table 67 Vector Table
134. gister CCON PCA Counter Control Register D8h 7 6 5 4 3 2 1 0 CF CR m 4 CCF2 CCF1 CCFO Bit Bit Number Mnemonic Description PCA Counter Overflow flag 7 CF Set by hardware when the counter rolls over CF flags an interrupt if bit ECF in CMOD is set CF may be set by either hardware or software but can only be cleared by software PCA Counter Run control bit 6 CR Must be cleared by software to turn the PCA counter off Set by software to turn the PCA counter on Reserved The value read from this bit is indeterminate Do not set this bit PCA Module 4 interrupt flag 4 CCF4 Must be cleared by software Set by hardware when a match or capture occurs PCA Module 3 interrupt flag 3 CCF3 Must be cleared by software Set by hardware when a match or capture occurs PCA Module 2 interrupt flag 2 CCF2 Must be cleared by software Set by hardware when a match or capture occurs PCA Module 1 Interrupt Flag 1 CCF1 Must be cleared by software Set by hardware when a match or capture occurs PCA Module 0 Interrupt Flag 0 CCFO be cleared by software Set by hardware when a match or capture occurs Reset Value 000X 0000b Not bit addressable ATMEL s 4338F USB 08 07 AMEL The watchdog timer function is implemented in module 4 See Figure 31 The PCA interrupt system is shown in Figure 29 Figure 29 PC
135. guration lo Output Low Current P3 6 and P3 7 LED modes 2 4 8 mA 4 configuration 5 10 20 mA 10 configuration Note 1 20 C to 50 C Vcc 2 V 20 4338F USB 08 07 AMEL 161 AMEL USB DC Parameters 162 1 VBus 2 D 3 D 4 GND R VREF 3 2 Ds USB no Hpad Receptacle 4 1 1 5 270 Symbol Parameter Min Typ Max Unit Vrer USB Reference Voltage 3 0 3 6 V Vin Input High Voltage for D and D Driven 2 0 V Vinz Input High Voltage for D and D Floating 2 7 3 6 V Vit Input Low Voltage for D and D 0 8 V Vou Output High Voltage for D and D 2 8 3 6 V VoL Output Low Voltage for D and D 0 0 0 3 V 4338F USB 08 07 189 5131 1 AC Parameters Explanation of the AC Symbols External Program Memory Characteristics 4338F USB 08 07 Each timing symbol has 5 characters The first character is always a T stands for time The other characters depending on their positions stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for Example TAy Time for Address Valid to ALE Low Time for ALE Low to PSEN Low 40 C to 85 Vss OV 3 3V 10 0 to 40 MHz
136. hat SPIF becomes set the received byte from the Slave is transferred to the receive data register in SPDAT Software clears SPIF by reading the Serial Peripheral Status register SPSTA with the SPIF bit set and then reading the SPDAT The SPI operates in Slave mode when the Master bit in the SPCON register is cleared Before a data transmission occurs the Slave Select pin SS of the Slave device must be set to 0 SS must remain low until the transmission is complete In a Slave SPI module data enters the shift register under the control of the SCK from the Master SPI module After a byte enters the shift register it is immediately transferred to the receive data register in SPDAT and the SPIF bit is set To prevent an overflow condition Slave software must then read the SPDAT before another byte enters the shift register 9 A Slave SPI must complete the write to the SPDAT shift register at least one bus cycle before the Master SPI starts a transmission If the write to the data register is late the SPI transmits the data already in the shift register from the previous transmission Software can select any of four combinations of serial clock SCK phase and polarity using two bits in the SPCON the Clock POLarity CPOL 09 and the Clock PHAse CPHA CPOL defines the default SCK line level in idle state It has no significant effect on the transmission format CPHA defines the edges on which the input data are sampled and the
137. he USB bus was in Suspend state for at least 5 ms When the upstream resume is com pleted the UPRSM bit is reset to 0 by hardware The firmware will then clear the SDRMWUP bit Figure 67 Example of REMOTE WAKEUP Management C USB Controller Init SET FEATURE DEVICE REMOTE WAKEUP e Detection of a SUSPEND State a Set RMWUPE SPINT Y Suspend Management Need USB Resume Enable Clocks Clear SPINT UPRSM 1q Set SDMWUP UPRSM V Upstream RESUME Sent Clear SDRMWUP 132 AT89C5131 A L 4338F USB 08 07 189 5131 1 Detach Simulation In order to be re enumerated by the Host the AT89C5131A L has the possibility to sim ulate a DETACH ATTACH of the USB bus The Vper output voltage is between 3 0V and 3 6V This output can be connected to the D pull up as shown in Figure 68 This output can be put in high impedance when the DETACH bit is set to 1 in the USBCON register Maintaining this output in high imped ance for more than 3 us will simulate the disconnection of the device When resetting the DETACH bit an attach is then simulated Figure 68 Example of Connection Vaer 5 15ko 14 2 3 10 4 GND AT89C5131 V USB B Connector Figure
138. he UEPRST register in order to reset the data toggle management The SOFINT bit in the USBINT register is set when the USB controller detects a Start of Frame PID This triggers an interrupt if enabled The firmware will clear the SOFINT bit to allow the next Start of Frame detection When receiving a Start of Frame the frame number is automatically stored in the UFNUML and UFNUMH registers The CRCOK and CRCERR bits indicate if the CRC of the last Start of Frame is valid CRCOK set at 1 or corrupted CRCERR set at 1 The UFNUML and UFNUMH registers are automatically updated when receiving a new Start of Frame The Data Toggle bit is set by hardware when a DATAO packet is received and accepted by the USB controller and cleared by hardware when a DATA1 packet is received and accepted by the USB controller This bit is reset when the firmware resets the endpoint FIFO using the UEPRST register For Control endpoints each SETUP transaction starts with a DATAO and data toggling is then used as for Bulk endpoints until the end of the Data stage for a control write transfer The Status stage completes the data transfer with a DATA1 for a control read transfer For Isochronous endpoints the device firmware will ignore the data toggle A MEL 129 AMEL Suspend Resume Management Suspend Resume 130 The Suspend state can be detected by the USB controller if all the clocks are enabled and if the USB controller is enabled The bit
139. he data to be sent and set the TXRDY bit in the UEP STAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning this endpoint To send a Zero Length Packet the firmware will set the TXRDY bit without writing any data into the endpoint FIFO Until the TXRDY bit has been set by the firmware the USB controller will answer a NAK handshake for each IN requests To cancel the sending of this packet the firmware has to reset the TXRDY bit The packet stored in the endpoint FIFO is then cleared and a new packet can be written and sent When the IN packet has been sent and acknowledged by the Host the TXCMPL bit in the UEPSTAX register is set by the USB controller This triggers a USB interrupt if enabled The firmware will clear the TXCMPL bit before filling the endpoint FIFO with new data The firmware will never write more bytes than supported by the endpoint FIFO All USB retry mechanisms are automatically managed by the USB controller 124 AT89C5131A L 4338F USB 08 07 189 5131 1 Bulk Interrupt IN Transactions Figure 65 Bulk Interrupt Transactions Ping pong Mode in Ping pong Mode iii HOST UFI C51 Endpoint FIFO Bank 0 Write Byte 1 IN Endpoint FIFO Bank 0 Write Byte 2 NACK Endpoint FIFO Bank 0 Write Byte Set TXRDY Endpoint FIFO Bank 1 Write Byte 1 En
140. he receiver checks each incoming data frame for a valid stop bit An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs If a valid stop bit is not found the Framing Error bit FE in SCON register See Table 56 bit is set Software may examine FE bit after each reception to check for data errors Once set only software or a reset can clear FE bit Subsequently received frames with valid stop bits cannot clear FE bit When FE feature is enabled rises on stop bit instead of the last data bit See Figure 35 and Figure 36 Figure 35 UART Timings in Mode 1 PAD 442523 6 3 623453 CJ C3 639 Start Data Byte Stop Bit Bit RI 2 SMODO 4338F USB 08 07 es 189 5131 1 Figure 36 UART Timings in Modes 2 and 3 RXD Start Data Byte Ninth Bit Bit Bit Automatic Address The automatic address recognition feature is enabled when the multiprocessor commu Recognition nication feature is enabled SM2 bit in SCON register is set Implemented in hardware automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame Only when the serial port recognizes its own address the receiver sets RI bit in SCON register to generate an interrupt This ensures that the CPU is not interrupted by command frames addressed to other devices If desired you may enable the automa
141. hen an endpoint interrupt source has been detected on the 6 EP6INT endpoint 6 The endpoint interrupt sources are in the UEPSTAX register and can be TXCMP RXOUTBO 1 RXSETUP or STLCRC A USB interrupt is triggered when the EP6IE bit in the UEPIEN register is set This bit is cleared by hardware when all the endpoint interrupt sources are cleared Endpoint 5 Interrupt This bit is set by hardware when an endpoint interrupt source has been detected on the 5 endpoint 5 The endpoint interrupt sources are in the UEPSTAX register and can be TXCMP RXOUTBO 1 RXSETUP or STLCRC A USB interrupt is triggered when the bit in the UEPIEN register is set This bit is cleared by hardware when all the endpoint interrupt sources are cleared Endpoint 4 Interrupt This bit is set by hardware when an endpoint interrupt source has been detected on the 4 EPAINT endpoint 4 The endpoint interrupt sources are in the UEPSTAX register and can be TXCMP RXOUTBO 1 RXSETUP or STLCRC A USB interrupt is triggered when the bit in the UEPIEN register is set This bit is cleared by hardware when all the endpoint interrupt sources are cleared Endpoint 3 Interrupt This bit is set by hardware when an endpoint interrupt source has been detected on the 3 EP3INT endpoint The endpoint interrupt sources are in the UEPSTAX register and can be TXCMP RXOUTBO 1 RXSETU
142. his bit Enable EEPROM Space bit 1 EEE Set to map the EEPROM space during MOVX instructions Write in the column latches Clear to map the ERAM space during MOVX Programming Busy flag Set by hardware when programming is in progress 0 EEBUSY 2722 Cleared by hardware when programming is done Cannot be set or cleared by software Reset Value XXXX XX00b Not bit addressable 4338F USB 08 07 189 5131 1 In System With the implementation of the User Space FMO and the Boot Space FM1 in Flash Proarammin ISP technology the AT89C5131 allows the system engineer the development of applications 9 5 with very high level of flexibility This flexibility is based on the possibility to alter the customer program at any stages of a product s life e Before mounting the chip on the PCB FMO flash can be programmed with the application code FM1 is always preprogrammed by Atmel with a USB bootloader Once the chip is mounted on the PCB it can be programmed by serial mode via the USB bus Note 1 The user also program his own bootloader FM1 This ISP allows code modification over the total lifetime of the product Besides the default Bootloaders Atmel provide customers all the needed Application Programming Interfaces API which are needed for the ISP The API are located in the Boot memory This allow the customer to have a full use of the 32 Kbyte user memory Flash Programming and There ar
143. ialized to 00h i e the given and broadcast addresses are all don t care bits This ensures that the serial port will reply to any address and so that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition SADEN Slave Address Mask Register B9h 7 6 5 4 3 2 1 0 Reset Value 0000 0000b Not bit addressable 4338F USB 08 07 189 5131 1 Baud Rate Selection for UART for Mode 1 and 3 Baud Rate Selection Table for UART Internal Baud Rate Generator BRG 4338F USB 08 07 SADDR Slave Address Register A9h 7 6 5 4 3 2 1 0 Reset Value 0000 0000b Not bit addressable The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers Figure 37 Baud Rate Selection TIMER1 0 TIMER BRG RX 2 TIMER2 16 A Rx Clock INT RBCK TIMER1 0 TIMER BRG TX TIMER2 716 a Tx Clock TCLK INT Clock Source Clock Source T2CON T2CON BDRCON BDRCON UART Tx UART Rx 0 0 0 0 Timer 1 Timer 1 1 0 0 0 Timer 2 Timer 1 0 1 0 0 Timer 1 Timer 2 1 1 0 0 Timer 2 Timer 2 X 0 1 0 INT BRG Time
144. ily Code Erasable 60 Copy of the Device ID 2 AT89C5131A L 32 Kbyte Memories Copy of the Device ID 3 AT89C5131A L 32 Kbyte 61 DFh revision 0 After programming the part by ISP the BSB must be cleared 00h in order to allow the application to boot at 0000h The content of the Software Security Byte SSB is described in Table 40 and Table 41 To assure code protection from a parallel access the HSB must also be at the required level Table 40 Software Security Byte SSB 7 6 5 4 3 2 1 0 5 3 1 LBO Bit Bit Number Mnemonic Description 7 _ Reserved Do not clear this bit 6 _ Reserved Do not clear this bit 5 Reserved Do not clear this bit 4 _ Reserved Do not clear this bit 3 Reserved Do not clear this bit 2 _ Reserved Do not clear this bit User Memory Lock Bits 1 0 LB1 0 See Table 41 The two lock bits provide different levels of protection for the on chip code and data when programmed as shown to Table 41 AMEL Flash Memory Status AMEL Table 41 Program Lock Bits of the SSB Program Lock Bits Security Level LBO LB1 Protection Description 1 U U No program lock features enabled 2 P U ISP programming of the Flash is disabled 3 P P Same as 2 also verify through ISP programming interface is disabled Notes 1 U unprogrammed or one level 2
145. ing the circuit from the board The ONCE mode is invoked by driving cer tain pins of the AT89C5131A L the following sequence must be exercised e ALE low while the device is in reset RST high and PSEN is high Hold ALE low as RST is deactivated While the AT89C5131A L is in ONCE mode an emulator or test CPU can be used to drive the circuit Table 111 shows the status of the port pins during ONCE mode Normal operation is restored when normal reset is applied Table 111 External Pin Status during ONCE Mode ALE PSEN Port 0 Port 1 Port 2 Port 3 Port 12 XTAL1 2 Weak Weak Float Weak Weak Weak Float Active pull up pull up pull up pull up pull up A MEL 157 Reduced Mode 158 AMEL The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory Nevertheless during internal code execution ALE signal is still generated In order to reduce EMI ALE signal can be disabled by setting AO bit The AO bit is located in AUXR register at bit location 0 As soon as AO is set ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches During ALE disabling ALE pin is weakly pulled high Table 112 AUXR Register AUXR Auxiliary Register 8Eh 7 6 5 4 3 2 1 0 DPU MO XRS1 XRSO EXTRAM AO Bit Bit Number Mnemonic Description Disable Weak P
146. ithout wait state Byte or page erase and programming 10 ms Typical programming time 32 Kbytes in 10 sec Parallel programming with 87C51 compatible hardware interface to programmer Programmable security for the code in the Flash e 100 write cycles 10 years data retention The 32 Kbytes Flash is programmed by bytes or by pages of 128 bytes It is not neces sary to erase a byte or a page before programming The programming of a byte or a page includes a self erase before programming There are three methods of programming the Flash memory 1 The on chip ISP bootloader may be invoked which will use low level routines to program the pages The interface used for serial downloading of Flash is the USB 2 The Flash may be programmed or erased in the end user application by calling low level routines through a common entry point in the Boot Flash 3 The Flash may be programmed using the parallel method The bootloader and the Application Programming Interface API routines are located in the Flash Bootloader 4338F USB 08 07 189 5131 1 Flash Registers Memory Map Hardware Registers Bootloader Jump Bit BLJB Flash Memory Lock Bits 4338F USB 08 07 The AT89C5131A L Flash memory uses several registers Hardware register can be accessed with a parallel programmer Some bits of the hardware register can be changed also by API i e X2 and bits of Hardware security B
147. ition will be transmitted when the bus becomes free C8h Last data byte in SSDAT has been transmitted 0 has been received No SSDAT action or 0 No SSDAT action or 0 No SSDAT action or 1 No SSDAT action 1 Switched to the not addressed slave mode no recognition of own SLA or GCA Switched to the not addressed slave mode own SLA will be recognised GCA will be recognised if GC logic 1 Switched to the not addressed slave mode no recognition of own SLA or GCA A START condition will be transmitted when the bus becomes free Switched to the not addressed slave mode own SLA will be recognised GCA will be recognised if GC logic 1 A START condition will be transmitted when the bus becomes free Table 85 Miscellaneous Status Application Software Response To from To SSCON Status Status of the 2 wire SSDAT Code bus and 2 wire Next Action Taken By 2 wire SSCS hardware STA STO SI AA Software No relevant state F8h information nb SSDAT No SSCON action Wait or proceed current transfer action available SI 0 Only the internal hardware is Bus error due to an No SSDAT affected no STOP condition is 00h illegal START or 0 1 0 X the bus In all cases STOP condition the bus is released and STO is reset 4338F USB 08 07 AMEL 113 Registers AMEL Table 86 SSCON Register SSCO
148. l data pointer a 16 bit up down Timer T2 a Programmable Counter Array up to 4 programmable LED current sources a programmable hardware watchdog and a power on reset AT89C5131A L has two software selectable modes of reduced activity for further reduc tion in power consumption In the idle mode the CPU is frozen while the timers the serial ports and the interrupt system are still operating In the power down mode the RAM is saved the peripheral clock is frozen but the device has full wake up capability through USB events or external interrupts 4338F USB 08 07 189 5131 1 Block Diagram XTAL2 EEPROM ERAM 1K B2Kx8 Flash 4Kx8 x8 2 SPI 1 1 PSEN RD a 2 0 Parallel I O Ports amp Ext Bus Key Watch USB Regu gt 1 Board Dog lator d WR 2 Port OPort 1 Port 2Port 3Port 4 VR F b BE 2 E g z jx 2 2 x aa Notes 1 Alternate function of Port 1 2 Alternate function of Port 3 3 Alternate function of Port 4 ATMEL 4338F USB 08 07 Pinout Description AMEL Pinout Figure 1 AT89C5131A L 52 pin PLCC Pinout 05 amp N x 222 ZZuaz x x
149. l clock cycle Set to select 12 clock periods per peripheral clock cycle Timer1 Clock This control bit is validated when the CPU clock X2 is set When X2 is low 2 T1X2 this bit has no effect Clear to select 6 clock periods per peripheral clock cycle Set to select 12 clock periods per peripheral clock cycle 0 Clock This control bit is validated when the CPU clock X2 is set When X2 is low 1 TOX2 this bit has no effect Clear to select 6 clock periods per peripheral clock cycle Set to select 12 clock periods per peripheral clock cycle System Clock Control bit Clear to select 12 clock periods per machine cycle STD mode Fper 0 2 Set to select 6 clock periods per machine cycle X2 mode Fper Fosc Reset Value 0000 0000b 4338F USB 08 07 es 189 5131 1 4338F USB 08 07 Table 15 CKCON1 S AFh Clock Control Register 1 7 6 5 4 3 2 1 0 SPIX2 Bit Bit Number Mnemonic Description 74 Reserved The value read from this bit is always 0 Do not set this bit SPI Clock This control bit is validated when the CPU clock X2 is set When X2 is low 0 SPIX2 this bit has no effect Clear to select 6 clock periods per peripheral clock cycle Set to select 12 clock periods per peripheral clock cycle Reset Value 0000 0000b Table 16 PLLCON S A3h PLL Control Register 7 6 5 4 3 2 1 0 48 PLLEN
150. l clock fci 6 1 CPSO 0 1 Internal clock fci 2 1 0 Timer 0 Overflow 1 1 External clock at ECI P1 2 pin max rate 4 PCA Enable Counter Overflow Interrupt 0 ECF Cleared to disable CF bit in CCON to inhibit an interrupt Set to enable CF bit in CCON to generate an interrupt Reset Value 00XX X000b Not bit addressable 56 AT89C5131A L memm 4338F USB 08 07 189 5131 1 CMOD register includes three additional bits associated with the See Figure 28 and Table 48 CIDL bit allows the PCA to stop during idle mode WDTE bit enables or disables the watchdog function on module 4 ECF bit when set causes an interrupt and the PCA overflow flag CF in the CCON SFR to be set when the PCA timer overflows The CCON register contains the run control bit for the PCA and the flags for the PCA timer CF and each module see Table 49 Bit CR CCON 6 must be set by software to run the PCA The PCA is shut off by clearing this bit Bit CF The CF bit CCON 7 is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set The CF bit can only be cleared by software Bits O through 4 are the flags for the modules bit 0 for module 0 bit 1 for module 1 etc and are set by hardware when either a match or a capture occurs These flags can only be cleared by software Table 49 CCON Re
151. lable because the serial interrupt flag is not set yet This occurs between other states and when the TWI module is not involved in a serial transfer Status 00h indicates that a bus error has occurred during a TWI serial transfer A bus error is caused when a START or a STOP condition occurs at an illegal position in the format frame Examples of such illegal positions happen during the serial transfer of an address byte a data byte or an acknowledge bit When a bus error occurs SI is set To recover from a bus error the STO flag must be set and SI must be cleared This causes the TWI module to enter the not addressed slave mode and to clear the STO flag no other bits in SSCON are affected The SDA and SCL lines are released and no STOP condition is transmitted the TWI module interfaces to the external 2 wire bus via two port pins SCL serial clock line and SDA serial data line To avoid low level asserting on these lines when the TWI module is enabled the output latches of SDA and SLC must be set to logic 1 Table 80 Bit Frequency Configuration Bit Frequency kHz CR2 CR1 CRO 12 MHz Fosca 16 MHz Fosca divided by 0 0 0 47 62 5 256 0 0 1 53 5 71 5 224 0 1 0 62 5 83 192 0 1 1 75 100 160 1 0 0 5 Unused 1 0 1 100 133 3 120 1 1 0 200 266 6 60 Timer 1 in mode 2 be used as TWI 1 1 1 05 lt lt 625 0 67 lt lt 83 baudrate generator with the following formula 96 256 Time
152. mmed level It generates a Keyboard interrupt request if the KBIE 6 bit in KBIE register is set Cleared by hardware when reading KBF SFR by software 6 KBF6 Keyboard line 5 flag Set by hardware when the Port line 5 detects a programmed level It generates a Keyboard interrupt request if the KBIE 5 bit in KBIE register is set Cleared by hardware when reading KBF SFR by software 5 KBF5 Keyboard line 4 flag Set by hardware when the Port line 4 detects a programmed level It generates a Keyboard interrupt request if the KBIE 4 bit in KBIE register is set Cleared by hardware when reading KBF SFR by software 4 KBF4 Keyboard line 3 flag Set by hardware when the Port line 3 detects a programmed level It generates a Keyboard interrupt request if the KBIE 3 bit in KBIE register is set Cleared by hardware when reading KBF SFR by software 3 KBF3 Keyboard line 2 flag Set by hardware when the Port line 2 detects a programmed level It generates a Keyboard interrupt request if the KBIE 2 bit in KBIE register is set Must be cleared by software 2 KBF2 Keyboard line 1 flag Set by hardware when the Port line 1 detects a programmed level It generates a Keyboard interrupt request if the KBIE 1 bit in KBIE register is set Cleared by hardware when reading KBF SFR by software 1 KBF1 Keyboard line 0 flag Set by hardware when the Port line 0 detects a programmed level It generates a Keyboard interrupt re
153. nd SSSTO flag will be reset Data byte has been Read data byte 0 0 0 0 Data byte will be received and NOT ACK will be 50h received has returned been returned Read data byte 0 0 0 1 Data byte will be received and ACK will be returned Read data byte 1 0 0 X Repeated START wili be transmitted Data byte has been Read data byte 0 1 0 STOP condition will be transmitted and SSSTO flag 58h received ACK y will be reset has been returned STOP condition followed by a START condition will Read data byte 1 0 be transmitted and SSSTO flag will be reset 108 AT89C5131 A L E 4338F USB 08 07 Figure 54 Format and State in the Slave Receiver Mode Reception of the own slave address and one or S SLA W Data Data A 5 more data bytes All are acknowledged Last data byte received 60h is not acknowledged A PorS Y 88h Arbitration lost as master addressed as slave 68h Reception of the general call address and or more data General Call A Data Data 5 bytes Last data byte received is not acknowledged Arbitration lost as master and addressed as slave by general call 70h 78h A PorS 98h From master to slave acknowledge bits 4338F USB 08 07 From slave to master
154. nded if other PCA mod ules are being used Remember the PCA timer is the time base for all modules changing the time base for other modules would not be a good idea Thus in most appli cations the first solution is the best option This watchdog timer won t generate a reset out on the reset pin AMEL 5 4338F USB 08 07 Serial I O Port Framing Error Detection AMEL The serial port in the AT89C5131A L is compatible with the serial port in the 80 52 It provides both synchronous and asynchronous communication modes It operates as an Universal Asynchronous Receiver and Transmitter UART in three full duplex modes modes 1 2 and 3 Asynchronous transmission and reception can occur simul taneously and at different baud rates Serial I O port includes the following enhancements Framing error detection e Automatic address recognition Framing bit error detection is provided for the three asynchronous modes modes 1 2 and 3 To enable the framing bit error detection feature set SMODO bit in PCON regis ter see Figure 34 Figure 34 Framing Error Block Diagram SMOIFE SM1 sme REN TB8 RB8 RI SCON 98h 04 Set FE Bit if Stop Bit is 0 framing error SMODO hc SMO to UART Mode Control SMODO 0 Svoor svood POF GF1 ero IDL PCON 87h To UART Framing Error Control When this feature is enabled t
155. ndpoint 0 Interrupt Enable Set this bit to enable the interrupts for thi Clear this bit to disable the interrupts for s endpoint this endpoint Reset Value 00h 4338F USB 08 07 es 189 5131 1 Table 105 UFNUMH Register UFNUMH S BBh read only USB Frame Number High Register 7 6 5 4 3 2 1 0 CRCOK CRCERR FNUM10 FNUM9 FNUM8 Bit Bit Number Mnemonic Description Frame Number CRC OK This bit is set by hardware when a new Frame Number in Start of Frame Packet 5 CRCOK _ jis received without CRC error This bit is updated after every Start of Frame packet receipt Important note the Start of Frame interrupt is generated just after the PID receipt Frame Number CRC Error This bit is set by hardware when a corrupted Frame Number in Start of Frame 4 CRCERR is received This bit is updated after every Start of Frame packet receipt Important note the Start of Frame interrupt is generated just after the PID receipt 3 _ Reserved The value read from this bit is always 0 Do not set this bit Frame Number FNUN 10 8 are the upper bits of the 11 bit Frame Number see the UFNUML 2 0 FNUM 10 8 Register UFNUML S BAh read only USB Frame Number Low Register on page 147 It is provided in the last received SOF packet see SOFINT in the USBIEN Register USBIEN S BEh USB Global Interrupt Enable Register on page 138 FNUM is updated if a c
156. nm CL PCA Counter Timer ECOMn CAPPn CAPNn TOGn PWMn ECCFn CCAPMn n 0 to 4 OxDA to 0 PCA Watchdog Timer An on board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count Watchdog timers are useful for systems that are susceptible to noise power glitches or electrostatic discharge Module 4 is the only PCA module that can be programmed as a watchdog However this module can still be used for other modes if the watchdog is not needed Figure 31 shows a diagram of how the watchdog works The user pre loads a 16 bit value in the compare registers Just like the other compare modes this 16 bit value is compared to the PCA timer value If a match is allowed to occur an internal reset will be generated This will not cause the RST pin to be driven low In order to hold off the reset the user has three options 1 Periodically change the compare value so it will never match the PCA timer 2 Periodically change the PCA timer value so it will never match the compare val ues or 3 Disable the watchdog by clearing the WDTE bit before a match occurs and then re enable it The first two options are more reliable because the watchdog timer is never disabled as in option 3 If the program counter ever goes astray a match will eventually occur and cause an internal reset The second option is also not recomme
157. ns when these pins make 1 to 0 transitions during bus operation In the worst cases capacitive loading 100 pF the noise pulse on the ALE line may exceed 0 45V with maxi Vo peak 0 6V A Schmitt Trigger use is not necessary 5 Typicals are based on a limited number of samples and are not guaranteed The values listed are at room temperature 6 Under steady state non transient conditions Io must be externally limited as follows Maximum lo per port pin 10 mA Maximum lo per 8 bit port Port 0 26 mA Ports 1 2 and 3 15 mA Maximum total lo for all output pins 71 mA If lg exceeds the test condition Vg may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions Figure 78 Test Condition Active Mode Voc NC CLOCK SIGNAL other pins are disconnected 160 AT89C5131 A L a _ 2 4338F USB 08 07 X 189 5131 1 Figure 79 lc Test Condition Idle Mode NC CLOCK SIGNAL other pins are disconnected Figure 80 Test Condition Power down Mode other pins are disconnected Figure 81 Clock Signal Waveform for Tests in Active and Idle Modes 9 5 0 7Vec Nazis Tenc Touch 518 LED s Table 113 LED Outputs DC Parameters Symbol Parameter Min Typ Max Unit Test Conditions 2 4 mA 2 confi
158. nsmitted the serial interrupt flag SI bit in SSCON is set and the status code in SSCS will be 08h This status must be used to vector to an interrupt routine that loads SSDAT with the slave address and the data direction bit SLA W When the slave address and the direction bit have been transmitted and an acknowl edgement bit has been received SI is set again and a number of status code in SSCS are possible There are 18h 20h or 38h for the master mode and also 68h 78h or BOh if the slave mode was enabled AA logic 1 The appropriate action to be taken for each of these status code is detailed in Table This scheme is repeated until a STOP condi tion is transmitted SSIE CR2 1 and are not affected by the serial transfer and are referred to Table 7 to Table 11 After a repeated START condition state 10h the TWI module may switch to the master receiver mode by loading SSDAT with SLA R In the master receiver mode a number of data bytes are received from a slave transmit ter Figure 53 The transfer is initialized as in the master transmitter mode When the START condition has been transmitted the interrupt routine must load SSDAT with the 7 bit slave address and the data direction bit SLA R The serial interrupt flag SI must then be cleared before the serial transfer can continue When the slave address and the direction bit have been transmitted and an acknowl edgement bit has been received the serial interrupt flag
159. nsmitted or a byte which has just been received It is addressable while it is not in process of shifting a byte This occurs when 2 wire logic is in a defined state and the serial interrupt flag is set Data in SSDAT remains stable as long as SI is set While data is being shifted out data on the bus is simultaneously shifted in SSDAT always contains the last byte present on the bus SSADR may be loaded with the 7 bit slave address 7 most significant bits to which the TWI module will respond when programmed as a slave transmitter or receiver The LSB is used to enable general call address 00h recognition Figure 51 shows how a data transfer is accomplished on the 2 wire bus Figure 51 Complete Data Transfer on 2 wire Bus _ KXAN LAN _ acknowledgement acknowledgement signal from receiver signal from receiver SCL AAAs f stat clock line held low stop condition while interrupts are serviced condition The four operating modes are Master Transmitter Master Receiver Slave transmitter Slave receiver Data transfer in each mode of operation is shown in Table to Table 85 and Figure 52 to Figure 55 These figures contain the following abbreviations S START condition Read bit high level at SDA W Write bit low level at SDA A MEL 101 Master Transmitter Mode Master Receiver Mode AMEL A Ackn
160. o not set this bit Enable Comparator 6 ECOMn Cleared to disable the comparator function Set to enable the comparator function Capture Positive 5 CAPPn Cleared to disable positive edge capture Set to enable positive edge capture Capture Negative 4 CAPNn Cleared to disable negative edge capture Set to enable negative edge capture Match When 1 a match of the counter with this module s compare capture register causes the CCFn bit in CCON to be set flagging an interrupt 3 MATn Toggle 2 TOGn When TOGn 1 a match of the PCA counter with this module s compare capture register causes the CEXn pin to toggle Pulse Width Modulation Mode 1 PWMn Cleared to disable the CEXn pin to be used as a pulse width modulated output Set to enable the CEXn pin to be used as a pulse width modulated output Enable CCF Interrupt Cleared to disable compare capture flag CCFn in the CCON register to 0 ECCFn generate an interrupt Set to enable compare capture flag CCFn in the CCON register to generate an interrupt Reset Value X000 0000b Not bit addressable AMEL 5 4338F USB 08 07 60 Table 51 Module Modes CCAPMn Registers AMEL PWM ECCF ECOMn CAPPn CAPNn MATn TOGn m n Module Function 0 0 0 0 0 0 0 No Operation 16 bit capture by a positive x 1 9 o 9 9 x edge trigger on CEXn 16 bit capture by a n
161. ochronous mode The configuration of an endpoint is performed by setting the field EPTYPE with the following values Control EPTYPE 00b Isochronous EPTYPE 01b Bulk EPTYPE 10b Interrupt EPTYPE 11b The Endpoint 0 is the Default Control Endpoint and will always be configured in Control type Endpoint direction configuration For Bulk Interrupt and Isochronous endpoints the direction is defined with the EPDIR bit of the UEPCONX register with the following values IN EPDIR 1b OUT EPDIR 06 For Control endpoints the EPDIR bit has no effect Summary of Endpoint Configuration Do not forget to select the correct endpoint number in the UEPNUM register before accessing to endpoint specific registers Table 90 Summary of Endpoint Configuration Endpoint Configuration EPEN EPDIR EPTYPE UEPCONX Disabled Ob Xb XXb OXXX XXXb Control 1b Xb 00b 80h Bulk in 1b 1b 10b 86h Bulk out 1b Ob 10b 82h Interrupt In 1b 1b 110 87h Interrupt Out 1b 05 110 83h Isochronous In 1b 1b 01b 85h Isochronous Out 1b Ob 01b 81h 4338F USB 08 07 es 189 5131 1 Read Write Data FIFO FIFO Mapping Endpoint FIFO reset Before using an endpoint its FIFO will be reset This action resets the FIFO pointer to its original value resets the byte counter of the endpoint UBYCTLX and UBYCTHX registers and resets the data toggle bit bit in UEPCONX The reset of an endpoint FIF
162. ode nescit teda aite ce ep aod aa tede nna 62 16 bit Software Timer Compare 2 62 High Speed Output 63 Pulse Width Modulator 64 Watchdog 65 SEA dama daa Qin Rd 66 Framing Error Detection 66 Automatic Address 67 Baud Rate Selection for UART for Mode 1 69 UART Emm 72 Interr pt System 76 ae ashe aes 76 77 Interrupt Sources and Vector 00 84 T 85 INTROGUCTION pcc CRUS 85 11161 c 85 528 sete 86 Programmable LED raa hd reed eR FERE Ea SR KUNA 89 Serial Peripheral Interface SPI uus 90 90 Signal D scriptiOn wee 90 Functional Description etre RR Ern trn Ttc 92 Two Wire Interface TWI reser rere nnne nnne nnn 99 BIcIegom p M
163. oi SP 8th Stack Pointer LSB of SPX Data Pointer DPL 82h Low byte LSB of DPTR Data Pointer DPH 83h High byte MSB of DPTR Table 20 I O Port SFRs Mnemonic Add 1 0 PO 80h Port 0 P1 90h Port 1 P2 AOh Port 2 P3 BOh P4 COh Port 4 2bits 4338F USB 08 07 X 189 5131 1 Table 21 Timer SFR s Mnemonic Add Name 7 6 5 4 3 2 1 0 THO 8Ch Timer Counter 0 High byte TLO 8Ah Timer Counter 0 Low byte TH1 8Dh Timer Counter 1 High byte TL1 8Bh Timer Counter 1 Low byte TH2 CDh 2 High byte TL2 CCh 2 Low byte TCON 1 TR1 TFO TRO IE1 ITi IEO ITO control TMOD 89h 1 GATE1 1 11 M01 GATEO C To M10 M00 T2CON C8h Timer Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 2 CP RL2 T2MOD C9h Timer Counter 2 Mode 2 DCEN Timer Counter 2 en Reload Capture High byte Timer Counter 2 RCAPAL Reload Capture Low byte WDTRST A6h WatchDog Timer Reset WDTPRG A7h WatchDog Timer Program S2 51 50 Table 22 Serial Port SFR s Mnemonic Add Name 7 6 5 4 3 2 1 0 SCON 98h Serial Control FE SMO SM1 SM2 REN TB8 RB8 TI RI SBUF 99h Serial Data Buffer SADEN 9 Slave Address Mask SADDR A9h Address
164. oller won t send anything at each IN requests concerning this bank The firmware will never write more bytes than supported by the endpoint FIFO 128 AT89C5131 A L 4338F USB 08 07 X 189 5131 1 Miscellaneous USB Reset STALL Handshake Start of Frame Detection Frame Number Data Toggle Bit 4338F USB 08 07 The EORINT bit in the USBINT register is set by hardware when a End Of Reset has been detected on the USB bus This triggers a USB interrupt if enabled The USB con troller is still enabled but all the USB registers are reset by hardware The firmware will clear the EORINT bit to allow the next USB reset detection This function is only available for Control Bulk and Interrupt endpoints The firmware has to set the STALLRQ bit in the UEPSTAX register to send STALL handshake at the next request of the Host on the endpoint selected with the UEPNUM register The RXSETUP TXRDY TXCMPL RXOUTBO and RXOUTB1 bits must be first reset to 0 The bit STLCRC is set at 1 by the USB controller when a STALL has been sent This triggers an interrupt if enabled The firmware will clear the STALLRQ and STLCRC bits after each STALL sent The STALLRQ bit is cleared automatically by hardware when a valid SETUP PID is received on a CONTROL type endpoint Important note when a Clear Halt Feature occurs for an endpoint the firmware will reset this endpoint using t
165. om this bit is indeterminate Do not set this bit 3 GF3 This bit is a general purpose user flag 2 0 Always cleared 1 Reserved The value read from this bit is indeterminate Do not set this bit Data Pointer Selection 0 DPS Cleared to select DPTRO Set to select DPTR1 Reset Value XX BLJB X Not bit addressable a Bit 2 stuck at 0 this allows to use INC AUXR1 to toggle DPS without changing AMEL 25 26 AMEL ASSEMBLY LANGUAGE Block move using dual data pointers Modifies DPTRO DPTR1 A and PSW note DPS exits opposite of entry state unless an extra INC AUXR1 is added 0042 AUXR1 EQU 0A2H 0000 909000MOV DPTR SOURCE address of SOURCE 0003 05A2 INC AUXR1 switch data pointers 0005 90A000 MOV DPTR DEST address of DEST 0008 LOOP 0008 05A2 INC AUXR1 switch data pointers 000A E0 MOVX A DPTR get a byte from SOURCE 000B INC DPTR increment SOURCE address 000 05A2 INC AUXR1 switch data pointers 000E DPTR A write the byte to DEST 000F INC DPTR increment DEST address 0010 70F6JNZ LOOP check for 0 terminator 0012 05A2 INC AUXR1 optional restore DPS INC is a short 2 bytes and fast 12 clocks way to manipulate the DPS bit in the AUXR1 SFR However note that the INC instruction does not directly force the DPS bit to a par ticular state but simply toggles it In simple routines such as the block move example only the fac
166. on External Clock Input P1 2 Capture External Input d apture Ex ptu pu P1 4 CEX 4 0 1 5 4 0 Compare External Output P1 6 P1 7 Table 3 Serial Signal Description Signal Alternate Name Type Description Function Serial Input RxD P3 0 The serial input for Extended UART Serial Output TxD 9 serial output for Extended UART 1 Table 4 Timer 0 Timer 1 Timer 2 Signal Description Signal Alternate Name Type Description Function Timer 0 Gate Input INTO serves as external run control for timer 0 when selected by GATEO bit in TCON register INTO External Interrupt 0 P3 2 INTO input set IEO in the TCON register If bit ITO in this register is set bits IEO are set by a falling edge on INTO If bit ITO is cleared bits IEO is set by a low level on INTO Timer 1 Gate Input INT1 serves as external run control for Timer 1 when selected by GATE1 bit in TCON register External Interrupt 1 P3 3 input set IE1 in the TCON register If bit IT1 in this register is set bits IE1 are set by a falling edge on INT1 If bit IT1 is cleared bits IE1 is set by a low level on INT1 189 5131 1 Table 4 Timer 0 Timer 1 and Timer 2 Signal Description Continued Signal Alternate Name Type Descrip
167. one first This will set the HSB in its inactive state and will erase the Flash memory The part ref erence can always be read using Flash parallel programming modes The default value of the HSB provides parts ready to be programmed with ISP Cleared to force ISP operation e X2 Set to force X1 mode Standard Mode e OSCON1 0 Set to start with 32 MHz oscillator configuration value LB2 0 Security level four to protect the code from a parallel access with maximum security Several registers are used in factory and by parallel programmers to make copies of hardware registers contents These values are used by Atmel ISP see Section In Sys tem Programming ISP These registers are in the Extra Flash Memory part of the Flash memory This block is also called XAF or eXtra Array Flash They are accessed in the following ways Commands issued by the parallel memory programmer Commands issued by the ISP software Calls of API issued by the application software Several software registers are described in Table 39 4338F USB 08 07 es 189 5131 1 4338F USB 08 07 Table 39 Software Registers Address Mnemonic Description Default value 01 SBV Software Boot Vector FFh 00 5 Boot Status Byte OFFh 05 55 Software Security Byte FFh 30 Copy of the Manufacturer 58h Atmel Code 31 _ Copy of the Device ID 1 D7h C51 X2 Electrically Fam
168. ontains the default address 0 after power up or USB bus reset It will be written with the value set by a SET_ADDRESS request received by the device firmware Reset Value 80h 138 4338F USB 08 07 XX 189 5131 1 4338F USB 08 07 Table 96 UEPNUM Register UEPNUM S C7h USB Endpoint Number 5 4 3 2 1 0 EPNUM2 EPNUM1 EPNUMO Bit Number Bit Mnemonic Description 7 4 Reserved The value read from these bits is always 0 Do not set these bits 3 0 3 0 Endpoint Number Set this field with the number of the endpoint which will be accessed when reading or writing to UEPDATX Register UEPDATX S CFh USB FIFO Data Endpoint X X EPNUM set in UEPNUM Register UEPNUM S C7h USB Endpoint Number UBYCTLX Register UBYCTLX S E2h USB Byte Count Low Register X X EPNUM set in UEPNUM Register UEPNUM S C7h USB Endpoint Number UBYCTHX Register UBYCTHX S E3h USB Byte Count High Register X X EPNUM set in UEPNUM Register UEPNUM S C7h USB Endpoint Number or UEPCONX Register UEPCONX S D4h USB Endpoint X Control Register This value can be 0 1 2 3 4 5 6 Reset Value 00h A MEL 139 140 AMEL Table 97 UEPCONX Register UEPCONX S D4h USB Endpoint X Control Register 7 6 5 3 2 1 0 EPEN
169. orrupted SOF is received Reset Value 00h Table 106 UFNUML Register UFNUML S BAh read only USB Frame Number Low Register 7 6 5 4 3 2 1 0 FNUM7 FNUM6 FNUM5 FNUM4 FNUM3 FNUM2 FNUM1 FNUMO Bit Bit Number Mnemonic Description Frame Number 7 0 FNUMI7 0 FNUM 7 0 are the lower 8 bits of the 11 bit Frame Number See UFNUMH Register UFNUMH S BBh read only USB Frame Number High Register page 147 Reset Value 00h 4338F USB 08 07 AMEL 147 AMEL Reset Introduction The reset sources are Power Management Hardware Watchdog PCA Watchdog and Reset input Figure 72 Reset schematic Power Monitor Hardware e Internal Reset Watchdog PCA Watchdog gt Reset Input The Reset input can be used to force a reset pulse longer than the internal reset con trolled by the Power Monitor RST input has a pull up resistor allowing power on reset by simply connecting an external capacitor to Vss as shown in Figure 73 Resistor value and input characteristics are discussed in the Section Characteristics of the AT89C5131A L datasheet RST Figure 73 Reset Circuitry and Power On Reset VCC E gt Tointernal reset RST input circuitry o Power on Reset 148 AT89C5131A L 189 5131 1 Reset Output 4
170. owledge bit low level at SDA A Not acknowledge bit high level at SDA Data 8 bit data byte P STOP condition In Figure 52 to Figure 55 circles are used to indicate when the serial interrupt flag is set The numbers in the circles show the status code held in SSCS At these points a ser vice routine must be executed to continue or complete the serial transfer These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software When the serial interrupt routine is entered the status code in SSCS is used to branch to the appropriate service routine For each status code the required software action and details of the following serial transfer are given in Table to Table 85 In the master transmitter mode a number of data bytes are transmitted to a slave receiver Figure 52 Before the master transmitter mode can be entered SSCON must be initialised as follows Table 77 SSCON Initialization CR2 SSIE STA STO SI AA CR1 CRO bit rate 1 0 0 0 X bit rate bit rate CRO CR1 and CR2 define the internal serial bit rate if external bit rate generator is not used SSIE must be set to enable TWI STA STO and SI must be cleared The master transmitter mode may now be entered by setting the STA bit The 2 wire logic will now test the 2 wire bus and generate a START condition as soon as the bus becomes free When a START condition is tra
171. pe BBh 60h Copy of the Device 10 3 Name and Revision FFh 61h It is possible to force the controller to execute the bootloader after a Reset with hard ware conditions Depending on the product type low pin count or high pin count package there are two methods to apply the hardware conditions For high pin count packages the hardware conditons EA 1 PSEN 0 are sampled during the RESET rising edge to force the on chip bootloader execution See Figure 82 on page 172 In this way the bootloader can be carried out regardless of the user Flash memory content It is recommended to pull the PSEN pin down to ground though a 1K resistor to prevent the PSEN pin from being damaged See Figure 24 below Figure 24 ISP Hardware conditions ALE H gt Unconnected C2 RST XTAL2 1 GND Bootloader Crystal PSEN GND 1 VSS GND GND GND AMEL i Low Pin Count Hardware Conditions SOIC28 AMEL As PSEN is an output port in normal operating mode running user application or boot loader code after reset it is recommended to release PSEN after rising edge of reset signal Low pin count products do not have PSEN signal thus for these products the boot loader is always executed after reset thanks to the BLJB bit The Hardware Conditions are detected at the begining of
172. per 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction Instructions that use direct addressing access SFR space For example MOV OAOH data accesses the SFR at location which is P2 Instructions that use indirect addressing access the Upper 128 bytes of data RAM For example MOV atRO data where RO contains OAOh accesses the data byte at address OAOh rather than P2 whose address is OAOh ERAM bytes can be accessed by indirect addressing with EXTRAM bit cleared and MOVX instructions This part of memory which is physically located on chip logically occupies the first bytes of external data memory The bits XRSO and XRS1 are used to hide a part of the available ERAM as explained in Table 44 This can be useful if external peripherals are mapped at addresses already used by the internal ERAM e With EXTRAM 0 the ERAM is indirectly addressed using the MOVX instruction in combination with any of the registers RO R1 of the selected bank or DPTR An access to ERAM will not affect ports PO P2 P3 6 WR and P3 7 RD For example with EXTRAM 0 MOVX atRO data where RO contains accesses the ERAM at address rather than external memory An access to external data memory locations higher than the accessible size of the ERAM will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51 with PO and P2 as data address busses and
173. pin is at inappropriate logic level 2 Reserved The value read from this bit is indeterminate Do not set this bit AMEL Serial Peripheral Data Register SPDAT AMEL Bit Bit Number Mnemonic Description Reserved The value read from this bit is indeterminate Do not set this bit 1 Reserved The value read from this bit is indeterminate Do not set this bit 0 Reserved The value read from this bit is indeterminate Do not set this bit Reset Value 00X0 XXXXb Not Bit addressable The Serial Peripheral Data Register Table 76 is a read write buffer for the receive data register A write to SPDAT places data directly into the shift register No transmit buffer is available in this model A Read of the SPDAT returns the value located in the receive buffer and not the content of the shift register Table 76 SPDAT Register SPDAT Serial Peripheral Data Register 0C5H Table 2 7 6 5 4 3 2 1 0 R7 R6 R5 R4 R3 R2 R1 RO Reset Value Indeterminate R7 RO Receive data bits SPCON SPSTA and SPDAT registers may be read and written at any time while there is no on going exchange However special care should be taken when writing to them while a transmission is on going not change SPR2 SPR1 and SPRO Do change Do change MSTR e Clearing would immediately disable the peripheral e
174. plete the reset operation and start using the FIFO Endpoint 3 FIFO Reset 3 EP3RST Set this bit and reset the endpoint FIFO prior to any other operation upon hardware reset or when an USB bus reset has been received Then clear this bit to complete the reset operation and start using the FIFO Endpoint 2 FIFO Reset 2 EP2RST Set this bit and reset the endpoint FIFO prior to any other operation upon hardware reset or when an USB bus reset has been received Then clear this bit to complete the reset operation and start using the FIFO Endpoint 1 FIFO Reset 1 EP4RST Set this bit and reset the endpoint FIFO prior to any other operation upon hardware reset or when an USB bus reset has been received Then clear this bit to complete the reset operation and start using the FIFO Endpoint 0 FIFO Reset 0 EPORST Set this bit and reset the endpoint FIFO prior to any other operation upon hardware reset or when an USB bus reset has been received Then clear this bit to complete the reset operation and start using the FIFO Reset Value 00h es 189 5131 1 Table 103 UEPINT Register UEPINT S F8h read only USB Endpoint Interrupt Register 7 6 5 4 3 2 1 0 EP6INT EPSINT EPAINT 2 EPOINT Bit Bit Number Mnemonic Description Reserved The value read from this bit is always 0 Do not set this bit Endpoint 6 Interrupt This bit is set by hardware w
175. put of the on chip inverting oscillator amplifier XTAL2 To use the internal oscillator a crystal resonator circuit is connected to this pin If an external oscillator is used leave XTAL2 unconnected PLL Low Pass Filter input PLLF Receives the RC network of the PLL low pass filter See Figure 4 on page 11 189 5131 1 4338F USB 08 07 Table 10 USB Signal Description Signal Name Type Description Alternate Function D USB Data signal Set to high level under reset Vo USB Data signal Set to low level under reset VREF USB Reference Voltage Connect this pin to D using 1 5 resistor to use the Detach function Table 11 System Signal Description Signal Name Type Description Alternate Function AD 7 0 Multiplexed Address Data LSB for external access Data LSB for Slave port access used for 8 bit and 16 bit modes 7 0 15 8 Address Bus MSB for external access Data MSB for Slave port access used for 16 bit mode only 217 0 Read Signal Read signal asserted during external data memory read operation Control input for slave port read access cycles P3 7 Write Signal Write signal asserted during external data memory write operation Control input for slave write access cycles
176. quest if the KBIE 0 bit in KBIE register is set Cleared by hardware when reading KBF SFR by software 0 KBFO Reset Value 0000 00000 4338F USB 08 07 es 189 5131 1 4338F USB 08 07 Table 69 KBE Register KBE Keyboard Input Enable Register 9Dh 7 KBE7 5 4 2 KBE1 KBEO Bit Number Bit Mnemonic Description KBE7 Keyboard line 7 Enable bit Cleared to enable standard pin Set to enable KBF 7 bit in KBF register to generate an interrupt request KBE6 Keyboard line 6 Enable bit Cleared to enable standard pin Set to enable KBF 6 bit in KBF register to generate an interrupt request 5 Keyboard line 5 Enable bit Cleared to enable standard pin Set to enable KBF 5 bit in KBF register to generate an interrupt request 4 Keyboard line 4 Enable bit Cleared to enable standard 1 pin Set to enable KBF 4 bit in KBF register to generate an interrupt request Keyboard line 3 Enable bit Cleared to enable standard pin Set to enable KBF 3 bit in KBF register to generate an interrupt request KBE2 Keyboard line 2 Enable bit Cleared to enable standard pin Set to enable KBF 2 bit in KBF register to generate an interrupt request KBE1 Keyboard line 1 Enable bit Cleared to enable standard pin Set to enable KBF 1 bit in KBF register to gen
177. r This action automatically decreases the corresponding address vector and the next data is then available in the UEPDATX register The write access for each IN endpoint is performed using the UEPDATX register To write a byte into an IN endpoint FIFO select the correct endpoint number in UEP NUM and write into the UEPDATX register The corresponding address vector is automatically increased and another write can be carried out Warning 1 The byte counter is not updated Warning 2 Do not write more bytes than supported by the corresponding endpoint A MEL 121 Bulk Interrupt Transactions Bulk Interrupt OUT Transactions in Standard Mode AMEL Bulk and Interrupt transactions are managed in the same way Figure 62 Bulk Interrupt OUT transactions in Standard Mode HOST UFI C51 OUT DATAO n bytes ACK RXOUTBO gt Endpoint FIFO read byte 1 OUT DATA Endpoint FIFO read byte 2 i OUT T DATAT Endpoint FIFO read byte n NAK Clear RXOUTBO OUT DATAT RXOUTBO LLL Endpoint FIFO read byte 1 An endpoint will be first enabled and configured before being able to receive Bulk or Interrupt packets When a valid OUT packet is received on an endpoint the RXOUTBO bit is set by the USB controller This triggers an interrupt if enabled
178. r 1 X 1 1 0 INT BRG Timer 2 0 X 0 1 Timer 1 INT BRG 1 X 0 1 Timer 2 INT BRG X X 1 1 INT BRG INT BRG When the internal Baud Rate Generator is used the Baud Rates are determined by the BRG overflow depending on the BRL reload value the value of SPD bit Speed Mode in BDRCON register and the value of the SMOD1 bit in PCON register AMEL s AMEL Figure 38 Internal Baud Rate auto reload counter 72 Peripheral Clock 76 0 SHG overflow 1 INT p BRL SMOD1 BRR The baud rate for UART is token by formula SMOD1 Baud_Rate 2 x FCLK PERIPH 2 6 SPD y 16 x 256 BRL SMOD1 BRL 256 2 X FCLK PERIPH 2 x e SPD x 16 x Baud Rate 4338F USB 08 07 es 189 5131 1 Table 56 SCON Register SCON Serial Control Register 98h 7 6 5 4 3 2 1 0 FE SMO SM1 SM2 REN TB8 RB8 TI RI Bit Bit Number Mnemonic Description Framing Error bit SMODO 1 Clear to reset the error state not cleared by a valid stop bit Set by hardware when an invalid stop bit is detected SMODO must be set to enable access to the FE bit FE Serial port Mode bit 0 SMO Refer to SM1 for serial port mode selection SMODO must be cleared to enable access to the SMO bit Serial port Mode bit 1 SMOSM1ModeDescriptionBaud Rate 0 0 0 Shift RegisterFopypeRipy 6 6
179. r1 reload value 104 AT89C5131A L memm 4338F USB 08 07 AT89C5131A L Figure 52 Format and State in the Master Transmitter Mode MT 5 full 1 transmission S SLA Data toaslave 1 185 Next transfer Y started with a repeated start S SLA condition Not acknowledge received after the slave address Y MR Not acknowledge received after data byte Arbitration lost in slave A or A ther P i A or A 0 masten address or data byte i continues i continues 52 38h 38h Arbitration lost and Other maste addressed as slave continues 68h 78h Boh To corresponding states in slave mode From master to slave A ninina ef data bytes and their associated acknowledge bits From slave to master This number contained SSCS corresponds to a defined state of the 2 wire bus A MEL 105 4338F USB 08 07 AMEL Table 81 Status in Master Transmitter Mode Application software response Status Status of the Two To SSCON Code wire Bus and Two SSSTA wire Hardware To From SSDAT SSSTA SSSTO SSI SSAA Next Action Taken by Two wire Hardware 08h 2
180. re 82 Flash Memory ISP Waveforms Figure 83 Flash Memory Internal Busy Waveforms FBUSY bit 172 89 5131 A L VNHLLLLE L CL L ELL 01 EALLoLLOLELeL LI LALEP L 4338F USB 08 07 USB AC Parameters Fall Time Rise Time AT89C5131A L 90 VHmin VcRS VLmax Differential Data Lines gt Table 126 USB Parameters Symbol Parameter Min Typ Max Unit Test Conditions tn Rise Time 4 20 ns tr Fall Time 4 20 ns teprate Full speed Data Rate 11 9700 12 0300 Mb s Vers Crossover Voltage 1 3 2 0 V io Source Jitter Total to Next 35 35 n Transaction t Source Jitter Total for Paired 4 4 hs DJ2 Transactions Receiver Jitter to Next tri Transaction 1859 ns t Receiver Jitter for Paired 9 9 s JR2 Transactions SPI Interface AC Parameters Definition of Symbols Table 127 SPI Interface Timing Symbol Definitions Signals Conditions H High Data In L Low Data Out V Valid X No Longer Valid 2 Floating 4338F USB 08 07 AMEL 173 Timings 174 Test conditions capacitive load on all pins 50 pF AMEL Table 128 SPI Interface Master AC Timing Vpp 2 7 to 5 5 V 40 to 85 Symbol Parameter Min Max Unit Sla
181. rflow 3 Gerben Cleared to Auto reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2 1 Set to capture on negative transitions on T2EX pin if EXEN2 1 Reset Value 0000 00000 Bit addressable AMEL n 74 AMEL Table 58 PCON Register PCON Power Control Register 87h 7 6 5 4 3 2 1 0 SMOD1 SMODO POF GF1 GFO PD IDL Bit Bit Number Mnemonic Description Serial port Mode bit 1 for UART SMOD Set to select double baud rate in mode 1 2 or 3 Serial port Mode bit 0 for UART 6 SMODO Cleared to select SMO bit in SCON register Set to select FE bit in SCON register 5 _ Reserved The value read from this bit is indeterminate Do not set this bit Power Off Flag 4 POF Cleared to recognize next reset type Set by hardware when Veg rises from 0 to its nominal voltage Can also be set by software General purpose Flag 3 GF1 Cleared by user for general purpose usage Set by user for general purpose usage General purpose Flag 2 GFO Cleared by user for general purpose usage Set by user for general purpose usage Power down Mode Bit 1 PD Cleared by hardware when reset occurs Set to enter power down mode Idle Mode Bit 0 IDL Cleared by hardware when interrupt or reset occurs Set to enter idle mode Reset Value 00X1 0000b Not bit addressable Power off flag reset value will be 1 only after a power on cold reset A
182. rity level 1 PTOL Timer 0 overflow interrupt Priority bit Refer to PTOH for priority level 0 PXOL External interrupt 0 Priority bit Refer to for priority level Reset Value X000 0000b Bit addressable ATMEL 79 80 AMEL Table 63 IPHO Register IPHO Interrupt Priority High Register B7h 7 6 5 4 3 PPCH PT2H PSH PT1H PX1H PTOH PXOH Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate Do not set this bit PPCH PCA interrupt Priority high bit PPCHPPCLPriority Level 0 OLowest 0 1 1 0 1 1Highest PT2H Timer 2 overflow interrupt Priority High bit PT2HPT2LPriority Level 0 OLowest 0 1 1 0 1 1Highest PSH Serial port Priority High bit PSHPSLPriority Level 0 OLowest 0 1 1 0 1 1Highest Timer 1 overflow interrupt Priority High bit PT1HPT1LPriority Level 0 OLowest 0 1 1 0 1 1Highest PX1H External interrupt 1 Priority High bit PX1HPX1LPriority Level 0 OLowest 0 1 1 0 1 1Highest PTOH Timer 0 overflow interrupt Priority High bit PTOHPTOLPriority Level 0 OLowest 0 1 1 0 1 1Highest External interrupt 0 Priority High bit PXOHPXOLPriority Level 0 OLowest 0 1 1 0 1 Highest Reset Value X000 0000b Not bit addressable 4338F USB 08 07
183. rmware will first enable the 48 MHz gener ation and then reset to 0 the SUSPCLK bit in the USBCON register if needed The firmware has to clear the SPINT bit in the USBINT register before any other USB operation in order to wake up the USB controller from its Suspend mode The USB controller is then re activated 4338F USB 08 07 AT89C5131A L Figure 66 Example of a Suspend Resume Management USB Init SPINT Detection of a SUSPEND State 46 Clear SPINT Set SUSPCLK Disable PLL microcontroller in Power down WUPCPU A Detection of a RESUME State Enable PLL Clear SUSPCLK Clear WUPCPU Bit A MEL 131 4338F USB 08 07 Upstream Resume AMEL A USB device can be allowed by the Host to send an upstream resume for Remote Wake Up purpose When the USB controller receives the SET_FEATURE request DEVICE REMOTE WAKEUP the firmware will set to 1 the RMWUPE bit in the USB CON register to enable this functionality RMWUPE value will be 0 in the other cases If the device is in SUSPEND mode the USB controller can send an upstream resume by clearing first the SPINT bit in the USBINT register and by setting then to 1 the SDRM WUP bit in the USBCON register The USB controller sets to 1 the UPRSM bit in the USBCON register All clocks must be enabled first The Remote Wake is sent only if t
184. rom 0000h to 7FFFh address bits 6 to 0 are used to select an address within a page while bits 14 to 7 are used to select the programming address of the page Setting this bit takes precedence on the EXTRAM bit in AUXR register ATMEL 2 Launching Programming Status of the Flash Memory Selecting FMO FM1 AMEL The other memory spaces user extra row hardware security are made accessible in the code segment by programming bits FMODO and FMOD1 in FCON register in accor dance with Table 34 A MOVC instruction is then used for reading these spaces Table 34 FMO Blocks Select Bits FMOD1 FMODO FMO Adressable Space 0 0 User 0000h FFFFh 0 1 Extra Row FF80h FFFFh 1 0 Hardware Security 0000h 1 1 reserved FPL3 0 bits in FCON register are used to secure the launch of programming A specific sequence must be written in these bits to unlock the write protection and to launch the programming This sequence is 5 followed by A Table 35 summarizes the memory spaces to program according to FMOD1 0 bits Table 35 Programming Spaces Write to FCON FPL3 0 FPS FMOD1 FMODO Operation 5 X 0 0 No action User x 0 0 Write the column latches in user space 5 X 0 1 No action Extra Row Write the column latches in extra row A X 0 1 space Security 5 X 1 0 No action Space A X 1 0 Write the fuse bits space 5 X 1 1 No action Reserved A X 1 1 No action
185. s location does not affect Ports 0 and 2 The external memory interface comprises the external bus Port 0 and Port 2 as well as the bus control signals PSEN and ALE Figure 14 shows the structure of the external address bus PO carries address A7 0 while P2 carries address A15 8 Data D7 0 is multiplexed with A7 0 on PO Table 33 describes the external memory interface signals Figure 14 External Code Memory Interface Structure AT89C5131 Flash EPROM A15 8 2 gt 15 8 ALE 7 0 Latch A7 0 AMEL External Bus Cycles Flash Memory Architecture AMEL Table 33 External Data Memory Interface Signals Signal Alternate Name Type Description Function Address Lines 7 Ades 9 Upper address lines for the external bus Pe Address Data Lines ADO VO Multiplexed lower address lines and data for the external memory PUT Address Latch Enable ALE ALE signals indicates that valid address information are available on lines AD7 0 Program Store Enable Output PSEN This signal is active low during external code fetch or external code read MOVC instruction This section describes the bus cycles the AT89C5131A L executes to fetch code see Figure 15 in the external program code memory External memory cycle takes 6 CPU clock periods This is equivalent to 12 oscillator clock periods in standard mode or 6 o
186. saction will be lost If the RXOUTBO bit is cleared while the Host is sending data the USB controller will store only the remaining bytes into the FIFO If the Host sends more bytes than supported by the endpoint FIFO the overflow data won t be stored but the USB controller will consider that the packet is valid if the CRC is correct An endpoint will be first enabled and configured before being able to receive Isochro nous packets When a OUT packet is received on the endpoint bank 0 the RXOUTBO bit is set by the USB controller This triggers an interrupt if enabled The firmware has to select the cor responding endpoint store the number of data bytes by reading the UBYCTLX and UBYCTHX registers If the received packet is ZLP Zero Length Packet the UBYCTLX UBYCTHX register values are equal to 0 and no data has to be read The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in FIFO has a corrupted CRC This bit is updated after each new packet receipt When all the endpoint FIFO bytes have been read the firmware will clear the RXOUBO bit to allow the USB controller to store the next OUT packet data into the endpoint FIFO bank 0 This action switches the endpoint bank 0 and 1 Until the RXOUTBO bit has been cleared by the firmware the data sent by the Host on the bank 0 endpoint FIFO will be lost If the RXOUTBO bit is cleared while the Host is sending data on the endpoint bank 0 the
187. scillator clock periods in X2 mode For further information on X2 mode see the clock Section For simplicity the accompanying figure depicts the bus cycle waveforms in idealized form and do not provide precise timing information Figure 15 External Code Fetch Waveforms 12417421 PSEN AT89C5131A L features two on chip Flash memories Flash memory containing 32 Kbytes of program memory user space organized into 128 byte pages Flash memory 1 3 Kbytes for bootloader and Application Programming Interfaces The FMO supports both parallel programming and Serial In System Programming ISP whereas 1 supports only parallel programming by programmers The ISP mode is detailed in the In System Programming section All Read Write access operations on Flash memory by user application are managed by a set of API described in the In System Programming section 4338F USB 08 07 es 189 5131 1 Figure 16 Flash Memory Architecture Hardware Security 1 Byte gt Extra Row 128 Bytes Column Latches 128 Bytes gt Memory Architecture User Space Extra Row XRow Hardware Security Space Column Latches Overview of FMO Operations Mapping of the Memory Space 4338F USB 08 07 FFFFh 3 Kbytes Flash Memory Boot Space F400h 7FFFh FM1 mapped between FFFFh
188. ssable 4338F USB 08 07 AMEL 5 54 AMEL Table 47 T2MOD Register T2MOD Timer 2 Mode Control Register C9h 7 6 5 4 3 2 1 0 T20E DCEN Bit Bit Number Mnemonic Description 7 _ Reserved The value read from this bit is indeterminate Do not set this bit 6 _ Reserved The value read from this bit is indeterminate Do not set this bit 5 Reserved The value read from this bit is indeterminate Do not set this bit 4 _ Reserved The value read from this bit is indeterminate Do not set this bit 3 _ Reserved The value read from this bit is indeterminate Do not set this bit 2 Reserved The value read from this bit is indeterminate Do not set this bit Timer 2 Output Enable bit 1 2 Cleared to program P1 0 T2 as clock input or port Set to program P1 0 T2 as clock output Down Counter Enable bit 0 DCEN Cleared to disable Timer 2 as up down counter Set to enable Timer 2 as up down counter Reset Value XXXX XX00b Not bit addressable 4338F USB 08 07 189 5131 1 Programmable Counter Array PCA 4338F USB 08 07 The PCA provides more timing capabilities with less CPU intervention than the standard timer counters Its advantages include reduced software overhead and improved accu racy The PCA consists of a dedicated timer counter which serves as the time base for an array of five compare captur
189. t that DPS is toggled in the proper sequence matters not its actual value In other words the block move routine works the same whether DPS is 0 or 1 on entry Observe that without the last instruction INC AUXR1 the routine will exit with DPS the opposite state 189 5131 1 Program Code Memory External Code Memory Access Memory Interface 4338F USB 08 07 The AT89C5131A L implement 32 Kbytes of on chip program code memory Figure 13 shows the split of internal and external program code memory spaces depending on the product The Flash memory increases EPROM and ROM functionality by in circuit electrical era sure and programming Thanks to the internal charge pump the high voltage needed for programming or erasing Flash cells is generated on chip using the standard Vpp volt age Thus the Flash Memory can be programmed using only one voltage and allows In application Software Programming commonly known as IAP Hardware programming mode is also available using specific programming tool Figure 13 Program Code Memory Organization FFFFh 32 Kbytes External Code 8000h 7FFFh 32 Kbytes Flash 0000h AT89C5131A L Note the program executes exclusively from on chip code memory from external mem ory beware of executing code from the upper byte of on chip memory 7FFFh and thereby disrupting I O Ports 0 and 2 due to external prefetch Fetching code constant from thi
190. terface SPI Features Signal Description Master Output Slave Input MOSI Master Input Slave Output MISO SPI Serial Clock SCK AMEL The Serial Peripheral Interface module SPI allows full duplex synchronous serial communication between the MCU and peripheral devices including other MCUs Features of the SPI module include the following Full duplex three wire synchronous transfers Master or Slave operation Eight programmable Master clock rates Serial clock with programmable polarity and phase Master mode fault error flag with MCU interrupt capability Write collision flag protection Figure 42 shows a typical SPI bus configuration using one Master controller and many Slave peripherals The bus is made of three wires connecting all the devices Figure 42 SPI Master Slaves Interconnection Master The Master device selects the individual Slave devices by using four pins of a parallel port to control the four SS pins of the Slave devices This 1 bit signal is directly connected between the Master Device and a Slave Device The MOSI line is used to transfer data in series from the Master to the Slave Therefore itis an output signal from the Master and an input signal to a Slave A byte 8 bit word is transmitted most significant bit MSB first least significant bit LSB last This 1 bit signal is directly connected between the Slave De
191. terrupt ES Serial port Enable bit Cleared to disable serial port interrupt Set to enable serial port interrupt Timer 1 overflow interrupt Enable bit Cleared to disable Timer 1 overflow interrupt Set to enable Timer 1 overflow interrupt EX1 External interrupt 1 Enable bit Cleared to disable external interrupt 1 Set to enable external interrupt 1 ETO Timer 0 overflow interrupt Enable bit Cleared to disable timer 0 overflow interrupt Set to enable timer 0 overflow interrupt EXO External interrupt 0 Enable bit Cleared to disable external interrupt 0 Set to enable external interrupt 0 Reset Value 0000 0000b Bit addressable 189 5131 1 4338F USB 08 07 Table 62 0 Register IPLO Interrupt Priority Register B8h 7 6 5 4 3 2 1 0 PPCL PT2L PSL PT1L PX1L PTOL PXOL Bit Bit Number Mnemonic Description 7 _ Reserved The value read from this bit is indeterminate Do not set this bit PCA interrupt Priority bit Refer to PPCH for priority level 5 PT2L Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level 4 PSL Serial port Priority bit Refer to PSH for priority level 3 PTIL Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level 2 PX1L External interrupt 1 Priority bit Refer to PX1H for prio
192. the Time out capability ranking from 16 ms to 2s at Fosca 12 MHz To manage this feature refer to WDTPRG register description Table 110 Table 109 WDTRST Register WDTRST Watchdog Reset Register 0A6h 7 6 5 4 3 2 1 0 Reset Value XXXXb Write only this SFR is used to reset enable the WDT by writing 01EH then OE1H in sequence A MEL 155 WDT During Power down and Idle 156 AMEL Table 110 WDTPRG Register WDTPRG Watchdog Timer Out Register 0A7h 7 6 5 4 3 2 1 0 S2 S1 S0 Bit Bit Number Mnemonic Description 7 6 5 Reserved The value read from this bit is undetermined Do not try to set this bit 4 3 2 S2 WDT Time out select bit 2 1 51 WDT Time out select bit 1 0 50 WDT Time out select bit 0 S2 S1 SO Selected Time out 0 0 0 16384x2 214 1 machine cycles 16 3 ms at FOSC 12 MHz 0 0 1 16384x2 215 1 machine cycles 32 7 ms at FOSC 12 MHz O 1 0 16384 2 216 1 machine cycles 65 5 ms at FOSC 12 MHz 0 1 1 16384 2 217 1 machine cycles 131 ms at FOSC 12 MHz 1 0 0 16384x2 218 1 machine cycles 262 ms at FOSC 12 MHz 1 0 1 16384 2 219 1 machine cycles 542 ms at FOSC 12 MHz 1 1 0 16384 2 220 1 machine cycles 1 05 s at FOSC 12 MHz 1 1 1 16384 2 221 1 machine cycles 2 09 s at FOSC 12 MHz 16384 2 5 machine cycles Reset value XXXX X000 In Po
193. the bootloader execution from reset The default factory Hardware Condition is assigned to port P1 P1 must be equal to FEh In order to offer the best flexibility the user can define its own Hardware Condition on one of the following Ports Porti Port3 Port4 only bitO and bit1 The Hardware Conditions configuration is stored in three bytes called P1 CF P3 CF P4 CF These bytes can be modified by the user through a set of API or through an ISP command Note 1 The BLJB must be at 0 programmed to be able to restart the bootloader 2 BLJB can always be changed by the means of API whether it s a low or high pin count package But for a low pin count version if BLJB 1 no ISP via the Bootloader is further possible because the HW conditions are never evaluated as described in the USB Bootloader Datasheet To go back to ISP BLJB needs to be changed by a parallel programmer or by the APIs See a detailed description in the applicable Document Datasheet Bootloader USB AT89C5131 4338F USB 08 07 189 5131 1 Expanded RAM ERAM The AT89C5131A L provides additional Bytes of random access memory RAM space for increased data parameters handling and high level language usage AT89C5131A L devices have an expanded RAM in the external data space maximum size and location are described in Table 44 Table 44 Description of Expanded RAM Address Part Number ERAM Size Start End
194. tic address recognition feature in mode 1 In this configuration the stop bit takes the place of the ninth data bit Bit RI is set only when the received command frame address matches the device s address and is terminated by a valid stop bit To support automatic address recognition a device is identified by a given address and a broadcast address Note multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 i e setting SM2 bit in SCON register in mode 0 has no effect Given Address Each device has an individual address that is specified in SADDR register the SADEN register is a mask byte that contains don t care bits defined by zeros to form the device s given address The don t care bits provide the flexibility to address one or more slaves at a time The following example illustrates how a given address is formed To address a device by its individual address the SADEN mask byte must be 1111 11115 For example SADDRO101 01106 SADEN1111 11006 Given0101 01XXb The following is an example of how to use given addresses to address different slaves Slave A SADDR1111 00016 SADEN1111 1010b 1111 OXOXb Slave B SADDR1111 0011b SADEN1111 1001b 1111 OXX1b Slave C SADDR1111 0011b SADEN1111 1101b 1111 00X1b AMEL s 4338F USB 08 07 Broadcast Address Reset Addresses AMEL The SADEN byte is selected so that each slave may be a
195. tion Function Timer Counter 0 External Clock Input TO When Timer 0 operates as counter a falling edge on the TO P3 4 increments the count Timer Counter 1 External Clock Input T1 When Timer 1 operates as counter a falling edge on the T1 pin P3 5 increments the count T2 Timer Counter 2 External Clock Input P10 Timer Counter 2 Clock Output 2 Timer Counter 2 Reload Capture Direction Control Input P1 1 Table 5 LED Signal Description Signal Alternate Name Description Function Direct Drive LED Output P3 3 These pins can be directly connected to the Cathode of standard LEDs P3 5 LED 3 0 without external current limiting resistors The typical current of each Baie output can be programmed by software to 2 6 or 10 mA Several outputs be connected together to get higher drive capabilities P3 7 Table 6 TWI Signal Description Signal Alternate Name Description Function SCL TWI Serial Clock SCL lO SCL output the serial clock to slave peripherals P4 0 SCL input the serial clock from master SDA TWI Serial Data SDA 10 scl isthe bidirectional TWI data line Table 7 SPI Signal Description Signal Alternate Name Type Description Function SS SS SPI Slave Select P1 1 MISO SPI Master Input Slave Output line MISO VO When SPI is in master mode MISO receives data from the slave 1 5 peripheral When SPI is in slave mode MISO outputs data to the master controller
196. trol Register Low OECh CCAP3L Module Compare Capture Control Register Low OEDh CCAPAL PCA Module 4 Compare Capture Control Register Low OEEh 7 6 5 4 3 2 1 0 Bit Bit Number Mnemonic Description 7 0 _ Module n Compare Capture Control CCAPnL Value Reset Value 2 XXXX XXXXb Not bit addressable Table 54 CH Register CH PCA Counter Register High OF9h 7 6 5 4 3 2 1 0 Bit Bit Number Mnemonic Description PCA counter CH Value Reset Value 0000 0000b Not bit addressable AMEL s 4338F USB 08 07 Capture Mode Figure 30 PCA Capture Mode AMEL Table 55 CL Register CL PCA Counter Register Low 7 6 5 4 3 2 1 0 Bit Bit Number Mnemonic Description PCA Counter 280 CL Value Reset Value 0000 0000b Not bit addressable To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set The external CEX input for the mod ule on port 1 is sampled for a transition When a valid transition occurs the PCA hardware loads the value of the PCA counter registers CH and CL into the module s capture registers CCAPnL and CCAPnH If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated see Figure 30
197. tus of the 2 wire bus and 2 wire hardware To from SSDAT To SSCON STA STO SI AA Next Action Taken By 2 wire Software 98h Previously addressed with general call data has been received NOT ACK has been returned Read data byte or Read data byte or Read data byte or Read data byte Switched to the not addressed slave mode no recognition of own SLA or GCA Switched to the not addressed slave mode own SLA will be recognised GCA will be recognised if GC logic 1 Switched to the not addressed slave mode no recognition of own SLA or GCA A START condition will be transmitted when the bus becomes free Switched to the not addressed slave mode own SLA will be recognised GCA will be recognised if GC logic 1 A START condition will be transmitted when the bus becomes free A STOP condition or repeated START condition has been received while still addressed as slave No SSDAT action or No SSDAT action or No SSDAT action or No SSDAT action Switched to the not addressed slave mode no recognition of own SLA or GCA Switched to the not addressed slave mode own SLA will be recognised GCA will be recognised if GC logic 1 Switched to the not addressed slave mode no recognition of own SLA or GCA A START condition will be transmitted when the bus becomes free Switched to the not addressed slave mode own SLA will be recognised GCA will be recognised if G
198. ull Up 7 DPU Cleared to enabled weak pull up on standard Ports Set to disable weak pull up on standard Ports 6 Reserved The value read from this bit is indeterminate Do not set this bit Pulse length Cleared to stretch MOVX control the RD and the WR pulse length is 6 clock 5 MO periods default Set to stretch MOVX control the RD and the WR pulse length is 30 clock periods 1 Reserved The value read from this bit is indeterminate Do not set this bit 3 XRS1 ERAM Size XRS1 XRSO ERAM size 0 0 256 bytes 2 XRSO 0 1 512 bytes 1 0 768 bytes 1 1 1024 bytes default EXTRAM bit 1 EXTRAM Cleared to access internal ERAM using MOVX at Ri at DPTR Set to access external memory ALE Output bit 0 Cleared ALE is emitted at a constant rate of 1 6 the oscillator frequency or 1 3 if X2 mode is used default Set ALE is active only during a MOVX or MOVC instruction is used Reset Value 0 0 11006 Not bit addressable 4338F USB 08 07 X 189 5131 1 Electrical Characteristics Absolute Maximum Ratings Ambient Temperature Under Bias sundusttlal rrr Eres 40 to 85 Storage Temperature 65 to 150 Voltage on Voc from 2 2 0 5V to 6V Voltage on Any Pin from Vas 0 5V to Vec 0 2 DC Parameters Note Stresses at or above those listed
199. under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other condi tions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions may affect device reliability 40 C to 85 Vss OV Vec 3 3V 10 0 to 40 MHz Symbol Parameter Min Typ Max Unit Test Conditions Vit Input Low Voltage 0 5 0 2Vcc 0 1 V Vin Input High Voltage except XTAL1 RST 0 2 Voc 0 9 Voc 0 5 V Input High Voltage XTAL1 RST 0 7 Voc Voc 0 5 V 0 3 100 uA VoL Output Low Voltage ports 1 2 3 and 49 0 45 lo 0 8 mA 1 0 1 6 0 3 200 uA Voi Output Low Voltage port 0 ALE PSEN 0 0 45 flo 1 6 mA 1 0 flo 3 5 mA 10 Vcc 0 3 M 30 P Output High Voltage ports 1 2 3 4 and 5 Vcc 0 7 V E _ 80 x 1 5 7 NR Voc 3 3V 10 200 uA 0 3 2 1 6 dh Vou Output High Voltage port 0 ALE PSEN Vcc 0 7 V _ NA Voc 1 5 Voc 3 3V 10 Rast RST Pullup Resistor 50 100 200 li Logical 0 Input Current ports 1 2 3 and 4 50 0 45V li Input Leakage Current 10 0 45 lt Vin lt Vec Logical 1 to 0 Transition Current ports 1 2 3 650 uA Vin 2 0V and 4
200. unter and the WatchDog Timer ReSeT WDTRST SFR The WDT is by default disabled from exiting reset To enable the WDT user must write 01EH and OE1H in sequence to the WDTRST SFR location OA6H When WDT is enabled it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset either hardware reset or WDT overflow reset When WDT overflows it will drive an output RESET LOW pulse at the RST pin To enable the WDT user must write 01EH and OE1H in sequence to the WDTRST SFR location OA6H When WDT is enabled the user needs to service it by writing to 01EH and OE1H to WDTRST to avoid WDT overflow The 14 bit counter overflows when it reaches 16383 3FFFH and this will reset the device When WDT is enabled it will increment every machine cycle while the oscillator is running This means the user must reset the WDT at least every 16383 machine cycle To reset the WDT the user must write 01EH and OE1H to WDTRST WDTRST is a write only register The WDT counter cannot be read or written When WDT overflows it will generate an output RESET pulse at the RST pin The RESET pulse duration is 96 x Where PERIPH l Feik perp make the best use of the WDT it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset To have a more powerful WDT a 2 counter has been added to extend
201. ve Mode Clock Period 2 Tper Tcucx Clock High Time 0 8 Tper Clock Low Time 0 8 Tper SS Low to Clock edge 100 ns Input Data Valid to Clock Edge 50 ns Teux T eux Input Data Hold after Clock Edge 50 ns Output Data Valid after Clock Edge 50 ns Tetox Output Data Hold Time after Clock Edge 0 ns Torsti SS High after Clock Edge 0 ns Tsiov SS Low to Output Data Valid 4Tpep 20 ns Output Data Hold after SS High 2 100 ns SS High to SS Low 2 120 Input Rise Time 2 us Input Fall Time 2 us Output Rise time 100 ns Output Fall Time 100 ns Master Mode Clock Period 4 Clock High Time 2 20 ns Clock Low Time 2 20 ns Input Data Valid to Clock Edge 50 ns Teux T eux Input Data Hold after Clock Edge 50 ns Output Data Valid after Clock Edge 20 ns Teiox Output Data Hold Time after Clock Edge 0 ns Note is XTAL period when SPI interface operates in X2 mode or twice XTAL period when SPI inter face operates in X1 mode 4338F USB 08 07 AT89C5131A L Waveforms Figure 84 SPI Slave Waveforms CPHA 0 ss input SCK CPOL 0 input SCK CPOL 1 input MISO output Toux Note 1 Not
202. vice and a Master Device The MISO line is used to transfer data in series from the Slave to the Master Therefore it is an output signal from the Slave and an input signal to the Master A byte 8 bit word is transmitted most significant bit MSB first least significant bit LSB last This signal is used to synchronize the data movement both in and out the devices through their MOSI and MISO lines It is driven by the Master for eight clock cycles which allows to exchange one byte on the serial lines Slave Select SS Each Slave peripheral is selected by one Slave Select pin SS This signal must stay low for any message for a Slave It is obvious that only one Master SS high level can drive the network The Master may select each Slave device by software through port 4338F USB 08 07 189 5131 1 Baud Rate 4338F USB 08 07 pins Figure 42 To prevent bus conflicts on the MISO line only one slave should be selected at a time by the Master for a transmission In a Master configuration the SS line can be used in conjunction with the MODF flag in the SPI Status register SPSTA to prevent multiple masters from driving MOSI and SCK see Section Error Conditions page 95 high level on the SS pin puts the MISO line of a Slave SPI in a high impedance state The SS pin could be used as a general purpose if the following conditions are met The device is configured as a Master and the SSDIS control bit in S
203. wer down mode the oscillator stops which means the WDT also stops While in Power down mode the user does not need to service the WDT There are 2 methods of exiting Power down mode by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power down mode When Power down is exited with hardware reset servicing the WDT should occur as it normally should whenever the AT89C5131A L is reset Exiting Power down with an interrupt is significantly different The interrupt is held low long enough for the oscillator to stabilize When the interrupt is brought high the interrupt is serviced To prevent the WDT from resetting the device while the interrupt pin is held low the WDT is not started until the interrupt is pulled high is suggested that the WDT be reset during the interrupt service routine To ensure that the WDT does not overflow within a few states of exiting of power down it is better to reset the WDT just before entering power down In the Idle mode the oscillator continues to run To prevent the WDT from resetting the AT89C5131A L while in Idle mode the user should always set up a timer that will peri odically exit Idle service the WDT and re enter Idle mode 4338F USB 08 07 X 189 5131 1 ONCE Mode ON Chip Emulation 4338F USB 08 07 The ONCE mode facilitates testing and debugging of systems using AT89C5131A L without remov
204. x 2 ij 9 99 lt lt lt 0 SNEAD n cono aoa nda nona oan n n ee A 7 6 5 4 3 2 1 525150494847 P4 1 SDA 8 46 NC P2 3 A11 9 45 P0 1 AD1 P2 4 A12 10 44 2 2 2 5 13 11 43 RST XTAL2 12 42 P0 3 AD3 XTAL1 13 41 VSS 2 6 14 14 52 40 P0 4 AD4 P2 7 A15 15 39 P3 7 RD LED3 VDD 16 38 P0 5 AD5 AVDD 17 37 P0 6 AD6 NC 18 36 P0 7 AD7 AVSS 19 35 P3 6 WR LED2 P3 0 RxD 20 34 29 30 31 32 33 d 1 e 1 gt lt za 2 jo Sgr 2 Re a gt lt e Peers o g e a 4338F USB 08 07 189 5131 1 Figure 2 AT89C5131A L 64 pin VQFP Pinout o 05 6 1 5 zzz 2242 ssx 2 5 4 X lt 5 lt lt lt 6 211110 2 1 1 21121 1 11 11 LL LL 63 62 61 60 59 5857 56 55 54 53 525150 4 1 48 P2 3 A11 2 NC P2 4 A12 3 46 1 P2 5 A13 45 P0 2 AD2 XTAL2 441 RST XTALI PO 3 A
205. yte or ISP Software registers are in a special page of the Flash memory which can be accessed through the or with the parallel programming modes This page called Extra Flash Memory is not in the internal Flash program memory addressing space The only hardware register of the AT89C5131A L is called Hardware Security Byte HSB Table 37 Hardware Security Byte HSB 7 6 5 4 3 2 1 0 2 BLJB 5 1 OSCONO LB2 LB1 LBO Bit Bit Number Mnemonic Description X2 Mode 7 2 Cleared to force X2 mode 6 clocks per instruction Set to force X1 mode Standard Mode Default Bootloader Jump Bit 6 BLJB Set this bit to start the user s application on next reset at address 0000h Cleared this bit to start the bootloader at address F400h default Oscillator Control Bits These two bits are used to control the oscillator in order to reduce consumption OSCON1 OSCONO Description 5 4 0 1 1 The oscillator is configured to run from 0 to 32 MHz 1 The oscillator is configured to run from 0 to 16 MHz 0 1 The oscillator is configured to run from 0 to 8 MHz 0 0 This configuration shouldn t be set 3 Reserved User Memory Lock Bits 2 0 LB2 0 See Table 38 One bit of the HSB the BLJB bit is used to force the boot address When this bit is set the boot address is 0000h When this bit is reset the boot address is F400h By default this bit is cl

ATMEL 8-bit Flash Microcontroller with Full Speed USB Device AT89C5131A-L Manual

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