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MICROCHIP PIC18F2450/4450 Data Sheet 28/40/44-Pin High-Performance 12 MIPS Enhanced Flash USB Microcontrollers with nanoWatt Technology Manual

1. 40 Pin PDIP uEDE N 7 MCLR VPP RE3 1 40 1 4 RB7 KBI3 PGD RAO ANO 4 2 39 L gt RB6 KBI2 PGC RA1 AN1 38 1 4 RB5 KBI1 PGM RA2 AN2 VREF 14 37 1 lt gt RB4 AN11 KBI0 RA3 AN3 VREF 4 5 36 L 4 RB3 AN9 VPO RA4 TOCKI RCV 6 35 O RB2 AN8 INT2 VMO RAS AN4 HLVDIN 7 34 1 gt RB1 AN10 INT1 REO AN5 8 2 33 1 4 RBO AN12 INTO RE1 AN6 19 32 11 7 10 hi 31 O vss VDD J 11 e O RD7 Vss gt 12 o 29 O 4 RD6 OSC1 CLKI 13 n 28 4 RD5 OSC2 CLKO RA6 2 14 27 O RD4 1 15 26 O 4 RC7 RX DT RC1 T1OSI UOE 1 16 25 RC6 TX CK RC2 CCP1 17 24 EL RC5 D VP VusB e 18 23 1 4 RCA D VM RDO 19 22 O RD1 20 21 gt RD2 44 z uo O0 525 age 2 GHIOATOBATS eerrrerrserer Qi993 9985998 RC7 RX DT 10 OSC2 CLKO RA6 RD4 2 5 1 RD5 3 X Vss RD6 1 4 7 AVss RD7 4 5
2. 9 5 2 MCLR VPP RE3 1 28 4 RB7 KBI3 PGD RAO ANO 4 2 27 RB6 KBI2 PGC RA1 AN1 3 26 RB5 KBI1 PGM RA2 AN2NREF 4 4 25 RB4 AN11 KBIO RA3 AN3 VREF 5 o 24 RB3 AN9 VPO RA4 TOCKI RCV 6 23 RB2 AN8 INT2 VMO RA5 AN4 HLVDIN 7 22 4 RB1 AN10 INT1 Vss gt 8 o 21 RBO AN12 INTO OSC1 CLKI gt 9 o 20 VDD OSC2 CLKO RA6 10 n 19 4 Vss RCO T1OSO T1CKI _ 11 18 RC7 RX DT RC4 T1OSI UOE 12 17L RC6 TX CK RC2 CCP1 13 16 RC5 D VP VusB 14 15L RCA D VM 28 Pin QFN gt rovom o 10 lt zz2mmmz lt lt OJJ Nog lt lt 8 22150 827262524232 RA2 AN2 VREF 1 e 211 lt RB3 AN9 VPO RA3 AN3 VREF 2 20 lt RB2 AN8 INT2 VMO RA4 TOCKI RCV 3 19 lt RB1 AN10 INT1 RAS AN4 HLVDIN gt 4 PIC18F2450 RBO AN12 INTO 55 gt 5 17 4 OSC1 CLKI 6 16 lt Vss OSC2 CLKO RA6 7 15 RC7 RX DT 8 9 Zur geen x 583255 QQE 0066 888 Sg a Note Pinouts are subject to change DS39760C page 2 Preliminary 2007 Microchip Technology Inc Pin Diagrams Continued PIC18F2450 4450
3. cleared TABLE 13 3 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2 44 kHz 9 77 kHz 39 06 kHz 156 25 kHz 312 50 kHz 416 67 kHz Timer Prescaler 1 4 16 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution bits 10 10 10 8 7 6 58 TABLE 13 4 REGISTERS ASSOCIATED WITH PWM AND TIMER2 Reset Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 49 RCON SBOREN RI TO PD POR BOR 50 PIR1 ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF 51 PIE1 ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE 51 IPR1 ADIP RCIP TXIP TMR2IP TMR1IP 51 TRISC TRISC7 TRISC6 TRISC2 TRISC1 TRISCO 51 TMR2 Timer2 Register 50 PR2 Timer2 Period Register 50 T2CON T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPSO TMR2ON T2CKPS1 T2CKPSO 50 CCPR1L Capture Compare PWM Register 1 Low Byte 50 CCPR1H_ Capture Compare PWM Register 1 High Byte 50 CCP1CON DC1B1 DC1BO CCP1M3 CCP1M2 CCP1M1 CCP1MO 50 Legend unimplemented read as 0 Shaded cells are not used by PWM or Timer2 Note 1 The SBOREN bit is only available when BOREN lt 1 0 gt 01 otherwise the bit reads as 0 DS39760C page 128 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 14 0 UNIVERSAL SERIAL BUS USB
4. FIGURE 14 1 USB PERIPHERAL AND OPTIONS PIC18F2450 4450 Family A y 3 3V Regulator 09 ws External 33 VREGEN EN Supply 9 p External Pull ups FSEN 4 E UPUEN pp ug Internal Pull ups Full Low UTRDIS i Speed Speed Transceiver I USB Bus USB Clock from the FS T i nj D 4 Oscillator Module gt 54 D v l3 External gt X i USB Control and pie Transceiver USB Bus Configuration lt j vp 4 l ke gt X 256 Byte USB RAM 1 Note 1 e e e e e mm m d This signal is only available if the internal transceiver is disabled UTRDIS 1 2 The pull ups can be supplied either from the VUSB pin or from an external 3 3V supply 3 Do not enable the internal regulator when using an external 3 3V supply 2007 Microchip Technology Inc Preliminary DS39760C page 129 PIC18F2450 4450 14 2 USB Status and Control The operation of the USB module is configured and managed through three control registers In addition a total of 22 registers are used to manage the actual USB transactions The registers are USB Control register UCON USB Configuration
5. 4 47 p at 48 Note Refer to Figure 21 4 for load conditions TABLE 21 11 TIMERO AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Symbol Characteristic Min Max Units Conditions 40 TtOH TOCKI High Pulse Width No prescaler 0 5 Tcv 20 ns With prescaler 10 ns 41 TtOL TOCKI Low Pulse Width No prescaler 0 5 Tcv 20 ns With prescaler 10 ns 42 TtOP TOCKI Period No prescaler Tcv 10 ns With prescaler Greater of ns N prescale 20 ns or value Tcv 40 N 1 2 4 256 45 Tt1H T1CKI High Synchronous no prescaler 0 5 Tcy 20 ns Time Synchronous 10 ns with prescaler PIC18LFXXXX 25 ns Vpb 2 0V Asynchronous PIC18FXXXX 30 ns PIC18LFXXXX 50 ns VDD 2 0V 46 Low Synchronous no prescaler 0 5 Tcv 5 ns Time Synchronous 10 ns with prescaler PIC18LFXXXX 25 ns Vpb 2 0V Asynchronous PIC18FXXXX 30 ns PIC18LFXXXX 50 ns VDD 2 0V 47 T1CKI Input Synchronous Greater of ns N prescale Period 20 ns or value 1 2 4 8 Tcv 40 N Asynchronous 60 ns Ft1 T1CKI Oscillator Input Frequency Range DC 50 kHz 48 Tcke2tmrl Delay from External T1CKI Clock Edge to Timer 2 TOSC 7Tosc Increment 2007 Microchip Technology Inc Preliminary DS39760C page 289 PIC18F2450 4450 FIGURE 21 10 CAPTURE COMPARE PWM TIMIN
6. FIGURE 14 13 USB LAYERS Device To other Configurations if any Configuration gt To other Interfaces if any Interface Interface Endpoint Endpoint Endpoint Endpoint Endpoint 2007 Microchip Technology Inc Preliminary DS39760C page 151 PIC18F2450 4450 The USB specification limits the power taken from the bus Each device is ensured 100 mA at approximately 5V one unit load Additional power may be requested up to a maximum of 500 mA Note that power above a one unit load is a request and the host or hub is not obligated to provide the extra current Thus a device capable of consuming more than a one unit load must be able to maintain a low power configuration of a one unit load or less if necessary The USB specification also defines a Suspend mode In this situation current must be limited to 500 nA averaged over 1 second A device must enter a Suspend state after 3 ms of inactivity i e no SOF tokens for 3 ms A device entering Suspend mode must drop current consumption within 10 ms after Suspend Likewise when signaling a wake up the device must signal a wake up within 10 ms of drawing current above the Suspend limit 14 9 5 ENUMERATION When the device is initially attached to the bus the host enters an enumeration process in an attempt to identify the device Essentiall
7. TABLE 5 1 Address Name Address Name Address FFFh TOSU FDFh INDF2 FBFh FFEh TOSH POSTINC2 1 FBEh FFDh TOSL FDDh POSTDEC2 FBDh FFCh STKPTR FDCh PREINC2 FBCh FFBh PCLATU FDBh PLUSW2 FBBh PCLATH FDAh FSR2H FBAh FF9h PCL FD9h FSR2L FB9h FF8h TBLPTRU FD8h STATUS FB8h FF7h TBLPTRH FD7h TMROH FB7h FF6h TBLPTRL FD6h TMROL FB6h FF5h TABLAT FD5h TOCON FB5h FF4h PRODH FD4h m2 FB4h FF3h PRODL FD3h OSCCON FB3h FF2h INTCON FD2h HLVDCON FB2h FFih INTCON2 FDih WDTCON FB1h FFOh INTCON3 FDOh RCON FBOh FEFh INDFO FCFh TMR1H FAFh FEEh 5 00 FCEh TMR1L FAEh FEDh POSTDECO FCDh T1CON FADh FECh PREINCO FCCh TMR2 FACh FEBh PLUSWO FCBh PR2 FABh FEAh FSROH FCAh T2CON FAAh FE9h FSROL FC9h FA9h FE8h WREG FC8h 2 FA8h FE7h INDF1 FC7h m2 FA7h FE6h POSTINC1 FC6h FA6h FE5h POSTDEC1 FC5h m FA5h FE4h PREINC1 FC4h ADRESH FA4h FE3h PLUSW1 FC3h ADRESL FA3h FE2h FSR1H FC2h ADCONO FA2h 1 FSR1L FC1h ADCON1 FAth FEOh BSR FCOh ADCON2 FAOh Note 1 Nota physical register Name Address Name Address Name CCPR1H F9Fh IPR1 F7Fh UEP15
8. FIGURE 14 6 EXAMPLE OF A BUFFER DESCRIPTOR Address Registers Contents 400h BDOSTAT xxh Buffer 401h BDOCNT 10h Size of Block Descriptor 402h BDOADRL a Sarii arting 403h BDOADRH 04h Address 7 480h Buffer 4 USB Data 48 Note Memory regions not to scale Unlike other control registers the bit configuration for the BDnSTAT register is context sensitive There are two distinct configurations depending on whether the microcontroller or the USB module is modifying the BD and buffer at a particular time Only three bit definitions are shared between the two 14 4 1 1 Buffer Ownership Because the buffers and their BDs are shared between the CPU and the USB module a simple semaphore mechanism is used to distinguish which is allowed to update the BD and associated buffers in memory This is done by using the UOWN bit BDnSTAT lt 7 gt as a semaphore to distinguish which is allowed to update the BD and associated buffers in memory UOWN is the only bit that is shared between the two configurations of BDnSTAT When UOWN is clear the BD entry is owned by the microcontroller core When the UOWN bit is set the BD entry and the buffer memory are owned by the USB peripheral The core should not modify the BD or its corresponding data buffer during this time Note that the microcontroller core can still read BDnSTAT while the SIE owns the buffer and vice
9. Output Enable Monitor Overview 4 5 E Ping Pong Buffer Configuration 5 cio tad Ee A 20 151 Power Modes ior vac RENNES Bus Power Only Dual Power with Self Power Dominance Self Power Only Pull up Resistors ndis Memory Map Speed Status and Control Status Register USTAT 134 Transfer Types UFRMH UFRML Registers 136 USB Internal Voltage Regulator Specifications 281 Module Specifications 281 USB See Universal Serial Bus Watchdog Timer WDT Associated Registers Control Register 0 2422 2 2 During Oscillator Failure Programming Considerations WWW Address s WWW On Line Support 2 X XOREW iioc d p Le poca en gestore 253 XORWE 12 45a ERU 254 DS39760C page 316 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www microchip com This web site is used as a means to make files and inf
10. 162 Brown out Reset BOR 288 Capture Compare PWM CCP 290 CLKO 287 Clock Instruction Cycle 57 EUSART Synchronous Receive Master Slave 291 EUSART Synchronous Transmission Master Slave 291 External Clock All Modes Except PLL 285 Fail Safe Clock Monitor High Low Voltage Detect Characteristics High Voltage Detect VDIRMAG 1 T Low Voltage Detect VDIRMAG 0 PWM Output 2 Reset Watchdog Timer WDT Oscillator Start up Timer OST and Power up Timer PWRT 288 Send Break Character Sequence 168 Slow Rise Time MCLR Tied to VDD VDD Rise gt 47 Synchronous Reception Master Mode SREN 171 Synchronous Transmission 169 Synchronous Transmission Through TXEN 170 Time out Sequence on POR w PLL Enabled MCLR Tied to VDD 1 47 Time out Sequence on Power up MCLR Not Tied to VDD Case 1 46 Time out Sequence on Power up MCLR Not Tied to VDD Case 2 46 Time out Sequence on Power up MCLR Tied to VDD VD
11. 72 Instructions Affected 70 Mapping the Access Bank A Indirect sion trt Inherent and Literal eene Data Memory Access Bank ET and the Extended Instruction Set 2 70 Bank Select Register BSR 59 General Purpose Registers 61 Map for PIC18F2450 4450 Devices 60 Special Function Registers 2 62 62 WSBiRAM deve etd ea 59 DAW noter nee tet te d bend eh 232 DC and AC Characteristics Graphs and Tables 295 DC Characteristics eeeeeeeeeeeeennennnnnnes 278 Power Down and Supply Current 270 Supply Voltage tee cte 269 233 DECF Demonstration Development and Evaluation Boards Development Support Device Differences Device Overview Features table New Core Features Other Special Features Direct Addressing 68 E Effect on Standard PIC MCU Instructions 260 Electrical Characteristics 267 Enhanced Universal Synchrono
12. Q1 Q2 Q3 Q4 Decode Read Process Write to register Data destination If skip Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example HERE NCFSZ CNT 1 0 NZERO ZERO Before Instruction PC Address HERE After Instruction CNT CNT 1 0 Address ZERO IICNT 0 PC Address NZERO INFSNZ Increment f Skip if Not 0 Syntax INFSNZ f d a Operands 0 lt 7 lt 255 d e 0 1 a e 0 1 Operation f 1 dest skip if result 0 Status Affected None Encoding 0100 10da ffff FETE Description The contents of register f are incremented If d is 0 the result is placed in W If d is 1 the result is placed back in register f default If the result is not 0 the next instruction which is already fetched is discarded and a NOP is executed instead making it a two cycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 19 2 3 Byte O
13. RRCF Rotate Right f through Carry Syntax f d a Operands 0 lt lt 255 0 1 0 1 Operation f lt n gt gt dest n 1 gt f lt 0 gt gt C C gt dest lt 7 gt Status Affected C N Z Encoding 0011 00da ffff ffff Description The contents of register f are rotated one bit to the right through the Carry flag If d is 0 the result is placed W If d is 1 the result is placed back in register default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 19 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details C register f Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register Data destination Example RRCF REG 0 0 Before Instruction REG 1110 0110 C 0 After Instruction REG 1110 0110 W 0111 0011 0 DS39760C page 246 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 Rotate Right f No Carry Syntax RRNCF a Operands 0 lt lt 255 0 1 0 1 Operation
14. R W 0 U 0 R 0 R W 0 R W 0 R W 1 R W 0 R W 1 VDIRMAG IRVST HLVDEN HLVDL3 HLVDL2 HLvDL1 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 VDIRMAG Voltage Direction Magnitude Select bit 1 Event occurs when voltage equals or exceeds trip point HLVDL3 HLDVLO 0 Event occurs when voltage equals or falls below trip point HLVDL3 HLVDLO bit 6 Unimplemented Read as 0 bit 5 IRVST Internal Reference Voltage Stable Flag bit 1 Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage trip point 0 Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage trip point and the LVD interrupt should not be enabled bit 4 HLVDEN High Low Voltage Detect Power Enable bit 1 HLVD enabled 0 HLVD disabled bit 3 0 HLVDL3 HLVDLO Voltage Detection Limit bits 1111 Reserved 1110 Maximum setting 0000 Minimum setting Note 1 See Table 21 4 in Section 21 0 Electrical Characteristics for specifications 2007 Microchip Technology Inc Preliminary DS39760C page 185 PIC18F2450 4450 The module is enabled by setting the HLVDEN bit Each time that the HLVD module is enabled the circuitry requires some time to stabilize The IRVST bit is a read only bit
15. 22 0 DC and AC Characteristics Graphs and Tables 2s 23 0 Packaging Information rbi ne e c e diei eve Ape emt cete ta npa 297 AppendbcAsRevisionm Er RR a e er rab a 305 Appendix B Device Differences 905 Appendix C Conversion Considerations 906 Appendix D Migration From Baseline to Enhanced Devices 906 Appendix E Migration From Mid Range to Enhanced nena 307 Appendix F Migration From High End to Enhanced 307 Index x The Microchip WebSites dete rep ep Ep tn d Fd P cR eR ET Ped dae aea va Dope 317 Customer Change Notification Service 0 0000 ein testis tren 317 Customer SUppoltt ree dtt der espe d c te co d LA el Oe dete ie e t t e ste ins hts fs 317 Reader R6eSponse aede eai ice diee asin P Pa anes re ded edere eua ct eds ae e v ene 318 PIC18F2450 4450 Product Identification System apa ea aada e Eaa aeaa anaa drittes sinn tese tenes nnn 319 2007 Microchip Technology Inc Preliminary DS39760C page 5 PIC18F2450 4450 TO OUR VALUED CUSTOMERS It is our intention to provide our valued custom
16. Note 1 Instruction cycle period equals four times the input oscillator time base period for all configurations except PLL All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code Exceeding these specified limits may result in an unstable oscillator operation and or higher than expected current consumption All devices are tested to operate at min values with an external clock applied to the OSC1 CLKI pin When an external clock input is used the max cycle time limit is DC no clock for all devices 2007 Microchip Technology Inc Preliminary DS39760C page 285 PIC18F2450 4450 TABLE 21 7 PLL CLOCK TIMING SPECIFICATIONS 3 0V TO 5 5V js Sym Characteristic Min Typt Max Units Conditions F10 Fosc Oscillator Frequency Range 4 48 2 11 Fsvs On Chip VCO System Frequency 96 2 12 tic PLL Start up Time lock time 2 ms F13 ACLK CLKO Stability jitter 0 25 0 25 96 T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested TABLE 21 8 AC CHARACTERISTICS INTERNAL RC ACCURACY PIC18F2450 4450 INDUSTRIAL PIC18LF2450 4450 INDUSTRIAL PIC18LF2450 4450 Standard Operating Conditions unless otherwise stated Industrial
17. BNZ Branch if Not Zero Syntax BNZ n Operands 128 lt n lt 127 Operation if Zero bit is 0 PC 2 2n PC Status Affected None Encoding 1110 0001 nnnn nnnn Description If the Zero bit is 0 then the program will branch The 2 s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a two cycle instruction Words 1 Cycles 1 2 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC n Data No No No No operation operation operation operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal Process No n Data operation Example HERE BNZ Jump Before Instruction BNOV Branch if Not Overflow Syntax BNOV n Operands 128 lt n lt 127 Operation if Overflow bit is 0 2 2 PC Status Affected None Encoding 1110 0101 nnnn nnnn Description If the Overflow bit is 0 then the program will branch The 2 s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a two cycle instruction Words 1 Cycles 1 2 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC n Data No No No No operation operation operation operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal Process No n Da
18. 140 CCP1CON Capture Compare PWM soccer ae 123 CONFIG1H Configuration 1 High 194 CONFIG1L Configuration 1 Low n CONFIG2H Configuration 2 High CONFIG2L Configuration 2 Low CONFIG3H Configuration 3 High CONFIGAL Configuration 4 Low CONFIG5H Configuration 5 High 2x CONFIGS5L Configuration 5 Low CONFIG6H Configuration 6 High CONFIG6L Configuration 6 Low CONFIG7H Configuration 7 High CONFIG7L Configuration 7 Low u DEVID1 1 DEVID2 Device ID 2 EECON1 Memory Control 1 HLVDCON High Low Voltage Detect Control INTCON Interrupt Control INTCON2 Interrupt Control 2 INTCONG Interrupt Control IPR1 Peripheral Interrupt Priority 1 HS IPR2 Peripheral Interrupt Priority 2 OSCCON Oscillator Control PIE1 Peripheral Interrupt Enable 1 PIE2 Peripheral Interrupt Enable 2 PIR1 Peripheral Interrupt Request Flag 1 ms PIR2 Peripheral Inte
19. PIC18LF2450 4450 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 C lt TA x 85 C for industrial PIC18F2450 4450 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 C x TA lt 85 C for industrial 52 Device Typ Max Units Conditions Supply Current Ipp 2 PIC18LF2450 4450 200 500 uA 40 C 200 500 uA 25 C VDD 2 0V 200 500 uA 85 C PIC18LF2450 4450 500 650 uA 40 C Fosc 1 MHZ 400 650 uA 25 C VDD 3 0V PRI_RUN 360 650 uA 85 EC oscillator All devices 1 0 1 6 mA 40 C 0 9 1 5 mA 25 VDD 5 0 0 8 1 4 85 C PIC18LF2450 4450 0 53 2 0 mA 40 C 0 53 2 0 mA 25 VDD 2 0 0 55 2 0 85 C PIC18LF2450 4450 1 0 3 0 mA 40 C Fosc 4 MHz 0 9 3 0 mA 25 C VDD 3 0V PRI RUN 0 9 30 mA 85 EC oscillator All devices 2 0 6 0 mA 40 C 1 9 6 0 mA 25 VDD 5 0 1 8 6 0 85 All devices 11 0 35 mA 40 C 11 0 35 mA 25 VDD 4 2 113 35 mA 85 PRI RUN All devices 14 0 40 mA 40 C EC oscillator 14 0 40 mA 25 VDD 5 0 14 5 40 85 C All devices 20 40 mA 40 C 20 40 mA 25 VDD 4 2 20 40 mA 85 Fosc 48 MHz PRI RUN All devices 25 50 mA 40 C EC oscillator 25 50 mA 25 C VDD 5 0V 25 50 mA 85 C Shading of rows is to assist in readability of the table T
20. Reading Flash Program Memory Word 77 Saving STATUS WREG BSR Registers in RAM 97 Writing to Flash Program Memory 80 81 Code Protection cin ene cete a deett COME acie idi ie d ei e a e eed Et Compare CCP Module Associated Registers 2H CCP1 Pin Configuration 125 Register anisini hican 125 Software Interrupt 125 Special Event Trigger 125 Timer1 Mode Selection 125 Configuration Bils 4 0n ec At 192 Configuration Register Protection 211 Context Saving During Interrupts 2 97 Conversion Considerations CPFSEQ osse gt CPESGT rue bo non bte es sete aii Het ets TE e Crystal Oscillator Ceramic Resonator Customer Change Notification Service 317 Customer Notification Service 317 Customer S pport ee e eee aee 317 D Data Addressing 67 Comparing Addressing Modes with the Extended Instruction Set Enabled 71 Dine Ct M 67 Indexed Literal Offset 0 4242 70 BSR
21. 191 Oscillator Start up Timer OST 191 Power on Reset Power up Timer PWRT M n vea e ana brefs RETEW EE ete Eae tetur ets and Associated Registers Return Stack Pointer STKPTR Revision History x n anat enema RLCF SEC IDLE 38 SEC RUNMode oie Od 34 Single Supply ICSP Programming 212 SLEEP TREE aed 248 Sleep OSC1 and OSC2 Pin States 32 Sleep Mode zu Software Simulator MPLAB SIM 264 Special Event Trigger See Compare CCP Module Special Features of the CPU Special ICPORT Features Stack Full Underflow Resets E STATUS Registers og e te SUBFSR eibi a ge e pde ge odes SUBEWB 72 5 ied tent Ate eis DS39760C page 314 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 Register PSA Bit Table Pointer Operations table Table Reads Table Writes Time out in Various Situations table 45 Time out Sequence Iu Associated Registers Clock So
22. JJO A dA QUEE 3 P M H P J M m r DS39760C page 22 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 2 0 OSCILLATOR CONFIGURATIONS 2 1 Overview Devices in the PIC18F2450 4450 family incorporate a different oscillator and microcontroller clock system than the non USB PIC18F devices The addition of the USB module with its unique requirements for a stable clock source make it necessary to provide a separate clock source that is compliant with both USB low speed and full speed specifications To accommodate these requirements PIC18F2450 4450 devices include a new clock branch to provide a 48 MHz clock for full speed USB operation Since it is driven from the primary clock source an additional system of prescalers and postscalers has been added to accommodate a wide range of oscillator frequencies An overview of the oscillator structure is shown in Figure 2 1 Other oscillator features used in PIC18 enhanced microcontrollers such as the internal RC oscillator and clock switching remain the same They are discussed later in this chapter 2 1 1 OSCILLATOR CONTROL The operation of the oscillator in PIC18F2450 4450 devices is controlled through two Configuration registers and two control registers Configuration registers CONFIG1L and CONFIG1H select the oscillator mode an
23. 211 xin ted tains PAIS Two Speed Start up Two Word Instructions Example Cases 58 TXSTA Register BRGH Bit 157 2007 Microchip Technology Inc Preliminary DS39760C page 315 PIC18F2450 4450 U Universal Serial Bus 00001 Address Register UADDR Associated Registers Buffer Descriptor Table Buffer Descriptors 4800 Address Validation Assignment in Different Buffering Modes 142 BDnSTAT Register CPU Mode 138 BDnSTAT Register SIE Mode 140 Byte 140 Example B Memory tcr teen 141 Ownership nien eere 137 Ping Pong Buffering Register Summary 142 Status and Configuration 137 Class Specifications and Drivers 152 Descriptors eee ena ettet rere n Endpoint Control Enumeration External Transceiver s Eye Pattern Test Enable Firmware and Drivers 140 4 0 Frame Number Registers 2 ttr rco aaga Internal Voltage Regulator o erac cse and USB Transactions Layered Framework Oscillator Requirements
24. e rare e ri 124 Software Interrupt 2 124 Capture Compare PWM 123 Capture Mode See Capture CCP Mode and Timer Resources 124 CCPR1H Register sess 124 CGPRAL Register dieere nes 124 Compare Mode See Compare Module Configuration 2 124 CIOCK SOUPCES terere nri 30 Selection Using OSCCON Register 90 229 CERWDT enero 229 2007 Microchip Technology Inc Preliminary DS39760C page 309 PIC18F2450 4450 Code Examples 16 x 16 Signed Multiply Routine 84 16 x 16 Unsigned Multiply Routine x 8x8 Signed Multiply Routine 83 8 x 8 Unsigned Multiply Routine 83 Changing Between Capture Prescalers 124 Computed GOTO Using an Offset Value 56 Erasing a Flash Program Memory Row Fast Register Stack How to Clear RAM Bank 1 Using Indirect Addressing 67 Implementing a Real Time Clock Using a Timer1 Interrupt Service 119 Initializing PORTA teret terne 99 Initializing PORTB eee 101 Initializing PORTC Initializing PORTD Initializing PORTE
25. PICSTART Plus Development Programmer E PIE Registers 2 ie e e tet DS39760C page 312 Preliminary 2007 Microchip Technology Inc PIC18F2450 4450 Pin Functions MCLR VPP RE3 12 16 21 NC ICDT ICPGD 020 42000000 21 21 NC ICRST ICVPP 20040041004 00 21 OSCA CLKI 12 16 OSC2 CLKO RA6 12 16 RAO ANO 13 17 Listeners 13 17 RA2 AN2 VREF M RA3 ANS VREF 13 17 RAMITOCKI RCV 13 17 RAS ANAIHLVDIN eee 13 17 RBO AN12 INTO 14 18 RB1 AN10 INT1 os RB2 AN8 INT2 VMO 2 14 18 RB3 AN9 VPO sss 14 18 RB4 AN11 KBIO 14 18 RB5 KBM PGM 14 18 RBO KBI2 PGC 14 18 RB7 KBI3 PGD 14 18 RCO T1OSO TACKI 15 19 RC4 T1OSI UOE 15 19 RC2 CCP1 15 19 RC4 D VM 15 19 RC5IDET VP 15 19 RGO TX OK cente crt das 15 19 RCTIRXIDT REO ANS 6 Pinout I O Descriptions PICI8F 2450 io REA a i 12 PIG18E4450 Aaa 16 PIR Registers PLL Frequency Multiplier 26 HSPLL XTPLL ECPLL and ECPI
26. RE3 2 RE20 RE1O REO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 4 Unimplemented Read as 0 bit 3 0 RE3 REO PORTE Data Input bits 2 3 Note 1 implemented only when Master Clear functionality is disabled MCLRE Configuration bit 0 otherwise read as 0 2 is the only PORTE bit implemented on both 28 pin and 40 44 pin devices All other bits are implemented only when PORTE is implemented i e 40 44 pin devices 3 Unimplemented in 28 pin devices read as 0 2007 Microchip Technology Inc Preliminary DS39760C page 109 PIC18F2450 4450 TABLE 9 9 PORTE I O SUMMARY Pin Function Benin y o I O Type Description REO AN5 REO 0 OUT DIG LATE lt 0 gt data output not affected by analog input IN ST lt 0 gt data input disabled when analog input enabled AN5 IN ANA A D input channel 5 default configuration on POR RE1 AN6 RE1 0 OUT DIG LATE lt 1 gt data output not affected by analog input IN ST PORTE lt 1 gt data input disabled when analog input enabled AN6 IN ANA A D input channel 6 default configuration on POR RE2 AN7 RE2 0 OUT DIG LATE lt 2 gt data output not affected by analog input IN ST PORTE lt 2 gt data input disabled when analog input enabled
27. U 0 R W 0 R C 0 R W 0 R W 0 R W 0 U 0 PPBRST SEO PKTDIS USBEN RESUME SUSPND bit 7 bit 0 Legend C Clearable bit R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 Unimplemented Read as 0 bit 6 PPBRST Ping Pong Buffers Reset bit bit 5 SEO Live Single Ended Zero Flag bit 0 No single ended zero detected bit 4 PKTDIS Packet Transfer Disable bit bit 3 USBEN USB Module Enable bit 1 Resume signaling activated 0 Resume signaling disabled bit 1 SUSPND Suspend USB bit bit O Unimplemented Read as 0 1 Reset all Ping Pong Buffer Pointers to the EVEN Buffer Descriptor BD banks 0 Ping Pong Buffer Pointers not being reset Single ended zero active on the USB bus 1 SIE token and packet processing disabled automatically set when a SETUP token is received 0 SIE token and packet processing enabled 1 USB module and supporting circuitry enabled device attached 0 USB module and supporting circuitry disabled device detached bit 2 RESUME Resume Signaling Enable bit 1 USB module and supporting circuitry in Power Conserve mode SIE clock inactive 0 USB module and supporting circuitry in normal operation SIE clock clocked at the configured rate DS39760C page 130 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 T
28. 11 6 Using Timer1 as a Real Time Clock Adding an external LP oscillator to Timer1 such as the one described in Section 11 3 Timer1 Oscillator gives users the option to include RTC functionality to their applications This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time When operating in Sleep mode and using a battery or supercapacitor as a power source it can completely eliminate the need for a separate RTC device and battery backup The application code routine RTCisr shown in Example 11 1 demonstrates a simple method to increment a counter at one second intervals using an Interrupt Service Routine Incrementing the TMR1 register pair to overflow triggers the interrupt and calls the routine which increments the seconds counter by one Additional counters for minutes and hours are incremented as the previous counter overflows Since the register pair is 16 bits wide counting up to overflow the register directly from a 32 768 kHz clock would take 2 seconds To force the overflow at the required one second intervals it is necessary to preload it The simplest method is to set the MSb of TMR1H with a BSF instruction Note that the TMR1L register is never preloaded or altered doing so may introduce cumulative error over many cycles For this method to be accurate Timer1 must operate in Asynchronous mode and the Timer1
29. Shading of rows is to assist in readability of the table The power down current in Sleep mode does not depend on the oscillator type Power down current is measured with the part in Sleep mode with all I O pins in high impedance state and tied to VDD or Vss and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc The supply current is mainly a function of operating voltage frequency and mode Other factors such as I O loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all I O pins tri stated pulled to VDD or Vss MCLR VDD WDT enabled disabled as specified Standard low cost 32 kHz crystals have an operating temperature range of 10 C to 70 C Extended temperature crystals are available at a much higher cost BOR and HLVD enable internal band gap reference With both modules enabled current consumption will be less than the sum of both specifications 2007 Microchip Technology Inc Preliminary DS39760C page 271 PIC18F2450 4450 21 2 DC Characteristics and Supply Current PIC18F2450 4450 Industrial PIC18LF2450 4450 Industrial Continued
30. c Set GIE bit Ws nu vi d mro 3 Wait the required acquisition time if required Bu vos PL T 8 a S 3 4 Start conversion n 27 2 Set GO DONE bit ADCONO register FIGURE 16 3 ANALOG INPUT MODEL MDP Sampling Switch TERI X Vr 0 6V Rs lt 1 55 Rss 0 mMX AM XV Gee VU D eus uel VAIN E se ILEAKAGE 5p F T ZNA V 06 T nA 7 ad e e vss Legend CPIN Input Capacitance VT Threshold Voltage 6V T ILEAKAGE Leakage Current at the due to Y SIE EN various junctions ay RIC Interconnect Resistance 2V SS Sampling Switch CHOLD Sample hold Capacitance from DAC 1 2 3 4 Rss Sampling Switch Resistance Sampling Switch kQ 2007 Microchip Technology Inc Preliminary DS39760C page 179 PIC18F2450 4450 16 1 A D Acquisition Requirements For the A D Converter to meet its specified accuracy the charge holding capacitor CHOLD must be allowed to fully charge to the input channel voltage level The analog input model is shown in Figure 16 3 The source impedance RS and the internal sampling switch Rss impedance directly affect the time required to charge the capacitor CHOLD The sampling switch Rss impedance varies over the device voltage To calculate the minimum acquisition time Equation 16 1 may be used This equation assumes that 1 2 LSb error is used 1024 steps for the
31. TRISE2 TRISE1 TRISEO 51 110 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISDO 1111 1 51 108 TRISC TRISC7 TRISC6 TRISC2 TRISC1 TRISCO 11 51 106 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISBO 1111 1 51 103 TRISA TRISAG 4 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 111 1 51 100 LATE LATE2 LATE1 LATEO xxx 51 110 LATD 9 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATDO xxxx xxxx 51 108 LATC LATC7 LATC6 LATC2 LATC1 LATCO xx xxx 51 106 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATBO xxxx xxxx 51 103 LATA LATAG 4 LATAS LATA4 LATA3 LATA2 LATA1 LATAO xxx xxxx 51 100 PORTE RE3 RE2 3 RE19 REO 000 51 109 07 RD6 RD5 RD4 RD3 RD2 RD1 RDO xxxx xxxx 51 108 Legend x unknown u unchanged unimplemented q value depends on condition Shaded cells are unimplemented read as 0 Note 1 Bit21 of the TBLPTRU allows access to the device Configuration bits H The SBOREN bit is only available when BOREN lt 1 0 gt 01 otherwise the bit reads as 0 3 These registers and or bits are not implemented on 28 pin devices and are read as 0 Reset values are shown for 40 44 pin devices individual unimplemented bits should be interpreted as 4 RA6 is configured as a port pin based on various primary oscillator modes When the port pin is disabled all of the associated bits read 0
32. DS39760C page 50 Preliminary 2007 Microchip Technology Inc PIC18F2450 4450 TABLE 4 4 INITIALIZATION CONDITIONS FOR ALL REGISTERS CONTINUED MCLR Resets Register Applicable Devices Power on Reset WDT Reset Wake up via WDT Brown out Reset RESET Instruction or Interrupt Stack Resets TXSTA 2450 4450 0000 0010 0000 0010 uuuu uuuu RCSTA 2450 4450 0000 000x 0000 000x uuuu uuuu EECON2 2450 4450 0000 0000 0000 0000 0000 0000 EECON1 2450 4450 x 0 x00 u 0 u00 u 0 u00 IPIR2 2450 4450 1 1 1 1 1 1 u u u PIR2 2450 4450 0 0 0 0 0 0 u u u PIE2 2450 4450 0 0 0 0 0 0 u u u IPR1 2450 4450 Suit I 111 111 uuu uuu PIR1 2450 4450 000 000 000 000 uuu uuu PIE1 2450 4450 000 000 000 000 uuu uuu TRISE 2450 4450 gt 1 __ 11 uuuu uuu TRISD 2450 4450 1111 1111 1111 1111 uuuu uuuu TRISC 2450 4450 11 111 11 111 uu uuu TRISB 2450 4450 1221 1111 CERE TEEL uuuu uuuu TRISA 2450 4450 111 11116 111 11119 uuu uuu LATE 2450 4450 uuu uuu LATD 2450 4450 XXXX XXXX uuuu uuuu uuuu uuuu LATC 2450 4450 XX XXX uu uuu uu uuu LATB 2450 4450 XXXX XXXX uuuu uuuu uuuu uuuu 2450 4450 xxx 9 uuu uuu uuu uuuul PORTE 2450 4450 x000 x000 uuuu PORTD 2450
33. Top of Stack Upper Byte TOS lt 20 16 gt 0 0000 49 54 TOSH Top of Stack High Byte TOS lt 15 8 gt 0000 0000 49 54 TOSL Top of Stack Low Byte TOS lt 7 0 gt 0000 0000 49 54 STKPTR STKFUL STKUNF 5 4 SP3 SP2 SP1 SPO 00 0 0000 49 55 PCLATU Holding Register for lt 20 16 gt 0 0000 49 54 PCLATH Holding Register for PC lt 15 8 gt 0000 0000 49 54 PCL PC Low Byte PC lt 7 0 gt 0000 0000 49 54 TBLPTRU bit 211 Program Memory Table Pointer Upper Byte TBLPTR lt 20 16 gt 00 0000 49 76 Program Memory Table Pointer High Byte TBLPTR lt 15 8 gt 0000 0000 49 76 TBLPTRL Program Memory Table Pointer Low Byte TBLPTR lt 7 0 gt 0000 0000 49 76 TABLAT Program Memory Table Latch 0000 0000 49 76 PRODH Product Register High Byte xxxx xxxx 49 83 PRODL Product Register Low Byte xxxx xxxx 49 83 INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 000x 49 87 INTCON2 RBPU INTEDGO INTEDG1 INTEDG2 TMROIP RBIP 1111 1 1 49 88 INT2IP INT1IP INT2IE INT1IE INT2IF INT1IF 11 0 0 00 49 89 INDFO Uses contents of FSRO to address data memory value of FSRO not changed not a physical register N A 49 68 POSTINCO Uses contents of FSRO to address data memory value of FSRO post incremented not a physical register N A 49 69 POSTDECO Uses contents of FSRO to address data memory value of FSRO post decremented not a physical register N A 49
34. efficient power management These modes provide a variety of options for selective power conservation in applications where resources may be limited i e battery powered devices There are three categories of power managed modes Run modes dle modes Sleep mode These categories define which portions of the device are clocked and sometimes what speed The Run and Idle modes may use any of the three available clock sources primary secondary or internal oscillator the Sleep mode does not use a clock source The power managed modes include several power saving features offered previous PIC microcontrollers One is the clock switching feature offered in other PIC18 devices allowing the controller to use the Timer1 oscillator in place of the primary oscillator Also included is the Sleep mode offered by all PIC microcontrollers where all device clocks are stopped 3 1 Selecting Power Managed Modes Selecting a power managed mode requires two decisions if the CPU is to be clocked or not and the selection of a clock source The IDLEN bit OSCCON lt 7 gt controls CPU clocking while the 5 51 5 50 bits OSCCON lt 1 0 gt select the clock source The individual modes bit settings clock sources and affected modules are summarized in Table 3 1 3 1 1 CLOCK SOURCES The 5 51 5 50 bits allow the selection of one of three clock sources for power managed modes They are The primary clock as defi
35. 0 1 0 1 Operation W AND f dest Status Affected 2 Encoding 0001 01da ffff ffff Description The contents of W are ANDed with register f If d is 0 the result is stored in W If d is 1 the result is stored back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 19 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example ANDWF REG 0 0 Before Instruction 17h C2h After Instruction 02h REG C2h BC Branch if Carry Syntax BC n Operands 128 lt n lt 127 Operation if Carry bit is 1 2 2n PC Status Affected None Encoding 1110 0010 nnnn nnnn Description If the Carry bit is 1 then the program will branch The 2 s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then two cycle instruction Words 1 Cycles 1 2 Q Cycle Activit
36. 0 FFh 1 1 1 1 1 1 1 1 100h 1 00h Bank Select Y FFh bd 200h 00h Bank 2 300h FFh 2 00h Bank 3 through s CUA Bank13 S FFh E00h 00h Bank 14 F00h 00h Bank 15 FFFh FFh Note 1 The Access RAM bit of the instruction can be used to force an override of the selected bank BSR lt 3 0 gt to the registers of the Access Bank 2 The MOVFF instruction embeds the entire 12 bit address in the instruction 5 3 3 ACCESS BANK While the use of the BSR with an embedded 8 bit address allows users to address the entire range of data memory it also means that the user must always ensure that the correct bank is selected Otherwise data may be read from or written to the wrong location This can be disastrous if a GPR is the intended target of an operation but an SFR is written to instead Verifying and or changing the BSR for each read or write to data memory can become very inefficient To streamline access for the most commonly used data memory locations the data memory is configured with an Access Bank which allows users to access a mapped block of memory without specifying a BSR The Access Bank consists of the first 96 bytes of memory 00h 5Fh in Bank 0 and the last 160 bytes of memory 60h FFh in Block 15 The lower half is known as the Access and is composed of GPRs The upper half is where the device s SFRs are mapped These two areas are mapped contiguously in the Access
37. CREN x64 Baud Rate CLK 64 BRG16 SPBRGH SPBRG or i 16 Qi ea tae or Baud Rate Generator 4 Pin Buffer Data x and Contro Recovery RX SPEN Interrupt a RX9 RX9D RCREG Register FIFO 8 RCIF Data Bus RCIE 2007 Microchip Technology Inc Preliminary DS39760C page 165 PIC18F2450 4450 FIGURE 15 7 ASYNCHRONOUS RECEPTION RX pin bit OY bit 1X GS Stop V bit eito y SS Stop bt 55 Stop bit bit bit Rev Shift Reg Read Rcv Buffer Reg RCREG RCIF OERR bit CREN Note Rev Buffer Reg D 5 o5 A Word 2 RCREG o5 5 SS 35 55 Interrupt Flag T 55 P 2 99 5 This timing diagram shows three words appearing on the RX input causing the OERR Overrun bit to be set 5 55 a The RCREG Receive Buffer is read after the third word TABLE 15 6 REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 49 PIR1 ADIF R
38. CASE 1 VDD MCLR INTERNAL POR PWRT TIME OUT OST TIME OUT INTERNAL RESET a TPWRT gt FIGURE 4 5 TIME OUT SEQUENCE ON POWER UP MCLR NOT TIED Vpp CASE 2 VDD MCLR INTERNAL POR PWRT TIME OUT OST TIME OUT INTERNAL RESET TPWRT si DS39760C page 46 Preliminary 2007 Microchip Technology Inc PIC18F2450 4450 FIGURE 4 6 SLOW RISE TIME MCLR TIED TO VoD RISE gt TPWRT 5V VDD ov V MCLR VENENUM d INTERNAL POR TPWRT PWRT TIME OUT TOST OST TIME OUT INTERNAL RESET FIGURE 4 7 TIME OUT SEQUENCE ON POR w PLL ENABLED MCLR TIED TO VDD VDD 4 MCLR INTERNAL POR PWRT TIME OUT 5 gt OST TIME OUT TPLL PLL TIME OUT INTERNAL RESET Note Tost 1024 clock cycles TPLL 2 ms max First three stages of the Power up Timer 2007 Microchip Technology Inc Preliminary DS39760C page 47 PIC18F2450 4450 4 6 Reset State of Registers Most registers are unaffected by a Reset Their status is unknown on POR and unchanged by all other Resets The other registers are forced to a Reset state depending on the type of Reset that occurred Most registers are not affected by a WDT wake up since this is viewed as the
39. 5 is only available as a port pin when the MCLRE Configuration bit is clear otherwise the bit reads as 0 6 RC5and RC4 are only available as port pins when the USB module is disabled UCON lt 3 gt 0 DS39760C page 64 Preliminary 2007 Microchip Technology Inc PIC18F2450 4450 TABLE 5 2 REGISTER FILE SUMMARY PIC18F2450 4450 CONTINUED File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR Bursa PORTC RC7 RC6 RC5 9 RC4 9 RC2 RC1 RCO xxxx xxx 51 106 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO xxxx xxxx 51 100 PORTA 6 5 RA4 RA3 RA2 RA1 RAO x0x 0000 51 100 UEP15 E EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 51 135 UEP14 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 51 135 UEP13 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 51 135 UEP12 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 51 135 UEP11 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 51 135 UEP10 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 51 135 UEP9 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 51 135 UEP8 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 52 135 UEP7 E EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
40. Extensive on line help Integration of select third party tools such as HI TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to Edit your source files either assembly or C One touch assemble or compile and download to PIC MCU emulator and simulator tools automatically updates all project information Debug using Source files assembly or C Mixed assembly and C Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm from the cost effective simulators through low cost in circuit debuggers to full featured emulators This eliminates the learning curve when upgrading to tools with increased flexibility and power 2007 Microchip Technology Inc Preliminary DS39760C page 263 PIC18F2450 4450 20 2 MPASM Assembler The MPASM Assembler is a full featured universal macro assembler for all PIC MCUs The MPASM Assembler generates relocatable object files for the MPLINK Object Linker Intel standard HEX files MAP files to detail memory usage and symbol reference absolute LST files that contain source lines and generated machine code and COFF files for debugging The MPASM Assembler features include Integration into MPLAB IDE projects User defined macros to streamline assembly code Conditional assembly for multi purpose source files Directives that allow complete control over the assembly process 20 3 MPLAB C18 a
41. In this method only one data byte may be stored in each instruction location and room on the return address stack is required EXAMPLE 5 2 COMPUTED USING AN OFFSET VALUE MOVF OFFSET W CALL TABLE ORG nnOOh TABLE ADDWF PCL RETLW nnh RETLW nnh RETLW nnh 5 1 4 2 Table Reads and Table Writes A better method of storing data in program memory allows two bytes of data to be stored in each instruction location Look up table data may be stored two bytes per program word by using table reads and writes The Table Pointer TBLPTR register specifies the byte address and the Table Latch TABLAT register contains the data that is read from or written to program memory Data is transferred to or from program memory one byte at a time Table read and table write operations are discussed further in Section 6 1 Table Reads and Table Writes DS39760C page 56 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 5 2 PIC18 Instruction Cycle 5 2 1 CLOCKING SCHEME The microcontroller clock input whether from an internal or external source is internally divided by four to generate four non overlapping quadrature clocks Q1 Q2 Q3 and Q4 Internally the program counter is incremented on every Q1 the instruction is fetched from the program memory and latched into the Instruc tion Register IR during Q4 The instruction is decoded and executed during the following Q1 through Q4
42. 2 Higher capacitance increases the stability of the oscillator but also increases the start up time 3 Since each resonator crystal has its own characteristics the user should consult the resonator crystal manufacturer for appropriate values of external components 4 Capacitor values are for design guidance only 11 3 1 USING TIMER1 AS A CLOCK SOURCE The Timer1 oscillator is also available as a clock source in power managed modes By setting the clock select bits SCS1 SCSO OSCCON lt 1 0 gt to 01 the device switches to SEC_RUN mode Both the CPU and peripherals are clocked from the Timer1 oscillator If the IDLEN bit OSCCON lt 7 gt is cleared and a SLEEP instruction is executed the device enters SEC IDLE mode Additional details are available in Section 3 0 Power Managed Modes Whenever the Timer1 oscillator is providing the clock source the Timer1 system clock status flag TTRUN T1CON 6 is set This can be used to determine the controller s current clocking mode It can also indicate the clock source being currently used by the Fail Safe Clock Monitor If the Clock Monitor is enabled and the Timer1 oscillator fails while providing the clock polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source 11 3 2 LOW POWER TIMER1 OPTION The Timer1 oscillator can operate at two distinct levels of power consumption based on dev
43. DS39760C page 264 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 20 7 MPLAB ICE 2000 High Performance In Circuit Emulator The MPLAB ICE 2000 In Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers Software control of the MPLAB ICE 2000 In Circuit Emulator is advanced by the MPLAB Integrated Development Environment which allows editing building downloading and source debugging from a single environment The MPLAB ICE 2000 is a full featured emulator system with enhanced trace trigger and data monitor ing features Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors The architecture of the MPLAB ICE 2000 In Circuit Emulator allows expansion to support new PIC microcontrollers The MPLAB ICE 2000 In Circuit Emulator system has been designed as a real time emulation system with advanced features that are typically found on more expensive development tools The PC platform and Microsoft Windows 32 bit operating system were chosen to best make these features available in a simple unified application 20 8 MPLAB REAL ICE In Circuit Emulator System MPLAB REAL ICE In Circuit Emulator System is Microchips next generation high speed emulator for Microchip Flash DSC and MCU devices It debugs and programs PIC Flash MCUs and dsPIC Flash DSCs w
44. If is 0 the result is placed in W If d is 1 the result is placed in data memory location f If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 19 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register Data destination Example ADDWFC REG 0 1 Before Instruction Carry bit 1 REG 02h Ww 4Dh After Instruction Carry bit 0 REG 02h Ww 50h ANDLW AND Literal with W Syntax ANDLW Operands 0 lt k lt 255 Operation W AND k gt W Status Affected N Z Encoding 0000 1011 kkkk kkkk Description The contents of W are ANDed with the 8 bit literal k The result is placed in W Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal Process Write to W Data Example ANDLW 05Fh Before Instruction Ww A3h After Instruction Ww 03h DS39760C page 220 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 ANDWF AND W with f Syntax f d a Operands 0 lt lt 255
45. Legend u unchanged Note 1 When the wake up is due to an interrupt and the GIEH or GIEL bit is set the PC is loaded with the interrupt vector 008h or 0018h 2 Reset state is 1 for POR and unchanged for all other Resets when software BOR is enabled BOREN1 BORENO Configuration bits 01 and SBOREN 1 otherwise the Reset state is 0 DS39760C page 48 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 TABLE 4 4 INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets Register Applicable Devices Power on Reset WDT Reset Wake up via WDT Brown out Reset RESET Instruction or Interrupt Stack Resets TOSU 2450 4450 0 0000 0 0000 0 uuu TOSH 2450 4450 0000 0000 0000 0000 uuuu uuuu f TOSL 2450 4450 0000 0000 0000 0000 uuuu uuuu f STKPTR 2450 4450 00 0 0000 uu 0 0000 uu u uuuull PCLATU 2450 4450 0 0000 0 0000 u uuuu PCLATH 2450 4450 0000 0000 0000 0000 uuuu uuuu PCL 2450 4450 0000 0000 0000 0000 PC 20 TBLPTRU 2450 4450 00 0000 00 0000 uu uuuu TBLPTRH 2450 4450 0000 0000 0000 0000 uuuu uuuu TBLPTRL 2450 4450 0000 0000 0000 0000 uuuu uuuu TABLAT 2450 4450 0000 0000 0000 0000 uuuu uuuu PRODH 2450 4450 XXXX XXXX uuuu uuuu uuuu uuuu PRODL 2450 4450 uuuu uuuu uuuu uuuu INTCON 2450 44
46. Note 4 137 TDIS Discharge Time 0 2 us Legend TBD To Be Determined Note 1 The time of the A D clock period is dependent on the device frequency and the TAD clock divider 2 ADRES registers may be read on the following Tcy cycle 3 The time for the holding capacitor to acquire the New input voltage when the voltage changes full scale after the conversion VDD to Vss or Vss to VDD The source impedance Rs on the input channels is 500 4 On the following cycle of the device clock DS39760C page 294 Preliminary 2007 Microchip Technology Inc PIC18F2450 4450 22 0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and tables are not available at this time SS X c s J 2007 Microchip Technology Inc Preliminary DS39760C page 295 PIC18F2450 4450 NOTES JP J C J M P J n DS39760C page 296 Preliminary 2007 Microchip Technology Inc PIC18F2450 4450 23 0 PACKAGING INFORMATION 23 4 Package Marking Information 28 Lead SPDIP Skinny DIP Example XXXXXXXXXXXXXXXXX PIC18F2450 I SP 3 XXXXXXXXXXXXXXXXX 0710017 YYWWNNN 28 Lead SOIC Example XXXXXXXXXXXXXXXXXXXX PIC18F2450 E SO XXXXXXXXXXXXXXXXXXXX 0710017 XXX
47. WRT1 WRTO 30000Bh CONFIG6H WRTB WRTC aii sull 30000Ch CONFIG7L EBTR1 EBTRO 30000Dh CONFIG7H 1 3FFFFEh DEVID1 DEV2 DEV1 DEVO REV4 REV3 REV2 REV1 REVO xxxx 1 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0001 0010 Legend x unknown u unchanged unimplemented Shaded cells are unimplemented read as 0 Note 1 by the user See Register 18 13 and Register 18 14 for device ID values DEVID registers are read only and cannot be programmed 2 Available only on PIC18F4450 devices in 44 pin TQFP packages Always leave this bit clear in all other devices DS39760C page 192 Preliminary 2007 Microchip Technology Inc PIC18F2450 4450 REGISTER 18 1 CONFIG1L CONFIGURATION REGISTER 1 LOW BYTE ADDRESS 300000h U 0 U 0 R P 0 R P 0 R P 0 R P 1 R P 1 R P 1 USBDIV CPUDIV1 CPUDIVO PLLDIV2 PLLDIV1 PLLDIVO bit 7 bit 0 Legend Readable bit P Programmable bit U Unimplemented bit read as 0 n Value when device is unprogrammed Unchanged from programmed state bit 7 6 Unimplemented Read as 0 bit 5 USBDIV USB Clock Selection bit used in Full Speed USB mode only UCFG FSEN 1 1 USB clock source comes from the 96 MHz PLL divided by 2 0 USB clock source comes directly from the primary oscillator block with no postscale bit 4
48. Z z z z z z z z z z 21 212 lt lt lt lt lt lt lt lt lt lt 00000 A 0001 0010 0011 0100 0101 0110 D A A A A A A A A 011100 D D D D D A A A A A A A 1000 D D D D D D A A A A A A 1001 D D D D D D D A A A A A 1010 D D D D D D D D A A A A 1011 D D D D D D D D D A A A 1100 D D D D D D D D D D A A 1101 D D D D D D D D D D D A 1110 D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D A Analog input D Digital I O Note 1 The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit When PBADEN 1 PCFG lt 3 0 gt 0000 when PBADEN 0 PCFG lt 3 0 gt 0111 2 AN5 through are available only on 40 44 pin devices DS39760C page 176 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 REGISTER 16 3 ADCON2 A D CONTROL REGISTER 2 R W 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 ADFM ACQT2 ACQT1 ACQTO ADCS2 ADCS1 ADCSO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 ADFM A D Result Format Select
49. 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 CSRC Clock Source Select bit Asynchronous mode Don t care Synchronous mode 1 Master mode clock generated internally from BRG 0 Slave mode clock from external source bit 6 TX9 9 Bit Transmit Enable bit 1 Selects 9 bit transmission 0 Selects 8 bit transmission bit 5 TXEN Transmit Enable bit 1 Transmit enabled 0 Transmit disabled bit 4 SYNC EUSART Mode Select bit 1 Synchronous mode 0 Asynchronous mode bit 3 SENDB Send Break Character bit Asynchronous mode 1 Send Sync Break on next transmission cleared by hardware upon completion 0 Sync Break transmission completed Synchronous mode Don t care bit 2 BRGH High Baud Rate Select bit Asynchronous mode 1 High speed 0 Low speed Synchronous mode Unused in this mode bit 1 TRMT Transmit Shift Register Status bit 1 TSR empty 0 TSR full bit 0 TX9D 9th bit of Transmit Data Can be address data bit or a parity bit Note 1 SREN CREN overrides TXEN in Sync mode with the exception that SREN has no effect in Synchronous Slave mode DS39760C page 154 Preliminary 2007 Microchip Technology Inc PIC18F2450 4450 REGISTER 15 2 RCSTA RECEIVE STATUS AND CONTROL REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R 0 R 0 R x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend Readable bit W
50. 14 2 2 1 Internal Transceiver The USB peripheral has a built in USB 2 0 full speed and low speed compliant transceiver internally con nected to the SIE This feature is useful for low cost single chip applications The UTRDIS bit UCFG lt 3 gt controls the transceiver it is enabled by default UTRDIS 0 The FSEN bit UCFG lt 2 gt controls the transceiver speed setting the bit enables full speed operation The on chip USB pull up resistors are con trolled by the UPUEN bit UCFG lt 4 gt They can only be selected when the on chip transceiver is enabled The USB specification requires 3 3V operation for communications however the rest of the chip may be running at a higher voltage Thus the transceiver is supplied power from a separate source VUSB 14 2 2 2 External Transceiver This module provides support for use with an off chip transceiver The off chip transceiver is intended for applications where physical conditions dictate the location of the transceiver to be away from the SIE For example applications that require isolation from the USB could use an external transceiver through some isolation to the microcontroller s SIE Figure 14 2 External transceiver operation is enabled by setting the UTRDIS bit FIGURE 14 2 TYPICAL EXTERNAL TRANSCEIVER WITH ISOLATION pic VDD Isolated 3 3V Derived Microcontroller from USB from USB VDD VUSB 1 5 KQ Mis Isolat
51. 40 C lt lt 85 C for industrial AC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section 21 1 and LF parts operate for industrial temperatures only FIGURE 21 4 LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 VDD 2 4640 Vss CL 50 pF Load Condition 2 for all pins except OSC2 CLKO and including D and E outputs as ports DS39760C page 284 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 21 4 3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 21 5 EXTERNAL CLOCK TIMING ALL MODES EXCEPT PLL OSC1 CLKO TABLE 21 6 EXTERNAL CLOCK TIMING REQUIREMENTS hs Symbol Characteristic Min Max Units Conditions 1A Fosc External CLKI Frequency DC 48 MHz EC ECIO Oscillator modes Oscillator Frequency 0 2 1 MHz XT XTPLL Oscillator modes 4 25 MHz HS Oscillator mode 4 25 MHz HSPLL Oscillator mode 1 Tosc External CLKI Period 20 8 ns ECIO Oscillator modes Oscillator Period 1 000 5 000 ns XT Oscillator mode 40 250 ns 5 Oscillator mode 40 250 ns HSPLL Oscillator mode 2 Tcy Instruction Cycle Time 83 3 ns Tcy 4 Fosc 3 TosL External Clock in OSC1 30 ns Oscillator mode TosH High or Low Time 10 ns HS Oscillator mode 4 TosR External Clock in OSC1 20 ns XT Oscillator mode TosF Rise or Fall Time 7 5 ns HS Oscillator mode
52. AN10 Analog Analog input 10 INT1 5 1 RB2 AN8 INT2 VMO 23 20 RB2 VO TTL Digital I O AN8 Analog Analog input 8 INT2 5 2 VMO O External USB transceiver VMO output RB3 AN9 VPO 24 21 RB3 TTL Digital I O AN9 Analog Analog input 9 VPO O External USB transceiver VPO output RB4 AN11 KBIO 25 22 RB4 VO TTL Digital I O AN11 Analog Analog input 11 KBIO TTL Interrupt on change pin RB5 KBI1 PGM 26 23 RB5 TTL Digital I O KBI1 TTL Interrupt on change pin PGM ST Low Voltage ICSP Programming enable pin RB6 KBI2 PGC 27 24 RB6 TTL Digital I O KBI2 TTL Interrupt on change pin PGC VO ST In Circuit Debugger and ICSP programming clock pin RB7 KBI3 PGD 28 25 RB7 TTL Digital I O KBI3 TTL Interrupt on change pin PGD 5 In Circuit Debugger and ICSP programming data pin Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input Output P Power DS39760C page 14 Preliminary 2007 Microchip Technology Inc PIC18F2450 4450 TABLE 1 2 PIC18F2450 PINOUT I O DESCRIPTIONS CONTINUED Pin Number Pin Name SPDIP Description SOIC QFN yp yp PORTC is a bidirectional I O port RCO T1OSO T1CKI 11 8 RCO 5 Digital I O
53. External Reset 1 2 MCLRE IDLE Sleep WDT H Time out VDD Rise POR Pulse Detect VDD Brown out Reset BOREN OST PWRT OST 1024 Cycles e Chip Reset DSS 10 Bit Ripple Counter OSC1 d Diocese oS 32u 655ms INTRC _K 41 Bit Ripple Counter Enable PWRT Enable 2 2 See Table 4 2 for time out situations Note 1 This is the INTRC source from the internal oscillator and is separate from the RC oscillator of the CLKI pin 2007 Microchip Technology Inc Preliminary DS39760C page 41 PIC18F2450 4450 REGISTER 4 1 RCON RESET CONTROL REGISTER R W 0 R Ww 10 U 0 R W 1 R 1 R 1 R W o 2 R W 0 IPEN SBOREN RI TO PD POR BOR bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 IPEN Interrupt Priority Enable bit 1 Enable priority levels on interrupts 0 7 Disable priority levels on interrupts PIC16CXXX Compatibility mode bit 6 SBOREN BOR Software Enable If BOREN1 BORENO 01 1 BOR is enabled 0 BOR is disabled If BOREN1 BORENO 10 or 11 Bit is disabled
54. MCLR Reset during normal operation c MCLR Reset during power managed modes Watchdog Timer WDT Reset during execution e Programmable Brown out Reset BOR f RESET Instruction g Stack Full Reset h Stack Underflow Reset This section discusses Resets generated by MCLR POR and BOR and covers the operation of the various start up timers Stack Reset events are covered in Section 5 1 2 4 Stack Full and Underflow Resets WDT Resets are covered in Section 18 2 Watchdog Timer WDT FIGURE 4 1 A simplified block diagram of the on chip Reset circuit is shown in Figure 4 1 4 1 RCON Register Device Reset events are tracked through the RCON register Register 4 1 The lower five bits of the register indicate that a specific Reset event has occurred In most cases these bits can only be cleared by the event and must be set by the application after the event The state of these flag bits taken together can be read to indicate the type of Reset that just occurred This is described in more detail in Section 4 6 Reset State of Registers The RCON register also has control bits for setting interrupt priority IPEN and software control of the BOR SBOREN Interrupt priority is discussed in Section 8 0 Interrupts BOR is covered Section 4 4 Brown out Reset BOR SIMPLIFIED BLOCK DIAGRAM OF ON CHIP RESET CIRCUIT RESET Instruction Stack Stack Full Underflow Reset Pointer
55. T10SO Timer1 oscillator output T1CKI ST Timer1external clock input RC41 T1OSI UOE 12 9 RC1 5 Digital I O T1OSI CMOS Timer1 oscillator input UOE External USB transceiver OE output RC2 CCP1 13 10 RC2 ST Digital I O CCP1 VO ST Capture 1 input Compare 1 output PWM 1 output RC4 D VM 15 12 RC4 TTL Digital input D USB differential minus line input output VM TTL External USB transceiver VM input RC5 D VP 16 13 RC5 TTL Digital input D VO USB differential plus line input output VP TTL External USB transceiver VP input RC6 TX CK 17 14 RC6 y o ST Digital I O TX EUSART asynchronous transmit CK VO ST EUSART synchronous clock see RX DT RC7 RX DT 18 15 RC7 VO ST Digital I O RX 5 EUSART asynchronous receive DT ST EUSART synchronous data see TX CK See MCLR VPP RES VUSB 14 11 Internal USB 3 3V voltage regulator Vss 8 19 5 16 P Ground reference for logic and I O pins VDD 20 17 P Positive supply for logic and I O pins Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input O Output P Power 2007 Microchip Technology Inc Preliminary DS39760C page 15 PIC18F2450 4450 TABLE 1 3 PIC18F4450 PINOUT I O DESCRIPTIONS Pin Number Pin Buffer 2 D
56. lt 5 gt data input disabled when USB module or on chip transceiver is enabled D OUT XCVR USB bus differential plus line output internal transceiver n IN XCVR USB bus differential plus line input internal transceiver VP nn IN TTL External USB transceiver VP input RC6 TX CK RC6 0 OUT DIG LATC 6 data output 1 IN ST lt 6 gt data input TX 0 OUT DIG Asynchronous serial transmit data output EUSART module takes priority over port data User must configure as output CK 0 OUT DIG Synchronous serial clock output EUSART module takes priority over port data 1 IN ST Synchronous serial clock input EUSART module RC7 RX DT RC7 0 OUT DIG LATC lt 7 gt data output 1 IN ST PORTC lt 7 gt data input RX 1 IN ST Asynchronous serial receive data input EUSART module DT 1 OUT DIG Synchronous serial data output EUSART module 1 IN ST Synchronous serial data input EUSART module User must configure as an input Legend OUT Output IN Input ANA Analog Signal DIG Digital Output ST Schmitt Buffer Input TTL TTL Buffer Input XCVR USB Transceiver x Don t care TRIS bit does not affect port direction or is overridden for this option Note 1 RC4 and RC5 do not have corresponding TRISC bits In Port mode these pins are input only USB data direction is determined by the USB configuration 2007 Microchip Technology Inc Preliminary DS39760C page 105 PIC18F2450 4450 TABL
57. selects the number of the bit affected by the operation while the file register designator f represents the number of the file in which the bit is located The literal instructions may use some of the following operands A literal value to be loaded into a file register specified by k The desired FSR register to load the literal value into specified by f No operand required specified by The control instructions may use some of the following operands A program memory address specified by n The mode of the CALL or RETURN instructions specified by s The mode of the table read and table write instructions specified by m No operand required specified by All instructions are a single word except for four double word instructions These instructions were made double word to contain the required information in 32 bits In the second word the 4 MSbs are 1 s If this second word is executed as an instruction by itself it will execute as a NOP All single word instructions are executed in a single instruction cycle unless a conditional test is true or the program counter is changed as a result of the instruc tion In these cases the execution takes two instruction cycles with the additional instruction cycle s executed as a NOP The double word instructions execute in two instruction cycles One instruction cycle consists of four osci
58. 0 and POR is 1 assuming that POR was set to T by software immediately after Power on Rest DS39760C page 42 Preliminary 2007 Microchip Technology Inc 4 2 Master Clear Reset MCLR The MCLR pin provides a method for triggering an external Reset of the device A Reset is generated by holding the pin low These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses The MCLR pin is not driven low by any internal Resets including the WDT In PIC18F2450 4450 devices the MCLR input can be disabled with the MCLRE Configuration bit When MCLR is disabled the pin becomes a digital input See Section 9 5 PORTE TRISE and LATE Registers for more information 4 3 Power on Reset POR A Power on Reset pulse is generated on chip whenever VDD rises above a certain threshold This allows the device to start in the initialized state when VDD is adequate for operation To take advantage of the POR circuitry tie the MCLR pin through a resistor 1 to 10 to This will eliminate external RC components usually needed to create a Power on Reset delay A minimum rise rate for VDD is specified parameter 0004 Section269 DC Characteristics For a slow rise time see Figure 4 2 When the device starts normal operation i e exits the Reset condition device operating parameters volt age frequency temperature etc must be met to ensure o
59. 0 0000 52 135 UEP6 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 52 135 UEP5 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 52 135 UEP4 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 52 135 UEP3 E EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 52 135 UEP2 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 52 135 UEP1 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 52 135 UEPO EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 52 135 UCFG UTEYE UOEMON UPUEN UTRDIS FSEN PPB1 PPBO 00 0 0000 52 132 UADDR ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDRO 000 0000 52 136 UCON PPBRST SEO PKTDIS USBEN RESUME SUSPND 0x0 000 52 130 USTAT ENDP3 ENDP2 ENDP1 DIR PPBI 52 134 UEIE BTSEE DFN8EE CRC16EE 5 PIDEE 0 0 0000 52 148 UEIR BTSEF DFN8EF CRC16EF 5 PIDEF 0 0 0000 52 147 UIE SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE 000 0000 52 146 UIR SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF 000 0000 52 144 UFRMH 10 FRM8 xxx 52 136 UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRMO xxxx 52 136 Legend x unknown u unchanged unimplemented q value depends on condition Shaded cells are unimplemented read as 0 Note 1 Bit21 of the TBLPTRU a
60. 1 1 sR nan Clock ia 0 CPU Clock 2 Ly ae eens PLL Clock Output Peripheral V DM v Ly Ly Ly Ly PC y 2 SCS1 SCS0 bits Changed OSTS bit Set Note 1 Tost 1024 Tosc TPLL 2 ms approx These intervals are not shown to scale 2 Clock transition typically occurs within 2 4 Tosc DS39760C page 36 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 3 3 The power managed Sleep mode in the PIC18F2450 4450 devices is identical to the legacy Sleep mode offered in all other PIC microcontrollers It is entered by clearing the IDLEN bit the default state on device Reset and executing the SLEEP instruction This shuts down the selected oscillator Figure 3 5 All clock Source status bits are cleared Sleep Mode Entering the Sleep mode from any other mode does not require a clock switch This is because no clocks are needed once the controller has entered Sleep If the WDT is selected the INTRC source will continue to operate If the Timer1 oscillator is enabled it will also continue to run When a wake event occurs in Sleep mode by interrupt Reset or WDT time out the device will not be clocked until the clock source selected by the SCS1 SCS0 bits becomes ready see Figure 3 6 or it will be clocked from the internal oscillator if either the Two Speed Start up or the F
61. 1 2 1 221 1 73 255 1 202 0 16 129 1 201 0 16 103 24 2 441 1 73 255 2 404 0 16 129 2 404 0 16 64 2 403 0 16 51 9 6 9 615 0 16 64 9 766 1 73 31 9 766 1 73 15 9 615 0 16 12 19 2 19 531 1 73 31 19 531 1 73 15 19 531 1 73 57 6 56 818 1 36 10 62 500 8 51 4 52 083 9 58 115 2 125 000 8 51 4 104 167 9 58 2 78 125 32 18 SYNC 0 BRGH 0 BRG16 0 E Fosc 4 000 MHz Fosc 2 000 MHz Fosc 1 000 MHz K Actual SPBRG Actual SPBRG Actual 9 SPBRG Rate Error value Rate Error value Rate Error value K decimal K decimal K decimal 0 3 0 300 0 16 207 0 300 0 16 103 0 300 0 16 51 1 2 1 202 0 16 51 1 201 0 16 25 1 201 0 16 12 24 2 404 0 16 25 2 403 0 16 12 9 6 8 929 6 99 6 19 2 20 833 8 51 2 57 6 62 500 8 51 0 115 2 62 500 45 75 0 SYNC 0 BRGH 1 BRG16 0 E Fosc 40 000 MHz Fosc 20 000 MHz Fosc 10 000 MHz Fosc 8 000 MHz K Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG Rate Error value Rate Error value Rate Error value Rate Error value K decimal K decimal K decimal K decimal 0 3 1 2 24 2 441 1 73 255 2 403 0 16 207 9 6 9 766 1 73 255 9 615 0 16 129 9 615 0 16 64 9 615 0 16 51 19 2 19 231 0 16 129 19 231 0 16
62. 4 Low power devices only 2007 Microchip Technology Inc Preliminary DS39760C page 181 PIC18F2450 4450 16 4 Operation in Power Managed Modes The selection of the automatic acquisition time and A D conversion clock is determined in part by the clock source and frequency while in a power managed mode If the A D is expected to operate while the device is in a power managed mode the ACQT2 ACQTO and ADCS2 ADCSO bits in ADCON2 should be updated in accordance with the clock source to be used in that mode After entering the mode an A D acquisition or conversion may be started Once started the device should continue to be clocked by the same clock source until the conversion has been completed If desired the device may be placed into the corresponding Idle mode during the conversion If the device clock frequency is less than 1 MHz the A D RC clock source should be selected Operation in the Sleep mode requires the A D FRC clock to be selected If bits ACQT2 ACQTO are set to 000 and a conversion is started the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode The IDLEN bit OSCCON lt 7 gt must have already been cleared prior to starting the conversion 16 5 Configuring Analog Port Pins The ADCON1 TRISA TRISB and TRISE registers all configure the A D port pins The port pins needed as analog inputs must have their correspon
63. External Block Table Read bit EBTRn Figure 18 5 shows the program memory organization for 24 and 32 Kbyte devices and the specific code protection bit associated with each block The actual locations of the bits are summarized in Table 18 3 FIGURE 18 5 CODE PROTECTED PROGRAM MEMORY FOR PIC18F2450 4450 MEMORY SIZE DEVICE Block Code Protection 16 Kbytes Address Controlled By PIC18F2450 4450 Range 000000h Boot Block 0007FFh CPB WRTB EBTRB OOOFFFh 001000h Block 0 WRTO EBTRO 001FFFh 002000h Block 1 CP1 WRT1 EBTR1 00 Unimplemented Read 0 s Unimplemented Read 0 s Unimplemented Read 0 s Unimplemented Memory Space 1FFFFFh TABLE 18 3 SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L CP1 CPO 300009h CONFIG5H CPB 30000Ah CONFIG6L WRT1 WRTO 30000Bh CONFIG6H WRTB WRTC 30000Ch CONFIG7L EBTR1 EBTRO 30000Dh CONFIG7H EBTRB Legend Shaded cells unimplemented DS39760C page 208 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 18 5 1 PROGRAM MEMORY CODE PROTECTION The program memory may be read to or written from any location using the table read and table
64. Maximum Memory Used 256 bytes Maximum BDs 64 BDO to BD63 2007 Microchip Technology Inc Preliminary DS39760C page 141 PIC18F2450 4450 TABLE 14 4 ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT BUFFERING MODES BDs Assigned to Endpoint Endpoint Mode 0 1 2 No Ping Pong Ping Pong on EPO OUT Ping Pong on all EPs Out In Out In Out In 0 0 1 0 E 1 O 2 0 E 1 O 2 3 O 1 2 3 3 4 4 E 5 6 E 7 O 2 4 5 5 6 8 E 9 O 10 E 11 O 3 6 7 7 8 12 E 13 O 14 E 15 O 4 8 9 9 10 16 E 17 O 18 E 19 O 5 10 11 11 12 20 E 21 O 22 E 23 O 6 12 13 13 14 24 E 25 O 26 E 27 O 7 14 15 15 16 28 E 29 O 30 E 31 O 8 16 17 17 18 32 E 33 O 34 E 35 O 9 18 19 19 20 36 E 37 O 38 E 39 O 10 20 21 21 22 40 E 41 O 42 E 43 O 11 22 23 23 24 44 E 45 O 46 E 47 O 12 24 25 25 26 48 E 49 O 50 E 51 13 26 27 27 28 52 E 53 O 54 E 55 14 28 29 29 30 56 E 57 58 E 59 O 15 30 31 31 32 60 E 61 O 62 E 63 O Legend EVEN transaction buffer ODD transaction buffer TABLE 14 5 SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BDnSTAT Drs PID3 2 1 20
65. PIC18F2450 4450 TABLE 4 4 INITIALIZATION CONDITIONS FOR ALL REGISTERS CONTINUED MCLR Resets Register Applicable Devices Power on Reset WDT Reset Wake up via WDT Brown out Reset RESET Instruction or Interrupt Stack Resets UEP8 2450 4450 0 0000 0 0000 u uuuu UEP7 2450 4450 0 0000 0 0000 u uuuu UEP6 2450 4450 0 0000 0 0000 u uuuu UEP5 2450 4450 0 0000 0 0000 u uuuu UEP4 2450 4450 0 0000 0 0000 u uuuu UEP3 2450 4450 0 0000 0 0000 u uuuu UEP2 2450 4450 0 0000 0 0000 u uuuu UEP1 2450 4450 0 0000 0 0000 u uuuu UEPO 2450 4450 0 0000 0 0000 u uuuu UCFG 2450 4450 00 0 0000 00 0 0000 uu u uuuu UADDR 2450 4450 000 0000 000 0000 uuu uuuu UCON 2450 4450 0x0 000 0x0 000 uuu uuu USTAT 2450 4450 XXX XXX XXX XXX uuu uuu UEIE 2450 4450 0 0 0000 0 0 0000 u u uuuu UEIR 2450 4450 0 0 0000 0 0 0000 u u uuuu UIE 2450 4450 000 0000 000 0000 uuu uuuu UIR 2450 4450 000 0000 000 0000 uuu uuuu UFRMH 2450 4450 XXX cA XXX uuu UFRML 2450 4450 XXXX XXXX XXXX XXXX uuuu uuuu Legend u unchanged x unknown unimplemented bit read as 0 q value depends on condition Shaded cells indicate conditions do not apply for the designated device Note 1 When the wake up is due to an interrupt and the GIEL or GIEH bit is set
66. R Readable bit C Clearable bit U Unimplemented bit read as 0 n Value when device is unprogrammed Unchanged from programmed state bit 7 bit 6 bit 5 bit 4 0 Note 1 Unimplemented Read as 0 WRTB Boot Block Write Protection bit 1 Boot block 000000 0007FFh or 000000 000FFFh is not write protected 0 Boot block 000000 0007FFh or 000000 000FFFh is write protected WRTC Configuration Register Write Protection bit 1 Configuration registers 300000 3000FFh are not write protected 0 Configuration registers 300000 3000FFh are write protected Unimplemented Read as 0 This bit is read only in normal execution mode it can be written only in Program mode DS39760C page 200 Preliminary 2007 Microchip Technology Inc PIC18F2450 4450 REGISTER 18 11 CONFIG7L CONFIGURATION REGISTER 7 LOW BYTE ADDRESS 30000Ch U 0 U 0 U 0 U 0 U 0 U 0 R C 1 R C 1 EBTR1 EBTRO bit 7 bit 0 Legend R Readable bit C Clearable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state bit 7 2 bit 1 bit O Unimplemented Read as 0 1 Table Read Protection bit 1 Block 1 002000 003FFFh is not protected from table reads executed in other blocks 0 Block 1 002000 003FFFh is protected from table reads executed in other blocks EBTRO Tabl
67. The PUSH instruction places the current PC value onto the stack This increments the Stack Pointer and loads the current PC value onto the stack The POP instruction discards the current TOS by decrementing the Stack Pointer The previous value pushed onto the stack then becomes the TOS value REGISTER 5 1 STKPTR STACK POINTER REGISTER R C 0 R C 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 STKFUL STKUNF SP4 SP3 SP2 SP1 SPO bit 7 bit 0 Legend C Clearable bit R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 STKFUL Stack Full Flag bit 1 Stack became full or overflowed 0 Stack has not become full or overflowed bit 6 STKUNF Stack Underflow Flag bit 1 Stack underflow occurred 0 Stack underflow did not occur bit 5 Unimplemented Read as 0 bit 4 0 5 4 5 0 Stack Pointer Location bits Note 1 Bit 7 and bit 6 are cleared by user software or by a POR 2007 Microchip Technology Inc Preliminary DS39760C page 55 PIC18F2450 4450 5 1 2 4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L When STVREN is set a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset When STVREN is c
68. Timer1 Oscillator 1 T1OSO TICKI x gt 1 i 1 Prescaler Synchronize Fosc 4 Detect 0 A Internal iuda 0 T1OSI x Clock UOTA ume Sleep Input T1OSCEN TMRICS Timer1 T1ICKPS1 T1CKPSO On Off TISYNC TMR1ON Y Set Clear TMRiL High Byte H TMRIIF CCP Special Event Trigger Note 1 When enable bit T1OSCEN is cleared the inverter and feedback resistor are turned off to eliminate power drain ZN 7 s on Overflow UN Read TMR1L Write TMR1L 8 it 2 gt Internal Data Bus DS39760C page 116 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 11 2 16 Bit Read Write Mode Timer1 can be configured for 16 bit reads and writes see Figure 11 2 When the RD16 control bit T1CON lt 7 gt is set the address for TMR1H is mapped to a buffer register for the high byte of Timer1 A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte followed by a read of the low byte has become invalid due to a rollover between reads A write to the high byte of Timer1 must also take place through the TMR1H Buffer register The Timer1 high byte is updated with the contents of TMR1H when a wri
69. W skip if f W unsigned comparison Status Affected None Encoding 0110 000a EEFT Description Compares the contents of data memory location f to the contents of W by performing an unsigned subtraction If the contents of are less than the contents of W then the fetched instruction is discarded and a NOP is executed instead making this a two cycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default Words 1 Cycles 1 2 Q Cycle Activity Note cycles if skip and followed by a 2 word instruction Q1 Q2 Q3 Q4 Decode Read Process No register Data operation If skip Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example HERE CPFSGT REG 0 NGREATER GREATER Before Instruction Q1 Q2 Q3 Q4 Decode Read Process No register Data operation If skip Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example HERE CPFSLT REG 1 NLESS LESS Before Instruction PC Address HERE W Afte
70. bit 7 bit 0 Legend R Readable bit C Clearable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state bit 7 bit 6 bit 5 0 2007 Microchip Technology Inc Unimplemented Read as 0 CPB Boot Block Code Protection bit 1 Boot block 000000 0007FFh or 000000 000FFFh is not code protected 0 Boot block 000000 0007FFh or 000000 000FFFh is code protected Unimplemented Read as 0 Preliminary DS39760C page 199 PIC18F2450 4450 REGISTER 18 9 CONFIG6L CONFIGURATION REGISTER 6 LOW BYTE ADDRESS 30000Ah U 0 U 0 U 0 U 0 U 0 U 0 R C 1 R C 1 WRT1 WRTO bit 7 bit 0 Legend R Readable bit C Clearable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state bit 7 2 bit 1 bit O Unimplemented Read as 0 WRT1 Write Protection bit 1 Block 1 002000 003FFFh is not write protected 0 Block 1 002000 003FFFh is write protected WRTO Write Protection bit 1 Block 0 000800 001FFFh or 001000 001FFFh is not write protected 0 Block 0 000800 001FFFh or 001000 001FFFh is write protected REGISTER 18 10 CONFIG6H CONFIGURATION REGISTER 6 HIGH BYTE ADDRESS 30000Bh U 0 R C 1 R 1 U 0 U 0 U 0 U 0 U 0 m WRTB WRTC B m bit 7 bit 0 Legend
71. port without the interfaces to other peripherals is shown in Figure 9 1 FIGURE 9 1 GENERIC I O PORT OPERATION RD LAT Data Bus 040 D gt e WR LAT pin or PORT CK Data Latch e D Q e WR TRIS CK X TRIS Latch Input 5 lt RD TRIS Q D RD PORT gt Note 1 pins have diode protection to VDD and Vss 9 1 PORTA TRISA and LATA Registers PORTA is an 8 bit wide bidirectional port The corresponding Data Direction register is TRISA Setting a TRISA bit 1 will make the corresponding PORTA pin an input i e put the corresponding output driver in a high impedance mode Clearing a TRISA bit 0 will make the corresponding PORTA pin an output i e put the contents of the output latch on the selected pin Reading the PORTA register reads the status of the pins writing to it will write to the port latch The Output Latch register LATA is also memory mapped Read modify write operations on the LATA register read and write the latched output value for PORTA The RA4 pin is multiplexed with the TimerO module clock input to become the RA4 TOCKI pin The RAG pin is multiplexed with the main oscillator pin it is enabled as an oscillator or I O pin by the selection of the main oscillator Configuration Register 1H see Section 18 1 Configuration Bits for details When not used as a port pin RA6 and its asso
72. 34 4 pins Note Refer to Figure 21 4 for load conditions FIGURE 21 8 BROWN OUT RESET TIMING VDD BVDD t 35 1 VBGAP 1 2V VIRVST S Enable Internal Reference Voltage Internal Reference Voltage Stable 4 36 TABLE 21 10 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER POWER UP TIMER AND BROWN OUT RESET REQUIREMENTS Symbol Characteristic Min Typ Max Units Conditions 30 TmcL MCLR Pulse Width low 2 us 31 Twpr Watchdog Timer Time out Period 4 00 4 6 ms no postscaler 32 TosT Oscillator Start up Timer Period 1024 1024 Tosc Tosc OSC1 period 33 TPWRT Timer Period 65 5 75 ms 34 Tioz I O High Impedance from MCLR 2 us Low or Watchdog Timer Reset 35 TBOR Brown out Reset Pulse Width 200 us VDD lt see 0005 36 TIRVST Time for Internal Reference 20 50 us Voltage to become Stable 37 TLVD Low Voltage Detect Pulse Width 200 us lt VLVD 38 TCSD CPU Start up Time 5 10 us 39 TIOBST Time for INTRC to Stabilize 1 ms DS39760C page 288 Preliminary 2007 Microchip Technology Inc PIC18F2450 4450 FIGURE 21 9 TIMERO AND TIMER1 EXTERNAL CLOCK TIMINGS lt T1OSO T1CKI 4 45 TOCKI
73. 5 data input disabled when analog input enabled AN4 1 IN ANA input channel 4 Default configuration on POR HLVDIN 1 IN ANA High Low Voltage Detect external trip point input OSC2 CLKO OSC2 x OUT ANA Main oscillator feedback output connection all XT and HS modes RAG CLKO x OUT DIG System cycle clock output Fosc 4 available in EC ECPLL and INTCKO modes RA6 0 OUT DIG LATA lt 6 gt data output Available only in ECIO ECPIO and INTIO modes otherwise reads as 0 1 IN TTL PORTA lt 6 gt data input Available only in ECIO ECPIO and INTIO modes otherwise reads as 0 Legend OUT Output IN Input ANA Analog Signal DIG Digital Output ST Schmitt Buffer Input TTL TTL Buffer Input x Don t care TRIS bit does not affect port direction or is overridden for this option TABLE 9 2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page PORTA m RAe RA5 RA4 RA3 RA2 RA1 RAO 51 LATA LATA6 LATAS LATA4 LATA3 LATA2 LATA1 LATAO 51 TRISA TRISAe TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 51 ADCON 1 VCFG1 VCFGO PCFG3 PCFG2 PCFG1 PCFGO 50 UCON PPBRST SEO PKTDIS USBEN RESUME SUSPND 52 Legend unimplemented read as 0 Shaded cells are not used by PORTA Note 1 RAG6 and its associated latch and data direction bits are e
74. A complete discussion of device Resets and interrupts is available in previous sections of this data sheet In addition to their Power up and Oscillator Start up Timers provided for Resets PIC18F2450 4450 devices have a Watchdog Timer which is either permanently enabled via the Configuration bits or software controlled if configured as disabled The inclusion of an internal RC oscillator also provides the additional benefits of a Fail Safe Clock Monitor FSCM and Two Speed Start up FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure Two Speed Start up enables code to be executed almost immediately on start up while the primary clock source completes its start up delays All of these features are enabled and configured by setting the appropriate Configuration register bits 2007 Microchip Technology Inc Preliminary DS39760C page 191 PIC18F2450 4450 18 1 The Configuration bits can be programmed read as 0 or left unprogrammed read as 1 to select various device configurations These bits are mapped starting at program memory location 300000h The user will note that address 300000h is beyond the user program memory space In fact it belongs to the configuration memory space 300000h 3FFFFFh which can only be accessed using table reads and table writes Configuration Bits Programming the Configuration registers is done in a
75. AN7 IN ANA A D input channel 7 default configuration on POR MCLR VPP MCLR 0 IN ST External Master Clear input enabled when MCLRE Configuration bit RE3 is set VPP 1 IN ANA High voltage detection used for ICSP mode entry detection Always available regardless of pin mode RE3 0 IN ST lt 3 gt data input enabled when MCLRE Configuration bit is clear Legend OUT Output IN Input ANA Analog Signal DIG Digital Output ST Schmitt Buffer Input Note 1 does not have a corresponding TRISE lt 3 gt bit This pin is always an input regardless of mode TABLE 9 10 SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page PORTE m m RE3 2 RE20 1 RE0 51 LATE LATE2 LATE1 LATEO 51 TRISE TRISE2 TRISE1 TRISEO 51 ADCON1 1 VCFGO PCFG3 PCFG2 PCFG1 PCFGO 50 Legend unimplemented read as 0 Note 1 Implemented only when Master Clear functionality is disabled MCLRE Configuration bit 0 otherwise read as 0 2 is the only PORTE bit implemented on both 28 pin and 40 44 pin devices All other bits are implemented only when PORTE is implemented i e 40 44 pin devices 3 These registers and or bits are unimplemented on 28 pin devices DS39760C page 110 Preliminary 2007 Microchip Technology In
76. B b 3 bit position of bit in file register f a 0 to force Access Bank a 1 for BSR to select bank f 8 bit file register address Literal operations 15 8 7 0 OPCODE k literal MOVLW 7Fh 8 bit immediate value Control operations CALL GOTO and Branch operations 15 87 0 OPCODE n lt 7 0 gt literal GOTO Label 15 12 11 0 1111 n lt 19 8 gt literal n 20 bit immediate value 15 8 7 0 OPCODE S n lt 7 0 gt literal CALL MYFUNC 15 12 11 0 1111 n lt 19 8 gt literal S Fast bit 15 11 10 0 OPCODE n lt 10 0 gt literal BRA MYFUNC 15 87 0 OPCODE n lt 7 0 gt literal BC MYFUNC 2007 Microchip Technology Inc Preliminary DS39760C page 215 PIC18F2450 4450 TABLE 19 2 PIC18FXXXX INSTRUCTION SET Mnemonic Tm 16 Bit Instruction Word Status Description Cycles Notes Operands MSb LSb Affected BYTE ORIENTED OPERATIONS ADDWF f d a Add WREG andf 1 0010 014 fff ffff 2 1 2 ADDWFC f d a Add WREG and Carry bit to f 1 0010 00da fff ffff 2 1 2 ANDWF AND WREG with f 1 0001 014 fff ffff 2 1 2 CLRF Clear f 1 0110 101a fff Z 2 COMF Complement f 1 0001 11 ffff 2 1 2 CPFSEQ Compare f with WREG Skip 1
77. CCPR1L F9Eh PIR1 F7Eh UEP14 CCP1CON F9Dh PIE1 F7Dh UEP13 m2 F9Ch F7Ch UEP12 m2 F9Bh 9 F7Bh UEP11 2 F9Ah m2 F7Ah UEP10 2 F99h m2 F79h UEP9 BAUDCON F98h 2 F78h UEP8 2 F97h 2 F77h UEP7 F96h TRISE F76h UEP6 e F95h TRISD F75h UEP5 0 F94h TRISC F74h UEP4 2 F93h TRISB F73h UEP3 F92h TRISA F72h UEP2 2 F91h m2 F71h UEP1 SPBRGH F90h A F70h UEPO SPBRG F8Fh F6Fh UCFG RCREG F8Eh 2 F6Eh UADDR TXREG F8Dh LATE F6Dh UCON TXSTA F8Ch LATD F6Ch USTAT RCSTA F8Bh LATC F6Bh UEIE 2 F8Ah LATB F6Ah UEIR e F89h LATA F69h UIE F88h m2 F68h UIR EECON2 F87h m2 F67h UFRMH EECON1 F86h m2 F66h UFRML 2 F85h F65h m2 F84h PORTE F64h m2 m2 F83h PORTD F63h IPR2 F82h PORTC F62h m2 PIR2 F81h PORTB F61h PIE2 F80h PORTA F60h m2 2 Unimplemented registers are read as 0 3 These registers are implemented only on 40 44 pin devices DS39760C page 62 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 5 2 REGISTER FILE SUMMARY PIC18F2450 4450 File Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 TOSU
78. DTSEN BDnSTAT 3 2 controls data toggle parity checking Setting DTSEN enables data toggle synchronization by the SIE When enabled it checks the data packet s parity against the value of DTS BDnSTAT 6 If a packet arrives with an incorrect synchronization the data will essentially be ignored It will not be written to the USB RAM and the USB transfer complete interrupt flag will not be set The SIE will send an ACK token back to the host to Acknowledge receipt however The effects of the DTSEN bit on the SIE are summarized in Table 14 3 The Buffer Stall bit BSTALL BDnSTAT lt 2 gt provides support for control transfers usually one time stalls on Endpoint 0 It also provides support for the SET FEATURE CLEAR FEATURE commands speci fied in Chapter 9 of the USB specification typically continuous STALLs to any endpoint other than the default control endpoint The BSTALL bit enables buffer stalls Setting BSTALL causes the SIE to return a STALL token to the host if a received token would use the BD in that location The EPSTALL bit in the corresponding UEPn control register is set and a STALL interrupt is generated when a STALL is issued to the host The UOWN bit remains set and the BDs are not changed unless a SETUP token is received In this case the STALL condition is cleared and the ownership of the BD is returned to the microcontroller core The BD9 BD8 bits 5 lt 1 0 gt store the two most significan
79. Direct Addressing using the BSR to select the data memory bank operates in the same manner as previously described REMAPPING THE ACCESS BANK WITH INDEXED LITERAL press gi 00h Bank 1 Window FIGURE 5 9 OFFSET ADDRESSING Example Situation ADDWF f d 000h FSR2H FSR2L 120h Bank 0 Locations in the region from the FSR2 Pointer 100h 120h to the pointer plus 120h 5 17Fh are mapped Window to the bottom of the Bank 1 Access RAM 000h 05Fh 200h Special Function Regis ters at F60h through FFFh are mapped to 60h wal Bank 2 through FFh as usual through Bank 0 addresses below Bank 14 5Fh are not available in this mode They can still be addressed by using the FOOh BSR Bank 15 F60h SFRs FFFh Data Memory 5 60h SFRs FFh Access Bank DS39760C page 72 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 6 0 FLASH PROGRAM MEMORY The Flash program memory is readable writable and erasable during normal operation over the entire VDD range A read from program memory is executed on one byte at a time A write to program memory is executed on blocks of 16 bytes at a time Program memory is erased in blocks of 64 bytes at a time A Bulk Erase operation may not be issued from user code Writing or erasing program memory will cease instruction fetches until the operation is complete The program mem
80. ECPIO 4 10 24 MHz 6 11 16 MHz Legend All clock frequencies except 24 MHz are exclusively associated with full speed USB operation USB clock of 48 MHz Bold is used to highlight clock selections that are compatible with low speed USB operation system clock of 24 MHz USB clock of 6 MHz Note 1 Only valid when the USBDIV Configuration bit is cleared DS39760C page 28 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 2 3 OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION CONTINUED Input Oscillator PLL Division Clock Mode MCU Clock Division Microcontroller Frequency PLLDIV2 PLLDIVO FOSC3 FOSCO CPUDIV1 CPUDIVO Clock Frequency None 00 12 MHz 22 01 6 MHz HS EC 3 10 4 MHz 4 11 3 MHz 12 MHz 3 010 2 00 48 MHz 3 01 32 MHz HSPLL ECPLL ECPIO 4 10 24 MHz 6 11 16 MHz None 00 8 MHz 2 01 4 MHz HS EC ECIO 3 10 2 67 MHz 4 11 2 MHz 8 MHz 2 001 2 00 48 MHz 3 01 32 MHz HSPLL ECPLL ECPIO 4 10 24 MHz 6 11 16 MHz None 00 4 MHz 2 01 2 MHz XT HS EC ECIO 3 10 1 33 MHz 4 11 1 MHz 4 MHz 1 000 2 00 48 MHz HSPLL ECPLL XTPLL 3 01 32 2 4 10 24 MHz 6 11 16 MHz Legend All clock frequencies except 24 MHz are exclusively associated with full speed USB operation USB clock of 48 MHz B
81. FIGURE 18 2 TIMING TRANSITION FOR TWO SPEED START UP INTRC TO HSPLL Q1 Q2 Q3 Q4 QT ceres 02 03 04 01 02 212 27 i ae TPO D Clock Re i CPU Clock EN Yes Penpneral 1 Y lat atv RS Cite gt PCT CPES Wake from Interrupt Event OSTS bit Set Note 1 1024 Tosc TPLL 2 ms approx These intervals are not shown to scale 2007 Microchip Technology Inc Preliminary DS39760C page 205 PIC18F2450 4450 18 4 Fail Safe Clock Monitor The Fail Safe Clock Monitor FSCM allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator The FSCM function is enabled by setting the FCMEN Configuration bit When FSCM is enabled the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure Clock monitoring shown in Figure 18 3 is accomplished by creating a sample clock signal which is the INTRC output divided by 64 This allows ample time between FSCM sample clocks for a peripheral clock edge to occur The peripheral device clock and the sample clock are presented as inputs to the Clock Monitor latch CM The CM is set on the falling edge of the device clock source but cleared on the rising e
82. Master Clear Reset MCLR 43 Memory Organization Data Memory Program Memory Memory Programming Requirements 280 Microchip Internet Web Site Migration from Baseline to Enhanced Devices 306 Migration from High End to Enhanced Devices 307 Migration from Mid Range to Enhanced Devices 307 MOVE tet edet C rep p a on 237 MPLAB ASM30 Assembler Linker Librarian 264 MPLAB ICD 2 In Circuit Debugger 265 MPLAB ICE 2000 High Performance Universal In Circuit Emulator essen 265 MPLAB Integrated Development Environment Software MPLAB Device Programmer MPLAB REAL ICE In Circuit Emulator System x MPLINK Object Linker MPLIB Object Librarian 264 kyoto teta e ete iind 240 MULNWE ihr rh pr em iter rerit 240 N Oscillator Selection gi Oscillator Settings for USB 27 Oscillator Start up Timer 32 45 Oscillator Switching Oscillator Transitions ds Oscillator Tier terree P Packaging Information 2 Details kia oa o er re e ee re nue Ree Mc PICkit 2 Development Programmer
83. None 1 2 BTFSC f b a Bit Test f Skip if Clear 1 20 3 1011 bbba ffff ffff None 3 4 BTFSS f b a Bit Test f Skip if Set 1 20 3 1010 bbba ffff ffff None 3 4 BTG Toggle f 1 0111 bbba ffff None 1 2 CONTROL OPERATIONS BC n Branch if Carry 1 2 1110 0010 nnnn nnnn BN n Branch if Negative 1 2 1110 0110 nnnn nnnn BNC n Branch if Not Carry 1 2 1110 0011 nnnn nnnn BNN n Branch if Not Negative 1 2 1110 0111 nnnn nnnn BNOV n Branch if Not Overflow 1 2 1110 0101 nnnn nnnn BNZ n Branch if Not Zero 1 2 1110 0001 nnnn nnnn BOV n Branch if Overflow 1 2 1110 0100 nnnn nnnn BRA n Branch Unconditionally 2 1101 Onnn nnnn nnnn BZ n Branch if Zero 1 2 1110 0000 nnnn nnnn CALL n Call Subroutine 1st word 2 1110 110s kkkk None 2nd word 1111 CLRWDT Clear Watchdog Timer 1 0000 0000 0000 0100 TO PD DAW Decimal Adjust Wreg 1 0000 0000 0000 0111 GOTO n Go To Address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP No Operation 1 0000 0000 0000 0000 None NOP No Operation 1 1111 xxxx xxxx xxxx None 4 POP Pop Top of Return Stack TOS 1 0000 0000 0000 0110 None PUSH Push Top of Return Stack TOS 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 i1nnn nnnn None RESET Software Device Reset 1 0000 0000 1111 1111 Al
84. Skip if 0 TSTFSZ f a 0 lt lt 255 0 1 skip if f 0 None 0110 011a ffff If 2 0 the next instruction fetched during the current instruction execution is discarded and a NOP is executed making this a two cycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 19 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details 1 1 2 Note cycles if skip and followed by a 2 word instruction Q1 Q2 Q3 Q4 Decode Read Process No register Data operation If skip Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example HERE TSTFSZ CNT 1 NZERO ZERO Before Instruction PC After Instruction Address HERE 00h Address ZERO 00h Address NZERO How oH d XORLW Exclusive OR Literal with W Syntax XORLW Operands 0 lt k lt 255 Operation W XOR k Status Affected N Z Encoding 0000 1010 kkkk kkkk Description
85. TABLE 9 1 PORTA I O SUMMARY Pin Function Sb y o Type Description RAO ANO RAO 0 OUT DIG LATA lt 0 gt data output not affected by analog input IN TTL PORTA O0 data input disabled when analog input enabled ANO IN ANA A D input channel 0 Default configuration on POR does not affect digital output RA1 AN1 RA1 0 OUT DIG LATA lt 1 gt data output not affected by analog input IN TTL lt 1 gt data input reads 0 POR AN1 IN ANA input channel 1 Default configuration on POR does not affect digital output RA2 AN2 RA2 0 OUT DIG LATA lt 2 gt data output not affected by analog input VREF IN TTL lt 2 gt data input Disabled when analog functions enabled AN2 IN ANA A D input channel 2 Default configuration on POR not affected by analog output VREF IN ANA voltage reference low input RA3 AN3 RA3 0 OUT DIG LATA lt 3 gt data output not affected by analog input VREF IN TTL lt 3 gt data input disabled when analog input enabled AN3 IN ANA input channel 3 Default configuration on POR VREF IN ANA A D voltage reference high input RA4 TOCKI RA4 0 OUT DIG LATA lt 4 gt data output not affected by analog input RCV IN ST PORTA lt 4 gt data input disabled when analog input enabled TOCKI IN ST TimerO clock input RCV x IN TTL External USB transceiver RCV input RAS AN4 RA5 0 OUT DIG LATA lt 5 gt data output not affected by analog input HLVDIN 1 IN TTL PORTA
86. TMR2IP 51 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 RCREG EUSART Receive Register 50 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 BAUDCON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register High Byte 51 SPBRG EUSART Baud Rate Generator Register Low Byte 50 Legend unimplemented read as 0 Shaded cells are not used for synchronous master reception 2007 Microchip Technology Inc Preliminary DS39760C page 171 PIC18F2450 4450 15 4 EUSART Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit CSRC TXSTA lt 7 gt This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK pin instead of being supplied internally in Master mode This allows the device to transfer or receive data while in any low power mode 15 4 1 EUSART SYNCHRONOUS SLAVE TRANSMIT The operation of the Synchronous Master and Slave modes is identical except in the case of Sleep mode If two words are written to the TXREG register and then the SLEEP instruction is executed the following will occur a The first word will immediately transfer to the TSR register and transmit b The second word will remain in the TXREG register c Flag bit TXIF will not be set d When the first word has been shifted out of TSR the TXREG register will transfer the second word to the TSR and flag
87. The clocks and instruction execution flow are shown in Figure 5 3 5 2 2 INSTRUCTION FLOW PIPELINING An Instruction Cycle consists of four Q cycles Q1 through Q4 The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle while the decode and execute takes another instruction cycle However due to the pipelining each instruction effectively executes in one cycle If an instruction causes the program counter to change e g GOTO then two cycles are required to complete the instruction Example 5 3 A fetch cycle begins with the Program Counter PC incrementing in Q1 In the execution cycle the fetched instruction is latched into the Instruction Register IR in cycle Q1 This instruction is then decoded and executed during the Q2 Q3 and Q4 cycles Data memory is read during Q2 operand read and written during Q4 destination write FIGURE 5 3 CLOCK INSTRUCTION CYCLE Q2 Q3 Q4 Q2 03 04 02 Q3 Q4 OSC1 NV V N SR Q1 y Q2 ____ Internal as ee A Q4 f 1 2 4 OSC2 CLKO a ee RC mode Execute INST PC 2 Fetch INST PC Execute INST PC Fetch INST PC 2 Execute INST PC 2 Fetch INST PC 4 EXAMPLE 5 3 INS
88. Universal Serial Bus USB Module 1 1 10 Bit Analog to Digital Module 10 Input Channels 13 Input Channels Resets and Delays POR BOR ET Instruction Stack Full RE Stack Underflow PWRT OST MCLR optional POR BOR ET Instruction Stack Full Stack Underflow PWRT OST MCLR optional RE WDT WDT Programmable Low Voltage Detect Yes Yes Programmable Brown out Reset Yes Yes Instruction Set 75 Instructions 83 with Extended Instruction Set 75 Instructions 83 with Extended Instruction Set enabled enabled Packages 28 Pin SPDIP 40 Pin PDIP 28 Pin SOIC 44 Pin QFN 28 Pin QFN 44 Pin TQFP 2007 Microchip Technology Inc Preliminary DS39760C page 9 PIC18F2450 4450 FIGURE 1 1 PIC18F2450 28 PIN BLOCK DIAGRAM Data B
89. Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register Data destination Example 1 SUBWFB REG 1 0 Before Instruction 19h 0001 1001 W ODh 0000 1101 1 After Instruction OCh 0000 1011 W ODh 0000 1101 1 2 0 0 result is positive Example 2 SUBWFB REG 0 0 Before Instruction 1Bh 0001 1011 W 1Ah 0001 1010 0 After Instruction REG 1Bh 0001 1011 00h 1 Z 1 result is zero N 0 Example 3 SUBWFB REG 1 0 Before Instruction 03h 0000 0011 W OEh 0000 1101 1 After Instruction REG Fb5h 1111 0100 2 s comp W OEh 0000 1101 G 0 4 0 N 1 result is negative SWAPF Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Q1 Swap f SWAPF f d a 0 lt lt 255 0 1 0 1 f lt 3 0 gt gt gt dest lt 7 4 gt lt 7 4 gt gt dest lt 3 0 gt None 0011 10da fttt The upper and lower nibbles of register f are exchanged If d is 0 the result is placed in W If d is 1 the result is placed in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset A
90. cause this interrupt to occur Any RB 7 RB4 configured as an output is excluded from the interrupt on change comparison The pins are compared with the old value latched on the last read of PORTB The mismatch outputs of RB7 RB4 are ORed together to generate the RB Port Change Interrupt with Flag bit RBIF lt 0 gt The interrupt on change can be used to wake the device from Sleep The user in the Interrupt Service Routine can clear the interrupt in the following manner a Any read or write of PORTB except with the MOVFF ANY PORTB instruction This will end the mismatch condition b Clear flag bit RBIF A mismatch condition will continue to set flag bit RBIF Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared The interrupt on change feature is recommended for wake up on key depression operation and operations where PORTB is only used for the interrupt on change feature Polling of PORTB is not recommended while using the interrupt on change feature Pins RB2 and RB3 are multiplexed with the USB peripheral and serve as the differential signal outputs for an external USB transceiver TRIS configuration Refer to Section 14 2 2 2 External Transceiver for additional information on configuring the USB module for operation with an external transceiver EXAMPLE 9 2 CLRF PORTB INITIALIZING PORTB Initialize PORTB by clearing output data
91. in other words RUN mode The IDLEN and SCS bits are not affected by the wake up While in any Idle mode or Sleep mode a WDT time out will result in a WDT wake up to the Run mode currently specified by the 5 51 5 50 bits FIGURE 3 5 TRANSITION TIMING FOR ENTRY TO SLEEP MODE deu uu M IAE E OSC NNNM ER ee TEE NE es Perpa MF ae t3 Mook S ef ue o 7 1 Sleep 2 A FA FIGURE 3 6 TRANSITION TIMING FOR WAKE FROM SLEEP HSPLL A gt 02 03 04 01 02 03 04 01 02 03 04 01 Q2 Q3 04 osc EAS PLL Clock TPL i i 1 Output CPU Clock B i pene enn Counter X 2 X PC 4 X PC 6 X Wake Event OSTS bit Set Note1 Tost 1024 Tosc TPLL 2 ms approx These intervals are not shown to scale 2007 Microchip Technology Inc Preliminary DS39760C page 37 PIC18F2450 4450 3 4 1 PRI IDLE MODE This mode is unique among the three low power Idle modes in that it does not disable the primary device clock For timing sensitive applications this allows for the fastest resumption of device operation with its more accurate primary clock source since the clock source does not have to
92. s application other registers may also need to be saved Example 8 1 saves and restores the WREG STATUS and BSR registers during an Interrupt Service Routine SAVING STATUS WREG AND BSR REGISTERS IN RAM MOVWF W TEMP MOVFF STATUS STATUS TEMP MOVFF BSR BSR TEMP USER ISR CODE MOVFF BSR TEMP BSR MOVF W TEMP W MOVFF STATUS TEMP STATUS W TEMP is in virtual bank STATUS TEMP located anywhere BSR TMEP located anywhere Restore BSR Restore WREG Restore STATUS 2007 Microchip Technology Inc Preliminary DS39760C page 97 PIC18F2450 4450 NOTES sc P M DS39760C page 98 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 9 0 I O PORTS Depending on the device selected and features enabled there are up to five ports available Some pins of the I O ports are multiplexed with an alternate function from the peripheral features on the device In general when a peripheral is enabled that pin may not be used as a general purpose I O pin Each port has three registers for its operation These registers are TRIS register Data Direction register PORT register reads the levels on the pins of the device LAT register Output Latch register The Output Latch register LATA is useful for read modify write operations on the value driven by the I O pins A simplified model of a generic
93. such as a Real Time Clock RTC Most often a 32 768 kHz watch crystal is connected between the RCO T1OSO T1CKI and RC1 T1OSI UOE pins Like the XT and HS Oscillator mode circuits loading capacitors are also connected from each pin to ground The Timer1 oscillator is discussed in greater detail in Section 11 3 Timer1 Oscillator In addition to being a primary clock source the internal oscillator is available as a power managed mode clock source The INTRC source is also used as the clock source for several special features such as the WDT and Fail Safe Clock Monitor 2 4 1 OSCILLATOR CONTROL REGISTER The OSCCON register Register 2 1 controls several aspects of the device clock s operation both in full power operation and in power managed modes The System Clock Select bits SCS1 SCSO select the clock source The available clock sources are the primary clock defined by the FOSC3 FOSCO Configuration bits the secondary clock Timer1 oscillator and the internal oscillator The clock source changes immediately after one or more of the bits is written to following a brief clock transition interval The SCS bits are cleared on all forms of Reset INTRC always remains the clock source for features such as the Watchdog Timer and the Fail Safe Clock Monitor The OSTS and T1RUN bits indicate which clock source is currently providing the device clock The OSTS bit indicates that the Oscillator Start up Timer OST has timed out
94. the CPU begins execut ing code being clocked by the Timer1 oscillator The IDLEN and SCS bits are not affected by the wake up the Timer1 oscillator continues to run see Figure 3 8 Note The Timer1 oscillator should already be running prior to entering SEC IDLE mode If the TTOSCEN bit is not set when the SLEEP instruction is executed the SLEEP instruction will be ignored and entry to SEC IDLE mode will not occur If the Timer1 oscillator is enabled but not yet run ning peripheral clocks will be delayed until the oscillator has started In such situations initial oscillator operation is far from stable and unpredictable operation may result TRANSITION TIMING FOR ENTRY TO IDLE MODE ai 2 a4 Q1 Me ege cup ede ems HR ae ee CPU Clock cM Wea RETINET program ak 2 FIGURE 3 8 TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q2 Q3 Q4 OSC1 XN EE Ei CPU Clock IN A Peripheral o 43A F 3 Clock pains 3 Fc Wake Event DS39760C page 38 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 3 4 3 RC IDLE MODE In RC IDLE mode the CPU is disabled but the periph erals continue to be clocked from the internal oscillator
95. the TOSU TOSH and TOSL are updated with the current value of the PC The STKPTR is modified to point to the next location in the hardware stack 2 or more bits in the INTCONx or PIRx registers will be affected to cause wake up 3 When the wake up is due to an interrupt and the GIEL or GIEH bit is set the PC is loaded with the interrupt vector 0008h or 0018h 4 See Table 4 3 for Reset value for specific condition 5 PORTA lt 6 gt LATA lt 6 gt and TRISA lt 6 gt are enabled depending on the oscillator mode selected When not enabled as PORTA pins they are disabled and read 0 DS39760C page 52 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 5 0 MEMORY ORGANIZATION There are two types of memory in PIC18F2450 4450 microcontroller devices Program Memory Data RAM As Harvard architecture devices the data and program memories use separate busses this allows for concurrent access of the two memory spaces Additional detailed information on the operation of the Flash program memory is provided in Section 6 0 Flash Program Memory FIGURE 5 1 5 1 Program Memory Organization PIC18 microcontrollers implement a 21 bit program counter which is capable of addressing a 2 Mbyte program memory space Accessing a location between the upper boundary of the physically implemented memory and the 2 Mbyte address will return all 05 a NOP instruction The PIC18F2450 and PIC18F4450
96. the bus Endpoint 0 must be available to configure the device 14 9 2 FRAMES Information communicated on the bus is grouped into 1 ms time slots referred to as frames Each frame can contain many transactions to various devices and endpoints Figure 14 9 shows an example of a transaction within a frame 14 9 3 TRANSFERS There are four transfer types defined in the USB specification Isochronous This type provides a transfer method for large amounts of data up to 1023 bytes with timely delivery ensured however the data integrity is not ensured This is good for streaming applications where small data loss is not critical such as audio Bulk This type of transfer method allows for large amounts of data to be transferred with ensured data integrity however the delivery timeliness is not ensured Interrupt This type of transfer provides for ensured timely delivery for small blocks of data plus data integrity is ensured Control This type provides for device setup control While full speed devices support all transfer types low speed devices are limited to interrupt and control transfers only 14 9 4 POWER Power is available from the Universal Serial Bus The USB specification defines the bus power requirements Devices may either be self powered or bus powered Self powered devices draw power from an external source while bus powered devices use power supplied from the bus
97. 0 16 207 19 2 19 193 003 520 19231 0 16 259 19231 0 16 129 19 280 0 16 103 57 6 57 803 0 35 172 57471 0 22 86 58 140 0 94 42 57 142 079 34 115 2 114 943 0 22 86 116 279 0 94 42 113 636 1 36 21 117 647 2 12 16 SYNC 0 BRGH 1 BRG16 1 or SYNC 1 BRG16 1 SE Fosc 4 000 MHz Fosc 2 000 MHz Fosc 1 000 MHz k Actual SPBRG Actual Actual Rate Error value Rate Er r value Rate Eror value K decimal K decimal K decimal 0300 0 01 3332 0 300 0 04 1665 0 300 004 832 12 1200 004 832 1201 0 15 415 1 201 0 16 207 24 2404 0 16 415 2403 0 16 207 2403 0 16 103 96 9615 0 16 103 9615 0 16 51 9 615 0 16 25 19 2 19 231 0 16 51 19 230 0 16 25 19 230 016 12 57 6 58 824 2 12 16 55 555 3 55 8 3 RE 115 2 111 111 3 55 8 ES DS39760C page 160 Preliminary 2007 Microchip Technology Inc 1 18 2450 4450 15 1 3 AUTO BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate This feature is active only in Asynchronous mode and while the WUE bit is clear The automatic baud rate measurement sequence Figure 15 1 begins whenever a Start bit is received and the ABDEN bit is set The calculation is self aver aging In the Auto Baud Rate Detect ABD mode the clock to the BRG is reversed Rather than the BRG clocking the incomi
98. 010 Taca 4 TaD TACQ Cycles qua Lu 23d Cycles 6 7 8 9 10