ANALOG DEVICES AD9833 English products handbook Rev D
Contents
1. 0 100k 0 100k RWB 100 VWB 30 100 2 RWB 100 VWB 30 ST100SEC 5 FREQUENCY Hz 5 FREQUENCY Hz 5 Figure 14 Power vs Frequency 10 MHz four 2 4 kHz Figure 17 Power vs Frequency 25 MHz four 6 kHz Frequency Word 0x000FBA9 Frequency Word OxO00FBA9 Rev D Page 8 of 24 POWER dB POWER dB POWER dB i T TRE 1 RWB 300 VWB 100 ST 100 SEC FREQUENCY Hz Figure 18 Power vs Frequency 25 MHz four 60 kHz Frequency Word 0x009D495 0 12 5M RWB 1k VWB 300 ST 100 SEC FREQUENCY Hz Figure 19 Power vs Frequency 25 MHz four 600 kHz Frequency Word 0x0624DD3 0 12 5 RWB 1k VWB 300 ST 100 SEC FREQUENCY Hz Figure 20 Power vs Frequency fuck 25 MHz four 2 4 MHz Frequency Word 0x189374D 02704 018 02704 019 02704 020 AD9833 POWER dB h 60 70 80 90 100 12 5 RWB 1k VWB 300 ST 100 SEC 02704 021 FREQUENCY Hz Figure 21 Power vs Frequency 25 MHz four 3 857 MHz fuaw 7 Frequency Word 0x2492492 POWER dB h 60 70 80 90 100 12 5 RWB 1k VWB 300 ST 100 SEC 02704 022 FREQUENCY Hz Figure 22 Power vs Frequency2. 21 PowerSupply ue innet tetti terii eee teri seti 21 Evaluation Board Schematics sss 22 Evaluation Board Layout sse 23 Outline Dimensions eese tentent entente nenne 24 Ordering Guides soe treten 24 Automotive Products iet eerte 24 9 10 Rev B to Rev C Changed 20 mW to 12 65 mW in Data Sheet Title and Features List Changes to Figure 6 Caption and Figure 7 6 10 Rev A to Rev B Changes to Features Section 4 1 Changes to Serial Interface Section sss 13 Changes to VOUT Pin 0 2 16 Changes to Grounding and Layout 17 Updated Outline Dimensions eee 24 Changes to Ordering Guide sse 24 Added Automotive Products Section sss 24 6 03 Rev 0 to Rev A Updated Ordering Guide see 4 Rev D Page 2 of 24 SPECIFICATIONS AD9833 VDD 2 3 V to 5 5 V AGND 0 V Ta Tmn to Tmax Rer 6 8 for VOUT unless otherwise noted Table 1 Parameter Min Typ Max Unit Test Conditions Comments SIGNAL DAC SPECIFICATIONS Resolution 10 Bits Update Rate 25 MSPS VOUT Maximum 0 65 V VOUT Minimum 38 mV VOUT Temperature Coefficient 200 DC Accuracy Integral Nonlinearity 1 0 LSB Di
3. 25 MHz four 8 333 MHz fma s3 Frequency Word 0x5555555 Rev D Page 9 of 24 109833 TERMINOLOGY Integral Nonlinearity INL INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function The end points of the transfer function are zero scale a point 0 5 LSB below the first code transition 000 00 to 000 01 and full scale a point 0 5 LSB above the last code transition 111 10 to 111 11 The error is expressed in LSBs Differential Nonlinearity DNL DNL is the difference between the measured and ideal 1 LSB change between two adjacent codes in the DAC A specified DNL of 1 LSB maximum ensures monotonicity Output Compliance Output compliance refers to the maximum voltage that can be generated at the output of the DAC to meet the specifications When voltages greater than that specified for the output compli ance are generated the AD9833 may not meet the specifications listed in the data sheet Spurious Free Dynamic Range SFDR Along with the frequency of interest harmonics of the funda mental frequency and images of these frequencies are present at the output of a DDS device SFDR refers to the largest spur or harmonic present in the band of interest The wideband SFDR gives the magnitude of the largest spur or harmonic relative to the magnitude of the fundamental frequency in the zero to Nyquist bandwidth The narrow band SFDR gives t
4. 16 BIT WRITE D15 014 11 D13 0 1 CHOOSE THE PHASE REGISTER D12 X D11 DO PHASE DATA WRITE TO ANOTHER PHASE REGISTER 02704 028 109833 109833 INTERFACING TO MICROPROCESSORS The AD9833 has a standard serial interface that allows the part to interface directly with several microprocessors The device uses an external serial clock to write the data or control information into the device The serial clock can have a frequency of 40 MHz maximum The serial clock can be continuous or it can idle high or low between write operations When data or control informa tion is written to the AD9833 FSYNC is taken low and is held low until the 16 bits of data are written into the AD9833 The FSYNC signal frames the 16 bits of information that are loaded into the AD9833 AD9833 TO 68HC11 68L11 INTERFACE Figure 29 shows the serial interface between the AD9833 and the 68HC11 68L11 microcontroller The microcontroller is con figured as the master by setting the MSTR bit in the SPCR to 1 This setting provides a serial clock on SCK the MOSI output drives the serial data line SDATA Because the microcontroller does not have a dedicated frame sync pin the FSYNC signal is derived from a port line PC7 The setup conditions for correct operation of the interface are as follows e idles high between write operations CPOL 0 e Data is valid on the SCK falling edge 1 When data is being transmitted to
5. Board Section sss 21 Added System Demonstration Platform Section AD9833 to SPORT Interface Section and Evaluation Kit Section 21 Changes to Crystal Oscillator vs External Clock Section and Power Supply Section sse 21 Added Figure 32 and Figure 33 Renumbered Figures Sequentially zc 21 Deleted Prototyping Area Section and Figure 33 22 Added Evaluation Board Schematics Section Figure 34 and Figure 35 eden enenitmeu edere eter den 22 Deleted Table 16 Added Evaluation Board Layout Section Figure 36 Figure 37 and Figure 38 Changes to Ordering Guide Register eere t tts 13 Frequency and Phase Registers see 15 Reset F nctlon eee tee tette sarei aisi neess 16 Sleep F nction z uec RR RH RD QU 16 VOU T Pini sciet te HEREDES 16 Applications Information eene 17 Grounding and Layout sees 17 Interfacing to Microprocessors eerte 20 AD9833 to 68HC11 68L11 Interface ese 20 AD9833 to 80C51 80L51 Interface se 20 AD9833 to DSP56002 Interface sse 20 Evaluation Board ceno rete Hen eee 21 System Demonstration Platform sse 21 AD9833 to SPORT Interface 2 21 Evaluation Kit og 21 Crystal Oscillator vs External Clock
6. The AD9833 accepts the MSB first the four MSBs are the control information the next four bits are the address and the eight LSBs contain the data when writing to a destination register Therefore the transmit routine of the 80C51 80L51 must take this into account and rearrange the bits so that the MSB is output first 80C51 80L51 AD9833 02704 031 Figure 30 80C51 80L51 to AD9833 Interface AD9833 TO DSP56002 INTERFACE Figure 31 shows the interface between the AD9833 and the DSP56002 The DSP56002 is configured for normal mode asyn chronous operation with a gated internal clock SYN 0 GCK 1 SCKD 1 The frame sync pin is generated internally SC2 1 the transfers are 16 bits wide WL1 1 WLO 0 and the frame sync signal frames the 16 bits FSL 0 The frame sync signal is available on the SC2 pin but it must be inverted before it is applied to the AD9833 The interface to the DSP56000 DSP56001 is similar to that of the DSP56002 DSP56002 AD9833 02704 032 Figure 31 05 56002 to AD9833 Interface Rev D Page 20 of 24 109833 EVALUATION BOARD The AD9833 evaluation board allows designers to evaluate the high performance AD9833 DDS modulator with a minimum of effort SYSTEM DEMONSTRATION PLATFORM The system demonstration platform SDP is a hardware and software evaluation tool for use in conjunction with product evaluation boards The SDP board is based on the Blackfin ADSP BF527 processor
7. addressed frequency register The FSELECT bit defines whether the FREQO register or the FREOT register is used in the phase accumulator The PSELECT bit defines whether the PHASEO register or the PHASE1 register data is added to the output of the phase accumulator This bit should be set to 0 Reset 1 resets internal registers to 0 which corresponds to an analog output of midscale Reset 0 disables reset This function is explained further in Table 13 When 51 1 the internal MCLK clock is disabled and the DAC output remains at its present value because the NCO is no longer accumulating When SLEEP1 0 MCLK is enabled This function is explained further in Table 14 SLEEP12 1 powers down the on chip DAC This is useful when the AD9833 is used to output the MSB of the DAC data SLEEP12 0 implies that the DAC is active This function is explained further in Table 14 The function of this bit in association with D1 mode is to control what is output at the VOUT pin This is explained further in Table 15 When OPBITEN 1 the output of the DAC is no longer available at the VOUT pin Instead the MSB or MSB 2 of the DAC data is connected to the VOUT pin This is useful as a coarse clock source The DIV2 bit controls whether it is the 5 or MSB 2 that is output When OPBITEN 0 the DAC is connected to VOUT The mode bit determines whether it is a sinusoidal or a ramp output that is available This bit must be set to 0 DI
8. t4 25 ns min SCLK period ts 10 ns min SCLK high duration te 10 ns min SCLK low duration t7 5 ns min FSYNC to SCLK falling edge setup time ts min 10 ns min FSYNC to SCLK hold time 18 max 4 5 5 to 5 ns min Data setup time tio 3 ns min Data hold time ti 5 ns min SCLK high to FSYNC falling edge setup time Guaranteed by design not production tested Timing Diagrams t gt MCLK t 4 8 5 Figure 3 Master Clock FSYNC SDATA 015 D14 02704 004 Figure 4 Serial Timing Rev D Page 4 of 24 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 3 Parameter Rating VDD to AGND 0 3V to 6 V VDD to DGND 0 3V to 6 V AGND to DGND 0 3 V to 40 3 V CAP 2 5V 2 75V Digital I O Voltage to Analog I O Voltage to AGND Operating Temperature Range Industrial B Version Storage Temperature Range Maximum Junction Temperature MSOP Package Thermal Impedance Osc Thermal Impedance Lead Temperature Soldering 10 sec IR Reflow Peak Temperature 0 3V to VDD 0 3 V 0 3 V to VDD 0 3 V 40 C to 105 C 65 C to 150 C 150 C 206 C W 44 C W 300 C 220 C AD9833 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this speci
9. the AD9833 the FSYNC line is taken low PC7 Serial data from the 68HC11 68L11 is trans mitted in 8 bit bytes with only eight falling clock edges occurring in the transmit cycle Data is transmitted MSB first To load data into the AD9833 PC7 is held low after the first eight bits are transferred and a second serial write operation is performed to the AD9833 Only after the second eight bits are transferred should FSYNC be taken high again 68HC11 68L11 AD9833 02704 030 Figure 29 68HC11 68L11 to AD9833 Interface AD9833 TO 80C51 80L51 INTERFACE Figure 30 shows the serial interface between the AD9833 and the 80C51 80L51 microcontroller The microcontroller is oper ated in Mode 0 so that TxD of the 80C51 80L51 drives SCLK of the AD9833 and RxD drives the serial data line SDATA The FSYNC signal is derived from a bit programmable pin on the port P3 3 is shown in Figure 30 When data is to be transmitted to the AD9833 P3 3 is taken low The 80C51 80L51 transmits data in 8 bit bytes thus only eight falling SCLK edges occur in each cycle To load the remaining eight bits to the AD9833 P3 3 is held low after the first eight bits are transmitted and a second write operation is initiated to transmit the second byte of data P3 3 is taken high following the completion of the second write operation SCLK should idle high between the two write operations The 80C51 80L51 outputs the serial data in a format that has the LSB first
10. with USB connectivity to the PC through a USB 2 0 high speed port For more information about the SDP board see the SDP board product page Note that the SDP board is sold separately from the AD9833 evaluation board AD9833 TO SPORT INTERFACE The Analog Devices SDP board has a SPORT serial port that is used to control the serial inputs to the AD9833 The connections are shown in Figure 32 AD9833 SPORT_TFS FSYNC SPORT_TSCLK SCLK SPORT_DTO SDATA ADSP BF527 02704 034 Figure 32 SDP to AD9833 Interface EVALUATION KIT The DDS evaluation kit includes a populated tested AD9833 printed circuit board PCB The schematics of the evaluation board are shown in Figure 34 and Figure 35 The software provided in the evaluation kit allows the user to easily program the AD9833 see Figure 33 The evaluation soft ware runs on any IBM compatible PC with Microsoft Windows software installed including Windows 7 The software is com patible with both 32 bit and 64 bit operating systems More information about the evaluation software is available on the software CD and on the AD9833 product page sS AD9833 DDS 02704 035 Figure 33 AD9833 Evaluation Software Interface CRYSTAL OSCILLATOR VS EXTERNAL CLOCK The AD9833 can operate with master clocks up to 25 MHz 25 MHz oscillator is included the evaluation board This oscillator can be removed and if required an external CMOS clock can be connect
11. 100 four Hz Figure 7 Typical loo vs four for fuck 25 MHz Figure 10 Wideband SFDR vs four fucix for Various MCLK Frequencies 02704 007 02704 010 VDD 25 C four MCLK 4096 a a kJ kJ a z 50 8 1 0 5 0 10 0 12 5 25 0 5 3 i MCLK FREQUENCY MHz E MCLK FREQUENCY MHz 5 Figure 8 Narrow Band SFDR vs MCLK Frequency Figure 11 SNR vs MCLK Frequency Rev D Page 7 of 24 109833 1000 0 950 10 900 P 20 850 30 40 5 750 6 50 VDD 5 5V 8 700 Q i 5 650 70 4 600 80 500 100 40 25 105 5 0 5 TEMPERATURE RWB 1k VWB 300 ST50SEC 2 B FREQUENCY Hz Figure 12 Wake Up Time vs Temperature Figure 15 Power vs Frequency 10 MHz four 1 43 MHz 7 Frequency Word 0x2492492 1 250 0 10 1 225 20 UPPER RANGE 1 200 b POWER dB dr 60 1 150 70 80 1 125 90 1 100 5 100 40 25 105 5 0 5M TEMPERATURE C RWB 1k VWB 300 ST50SEC 5 8 3 FREQUENCY Hz Figure 13 Vrer vs Temperature Figure 16 Power vs Frequency 10 MHz four 3 33 MHz fuaw 3 Frequency Word 0x5555555 POWER dB POWER dB
12. 212 CHANGE CHANGE PHASE PSELECT NO NO CHANGE 2 CHANGE PHASE FSELECT CHANGEFREQUENCY REGISTER NO NO YES YES CHANGE FREQUENCY REGISTER CHANGE DAC OUTPUT FROM SIN TO RAMP NO CONTROL REGISTER CHANGE OUTPUT TO WRITE A DIGITAL SIGNAL NO SEE TABLE 6 Figure 26 Flowchart for AD9833 Initialization and Operation INITIALIZATION APPLY RESET CONTROL REGISTER WRITE RESET 1 WRITE TO FREQUENCY AND PHASE REGISTERS FREQO REG 228 FREQ1 REG 228 PHASEO AND PHASE1 REG PHASESHIFT x 212 21r SEE FIGURE 28 SET RESET 0 SELECT FREQUENCY REGISTERS SELECT PHASE REGISTERS CONTROL REGISTER WRITE RESET 0 FSELECT SELECTED FREQUENCY REGISTER PSELECT SELECTED PHASE REGISTER 02704 027 Figure 27 Flowchart for Initialization Rev D Page 18 of 24 02704 026 DATA WRITE WRITE A FULL 28 BIT WORD TO A FREQUENCY REGISTER CONTROL REGISTER WRITE B28 013 1 WRITE TWO CONSECUTIVE 16 BIT WORDS SEE TABLE 9 FOR EXAMPLE WRITE ANOTHER FULL 28 BIT WORD TOA FREQUENCY REGISTER WRITE 14MSBs OR LSBs TO A FREQUENCY REGISTER CONTROL REGISTER WRITE B28 D13 0 HLB 012 0 4 WRITE A 16 BIT WORD SEE TABLE 10 AND TABLE 11 FOR EXAMPLES WRITE 14MSBs OR LSBs TOA FREQUENCY REGISTER Figure 28 Flowchart for Data Writes Rev D Page 19 of 24 WRITE TO PHASE REGISTER
13. 6 bit word define the frequency register to which the word is loaded and should therefore be the same for both of the consecutive writes See Table 8 for the appropriate addresses The write to the frequency register occurs after both words have been loaded therefore the register never holds an intermediate value An example of a complete 28 bit write is shown in Table 9 When B28 0 the 28 bit frequency register operates as two 14 bit registers one containing the 14 MSBs and the other containing the 14 LSBs This means that the 14 MSBs of the frequency word can be altered independent of the 14 LSBs and vice versa To alter the 14 MSBs or the 14 LSBs a single write is made to the appropriate frequency address The control bit D12 HLB informs the AD9833 whether the bits to be altered are the 14 MSBs or 14 LSBs This control bit allows the user to continuously load the MSBs or LSBs of a frequency register while ignoring the remaining 14 bits This is useful if the complete 28 bit resolution is not required HLB is used in conjunction with D13 B28 This control bit indicates whether the 14 bits being loaded are being transferred to the 14 MSBs or 14 LSBs of the addressed frequency register 013 828 must be set to 0 to be able to change the MSBs and LSBs of a frequency word separately When D13 B28 1 this control bit is ignored HLB 1 allows a write to the 14 MSBs of the addressed frequency register HLB 0 allows a write to the 14 LSBs of the
14. ANALOG DEVICES Low Power 12 65 mW 2 3 V to 5 5 V Programmable Waveform Generator AD9833 FEATURES Digitally programmable frequency and phase 12 65 mW power consumption at 3 V 0 MHz to 12 5 MHz output frequency range 28 bit resolution 0 1 Hz at 25 MHz reference clock Sinusoidal triangular and square wave outputs 2 3 V to 5 5 V power supply No external components required 3 wire SPI interface Extended temperature range 40 C to 105 C Power down option 10 lead MSOP package Qualified for automotive applications APPLICATIONS Frequency stimulus waveform generation Liquid and gas flow measurement Sensory applications proximity motion and defect detection Line loss attenuation Test and medical equipment Sweep clock generators Time domain reflectometry TDR applications GENERAL DESCRIPTION The AD9833 is a low power programmable waveform generator capable of producing sine triangular and square wave outputs Waveform generation is required in various types of sensing actuation and time domain reflectometry TDR applications The output frequency and phase are software programmable allowing easy tuning No external components are needed The frequency registers are 28 bits wide with a 25 MHz clock rate resolution of 0 1 Hz can be achieved with a 1 MHz clock rate the AD9833 can be tuned to 0 004 Hz resolution The AD9833 is written to via a 3 wire serial interface This serial interface operates at cl
15. ORT_DR3 SPORT RSCLK ISCLK ISDATA FSYNC PARALLEL PORT 3 3V_BF 5V EXT VIO USE to set 10 voltage max draw 20mA Figure 35 SDP Connector Schematic Rev D Page 22 of 24 02704 037 109833 EVALUATION BOARD LAYOUT sececescesecos LASS LI LILI ee 02704 038 02704 040 Figure 38 AD9833 Evaluation Board Solder Side 02704 039 Figure 37 AD9833 Evaluation Board Silkscreen Rev D Page 23 of 24 109833 OUTLINE DIMENSIONS 091709 A COMPLIANT TO JEDEC STANDARDS MO 187 BA Figure 39 10 Lead Mini Small Outline Package MSOP RM 10 Dimensions shown in millimeters ORDERING GUIDE Model 2 3 Temperature Range Package Description Package Option Branding AD9833BRM 40 C to 105 C 10 Lead MSOP RM 10 DJB AD9833BRM REEL 40 C to 105 C 10 Lead MSOP RM 10 DJB AD9833BRM REEL7 40 C to 105 C 10 Lead MSOP RM 10 DJB AD9833BRMZ 40 C to 105 C 10 Lead MSOP RM 10 D68 AD9833BRMZ REEL 40 C to 105 C 10 Lead MSOP RM 10 D68 AD9833BRMZ REEL7 40 C to 105 C 10 Lead MSOP RM 10 D68 AD9833WBRMZ REEL 40 C to 105 C 10 Lead MSOP RM 10 D68 EVAL AD9833SDZ Evaluation Board 17 RoHS Compliant Part W Qualified for Automotive Applications 3 T
16. V the CAP 2 5V and VDD pins should be tied together thus bypassing the on board regulator Rev D Page 12 of 24 FUNCTIONAL DESCRIPTION SERIAL INTERFACE The AD9833 has a standard 3 wire serial interface that is compatible with the SPI QSPI MICROWIRE and DSP interface standards Data is loaded into the device as a 16 bit word under the control of a serial clock input SCLK The timing diagram for this operation is given in Figure 4 The FSYNC input is a level triggered input that acts as a frame synchronization and chip enable Data can be transferred into the device only when FSYNC is low To start the serial data transfer FSYNC should be taken low observing the minimum FSYNC to SCLK falling edge setup time tz After FSYNC goes low serial data is shifted into the input shift register of the device on the falling edges of SCLK for 16 clock pulses FSYNC may be taken high after the 16th falling edge of SCLK observing the minimum SCLK falling edge to FSYNC rising edge time ts Alternatively FSYNC can be kept low for a multiple of 16 SCLK pulses and then brought high at the end of the data transfer In this way a continuous stream of 16 bit words can be loaded while FSYNC is held low FSYNC goes high only after the 16th SCLK falling edge of the last word loaded The SCLK can be continuous or it can idle high or low between write operations In either case it must be high when FSYNC goes low ti For an example of ho
17. V2 is used in association with D5 OPBITEN This is explained further in Table 15 When DIV2 1 the MSB of the DAC data is passed directly to the VOUT pin When DIV2 0 the MSB 2 of the DAC data is output at the VOUT pin This bit must be set to O This bit is used in association with OPBITEN D5 The function of this bit is to control what is output at the VOUT pin when the on chip DAC is connected to VOUT This bit should be set to 0 if the control bit OPBITEN 1 This is explained further in Table 15 When mode 1 the SIN ROM is bypassed resulting in a triangle output from the DAC When mode 0 the SIN ROM is used to convert the phase information into amplitude information which results in a sinusoidal signal at the output This bit must be set to O Rev D Page 14 of 24 FREQUENCY AND PHASE REGISTERS The AD9833 contains two frequency registers and two phase registers which are described in Table 7 Table 7 Frequency and Phase Registers AD9833 Table 9 Writing 0xFFFC000 to the FREQO Register SDATA Input Result of Input Word Register Size Description FREQO 28 bits Frequency Register 0 When the FSELECT bit 0 this register defines the output frequency as a fraction of the MCLK frequency FREO1 28 bits Frequency Register 1 When the FSELECT bit 1 this register defines the output frequency as a fraction of the MCLK frequency PHASEO 12bits Phase Offset Register 0 When the PSELECT
18. a reference interval clock period the phase rotation for that period can be determined APhase wAt Solving for w w APhase At 2nf Solving for f and substituting the reference clock frequency for the reference period 1 fuax At f x 2 The AD9833 builds the output based on this simple equation A simple DDS chip can implement this equation with three major subcircuits numerically controlled oscillator NCO and phase modulator SIN ROM and digital to analog converter DAC Each subcircuit is described in the Circuit Description section Rev D Page 11 of 24 109833 CIRCUIT DESCRIPTION The AD9833 is a fully integrated direct digital synthesis DDS chip The chip requires one reference clock one low precision resistor and decoupling capacitors to provide digitally created sine waves up to 12 5 MHz In addition to the generation of this signal the chip is fully capable of a broad range of simple and complex modulation schemes These modulation schemes are fully implemented in the digital domain allowing accurate and simple realization of complex modulation algorithms using DSP techniques The internal circuitry of the AD9833 consists of the following main sections a numerically controlled oscillator NCO frequency and phase modulators SIN ROM a DAC and a regulator NUMERICALLY CONTROLLED OSCILLATOR PLUS PHASE MODULATOR This consists of two frequency select registers a ph
19. ase accumulator two phase offset registers and a phase offset adder The main component of the NCO is a 28 bit phase accumulator Continuous time signals have a phase range of 0 to 2 Outside this range of numbers the sinusoid functions repeat themselves in a periodic manner The digital implementation is no different The accumulator simply scales the range of phase numbers into a multibit digital word The phase accumulator in the AD9833 is implemented with 28 bits Therefore in the AD9833 2 2 Likewise the APhase term is scaled into this range of numbers 0 lt APhase lt 2 1 With these substitutions the previous equation becomes f APhase x fuciw2 where 0 lt APhase lt 2 1 The input to the phase accumulator can be selected from either the FREQO register or the FREQI register and is controlled by the FSELECT bit NCOs inherently generate continuous phase signals thus avoiding any output discontinuity when switching between frequencies Following the NCO a phase offset can be added to perform phase modulation using the 12 bit phase registers The contents of one of these phase registers are added to the most significant bits of the NCO The AD9833 has two phase registers their resolution is 27 4096 SIN ROM To make the output from the NCO useful it must be converted from phase information into a sinusoidal value Because phase information maps directly into amplitude the SIN ROM uses the digital ph
20. ase information as an address to a lookup table and converts the phase information into amplitude Although the NCO contains a 28 bit phase accumulator the output of the NCO is truncated to 12 bits Using the full resolution of the phase accumulator is impractical and unnecessary because this would require a lookup table of 2 entries It is necessary only to have sufficient phase resolution such that the errors due to truncation are smaller than the resolution of the 10 bit DAC This requires that the SIN ROM have two bits of phase resolution more than the 10 bit DAC The SIN ROM is enabled using the mode bit D1 in the control register see Table 15 DIGITAL TO ANALOG CONVERTER DAC The AD9833 includes a high impedance current source 10 bit DAC The DAC receives the digital words from the SIN ROM and converts them into the corresponding analog voltages The DAC is configured for single ended operation An external load resistor is not required because the device has a 200 resistor on board The DAC generates an output voltage of typically 0 6 V p p REGULATOR VDD provides the power supply required for the analog section and the digital section of the AD9833 This supply have a value of 2 3 V to 5 5 V The internal digital section of the AD9833 is operated at 2 5 V An on board regulator steps down the voltage applied at VDD to 2 5 V When the applied voltage at the VDD pin of the AD9833 is less than or equal to 2 7
21. ase registers into amplitude information that results in a sinusoidal signal at the output To have a sinusoidal output from the VOUT pin set the mode D1 bit to 0 and the OPBITEN D5 bit to 0 Triangle Output The SIN ROM can be bypassed so that the truncated digital output from the NCO is sent to the DAC In this case the output is no longer sinusoidal The DAC will produce a 10 bit linear triangular function To have a triangle output from the VOUT pin set the mode D1 bit 1 Note that the SLEEP12 bit must be 0 that is the DAC is enabled when using this pin Table 15 Outputs from the VOUT Pin OPBITEN Bit Mode Bit DIV2 Bit VOUT Pin 0 0 x Sinusoid 0 1 x Triangle 1 0 0 DAC data MSB 2 1 0 1 DAC data MSB 1 1 x Reserved 1X don t care 02704 025 4m 6T Figure 25 Triangle Output Rev D Page 16 of 24 109833 APPLICATIONS INFORMATION Because of the various output options available from the part the AD9833 can be configured to suit a wide variety of applications One of the areas where the AD9833 is suitable is in modulation applications The part can be used to perform simple modulation such as FSK More complex modulation schemes such as GMSK and QPSK can also be implemented using the AD9833 Inan FSK application the two frequency registers of the AD9833 are loaded with different values One frequency represents the space frequency while the other represents the mark freq
22. ates as two 14 bit registers one containing the 14 MSBs and the other containing the 14 LSBs This means that the 14 MSBs of the frequency word can be altered independent of the 14 LSBs and vice versa Bit HLB D12 in the control register identifies which 14 bits are being altered Examples of this are shown in Table 10 and Table 11 Table 10 Writing Ox3FFF to the 14 LSBs of the FREQI Register SDATA Input Result of Input Word 0000 0000 0000 0000 Control word write 015 D14 00 B28 D13 0 HLB D12 0 that is LSBs 1011 1111 11111111 FREQ1 REG write 015 D14 10 14 LSBs Ox3FFF Table 11 Writing 0 00 to the 14 MSBs of the FREQO Register SDATA Input Result of Input Word 0001 0000 0000 0000 Control word write D15 D14 00 B28 D13 0 HLB D12 1 that is MSBs 0100 0000 1111 1111 FREQO REG write 015 D14 01 14 MSBs OxOOFF Writing to a Phase Register When writing to a phase register Bit D15 and Bit D14 are set to 11 Bit D13 identifies which phase register is being loaded Table 12 Phase Register Bits D15 D14 D13 DO 0 1 MSB 14 FREQO REG bits LSB 1 0 MSB 14 1 REG bits LSB D15 D14 D13 D12 D11 DO 1 1 0 X MSB 12 PHASEO bits LSB 1 1 1 X MSB 12 PHASE bits LSB If the user wants to change the entire contents of a frequency register two consecutive writes to the same address must be performed because the frequency regi
23. bit 0 the contents of this register are added to the output of the phase accumulator PHASE1 12bits Phase Offset Register 1 When the PSELECT bit 1 the contents of this register are added to the output of the phase accumulator 0010 0000 0000 0000 Control word write 015 D14 00 B28 013 1 HLB D12 X 0100 0000 0000 0000 FREQO register write D15 D14 01 14 LSBs 0x0000 0111 1111 1111 1111 FREQO register write D15 D14 01 14 MSBs Ox3FFF The analog output from the AD9833 is 22 FREQREG where FREQREG is the value loaded into the selected frequency register This signal is phase shifted by 21 4096 x PHASEREG where PHASEREG is the value contained in the selected phase register Consideration must be given to the relationship of the selected output frequency and the reference clock frequency to avoid unwanted output anomalies The flowchart in Figure 28 shows the routine for writing to the frequency and phase registers of the AD9833 Writing to a Frequency Register When writing to a frequency register Bit D15 and Bit D14 give the address of the frequency register Table 8 Frequency Register Bits In some applications the user does not need to alter all 28 bits of the frequency register With coarse tuning only the 14 MSBs are altered while with fine tuning only the 14 LSBs are altered By setting the B28 D13 control bit to 0 the 28 bit frequency register oper
24. control bits other than the mode bit are sampled on the internal falling edge of MCLK Table 6 describes the individual bits of the control register The different functions and the various output options of the AD9833 are described in more detail in the Frequency and Phase Registers section To inform the AD9833 that the contents of the control register will be altered D15 and D14 must be set to 0 as shown in Table 5 Table 5 Control Register Bits D15 D14 D13 DO 0 0 Control Bits AD9833 LOW POWER DIGITAL OUTPUT O VOUT DIVIDE ENABLE BY2 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 0 B28 HLB FSELECT PSELECT 0 RESET SLEEP1 SLEEP12 OPBITEN 0 DIV2 0 MODE 0 02704 024 Figure 24 Function of Control Bits Rev D Page 13 of 24 109833 Table 6 Description of Bits the Control Register Bit Name Function D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO B28 HLB FSELECT PSELECT Reserved Reset SLEEP1 SLEEP12 OPBITEN Reserved DIV2 Reserved Mode Reserved Two write operations are required to load a complete word into either of the frequency registers B28 1 allows a complete word to be loaded into a frequency register in two consecutive writes The first write contains the 14 LSBs of the frequency word and the next write contains the 14 MSBs The first two bits of each 1
25. ed to the part Options for the general oscillator include the following e AEL 301 Series oscillators AEL Crystals e SG 310SCN oscillators Epson Electronics POWER SUPPLY Power to the AD9833 evaluation board can be provided from the USB connector or externally through pin connections The power leads should be twisted to reduce ground loops Rev D Page 21 of 24 109833 EVALUATION BOARD SCHEMATICS voo 33 1 ca 10uF wF DGND 2 AVDD ae 44 1 7 DATA 100 SDATA SYNC AGND LL Q2 FSYNC s A R4 SOR QUT2 DGND Loeng 5 vouTt DGND AGND 4 AGND 2 ARS _ AGND 02 SV_EXT 2 REF 196 3 cia 10uF 02704 036 jg RESET SDP NC STANDARD CONNECTOR 3 3V_BF 2 SCL VSS SDA 24164 gt 5 lt 5 8 mm 38 5 GENERAL 00104 INPUT OUTPUT 5 2 SDA1 26 12 bus 1 is common across both connectors on SDP Pull up resistors required connected to blackfin GPIO use 12 0 first Main 12 bus Connected to blackfin Pull up resistors not required SPI 5 11 5 SS SPI SEL C SPI SEL B SP GND SPORT INT SPORT DT3 SPORT DT2 SPORT DTI SPORT SPORT DRI SPORT DR2 ISP
26. efore it can be powered down to reduce power consumption Internal Clock Disabled When the internal clock of the AD9833 is disabled the DAC output remains at its present value because the NCO is no longer accumulating New frequency phase and control words can be written to the part when the SLEEPI control bit is active The synchronizing clock is still active which means that the selected frequency and phase registers can also be changed using the control bits Setting the SLEEPI bit to 0 enables the MCLK Any changes made to the registers while SLEEP1 is active will be seen at the output after a latency period Vout Vour MIN 2T VOUT PIN The AD9833 offers a variety of outputs from the chip all of which are available from the VOUT pin The choice of outputs is the MSB of the DAC data a sinusoidal output or a triangle output The OPBITEN D5 and mode D1 bits in the control register are used to decide which output is available from the AD9833 MSB of the DAC Data The MSB of the DAC data can be output from the AD9833 By setting the OPBITEN D5 control bit to 1 the MSB of the DAC data is available at the VOUT pin This is useful as a coarse clock source This square wave can also be divided by 2 before being output The DIV2 D3 bit in the control register controls the frequency of this output from the VOUT pin Sinusoidal Output The SIN ROM is used to convert the phase information from the frequency and ph
27. es are expressed as a binary fraction of the frequency of MCLK The output frequency accuracy and phase noise are determined by this clock 6 SDATA Serial Data Input The 16 bit serial data word is applied to this input 7 SCLK Serial Clock Input Data is clocked into the AD9833 on each falling edge of SCLK 8 FSYNC Active Low Control Input FSYNC is the frame synchronization signal for the input data When FSYNC is taken low the internal logic is informed that a new word is being loaded into the device 9 AGND Analog Ground 10 VOUT Voltage Output The analog and digital output from the AD9833 is available at this pin An external load resistor is not required because the device has a 200 O resistor on board Rev D Page 6 of 24 109833 TYPICAL PERFORMANCE CHARACTERISTICS ui 22 VDD 3V Ipp SFDR dBc 0 5 10 15 20 25 5 5 7 9 1 1 15 1 19 21 23 258 MCLK FREQUENCY MHz 5 MCLK FREQUENCY MHz 5 Figure 6 Typical Current Consumption loo vs MCLK Frequency Figure 9 Wideband SFDR vs MCLK Frequency for four MCLK 10 VDD 3V 25 C 18 2 SFDR dB rm A 1 25MHz 90 0 001 0 01 0 1 1 10 100
28. fferential Nonlinearity 0 5 15 DDS SPECIFICATIONS SFDR Dynamic Specifications Signal to Noise Ratio SNR 55 60 dB 25 MHz four 4096 Total Harmonic Distortion THD 66 56 dBc 25 MHZ four 4096 Spurious Free Dynamic Range SFDR Wideband 0 to Nyquist 60 dBc 25 MHz four 50 Narrow Band 200 kHz 78 dBc 25 MHz four 50 Clock Feedthrough 60 dBc Wake Up Time 1 ms LOGIC INPUTS Input High Voltage 1 7 V 2 3 V to 2 7 V power supply 2 0 V 2 7 V to 3 6V power supply 2 8 V 4 5 V to 5 5 V power supply Input Low Voltage Vin 0 5 V 2 3 V to 2 7 V power supply 0 7 V 2 7V to 3 6V power supply 0 8 V 4 5 V to 5 5 V power supply Input Current 10 mA Input Capacitance Cin 3 pF POWER SUPPLIES 25 MHz four 4096 VDD 2 3 5 5 V 4 5 5 5 mA code dependent see Figure 7 Low Power Sleep Mode 0 5 mA DAC powered down MCLK running 1 Operating temperature range is 40 C to 105 C typical specifications are at 25 C REGULATOR 10 BIT DAC AD9833 Figure 2 Test Circuit Used to Test Specifications Rev D Page 3 of 24 02704 002 109833 TIMING CHARACTERISTICS VDD 2 3 V to 5 5 V AGND DGND 0 V unless otherwise noted Table 2 Parameter Limit at Tmn to Tmax Unit Description ti 40 ns min MCLK period t 16 ns min MCLK high duration ts 16 ns min MCLK low duration
29. fication is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev D Page 5 of 24 109833 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 02704 005 Figure 5 Pin Configuration Table 4 Pin Function Descriptions Pin No Mnemonic Description 1 COMP DAC Bias Pin This pin is used for decoupling the DAC bias voltage 2 VDD Positive Power Supply for the Analog and Digital Interface Sections The on board 2 5 V regulator is also supplied from VDD VDD can have a value from 2 3 V to 5 5 V A 0 1 UF and a 10 pF decoupling capacitor should be connected between VDD and AGND 3 CAP 2 5V The digital circuitry operates from a 2 5 V power supply This 2 5 V is generated from VDD using an on board regulator when VDD exceeds 2 7 V The regulator requires a decoupling capacitor of 100 nF typical which is connected from CAP 2 5V to DGND If VDD is less than or equal to 2 7 V CAP 2 5V should be tied directly to VDD 4 DGND Digital Ground 5 MCLK Digital Clock Input DDS output frequenci
30. he attenuation of the largest spur or harmonic in a bandwidth of 200 kHz about the fundamental frequency Total Harmonic Distortion THD THD is the ratio of the rms sum of harmonics to the rms value of the fundamental For the AD9833 THD is defined as V V V V V Vi THD 22 where Vi is the rms amplitude of the fundamental V2 V3 Va Vs and Ve are the rms amplitudes of the second through sixth harmonics Signal to Noise Ratio SNR SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency The value for SNR is expressed in decibels Clock Feedthrough There is feedthrough from the MCLK input to the analog output Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the output spectrum of the AD9833 Rev D Page 10 of 24 THEORY OF OPERATION Sine waves are typically thought of in terms of their magnitude form a t sin wt However these sine waves are nonlinear and not easy to generate except through piecewise construction On the other hand the angular information is linear in nature That is the phase angle rotates through a fixed angle for each unit of time The angular rate depends on the frequency of the signal by the traditional rate of w 2 MAGNITUDE 02704 023 Figure 23 Sine Wave AD9833 Knowing that the phase of a sine wave is linear and given
31. he evaluation board for the AD9833 requires the system demonstration platform SDP board which is sold separately AUTOMOTIVE PRODUCTS The AD9833WBRMZ REEL model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications Note that this automotive model may have specifications that differ from the commercial models therefore designers should review the Specifications section of this data sheet carefully Only the automotive grade product shown is available for use in automotive applications Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models 2003 2011 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D02704 0 4 11 D cS Rev D Page 24 of 24
32. ock rates up to 40 MHz and is compatible with DSP and microcontroller standards The device operates with a power supply from 2 3 V to 5 5 V The AD9833 has a power down function SLEEP This function allows sections of the device that are not being used to be powered down thus minimizing the current consumption of the part For example the DAC can be powered down when a clock output is being generated The AD9833 is available in a 10 lead MSOP package FUNCTIONAL BLOCK DIAGRAM AGND DGND CAP 2 5V O REGULATOR 2 5V FREQO REG FREQ1 REG PHASE ACCUMULATOR 28 BIT PHASEO REG PHASE1 REG CONTROL REGISTER SERIAL INTERFACE AND CONTROL LOGIC FSYNC 5 SDATA Rev D Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners ON BOARD REFERENCE FULL SCALE CONTROL 10 BIT DAC DIVIDE BY 2 Figure 1 AD9833 02704 001 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2003 2011 Anal
33. og Devices Inc All rights reserved 109833 TABLE OF CONTENTS Features EE 1 Applications en e eri eR CURIE 1 General 1 Functional Block Diagram seen 1 REVISION History 2 6 erepti tet te e 3 Timing Characteristics 4 Absolute Maximum Ratings eerte 5 ESD Caution eee e Ore 5 Pin Configuration and Function 6 Typical Performance Characteristics sse 7 Terminology c nderit tetti ede EA eibi los itm 10 Theory of Operation Circuit Descriptions ee tee tae ek aes Numerically Controlled Oscillator Plus Phase Modulator 12 SI ROM ettet 12 Digital to Analog Converter DAC 0002 12 Regulator 12 Functional 13 Serial Interface Et e nd 13 Powering Up the 9833 13 Latency Peri da 1 rniran 13 REVISION HISTORY 4 11 Rev C to Rev D Change t Figure 13 8 Changes to Table 9 Deleted AD9833 to ADSP 2101 ADSP 2103 Interface ei 20 Changes to Evaluation
34. sters are 28 bits wide The first write contains the 14 LSBs and the second write contains the 14 MSBs For this mode of operation the B28 D13 control bit should be set to 1 An example of a 28 bit write is shown in Table 9 Rev D Page 15 of 24 109833 RESET FUNCTION The reset function resets appropriate internal registers to 0 to provide an analog output of midscale Reset does not reset the phase frequency or control registers When the AD9833 is powered up the part should be reset To reset the AD9833 set the reset bit to 1 To take the part out of reset set the bit to 0 A signal appears at the DAC to output eight MCLK cycles after reset is set to 0 Table 13 Applying the Reset Function Reset Bit Result 0 No reset applied 1 Internal registers reset SLEEP FUNCTION Sections of the AD9833 that are not in use can be powered down to minimize power consumption This is done using the sleep function The parts of the chip that can be powered down are the internal clock and the DAC The bits required for the sleep function are outlined in Table 14 Table 14 Applying the Sleep Function SLEEP1 Bit SLEEP12 Bit Result 0 0 No power down 0 1 DAC powered down 1 0 Internal clock disabled 1 1 Both the DAC powered down and the internal clock disabled DAC Powered Down This is useful when the AD9833 is used to output the MSB of the DAC data only In this case the DAC is not required ther
35. the AD9833 Avoid running digital lines under the device as these couple noise onto the die The analog ground plane should be allowed to run under the AD9833 to avoid noise coupling The power supply lines to the AD9833 should use as large a track as possible to provide low impedance paths and reduce the effects of glitches on the power supply line Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board Avoid crossover of digital and analog signals Traces on opposite sides of the board should run at right angles to each other This reduces the effects of feedthrough through the board A microstrip technique is by far the best but it is not always possible with a double sided board In this technique the component side of the board is dedicated to ground planes and signals are placed on the other side Good decoupling is important The AD9833 should have supply bypassing of 0 1 uF ceramic capacitors in parallel with 10 uF tantalum capacitors To achieve the best performance from the decoupling capacitors they should be placed as close as possible to the device ideally right up against the device Rev D Page 17 of 24 109833 DATA WRITE SEE FIGURE 28 SELECT DATA SOURCES WAIT 7 8 MCLK INITIALIZATION CYCLES SEE FIGURE 27 BELOW DAC OUTPUT Vout Veer 18 1 SIN 2 FREQREG x t 228 PHASEREG
36. uency Using the FSELECT bit in the control register of the AD9833 the user can modulate the carrier frequency between the two values The AD9833 has two phase registers which enables the part to perform PSK With phase shift keying the carrier frequency is phase shifted the phase being altered by an amount that is related to the bit stream being input to the modulator The AD9833 is also suitable for signal generator applications Because the MSB of the DAC data is available at the VOUT pin the device can be used to generate a square wave With its low current consumption the part is suitable for applications in which it can be used as a local oscillator GROUNDING AND LAYOUT The printed circuit board PCB that houses the AD9833 should be designed so that the analog and digital sections are separated and confined to certain areas of the board This facilitates the use of ground planes that can be separated easily A minimum etch technique is generally best for ground planes because it gives the best shielding Digital and analog ground planes should be joined in one place only If the AD9833 is the only device requiring an AGND to DGND connection then the ground planes should be connected at the AGND and DGND pins of the AD9833 If the AD9833 is in a system where multiple devices require AGND to DGND connections the connection should be made at one point only a star ground point that should be established as close as possible to
37. w to program the AD9833 see the AN 1070 Application Note on the Analog Devices Inc website POWERING UP THE AD9833 The flowchart in Figure 26 shows the operating routine for the AD9833 When the AD9833 is powered up the part should be reset This resets the appropriate internal registers to 0 to provide an analog output of midscale SLEEP12 SLEEP1 RESET PHASE ACCUMULATOR 28 BIT MODE OPBITEN DIV2 OPBITEN AD9833 To avoid spurious DAC outputs during AD9833 initialization the reset bit should be set to 1 until the part is ready to begin generating an output A reset does not reset the phase frequency or control registers These registers will contain invalid data and therefore should be set to known values by the user The reset bit should then be set to 0 to begin generating an output The data appears on the DAC output seven or eight MCLK cycles after the reset bit is set to 0 LATENCY PERIOD latency period is associated with each asynchronous write operation in the AD9833 If a selected frequency or phase register is loaded with a new word there is a delay of seven or eight MCLK cycles before the analog output changes The delay can be seven or eight cycles depending on the position ofthe MCLK rising edge when the data is loaded into the destination register CONTROL REGISTER The AD9833 contains a 16 bit control register that allows the user to configure the operation of the AD9833
Download Pdf Manuals
Related Search
ANALOG DEVICES AD9833 English products handbook Rev D