ANALOG DEVICES AD9956 English products handbook Rev A
Contents
1. DELTA 1 T1 RBW 500kHz RE ATT 20dB DELTA 1 T1 RBW 10kHz RFATT 20dB REF LVL 78 134B VBW 500kHz REF LVL 56 33dB VBW 10kHz ee 100 20040080kHz SWT 20s UNIT dB 0dBm 80 96192385MHz SWT 5s UNIT dB YF fos 1 fe D 1 AP 1 AP 0 E o Ej CENTER 159 5MHz 100kHz SPAN 1MHz START 0Hz 20MHz STOP 200MHz Figure 10 AD9956 DAC Performance 400 MSPS Clock Figure 13 AD9956 DAC Performance 400 MSPS Clock 160 MHz Four 1 MHz Span 160 MHz Four 200 MHz Span Up dBc Hz ae ae ee ee ee gt 0 0 0 0 0 0 0 0 0 0000 0 0 04806 0 023 Up dBc Hz 04806 0 025 10 100 1k 10k 100k 1M FREQUENCY Hz FREQUENCY Hz Figure 11 AD9956 DDS DAC Residual Phase Noise Figure 14 AD9956 DDS DAC Residual Phase Noise 400 MHz Clock 10 MHz Output 400 MHz Clock 103 MHz Output L f dBc Hz BLEELELLL I 1 L m a E DER COOCOOOCOOCOOOCOOOOOCOOCOOCOOEE 04806 0 024 L f dBc Hz LLLLL LLL I m Jaaaddasobd td lkk dk U SOOO OOCOOCOOCOOCOOOOCOOCOOOCOOECOE 04806 0 026 10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M 10 FREQUENCY Hz FREQUENCY Hz Figure 12 AD9956 DDS DAC Residual Phase Noise Figure 15 AD9956 DDS DAC Residual Phase Noise 400 MHz Clock 40 MHz Output 400 MHz2. CFR1 lt 0 gt 0 default High speed synchronization is disabled CFR1 lt 0 gt 1 High speed synchronization is enabled Control Function Register 2 CFR2 This control register is comprised of five bytes which must be written during a write operation involving CFR2 With some minor exceptions the CFR2 primarily controls analog and tim ing functions on the AD9956 AD9956 CFR2 lt 39 gt DAC Power Down Bit This bit powers down the DAC portion of the AD9956 and puts it into the lowest power dissipation state CFR2 lt 39 gt 0 default DAC is powered on and operating CFR2 lt 39 gt 1 DAC is powered down and the output is in a high impedance state CFR2 lt 38 gt to CFR2 lt 34 gt Open Unused locations Write a Logic 0 CFR2 lt 33 gt Internal Band Gap Power Down To shut off all internal quiescent current the band gap needs to be powered down This is normally not done because it takes a long time 10 ms for the band gap to power up and settle to its final value CFR2 lt 33 gt 0 Even when all other sections are powered down the band gap is powered up and is providing a regulated voltage CFR2 lt 33 gt 1 The band gap is powered down CFR2 lt 32 gt Internal CML Driver DRV_RSET To program the CML drivers output current a resistor must be placed between the DRV_RSET pin and ground This bit enables an internal resistor to program the output current of the driver CFR2 lt 32 gt 0 def
3. CFR2 lt 22 21 gt 01 RF Divider R 2 CFR2 lt 22 21 gt 00 RF Divider R 1 Note that this is not the same as bypassing the RF divider CFR2 lt 20 gt Clock Driver Power Down This bit powers down the CML clock driver circuit CFR2 lt 20 gt 1 default CML clock driver circuit is powered down CFR2 lt 20 gt 0 CML clock driver is powered up CFR2 lt 19 18 gt Clock Driver Input Select These bits control the mux on the input for the CML clock driver CFR2 lt 19 18 gt 00 The CML clock driver is disconnected from all inputs and does not toggle CFR2 lt 19 18 gt 01 The CML clock driver is driven by the PLLOSC input pin CFR2 lt 19 18 gt 10 default The CML clock driver is driven by the output of the RF divider CFR2 lt 19 18 gt 11 The CML clock driver is driven by the input of the RF divider CFR2 lt 17 gt Slew Rate Control Bit Even without the additional surge current supplied by the rising edge slew rate control bits and the falling edge slew rate control bits the device applies a default 7 6 mA surge current to the rising edge and a 4 05 mA surge current to the falling edge This bit disables all slew rate enhancement surge current including the default values CFR2 lt 17 gt 0 default The CML driver applies default surge current to rising and falling edges CFR2 lt 17 gt 1 Driver applies no surge current during transi tions The only current is the continuous current CFR2
4. lt 23 16 gt 0x00 lt 15 8 gt Frequency Tuning Word 0 FTWO lt 15 8 gt 0x00 lt 7 0 gt Frequency Tuning Word 0 FTWO lt 7 0 gt 0x00 Profile Control Register lt 63 56 gt Open Phase Offset Word 1 POW1 lt 13 8 gt 0x00 No 1 PCR1 0x07 lt 55 48 gt Phase Offset Word 1 POW1 lt 7 0 gt 0x00 lt 47 40 gt Frequency Tuning Word 1 FTW1 lt 47 40 gt 0x00 lt 39 32 gt Frequency Tuning Word 1 FTW1 lt 39 32 gt 0x00 lt 31 24 gt Frequency Tuning Word 1 FTW1 lt 31 24 gt 0x00 lt 23 16 gt Frequency Tuning Word 1 FTW1 lt 23 16 gt 0x00 lt 15 8 gt Frequency Tuning Word 1 FTW1 lt 15 8 gt 0x00 lt 7 0 gt Frequency Tuning Word 1 FTW1 lt 7 0 gt 0x00 Profile Control Register lt 63 56 gt Open Phase Offset Word 2 POW2 lt 13 8 gt 0x00 No 2 PCR2 0x08 lt 55 48 gt Phase Offset Word 2 POW2 lt 7 0 gt 0x00 lt 47 40 gt Frequency Tuning Word 2 FTW1 lt 47 40 gt 0x00 lt 39 32 gt Frequency Tuning Word 2 FTW2 lt 39 32 gt 0x00 lt 31 24 gt Frequency Tuning Word 2 FTW2 lt 31 24 gt 0x00 lt 23 16 gt Frequency Tuning Word 2 FTW2 lt 23 16 gt 0x00 lt 15 8 gt Frequency Tuning Word 2 FTW2 lt 15 8 gt 0x00 lt 7 0 gt Frequency Tuning Word 2 FTW2 lt 7 0 gt 0x00 Profile Control Register lt 63 56 gt Open Phase Offset Word 3 POW3 lt 13 8 gt 0x00 No 3 PCR3 0x09 lt 55 48 gt Phase Offset Word 3 POW3 lt 7 0 gt 0x00 lt 47 40 gt Frequency Tuning Word 3 FTW3 lt 47 40 gt 0x00 lt 39 32 g
5. H 43 AGND H 42 PLLOSC H 41 PLLOSC 40 PLLREF H 39 PLLREF 38 AVDD H 37 AGND 47 DAC_RSET Q a gt lt E Ki I AGND 1 pity 4 36 CP_OUT AVDD 2 INDICATOR 35 CP_VDD AGND 3 34 AGND AVDD 4 33 DRV IOUT 5 32 DRV TOUT 6 AD9956 31 CP_VDD AVDD 7 TOP VIEW 30 AGND AGND 8 Not to Scale 29 REFCLK VO_RESET 9 28 REFCLK RESET 10 27 AVDD DVDD 11 26 AGND DGND 12 25 DVDD NC NO CONNECT OtTMORDADMOTAMS e e e er e er ANNAA x o KS WU eco GQ goxgobzuagnae OBR d ee TT aoga A Z m 2 DS ZS Dm SO os o E 4 2 4 2 a A Figure 3 48 Lead LFCSP Pin Configuration Note that the exposed paddle on this package is an electrical connection Pin 49 as well as a thermal enhancement For the device to function properly the paddle MUST be attached to analog ground Rev A Page 11 of 32 AD9956 Table 3 48 Lead LFCSP Pin Function Description Pin No Mnemonic Description 1 3 8 26 30 AGND Analog Ground 34 37 43 49 2 4 7 27 38 AVDD Analog Core Supply 1 8 V 44 48 5 IOUT DAC Analog Output 6 TOUT DAC Analog Complementary Output 9 I O_RESET Resets the serial port when synchronization is lost in communications but does not reset the de vice itself ACTIVE HIGH When not being used this pin should be forced low because it floats to the threshold value 10 RESET Master RESET Clears all accumulators and returns all registers to their default values ACTIVE
6. Clock 159 MHz Output Rev A Page 14 of 32 L f dBc Hz L f dBc Hz L f dBc Hz 10 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 16 RF Divider and CML Driver Residual Phase Noise 840 MHz In 105 MHz Out FREQUENCY Hz Figure 17 RF Divider and CML Driver Residual Phase Noise 1240 MHz In 155 MHz Out 10 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 18 RF Divider and CML Driver Residual Phase Noise 1680 MHz In 210 MHz Out I o 04806 0 027 04806 0 028 04806 0 029 L f dBc Hz L f dBc Hz Up dBc Hz Rev A Page 15 of 32 AD9956 10 100 1k 10k 100k 1M 10M FREQUENCY Hz E Figure 19 RF Divider and CML Driver Residual Phase Noise 2488 MHz In 622 MHz Out 10 100 1k 10k 100k 1M 10 FREQUENCY Hz 04806 0 030 04806 0 031 Figure 20 Total System Phase Noise for 105 MHz Converter Clock 10 100 1k 10k 100k 1M FREQUENCY Hz Figure 21 Total System Phase Noise for 622 MHz OC 12 Clock 04806 0 032 AD9956 TYPICAL APPLICATION CIRCUITS 25MHz PHASE FREQUENCY CRYSTAL i DETECTOR CHARGE PUMP 1 400MHz CLOCK1 AD9956 CLOCK1 04806 0
7. HIGH 11 25 DVDD Digital Core Supply 1 8 V 12 24 DGND Digital Ground 13 SDO Serial Data Output Used only when device is programmed for 3 wire serial data mode 14 SDI O Serial Data I O When the part is programmed for 3 wire serial data mode this is input only in 2 wire mode it serves as both the input and output 15 SCLK Serial Data Clock Provides the clock signal for the serial data port 16 cs Active Low Signal That Enables Shared Serial Busses When brought high the serial port ignores the serial data clocks 17 DVDD_I O Digital Interface Supply 3 3 V 18 SYNC_OUT Synchronization Clock Output 19 PLL_LOCK SYNC_IN Bidirectional Dual Function Pin Depending on device programming it is either the DDS synchro nization input allows alignment of multiple subclocks or the PLL lock detect output signal 20 LO UPDATE This input pin when set high transfers the data from the I O buffers to the internal registers on the rising edge of the internal SYNC_CLK which can be observed on SYNC_OUT 21 to 23 PSO to PS2 Profile Select Pins Specify one of eight frequency tuning word phase offset word profiles In linear sweep mode PSO determines the state of the sweep In linear sweep no dwell mode PSO is a trig ger that initiates the sweep PS1 and PS2 have no function during linear sweep mode or linear sweep no dwell mode 28 REFCLK RF Divider and DDS REFCLK Complementary Input 29 REFCLK RF Divider and DDS REFCLK Input 32 DR
8. current in response to an error signal generated in the phase frequency detector The output current is programmed through by placing a resistor CP_Rsrr from the CP_RSET pin to ground The value is dictated by the following equation CP_OUT CP_RSET This sets the charge pump reference output current Also a programmable scaler multiplies this base value by any integer from 1 to 8 programmable through the CP current scale bits in the Control Function Register 2 CFR2 lt 2 0 gt Rev A Page 18 of 32 AD9956 CML DRIVER For clocking applications an on chip current mode logic CML driver is included This CML driver generates very low jitter clock edges The outputs of the CML driver are current outputs and drives PECL levels when terminated into a 100 Q load The base output current of the driver is programmed by attaching a resistor from the DRV_RSET pin to ground nomi nally 4 02 KO for a continuous current of 7 2 mA An optional I t on chip current programming resistor is enabled by setting a bit in the control register The rising edge and falling edge slew RISING EDGE SURGE CONTINUOUS CONTINUOUS rates are independently programmable to help control over shoot and ringing through the application of surge current during rising edge transitions and falling edge transitions see Figure 27 There is a default surge current of 7 6 mA on the rising edge and 4 05 mA on the falling edge Bits
9. in the control register enable additional rising edge and falling edge surge current as well disable the default surge current see the FALLING EDGE SURGE Control Function Register Descriptions section for details The CML driver can be driven by the 04806 0 002 250ps 250ps e RE divider input Figure 27 Rising Edge and Falling Edge Surge Current Output of the CML Clock Driver as Opposed to the Steady State Continuous Current s RF divider output e PLLO C input Rev A Page 19 of 32 AD9956 MODES OF OPERATION DDS MODES OF OPERATION Single Tone Mode This is the default mode of operation for the DDS core The phase accumulator runs at a fixed frequency as per the active profiles tuning word Likewise any phase offset applied to the signal is a static value which comes from the phase offset word of the active profile The device has eight different phase fre quency profiles each with its own 48 bit frequency tuning word and 14 bit phase offset word Profiles are selected by applying their digital value on the profile select pins PS2 PS1 and PSO It is impossible to use the phase offset of one profile and the frequency tuning word of another Linear Sweep Mode This mode is entered by setting the linear sweep enable bit in the control register CFR1 lt 17 gt 1 but leaving the linear sweep no dwell bit clear CFR1 lt 16 gt 0 When the part is in linear sweep mode the frequency accumulator ramps
10. this pin should be forced low because it floats to the threshold value AD9956 MSB LSB TRANSFERS The AD9956 serial port can support both most significant bit MSB first or least significant bit LSB first data formats This functionality is controlled by the LSB first bit in Control Register 1 CFR1 lt 15 gt The default value of this bit is low MSB first When CFR1 lt 15 gt is set high the AD9956 serial port is in LSB first format The instruction byte must be written in the format indicated by CFR1 lt 15 gt If the AD9956 is in LSB first mode the instruction byte must be written from least significant bit to most significant bit However the instruction byte phase of the communications cycle still precedes the data transfer cycle For MSB first operation all data written to read from the AD9956 are in MSB first order If the LSB mode is active all data written to read from the AD9956 are in LSB first order TPRE SCLK SYMBOL DEFINITION TPRE CS SETUP TIME TsCLKW PERIOD OF SERIAL DATA CLOCK WRITE Tpsu SERIAL DATA SETUP TIME 2 Toun SERIAL DATA HOLD TIME S ae ee SYMBOL MAX DEFINITION Tov 40ns DATA VALID TIME TscLKR 400ns PERIOD OF SERIAL DATA CLOCK READ Figure 34 Timing Diagram for Data Read to AD9956 04806 0 035 Rev A Page 23 of 32 AD9956 REGISTER MAP AND DESCRIPTION Table 5 Regist
11. to the device is in 2 wire mode The SDI O pin is bidirectional CFR1 lt 14 gt 1 Serial data transfer to the device is in 3 wire mode The SDI O pin is input only CFR1 lt 13 8 gt Open Unused locations Write a Logic 0 CFR1 lt 7 gt Digital Power Down This bit powers down the digital circuitry not directly related to the I O port The I O port functionality is not suspended re gardless of the state of this bit CFR1 lt 7 gt 0 default Digital logic operating as normal CFR1 lt 7 gt 1 All digital logic not directly related to the I O port is powered down Internal digital clocks are suspended CFR1 lt 6 gt Phase Frequency Detector Input Power Down This bit controls the input buffers on the phase frequency detec tor It provides a way to gate external signals from the phase frequency detector itself CFR1 lt 6 gt 0 default Phase frequency detector input buffers are functioning normally CFR1 lt 6 gt 1 Phase frequency detector input buffers are pow ered down isolating the phase frequency detector from the outside world CFR1 lt 5 gt PLLREF Crystal Enable The AD9956 phase frequency detector has an on chip oscillator circuit When enabled the reference input to the phase fre quency detector PLLREF PLLREF can be driven by a crystal CFR1 lt 5 gt 0 default Phase frequency detector reference input operates as a standard analog input CFR1 lt 5 gt 1 Reference input oscillator circu
12. 00 lt 31 24 gt Frequency Tuning Word 5 FTW5 lt 31 24 gt 0x00 lt 23 16 gt Frequency Tuning Word 5 FTW5 lt 23 16 gt 0x00 lt 15 8 gt Frequency Tuning Word 5 FTW5 lt 15 8 gt 0x00 lt 7 0 gt Frequency Tuning Word 5 FTW5 lt 7 0 gt 0x00 Profile Control lt 63 56 gt Open Phase Offset Word 6 POW6 lt 13 8 gt 0x00 Register lt 55 48 gt Phase Offset Word 6 POW6 lt 7 0 gt 0x00 No 6 PCR6 0x0C lt 47 40 gt Frequency Tuning Word 6 FTW6 lt 47 40 gt 0x00 lt 39 32 gt Frequency Tuning Word 6 FTW6 lt 39 32 gt 0x00 lt 31 24 gt Frequency Tuning Word 6 FTW6 lt 31 24 gt 0x00 lt 23 16 gt Frequency Tuning Word 6 FTW6 lt 23 16 gt 0x00 lt 15 8 gt Frequency Tuning Word 6 FTW6 lt 15 8 gt 0x00 lt 7 0 gt Frequency Tuning Word 6 FTW6 lt 7 0 gt 0x00 Profile Control lt 63 56 gt Open Phase Offset Word 7 POW7 lt 13 8 gt 0x00 Register lt 55 48 gt Phase Offset Word 7 POW7 lt 7 0 gt 0x00 No 7 PCR7 0x0D Are Frequency Tuning Word 7 FTW7 lt 47 40 gt 0x00 lt 39 32 gt Frequency Tuning Word 7 FTW7 lt 39 32 gt 0x00 lt 31 24 gt Frequency Tuning Word 7 FTW7 lt 31 24 gt 0x00 lt 23 16 gt Frequency Tuning Word 7 FTW7 lt 23 16 gt 0x00 lt 15 8 gt Frequency Tuning Word 7 FTW7 lt 15 8 gt 0x00 lt 7 0 gt Frequency Tuning Word 7 FTW7 lt 7 0 gt 0x00 1 In all cases open bits must be written to 0 Rev A Page 26 of 32 CONTROL FUNCTION REGISTER DESCRIPTIONS Control Fu
13. 011 1 8 LEVEL FSK FC 100MHz CML DRIVER 25MHz PLLREF CRYSTAL CP_OUT 04806 0 012 Figure 24 LO and Baseband Modulation Generation Rev A Page 16 of 32 04806 0 010 PHASE FREQUENCY DETECTOR EXTERNAL I REFERENCE AD9956 AD9956 622MHz CML i DRIVER CLOCK1 CLOCK2 04806 0 013 Figure 25 Optical Networking Clock FREQUENCY DETECTOR 04806 0 014 Figure 26 Direct Upconversion APPLICATION CIRCUIT EXPLANATIONS Dual Clock Configuration In this loop M 1 N 16 and R 4 The DDS tuning word is also equal to so that the frequency of CLOCK I equals the frequency of CLOCK 1 Phase adjustments in the DDS provide a 14 bit programmable rising edge skew capability of CLOCK 1 with respect to CLOCK 1 see Figure 22 Fractional Divider Loop This loop offers the precise frequency division 48 bit of the DDS in the feedback path as well as the frequency sweeping capability of the DDS Programming the DDS to sweep from 24 MHz to 25 MHz sweeps the output of the VCO from 2 7 GHz to 2 6 GHz The reference in this case is a simple crystal see Figure 23 LO and Baseband Modulation Generation Using the AD9956 s PLL section to generate an LO and the DDS portion to generate a modulated baseband this circuit uses an external mixer to perform some simple modulation at RF frequencies see Figure 24 Optical Networking Clock This is the AD9956 configured as an o
14. 30 40 1AP 50 60 70 80 90 04806 0 016 100 CENTER 40 1MHz 100kHz SPAN 1MHz Figure 5 AD9956 DAC Performance 400 MSPS Clock 40 MHz Four 1 MHz Span DELTA 1 T1 RBW 500Hz RPF ATT 20dB REF LVL 57 74dB VBW 500Hz 0dBm 400 80160321kHz SWT 20s UNIT dB 1AP 04806 0 017 CENTER 100 1MHz 100kHz SPAN 1MHz Figure 6 AD9956 DAC Performance 400 MSPS Clock 100 MHz Four 1 MHz Span 100 0 10 20 30 100 0 10 20 30 40 50 100 Rev A Page 13 of 32 AD9956 DELTA 1 T1 RBW 10kHz RFATT 20dB REF LVL 67 45dB VBW 10kHz 0dBm 74 50901804MHz SWT 4 3s UNIT dB START 0Hz 16 9MHz STOP 169MHz Figure 7 AD9956 DAC Performance 400 MSPS Clock 10 MHz Four 200 MHz Span DELTA 1 T1 RBW 10kHz RPF ATT 20dB REF LVL 62 65dB VBW 10kHz 0dBm 100 20040080MHz SWT 5s UNIT START 0Hz 20MHz STOP 200MHz Figure 8 AD9956 DAC Performance 400 MSPS Clock 40 MHz Four 200 MHz Span DELTA 1 T1 RBW 10kHz RFATT 20dB REF LVL 48 78dB VBW 10kHz 0dBm 400 80160321kHz SWT 5s UNIT START 0Hz 20MHz STOP 200MHz Figure 9 AD9956 DAC Performance 400 MSPS Clock 100 MHz Four 200 MHz Span 1AP 04806 0 018 1AP 04806 0 019 1AP 04806 0 020 AD9956
15. 4 dBc 40 MHz Analog Out 62 dBc 80 MHz Analog Out 60 dBc 120 MHz Analog Out 55 dBc 160 MHz Analog Out 55 dBc Narrowband SFDR 10 MHz Analog Out 1 MHz 89 dBc 10 MHz Analog Out 250 kHz 91 dBc 10 MHz Analog Out 50 kHz 93 dBc 40 MHz Analog Out 1 MHz 87 dBc 40 MHz Analog Out 250 kHz 89 dBc 40 MHz Analog Out 50 kHz 91 dBc 80 MHz Analog Out 1 MHz 85 dBc 80 MHz Analog Out 250 kHz 87 dBc 80 MHz Analog Out 50 kHz 89 dBc 120 MHz Analog Out 1 MHz 83 dBc 120 MHz Analog Out 250 kHz 85 dBc 120 MHz Analog Out 50 kHz 87 dBc Rev A Page 5 of 32 AD9956 Parameter Min Typ Max Unit Test Conditions Comments 160 MHz Analog Out 1 MHz 81 dBc 160 MHz Analog Out 250 kHz 83 dBc 160 MHz Analog Out 50 kHz 85 dBc DAC Residual Phase Noise 19 7 MHz Four 10 Hz Offset 125 dBc Hz 100 Hz Offset 135 dBc Hz 1 kHz Offset 143 dBc Hz 10 kHz Offset 152 dBc Hz 100 kHz Offset 158 dBc Hz gt 1 MHz Offset 163 dBc Hz 51 84 MHz Four 10 Hz Offset 119 dBc Hz 100 Hz Offset 125 dBc Hz 1 kHz Offset 132 dBc Hz 10 kHz Offset 142 dBc Hz 100 kHz Offset 150 dBc Hz gt 1 MHz Offset 155 dBc Hz 105 3 MHz Analog Out 10 Hz Offset 105 dBc Hz 100 Hz Offset 115 dBc Hz 1 kHz Offset 122 dBc Hz 10 kHz Offset 131 dBc Hz 100 kHz Offset 139 dBc Hz gt 1 MHz Offset 142 dBc Hz 155 52 MHz Analog Out 10 Hz Offset 105 d
16. ANALOG DEVICES 2 7 GHz DDS Based AgileRF Synthesizer AD9956 FEATURES 3 3 V supply for I O and charge pump Software controlled power down 400 MSPS internal DDS clock speed 48 lead LFCSP package 48 bit frequency tuning word 14 bit programmable phase offset Integrated 14 bit DAC Phase modulation capability Excellent dynamic performance Multichip synchronization Phase noise lt 135 dBc Hz 1 KHz offset Dual mode PLL lock detect Automatic linear frequency sweeping capability in DDS Programmable charge pump current up to 4 mA 80 dB SFDR 160 MHz 100 KHz offset lour 655 MHz CML mode PECL compliant driver 25 Mb s write speed serial I O control 200 MHz phase frequency detector inputs APPLICATIONS 655 MHz programmable input dividers for the phase Agile LO frequency synthesis frequency detector M N M N 1 16 bypassable FM chirp source for radar and scanning systems Programmable RF divider R R 1 2 4 8 bypassable Automotive radars 8 phase frequency profiles Test and measurement equipment 1 8 V supply for device operation Acousto optic device drivers FUNCTIONAL BLOCK DIAGRAM DAC_RSET O DELTA FREQUENCY TUNING WORD Q IOUT Q IOUT DELTA FREQUENCY RAMP RATE PLL_LOCK SYNC_IN C Q I O_RESET UO UPDATE 7 LOCK CHARGE SYNC_OUT PETREN SCALER REFCLK REFCLK cP_OUT 04806 0 001 DRV DRV DRV_RSET PS lt 2 0 gt RESET UO PORT PLLREF PLLOSC CP_RSET PLLREF PLLOSC Figure 1 Rev A Information
17. Bc Hz 100 Hz Offset 110 dBc Hz 1 kHz Offset 119 dBc Hz 10 kHz Offset 127 dBc Hz 100 kHz Offset 135 dBc Hz gt 1 MHz Offset 142 dBc Hz CRYSTAL OSCILLATOR ON PLLREF INPUT Operating Range 20 25 30 MHz Residual Phase Noise 25 MHz 10 Hz Offset 95 dBc Hz 100 Hz Offset 120 dBc Hz 1 kHz Offset 137 dBc Hz 10 kHz Offset 156 dBc Hz 100 kHz Offset 164 dBc Hz gt 1 MHz Offset 170 dBc Hz DIGITAL TIMING SPECIFICATIONS CS to SCLK Setup Time TPRE 6 ns Period of SCLK Write Speed TSCLKW 40 ns Period of SCLK Read Speed TSCLKR 400 ns Serial Data Setup Time TDSU 6 5 ns Serial Data Hold Time TDHLD 0 ns TDV Data Valid Time TDV 40 ns I O Update to SYNC_CLK Setup Time TUD 7 ns PS lt 2 0 gt to SYNC_CLK Setup Time TPS 7 ns Rev A Page 6 of 32 AD9956 Parameter Min Typ Max Unit Test Conditions Comments Latencies Pipeline Delays I O Update to DAC Frequency Change 33 SYSCLK Cycles I O Update to DAC Phase Change 33 SYSCLK Cycles PS lt 2 0 gt to DAC Frequency Change 29 SYSCLK Cycles PS lt 2 0 gt to DAC Phase Change 29 SYSCLK Cycles I O Update to CP OUT Scaler Change 4 SYSCLK Cycles I O Update to Frequency Accumulator 4 SYSCLK Cycles Step Size Change I O Update to Frequency Accumulator 4 SYSCLK Cycles Ramp Rate Change RF DIVIDER CML DRIVER EQUIVALENT INTRINSIC TIME JITTER Fin 414 72 MHz Four 51 84 MHz BW 12 kHz gt 400 kHz 136 fs rms OCT RF Divider R 8 Fin 1244 16 MH
18. DRIVER DRV Differential Output Voltage Swing 720 mV 50 load to supply both lines Maximum Toggle Rate 655 MHz Common Mode Output Voltage 1 75 V Output Duty Cycle 42 50 58 Output Current Continuous 7 2 mA Rising Edge Surge 20 9 mA Falling Edge Surge 13 5 mA Output Rise Time 250 ps 100 Q terminated 5 pF load Rev A Page 4 of 32 AD9956 Parameter Min Typ Max Unit Test Conditions Comments LOGIC INPUTS SDI O I O_RESET RESET UO UPDATE PSO to PS2 SYNC_IN Vin Input High Voltage 2 0 V Vi Input Low Voltage 0 8 V linn line Input Current 1 5 HA Cn Maximum Input Capacitance 3 pF LOGIC OUTPUTS SDO SYNC_OUT PLL_LOCK Vou Output High Voltage 2 7 V Von Output Low Voltage 0 4 V lon 100 HA lot 100 HA POWER CONSUMPTION Total Power Consumed All Functions On 400 mW IAVDD 85 mA IDVDD 45 mA IDVDD_I O 20 mA ICP_VDD 15 mA Power Down Mode 80 mW WAKE UP TIME from Power Down Mode Digital Power Down CFR1 lt 7 gt 12 ns DAC Power Down CFR2 lt 39 gt 7 us RF Divider Power Down CFR2 lt 23 gt 400 ns Clock Driver Power Down CFR2 lt 20 gt 6 us Charge Pump Full Power Down CFR2 lt 4 gt 10 us Charge Pump Quick Power Down CFR2 lt 3 gt 150 ns DAC OUTPUT CHARACTERISTICS Resolution 14 Bits Full Scale Output Current 10 15 mA Gain Error 10 10 FS Output Offset 0 6 HA Output Capacitance 5 pF Voltage Compliance Range AVDD 0 50 AVDD 0 50 V Wideband SFDR DC to Nyquist 10 MHz Analog Out 6
19. K Figure 29 through Figure 32 are useful in understand ing the general operation of the AD9956 serial port DATA TRANSFER CYCLE 04806 0 004 Figure 29 Serial Port Write Timing Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE e BRR ho M 2 I wio r es GG GG SES Li spo Be 5 5 GP B Po GD Poo DON T CARE 0 005 04806 Figure 30 3 Wire Serial Port Read Timing Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE es i AV AVAVAVAVAVAV MEU AUAVAVAVAUAUAV IE I sovo L A s Js Js s z no fi Pr XX Ps OX Bs Dz BJ o 04806 0 006 Figure 31 Serial Port Write Timing Clock Stall High INSTRUCTION CYCLE DATA TRANSFER CYCLE es i 1 l soo L X Ae X s Js s Je KX to Po7 PosfPosfPoa Pos PozfPo Pos I 0 007 04806 Figure 32 2 Wire Serial Port Read Timing Clock Stall High Rev A Page 22 of 32 INSTRUCTION BYTE The instruction byte contains the following information Table 4 D7 D6 D5 D4 D3 D2 D1 DO R Wb X X A4 A3 A2 A1 AO R Wb Bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte write Logic 1 indicates a read operation Logic 0 indicates a write operation X X Bits 6 and 5 of the instruction byte are Don t Care A4 to A0 Bits 4 to 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications c
20. PS device function requires that for any RF input signal gt 400 MHz the RF divider be engaged The RF divider can be programmed to take values of 1 2 4 or 8 The ratio for the divider is pro grammed in the control register The output of the divider can be routed to the input of the on chip CML driver For lower frequency input signals it is possible to use the divider to divide the input signal to the CML driver and use the undivided input of the divider as the SYSCLK input to the DDS or vice versa In all cases the clock to the DDS should not exceed 400 MSPS The on chip phase frequency detector has two differential inputs PLLREF the reference input and PLLOSC the feed back or oscillator input These differential inputs can be driven by single ended signals however when doing so tie the unused input through a 100 pF capacitor to the analog supply AVDD The maximum speed of the phase frequency detector inputs is 200 MHz Each of the inputs has a buffer and a divider M on PLLREF and N on PLLOSC that operates at up to 655 MHz If the signal exceeds 200 MHz however the divider must be used The dividers are programmed through the control registers and take any integer value between 1 and 16 The PLLREF input also has the option of engaging an in line oscillator circuit Engaging this circuit means that the PLLREF input can be driven with a crystal in the of 20 MHz lt PLLREF lt 30 MHz range The charge pump outputs a
21. RATINGS Table 2 Parameter Rating Analog Supply Voltage AVDD 2V Digital Supply Voltage DVDD 2V Digital I O Supply Voltage 3 6V DVDD_1I 0 Charge Pump Supply Voltage 3 6V CPVDD Maximum Digital Input Voltage 0 5 V to DVDD_I O 0 5 V Storage Temperature 65 C to 150 C Operating Temperature Range 40 C to 125 C Lead Temperature Range 300 C Soldering 10 sec Junction Temperature 150 C Thermal Resistance ya 26 C W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy elec trostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality Rev A Page 10 of 32 EP ESD SENSITIVE DEVICE AD9956 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 46 DRV_RSET 45 CP RSET H 44 AVDD
22. V CML Driver Complementary Output 33 DRV CML Driver Output 31 35 CP VDD Charge Pump Supply Pin 3 3 V To minimize noise on the charge pump isolate this supply from DVDD_ O 36 CP_OUT Charge Pump Output 39 PLLREF Phase Frequency Detector Reference Input 40 PLLREF Phase Frequency Detector Reference Complementary Input 41 PLLOSC Phase Frequency Detector Oscillator Feedback Complementary Input 42 PLLOSC Phase Frequency Detector Oscillator Feedback Input 45 CP_RSET Charge Pump Current Set Program Charge Pump Current with a Resistor to AGND 46 DRV_RSET CML Driver Output Current Set Program CML Output Current with a Resistor to AGND 47 DAC_RSET DAC Output Current Set Program DAC Output Current with a Resistor to AGND Note that the exposed paddle on this package is an electrical connection Pin 49 as well as a thermal enhancement In order for the device to function properly the paddle MUST be attached to analog ground Rev A Page 12 of 32 TYPICAL PERFORMANCE CHARACTERISTICS DELTA 1 T1 RBW 500Hz RPF ATT 20dB REF LVL 84 82dB VBW 500Hz 0dBm 404 80961924kHz SWT 20s UNIT dB 0 90 ta 04806 0 015 100 CENTER 10 1MHz 100kHz SPAN 1MHz Figure 4 AD9956 DAC Performance 400 MSPS Clock 10 MHz Four 1 MHz Span DELTA 1 T1 78 67dB 100 20040080kHz RBW 500Hz RFATT 20dB VBW 500Hz SWT 20s UNIT dB 1 D REF LVL 0dBm 0 10 20
23. art 2004 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www ana l 0 g com nosan LA DEVICES Rev A Page 32 of 32
24. asurement Condi tions section 1 The input impedance of the REFCLK input is 1500 Q However in order to provide matching on the clock line an external 50 Q load is used Driving the PLLREF input buffer the crystal oscillator section of this input stage performs up to only 30 MHz gt The charge pump output compliance range is functionally 0 2 V to CP VDD 0 2 V The value listed here is the compliance range for 5 matching 4 Measured as peak to peak from DRV to DRV 5 For a 4 02 kO resistor from DRV_RSET to GND 5 Assumes a 1 mA load 7 O_UPDATE PS lt 2 0 gt are detected by the AD9956 synchronous to the rising edge of SYNC_CLK Each latency measurement is from the first SYNC_CLK rising edge after the I O_UPDATE PS lt 2 0 gt state change Rev A Page 8 of 32 LOOP MEASUREMENT CONDITIONS 622 MHz OC 12 Clock VCO Sirenza 190 640T Reference Wenzel 500 10116 30 3 MHz Loop Filter 10 kHz BW 60 Phase Margin C1 170 nk R1 14 4 Q C2 5 11 uF R2 89 3 O C3 Omitted CP_OUT 4 mA Scaler x8 R 2 M 1 N lL AD9956 105 MHz Converter Clock VCO Sirenza 190 845T Reference Wenzel 500 10116 30 3 MHz Loop Filter 10 kHz BW 45 Phase Margin C1 117 n RI 28 Q C2 1 6 uF R2 57 1 QO C3 53 4 nF CP_OUT 4 mA Scaler x8 R 8 M 1 N 1 INPUT OUTPUT CH at CH N Q 04806 0 033 Figure 2 Generic Loop Filter Rev A Page 9 of 32 AD9956 ABSOLUTE MAXIMUM
25. ault The DRV_RSET pin is enabled and an external resistor must be attached to the CP_RSET pin to program the output current CFR2 lt 32 gt 1 The CML current is programmed by the inter nal resistor and ignores the resistor on the DRV_REST pin CFR2 lt 31 29 gt Clock Driver Rising Edge These bits control the slew rate of the CML clock driver output s rising edge When these bits are on additional current is sent to the output driver to increase the rising edge slew rate capability the contributions of each bit are cumulative Table 6 describes how the bits increase the current Note that the additional cur rent is on only during the rising edge of the waveform for ap proximately 250 ps but not on during the entire transition Table 6 CML Clock Driver Rising Edge Slew Rate Control Bits and Associated Surge Current CFR2 lt 31 gt 1 7 6 mA CFR2 lt 30 gt 1 3 8 mA CFR2 lt 29 gt 1 1 9 mA Rev A Page 29 of 32 AD9956 CFR2 lt 28 26 gt Clock Driver Falling Edge Control These bits control the slew rate of the CML clock driver outputs falling edge When these bits are on additional current is sent to the output driver to increase the rising edge slew rate capability Table 7 describes how the bits increase the current the contri butions of each bit are cumulative Note that the additional cur rent is on only during the rising edge of the waveform for ap proximately 250 ps but not on during the entire tra
26. clocks among different devices in the system It is important to note that the synchronization functions included on the AD9956 control only the timing relationships among different digital clocks They do not compensate for the analog timing skew on the system clock due to mismatched phase relationships on the input clock REFCLK Figure 28 illustrates this concept Rev A Page 20 of 32 Automatic Synchronization In automatic synchronization mode the device is placed into slave mode and automatically aligns the internal SYNC_CLK to a master SYNC_CLK signal supplied on the SYNC_IN input When this bit is enabled the PLL_LOCK is not available as an output however an out of lock condition can be detected by reading Control Function Register 1 and checking the status of the PLL_LOCK_ERROR bit CFR1 lt 24 gt The automatic synchronization function is enabled by setting the Control Function Register 1 automatic synchronization bit CFR1 lt 3 gt To employ this function at higher clock rates SYNC_CLK gt 62 5 MHz and SYSCLK gt 250 MHz the high speed sync enable bit CFR1 lt 0 gt should be set as well Manual Synchronization Hardware Controlled In this mode the user controls the timing relationship of the SYNC_CLK with respect to SYSCLK When hardware manual synchronization is enabled the PLL_LOCK SYNC_IN pin becomes a digital input For each and every rising edge detected on the SYNC_IN input the device advances the SYNC_IN
27. d lt 23 16 gt 0x00 Frequency lt 15 8 gt Rising Delta Frequency Tuning Word lt 15 8 gt 0x00 NSE lt 7 0 gt Rising Delta Frequency Tuning Word lt 7 0 gt 0x00 RDFTW 0x02 Falling Delta lt 23 16 gt Falling Delta Frequency Tuning Word lt 23 16 gt 0x00 Frequency lt 15 8 gt Falling Delta Frequency Tuning Word lt 15 8 gt 0x00 Naa lt 7 0 gt Falling Delta Frequency Tuning Word lt 7 0 gt 0x00 FDFTW 0x03 Rising lt 15 8 gt Rising Sweep Ramp Rate lt 15 8 gt 0x00 Sweep lt 7 0 gt Rising Sweep Ramp Rate lt 7 0 gt 0x00 Ramp Rate RSRR 0x04 Falling lt 15 8 gt Rising Sweep Ramp Rate lt 15 8 gt 0x00 Sweep lt 7 0 gt Rising Sweep Ramp Rate lt 7 0 gt 0x00 Ramp Rate FSRR 0x05 1 In all cases open bits must be written to 0 Rev A Page 24 of 32 AD9956 Register Name BitO Default Value Serial Address Bit Range MSB Bit 7 Bit6 BitS Bit4 Bit3 Bit2 Bit1 LSB Profile Profile Control Register lt 63 56 gt Open Phase Offset Word 0 POWO lt 13 8 gt 0x00 No 0 PCRO 0x06 lt 55 48 gt Phase Offset Word 0 POWO lt 7 0 gt 0x00 lt 47 40 gt Frequency Tuning Word 0 FTWO lt 47 40 gt 0x00 lt 39 32 gt Frequency Tuning Word 0 FTWO lt 39 32 gt 0x00 lt 31 24 gt Frequency Tuning Word 0 FTWO lt 31 24 gt 0x00 lt 23 16 gt Frequency Tuning Word 0 FTWO
28. er Name Default Serial Bit Bit 0 Value Address Range MSB Bit7 Bit6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Profile Control lt 31 24 gt Open Open Open Open Open Open Open PLLLock 0x00 Function Error Register 1 lt 23 16 gt LOADSRR Auto Clr Auto Enable Clear Clear Linear Linear 0x00 CFR1 I O_UPDATE Frequency Clr Sine Frequency Phase Sweep Sweep 0x00 Accum Phase Output Accum Accum Enable No Dwell Accum lt 15 8 gt LSB First SDI O Open Open Open Open Open Open 0x00 Input Only lt 7 0 gt Digital PFDlnput PLLREF SYNC_CLK AutoSync Software Hardware High 0x00 Power Power Crystal Disable Multiple Manual Manual Speed Down Down Enable AD9956s Sync Sync Sync Enable Control lt 39 32 gt DAC Open Open Open Open Open Internal Internal 0x00 Function Power Band Gap CML Register 2 Down Power Driver CFR2 Down DRV_RSET 0x01 lt 31 24 gt Clock Driver Rising Edge lt 31 29 gt Clock Driver Falling Edge Control PLLLock PLLLock 0x00 lt 28 26 gt Detect Detect Enable Mode lt 23 16 gt RF Divider RF Divider Ratio Clock Clock Driver Input Slew Rate RF Div 0x78 Power lt 22 21 gt Driver Select lt 19 18 gt Control REFCLK Down Power Mux Bit Down lt 15 8 gt Divider N Control lt 15 12 gt Divider M Control lt 11 8 gt 0x00 lt 7 0 gt Open Open CP CP CP CP Current Scale lt 2 0 gt 0x07 Polarity Full PD Quick PD Rising Delta lt 23 16 gt Rising Delta Frequency Tuning Wor
29. erates frequencies in single tone mode CFR1 lt 17 gt 1 The DDS uses the frequency accumulator to sweep the frequency tuning word being sent to the phase accumulator according to the values set in the delta frequency tuning word and delta frequency ramp rate registers For a detailed explanation of this mode see the linear sweep mode of operation section CFR1 lt 16 gt Linear Sweep No Dwell This bit dictates the behavior of the DDS core upon completion of a linear sweep CFR1 lt 16 gt 0 default Upon reaching the upper value of the sweep FTW1 the DDS holds at the frequency value stored in FTWI1 CFR1 lt 16 gt 1 Upon reaching the upper value of the sweep FTW1 the DDS returns to the initial value in the sweep FT WO and continues to output that frequency until a new sweep is initiated by bringing PSO low and then high CFR1 lt 15 gt LSB First Serial Data Mode The serial data transfer to the device can be either MSB first or LSB first This bit controls that operation CFR1 lt 15 gt 0 default Serial data transfer to the device is in MSB first mode CFR1 lt 15 gt 1 Serial data transfer to the device is in LSB first mode CFR1 lt 14 gt SDI O Input Only 3 Wire Serial Data Mode The serial port on the AD9956 can act in 2 wire mode SCLK and SDI O or 3 wire mode SCLK SDI O and SDO This bit toggles the serial port between these two modes CFR1 lt 14 gt 0 default Serial data transfer
30. et block normalized to 27 Finally the amplitude words are piped to a 14 bit DAC Because the DAC is a sampled data system the output is a reconstructed sine wave that needs to be filtered to take high frequency images out of the spectrum The DAC is a current steering DAC that is AVDD referenced To get a measurable voltage output the DAC outputs must terminate through a load resistor to AVDD typically 50 Q At positive full scale IOUT sinks no current and the voltage drop across the load resistor is zero However the IOUT output sinks the DAC s programmed full scale output current causing the maximum output voltage to drop across the load resistor At negative full scale the situation is reversed and IOUT sinks the full scale current and generates the maximum drop across the load resistor At the same time IOUT sinks no current and generates no voltage drop At midscale the outputs sink equal amounts of current generating equal voltage drops PLL CIRCUITRY The AD9956 includes an RF divider divide by R a phase frequency detector and a programmable output current charge pump Incorporating these blocks together users can generate many useful circuits for frequency synthesis A few simple examples are shown in the Typical Application Circuits The RF divider accepts differential or single ended signals up to 2 7 GHz The RF divider also supplies the SYSCLK input to the DDS Because the DDS operates up to only 400 MS
31. furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A or otherwise under any patent or patent rights of Analog Devices Trademarks and Tel 781 329 4700 www analog com registered trademarks are the property of their respective owners Fax 781 326 8703 2004 Analog Devices Inc All rights reserved AD9956 TABLE OF CONTENTS Product EEN ee Loop Measurement Conditions EE Absolute Maximum Range ICAL Pin Configuration and Function Descriptions Typical Performance Characteristics enee Typical Application Circuits eee Application Circuit Explanations en General DESCHIDUG eege die tee IR L ycia iwa adw e nna Raka lila R DE ee E REVISION HISTORY 9 04 Data Sheet Changed from Rev 0 to Rev A Changes to the Pin Confteuration En Changes to the Pin Function Descriptions en Changes to Table Bt y O A E AE Changes to CFR2 lt 15 12 gt PLLREF Divider Contr l Bits EN Set Changes to CFR2 lt 11 8 gt PLLREF Divider Eo trol Bits EM eege Changes to Ordering Guide ee 7 04 Revision Initial Version ENEE 19 Modes of Operation ENEE 20 DDS Modes of Operation EEN 20 Synchronization Modes for Multi
32. harge pump is on and running but the output buffer is powered down CFR2 lt 2 0 gt Charge Pump Current Scale A base output current from the charge pump is determined by a resistor connected from the CP_RSET pin to ground see the PLL Circuitry section However it is possible to multiply the charge pump output current by a value from 1 8 by programming these bits The charge pump output current is scaled by CFR2 lt 2 0 gt 1 CFR2 lt 2 0 gt 000 default Scale factor 1 to CFR2 lt 2 0 gt 111 8 CFR2 lt 2 0 gt Scale Factor 000 001 010 011 100 101 110 111 ANA U RW N A Rev A Page 31 of 32 AD9956 OUTLINE DIMENSIONS 1 INDICATOR EXPOSED TOP VIEW PAD BOTTOM VIEW 0 80 MAX mej a gem 0 80 0 05 MAX TL 0 09 NOM e 0 50 BSC U COPLANARITY 0 20 REF 0 08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO 220 VKKD 2 Figure 35 48 Lead Lead Frame Chip Scale Package LFCSP 7mm x 7mm Body CP 48 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9956YCPZ 40 C to 125 C 48 Lead Lead Frame Chip Scale Package LFCSP CP 48 AD9956YCPZ REEL 40 C to 125 C 48 Lead Lead Frame Chip Scale Package LFCSP Tape and Reel CP 48 AD9956 PCB Evaluation Board with No VCO and Charge Pump Filter AD9956 VCO PCB Evaluation Board with 2 4 GHz VCO and Charge Pump Filter 1 Z Pb free p
33. inear sweep no dwell mode the frequency accumulator ramps the output frequency of the device from a programmed lower frequency to a pro grammed upper frequency Upon reaching the upper frequency the accumulator returns to the lower frequency directly without ramping back down Unlike the default mode of the linear sweep this mode uses only the rising delta frequency tuning word RDFTW and the rising sweep ramp rate RSRR The operation is still controlled by the PSO pin In this mode how ever it acts as a trigger for the sweep not a direction bit Once a PSO low to high transition is detected the part completes the entire sweep regardless of whether or not the PSO pin is changed back to low during the sweep After the sweep is com pleted another sweep may be initiated by applying another rising edge on the PSO pin This means that the PSO pin needs to be brought low prior to the next sweep SYNCHRONIZATION MODES FOR MULTIPLE DEVICES In a DDS system the SY NC CLK 15 derived internally off the master system clock SYSCLK with a 4 divider Because the divider does not power up to a known state it is possible for multiple devices in a system to have staggered clock phase relationships This is because each device could potentially gen erate the SYNC_CLK rising edge from any one of four rising edges of SYSCLK This ambiguity can be resolved by employing digital synchronization logic to control the phase relationships of the derived
34. it is enabled allowing the use of a crystal for the reference of the phase frequency detector CFR1 lt 4 gt SYNC_CLK Disable If synchronization of multiple devices is not required the spec tral energy resulting from this signal can be reduced by gating the output buffer off This function gates the internal clock ref erence SYNC_CLK SYSCLK 4 off of the SYNC_OUT pin CFR1 lt 4 gt 0 default SYNC_CLK signal is present on the SYNC_OUT pin and is ready to be ported to other devices CFR1 lt 4 gt 1 SYNC_CLK signal is gated off putting the SYNC_OUT pin into a high impedance state CFR1 lt 3 gt Automatic Synchronization One of the synchronization modes of the AD9956 forces the DDS core to derive the internal reference from an external ref erence supplied on the SYNC_IN pin For details on synchroni zation modes for the DDS core see the Synchronization Modes for Multiple Devices section Rev A Page 28 of 32 CFR1 lt 3 gt 0 default The automatic synchronization function of the DDS core is disabled CFR1 lt 3 gt 1 The automatic synchronization function is on The device is slaved to an external reference and adjusts the internal SYNC_CLK to match the external reference which is supplied on the SYNC_IN input CFR1 lt 2 gt Software Manual Synchronization Rather than relying on the part to automatically synchronize the internal clocks the user can program the part to advance the internal SYNC_CLK one sys
35. ity This bit sets the polarity of the charge pump in response to a ground referenced or a supply referenced VCO CFR2 lt 5 gt 0 default The charge pump is configured to operate with a supply referenced VCO If PLLOSC lags PLLREF the charge pump will attempt to drive the VCO control node voltage higher If PLLOSC leads PLLRE the charge pump will attempt to drive the VCO control node voltage lower AD9956 CFR2 lt 5 gt 1 The charge pump is configured to operate with a ground referenced VCO If PLLOSC lags PLLREF the charge pump will attempt to drive the VCO control node voltage lower If PLLOSC leads PLLREF the charge pump will attempt to drive the VCO control node voltage higher CFR2 lt 4 gt Charge Pump Full Power Down This bit when set will put the charge pump into a full power down mode CFR2 lt 4 gt 0 default The charge pump is powered on and operating normally CFR2 lt 4 gt 1 The charge pump is completely powered down CFR2 lt 3 gt Charge Pump Quick Power Down Rather than power down the charge pump which can take a long time to recover from a quick power down mode which powers down only the charge pump output buffer is included While this doesn t reduce the power consumption significantly it does shut off the output to the charge pump and allows it to come back on in a rapidly CFR2 lt 3 gt 0 default The charge pump is powered on and operating normally CFR2 lt 3 gt 1 The c
36. lt 16 gt RF Divider SYSCLK Mux Bit This bit toggles the mux to control whether the RF divider out put or input is supplying SYSCLK to the device CFR2 lt 16 gt 0 default The RF divider output supplies the DDS SYSCLK CFR2 lt 16 gt 1 The RF divider input supplies the DDS SYSCLK bypass the divider Note that regardless of the condition of the configuration of the clock input the DDS SYSCLK must not exceed the maximum rated clock speed Rev A Page 30 of 32 CFR2 lt 15 12 gt PLLREF Divider Control Bits N These 4 bits set the PLLREF divider N ratio where N is a value equal to 1 to 16 CFR2 lt 15 12 gt 0000 means that N 1 and CFR2 lt 15 12 gt 1111 means that N 16 or simply N CFR2 lt 15 12 gt 1 CFR2 lt 15 12 gt N CFR2 lt 15 12 gt N 0000 1 1000 9 0001 2 1001 10 0010 3 1010 11 0011 4 1011 12 0100 5 1100 13 0101 6 1101 14 0110 7 1110 15 0111 8 1111 16 CFR2 lt 11 8 gt PLLREF Divider Control Bits M These 4 bits set the PLLOSC divider M ratio where M is a value equal to 1 to 16 CFR2 lt 11 8 gt 0000 means that M 1 and CFR2 lt 11 8 gt 1111 means that M 16 or M CFR2 lt 11 8 gt 1 CFR2 lt 11 8 gt M CFR2 lt 11 8 gt M 0000 1 1000 9 0001 2 1001 10 0010 3 1010 11 0011 4 1011 12 0100 5 1100 13 0101 6 1101 14 0110 7 1110 15 0111 8 1111 16 CFR2 lt 7 6 gt Open Unused locations Write a Logic 0 CFR2 lt 5 gt CP Polar
37. nction Register 1 CFR1 This control register is comprised of four bytes all of which must be written during a write operation involving CFR1 CFR1 is used to control various functions features and operating modes of the AD9956 The functionality of each bit s is described below In general the bit is named for the function it serves when the bit is set CFR1 lt 31 25 gt Open Unused locations Write a Logic 0 CFR1 lt 24 gt PLL Lock Error Read Only When the device is operating in automatic synchronization mode or hardware manual synchronization mode see below the PLL_LOCK SYNC_IN pin behaves as the SYNC_IN To determine whether or not the PLL has become unlocked while in synchronization mode this bit serves as a flag to indicate that an unlocked condition has occurred within the phase frequency detector Once set the flag stays high until it is cleared by a readback of the value even though the loop might have relocked Readback of the CFRI register clears this bit CFR1 lt 24 gt 0 indicates that the loop has maintained lock since the last readback CFR1 lt 24 gt 1 indicates that the loop became unlocked at some point since the last readback of this bit CFR1 lt 23 gt Load Sweep Ramp Rate at UO UPDATE also known as Load SRR I O_UPDATE The sweep ramp rate is set by entering a value to a down counter that is clocked by the SYNC_CLK Each time a new step is taken in the linear sweep algorithm the ramp rate val
38. ng in the linear sweep default mode combina tional logic ensures that the part never ramps up past FTW1 even if the next RDFTW increments the frequency past FTW1 Once it reaches FT W1 as long as the PSO pin stays high the frequency remains at FTW1 Likewise the internal logic ensures that the part never ramps down past FT WO even if the next RDFTW increments the frequency past FT WO During a sweep down PSO 0 once the part reaches FTWO as long as the PSO pin stays low the frequency remains at FTWO If a sweep is interrupted and the state of the PSO pin is changed during the midst of a sweep the part begins sweeping in the new direction at the rate dictated by the relevant delta fre quency tuning word and sweep ramp rate word For example if the part is programmed to sweep from 100 MHz to 140 MHz and to take 1 kHz steps every 1000 sync clock cycles rising and falling sweep words are the same it would take four seconds to complete a sweep If the PSO has been low for a very long time more than four seconds changing the PSO pin to high starts a sweep up to 140 MHz If after two seconds not enough time for a full sweep in this example the PSO pin is brought low again the part begins sweeping down from the current value roughly 120 MHz Linear Sweep No Dwell Mode This mode is entered by setting the linear sweep enable bit and the linear sweep no dwell bit in the control register CFR lt 17 16 gt 1 When the part is in l
39. nsition Table 7 CML Clock Drive Falling Edge Slew Rate Control Bits and Associated Surge Current CFR2 lt 28 gt 1 5 4 mA CFR2 lt 30 gt 1 2 7 mA CFR2 lt 29 gt 1 1 35 mA CFR2 lt 25 gt PLL_LOCK_DETECT Enable This bit enables the PLL_LOCK SYNC_IN pin as a lock detect output for the PLL CFR2 lt 25 gt 0 default The PLL_LOCK_DETECT signal is disabled CFR2 lt 25 gt 1 The PLL_LOCK_DETECT signal is enabled CFR2 lt 24 gt PLL_LOCK_DETECT Mode This bit toggles the modes of the PLL_LOCK_DETECT func tion The lock detect can either be a status indicator locked or unlocked or it can indicate a lead lag relationship between the two phase frequency detector inputs CFR2 lt 24 gt 0 default The lock detect acts as a status indica tor PLL is locked 0 or unlocked 1 CFR2 lt 24 gt 1 The lock detect acts as a lead lag indicator A 1 on the PLL_LOCK pin means that the PLLOSC pin lags the reference A 0 means that the PLLOSC pin leads the reference CFR2 lt 23 gt RF Divider Power Down This bit powers the RF divider down to save power when not in used CFR2 lt 23 gt 0 default RF divider is on CFR2 lt 23 gt 1 RF divider is powered down and an alternate path between the REFCLK inputs and SYSCLK is enabled CFR2 lt 22 21 gt RF Divider Ratio These two bits control the RF divider ratio R CFR2 lt 22 21 gt 11 default RF Divider R 8 CFR2 lt 22 21 gt 10 RF Divider R 4
40. ple Devices 11 111111111 20 Serial Port Operation a ENE E EEE 22 eet 23 Serial Interface Port Pin Description 23 MSB LSB Trans TETS o Haa 23 Register Map and Description 24 Control Function Register DescripHong sese 27 Elte Dimension Sasss eea se Eain 32 Ordering Guides i wa okna 32 Rev A Page 2 of 32 PRODUCT OVERVIEW The AD9956 is Analog Devices newest AgileRF synthesizer The device is comprised of DDS and PLL circuitry The DDS features a 14 bit DAC operating at up to 400 MSPS and a 48 bit frequency tuning word FTW The PLL circuitry includes a phase frequency detector with scaleable 200 MHz inputs divider inputs operate up to 655 MHz and digital control over the charge pump current The device also includes a 655 MHz CML mode PECL compliant driver with programmable slew rates The AD9956 uses advanced DDS technology an internal high speed high performance DAC and an advanced phase frequency detector charge pump combination which when used with an external VCO enables the synthesis of digitally programmable frequency agile analog output sinusoidal wave forms up to 2 7 GHz The AD9956 is designed to provide fast frequency hopping and fine tuning resolution 48 bit frequency tuning word Information is loaded into the AD9956 via a serial I O port that has a device write speed of 25 Mb s The AD9956 DDS block also supports a user defined linear sweep mode of operation The AD9956 is specified to ope
41. ptical networking clock The loop can be used to generate a 622 MHz clock for OC12 The DDS can be programmed to output 8 kHz to serve as a base reference for other circuits in the subsystem see Figure 25 Direct Upconversion The AD9956 is configured to use the DDS as a precision refer ence to the PLL loop Since the VCO is lt 655 MHz it can be fed straight into the phase frequency detector feedback input with the divider enabled as seen in Figure 26 Rev A Page 17 of 32 AD9956 GENERAL DESCRIPTION DDS CORE The DDS can create digital phase relationships by clocking a 48 bit accumulator The incremental value loaded into the accumulator known as the frequency tuning word controls the overflow rate of the accumulator Similar to a sine wave com pleting a 27 radian revolution the overflow of the accumulator is cyclical in nature and generates a base frequency according to the following equation _ FTWx f 8 0 lt FTW lt 2 o The instantaneous phase of the sine wave is therefore the out put of the phase accumulator block This signal can be phase offset by programming an additive digital phase added to each and every phase sample coming out of the accumulator These instantaneous phase values are then piped through a phase to amplitude conversion sometimes called an angle to amplitude conversion or AAC block This algorithm follows a COS x relationship where x is the phase coming out of the phase offs
42. r CFR1 lt 21 gt 1 Issuing an I O_UPDATE clears the current con tents of the phase accumulator for one SYNC_CLK period CFRI1 lt 20 gt Enable Sine Output Two different trigonometric functions can be used to convert the phase angle to an amplitude value cosine or sine This bit selects the function used CFR1 lt 20 gt 0 default The phase to amplitude conversion block uses a cosine function CFR1 lt 20 gt 1 The phase to amplitude conversion block uses a sine function CERI lt 19 gt Clear Frequency Accumulator This bit serves as a static clear or a clear and hold bit for the frequency accumulator It prevents the frequency accumulator from incrementing the value as long as it is set CFRI lt 19 gt 0 default The frequency accumulator operates normally CFRI lt 19 gt 1 The frequency accumulator is cleared and held at a value of 0 CFRI lt 18 gt Clear Phase Accumulator This bit serves as a static clear or a clear and hold it for the phase accumulator It prevents the phase accumulator from incrementing the value as long as it is set CFRI lt 18 gt 0 default The phase accumulator operates normally CFRI lt 18 gt 1 The phase accumulator is cleared and held at a value of 0 Rev A Page 27 of 32 AD9956 CFR1 lt 17 gt Linear Sweep Enable This bit turns on the frequency accumulator which enables the DDS to perform linear sweeping CFR1 lt 17 gt 0 default The DDS gen
43. rate over the extended automotive range of 40 C to 125 C Rev A Page 3 of 32 AD9956 AD9956 SPECIFICATIONS AVDD DVDD 1 8 V 5 DVDD_I O CP_VDD 3 3 V 5 Ta 25 C DAC_Rser 3 92 kQ CP_Rser 3 09 kQ DRV_Rser 4 02 kQ unless otherwise noted Table 1 Parameter Min Typ Max Unit Test Conditions Comments RF DIVIDER REFCLK INPUT SECTION R RF Divider Input Range 1 2700 MHz DDS SYSCLK not to exceed 400 MSPS Input Capacitance DC 3 pF Input Impedance DC 1500 Q Input Duty Cycle 42 50 58 Input Power Sensitivity 10 4 dBm Single ended into a 50 Q load Input Voltage Level 350 1000 mV p p PHASE FREQUENCY DETECTOR CHARGE PUMP PLLREF Input Input Frequency M Set to Divide by at Least 4 655 MHz M Bypassed 200 MHz Input Voltage Levels 200 450 600 mV p p Input Capacitance 10 pF Input Resistance 1500 Q PLLO C Input Input Frequency N Set to Divide by at Least 4 655 MHz N Bypassed 200 MHz Input Voltage Levels 200 450 600 mV p p Input Capacitance 10 pF Input Resistance 1500 Q Charge Pump Source Sink Maximum Current 4 mA Charge Pump Source Sink Accuracy 15 5 Charge Pump Source Sink Matching 5 5 Charge Pump Output Compliance Range 0 5 CP_VDD 0 5 V PLL_LOCK Drive Strength 2 mA PHASE FREQUENCY DETECTOR NOISE FLOOR 50 kHz PFD Frequency 149 dBc Hz 2 MHz PFD Frequency 133 dBc Hz 100 MHz PFD Frequency 116 dBc Hz 200 MHz PFD Frequency 113 dBc Hz CML OUTPUT
44. rising edge by one SYSCLK period When this bit is enabled the PLL_LOCK is not available as an output However an out of lock condition can be detected by reading Control Function Register 1 and checking the status of the PLL Lock Error bit CFR1 lt 24 gt This synchronization function is enabled by setting the hardware manual synchronization enable bit CFR1 lt 1 gt AD9956 Manual Synchronization Software Controlled In this mode the user controls the timing relationship between SYNC_CLK and SYSCLK through software programming When the software manual synchronization bit CFR1 lt 2 gt is set high the SYNC_CLK is advanced by one SYSCLK cycle Once this operation is complete the bit is cleared The user can set this bit repeatedly to advance the SYNC_CLK rising edge multiple times Because the operation does not use the PLL_LOCK SYNC_IN pin as a SYNC_IN input the PLL_LOCK signal can be monitored on the PLL_LOCK pin during this operation SYNCHRONIZATION FUNCTIONS CAN ALIGN DIGITAL CLOCK RELATIONSHIPS THEY CANNOT DESKEW THE EDGES OF CLOCKS SYSCLK DUT 1 0 1 2 3 0 SYNC CLK DUT SYNC CLK DUT2 WITHOUT SYNC_CLK ALIGNED SYNC_CLK ALIGNED T 1 1 1 l 1 SYNC CLK DUT2 WITH 1 1 Figure 28 Synchronization Functions Capabilities and Limitations Rev A Page 21 of 32 AD9956 SERIAL PORT OPERATION An AD9956 serial data port communication cycle has two phases Phase 1 is the instruction cycle which is the w
45. riting of an instruction byte to the AD9956 coincident with the first eight SCLK rising edges The instruction byte provides the AD9956 serial port controller with information regarding the data transfer cycle which is Phase 2 of the communication cycle The Phase 1 instruction byte defines whether the upcoming data transfer is read or write and the serial address of the register being accessed The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9956 The remaining SCLK edges are for Phase 2 of the communication cycle Phase 2 is the actual data transfer between the AD9956 and the system controller The number of bytes transferred during Phase 2 of the communication cycle is a function of the INSTRUCTION CYCLE register being accessed For example when accessing Control Function Register 2 which is four bytes wide Phase 2 requires that four bytes be transferred If accessing a frequency tuning word which is six bytes wide Phase 2 requires that six bytes be transferred After transferring all data bytes per the instruction the communication cycle is completed At the completion of any communication cycle the AD9956 serial port controller expects the next eight rising SCLK edges to be the instruction byte of the next communication cycle All data input to the AD9956 is registered on the rising edge of SCLK All data is driven out of the AD9956 on the falling edge of SCL
46. t Frequency Tuning Word 3 FTW3 lt 39 32 gt 0x00 lt 31 24 gt Frequency Tuning Word 3 FTW3 lt 31 24 gt 0x00 lt 23 16 gt Frequency Tuning Word 3 FTW3 lt 23 16 gt 0x00 lt 15 8 gt Frequency Tuning Word 3 FTW3 lt 15 8 gt 0x00 lt 7 0 gt Frequency Tuning Word 3 FTW3 lt 7 0 gt 0x00 1 In all cases open bits must be written to 0 Rev A Page 25 of 32 AD9956 Default Register Name Bit MSB Bit 0 Value Serial Address Range Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Profile Profile Control lt 63 56 gt Open Phase Offset Word 4 POW4 lt 13 8 gt 0x00 Register lt 55 48 gt Phase Offset Word 4 POW4 lt 7 0 gt 0x00 No 4 RCRA 0x0A ege Frequency Tuning Word 4 FTW4 lt 47 40 gt 0x00 lt 39 32 gt Frequency Tuning Word 4 FTW4 lt 39 32 gt 0x00 lt 31 24 gt Frequency Tuning Word 4 FTW4 lt 31 24 gt 0x00 lt 23 16 gt Frequency Tuning Word 4 FTW4 lt 23 16 gt 0x00 lt 15 8 gt Frequency Tuning Word 4 FTW4 lt 15 8 gt 0x00 lt 7 0 gt Frequency Tuning Word 4 FTW4 lt 7 0 gt 0x00 Profile Control lt 63 56 gt Open Phase Offset Word 5 POW5 lt 13 8 gt 0x00 Register lt 55 48 gt Phase Offset Word 5 POW5 lt 7 0 gt 0x00 No 5 PCRS 0x0B lt 47 40 gt Frequency Tuning Word 5 FTW5 lt 47 40 gt 0x00 lt 39 32 gt Frequency Tuning Word 5 FTW5 lt 39 32 gt 0x
47. tem clock cycle This bit is self clearing and can be set multiple times CFR1 lt 2 gt 0 default The SYNC_CLK stays in the current timing relationship to SYSCLK CFR1 lt 2 gt 1 The SYNC_CLK advances the rising and falling edges by one SYSCLK cycle This bit is then self cleared CFR1 lt 1 gt Hardware Manual Synchronization Similar to the software manual synchronization CFR1 lt 2 gt this function enables the user to advance the SYNC_CLK rising edge by one system clock period This bit enables the PLL_LOCK SYNC_IN pin as a digital input Once enabled every rising edge on the SYNC_IN input advances the SYNC_CLK by one SYSCLK period While enabled the PLL_LOCK signal is not available on an external pin However loop out of lock events trigger a flag in the control register CFR1 lt 24 gt CFR1 lt 1 gt 0 default The hardware manual synchronization function is disabled Either the part is outputting the PLL_LOCK CFR1 lt 3 gt 0 or it is using the SYNC_IN to slave the SYNC_CLK signal to an external reference provided on SYNC_IN CFR1 lt 3 gt 1 CFR1 lt 1 gt 1 PLL_LOCK SYNC_IN is set as a digital input Each subsequent rising edge on this pin advances the SYNC_CLK rising edge by one SYSCLK period CFR1 lt 0 gt High Speed Synchronization Enable Bit This bit enables extra functionality in the auto synchronization algorithm which enables the device to synchronize high speed clocks SYNC_CLK gt 62 5 MHz
48. the output frequency of the device from a programmed lower frequency to a programmed upper frequency or from the upper frequency to the lower frequency The lower frequency is set by the frequency tuning word stored in Profile 0 and the upper frequency is set by the frequency tuning word stored in Profile 1 The combinational logic within the frequency accumulator requires that the value stored at FTWO must always be less than the value stored in FTW The direction of the sweep sweep up to FTW1 sweep down to FT WO is controlled by the PSO pin A high state on this pin tells the part to sweep up to FTW1 A low state on this pin tells the part to sweep down to FTWO The frequency accumulator requires four values which are stored in the register map First it requires an incremental frequency value that tells the frequency accumulator how big of a fre quency step to take each time it takes a step when ramping up This value is stored in the rising delta frequency tuning word RDFTW The second value required is the rate at which the frequency accumulator should increment that is how often it should take a step This value is stored in the rising sweep ramp rate word RSRR The RSRR value specifies the number of SYNC_CLK cycles the frequency accumulator should count between steps The third and fourth values are the falling ramp equivalents the falling delta frequency tuning word FDFTW and the falling sweep ramp rate FSRR When operati
49. ue is passed from the linear sweep ramp rate register to this down counter When set CFR1 lt 23 gt enables the user to force the part to restart the countdown sequence for the current linear sweep step by toggling the I O_UPDATE pin CFR1 lt 23 gt 0 default The linear sweep ramp rate countdown value is loaded only upon completion of a countdown sequence CFR1 lt 23 gt 1 The linear sweep ramp rate countdown value is reloaded if an I O_UPDATE signal is sent to the part during a sweep CFR1 lt 22 gt Auto Clear Frequency Accumulator This bit enables the auto clear function for the frequency accu mulator The auto clear function serves as a clear and release func tion for the frequency accumulator which performs the linear sweep operation which then begins sweeping from a known value of FTWO AD9956 CFR1 lt 22 gt 0 default Issuing an UO UPDATE has no effect on the current state of the frequency accumulator CFRI lt 22 gt 1 Issuing an I 0_UPDATE signal to the part clears the current contents of the frequency accumulator for one sync clock period CFRI lt 21 gt Auto Clear Phase Accumulator This bit enables the auto clear function for the phase accumula tor The auto clear function serves as a reset function for the phase accumulator which then begins accumulating from a known phase value of 0 CFR1 lt 21 gt 0 default Issuing an UO UPDATE has no effect on the current state of the phase accumulato
50. ycle SERIAL INTERFACE PORT PIN DESCRIPTION SCLK Serial Clock The serial clock pin is used to synchronize data to and from the AD9956 and to run the internal state machines The SCLK maximum frequency is 25 MHz CS Chip Select Bar CS is an active low input that allows more than one device on the same serial communications line The SDO and SDI O pins go to a high impedance state when this input is high If driven high during any communications cycle that cycle is suspended until CS is reactivated low Chip select can be tied low in systems that maintain control of SCLK SDI O Serial Data Input Output Data is always written to the AD9956 on this pin However this pin can be used as a bidirec tional data line CFR1 lt 7 gt controls the configuration of this pin The default value 0 configures the SDI O pin as bidirectional SDO Serial Data Out Data is read from this pin for protocols that use separate lines for transmitting and receiving data When the AD9956 operates in a single bidirectional I O mode this pin does not output data and is set to a high impedance state I O_RESET A high signal on this pin resets the I O port state machines without affecting the addressable registers contents An active high input on the I O_RESET pin causes the current communication cycle to abort After I O_RESET returns low 0 another communication cycle can begin starting with the instruction byte write Note that when not in use
51. z Four 155 52 MHz BW 12 kHz gt 1 3 MHz 101 fs rms OC3 RF Divider R 8 Fin 2488 32 MHz Four 622 08 MHz BW 12 kHz gt 5 MHz 108 fs rms OC12 RF Divider R 4 RF DIVIDER CML DRIVER RESIDUAL PHASE NOISE Fin 157 6 MHz Four 19 7 MHz RF DividerR 8 10 Hz 115 dBc Hz 100 Hz 126 dBc Hz 1 kHz 134 dBc Hz 10 kHz 143 dBc Hz 100 kHz 150 dBc Hz gt 1 MHz 151 dBc Hz Fin 1240 MHz Four 155 MHz RF DividerR 8 10 Hz 111 dBc Hz 100 Hz 122 dBc Hz 1 kHz 129 dBc Hz 10 kHz 138 dBc Hz 100 kHz 146 dBc Hz 1 MHz 150 dBc Hz gt 3 MHz 153 dBc Hz Fin 2488MHz Four 622 MHz RF Divider R 4 10 Hz 97 dBc Hz 100 Hz 110 dBc Hz 1 kHz 120 dBc Hz 10 kHz 126 dBc Hz 100 kHz 136 dBc Hz 1 MHz 141 dBc Hz gt 3 MHz 144 dBc Hz TOTAL SYSTEM TIME JITTER FOR 622 MHz CLOCK See the Loop Measurement Condi tions section 12 kHz to 5 MHz Bandwidth 0 7 ps rms Rev A Page 7 of 32 AD9956 Parameter TOTAL SYSTEM JITTER AND PHASE NOISE FOR 105 33 MHz ADC CLOCK GENERATION CIRCUIT Converter Limiting Jitter Resultant SNR Phase Noise of Fundamental 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 kHz Offset 100 kHz Offset 1 MHz Offset Min Typ Max 0 53 67 75 87 93 105 145 152 Unit ps rms dB dBc Hz dBc Hz dBc Hz dBc Hz dBc Hz dBc Hz Test Conditions Comments See the Loop Me
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ANALOG DEVICES AD9956 English products handbook Rev A