ANALOG DEVICES ADRF6603 English products handbook Rev A
Contents
1. 1 0 LO FREQUENCY 2595 2MHz z 07 9 o 8 2 06 3 lt 05 n Q 04 2 0 3 x 02 0 1 0 1k 10k 100k 1M 10M 100M 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 5 OFFSET FREQUENCY Hz i LO FREQUENCY MHz Figure 32 Phase Noise vs Offset Frequency Figure 35 Integrated Phase Noise vs LO Frequency 75 _ 100 5 5 m OFFSET 110 d gt 5 120 tc 5 130 5 E 100 140 105 150 110 160 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 x 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY MHz LO FREQUENCY MHz Figure 33 PLL Reference Spurs vs LO Frequency 2x PFD and 4x PFD Figure 36 Phase Noise vs LO Frequency 1 kHz 100 kHz and 5 MHz Steps 75 80 PFD FREQUENCY 85 1x PFD FREQUENCY 25 80 40 C 90 _ 100 S z a 110 E 90 m 2 120 95 tc 5 130 E s 100 140 105 150 110 4 160 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 T 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 z LO FREQUENCY MHz LO FREQUENCY MHz Figure 34 PLL Reference Spurs vs LO Frequency 0 25x PFD 1x PFD and 3x PFD Figure 32. 2 5 SogA A g L 5 5 1 39001 pe vsu 3 3400 _ 51 qeu I e dovo 20 29 En OT 99 0 6 Qr eir 0 Nai SRL i 7 mewe 2522 EA 101 92 oS 2088 d 209 ING 7 esu qN v angy GN9V 61H A bd gal ep noL ag t m 7 n yos ING 4400 0 99 SH GREY e E eso z 9 dt 9i 0 9159999 5 4 0 angy angy z 2 K 542 gly 1n6d38 8 Pq Ids ng gt 5 6 3 5 5 2 390001 20 jd 7 Huano Z ONTT or igo usd E a994 OAT sd 5 552 88 Seu lt MOV ibtd E z Huano 90110033 188 gir SRY ARA pe DN F I lt Nudd 3335 55 527 13686 800022 aNSv angy z ZZ HHOOA 20 gz Huano 10099 950 2 dE 621 135841 42 o lt O0NT 950 09 5 9 8 9 s 8 E 8 5 655 5 m v 39001 JjnroL ano dc c de 4 pi a5 Wor 340 IN
3. 08547 012 Figure 52 Evaluation Board Layout Top ADRF6603 EVALUATION BOARD CONFIGURATION OPTIONS Table 10 Component Description Default Condition Option Settings S1 R55 R56 R33 LO select Switch and resistors to ground the LODRV_EN pin The LODRV_EN pin setting in combination with internal register settings determines whether the LOP and LON pins 1 R55 open not installed function as inputs or outputs see the LO Selection Logic section for more information R56 R33 00 LODRV EN 0V LO IN OUT LO input output An external 1x LO or 2x LO can be applied to this single ended input LO input SMA Connector connector REFIN Reference input The input reference frequency for the PLL is applied to this connector SMA Connector Input impedance is 50 O REFOUT Multiplexer output The REFOUT connector connects directly to the MUXOUT pin The Lock detect SMA Connector on board multiplexer can be programmed to bring out the following signals REFIN 2x REFIN REFIN 2 and REFIN 4 temperature sensor output voltage and lock detect indicator CP Test Point Charge pump test point The unfiltered charge pump signal can be probed at this test point Note that the CP pin should not be probed during critical measurements such as phase noise R37 C14 R9 R10 C15 C13 R65 C40 Loop filter Loop filter components R11 R12 Loop filter return Wh
4. 1 Cha geste Tablerlu eerte 1 Changes t Table 2 a aaa maa e t haqa 3 Changes to Table 3 and Table 4 sss 4 Charges to Table 6 Change to Table 7 Pin 36 Description Changes to Typical Performance Characteristics Section Added Spurious Performance Section sss 15 Register 3 gt A Modulator Dither Control Default 10000 17 Register 4 PLL Charge Pump Reference Path Control Default 0x0AA7E4 3 18 Register 5 PLL Enable and LO Path Control Default 0 0000 5 ette 19 Register 6 VCO Control and VCO Enable Default DETE2 106 eco 19 Register 7 Mixer Bias Enable and External VCO Enable Default 0x000007 tieu tete tette necatus 19 Theory of Operation 20 Programming the ADRF6603 sse 20 Initialization Sequence 20 LO Selection Logic eerte tentent 21 Applications Information 22 Basic Connections for Operation sse 22 Test Pix tune a ii eet ice mie en 23 Evaluation Board noe uwa CHO Ren PP 24 Evaluation Board Control Software sss 24 Schematic and seen 26 Evaluation Board Configuration 28 Outline DimensioTns irei a er RR Pe ees 29 Ordering Glide accepere t
5. 08547 007 Figure 41 Register 3 2 Modulator Dither Control Register Rev A Page 17 of 32 ADRF6603 REGISTER 4 PLL CHARGE PUMP PFD AND REFERENCE PATH CONTROL DEFAULT 0x0AA7E4 INPUT REF CURRENT MUX SELECT PATH REF PFD ANTI PFD PHASE OFFSET CONTROL BITS MULTIPLIER DELAY DB23 DB22 21 DB20 DB19 0817 16 DB15 14 13 DB12 DB11 DB10 pee pes bet Rus2 Rusi Ruso 931 CPB2 CPB0 cps crco PE Peo 1 PABo c20 C1 0 PFD ANTI BACKLASH PAB0 PAB1 DELAY 0 0 Ons DEFAULT 0 1 0 5ns 1 0 0 75ns 1 1 0 9ns REFERENCE PATH EDGE SENSITIVITY FALLING EDGE RISING EDGE DEFAULT DIVIDER PATH EDGE SENSITIVITY FALLING EDGE RISING EDGE DEFAULT 1 CHARGE PUMP CONTROL BOTH ON PUMP DOWN PUMP UP TRISTATE DEFAULT CHARGE PUMP CONTROL SOURCE CONTROL BASED ON STATE OF DB7 DB8 CP CONTROL 1 CONTROL FROM PFD DEFAULT CHARGE PUMP CURRENT H 250 500 DEFAULT 750 1000 CPB4 CPB3 2 1 CPB0 PFD PHASE OFFSET MULTIPLIER 0 0 aM dE 1 x 22 5 ICPMULT 6 x 22 5 RECOMMENDED CPBD PFD PHASE OFFSET POLARITY NEGATIVE POSITIVE DEFAULT cpm CHARGE PUMP CURRENT REFERENCE SOURCE INTERNAL DEFAULT EXTERNAL 10
6. 1 0 0 5 0 0 5 1 0 15 20 2 20 26 28 GAIN dB 8 INPUT IP3 dBm Figure 26 Gain Figure 29 Input IP3 IP3SET OPEN IP3SET 3 3V 5 OPEN IP3SET 3 3V DISTRIBUTION PERCENTAGE DISTRIBUTION PERCENTAGE 85 25 40 C 08547 127 08547 130 INPUT IP2 dBm INPUT P1dB dBm Figure 27 Input IP2 Figure 30 Input P1dB 100 100 IP3SET OPEN 90 90 IP3SET 3 3V 80 80 D 9 9 70 E 8 8 60 n 50 50 2 z S S B 40 30 8 30 2 2 2 2 7 85 C 10 10 ff TA 25 1 40 C 0 0 55 53 51 49 47 45 43 41 39 37 35 LO FEEDTHROUGH dBm Figure 28 Noise Figure Figure 31 LO Feedthrough to IF LO Output Turned Off 08547 128 NOISE FIGURE dB 08547 131 Rev A Page 13 of 32 ADRF6603 Measured at IF output CDAC 0x1 IP3SET open internally generated high side LO frer 153 6 MHz 38 4 MHz 5 dBm 140 MHz unless otherwise noted Phase noise measurements made at LO output unless otherwise noted
7. CHARGE 3 3V vco VCOLDO VCO vco See ENABLE ENABLE pB23 pB22 bBz1 20 19 0818 16 15 14 13 12 11 10 DBS pes 2 DBO o LvEN DISABLE ENABLE DEFAULT 5225 24 DEFAULT L3EN 3 3V LDO ENABLE 43 DISABLE 63 RECOMMENDED VBSRC VCO BW CAL AND SW SOURCE CONTROL ENABLE DEFAULT E BAND CAL DEFAULT VCO SW VCO SWITCH CONTROL FROM SPI SPI LVEN VCO LDO ENABLE REGULAR DEFAULT 0 DISABLE BAND CAL 1 ENABLE DEFAULT VCO EN VCO ENABLE DISABLE ENABLE DEFAULT Figure 44 Register 6 VCO Control and VCO Enable Register DEFAULT 0x20 08547 010 REGISTER 7 MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE DEFAULT 0x000007 Rs XVCO E RESERVED CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 pes DB2 0 MBE MIXER BIAS ENABLE ENABLE DEFAULT DISABLE XVCO EXTERNAL VCO INTERNAL VCO DEFAULT EXTERNAL VCO Figure 45 Register 7 Mixer Bias Enable and External VCO Enable Register Map Rev A Page 19 of 32 08547 011 ADRF6603 THEORY OF OPERATION The ADRF6603 integrates a high performance downconvertin
8. 22 5 cpmuLr DEFAULT 16 x 22 5 lCPMULT 31 x 22 5 lCPMULT INPUT REFERENCE SOURCE 2 REFIN REFIN DEFAULT 0 5x REFIN 0 25x REFIN Ruso REF OUTPUT MUX SELECT LOCK DETECT DEFAULT VPTAT REFIN BUFFERED 0 5x REFIN BUFFERED 2x REFIN BUFFERED TRISTATE RESERVED RESERVED 2aaaaoooo H H 08547 008 Figure 42 Register 4 PLL Charge Pump PFD and Reference Path Control Register Map Rev A Page 18 of 32 ADRF6603 REGISTER 5 PLL ENABLE AND LO PATH CONTROL DEFAULT 0x0000E5 PLL LO LO LO 23 0622 B21 20 19 18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 pBs pee pes pes DB2 081 DBO o Lovi fesa fezo cim CAPACITOR DAC LO OUTPUT DRIVER CD3 CD2 CONTROL FOR IIP3 LDRV ENABLE OPTIMIZATION 0 DRIVER OFF DEFAULT RE DRIVER ON 1 EXTERNAL LO DRIVE LXL ENABLE PIN 37 PIN 38 INTERNAL LO OUTPUT DEFAULT EXTERNAL LO INPUT DIVIDE BY 2 IN LO CHAIN ENABLE 0 DIVIDE BY 1 1 DIVIDE BY 2 DEFAULT PLEN PLL ENABLE DISABLE ENABLE DEFAULT Figure 43 Register 5 PLL Enable and LO Path Control Register Map 08547 009 REGISTER 6 VCO CONTROL AND VCO ENABLE DEFAULT 0x1E2106
9. 0603 1206 R11 R1 que OPEN 00 0402 0402 0402 C43 C2 Ci 10 OPEN 100pF 0603 0402 0402 08547 024 Figure 46 Basic Connections for Operation of the ADRF6603 Rev A Page 22 of 32 ADRF6603 AC TEST FIXTURE Characterization data for the ADRF6603 was taken under very the signal generation and measurement equipment Figure 47 strict test conditions All possible techniques were used to shows the typical AC test set up used in the characterization of achieve optimum accuracy and to remove degrading effects of the ADRF6603 ADRF6603 CHARACTERIZATION RACK DIAGRAM 222261682225 ALL INSTRUMENTS ARE CONTROLLED BY A LAB sss COMPUTER VIA A USB TO GPIB CONTROLLER DAISY CHAINED TO EACH INDIVIDUAL INSTRUMENT RF1 AGILENT N5181A z HP 11636A POWER DIVIDER a ROHDE amp SCHWARTZ lt FSEA30 m 25 85 nc 58 2 ER 82 AGILENT 34401A SET TO IDC z SET FOR SUPPLY CURRENT a F o 5V dc VIA 10 PIN DC HEADER GND VIA 10 PIN DC HEADER 3 3V dc VIA 10 PIN DC HEADER gt 399 7 595 gt 3299 00 9222 AGILENT 34980A WITH THREE 34921 MODULES AND ONE 34950 MODULE 5V dc MEASURED FOR SUPPLY CURRENT AGILENT E3631A 25V SET TO 3 3V 6V SET TO 5V RETURNS ARE JUMPERED TOGETHER 08547 047 Figure 47 ADRF6603 AC Test Setup Rev A Page 23 of 32 ADRF6603 EVALUATION BOARD Figure 50 shows the schematic of the RoHS compliant eva
10. C 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 IF FREQUENCY MHz Figure 11 Noise Figure vs IF Frequency INPUT IP3 dBm 08547 109 INPUT P1dB dBm 08547 110 08547 111 Rev A Page 10 of 32 45 IP3SET OPEN IP3SET 3 3V 40 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 IF FREQUENCY MHz Figure 12 Input IP3 vs IF Frequency 5 dBm IP3SET OPEN IP3SET 3 3V 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 IF FREQUENCY MHz Figure 13 Input P1dB vs IF Frequency 08547 112 08547 113 ADRF6603 0 0 IP3SET OPEN TA 85 C 5 IP3SET 3 3V 25 TA 40 10 4 B 15 20 B 8 30 2 10 u 35 po 4 40 14 45 9 16 50 18 20 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 LO FREQUENCY MHz 60 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO MHz 08547 114 08547 117 Figure 14 LO to IF Feedthrough vs LO Frequency Figure 17 LO Input Return Loss vs LO Freq
11. DB23 MSB t DB2 DB1 CONTROL BIT C3 CONTROL BIT C2 Figure 2 Timing Diagram Rev A Page 5 of 32 DB0 LSB CONTROL BIT C1 08547 002 ADRF6603 ABSOLUTE MAXIMUM RATINGS Table 6 Parameter Rating Supply Voltage VCC1 VCC2 LO 0 5 V to 5 5 V 21 Digital CLK DATA LE LODRV 0 3V to 3 6 V PLL EN VTUNE 0Vto3 3V IFP IFN 0 3V to V21 0 3 V RFin 16 dBm LOP LON REF_IN 13 dBm Exposed Paddle Soldered Down 35 C W Maximum Junction Temperature 150 C Operating Temperature Range Storage Temperature Range 40 to 85 C 65 to 150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge 4 without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality
12. 68 23 103 38 4 106 13 106 74 112 72 5 107 26 105 45 6 110 74 7 Rev A Page 15 of 32 ADRF6603 REGISTER STRUCTURE This section provides the register maps for the ADRF6603 The three LSBs determine the register that is programmed REGISTER O INTEGER DIVIDE CONTROL DEFAULT 0 0001 0 DIVIDE RESERVED MODE INTEGER DIVIDE RATIO CONTROL BITS sas pass oss bez pese ss o osse pes psa ors osea pss ess pes nes v pas oes oss 1 we or DIVIDE MODE FRACTIONAL DEFAULT INTEGER 21 INTEGER MODE ONLY 22 INTEGER MODE ONLY 23 INTEGER MODE ONLY 24 56 DEFAULT 119 120 INTEGER MODE ONLY 121 INTEGER MODE ONLY 122 INTEGER MODE ONLY 123 INTEGER MODE ONLY Figure 38 Register 0 Integer Divide Control Register Map REGISTER 1 MODULUS DIVIDE CONTROL DEFAULT 0x003001 RESERVED MODULUS VALUE CONTROL BITS reve pszs 0522 Dezo were ose 877 Dra 0513 prt 0616 pe par o uos woe woe wor wor upo cat cat jern MD2 MD MDO MODULUS VALUE MD7 MD4 MD10 MD9
13. Frequency 90 20 IP3SET OPEN IP3SET OPEN IP3SET 3 3V 19 IP3SET 3 3V 80 18 _ 1 70 m 5 5 16 2 m 60 9 45 E amp 50 13 40 12 11 30 gt 10 g 1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460 1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460 RF FREQUENCY MHz 8 RF FREQUENCY MHz 5 Figure 5 Input 2 vs Frequency Figure 8 Input P1dB vs RF Frequency NOISE FIGURE dB IP3SET OPEN IP3SET 3 3V 1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460 RF FREQUENCY MHz 08547 106 Figure 6 Noise Figure vs RF Frequency Rev A Page 9 of 32 ADRF6603 IF FREQUENCY SWEEP CDAC 0 1 internally generated swept low side LO 1960 MHz 5 dBm unless otherwise noted GAIN dB INPUT IP2 dBm NOISE FIGURE dB IP3SET OPEN IP3SET 3 3V 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 IF FREQUENCY MHz Figure 9 Gain vs IF Frequency IP3SET OPEN IP3SET 3 3V 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 IF FREQUENCY MHz Figure 10 Input IP2 vs IF Frequency RFin 5 dBm 20 IP3SET OPEN 18 IP3SET 3 3V 85 C 2 425 C Ta 40
14. MD5 MD8 MD6 1536 DEFAULT 08547 005 Figure 39 Register 1 Modulus Divide Control Register Map Rev A Page 16 of 32 08547 004 ADRF6603 REGISTER 2 FRACTIONAL DIVIDE CONTROL DEFAULT 0x001802 EE pas 0822 820 e19 ove ppiz per pea vers pera pes a pes o o o o o o o For ros Fo ps 768 DEFAULT FRACTIONAL VALUE MUST BE LESS THAN MODULUS 08547 006 Figure 40 Register 2 Fractional Divide Control Register Map REGISTER 3 2 A MODULATOR DITHER CONTROL DEFAULT 0x10000B DITHER DITHER aM MAGNITUDE DITHER VALUE CONTROL BITS DB22 252 o DEN Dve nva pve ovs ova bv2 Dv ovo JestyJcato eicn DITH1 DITHO DITHER MAGNITUDE 15 DEFAULT 7 3 1 RECOMMENDED DEN DITHER ENABLE 0 DISABLE 1 ENABLE DEFAULT RECOMMENDED DV16 DV15 DV13 DV12 DV11 DV10 DV2 Dvo DITHER RESTART 0x00001 DEFAULT
15. current multiplier PFD Phase Offset Polarity postive PFD Phase Offset 112 5 Output Reference Mux Source VCO Controls and Enables PFD Falling Edge v SDM Dither Control VCO LDO Enable E PFD Reference Path Edge Sensitivity Dither Restart Value 3 3V LDO Enable 1 SDM Dither Enable Dither En Lock Detect Rising Edge recs PFD Anti Backlash Delay SDM Dither Magnitude Extemal VCO Enable Disable nsec v VCO Switch Control from SPI VCO Band Select from SPI VCO Amplitude Setting 55 5 VCO Band Select and SW Source Band To be Loaded in Registers on Next Update To be Loaded in Registers on Next Update MSB Binary LSB Hex MSB Binary LSB Hex 0000 0000 0000 0001 1111 000 000000 mmm 0000 1010 1010 0111 1010 0 100 000000 0000 0000 0011 0000 0000 001 000000 0000 0000 0000 0000 0110 0 101 000000 0000 0000 000 1000 0000 000000 0001 1110 1101 1101 0000 110 000000 0110 0000 0000 0000 0000 1 01 00000 0000 0000 0000 0000 0000 0 111 000000 Cap DAC Value 0 Spare R7 Value 08547 049 Figure 49 Main Screen of the ADRF6603 Evaluation Board Software Rev A Page 25 of 32 ADRF6603 SCHEMATIC AND ARTWORK
16. is powered down and the external LO input is routed to the mixer LO inputs The SPI can also be used to switch modes Rev A Page 7 of 32 ADRF6603 Pin No Mnemonic Description 17 34 VCC_LO Power Supply Power supply voltage range is 4 75 V to 5 25 V Each power supply pin should be decoupled with a 100 pF capacitor and a 0 1 pF capacitor located close to the pin 18 19 IFP IFN Mixer IF Outputs These outputs should be pulled to VCC with RF chokes 22 VCC MIX Power Supply Power supply voltage range is 4 75 V to 5 25 V Each power supply pin should be decoupled with a 100 pF capacitor and a 0 1 capacitor located close to the pin 26 RFin RF Input Single Ended 50 27 21 Power Supply Power supply voltage range is 4 75 V to 5 25 V Each power supply pin should be decoupled with a 100 pF capacitor and 0 1 uF capacitor located close to the pin 29 IP3SET Connect a resistor from this pin to a 5 V supply to adjust IIP3 Normally leave open 32 33 NC No Connection 36 LODRV EN LO Driver Enable Together with Pin 16 PLL EN this digital input pin determines whether the LOP and LON pins operate as inputs or outputs LOP and LON become inputs if the PLL EN pin is low or if the PLL EN pin is set high with the PLEN bit DB6 in Register 5 set to 0 LOP and LON become outputs if either the LODRV EN pin or the LDRV bit DB3 in Register 5 is set to 1 while the PLL EN pin is set high External LO drive frequen
17. to peak differential swing on of 1 V 0 353 V rms for a sine wave input results in an IF output power of 4 7 dBm The reference frequency for the PLL should be from 12 MHz to 160 MHz and should be applied to the REF IN pin which should P1 9 PIN GOGOGGGGOG sus vcc R36 si RIS R35 m 00 300 10kQ R20 0402 0402 1 0402 R57 0402 00 82 0402 0402 038 vec 0402 OPEN OPEN 0402 RED O V 0402 1 0402 45V C9 C33 R51 Jour low OPEN 0402 0402 V i C32 R50 RED 9055 OPEN OPEN R55 0402 0402 XL 0402 e ir 40462 0402 8 51 LO 7 R56 Q9 TT 09 71 DECL2P5 00 LODRV_EN C16 R18 C17 C42 m TS 8 8 67 0402 bee LOP 9 DECL3P3 s YT 0402 C12 Rs Cii C41 100pF OPEN TC1 1 13 C6 4 0462 0402 4 6402 0603 1nF 0402 v THIRD ORDER RFIN c31 FRACTIONAL INTERPOLATOR 00 PRESCALER REFIN 0402 REF IN C REFOUT DETECTOR 750 6 2 4830 CHARGE PUMP s SET 0402 PHASE 250 27 27 FREQUENCY 500pA DEFAULT 00 0 1pF 0402 L 6402 MO 1000 R16 V 00 Rset 9 2 0402 R2 RFOUT V R37 OPEN 00 0402 0402 V R38 cp 00 R910kQ R65 10kO TEST _ 0402 0402 0402 POINT w ORANGE 0603 C13 C40 22pF Cis 6 8 22pF 0603 c15 0603
18. 2 ADRF6603 SYNTHESIZER PLL SPECIFICATIONS Vs 5 Vi ambient temperature Ta 25 C frer 153 6 MHz frer power 4 dBm ferp 38 4 MHz high side LO injection fir 140 MHz IIP3 optimized using CDAC 0x1 and IP3SET 3 3 V unless otherwise noted Table 3 Parameter Test Conditions Comments Min Typ Max Unit SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to 1x LO Frequency Range Internally generated LO 2100 2600 MHz Figure of Merit Prer in dBm 222 dBc Hz Hz Reference Spurs 38 4 MHz 4 107 dBc 82 gt fprp 85 dBc PHASE NOISE fio 2100 MHz to 2600 MHz fero 38 4 MHz 1 kHz to 10 kHz offset 88 dBc Hz 100 kHz offset 99 5 dBc Hz 500 kHz offset 120 dBc Hz 1 MHz offset 128 dBc Hz 5 MHz offset 142 dBc Hz 10 MHz offset 148 dBc Hz 20 MHz offset 150 dBc Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth 0 42 rms PFD Frequency 20 40 MHz REFERENCE CHARACTERISTICS REF_IN MUXOUT pins REF_IN Input Frequency 12 160 MHz REF_IN Input Capacitance 4 pF MUXOUT Output Level Vo lock detect output selected 0 25 V Von lock detect output selected 2 7 V MUXOUT Duty Cycle 50 96 CHARGE PUMP Pump Current Programmable to 250 500 750 uA 1 mA 500 HA Output Compliance Range 1 2 8 V 1 The figure of merit is computed as phase noise dBc Hz 10Log10 fero 2010910 The was measured across the full L
19. 603 APPLICATIONS INFORMATION BASIC CONNECTIONS FOR OPERATION be ac coupled and terminated with a 50 O resistor as shown in Figure 46 The reference signal or a divided down version of the reference signal can be brought back off chip at the multiplexer output pin MUXOUT A lock detect signal and a voltage proportional to the ambient temperature can also be selected Figure 46 shows the schematic for the ADRF6603 evaluation board The six power supply pins should be individually decoupled using 100 pF and 0 1 capacitors located as close as possible to the device In addition the internal decoupling nodes DECL3P3 DECL2P5 and DECLVCO should decoupled on the multiplexer output pin with the capacitor values shown in Figure 46 The loop filter is connected between the CP and VTUNE pins When connected in this way the internal VCO is operational For information about the loop filter components see the Evaluation Board Configuration Options section The RF input is internally ac coupled and needs no external bias The IF outputs are open collector and a bias inductor is required from these outputs to VCC Operation with an external VCO is also possible In this case the loop filter components should be referred to ground The output of the loop filter is connected to the input voltage pin of the external VCO The output of the VCO is brought back into the device on the LOP and LON pins using a balun if necessary A peak
20. 7 Phase Noise vs LO Frequency 10 kHz 1 MHz Steps Rev A Page 14 of 32 SPURIOUS PERFORMANCE ADRF6603 N x fre M x fio spur measurements were made using the standard evaluation board see the Evaluation Board section Mixer spurious products were measured in dB relative to the carrier dBc from the IF output power level All spurious components greater than 125 dBc are shown LO 2280 MHz 2140 MHz horizontal axis is m vertical axis is n and power 0 dBm M 0 1 2 3 4 0 114 35 45 19 36 94 1 20 79 0 0 67 43 52 11 2 58 20 61 95 78 15 85 93 93 10 3 71 79 91 89 67 46 105 88 4 107 79 110 27 107 87 5 107 88 112 41 6 107 71 7 108 62 LO 2540 MHz RF 2400 MHz horizontal axis is m vertical axis is n and power 0 dBm M 0 1 2 3 4 0 113 65 47 04 36 36 1 18 91 0 0 65 01 56 24 2 59 08 60 49 69 27 89 85 94 25 3 77 54 89 56 68 39 109 30 4 108 79 110 65 111 94 5 108 85 111 54 6 108 89 7 LO 2650 MHz RF 2510 MHz horizontal axis is m vertical axis is and power 0 dBm M 0 1 2 3 4 0 111 38 46 57 36 03 1 17 70 0 0 65 70 54 37 2 58 49 75 49 72 27 71 05 95 32 3 81 35 89 18
21. ANALOG 2100 MHz to 2600 MHz Rx Mixer with DEVICES Integrated Fractional N and ADRF6603 FEATURES The PLL can support input reference frequencies from 12 MHz to 160 MHz The PFD output controls a charge pump whose Rx mixer with integrated fractional N PLL output drives an off chip loop filter RF input frequency range 1100 MHz to 3200 MHz Internal LO frequency range 2100 MHz to 2600 MHz The loop filter output is then applied to an integrated VCO The Input P1dB 14 8 dBm VCO output at 2 x fio is applied to an LO divider as well as to a Input IP3 28 5 dBm programmable PLL divider The programmable PLL divider is optimization via external pin controlled by a sigma delta Z A modulator SDM The modulus SSB noise figure of the SDM can be programmed from 1 to 2047 IP3SET pin open 14 3 dB IP3SET pin at 3 3 V 15 6 dB Voltage conversion gain 6 7 dB The active mixer converts the single ended 50 O RF input to a 200 differential IF output The IF output can operate up to 500 MHz Matched 200 IF output impedance IF 3 dB bandwidth 500 MHz The ADRF6603 is fabricated using an advanced silicon germanium Programmable via 3 wire SPI interface BiCMOS process It is available in a 40 lead RoHS compliant 40 lead 6 mm x 6 mm LFCSP 6 mm x 6 mm LFCSP with an exposed paddle Performance is specified over the 40 C to 85 C temperature range APPLICATIONS 1 Cellular base stations Internal L
22. LEN bit to 1 Register 5 Bit DB6 After this procedure is followed the other registers should be programmed in this order Register 7 Register 6 Register 4 Register 3 Register 2 Register 1 Then after a delay of gt 100 ms Register 0 should be programmed Rev A Page 20 of 32 LO SELECTION LOGIC The downconverting mixer in the ADRF6603 can be used without the internal PLL by applying an external differential LO to Pin 37 and Pin 38 LON and LOP In addition when using an LO generated by the internal PLL the LO signal can be accessed directly at these same pins This function can be used for debugging purposes or the internally generated LO can be used as the LO for a separate mixer Table 9 LO Selection Logic ADRF6603 The operation of the LO generation and whether LOP and LON are inputs or outputs are determined by the logic levels applied at Pin 16 EN and Pin 36 EN as well as Bit LDRV and Bit DB6 PLEN in Register 5 The combination of externally applied logic and internal bits required for particular LO functions is given in Table 9 Pins Register 5 Bits Outputs Pin 16 PLL EN Pin 36 LODRV EN Bit DB6 PLEN Bit DB3 LDRV Output Buffer LO 0 X 0 X Disabled External 0 X 1 X Disabled External 1 X 0 X Disabled External 1 0 1 0 Disabled Internal 1 X 1 1 Enabled Internal 1 1 1 X Enabled Internal 1X don t care Rev A Page 21 of 32 ADRF6
23. O 3 dB RFin 1 dB RF GENERAL DESCRIPTION Part No Range Balun Range Balun Range The ADRF6603 is a high dynamic range active mixer with 150 MHZ 300 MNZ integrated phase locked loop PLL voltage controlled 1160 MHz 2500 MHz 1600 MHz oscillator VCO The PLL synthesizer uses a fractional N ADRF6602 1550 MHz 1000 MHz 1350 MHz PLL to generate a fio input to the mixer The reference input 2150 MHz 3100 MHz 2750 MHz can be divided or multiplied and then applied to the PLL phase ADRF6603 2100 MHz 1100 MHz 1450 MHz frequency detector PFD 2600 MHz 3200 MHz 2850 MHz ADRF6604 2500 MHz 1200 MHz 1600 MHz 2900 MHz 3600 MHz 3200 MHz FUNCTIONAL BLOCK DIAGRAM VCC1 VCC LO VCC VCC LO NC NC ADRF6603 LODRV_EN 36 INTERNAL LO RANGE 2100MHz TO 2600MH 3 3V LG DECL3P3 LOP So DECL2P5 PLL EN 16 20 pECLVCO LE THIRD ORDER 26 FRACTIONAL INTERPOLATOR N COUNTER 29 IP3SET 21 TO 123 REFIN ee PHASE FREQUENCY DETECTOR MUXOUT 8 GND RsET CP VTUNE IFP IFN 3 Figure 1 Rev Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A license i
24. O range with frer 80 MHz and frer power 10 dBm 500 V us slew rate with a 40 MHz fero The was computed at 50 kHz offset LOGIC INPUT AND POWER SP ECIFICATIONS Vs 5 Vi ambient temperature Ta 25 C frer 153 6 MHz 38 4 MHz high side LO injection fir 140 MHz optimized using CDAC 0x1 and IP3SET 3 3 V unless otherwise noted Table 4 Parameter Test Conditions Comments Min Typ Max Unit LOGIC INPUTS CLK DATA LE Input High Voltage 1 4 3 3 V Input Low Voltage Vint 0 0 7 V Input Current 0 1 Input Capacitance CiN 5 pF POWER SUPPLIES VCC2 LO MIX 2 pins Voltage Range 4 75 5 5 25 V Supply Current PLL only 97 mA External LO mode internal PLL disabled LO output buffer off IP3SET pin 3 3 V 164 mA Internal LO mode internal PLL enabled IP3SET pin 3 3 V LO output buffer on 274 mA Internal LO mode internal PLL enabled IP3SET pin 3 3 V LO output buffer off 261 mA Power down mode 30 mA Rev A Page 4 of 32 TIMING CHARACTERISTICS VCC2 5 V 5 ADRF6603 Table 5 Parameter Limit Unit Description t 20 ns min LE setup time t 10 ns min DATA to CLK setup time ts 10 ns min DATA to CLK hold time ta 25 ns min CLK high duration ts 25 ns min CLK low duration 10 ns min CLK to LE setup time t 20 ns min LE pulse width Timing Diagram CLK DATA LE athe
25. Output Turned Off IP3SET OPEN IP3SET 3 3V LO FREQUENCY MHz Figure 21 LO Output Amplitude vs LO Frequency TIME ps Figure 22 Frequency Deviation from 2140 MHz vs Time SUPPLY CURRENT mA 08547 121 VPTAT VOLTAGE V 08547 122 Demonstrates LO Frequency Settling Time from 2150 MHz to 2140 MHz Rev A Page 12 of 32 TA 85 25 C 40 2100 2200 2300 2400 2500 2600 LO FREQUENCY MHz Figure 23 VTUNE vs LO Frequency IP3SET OPEN IP3SET 3 3V 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY MHz Figure 24 Supply Current vs LO Frequency IP3SET OPEN IP3SET 3 3V TEMPERATURE C Figure 25 VPTAT Voltage vs Temperature IP3SET Optimized Open 08547 123 08547 124 08547 125 ADRF6603 Complementary cumulative distribution function CCDF fre 2140 MHz 140 MHz 100 100 IP3SET OPEN IP3SET OPEN IP3SET 3 3V 90 IP3SET 3 3V E Ta 85 lt amp s T 25 C 80 lu Ta 40 u 7 9 8 60 8 60 50 a 50 z O 40 2 5 5 30 30 20 2 10 10 0 0
26. R e Odi 2 a eru is 88 TECE gt 0 NA Id 13581 4 A of 2 05 eor N oon 0 255 99 e C rir 0 o VOSA E Cle gt asNas 109 prs sal NOV N 9 528 sop 35 2 13554 iil 8 822 0 2 oat oL e Sou 5 9 _ OT L Cale O oqT saz 499 9 OR nyao 990A gt anew 07 angy INANLA ol a 0 e 3 gs p ACA SNS ei vd 3sNas 81 ISNS os 2 05 2 5 2 S 94 58 Lodi 118 99 lt lt lt F k 8 8 8 99 5 m Figure 50 Evaluation Board Schematic Rev A Page 26 of 32 A02045B REFOUT Figure 51 Evaluation Board Layout Bottom ADRF6603 A02045B Q VTUNE GENE R33 51 lt 9 8 i BE ry 08547 013 Rev A Page 27 of 32
27. Rev A Page 6 of 32 ADRF6603 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 36 LODRV_EN 33 NC 32 NC 31 GND gt t 35 GND 34 VCC LO vc 1 30 GND DECL3P3 2 H INDICATOR 29 IP3SET H 27 2 SET H ADRF6603 26 CHE COMES H N MUXOUT 8 Notto Seale 23 GND DECL2P5 9 22 VCC_MIX VCC210 B 21 GND NOTES 1 NC NO CONNECT 2 THE EXPOSED PADDLE SHOULD BE SOLDERED TO A LOW IMPEDANCE GROUND PLANE Figure 3 Pin Configuration 08547 003 Table 7 Pin Function Descriptions Pin No Mnemonic Description 1 VCC1 Power Supply for the 3 3 V LDO Power supply voltage range is 4 75 V to 5 25 V Each power supply pin should be decoupled with 100 pF capacitor and a 0 1 uF capacitor located close to the pin 2 DECL3P3 Decoupling Node for 3 3 V LDO Connect a 0 1 pF capacitor between this pin and ground 3 CP Charge Pump Output Pin Connect to VTUNE through the loop filter 4 7 11 15 20 GND Ground Connect these pins to a low impedance ground plane 21 23 24 25 28 30 31 35 5 Rset Charge Pump Current The nominal charge pump current can be set to 250 pA 500 uA 750 uA or 1 mA using Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 in Register 4 to 0 internal reference current In this mode no external is required If Bit DB18 is set to 1 the four nominal charge pump currents INowINAL can be externally adjusted according to the
28. UNCTION DESCRIPTIONS 0 80 0 23 0 20REF COPLANARITY SECTION OF THIS DATA SHEET SEATING 0 08 PLANE 0 18 COMPLIANT TO JEDEC STANDARDS MO 220 VJJD 2 Figure 53 40 Lead Lead Frame Chip Scale Package LFCSP_VQ 6 mm x 6 mm Body Very Thin Quad CP 40 1 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADRF6603ACPZ R7 40 C to 85 C 40 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 40 1 ADRF6603 EVALZ Evaluation Board 17 RoHS Compliant Part Rev A Page 29 of 32 ADRF6603 NOTES Rev A Page 30 of 32 ADRF6603 NOTES Rev A Page 31 of 32 ADRF6603 NOTES 2010 Analog Devices Inc All rights reserved Trademarks and AN ALOG registered trademarks are the property of their respective owners D08547 0 11 10 A DEVICES www ana 0 9 Rev A Page 32 of 32
29. cy must be 1x LO This pin has an internal 100 kO pull down resistor 37 38 LON LOP Local Oscillator Input Output The internally generated 1x LO is available on these pins When internal LO generation is disabled an external 1x LO can be applied to these pins 39 VTUNE VCO Control Voltage Input This pin is driven by the output of the loop filter Nominal input voltage range on this pin is 1 5 V to 2 5 V 40 DECLVCO Decoupling Node for VCO LDO Connect a 100 pF capacitor and a 10 uF capacitor between this and ground EPAD Exposed Paddle The exposed paddle should be soldered to a low impedance ground plane Rev A Page 8 of 32 ADRF6603 TYPICAL PERFORMANCE CHARACTERISTICS RF FREQUENCY SWEEP CDAC 0x1 internally generated high side RFin 5 dBm fir 140 MHz unless otherwise noted 5 40 IP3SET OPEN 85 IP3SET OPEN T 85 C 4 IP3SET 3 3V TA 25 C IP3SET 3 3V 425 C T 40 C Ta 40 C 3 35 2 A 1 z 0 lt E O 4 5 25 z 2 3 20 4 5 15 1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460 RF FREQUENCY MHz 1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460 RF FREQUENCY MHz 08547 104 08547 107 Figure 4 Gain vs RF Frequency Figure 7 Input IP3 vs RF
30. ei ted e e SH abus 29 Changes to Programming the ADRF6603 Section 20 Ch nge s to Figure eee tipp 22 Added AC Test Fixture Section and Figure 47 Renumbered Sequentially 23 Changes to Evaluation Board Control Software Section Changes to Figure 48 24 Changes to Figure 49 2425 Changes to Figure 50 0 2 20 2 00 26 1 10 Revision 0 Initial Version Rev A Page 2 of 32 SPECIFICATIONS RF SPECIFICATIONS ADRF6603 Vs 5 ambient temperature Ta 25 C frer 153 6 MHz 38 4 MHz high side LO injection fir 140 MHz optimized using CDAC 0x1 and IP3SET 3 3 V unless otherwise noted Table 2 Parameter Test Conditions Comments Min Typ Max Unit INTERNAL LO FREQUENCY RANGE 2100 2600 MHz RF INPUT FREQUENCY RANGE 3 dB RF input range 1100 3200 MHz RF INPUT AT 2140 MHz Input Return Loss Relative to 50 Q can be improved with external match 20 Input 14 9 dBm Second Order Intercept IIP2 5 dBm each tone 10 MHz spacing between tones 55 3 dBm Third Order Intercept IIP3 5 dBm each tone 10 MHz spacing between tones 29 3 dBm Single Side Band Noise Figure IP3SET 3 3 15 6 dB IP3SET open 14 4 dB LO to IF Leakage At 1x LO frequency 50 O termination at the RF port 43 dBm RF INPUT AT 2400 MHz Input Return Loss Relative to 50 O can be improved with external match 16 Input 14 9 dBm Second Order I
31. en the internal VCO is used the loop filter components should be returned to Pin 40 DECLVCO by installing 0 O resistor in R12 When an external VCO is used the loop filter components can be returned to ground by installing a 0 resistor in R11 R12 0 0402 R11 open 0402 R62 R63 VTUNE Internal vs external VCO When the internal VCO is enabled the loop filter components are R62 0 O 0402 SMA Connector connected directly to the VTUNE pin Pin 39 by installing a 0 Q resistor in R62 To use an R63 open 0402 external VCO R62 should be left open A 0 O resistor should be installed in R63 and the voltage input of the VCO should be connected to the VTUNE SMA connector The output of the VCO is brought back into the PLL via the LO IN OUT SMA connector R2 pin This pin is unused and should be left open R2 open 0402 RFIN SMA Connector RF input The RF input signal should be applied to the RFIN SMA connector The RF input of the ADRF6603 is ac coupled so no bias is necessary R3 R23 open 0402 T3 IF output The differential IF output signals from the ADRF6603 IFP and IFN are converted to a single ended signal by T3 Rev A Page 28 of 32 ADRF6603 OUTLINE DIMENSIONS PIN 1 INDICATOR PIN 1 4 INDICATOR 4 2 4 10 50 95 0 25 MIN 12 MAX 0 80 MAX 0 65 dece d 1 00 LL 0 02 NOM THE PIN CONFIGURATION AND 0 85 0 30 j F
32. following equation TE es x c asta I NOMINAL 6 REF_IN Reference Input Nominal input level is 1 V p p Input range is 12 MHz to 160 MHZ This pin is internally dc biased and should be ac coupled 8 MUXOUT Multiplexer Output This output can be programmed to provide the reference output signal or the lock detect signal The output is selected by programming the appropriate register 9 DECL2P5 Decoupling Node for 2 5 V LDO Connect a 0 1 pF capacitor between this pin and ground 10 VCC2 Power Supply for the 2 5 V LDO Power supply voltage range is 4 75 V to 5 25 V Each power supply pin should be decoupled with 100 pF capacitor and a 0 1 uF capacitor located close to the pin 12 DATA Serial Data Input The serial data input is loaded MSB first the three LSBs are the control bits 13 CLK Serial Clock Input The serial clock input is used to clock in the serial data to the registers The data is latched into the 24 bit shift register on the CLK rising edge Maximum clock frequency is 20 MHz 14 LE Load Enable When the LE input pin goes high the data stored in the shift registers is loaded into one of the eight registers The relevant latch is selected by the three control bits of the 24 bit word 16 PLL EN PLL Enable Switch between internal PLL and external LO input When this pin is logic high the mixer LO is automatically switched to the internal PLL and the internal PLL is powered up When this pin is logic low the internal PLL
33. g mixer with a state of the art fractional N PLL The PLL also integrates a low noise VCO The SPI port allows the user to control the fractional N PLL functions and the mixer optimization functions as well as allowing for an externally applied LO or VCO The mixer core within the ADRF6603 is the next generation of an industry leading family of mixers from Analog Devices Inc The RF input is converted to a current and then mixed down to IF using high performance NPN transistors The mixer output currents are transformed to a differential output The high performance active mixer core results in an exceptional IIP3 and IP1dB with a very low output noise floor for excellent dynamic range Over the specified frequency range the ADRF6603 typically provides IF input P1dB of 14 6 dBm and of 27 dBm Improved performance at specific frequencies can be achieved with the use of the internal capacitor DAC CDAC which is programmable via the SPI port and by using a resistor to a 5 V supply from the IP3SET pin Pin 29 Adjustment of the capacitor DAC allows increments in phase shift at internal nodes in the ADRF6603 thus allowing cancellation of third order distortion with no change in supply current Connecting a resistor to a 5 V supply from the IP3SET pin increases the internal mixer core current thereby improving overall IIP2 and IIP3 as well as IP1dB Using the IP3SET pin for this purpose increases the overall supply current The fracti
34. ixer bias enable and external VCO enable Note that internal calibration for the PLL must be run when the ADRF6603 is initialized at a given frequency This calibration is run automatically whenever Register 0 Register 1 or Register 2 is programmed Because the other registers affect PLL performance Register 0 Register 1 and Register 2 should always be programmed last and in this order Register 0 Register 1 Register 2 To program the frequency of the ADRF6603 the user typically programs only Register 0 Register 1 and Register 2 However if registers other than these are programmed first a short delay should be inserted before programming Register 0 This delay ensures that the VCO band calibration has sufficient time to complete before the final band calibration for Register 0 is initiated Software is available on the ADRF6603 product page under the Evaluation Boards amp Development Kits section that allows easy programming from a PC running Windows XP or Vista INITIALIZATION SEQUENCE To ensure proper power up of the ADRF6603 it is important to reset the PLL circuitry after the VCC supply rail settles to 5 V 0 25 V Resetting the PLL ensures that the internal bias cells are properly configured even under poor supply start up conditions To ensure that the PLL is reset after power up follow this procedure l Disable the PLL by setting the PLEN bit to 0 Register 5 Bit DB6 2 After a delay of 2100 ms set the P
35. luation board for the ADRF6603 This board has four layers and was designed using Rogers 4350 hybrid material to minimize high frequency losses FR4 material is also adequate if the design can accept the slightly higher trace loss of this material The evaluation board is designed to operate using the internal VCO of the device the default configuration or with an external VCO To use an external VCO R62 and R12 should be removed Place 0 Q resistors in R63 and R11 The input of the external VCO should be connected to the VTUNE SMA connector and the external VCO output should be connected to the LO IN OUT SMA connector In addition to these hardware changes internal register settings must also be changed to enable operation with an external VCO see the Register 6 VCO Control VCO Enable Default 0x 1E2106 section Additional configuration options for the evaluation board are described in Table 10 EVALUATION BOARD CONTROL SOFTWARE Software to program the ADRF6603 is available for download on the ADRF6603 product page under the Evaluation Boards amp Development Kits section To install the software 1 Download and extract the zip file ADRF6x0x_3p0p0_XP_install exe file 2 Follow the instructions in the read me file The evaluation board can be connected to the PC using a PC parallel port or a USB port These options are selectable from the opening menu of the software interface see Figure 48 The evaluation board i
36. ntercept IIP2 5 dBm each tone 10 MHz spacing between tones 55 1 dBm Third Order Intercept IIP3 5 dBm each tone 10 MHz spacing between tones 28 6 dBm Single Side Band Noise Figure IP3SET 3 3 V 15 8 dB IP3SET open 14 2 dB LO to IF Leakage At 1x LO frequency 50 O termination at the RF port 43 dBm RF INPUT AT 2650 MHz Input Return Loss Relative to 50 Q can be improved with external match 11 Input 14 7 dBm Second Order Intercept IIP2 5 dBm each tone 10 MHz spacing between tones 52 1 dBm Third Order Intercept IIP3 5 dBm each tone 10 MHz spacing between tones 28 1 dBm Single Side Band Noise Figure IP3SET 3 3 V 15 8 dB IP3SET open 14 5 dB LO to IF Leakage At 1x LO frequency 50 O termination at the RF port 44 dBm IF OUTPUT Voltage Conversion Gain Differential 200 O load 6 7 dB IF Bandwidth Small signal 3 dB bandwidth 500 MHz Output Common Mode Voltage External pull up balun or inductors required 5 V Gain Flatness Over frequency range any 5 MHz 50 MHz 0 2 1 0 dB Gain Variation Over full temperature range 1 2 dB Output Swing Differential 200 O load 2 V p p Differential Output Return Loss Measured through 4 1 balun 15 dB LO INPUT OUTPUT LOP LON Externally applied 1x LO input internal PLL disabled Frequency Range 250 6000 MHz Output Level LO as Output 1x LO into a 50 O load LO output buffer enabled 7 dBm Input Level LO as Input 6 0 6 dBm Input Impedance 50 Rev A Page 3 of 3
37. onal divide function of the PLL allows the frequency multiplication value from REF IN to LO output to be a fractional value rather than be restricted to an integer value as in traditional PLLs In operation this multiplication value is INT FRAC MOD where INT is the integer value FRAC is the fractional value and MOD is the modulus value all programmable via the SPI port In other fractional N PLL designs fractional multiplication is achieved by periodically changing the fractional value in a deterministic way The disadvantage of this approach is often spurious components close to the fundamental signal In the ADRF6603 a Z A modulator is used to distribute the fractional value randomly thus significantly reducing the spurious content due to the fractional function PROGRAMMING THE ADRF6603 The ADRF6603 is programmed via a 3 pin SPI port The timing requirements for the SPI port are shown in Figure 2 Eight pro grammable registers each with 24 bits control the operation of the device The register functions are listed in Table 8 Table 8 ADRF6603 Register Functions Register Function Register 0 Integer divide control for the PLL Register 1 Modulus divide control for the PLL Register 2 Fractional divide control for the PLL Register 3 gt A modulator dither control Register 4 PLL charge pump PFD reference path control Register 5 PLL enable and LO path control Register 6 VCO control and VCO enable Register 7 M
38. s granted by implication or otherwise under any patent or patent rights of Analog Devices Tel 781 329 4700 www analog com Trademarks and registered trademarks are the property of their respective owners Fax 781 461 3113 2010 Analog Devices Inc All rights reserved ADRF6603 TABLE OF CONTENTS Features aS mamay Sua asua a naa 1 Applications 2 enl en e eri eR CURIE 1 General Descriptions sa is a SRE su Disa sas 1 Functional Block Diagram 1 REVISION History uy quyu 2 Sp cifications nte mt tel hs 3 RE Specifications ee ettet ib e 3 Synthesizer PLL Specifications sse 4 Logic Input and Power Specifications 4 Timing Characteristics 0 222 5 Absolute Maximum Ratings esee 6 ESD cette tiet teintes 6 Pin Configuration and Function 7 Typical Performance Characteristics 9 RE Frequency Sweep 9 IE Frequency S Weep REOR ARE 10 Sp rio s Performance 15 Register Structure see ettet tete 16 Register 0 Integer Divide Control Default 0 0001 0 16 Register 1 Modulus Divide Control Default 0x003001 16 Register 2 Fractional Divide Control Default 0x001802 aces siete ivi 17 REVISION HISTORY 11 10 Rev 0 to Rev A Changes to Features and General Description
39. s shipped with a 25 pin parallel port cable for connection to the PC parallel port To connect the evaluation board to a USB port a USB adapter board EVAL ADF4XXXZ USB must be purchased from Analog Devices This board connects to the PC using a standard USB cable with a USB mini connector at one end An additional 25 pin male to 9 pin female adapter is required to mate the ADF4XXXZ USB board to the 9 pin D Sub connector on the ADRF6603 evaluation board ADRF6xxx Device Form ADRF6601 TOR 750 1160MHz ADRF6602 TOR 1550 2150MHz ADRF6603 TOR 2100 2600MHz ADRF6604 TOR 2500 2900MHz ADRF6701 TxMod 750 1160MHz ADRF6702 TxMod 1550 2150MHz OK ADRF6703 TxMod 2100 2600MHz ADRF6704 TxMod 2500 2900MHz ADRF6655 Broadband Up Down Mixer 08547 048 Figure 48 Control Software Opening Menu Figure 49 shows the main menu of the control software with the default settings displayed Rev A Page 24 of 32 ADRF6603 P Analog Devices ADRF 6x0x Software ADRF6603 TOR 2100 2600MHz Device LO Path and Modulator Control RF Section Charge Pump CP Divie Mode Cent Reference Source ntema250 0 Ref Input Frequency 38 4 MHz Curent Multiplier e PFD Frequency 38 4 MHz CP Current uA Modulus 1536 500uA VCO Frequency 2xLO 2400 MHz mum LO Frequency 2400 MHz Charge Pump Control Channel Step Size 25 kHz CP Control Source PFD Phase Offset Multiplier 0 31 E 10 x 22 5 CP
40. uency Including TC1 1 13 Balun LO Output Turned Off CDAC 0x0 IP3SET OPEN 350 300 3 0 RESISTANCE m 250 2 5 amp s M 200 2 0 9 lt z ui 2 150 15 9 oc a CAPACITANCE lt 100 1 0 l 50 0 5 o 0 0 E 2100 2200 2300 2400 2500 2600 50 100 150 200 250 300 350 400 450 500 LO FREQUENCY MHz 8 IF FREQUENCY MHz Figure 15 LO to RF Leakage vs LO Frequency LO Output Turned Off Figure 18 IF Differential Output Impedance R Parallel C Equivalent 0 IP3SET OPEN 5 IP3SET 3 3V 10 amp 5 8 ul 9 20 s 3 25 2 7 lu o 30 2 35 40 45 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 T RF FREQUENCY MHz CW BLOCKER LEVEL dBm 8 Figure 16 RF Input Return Loss vs RF Frequency Figure 19 SSB Noise Figure vs 5 MHz Offset Blocker Level LO Frequency 2105 MHz RF Frequency 1965 MHz Rev A Page 11 of 32 ADRF6603 5 RF TO IF ISOLATION dB 60 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 IP3SET OPEN 85 IP3SET 3 3V 25 TA 40 C LO FREQUENCY MHz VTUNE VOLTAGE V 08547 120 Figure 20 RF to IF Isolation vs RF Frequency High Side LO IF 140 MHz LO OUTPUT AMPLITUDE dBm 12 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 FREQUENCY DEVIATION FROM 2140MHz MHz LO
Download Pdf Manuals
Related Search
ANALOG DEVICES ADRF6603 English products handbook Rev A