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MICROCHIP PIC16C6X 8-Bit CMOS Microcontrollers Manual

1. 25 2 28 Lead Plastic Dual In line 300 mil SP N aN La i N E1 E CANC C Pin No 1 eA Indicator Le eB gt Area e B2 B1 Base Piane NS Seating gt L Plane L Detail A zu et At A2 A B3 B lt D1 Detail A Package Group Plastic Dual In Line PLA Millimeters Typical Typical 4 places 4 places 4 places 4 places Typical Typical Reference Reference Typical Typical Reference Reference 0 584 0 023 1997 Microchip Technology Inc DS30234D page 292 PIC16C6X 25 3 40 Lead Plastic Dual In line 600 mil P N 1 1 ECH Et E SCH Pin No 1 Indicator f T Le Area D Base N Plane N Seating gt x Plane Il E B1 EW do B gt La Di gt Package Group Plastic Dual In Line PLA Millimeters Inches Symbol Min Max Notes Min Max Not
2. N Is 1 Et E de Pin 1 amp Indicator Area Le D HS Y Base T Plane i 7 Seating i 4 t A3 A2 Plane i n M A PD mL iB i Le D1 gt i Package Group Ceramic Side Brazed Dual In Line CER Millimeters Inches Symbol Min Max Notes Min Max Notes a 0 10 0 10 A 3 937 5 030 0 155 0 198 A1 1 016 1 524 0 040 0 060 A2 2 921 3 506 0 115 0 138 A3 1 930 2 388 0 076 0 094 B 0 406 0 508 0 016 0 020 B1 1 219 1 321 Typical 0 048 0 052 C 0 228 0 305 Typical 0 009 0 012 D 35 204 35 916 1 386 1 414 D1 32 893 33 147 Reference 1 295 1 305 E 7 620 8 128 0 300 0 320 E1 7 366 7 620 0 290 0 300 ei 2 413 2 667 Typical 0 095 0 105 eA 7 366 7 874 Reference 0 290 0 310 eB 7 594 8 179 0 299 0 322 L 3 302 4 064 0 130 0 160 N 28 28 28 28 S 1 143 1 397 0 045 0 055 S1 0 533 0 737 0 021 0 029 1997 Microchip Technology Inc DS30234D page 299 PIC16C6X 25 10 28 Lead Plastic Surface Mount SSOP 209 mil Body 5 30 mm SS
3. 100 000 1 000 000 10 000 000 100 000 000 Frequency Hz DS30234D page 178 1997 Microchip Technology Inc PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17 14 MAXIMUM IDD vs FREQUENCY EXTERNAL CLOCK 55 TO 125 C 100 000 1 000 000 10 000 000 100 000 000 Frequency Hz FIGURE 17 15 WDT TIMER TIME OUT FIGURE 17 16 TRANSCONDUCTANCE gm PERIOD vs VDD OF HS OSCILLATOR vs VDD WDT period ms Typ 25 C Min 85 C 4 5 4 VoD Volts VDD Volts 1997 Microchip Technology Inc DS30234D page 179 Data based on matrix samples See first page of this section for details Data based on matrix samples See first page of this section for details PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A Res ee e7 FIGURE 17 17 TRANSCONDUCTANCE gm OF LP OSCILLATOR vs VDD 3
4. Q2 Q4 clk aha aha aka Samples Samples Samples FIGURE 12 5 RX PIN SAMPLING SCHEME BRGH 1 PIC16C63 R63 65 65A R65 RC7 RX DT pin Start Bit Baud clk for all but start bit baud clk First falling edge after RX pin goes low SS Second rising edge X4 clk L_ 2 3 4 Q2 Q4 clk UUUUUUUUUUUUL Samples DS30234D page 110 1997 Microchip Technology Inc PIC16C6X FIGURE 12 6 RX PIN SAMPLING SCHEME BRGH 0 OR 1 PIC16C66 67 Start bit Bito 7 Baud CLK for all but start bit RX RC7 RX DT pin baud CLK x16CLK Samples 1997 Microchip Technology Inc DS30234D page 111 PIC16C6X 12 2 USART Asynchronous Mode Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 In this mode the USART uses standard nonreturn to zero NRZ format one start bit eight or nine data bits and one stop bit The most common data format is 8 bits An on chip dedicated 8 bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator The USART transmits and receives the LSb first The USART s transmitter and receiver are functionally ind
5. Chamfer hx 45 UE Y t D gt A Base Seating Gs d H H Plane Plane A1 A Package Group Plastic SOIC SO Millimeters Inches Symbol Min Max Notes Min Max Notes a 0 8 0 8 A 2 362 2 642 0 093 0 104 A1 0 101 0 300 0 004 0 012 B 0 355 0 483 0 014 0 019 C 0 241 0 318 0 009 0 013 D 17 703 18 085 0 697 0 712 E 7 416 7 595 0 292 0 299 e 1 270 1 270 Typical 0 050 0 050 Typical H 10 007 10 643 0 394 0 419 h 0 381 0 762 0 015 0 030 L 0 406 1 143 0 016 0 045 N 28 28 28 28 CP 0 102 0 004 1997 Microchip Technology Inc DS30234D page 295 PIC16C6X 25 6 18 Lead Ceramic CERDIP Dual In line with Window 300 mil JW SE CANO eA Pin No 1 eB gt Indicator Area ra D Base L PaneN PTS E BE E EEEE Seating gt BW N Y i SS AE M A D i RL Gr A1 A3 A2 B _ La D1 Package Group Ceramic CERDIP Dual In Line CDP Millimeters Inches Symbol Min Max Notes Min Max Notes o 0 10 0 10 A 5 080 0 200 A1 0 381 1 778 0 015 0 070 A2 3 810 4 699 0 150 0 185 A3 3 810 4 445 0 150 0 175 B 0 355 0 585 0 014 0 023 B1 1 270 1 651 Typical 0 050 0 065 Typical C 0 203 0 381 Typical 0 008 0 01
6. TABLE 11 1 REGISTERS ASSOCIATED WITH SPI OPERATION Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR all other BOR Resets OBh 8Bh INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u OCh PIR1 PSPIFZ RCIF TXIF ssPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PsPIEO 9 RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer Transmit Register XXXX XXXX uuuu uuuu 14h SSPCON WCOL ssPov ssPEN ckP Sspm3 Sspm2 SSPM1 SSPMO oooo 0000 0000 0000 85h TRISA PORTA Data Direction Register 11 1111 11 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 94h SSPSTAT D A P S RW UA BF 00 0000 00 0000 Legend x unknown u unchanged unimplemented locations read as 0 Shaded cells are not used by SSP module in SPI mode Note 1 These bits are associated with the USART which is implemented on the PIC16C63 R63 65 65A R65 only 2 PSPIF and PSPIE are reserved on the PIC16C62 62A R62 63 R63 always maintain these bits clear 8 PIR1 6 and PIE1 lt 6 gt are reserved always maintain these bits clear DS30234D page 88 1997 Microchip Technology Inc Applicable Devices 61 62 e2A Re2 63 R63 64 64A R64 65 65A R65 66 67 PIC1 6C6X 11 3
7. PWRT Time out OSC Time out Internal RESET Watchdog Timer RESET I O Pins Note Refer to Figure 18 1 for load conditions TABLE 18 4 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER AND POWER UP TIMER REQUIREMENTS Sym Characteristic No MCLR Pulse Width low VDD 5V 40 C to 85 C Watchdog Timer Time out Period VDD 5V 40 C to 85 C No Prescaler Oscillation Start up Timer Period 1024Tosc TOSC OSC1 period Power up Timer Period 72 VDD 5V 40 C to 85 C 34 Tioz 1 O Hi impedance from MCLR Low 100 ns These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 1997 Microchip Technology Inc DS30234D page 191 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A Re5 66 67 FIGURE 18 5 TIMERO AND TIMER1 EXTERNAL CLOCK TIMINGS lt m RCO T1OSI T1CKI RA4 TOCKI TMRO or TMR1 Note Refer to Figure 18 1 for load conditions TABLE 18 5 TIMERO AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Ty
8. t Note 2 Synchronous Serial Port Note 1 Higher order bits are from the STATUS register 2 PORTD PORTE and the Parallel Slave Port are not available on the PIC16C63 R63 3 Brown out Reset is not available on the PIC16C65 DS30234D page 12 1997 Microchip Technology Inc PIC16C6X FIGURE 3 4 PIC16C66 67 BLOCK DIAGRAM Data Bus EPROM Program Counter G I RAO Program RAI RA2 Memory RAM RA3 ges 8 Level Stack File RA4 TOCKI 13 bit Registers 368 x 8 RA5 SS rogram Bus 1 RAM Adar de 9 R Addr MUX Instruction reg 7 Indirect Direct Addr Addr FSR reg RB7 RB1 RBO INT STATUS reg RCO T1OSO T1CKI RC1 T1OSI CCP2 Power up RC2 CCP1 Timer RC3 SCK SCL i Oscillator RC4 SDI SDA EN Start up Timer RC5 SDO Control Poweron RC6 TX CK Power on Reset RC7 RX DT Timing Watchdog DX Generation Timer OSC1 CLKIN Brown out RDO PSP OSC2 CLKOUT Reset CN l RD2 PSP d RD3 PSP3 RD4 PSP4 MCLR RD5 PSPS5 SE ee pie RDG PSPG Parallel Slave RD7 PSP7 Port Le Vm REO RD RE1 WR Time Timer1 Timer2 t
9. PIC16C65 PIC16C65A PIC16CR65 PIC16C67 22mm mm o2 KSE LdO9 204 6 OdSd 0dY IdSd IdH lt zz edSd cQH llecz dSd QH 1 rvc vas Ias pou 1 sz OQS S94 1 92z TOS MOS EOY as 2d99 ISOIL 19H RB3 RB2 RB1 RBO INT VDD Vss RD7 PSP7 RD6 PSP6 RD5 PSP5 RD4 PSP4 RC7 RB3 RB2 D I RBO INT VDD Vss RD7 PSP7 RD6 PSP6 RD5 PSP5 RD4 PSP4 RC7 RB3 RB2 D I RBO INT VDD Vss RD7 PSP7 RD6 PSP6 RD5 PSP5 RD4 PSP4 RC7 RX DT 1997 Microchip Technology Inc DS30234D page 3 PIC16C6X Table Of Contents 1 0 General Description erter 0 treten pee RE eI rte HERE Ee A dt T EET EENS 5 SD PIC16G6X Device Varieties ue 1 ordrrtdabct ie noce ge rt eot uoc ce ede Edel 7 3 0 Architectural Overview m m ET 4 0 Memory Ormgantzation nennen nente tne treni tns e reete treten enne tns nnr inne inre tee tnit e tenete enne e nnne 5 0 VO POS fist nr a tan Pa dE AT Naa edd ee edd candle ab ene a a en eee 6 0 Overview of Timer Modules 7 0 TimerO Module 12 0 Universal Synchronous Asynchronous Receiver Transmitter USART Module senes 105 13 0 Special Features of the CPU 2t T z 14 0 Instr ction Set SUmffiarys EE 15 0 Developmoent GERGEN ei RE EE A ree o ette HR Hee its 16 0 Electrical Characteristics for PIC16C61 ueesssss 163 17 0 DC and AC Characterist
10. HOU Y 123 S B 4 Lan 5 P s Base plane 7 d KH Seating plane D gt A1 Package Group Plastic SSOP Millimeters Inches Symbol Min Max Notes Min Max Notes a 0 8 0 8 A 1 730 1 990 0 068 0 078 A1 0 050 0 210 0 002 0 008 B 0 250 0 380 0 010 0 015 C 0 130 0 220 0 005 0 009 D 10 070 10 330 0 396 0 407 E 5 200 5 380 0 205 0 212 e 0 650 0 650 Reference 0 026 0 026 Reference H 7 650 7 900 0 301 0 311 L 0 550 0 950 0 022 0 037 N 28 28 28 28 CP 0 102 0 004 DS30234D page 300 1997 Microchip Technology Inc PIC16C6X 25 11 44 Lead Plastic Leaded Chip Carrier Square PLCC 0 812 0 661 N Pics mE gt La 0 177 1 27 032 026 esr Fo i CH 0 177 2 Sid m y E edere UE BC R G Sg Ur H 2 Sides Jas OC Dee SE 1 dd DyEs 0 101 i 4 Do P p Seating 0 38 A PN gt os VAN F B E2 Se AA i 4 EE 0 38 I Le Dias F6 N ES x LT Y Ee 007 ld EO 0 812 0 661 0 254 0 254 PA Ka 010 Max _ 7010 Max NA 032 026 0 508 1524 02m Dua 060 M C L 1 651 1 651 0 64 0 533 0 331
11. Note 2 Synchronous Timero Serial Port Note 1 Higher order bits are from the STATUS register PORTD PORTE and the Parallel Slave Port are not available on the PIC16C62 62A R62 Brown out Reset is not available on the PIC16C62 64 Pin functions T1OSI and T1OSO are swapped on the PIC16C62 64 1997 Microchip Technology Inc DS30234D page 11 PIC16C6X FIGURE 3 3 PIC16C63 R63 65 65A R65 BLOCK DIAGRAM Data Bus EPROM Program Counter I RAO Program RA1 Memory RAM RA2 8 Level Stack RA3 File 4K x 14 13 bit Registers RA4 TOCKI 192x8 RA5 SS rogram Bus 1 RAM Adar de 9 Addr MUX Instruction reg Y Indirect Direct Addr Addr FSR reg RB7 RB1 RBO INT STATUS reg RCO T1OSO T1CKI RC1 T1OSI CCP2 Power up RC2 CCP1 Timer RC3 SCK SCL i Oscillator RC4 SDI SDA VEH Start up Timer RC5 SDO Control Poweron RC6 TX CK Power on Reset RC7 RX DT Timing Watchdog DX Generation Timer OSC1 CLKIN Brown gut OSC2 CLKOUT Reset RDO PSPO RD1 PSP1 RD2 PSP i RD3 PSP3 RD4 PSP4 MCLR RD5 PSP5 iM c picem E RDG PSPG l Parallel Slave RD7 PSP7 Port L REO RD RE1 WR Time Timer1 Timer2
12. 22 3 DC Characteristics PIC16CR63 R65 04 Commercial Industrial PIC16CR63 R65 10 Commercial Industrial PIC16CR63 R65 20 Commercial Industrial PIC16LCR63 R65 04 Commercial Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40C lt TA lt 85 C for industrial and DC CHARACTERISTICS 0 C TA 70 C for commercial Operating voltage VDD range as described in DC spec Section 22 1 and Section 22 2 Param Characteristic Sym Min Typ Max Units Conditions No T Input Low Voltage UO ports VIL D030 with TTL buffer Vss D030A Vss D031 with Schmitt Trigger buffer Vss a D032 MCLR OSC1 in RC mode Vss D033 OSC1 in XT HS and LP Vss Input High Voltage UO ports VIH AN D040 with TTL buffer j VDD 4 5V lt VDD 5 5V D040A or entire VDD range D041 with Schmitt Trigger buffer For entire VDD range D042 MCLR D042A OSC 1 XT HS and LP Note1 DO43 OSC1 in RC mode D070 PORTB weak pull up current VDD 5V VPIN VSS Input Leakage Current Notes 2 3 D060 UO ports Vss lt VPIN lt VDD Pin at hi impedance Vss lt VPIN lt VDD Vss lt VPIN lt VDD XT HS and LP osc configuration D061 MCLR RA4 TOCKI D063 OSC1 Output Low Voltag D080 1 O ports VoL 0 6 V lor 28 5 mA VDD 4 5V 40 C to 85 C D083 0 6 V loL 1 6 mA VDD 4 5V 40
13. D gt ei 1 09 0 0399 Ref k Pin i Pini iL i s e v SEE X eu 0 Min js S E1 TE i s co Ho Ge oum Be Var I d 11 13 4x CT C Ij H Detail B JHHHRLE e el 3 00 0 1189 Ref R1 0 08 Min Option 1 TOP side Option 2 TOP side R 0 08 0 20 i i Gage Plane ums A1 0 250 x A2 A Base Metal Lead Finish i ee deci Detail A B c ie Detail B la 1 00 Ref f y t 1 00 Ref Detail A Detail B Package Group Plastic TQFP Millimeters Inches Symbol Min Max Notes Min Max Notes A 1 00 1 20 0 039 0 047 A1 0 05 0 15 0 002 0 006 A2 0 95 1 05 0 037 0 041 D 11 75 12 25 0 463 0 482 D1 9 90 10 10 0 390 0 398 E 11 75 12 25 0 463 0 482 E1 9 90 10 10 0 390 0 398 L 0 45 0 75 0 018 0 030 e 0 80 BSC 0 031 BSC b 0 30 0 45 0 012 0 018 b1 0 30 0 40 0 012 0 016 C 0 09 0 20 0 004 0 008 c1 0 09 0 16 0 004 0 006 N 44 44 44 44 0 T 0 7 Note 1 Dimensions D1 and E1 do not include mold protrusion Allowable mold protrusion is 0 25m m 0 010 per side D1 and E1 dimensions including mold mismatch 2 Dimension b does not include Dambar protrusion allowable Dambar protrusion shall be 0 08m m 0 003 max 3 This outline conforms to JEDEC MS 026 1997 Microchip Technology Inc DS30234D page 303 PIC16C6X 25 14 Package Marking Information 18 Lead PDIP Example MMMMMMMMMMMMM PI
14. Power up Timer Instruction Oscillator Decode amp Start up Timer Control Power on Reset Timing Watchdog GL Generation Timer OSC1 CLKIN OSC2 CLKOUT TimerO MCLR VDD Vss 4 Note 1 Higher order bits are from the STATUS register DS30234D page 10 1997 Microchip Technology Inc PIC16C6X FIGURE 3 2 PIC16C62 62A R62 64 64A R64 BLOCK DIAGRAM Data Bus RAO RA1 EPROM Program Counter K ROM f Program Memory RAM ie eee 8 Level Stack File 13 bit Registers RA4 TOCKI 128x8 RA5 SS Program Bus 4 RAM Addr 7 9 Addr MUX Instruc i 7 Indirect Direct Addr Addr FSR reg RB7 RB1 RBO INT STATUS reg RCO T1OSO T1CKI 9 RC1 T10SI Power up RC2 CCP1 Timer RC3 SCK SCL i Oscillator RC4 SDI SDA Decode a Start up Timer RC5 SDO Control Power on Reset Timing Watchdog DK Generation Timer OSC1 CLKIN Brown out OSC2 CLKOUT Reset RDO PSPO RD2 PSP2 RD3 PSP3 RD4 PSP4 RD5 PSP5 MCLR VoD Vss RD6 PSP6 RD7 PSP7 Parallel Slave Port REO RD ala rri ESA RE1 WR Timer1 Timer2
15. 171 PIC16C62 Capture Compare PWM A 193 CLKOUT and 1 O ea 190 External Clock we EE Bus Dala 2 25222 eege IC Bus Start Stop Bits sssssssss 196 Oscillator Start up Timer Power p Timer entente Watchdog Timer PIC16C62A Brown out Reset Capture Compare PWM whe CLKOUT and I O nssssssssnssnssnnssnsresinsrnernrrnerneeee External Clock DC Bus Data DC Bus Start Stop Bits Oscillator Start up Timer 207 Power up Timer F 1997 Microchip Technology Inc PIC16C63 Watchdog Timer rene 207 Brown out Heset 239 Capture Compare PWM eee 241 CLKOUT and l O entres 238 External Clock 12C Bus Data ssssenes DC Bus Start Stop Bits 005111111110011111111ei 244 Oscillator Start up Timer SPI Mode Se TimerO essent El e USART Synchronous Receive Master Slave AAA 246 Watchdog Timer 239 PIC16C64 Capture Compare PWM seee 193 CLK OUT and VO one eee en eats 190 External Clock IEN EE DC Bus Start Stop Bits 00511111111001111111eei Oscillator Start up Timer Parallel Slave Port Watchdog Timer PIC16C64A Brown out R656t 4 neni 207 Capture Compare PWM CLKOUT and l O ES External Clock
16. RA4 TOCKI t RCO T1OSO T1CKI TMRO or TMR1 Note Refer to Figure 23 1 for load conditions TABLE 23 5 TIMERO AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typt Max Units Conditions No 40 TtOH TOCKI High Pulse Width No Prescaler 0 5TCY 20 ns Must also meet With Prescaler 10 ns Parameter 42 41 TtOL TOCKI Low Pulse Width No Prescaler 0 5TCY 20 ns Must also meet With Prescaler 10 ns parameter 42 42 TtOP TOCKI Period No Prescaler Tcy 40 ns With Prescaler Greater of ns N prescale value 20 or Tcv 40 2 4 256 N 45 TtH T1CKI High Time Synchronous Prescaler 1 0 5TCY 20 ns Must also meet Synchronous PIC16C6X 15 ns parameter 47 Prescaler PIC16LC6X 25 ns 2 4 8 Asynchronous PIC16C6X 30 ns PIC16LC6X 50 ns 46 TOL T1CKI Low Time Synchronous Prescaler 1 0 5TCY 20 ns Must also meet Synchronous PIC16C6X 15 ns parameter 47 Prescaler PIC16LC6X 25 ns 2 4 8 Asynchronous PIC16C6X 30 ns PIC16LC6X 50 ns 47 TtiP T1CKI input period Synchronous PIC16C6X Greater of ns N prescale value 30 oR TCY 40 1 2 4 8 N PIC16LC6X Greater of N prescale value 50 op TCY 40 1 2 4 8
17. FIGURE 22 10 CC BUS START STOP BITS TIMING Condition Note Refer to Figure 22 1 for load conditions TABLE 22 9 12C BUS START STOP BITS REQUIREMENTS lt Parameter Sym Characteristic Conditions No 90 Tsu sTA START condition 100 kHz mode ly relevant for repeated START Setup time 400 kHz mode Klon 91 THD STA START condition 100 kHz mode After this period the first clock Hold time 400 kHz mode pulse is generated EEN Tsu sTO STOP condition 100 kHz mode Setup time 400 kHz mode 93 THD STO STOP condition 100 kHz mode Hold time 400 kHz These parameters are characterized but not teste V YY DS30234D page 260 Preliminary 1997 Microchip Technology Inc PIC16C6X 65A R65 61 62 62A R62 63 R63 R64 65 66 67 Applicable Devices FIGURE 22 11 12C BUS DATA TIMING SDA Out Note Refer to Figure 22 1 for load conditions TABLE 22 10 I C BUS DATA REQUIREMENTS Parameter Sym Characteristic Min Max Units Sonditions No 100 THIGH Clock high time 100 kHz mode 4 0 must operate at a min um of 1 5 MHz 400 kHz mode 0 6 S Device must operate at a min imum of 10 MHz SSP Module 1 N 101 TLow Clock low time 100 kHz mode us Device must operate at a
18. the external clock to meet the sampling requirement the ripple counter must be taken into account There fore it is necessary for TOCKI to have a period of at least 4Tosc and a small RC delay of 40 ns divided by the prescaler value The only requirement on TOCKI high and low time is that they do not violate the mini When an external clock input is used for TimerO it must meet certain requirements The requirements ensure the external clock can be synchronized with the internal phase clock TOSC Also there is a delay in the actual incrementing of TimerO after synchronization 724 EXTERNAL CLOCK SYNCHRONIZATION mum pulse width requirement of 10 ns Refer to param eters 40 41 and 42 in the electrical specification of the When no prescaler is used the external clock input is desired device the same as the prescaler output The synchronization of TOCKI with the internal phase clocks is accom plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks Figure 7 5 Therefore it is necessary for TOCKI to be high for at least 2Tosc and a small RC delay of 20 ns and low for at least 2Tosc and a small RC delay of 20 ns Refer to the electrical specification of the desired device 7 2 2 TIMERO INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks there is a small delay from the time the external clock edge occurs to the time the TimerO mod
19. 130 Power down bit Power down Mode enn Power on Reset DOP Power on Reset Status bit POR Power up Timer PWRT seen PR ise tr REGGIO IR DERE Pr Scaler mem Prescaler Assignment bit PSA Prescaler Rate Select bits PS2 PSO assesseer 36 PRO MATE Universal Programmer sess 159 Program Memory Programming While In circuit 142 PS2 PS0 PWM Block Diagram eene 80 Galculations teret Reine 81 Output TIMING enai a a 80 PWM Least Significant bits 78 Q Quadrat re Clock8 oen rine nri Int 18 Quick Turnaround Production Y R EUM Bib eite ee 84 89 96 100 101 102 RAO DIET nda serment nation Garon 51 HAT pin 51 RA2 pin 51 RAS pin 51 RA4 TOCKI pin 51 RAS In EE 51 RB Port Change Interrupt Enable bit RBIE 37 RB Port Change Interrupt Flag bit RBIF RBO INT irr tritt rtt mter niet RBO INT External Interrupt Enable bit INTE 37 RBO INT External Interrupt Flag bit INTF RCREQG nein bene cete 24 26 28 30 32 34 24 26 28 30 32 34 106 RCV MODE Read Only Memory sseseesesieesieeieiseieierisieinrsiesieriernriernes 7 Read Write bit Information R W 84 89 Receive and Control Register 106 Receiv
20. Note 1 Instruction cycle period TCY equals four times the input oscillator time base period All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code Exceeding these specified limits may result in an unstable oscillator operation and or higher than expected current con sumption All devices are tested to operate at min values with an external clock applied to the OSC1 CLKIN pin When an external clock input is used the Max cycle time limit is DC no clock for all devices 1997 Microchip Technology Inc Preliminary DS30234D page 253 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22 3 CLKOUT AND I O TIMING Q4 CLKOUT UO Pin input UO Pin output old value Note Refer to Figure 22 1 for load conditions TABLE 22 3 CLKOUT AND I O TIMING REQUIREMENTS Zeg Param Sym Characteristic Rt Max Units Conditions No 10 TosH2ckL OSC1T to CLKOUTL 75 200 ns Note 1 11 TosH2ckH OSC1T to CLKOUTT 75 200 ns Note 1 12 TckR CLKOUT rise time 35 100 ns Note 1 13 TckF CLKOUT fall time 35 100 ns Note 1 14 TckL2ioV CLKOUT J to Port out valid 0 5TCY 20 ns Note 1 15 TioV2ckH Port in valid
21. SDO E ou X ml mi bite X bis X bt X bu X bio X SDI SMP 0 lt 4 DK SLE 1997 Microchip Technology Inc DS30234D page 93 Applicable Devices PIC1 6C6X 61 62 e2A Re2 63 R63 64164A Re4 65 65A R65 66 67 FIGURE 11 13 SPI MODE TIMING SLAVE MODE WITH CKE 1 PIC16C66 67 SS not optional SCK CKP 0 SCK CKP 1 SDI SMP 0 2 gt S gt SSPIF TABLE 11 2 REGISTERS ASSOCIATED WITH SPI OPERATION PIC16C66 67 Value on Value on all Power on other resets Reset OBh 8Bh INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u 10Bh 18Bh OCh PIR1 PsPIF D 2 RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PsPIED 2 RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer Transmit Register XXXX XXXX uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO 0000 0000 0000 0000 85h TRISA PORTA Data Direction register Em LL elt 3111 87h TRISC PORTC Data Direction register 1111 1111 1111 1111 94h SSPSTAT SMP CKE D A P S R W UA BF 0000 0000 0000 0000 Legend x unknown u unchanged unimplemented locati
22. sise 55 C to 85 C Storage temp rature iioi dete perio teo e EE Lp ee rente 65 C to 150 C Voltage on any pin with respect to Vss except VDD MCLR and RAM ssssseee 0 3V to VDD 0 3V Voltage on VDD with respect to VSS issues 0 3V to 7 5V Voltage on MCLR with respect to VSS Note 21 OV to 14V Voltage on RA4 with respect to VSS dette eee pie ces GE teeter a Gn lee OV to 14V Total power dissipation Note Re EE ee Ee 1 0W Maximum current out of Vss pin Maximum current into VDD plris 25 dein Mek ot o thee te ni I per eere RE ree Hr ee Input clamp current IK VI lt 0 or VI gt MDDI Output clamp current lok VO lt 0 or Vo gt VDD Maximum output current sunk by any I O in Maximum output current sourced by any I O pin sisi Maximum current sunk by PORTA PORTB and PORTE combined Maximum current sourced by PORTA PORTB and PORTE combined Maximum current sunk by PORTC and PORTD combined ss Maximum current sourced by PORTC and PORTD eombined ss Note 1 Power dissipation is calculated as follows Pdis VDD x IDD Y loH Y VDD VOH x lOH Y Vol x IOL Note 2 Voltage spikes below Vss at the MCLR pin inducing currents greater than 80 mA may cause latch up Thus a series resistor of 50 1000 should be used when applying a low level to the MCLR pin rather than pulling this pin directly to Vss T NOTICE Stresses above those lis
23. Value on Value on Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit 1 Bit 0 POR all other BOR Resets DCH PIR1 PSPIF 2 RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 00x 0000 00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE 0 RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 0000 010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend x unknown unimplemented locations read as 0 Shaded cells are not used for Synchronous Master Reception Note 1 PSPIF and PSPIE are reserved on the PIC16C63 R63 66 always maintain these bits clear 2 PIR1 lt 6 gt and PIE1 lt 6 gt are reserved always maintain these bits clear DS30234D page 118 1997 Microchip Technology Inc PIC16C6X FIGURE 12 14 SYNCHRONOUS RECEPTION MASTER MODE SREN calasfadar aciadadar acjaglaslar aalag adarlazlaslaslarjazjag Giele a4 arjaz as ospioejasjo blazlasjas lo o3ado RC7 RX DT pin XX bito Du D SKC bits XK Di wv D x bite lt _bit7 RC6 TX CK pin E Write to bit SREN SREN bit CREN bit H RCIF bit i I i i i i i interrupt i i i i i C Read RXREG Note Timing diagr
24. Unimplemented x unknown u unchanged q value depends on condition unimplemented location read as O Shaded locations are unimplemented read as 0 These registers can be addressed from either bank The upper byte of the Program Counter PC is not directly accessible PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter PC lt 12 8 gt Other non power up resets include external reset through MCLR and the Watchdog Timer reset The BOR bit is reserved on the PIC16C64 always maintain this bit set The IRP and RP1 bits are reserved on the PIC16C64 64A R64 always maintain these bits clear PIE1 lt 6 gt and PIR1 lt 6 gt are reserved on the PIC16C64 64A R64 always maintain these bits clear DS30234D page 28 1997 Microchip Technology Inc PIC16C6X TABLE 4 4 SPECIAL FUNCTION REGISTERS FOR THE PIC16C64 64A R64 Cont d Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR all other BOR resets Bank 1 son INDF Addressing this location uses contents of FSR to address data memory not a physical register 0000 0000 0000 0000 81h OPTION RBPU INTEDG TOCS TOSE PSA PS2 PS1 PSO 111 111 1111 1111 82n PCL Program Counter s PC Least Significant Byte 00
25. Parameter Sym Characteristic Min Typ Max Units Conditions No 90 TSU STA START condition 100 kHz mode 4700 Only relevant for repeated START Setup time 400 kHz mode 600 condition 91 THD STA START condition 100 kHz mode 4000 ns After this period the first clock Hold time 400 kHz mode 600 pulse is generated EEN Tsu sTO STOP condition 100 kHz mode 4700 ge Setup time 400 kHz mode 600 93 THD STO STOP condition 100 kHz mode 4000 e Hold time 400 kHz mode 600 D These parameters are characterized but not tested DS30234D page 244 1997 Microchip Technology Inc PIC16C6X SDA Out Applicable Devices 61 62 62A R62 63 R63 R64 65 66 67 65A Re5 FIGURE 21 11 CC BUS DATA TIMING Note Refer to Figure 21 1 for load conditions TABLE 21 10 I C BUS DATA REQUIREMENTS Parameter Sym Characteristic Min Max Units Conditions No 100 THIGH Clock high time 100 kHz mode 4 0 Ge us Device must operate at a min imum of 1 5 MHz 400 kHz mode 0 6 us Device must operate at a min imum of 10 MHz SSP Module 1 5TCY 101 TLow Clock low time 100 kHz mode 4 7 us Device must operate at a min imum of 1 5 MHz 400 kHz mode
26. These parameters are characterized but not tested T Datain Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 In RC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC16C6X be driven with external clock in RC mode 2 The leakage current on the MCLR VPP pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input volt ages 3 Negative current is defined as current sourced by the pin 1997 Microchip Technology Inc DS30234D page 235 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R6566 67 21 4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats 1 TppS2ppS 3 TCC ST IC specifications only 2 TppS 4 Ts EC specifications only T F Frequency T Time Lowercase letters pp and their meanings pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs cs rw RD or WR di SDI sc SCK do SDO ss ss dt Data in tO TOCKI io UO port ti T1CKI mc MCLR wr WR Uppercase letters and their meanings F Fall P Period H High R Rise Invalid Hi impedance V Valid L Low Z Hi impedance PC only AA output access High High BUF B
27. Device in Brown out Reset D 4 5 5 0 5 5 6 0 Vpp Volts 3 5 The shaded region represents the built in hysteresis of the 4 0 4 5 brown out reset circuitry Vpp Volts FIGURE 24 9 MAXIMUM IPD vs VDD BROWN OUT DETECT FIGURE 24 11 MAXIMUM IPD vs TIMER1 ENABLED ENABLED 85 C TO 40 C RC MODE 32 kHz RCO RC1 z 33 pF 33 pF 85 C TO 40 C RC MODE Device NOT in Brown out Reset Device in Brown out Reset 3 5 4 0 4 5 5 0 5 5 6 0 Vop Volts The shaded region represents the built in hysteresis of the S 3 5 4 0 4 5 brown out reset circuitry Vpp Volts 1997 Microchip Technology Inc DS30234D page 283 Data based on matrix samples See first page of this section for details Data based on matrix samples See first page of this section for details PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A Re5 66 67 FIGURE 24 12 TYPICAL IDD vs FREQUENCY RC MODE 22 pF 25 C 1 GE H D 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 Frequency MHz Shaded area is beyond recommended range FIGURE 24 13 MAXIMUM IDD vs FREQUENCY RC MODE 22 pF 40 C TO 85 C ud H G GE H
28. Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt TA lt 125 C for extended 40 C lt Ta lt 85 C for industrial and DC CHARACTERISTICS DC TA 70 C for commercial Operating voltage VDD range as described in DC spec Section 16 1 and Section 16 2 Param Characteristic Sym Min Typf Max Units Conditions No Input Low Voltage I O ports VIL D030 with TTL buffer Vss 0 15VpD V For entire VDD range D030A Vss 0 8V V 4 5V lt VDD 5 5V D031 with Schmitt Trigger buffer Vss 0 2VbD V D032 MCLR OSC1 in RC mode Vss 0 2VoD V D033 OSC1 in XT HS and LP Vss 0 3VoD V Note Input High Voltage IO ports VIH D040 with TTL buffer 2 0 VDD V 4 5V VDD 5 5V D040A 0 25VDD VDD V For entire VDD range 0 8V D041 with Schmitt Trigger buffer 0 85VDD VDD V For entire VoD range D042 MCLR 0 85VDD VDD V D042A OSC1 XT HS and LP 0 7VDD VDD V Note D043 OSC1 in RC mode 0 9VDD VDD V D070 PORTB weak pull up current IPURB 50 250 400 uA VDD 5V VPIN VSS Input Leakage Current Notes 2 3 D060 1 O ports liL 1 uA Vss VPIN VDD Pin at hi impedance D061 MCLR RA4 TOCKI 5 uA Vss VPIN lt VDD D063 OSC1 5 uA Vss VPIN lt VDD XT HS and LP osc configuration Output Low Voltage D080 1 O ports VoL 0 6 V oL 8 5 mA VDD 4 5V 40 C to 85 C D080A 0 6 V loi 7 0 mA VDD 4 5V 40 C
29. Note 2 Synchronous Serial Port Note 1 Higher order bits are from the STATUS register 2 PORTD PORTE and the Parallel Slave Port are not available on the PIC16C66 1997 Microchip Technology Inc DS30234D page 13 PIC16C6X TABLE 3 1 PIC16C61 PINOUT DESCRIPTION Pin Name Suit Se Pin Type pd Description OSC1 CLKIN 16 16 ST CMOS Oscillator crystal input external clock source input OSC2 CLKOUT 15 15 O Oscillator crystal output Connects to crystal or resonator in crystal oscillator mode In RC mode the pin outputs CLKOUT which has 1 4 the frequency of OSC1 and denotes the instruction cycle rate MGLR VPP 4 4 VP ST Master clear reset input or programming voltage input This pin is an active low reset to the device PORTA is a bi directional UO port RAO 17 17 UO TTL RA1 18 18 UO TTL RA2 1 1 UO TTL RA3 2 2 UO TTL RA4 TOCKI 3 3 UO ST RA4 can also be the clock input to the TimerO timer counter Output is open drain type PORTB is a bi directional UO port PORTB can be software pro grammed for internal weak pull up on all inputs RBO INT 6 6 y o TTL sT RBO can also be the external interrupt pin RB1 7 7 1 0 TTL RB2 8 8 UO TTL RB3 9 9 UO TTL RB4 10 10 UO TTL Interrupt on change pin RB5 11 11 y o TTL Interrupt on change pin RB6 12 12 UO TTL sT Interrupt on change pin Serial programming clock RB7 13 13 UO TTL sT Inter
30. value on Value on all Address Name Bit7 Bit6 Bit5 Bit 4 Bit3 Bit2 Bit 1 Bit 0 POR other resets BOR 08h PORTD PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSPO xxxx xxxx uuuu uuuu 09h PORTE RE2 RE1 REO xxx uuu 89h TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits 0000 111 0000 111 DCH PIR1 PsPIF 0 RcIF TxiF SSPIF CCP1IF TMR2IF TRM1IF 0000 0000 0000 0000 8Ch PIE1 PsPIE 0 RcIEO TXIE SSPIE CCP1IE TMR2IE TMRIIE 0000 0000 0000 0000 Legend x unknown u unchanged unimplemented locations read as 0 Shaded cells are not used by the PSP Note 1 These bits are reserved always maintain these bits clear 2 These bits are implemented on the PIC16C65 65A R65 67 only DS30234D page 62 1997 Microchip Technology Inc PIC16C6X 6 0 OVERVIEW OF TIMER MODULES Applicable Devices 61162 62A R62 63 R63 64 64A R64 65 65A R65 66 67 All PIC16C6X devices have three timer modules except for the PIC16C61 which has one timer module Each module can generate an interrupt to indicate that an event has occurred i e timer overflow Each of these modules are detailed in the following sections The timer modules are e TimerO module Section 7 0 e Timer1 module Section 8 0 Timer2 module Section 9 0 6 1 TimerO Overview Applicable Devices 61 62 62A R62 63 R63 64 64A R64165 65A Gelee 67 The TimerO module is a
31. RE2 RE1 REO xxx uuu 89h TRISE IBF OBF IBOV PSPMODE _ PORTE Data Direction Bits 0000 111 0000 111 Legend x unknown u unchanged unimplemented locations read as 0 Shaded cells not used by PORTE 1997 Microchip Technology Inc DS30234D page 59 PIC16C6X 5 6 UO Programming Considerations EXAMPLE 5 4 READ MODIFY WRITE Applicable Devices INSTRUCTIONS ON AN e1 e2 e2A Re2 es Res e4 e4A Re4 es e5A Res5 s6 e7 UO PORT 5 6 1 BI DIRECTIONAL UO PORTS Initial PORT settings PORTB lt 7 4 gt Inputs E PORTB lt 3 0 gt Outputs Any instruction which writes operates internally as a PORTB 7 6 have external pull ups and are read followed by a write operation The BCF and BSF not connected to other circuitry instructions for example read the register into the i CPU execute the bit operation and write the result back to the register Caution must be used when these instructions are applied to a port with both inputs and BCF PORTB 7 BCF PORTB 6 outputs defined For example a BSF operation on bit5 BSF STATUS RPO of PORTB will cause all eight bits of PORTB to be read BCF TRISB 7 10pp pppp 1lpp pppp into the CPU Then the BSF operation takes place on BCF TRISB 6 10pp pppp 10pp pppp bits and PORTB is written to the output latches If another bit of PORTB is used as a bi directional I O pin Note that the user may have expected th
32. 87 SPI Oe EE 86 Synchronous Serial Port Enable bit SSPEN 85 90 Synchronous Serial Port Interrupt Enable bit SSPIE 38 Synchronous Serial Port Interrupt Flag bit SSPIF 41 Synchronous Serial Port Mode Select bits SSPM3 SSPMO EE 85 90 Synchronous Serial Port Module 83 Synchronous Serial Port Status Register 89 T TOC S EE 36 TOIE 97 TOIF 97 TE EE 96 T1CKPS1 T1CKPSO sse 71 TH CON EE 34 T1OSCEN 71 TISYNG fica dese caters 71 T2CKPS1 T2CKPSO T2CON 24 26 28 30 32 34 75 Blue 130 Titnig OUE e EE 35 Time out Sequence oe eee eset eeseeteeeeetaeteeeeaeeeeeaeeneeeatens 130 Timer Modules Overview all 63 TimerO Block Diagram eene 65 Counter Mode incer EE rg 65 External Clock wi eot aie pe ie ttt 67 Interrupt EN OVOTVIQW 25 Hein vo ee ree Or ene 63 Prescalar oe oce etie Set 68 Section 3 Timer Mode AA 65 Timing DiagramTiiming Diagrams TIM ce cn tr cde RE ERR RHET 65 TMRO register 65 Timer1 Block Diagram esee 72 Capacitor Selection 73 Counter Mode Asynchronous 73 Counter Mode Synchronous 72 External Clock 73 Oscillator esses 73 1997 Microchip Technology Inc PIC16C6X MEEN
33. All instructions are single cycle except for any program branches These take two cycles since the fetch instruction is flushed from the pipeline while the new instruction is being fetched and then executed DS30234D page 18 1997 Microchip Technology Inc PIC16C6X 4 0 MEMORY ORGANIZATION FIGURE 4 2 PIC16C62 62A R62 64 64A Applicable Devices R64 PROGRAM MEMORY