ANALOG DEVICES ADL5353 English products handbook Rev 0
Contents
1. 220 210 t E 200 E a g N 190 gt 5 gt a 480 2 o 170 160 7 10 e 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 2 65 2 70 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 2 65 2 70 9 RF FREQUENCY GHz amp RF FREQUENCY GHz S Figure 3 Supply Current vs RF Frequency Figure 6 Input IP2 vs RF Frequency 12 14 ii 12 T 10 kJ z amp E kJ eo m 8 o 2 E 6 ui amp 6 8 8 4 d 2 6 x 0 5 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 2 65 2 70 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 2 65 2 70 RF FREQUENCY GHz E RF FREQUENCY GHz 5 Figure 4 Power Conversion Gain vs RF Frequency Figure 7 Input P1dB vs RF Frequency 28 12 26 11 Tas 85 C 24 S 2 2 u 0 T4 25 C E S 20 o a m 9 Ta 40 C E 18 7 5 E SS o zZ z 16 a 8 o o 14 7 12 10 6 2 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 2 65 2 70 9 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 265 2 70 RF FREQUENCY GHz E RF FREQUENCY GHz 5 Figure 5 Input IP3 vs RF Frequency Figure 8 SSB Noise Figure vs RF Frequency Rev 0 Page 7 of 24 ADL5353 V 25V I 190 mA T 25 C fg 2535 MHz f o 2738 MHz LO power 0 dBm R9 1 1 kQ R14 910 Q VGS0 VGSI 0 V and Zo 50 Q unless otherwise noted 52 51 50 25 Vg 5 25V2. 138 136 Ta 40 C T 134 E D z E D 132 z i c TA 25 C a 2 amp S 10 5 z z 5 a 128 126 Ta 85 C 124 30 2 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 260 265 2 70 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 265 2 70 RF FREQUENCY GHz amp RF FREQUENCY GHz amp Figure 44 Supply Current vs RF Frequency at 3 3 V Figure 47 Input IP2 vs RF Frequency at 3 3 V 12 9 Tas 85 C TA 25 C 8 11 7 a 5 Tas 40 C z 10 6 S T4 25 C m 5 Ta 40 C 9 o 9 2 TA 85 C p 4 ul amp S s Z 3 bei o 2 7 1 6 e 0 2 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 2 65 2 70 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 265 2 70 RF FREQUENCY GHz S RF FREQUENCY GHz B Figure 45 Power Conversion Gain vs RF Frequency at 3 3 V Figure 48 Input P1dB vs RF Frequency at 3 3 V 24 14 22 13 Ta 40 C 12 20 d a ur Ta 85 C E Bon E a s g Ta 85 C u i BW o 0 Ty 425 C 5 16 TA 25 C a a o z z 9 a 14 9 8 12 7 TA 40 C 10 6 2 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 2 65 2 70 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 265 2 70 RF FREQUENCY GHz S RF FREQUENCY GHz E Figure 46 Input IP3 vs RF Frequency at 3 3 V Figure 49 SSB Noise Figure vs RF Frequency at 3 3 V Rev 0 Page 14 of 24 SPUR TABLES SPUR TABLES All
3. 220 210 200 zs E 5 N 190 2 5 gt Q amp 180 2 o 170 160 o 2 30 80 130 180 230 280 330 380 430 5 30 80 130 180 230 280 330 380 430 amp IF FREQUENCY MHz S IF FREQUENCY MHz S Figure 15 Supply Current vs IF Frequency Figure 18 Input IP2 vs IF Frequency H z E E z o m Z S 9 E t 5 u a Z Z o o 30 80 130 180 230 280 330 380 430 30 80 130 180 230 280 330 380 430 amp IF FREQUENCY MHz E IF FREQUENCY MHz amp Figure 16 Power Conversion Gain vs IF Frequency Figure 19 Input P1dB vs IF Frequency 30 11 0 28 10 5 26 Ey D ET 10 0 E A w D S 24 8 g amp E as 5 22 TA 85 C o z T4 425 C m 9 0 20 EI 18 8 5 16 amp 8 0 g 30 80 130 180 230 280 330 380 430 amp 30 80 130 180 230 280 330 380 430 ki IF FREQUENCY MHz S IF FREQUENCY MHz S Figure 17 Input IP3 vs IF Frequency Figure 20 SSB Noise Figure vs IF Frequency Rev 0 Page 9 of 24 ADL5353 V 2 5 V I 190 mA T 25 C f 2535 MHz f 2738 MHz LO power 0 dBm R9 1 1 kQ R14 910 Q VGS0 VGSI 0 V and Z 50 Q unless otherwise noted T Ki z E KE z o e o n tc
4. 48 47 Vs 5 00V SUPPLY CURRENT mA INPUT IP2 dBm 46 Vg 4 75V 45 44 40 20 0 20 40 60 80 TEMPERATURE C 40 20 0 20 40 60 80 TEMPERATURE C 09117 009 09117 012 Figure 9 Supply Current vs Temperature Figure 12 Input IP2 vs Temperature Vg 5 25V Vg 4 75V Vs 5 00V INPUT P1dB dBm o CONVERSION GAIN dB L40 20 0 20 40 60 80 TEMPERATURE C 40 20 0 20 40 60 80 TEMPERATURE C 09117 010 09117 013 Figure 10 Power Conversion Gain vs Temperature Figure 13 Input P1dB vs Temperature Vg 5 25V Vg 4 75V INPUT IP3 dBm 8 5 I Vg 5 00V SSB NOISE FIGURE dB a 7 5 7 0 40 20 0 20 40 60 an 40 30 20 10 0 10 20 30 40 50 60 70 80 E TEMPERATURE C B TEMPERATURE C 5 Figure 11 Input IP3 vs Temperature Figure 14 SSB Noise Figure vs Temperature Rev 0 Page 8 of 24 ADL5353 V 5 V I 190 mA T 25 C bn 2535 MHz f o 2738 MHz LO power 0 dBm R9 1 1 KQ R14 910 Q VGS0 VGSI 0 V and Z 50 Q unless otherwise noted
5. M 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 20 2 45 0 1 36 9 0 00 57 7 66 5 2 81 7 74 3 63 7 81 9 3 100 97 9 69 2 100 4 lt 100 100 100 100 5 100 100 100 lt 100 6 100 100 100 100 7 100 100 100 100 100 8 100 100 100 100 100 9 100 100 100 100 100 10 100 100 100 100 100 11 lt 100 100 100 100 12 100 100 100 100 13 100 100 100 100 14 100 100 100 15 100 100 Rev 0 Page 15 of 24 CIRCUIT DESCRIPTION The ADL5353 consists of two primary components the radio frequency RF subsystem and the local oscillator LO subsystem The combination of design process and packaging technology allows the functions of these subsystems to be integrated into a single die using mature packaging and interconnection technolo gies to provide a high performance low cost design with excellent electrical mechanical and thermal properties In addition the need for external components is minimized thereby optimizing cost and size The RF subsystem consists of an integrated low loss RF balun passive MOSFET mixer sum termination network and IF amplifier The LO subsystem consists of an SPDT terminated FET switch and a three stage limiting LO amplifier The purpose of the LO subsystem is to provide a large fixed amplitude balanced signal to
6. NOTES 1 NC NO CONNECT 2 EXPOSED PAD MUST BE SOLDERED TO GROUND 09117 002 Figure 2 Pin Configuration Table 6 Pin Function Descriptions Pin No Mnemonic Description 1 VPIF Positive Supply Voltage for IF Amplifier 2 RFIN RF Input Must be ac coupled 3 RFCT RF Balun Center Tap AC Ground 4 5 COMM Device Common DC Ground 6 8 VLO3 VLO2 Positive Supply Voltages for LO Amplifier 7 LGM3 LO Amplifier Bias Control 9 LOSW LO Switch LOI1 selected for 0 V and LOI2 selected for 3 V 10 NC No Connect 11 15 LOI1 LOI2 LO Inputs Must be ac coupled 12 13 VGSO VGS1 Mixer Gate Bias Controls 3 V logic Ground these pins for nominal setting 14 VPSW Positive Supply Voltage for LO Switch 16 LEXT IF Return This pin must be grounded 17 PWDN Power Down Connect this pin to ground for normal operation and connect this pin to 3 0 V for disable mode 18 19 IFON IFOP Differential IF Outputs Open Collectors Each requires an external dc bias 20 IFGM IF Amplifier Bias Control EPAD EP Exposed Pad The exposed pad must be soldered to ground Rev 0 Page 6 of 24 ADL5353 TYPICAL PERFORMANCE CHARACTERISTICS 5 V PERFORMANCE V 2 5 V I 190 mA T 25 C f 2535 MHz f o 2738 MHz LO power 0 dBm R9 1 1 KO R14 910 Q VGSO VGSI 0 V and Zo 50 Q unless otherwise noted
7. Table 2 Parameter Test Conditions Comments Min Typ Max Unit RF INPUT INTERFACE Return Loss Tunable to gt 20 dB over a limited bandwidth 18 dB Input Impedance 50 Q RF Frequency Range 2200 2700 MHz OUTPUT INTERFACE Output Impedance Differential impedance f 200 MHz 230 1 5 Q pF IF Frequency Range 30 450 MHz DC Bias Voltage Externally generated 3 3 5 0 5 5 V LO INTERFACE LO Power 6 0 10 dBm Return Loss 15 dB Input Impedance 50 Q LO Frequency Range 2230 3150 MHz POWER DOWN PWDN INTERFACE PWDN Threshold 1 0 V Logic 0 Level 0 4 V Logic 1 Level 1 4 V PWDN Response Time Device enabled IF output to 9096 of its final level 160 ns Device disabled supply current 5 mA 220 ns PWDN Input Bias Current Device enabled 0 0 yA Device disabled 70 yA 1 Apply the supply voltage from the external circuit through the choke inductors 2 The power down function is intended for use with V lt 3 6 V only Rev 0 Page 3 of 24 ADL5353 RF Dynamic Performance V 5 V I 190 mA T 25 C frp 2535 MHz fio 2738 MHz LO power 0 dBm VGS0 VGSI 0 V and Zo 50 Q unless otherwise noted Table 3 Parameter Test Conditions Comments Min Typ Max Unit DYNAMIC PERFORMANCE Power Conversion Gain Including 4 1 IF port transformer and PCB loss 8 7 dB Voltage Conversion Gain Zsource 50 O differential Z 5 5 200 Q differential 14 7 dB SSB Noise Figure 9 8 dB Input Third Order Intercept IIP3 fre
8. 2534 5 MHz fre 2535 5 MHz fio 2738 MHz each RF 21 24 5 dBm tone at 10 dBm Input Second Order Intercept IIP2 fkr 2535 MHZ fer 2585 MHz fiy 2738 MHz each RF tone 47 5 dBm at 10 dBm Input 1 dB Compression Point IP1dB 10 4 dBm LO to IF Leakage Unfiltered IF output 15 dBm LO to RF Leakage 38 dBm RF to IF Isolation 28 dBc IF 2 Spurious 10 dBm input power 70 dBc IF 3 Spurious 10 dBm input power 78 dBc POWER SUPPLY Positive Supply Voltage 45 50 5 5 V Quiescent Current LO supply resistor programmable 100 mA IF supply resistor programmable 90 mA Total Quiescent Current V 5V 190 mA 3 3 V PERFORMANCE SPECIFICATIONS V 3 3 V I 125 mA T 25 C fg 2535 MHz f o 2738 MHz LO power 0 dBm R9 226 Q R14 604 Q VGS0 VGSI 0 V and Zo 50 Q unless otherwise noted Table 4 Parameter Test Conditions Comments Min Typ Max Unit DYNAMIC PERFORMANCE Power Conversion Gain Including 4 1 IF port transformer and PCB loss 9 dB Voltage Conversion Gain Zsource 50 O differential Z 5 5 200 Q differential 15 dB SSB Noise Figure 8 95 dB Input Third Order Intercept IIP3 fre 2534 5 MHZ fre 2535 5 MHz fio 2738 MHz each RF 19 dBm tone at 10 dBm Input Second Order Intercept IIP2 fre 2535 MHz far 2585 MHz fio 2738 MHz each RF tone 41 5 dBm at 10 dBm Input 1 dB Compression Point IP1dB 7 5 dBm POWER INTERFACE Supply Voltage 30 3 3 3 6 V Quiescent Current Res
9. 8 dB and can be used with a wide range of output impedances Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rightsofthird parties that may result fromits use Specifications subjectto change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM IFGM IFOP IFON PWDN LEXT VLO3 LGM3 VLO2 LOSW NC NC NO CONNECT 09117 001 Figure 1 The ADL5353 provides two switched LO paths that can be used in TDD applications where it is desirable to rapidly switch between two local oscillators LO current can be externally set using a resistor to minimize dc current commensurate with the desired level of performance For low voltage applications the ADL5353 is capable of operation at voltages down to 3 3 V with substantially reduced current For low voltage operation an additional logic pin is provided to power down 200 uA the circuit when desired The ADL5353 is fabricated using a BiCMOS high performance IC process The device is available in a 5 mm x 5 mm 20 lead LFCSP and operates over a 40 C to 85 C temperature range An evaluation board is also available Table 1 Passive Mixers Single Single Mixe
10. Board 1 Z RoHS Compliant Part Rev 0 Page 22 of 24 ADL5353 NOTES Rev 0 Page 23 of 24 ADL5353 NOTES 2010 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D09117 0 10 10 0 DEVICES www analog com Rev 0 Page 24 of 24
11. LO to RF Leakages vs LO Frequency 20 0 22 10 a 24 z E 20 26 Ta 85 C u E Ta 40 C ul i g o 28 d 30 a E k ul 30 o n Ty 25 C ad 710 32 50 34 36 a 60 5 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 265 2 70 9 2 40 2 45 2 50 2 55 2 60 2 65 2 70 2 75 2 80 2 85 2 90 9 RF FREQUENCY GHz S LO FREQUENCY GHz S Figure 34 RF to IF Isolation vs RF Frequency Figure 37 2LO Leakage vs LO Frequency 10 20 LO TO IF LEAKAGE dBm 3LO LEAKAGE dBm L a 20 2 40 2 45 2 50 2 55 2 60 2 65 2 70 2 75 2 80 2 85 2 90 LO FREQUENCY GHz 30 2 40 2 45 2 50 2 55 2 60 2 65 2 70 2 75 2 80 2 85 2 90 LO FREQUENCY GHz 09117 035 09117 038 Figure 35 LO to IF Leakage vs LO Frequency Figure 38 3LO Leakage vs LO Frequency Rev 0 Page 12 of 24 ADL5353 V 5 V I 190 mA T 25 C fg 2535 MHz f o 2738 MHz LO power 0 dBm R9 1 1 KQ R14 910 Q VGS0 VGSI 0 V and Zo 50 Q unless otherwise noted 160 140 120 100 LO SUPPLY CURRENT 80 CONVERSION GAIN dB SSB NOISE FIGURE dB SUPPLY CURRENT mA SUPPLY CURRENT VGS 00 VGS 01 VGS z 10 VGS 11 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 2 65 2 70 RF FREQUENCY GHz 60 40 600
12. available for the family of double balanced Table 7 describes the various configuration options of the mixers The standard evaluation board schematic is shown in evaluation board Evaluation board layout is shown in Figure 53 to Figure 52 The evaluation board is fabricated using Rogers Figure 56 RO3003 material L5 470nH Vg 0 n IF1 OUT Y E C19 L4 c17 R1 T 470nH 1 00 R25 R24 00 00 O PWR UP R21 EU Lg iio 9100 b V V V C12 22pF LO2IN wy O Vso c2 C21 ue C20 Jio vier VY 10pF ec RF IN i VPSW 1 5pF 1o H fae Se n H 1nF R ADL5353 veer o L 13KO V vas V c5 c4 engan 0 01pF i 10pF J i vaso oi VGSO Lon V Vs 0 O LOSEL O V C8 Ss wv d Figure 52 Evaluation Board Schematic C6 R9 R4 10pF i 1 1KQ 10kQ 09117 151 Rev 0 Page 19 of 24 ADL5353 Table 7 Evaluation Board Configuration Components Function Description Default Conditions C2 C6 C8 C18 Power Nominal supply decoupling consists of a 10 uF capacitor to C2 10 uF size 0603 C19 C20 C21 supply ground in parallel with a 10 pF capacitor to ground positioned C6 C8 C20 C21 10 pF size 0402 decoupling as close to the device as possible C18 C19 100 pF size 0402 C1 C4 C5 Z1 RF input The input channels are ac coupled through C1 C4 and C5 C12 1 5 pF size 0402 interface provide bypassing for the center taps of the RF input baluns C4 10 pF size 0402 C5 0 01 pF size 0402 Z1 10 nH
13. size 0402 T1 C17 LA L5 IF output The open collector IF output interfaces are biased through T1 TC4 1W Mini Circuits R1 R24 R25 interface pull up choke inductors L4 and L5 T1 is a 4 1 impedance C17 150 pF size 0402 transformer used to provide a single ended IF output interface L4 L5 470 nH size 1008 with C17 providing center tap bypassing Remove R1 for recon balanced output operation R1 R24 R25 0 Q size 0402 C10 C12 R4 LO interface C10 and C12 provide ac coupling for the LO1 IN and LO2 IN C10 C12 22 pF size 0402 local oscillator inputs LOSEL selects the appropriate LO input R4 10 KQ size 0402 for both mixer cores R4 provides a pull down to ensure that LO1 IN is enabled when the LOSEL test point is logic low LO2 IN is enabled when LOSEL is pulled to logic high R21 PWDN R21 pulls the PWDN logic low and enables the device The R21 10 kQ size 0402 interface PWR UP test point allows the PWDN interface to be exercised using the external logic generator Grounding the PWDN pin for nominal operation is allowed Using the PWDN pin when supply voltages exceed 3 3 V is not allowed C22 L3 RS R14 Bias control R22 and R23 form a voltage divider to provide 3 V for logic C22 1 nF size 0402 R22 R23 VGSO VGS1 control bypassed to ground through C22 VGSO and VGS1 jumpers provide programmability at the VGSO and VGS1 pins It is recommended to pull these two pins to ground for nominal operation
14. spur tables are N x fre M x fio and were measured using the standard evaluation board Mixer spurious products are measured in dBc from the IF output power level Data was measured for frequencies less than 6 GHz only Typical noise floor of the measurement system 100 dBm 5 V Performance Vs 5 V Is 190 mA Ta 25 C frr 2600 MHz fio 2803MHz LO power 0 dBm RF power 10 dBm VGS0 VGS1 VGS2 0 V and Zo 50 Q unless otherwise noted M 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 14 9 33 1 1 36 5 0 00 63 4 59 8 2 80 2 87 8 66 8 86 8 3 100 100 96 7 100 4 100 100 100 100 5 100 100 100 100 6 100 lt 100 100 100 N 7 lt 100 100 100 100 8 100 100 100 100 9 100 100 100 100 10 100 100 100 100 11 100 100 100 100 12 100 100 100 100 100 13 100 100 100 100 100 14 100 100 100 100 3 3 V Performance Vs 3 3 V Is 125 mA Ta 25 C frr 2600 MHz fio 2803 MHz LO power 0 dBm RF power 10 dBm R9 226 Q R14 604 Q VGSO VGSI 0 V and Zo 50 Q unless otherwise noted
15. 800 1000 1200 1400 1600 1800 BIAS RESISTOR VALUE Q 09117 039 09117 043 Figure 39 Power Conversion Gain and SSB Noise Figure vs RF Frequency Figure 42 LO and IF Supply Current vs IF and LO Bias Resistor Value A wo SSB NOISE FIGURE N CONVERSION G INPUT IP3 dBm INPUT P1dB dBm VGS 01 VGS 10 VGS z 11 14 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 2 65 2 70 RF FREQUENCY GHz INPUT IP3 dBm CONVERSION GAIN AND SSB NOISE FIGURE dB 06 0 7 08 09 1 0 11 1 2 13 14 15 1 6 IF BIAS RESISTOR VALUE kQ 09117 040 09117 044 Figure 40 Input IP3 and Input P1dB vs RF Frequency Figure 43 Power Conversion Gain SSB Noise Figure and Input IP3 vs IF Bias Resistor Value N E o INPUT IP3 dBm CONVERSION GAIN AND SSB NOISE FIGURE dB 0 6 0 8 1 0 1 2 1 4 1 6 1 8 LO BIAS RESISTOR VALUE kQ 09117 041 Figure 41 Power Conversion Gain SSB Noise Figure and Input IP3 vs LO Bias Resistor Value Rev 0 Page 13 of 24 ADL5353 3 3 V PERFORMANCE V 3 3 V I 125 mA T 25 C f 2535 MHz f 2738 MHz LO power 0 dBm R9 226 Q R14 604 Q VGS0 VGSI 0 V and Z 50 Q unless otherwise noted
16. ANALOG DEVICES 2200 MHz to 2700 MHz Balanced Mixer LO Buffer IF Amplifier and RF Balun ADL5353 FEATURES Frequency ranges of 2200 MHz to 2700 MHz RF and 30 MHz to 450 MHz IF Power conversion gain 8 7 dB Input IP3 of 24 5 dBm and Input P1dB of 10 4 dBm SSB noise figure of 9 8 dB Typical LO drive of 0 dBm Single ended 50 O RF and LO input ports High isolation SPDT LO input switch Single supply operation 3 3 V to 5 V Exposed pad 5 mm x 5 mm 20 lead LFCSP 1500 V HBM 500 V FICDM ESD performance APPLICATIONS Cellular base station receivers Transmit observation receivers Radio link downconverters GENERAL DESCRIPTION The ADL5353 uses a highly linear doubly balanced passive mixer core along with integrated RF and local oscillator LO balancing circuitry to allow for single ended operation The ADL5353 incorporates an RF balun to provide optimal perfor mance over a 2200 MHz to 2700 MHz input frequency range using high side LO The balanced passive mixer arrangement provides good LO to RF leakage typically better than 36 dBm and excellent intermodulation performance The balanced mixer core also provides extremely high input linearity allowing the device to be used in demanding cellular applications where in band blocking signals might otherwise result in the degradation of dynamic performance A high linearity IF buffer amplifier follows the passive mixer core to yield a typical power conversion gain of 8
17. E g 2 Z Z fo o amp 6 A 2 0 2 4 6 8 10 6 4 2 0 2 4 6 8 10 LO POWER dBm S LO POWER dBm S Figure 21 Power Conversion Gain vs LO Power Figure 24 Input P1dB vs LO Power m t S m 2 z g 3 S 5 amp a o z e u x 75 6 4 2 0 2 4 6 8 10 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 2 65 2 70 LO POWER dBm S RF FREQUENCY GHz E Figure 22 Input IP3 vs LO Power Figure 25 IF 2 Spurious vs RF Frequency RF Power 10 dBm Ej S kJ S o St o T LE 2 i 5 z e u g 90 g 6 A 2 0 2 4 6 8 10 9 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 265 2 70 LO POWER dBm S RF FREQUENCY GHz 5 Figure 23 Input IP2 vs LO Power Figure 26 IF 3 Spurious vs RF Frequency RF Power 10 dBm Rev 0 Page 10 of 24 ADL5353 V 5 V I 190 mA T 25 C En 2535 MHz f o 2738 MHz LO power 0 dBm R9 1 1 KO R14 910 Q VGS0 VGSI 0 V and Zo 50 Q unless otherwise noted 100 500 10 80 400 8 60 6 40 4 20 100 2 S 0 0 0 8 70 8 75 8 80 8 85 8 90 30 80 130 180 230 280 330 380 430 CONVERSION GAIN dB IF FREQUENCY MHz e e eo V RESISTANCE 0 M eo e CAPACITANCE pF DISTRIBUTION PERCENTAGE W 09117 027 09117 030 Figure 27 Power Conversion Gain Distribution Figure 30 IF Differential Output Impedance R Parallel C Equivalent DISTRIBUTION PERCENTAGE o S 8 S S
18. For dc current sensitive applications it is per missible to reduce the current in the LO amplifier by raising the value of the external bias control resistor For dc current critical applications the LO chain can operate with a supply voltage as low as 3 3 V resulting in substantial dc power savings In addition when operating with supply voltages below 3 6 V the ADLS5353 has a power down mode that permits the dc current to drop to 200 uA All of the logic inputs are designed to work with any logic family that provides a Logic 0 input level of less than 0 4 V and a Logic 1 input level that exceeds 1 4 V All logic inputs are high impedance up to Logic 1 levels of 3 3 V At levels exceeding 3 3 V protection circuitry permits operation of up to 5 5 V although a small bias current is drawn All pins including the RF pins are ESD protected and have been tested to a level of 1500 V HBM and 500 V CDM Rev 0 Page 17 of 24 ADL5353 APPLICATIONS INFORMATION BASIC CONNECTIONS The ADL5353 mixer is designed to downconvert radio frequen cies RF primarily between 2200 MHz and 2700 MHz to lower intermediate frequencies IF between 30 MHz and 450 MHz Figure 51 depicts the basic connections of the mixer To prevent nonzero dc voltages from damaging the RF balun or LO input circuit ac couple the RF and LO input ports The RFIN matching network consists of a series 1 5 pF capacitor and a shunt 10 nH inductor to provide the optimized
19. R9 sets the bias point for the internal LO buffers R14 sets the bias point for the internal IF amplifier L3 2 0 Q size 0603 R9 1 1 k Q size 0402 R14 910 Q size 0402 R22 10 k Q size 0402 R23 15 KQ size 0402 VGSO VGS1 3 pin shunt Rev 0 Page 20 of 24 ADL5353 09117 152 09117 154 se e V 9 9 09117 153 09117 155 Figure 54 Evaluation Board Ground Plane Internal Layer 1 Figure 56 Evaluation Board Bottom Layer Rev 0 Page 21 of 24 ADL5353 OUTLINE DIMENSIONS PIN 1 INDICATOR 5 00 gt li pe N 0 60 xl COPLANARITY 0 60 MAX PIN 1 o INDICATOR Fo 15 46 0 65 3 20 EXPOSED e SS E 3 10 so l Y 3 00 c 2 60 BSC FOR PROPER CONNECTION OF THE EXPOSED PAD REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET 3 0 35 PLANE B 0 28 L 0 20 REF 9 05 0 23 m COMPLIANT TO JEDEC STANDARDS MO 220 VHHC 3 Figure 57 20 Lead Lead Frame Chip Scale Package LFCSP_VQ 5mm x 5 mm Body Very Thin Quad CP 20 5 Dimensions shown in millimeters ORDERING GUIDE Temperature Package Model Range Package Description Option Ordering Quantity ADL5353ACPZ R7 40 C to 85 C 20 Lead Lead Frame Chip Scale Package LFCSP VQ CP 20 5 1 500 7 Tape and Reel ADL5353ACPZ WP 40 C to 85 C 20 Lead Lead Frame Chip Scale Package LFCSP VQ CP 20 5 36 Waffle Package ADL5353 EVALZ Evaluation
20. RF RETURN LOSS dB I l L I Fa e nN nN I a eo a eo a eo a o V N 40 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 2 65 2 70 22 23 24 25 26 a 8 INPUT IP3 dBm amp RF FREQUENCY GHz S Figure 28 Input IP3 Distribution Figure 31 RF Port Return Loss Fixed IF LO RETURN LOSS dB DISTRIBUTION PERCENTAGE 100 0 5 80 10 60 15 40 FETT 20 25 0 30 9 0 9 4 9 8 10 2 10 6 11 0 11 4 11 8 20 21 22 23 24 25 26 27 28 29 INPUT P1dB dBm LO FREQUENCY GHz 09117 029 pa eo 09117 032 Figure 29 Input P1dB Distribution Figure 32 LO Return Loss Selected and Unselected Rev 0 Page 11 of 24 ADL5353 V 5 V I 190 mA T 25 C fp 2535 MHz f o 2738 MHz LO power 0 dBm R9 1 1 kO R14 910 Q VGS0 VGSI 0 V and Z 50 Q unless otherwise noted 60 20 55 25 5 Ta 40 C z kd 50 u y k g 30 TA 25 C S E o 45 X E E 35 4 g TA 85 C 9 S 40 35 30 2 45 2 20 2 25 2 30 2 35 2 40 2 45 2 50 2 55 2 60 265 2 70 2 40 2 45 2 50 2 55 2 60 2 65 2 70 2 75 2 80 2 85 2 90 5 LO FREQUENCY GHz S LO FREQUENCY GHz S Figure 33 LO Switch Isolation vs LO Frequency Figure 36
21. RF input return loss for the desired frequency band IF port The mixer differential IF interface requires pull up choke inductors to bias the open collector outputs and to set the output match The shunting impedance of the choke inductors used to couple dc current into the IF amplifier should be selected to provide the desired output return loss The real part of the output impedance is approximately 200 Q which matches many commonly used SAW filters without the need for a transformer This results in a voltage conversion gain that is approximately 6 dB higher than the power conversion gain as shown in Table 3 When a 50 Q output impedance is needed use a 4 1 impedance transformer as shown in Figure 51 BIAS RESISTOR SELECTION Two external resistors Ryjas jp and Basste are used to adjust the bias current of the integrated amplifiers at the IF and LO terminals It is necessary to have a sufficient amount of current to bias both the internal IF and LO amplifiers to optimize dc current vs optimum IIP3 performance MIXER VGS CONTROL DAC The ADL5353 features two logic control pins VGSO Pin 12 and VGS1 Pin 13 that allow programmability for internal gate to source voltages for optimizing mixer performance over desired frequency bands The evaluation board defaults both VGSO and VGSI to ground 09117 150 Figure 51 Typical Application Circuit Rev 0 Page 18 of 24 ADL5353 EVALUATION BOARD An evaluation board is
22. drive the mixer independent of the level of the LO input A block diagram of the device is shown in Figure 50 IFGM IFOP IFON PWDN LEXT BIAS GENERATOR VLO3 LGM3 VLO2 LOSW NC 09117 149 NC NO CONNECT Figure 50 Simplified Schematic RF SUBSYSTEM The single ended 50 RF input is internally transformed to a balanced signal using a low loss lt 1 dB unbalanced to balanced balun transformer This transformer is made possible by an extremely low loss metal stack which provides both excellent balance and dc isolation for the RF port Although the port can be dc connected it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part The RF balun can easily support an RF input frequency range of 2200 MHz to 2700 MHz The resulting balanced RF signal is applied to a passive mixer that commutates the RF input with the output of the LO subsystem The passive mixer is essentially a balanced low loss switch that adds minimum noise to the frequency translation The only noise contribution from the mixer is due to the resistive loss of the switches which is in the order of a few ohms Because the mixer is inherently broadband and bidirectional it is necessary to properly terminate all the idler M x N product frequencies generated by the mixing process Terminating the mixer avoids the generation of unwanted intermodulation pro ducts and reduces the level of unwanted signals at the
23. ed power of the part Note that no performance enhancement is obtained by reducing the value of these resistors and excessive dc power dissipation may result LO SUBSYSTEM The ADL5353 has two LO inputs permitting multiple synthe sizers to be rapidly switched with extremely short switching times lt 40 ns for frequency agile applications The two inputs are applied to a high isolation SPDT switch that provides a constant input impedance regardless of whether the port is selected to avoid pulling the LO sources This multiple section switch also ensures high isolation to the off input minimizing any leakage from the unwanted LO input that may result in undesired IF responses The single ended LO input is converted to a fixed amplitude differential signal using a multistage limiting LO amplifier This results in consistent performance over a range of LO input power Optimum performance is achieved from 6 dBm to 10 dBm but the circuit continues to function at considerably lower levels of LO input power Rev 0 Page 16 of 24 The performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system This is a critical requirement in an interferer rich environ ment such as cellular infrastructure where blocking interferers can limit mixer performance The bandwidth of the intermodulation performance is somewhat influenced by the current in the LO amplifier chain
24. input of the IF amplifier where high peak signal levels can compromise the compression and intermodulation performance of the system This termination is accomplished by the addition of a sum network between the IF amplifier and the mixer and also in the feedback elements in the IF amplifier The IF amplifier is a balanced feedback design that simultaneously provides the desired gain noise figure and input impedance that are required to achieve the overall performance The balanced open collector output of the IF amplifier with impedance mod ified by the feedback within the amplifier permits the output to be connected directly to a high impedance filter differential amplifier or to an analog to digital input while providing optimum second order intermodulation suppression The differential output impedance of the IF amplifier is approximately 200 If operation in a 50 Q system is desired the output can be transformed to 50 Q by using a 4 1 transformer The intermodulation performance of the design is generally limited by the IF amplifier The Input IP3 performance can be optimized by adjusting the IF current with an external resistor Figure 41 Figure 42 and Figure 43 illustrate how various IF and LO bias resistors affect the performance with a 5 V supply Addi tionally dc current can be saved by increasing either or both resistors It is permissible to reduce the dc supply voltage to as low as 3 3 V further reducing the dissipat
25. istor programmable 125 mA Power Down Current Device disabled 150 uA Rev 0 Page 4 of 24 ABSOLUTE MAXIMUM RATINGS Table 5 Parameter Rating Supply Voltage V 55V RF Input Level 20 dBm LO Input Level 13 dBm IFOP IFON Bias Voltage 6 0V VGSO VGS1 LOSW PWDN 55V Internal Power Dissipation 1 2 W Thermal Resistance 0 25 C W Temperature Maximum Junction Temperature 150 C Operating Temperature Range 40 C to 85 C Storage Temperature Range 65 C to 150 C Lead Temperature Soldering 60 sec 260 C ADL5353 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION A Aen ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev 0 Page 5 of 24 ADL5353 PIN 1 VPIF 11 INDICATOR RFIN 28 ADL5353 RFCT 3 COMM 4 TOP VIEW Not to Scale
26. r Dual Mixer RF Frequency MHz Mixer and IF Amp and IF Amp 500 to 1700 ADL5367 ADL5357 ADL5358 1200 to 2500 ADL5365 ADL5355 ADL5356 2200 to 2700 ADL5353 ADL5354 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2010 Analog Devices Inc All rights reserved TABLE OF CONTENTS te 1 3 3 V Perform nce ee 14 E EE 1 SpursTables estie tenere biete et e i tee eere 15 General Description i eee tae tee S edet 1 Circuit Description eee tere tree ne terere tuere 16 Functional Block Diagram ENEE 1 RE S bsySstem i nce eere n EENEG 16 Revision History EEN 2 LO SubSystenni z certet Ebene 16 GEELEN ee 3 Applications Information EE 18 5 V Performance Specifications sse 3 Basic Connections essere 18 3 3 V Performance Specifications sse 4 Bias Resistor Selection EEN 18 Absolute Maximum Ratings essent 5 Mixer VGS Control DAC sssrini 18 LR 5 Evaluation Board ette tete 19 Pin Configuration and Function Descriptions 6 Outline Dimensions sea t t PO 22 Typical Performance Characteristics uneneen 7 e at 22 Ka H REVISION HISTORY 10 10 Revision 0 Initial Version Rev 0 Page 2 of 24 ADL5353 SPECIFICATIONS 5 V PERFORMANCE SPECIFICATIONS RF Interface V 5V 1 190 mA T 25 C frr 2535 MHz fio 2738 MHz LO power 0 dBm Zo 50 Q unless otherwise noted
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ANALOG DEVICES ADL5353 English products handbook Rev 0