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MICROCHIP - 2002 Microchip Technology Inc. Preliminary DS30485A PIC18FXX39 Data Sheet Enhanced FLASH Microcon

1. 40 Pin DIP 7 MCLR Vpp e 1 40 O RB7 PGD 2 39 E lt RB6 PGC RA1 AN1 3 38 lt RB5 PGM RA2 AN2 VREF 4 4 37 O RA3 ANS VREF 5 36 E lt RAA TOCK 0 6 35 lt RB2 INT2 RAS AN4 SS LVDIN 7 34 E RBI INT1 REO ANS RD lt 08 amp 9 330 RBO INTO RE1 AN6WR 9 9 21 v 2 7 5 e 10 LL 31 4 Vss g1 0 RD7PSP7 __ 12 2 gt 91 RD6 PSP6 OSC1 CLKI gt H13 2 281 lt RDS PSP5 OSC2 CLKO RA6 14 27 RD4 PSP4 RCO T13CKI 15 26 1 lt RC7 RX DT PWM2 16 25 1 lt RC6 TXICK PWM1 17 24 RC5 SDO RC3 SCK SCL 18 23 RC4 SDI SDA RDO PSPO 19 22 1 lt RD3 PSP3 RD1 PSP1 20 21 1 RD2 PSP2 28 Pin DIP SOIC MCLR VPP 1 M 28 lt RB7 PGD RAO ANO 2 27 lt RBe PGC RATAN1 26 lt gt RBS PGM RAZIAN2NREP 4 o 25 RB4 RAS AN3 Veer lt 5 9 Q 24 1 lt 6 N 0 230 RBZ INT2 RAS ANA SSILVDIN 220 gt RB1 NT1
2. FIGURE 1 2 PIC18F4X39 BLOCK DIAGRAM Data Bus 8 I A gt lt RAO ANO 21 Table Pointer Data Latch RA1 AN1 Data RAM 4 RA2 AN2 VREF 8 48 48 ie Mn H 54 RA3 AN3 VREF 24 inc dec logic dd ch aneres sach RAS ANA SSILVDIN Address Latch I4 RAG Address Latch 21 PCLATU PCLATH y 42 Program Memory Address lt 12 gt PORTB up to 2 Mbytes PCU PCH PCL RBO INTO Program Counter 4 12 4 Data Latch ae M N RB1 INT1 FSRO F ___ RB2 INT2 31 Level Stack FSR1 gt XJ RBS L N FSR2 12 4 RB4 RB5 PGM 16 2 4 5 RB6 PGC Decode magee T D9 RB7 PGD Table Latch g 8 PORTC HOMES RCO T13CKI 4 4 RC4 SDI SDA Instruction 9 5 RC5 SDO Register RCG TX CK 8 4 Instruction Decode amp Control PRODH PRODL OSC2 CLKO i PORTD OSC1 CLKI 3 8 x 8 Multiply RDO PSPO Power up 8 RD1 PSP1 KK gt Timer 28 RD2 PSP2 Timing TE Oscillator WREG RD3 PSP3 TOC Generation Start up Timer BiT 8 RD4 PSP4 gt Power on gt RD5 PSP5 Reset 4 RD6 PSP6 8 Watchdog RD7 PSP7 4X PLL N l
3. File Name Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BOR BOR e TOSU Top of Stack Upper Byte TOS lt 20 16 gt 0 0000 26 34 TOSH Top of Stack High Byte TOS lt 15 8 gt 0000 0000 26 34 TOSL Top of Stack Low Byte TOS lt 7 0 gt 0000 0000 26 34 STKPTR STKFUL STKUNF Return Stack Pointer 00 0 0000 26 35 PCLATU Holding Register for lt 20 16 gt 0 0000 26 36 PCLATH Holding Register for lt 15 8 gt 0000 0000 26 36 PCL PC Low Byte lt 7 0 gt 0000 0000 26 36 TBLPTRU bit21 Program Memory Table Pointer Upper Byte TBLPTR lt 20 16 gt 00 0000 26 54 TBLPTRH Program Memory Table Pointer High Byte TBLPTR lt 15 8 gt 0000 0000 26 54 TBLPTRL Program Memory Table Pointer Low Byte lt 7 0 gt 0000 0000 26 54 TABLAT Program Memory Table Latch 0000 0000 26 54 PRODH Product Register High Byte xxxx xxxx 26 67 PRODL Product Register Low Byte xxxx xxxx 26 67 INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 000 26 71 INTCON2 RBPU INTEDGO INTEDG1 INTEDG2 TMROIP RBIP 1111 1 1 26 72 INTCON3 INT2IP INT1IP INT2IE INT1IE INT2IF INT1IF 11 0 0 00 26 73 INDFO Uses contents of FSRO to address data memory value of FSRO not changed not a physical register n a 26 47 POSTIN
4. Bus Collision 4 Internal SSPM3 SSPMO Data Bus SSPADD lt 6 0 gt Read MET Write SSPBUF Baud Rate Generator J Shift x SDA in Clock 9 SSPSR 3E MSb LSb 5 E c gt 15 START bit STOP bit 9 8 2 Acknowledge Be 9 Generate x 2 SCL e E tle 4 gt gt 3 Ds 9 lt ale START bit Detect STOP bit Detect SCL in Write Collision Detect e Set Reset S P WCOL SSPSTAT Clock Arbitration Set SSPIF BCLIF State Counter for end of XMIT RCV Reset ACKSTAT PEN SSPCON2 2002 Microchip Technology Inc Preliminary DS30485A page 149 PIC18FXX39 16 4 6 1 12 Master Mode Operation The master device generates all of the serial clock pulses and the START and STOP conditions trans fer is ended with a STOP condition or with a Repeated START condition Since the Repeated START condi tion is also the beginning of the next serial transfer the 2 bus will not be released In Master Transmitter mode serial data is output through SDA while SCL outputs the serial clock The first byte transmitted contains the slave address of the receiving device 7 bits and the Read Write R W bit In this case the R W bit will be logic 0 Serial data is trans
5. i U c r J DS30485A page 60 Preliminary 2002 Microchip Technology Inc PIC18FXX39 6 0 DATA EEPROM MEMORY The Data EEPROM is readable and writable during normal operation over the entire VDD range The data memory is not directly mapped in the register file space Instead it is indirectly addressed through the Special Function Registers SFR There are four SFRs used to read and write the program and data EEPROM memory These registers are EECON1 EECON2 EEDATA EEADR The EEPROM data memory allows byte read and write When interfacing to the data memory block EEDATA holds the 8 bit data for read write and EEADR holds the address of the EEPROM location being accessed These devices have 256 bytes of data EEPROM with an address range from Oh to FFh The EEPROM data memory is rated for high erase write cycles A byte write automatically erases the loca tion and writes the new data erase before write The write time is controlled by an on chip timer The write time will vary with voltage and temperature as well as from chip to chip Please refer to parameter D122 Electrical Characteristics Section 23 0 for exact limits 6 1 EEADR The address register can address up to a maximum of 256 bytes of data EEPROM 6 2 EECON1 and 2 Registers is the control
6. 8 x 8 Unsigned Multiply Routine Data EEPROM Read Data EEPROM Refresh Routine e Data EEPROM Write Erasing a FLASH Program Memory 56 How to Clear RAM Bank 1 Using Indirect Addressing 47 Initializing PORTA Initializing 0 0000004 86 Initializing 1 89 Initializing PORTD ai Ot Initializing PORTE 2 93 Loading the SSPBUF SSPSR Register 128 Motor Control Routine using ProMPT APIs 121 Reading a FLASH Program Memory Word 55 Saving STATUS WREG and BSR Registers in RAM 81 Writing to FLASH Program Memory 58 59 Code Protection treten rne tnde COME eo uu e do A ntes dor er Configuration Bits Context Saving During Interrupts 81 Conversion Considerations 306 228 etse 229 229 D Data EEPROM Memory Associated Registers 65 EEADR Register eie secrets 61 EEC
7. BNOV Branch if Not Overflow Syntax abel BNOV n Operands 128 lt n lt 127 Operation if overflow bit is 0 2 2 gt Status Affected None Encoding 1110 0101 nnnn nnnn Description If the Overflow bit is 0 then the program will branch The 25 complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a two cycle instruction Words 1 Cycles 1 2 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Data No No No No operation operation operation operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal Process No Data operation Example HERE BNOV Jump Before Instruction PC address HERE After Instruction If Overflow 0 PC address Jump If Overflow 1 address HERE 2 BNZ Branch if Not Zero Syntax label BNZ n Operands 128 lt n lt 127 Operation if zero bit is 0 2 2n 5 Status Affected None Encoding 1110 0001 nnnn nnnn Description If the Zero bit is 0 then the program will branch The 2 s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a two cycle instruction Words 1 Cycles 1 2
8. POR See Power on Reset PORTA Associated Registers LATA Register E PORTA Register TRISA Register eee PORTB Associated Registers LATB Register PORTB Register 200 0 RBO INT Pin External 81 RB7 RB4 Interrupt on Change Flag RBIE Bil 86 TRISB Register netten 86 PORTC Associated Registers 90 LATC Register PORTO Register 04 4 89 RC3 SCK SCL Pin exis itd 139 RC7 RX DT Pin TRISC Register PORTD Associated Registers 92 Register req 91 Parallel Slave Port PSP Function 91 PORTD Register 2 91 TRISD Register esee 91 PORTE Analog Port trn tee Associated Registers LATE REGIST eb As PORTE Register PSP Mode Select PSPMODE Bit 91 96 REO ANS RD Pin sss RE1 ANG WR Pin e RE2 ANT CS Pin sees Register ned eter Postscaler WDT Assignment PSA Bit Rate Select TOPS2 TOPSO Bits n Switching Between 0 WDT 101 Power down Mode See SLEEP Power on Reset 24 Oscill
9. R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 U 0 R W 0 ADCS1 ADCSO CHS2 CHS1 50 GO DONE ADON bit 7 bit 0 bit7 6 ADCS1 ADCSO A D Conversion Clock Select bits ADCONO bits in bold ADCON1 ADCONO Clock C lt ADCS2 gt lt ADCS1 ADCS0 gt 0 00 Fosc 2 0 01 Fosc 8 0 10 Fosc 32 0 11 FRC clock derived from the internal A D RC oscillator 1 00 Fosc 4 1 01 Fosc 16 1 10 Fosc 64 1 11 FRC clock derived from the internal A D RC oscillator bit 5 3 CHS2 CHSO0 Analog Channel Select bits 000 Channel 0 ANO 001 7 Channel 1 AN1 010 Channel 2 AN2 011 Channel 3 AN3 100 Channel 4 4 101 Channel 5 5 7 110 Channel 6 AN6 111 Channel 7 AN7 Note 1 These channels are unimplemented on PIC18F2X39 devices Do not select any unimplemented channel bit 2 GO DONE A D Conversion Status bit When ADON 1 1 A D conversion in progress setting this bit starts the A D conversion which is automatically cleared by hardware when the A D conversion is complete 0 A D conversion not in progress bit 1 Unimplemented Read as 0 bit 0 ADON A D On bit 1 A D converter module is powered up 0 A D converter module is shut off and consumes no operating current Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2002 Microchip Technology Inc
10. 0000008 Byte Locations 000002h 000004h 000006h Instruction 1 wovrw 055h OFh 55h 000008h Instruction 2 000006h EFh 03h 00000Ah FOh 00h 00000Ch Instruction 3 123h 456h Cih 23h 00000 56h 000010h 000012h 000014h 2002 Microchip Technology Inc Preliminary DS30485A page 37 PIC18FXX39 4 7 1 TWO WORD INSTRUCTIONS The PIC18FXX39 devices have four two word instruc tions MOVFF CALL GOTO and LFSR The second word of these instructions has the 4 MSBs set to 1 s and is a special kind of NoP instruction The lower 12 bits of the second word contain data to be used by the instruction If the first word of the instruction is exe cuted the data in the second word is accessed If the second word of the instruction is executed by itself first word was skipped it will execute as a NOP This action is necessary when the two word instruction is preceded by a conditional instruction that changes the PC A pro gram example that demonstrates this concept is shown in Example 4 2 Refer to Section 21 0 for further details of the instruction set EXAMPLE 4 2 TWO WORD INSTRUCTIONS CASE 1 Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 is RAM location 0 1100 0001 0010 0011 MOVFF REG1 REG2 No execute 2 word instruction 1111 0100 0101 0110 2nd oper
11. PWM Operation Simplified RA3 RAO and RAS Pins Piti th Petr ems Pin Reads from FLASH Program Memory 55 Table Read Operation 51 Table Write Operation it Table Writes to FLASH Program Memory 57 TimerO in 16 bit Mode TimerO in 8 bit REED Har Timer1 16 bit R W Mode 25 cre TIMERS arvasingi bc err rrt eye ttes Timer3 16 bit R W Mode Typical Motor Control System USART Receive ies USART Transit ter tent Watchdog Timer ttc BOV ceste potat es e oua aan LN d LI Pu caters 225 BRA URB IRE E 223 BRG See Baud Rate Generator Brown out Reset 24 2002 Microchip Technology Inc Preliminary DS30485A page 309 PIC18FXX39 CALL ah deisel oracio edited e Clocking Scheme Instruction Cycle aenea eer CERWD To as sik e AE eei Code Examples 16 x 16 Signed Multiply Routine 68 16 x 16 Unsigned Multiply Routine 68 8 x 8 Signed Multiply Routine
12. series microcontrollers on an instruction level On any given instruction the data areas can be examined or modified and stimuli can be applied from a file or user defined key press to any of the pins The execution can be performed in single step execute until break or trace mode The MPLAB SIM simulator fully supports symbolic debug ging using the MPLAB C17 and the MPLAB C18 C com pilers and the MPASM assembler The software simulator offers the flexibility to develop and debug code outside of the laboratory environment making it an excellent multi project software development tool 22 6 MPLAB ICE High Performance Universal In Circuit Emulator with MPLAB IDE The MPLAB ICE universal in circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for microcontrollers MCUs Software control of the MPLAB ICE in circuit emulator is provided by the MPLAB Integrated Development Environment IDE which allows editing building downloading and source debugging from a single environment The MPLAB ICE 2000 is a full featured emulator sys tem with enhanced trace trigger and data monitoring features Interchangeable processor modules allow the system to be easily reconfigured for emulation of differ ent processors The universal architecture of the MPLAB ICE in circuit emulator allows expansion to support new PlCmicro microcontrollers
13. DAW Decimal Adjust W Register DECF Decrement f Syntax abel DAW Syntax abel DECF Operands None Operands 0 lt f lt 255 Operation If W lt 3 0 gt gt 9 or DC 1 then d 0 1 lt 3 0 gt 6 gt W lt 3 0 gt 0 1 else Operation f 1 5 dest W lt 3 0 gt lt 3 0 gt Status Affected DC OV Z If W 7 4 gt 9 or C 1 then Encoding 0000 01da W lt 7 4 gt 6 gt lt 7 4 gt Description Decrement register If d is 0 the else result is stored in W If d is 1 the W lt 7 4 gt gt lt 7 4 gt result is stored back in register f Status Affected C default If a is 0 the Access Bank will be selected overriding Encoding 0000 0000 0000 0111 the BSR value If a 1 then the Description DAW adjusts the eight bit value in bank will be selected as per the W resulting from the earlier addi BSR value default tion of two variables each in Words 1 packed BCD format and produces 5 a correct packed BCD result Cycles 1 Words 1 Q Cycle Activity Cycles 1 Q1 Q2 Q3 Q4 ae Decode Read Process Write to Q Cycle Activity register f Data destination Q1 Q2 Q3 Q4 Decode Read Process Write Example DECF CNT deh 19 register W Data Ww Before Instruction Example1 DAW CNT 0x01 Before Instruction 2 6B W 0 5 After Instruction C 0 CNT 0x00 DC 0 2 After Instruction 0x05 C 1 DC 0 Example
14. Reset WM S Lond 31 gt 34 34 lt I O Pins Note Refer to Figure 23 4 for load conditions FIGURE 23 8 BROWN OUT RESET TIMING BVDD VDD 8670 VBGAP 1 2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage stable TABLE 23 7 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER POWER UP TIMER AND BROWN OUT RESET REQUIREMENTS Eois Symbol Characteristic Min Typ Max Units Conditions 30 TmcL MCLR Pulse Width low us 31 TWDT Watchdog Timer Time out Period No 18 33 ms Postscaler 32 TOST Oscillation Start up Timer Period 1024 Tosc 1024 Tosc Tosc OSC1 period 33 TPWRT Power up Timer Period 28 72 132 ms 34 TIOZ high impedance from MCLR Low 2 us or Watchdog Timer Reset 35 TBOR Brown out Reset Pulse Width 200 us VDD lt see 0005 36 5 Time for Internal Reference 20 500 us Voltage to become stable 37 TLVD Low Voltage Detect Pulse Width 200 us VDD lt see D420 DS30485A page 272 Preli minary 2002 Microchip Technology Inc PIC18FXX39 FIGURE 23 9 TIMERO AND TIMER1 EXTERNAL CLOCK TIMINGS TOCKI 7 ji cu 40 a 41 gt E 42 1 3 iN
15. Baup FOsc 40MHz sppng 33 MHz SPBRG 25 MHz SPBRG 20 MHz SPBRG RATE value value value value Kbps kgAup ERROR decimal ERROR decima KBaup ERROR decimal ERROR decimal 03 NA E z NA z 12 5 24 5 NA 96 2 5 2 2 z 19 2 E NA z NA 5 2 768 7692 016 129 7710 039 106 77 16 047 80 7692 016 64 96 96 15 016 103 9593 007 85 96 15 016 64 96 15 40 16 51 300 30303 101 32 20464 179 27 297 62 079 20 294 12 1 96 16 500 500 0 19 48530 2 94 16 48077 3 85 12 500 0 9 HIGH 10000 l 0 8250 0 6250 R 0 5000 0 LOW 39 06 255 32 23 255 24 41 255 19 53 255 Baup F9367 16 MHz SPBRG 10 MHz PERG 7 15909 MHz 5 0688 MHz SEHE RATE value value value value Kbps KBaup ERROR decimal ERROR decimal ERROR decimal ERROR decimal 03 NA z NA z NA z 1 2 NA 5 24 NA S 3 9 6 NA NA 3 5 962 0 23 185 9 60 0 131 19 2 1923 016 207 19 23 016 129 19 24 023 92 19 20 0 65 768 7692 016 51 7576 136 32 77 82 132 22 7454 294 16 96 9524 079 41 96 05 016 25 94 20 188 18 97 48 154 12 300 30770 256 12 842 50 447 7 208 35 0 57 5 816 80 560 3 500 500 0 7 500 0 4 44744 10 51 3 42240 15 52 2 HIGH 4000 0 2500
16. M empjeu q NAS UOpuoo LYYLS N3d M 5 si INGdSS 1 1 1 1 1 1 NAS 409455 1 lt 0 gt LVLSdSS MOV 55 1IQ 0 JO 0 0 sseJppy SJEMYOS 466 UI Y Y 9UnnoJ 92IAJOS 9JeEAgJOS UI i 31985 i 114655 spuodsoi ae 195 m C 4 VJ vef Nef v NV 06 7 e Vf 09 7 Vf V ef vf Vi ovs E yusue es e TE ae pue sse pego uy 55 va va Yza 0 402 62 ew Yov Xov e vas 23094855 ut IVLSMOV Jo geq Bumiusuei lt 9 gt CNOOdSS 1 IVLSMOV 1 5 0 N3s uonipuoo LYWLS NIS 0 ZNOOdSS AM 2002 Microchip Technology Inc iminary Prel DS30485A page 156 PIC18FXX39 I C MASTER MODE WAVEFORM RECEPTION 7 BIT ADDRESS FIGURE 16 22 L ene S eyeq SARIS sseJppy 3iusueJ In Iis 51 5409958 esneoeq 195 61 AOdSS i AOdSS
17. 14 15 L N3S lt 0 gt ZNOOdSS DS30485A page 157 iminary Prel 2002 Microchip Technology Inc PIC18FXX39 16 4 12 ACKNOWLEDGE SEQUENCE 16 4 13 STOP CONDITION TIMING TIMING STOP bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive transmit by setting the STOP sequence enable Acknowledge sequence enable bit bit PEN 55 2 lt 2 gt At the end of a receive SSPCON2 lt 4 gt When this bit is set the SCL pin is transmit the SCL line is held low after the falling edge pulled low and the contents of the Acknowledge data bit of the ninth clock When the PEN bit is set the master are presented on the SDA pin If the user wishes to gen will assert the SDA line low When the SDA line is sam erate an Acknowledge then the ACKDT bit should be pled low the baud rate generator is reloaded and cleared If not the user should set the ACKDT bit before counts down to 0 When the baud rate generator times starting an Acknowledge sequence The baud rate gen out the SCL pin will be brought high and one TBRG erator then counts for one rollover period TBRG and the baud rate generator rollover count later the SDA pin SCL pin is de asserted pulled high When the SCL pin will be de asserted When the SDA pin is sampled high is sampled high clock arbitration the baud rate gener while SCL is high the P bit SSPSTAT lt 4 gt
18. Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2002 Microchip Technology Inc Preliminary DS30485A page 167 PIC18FXX39 171 USART Baud Rate Generator BRG The BRG supports both the Asynchronous and Syn chronous modes of the USART It is a dedicated 8 bit baud rate generator The SPBRG register controls the period of a free running 8 bit timer In Asynchronous mode bit BRGH TXSTA lt 2 gt also controls the baud rate In Synchronous mode bit BRGH is ignored Table 17 1 shows the formula for computation of the baud rate for different USART modes which only apply in Master mode internal clock Given the desired baud rate and Fosc the nearest integer value for the SPBRG register can be calculated using the formula in Table 17 1 From this the error in baud rate can be determined EXAMPLE 17 1 Example 17 1 shows the calculation of the baud rate error for the following conditions Fosc 16 MHz Desired Baud Rate 9600 BRGH 0 SYNC 0 It may be advantageous to use the high baud rate BRGH 1 even for slower baud clocks This is because the Fosc 16 X 1 equation can reduce the baud rate error in some cases Writing a new value to the SPBRG register causes the BRG timer to be reset or cleared This ensures the BRG does not wait for a timer overflow before o
19. ee One bit of PORTD Set Interrupt Flag e PSPIF 1 lt 7 gt eed NUA BE Chip Select Write 223 Note I O pin has protection diodes to VDD Vss Q4 FIGURE 9 11 PARALLEL SLAVE PORT WRITE WAVEFORMS 1 2 a4 at 02 03 a zy WR i RD PORTD lt 7 0 gt PSPIE DS30485A page 96 Preliminary 2002 Microchip Technology Inc PIC18FXX39 FIGURE 9 12 PARALLEL SLAVE PORT READ WAVEFORMS 1 02 03 Q4 1 a2 PSPIF TABLE 9 11 REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR All Other RESETS PORTD Port Data Latch when written Port pins when read XXXX XXXX uuuu uuuu LATD LATD Data Output bits XXXX XXXX uuuu uuuu TRISD PORTD Data Direction bits TITLE TLITI GT TILIL PORTE RE2 RE1 REO 000 000 LATE LATE Data Output bits XXX uuu TRISE IBF OBF IBOV PSPMODE PORTE Data Direction bits 0000 111 0000 111 INTCON GIE PEIE TMROIF INTOIE RBIE TMROIF INTOIF RBIF 0000 000x 0000 000u G
20. 45 gt l a 46 gt lt 47 48 TMRO or TMR1 5 Note Refer to Figure 23 4 for load conditions TABLE 23 8 TIMERO AND TIMER1 EXTERNAL CLOCK REQUIREMENTS ifs Symbol Characteristic Min Max Units Conditions 40 TtOH TOCKI High Pulse Width No Prescaler 0 5Tcv 20 ns With Prescaler 10 ns 41 TtOL TOCKI Low Pulse Width No Prescaler 0 5Tcv 20 ns With Prescaler 10 ns 42 TtOP TOCKI Period No Prescaler Tcv 10 ns With Prescaler Greater of ns N prescale 20 ns or Tcv 40 value N 1 2 4 256 45 Tt1H T13CKI High Synchronous no prescaler 0 5 20 ns Time Synchronous 10 ns with prescaler PIC18LFXXXX 25 ns Asynchronous PIC18FXXXX 30 ns PIC18LFXXXX 50 ns 46 Tt1L T13CKI Low Synchronous no prescaler 0 5 5 ns Time Synchronous 10 ns with prescaler picC48L 25 ns Asynchronous PIC18FXXXX 30 ns PIC18LFXXXX 50 ns 47 TtiP T13CKI input Synchronous Greater of ns prescale period 20 ns or Tcv 40 value N 1 2 4 8 Asynchronous 60 ns Ft1 T13CKI oscillator input frequency range DC 50 kHz 48 Tcke2tmrl Delay from external T13CKI clock edge to timer 2 Tosc 7 Tosc increment 2002 Microchip Technology Inc Preliminary DS30485A page 273 PIC18FXX39 FIGURE 23 10 PWM TIMINGS PWM1 AND 2 PWMxOutput 7
21. Example MOVFF Before Instruction REG1 REG2 After Instruction REG1 REG2 DS30485A page 236 REG2 0x33 0x11 0x33 0x33 MOVLB Move literal to low nibble in BSR Syntax label MOVLB k Operands 0 lt k lt 255 Operation k gt BSR Status Affected None Encoding 0000 0001 kkkk kkkk Description The 8 bit literal is loaded into the Bank Select Register BSR Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal Process Write k Data literal k to BSR Example MOVLB 5 Before Instruction BSR register 0x02 After Instruction BSR register Preliminary 0x05 2002 Microchip Technology Inc PIC18FXX39 MOVLW Move literal to W Syntax label MOVLW Operands 0 lt k lt 255 Operation k gt W Status Affected None Encoding 0000 1110 kkkk kkkk Description The eight bit literal k is loaded into W Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to W literal k Data Example MOVLW 5 After Instruction 0x5A MOVWF Move W to f Syntax label MOVWF f a Operands 0 lt 1 lt 255 a e 0 1 Operation 5f Status Affected None Encoding 0110 111a ffff FEFE Description Move data from W to register f Location f can be anywhere in the 256 byte bank I
22. V 2002 Microchip Technology Inc Preliminary DS30485A page 295 PIC18FXX39 FIGURE 24 19 AID NON LINEARITY vs VREFH VDD VREFH 40 C TO 125 C FIGURE 24 20 A D NON LINEARITY vs VREFH VDD 5V 40 C TO 125 C DS30485A page 296 Preliminary 2002 Microchip Technology Inc PIC18FXX39 25 0 PACKAGING INFORMATION 25 1 Package Marking Information 28 Lead PDIP Skinny DIP Example PIC18F2439 I SP D QS YYWWNNN 0217017 28 Lead SOIC Example XXXXXXXXXXXXXXXXX PIC18F2439 E SO XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX O RS YYWWNNN O 0210017 Legend XX X Customer specific information Y Year code last digit of calendar year YY Year code last 2 digits of calendar year WW Week code week of January 1 is week 401 NNN Alphanumeric traceability code Note In the event the full Microchip part number cannot be marked on one line it will be carried over to the next line thus limiting the number of available characters for customer specific information Standard PlCmicro device marking consists of Microchip part number year code week code and traceability code For PlCmicro device marking beyond this certain price adders apply Please check with your Microchip Sales Office For QTP devices any special marking adders are included in
23. VoL V lot 2002 Microchip Technology Inc Preliminary DS30485A page 293 PIC18FXX39 FIGURE 24 15 TYPICAL AND MAXIMUM VOL vs IOL VDD 40 C TO 125 C 2 5 Typical statistical mean 25 C Maximum mean 40 C to 125 C Minimum mean 3 40 C to 125 C VoL V lo mA FIGURE 24 16 MINIMUM AND MAXIMUM vs VDD ST INPUT 40 C TO 125 C 4 0 Typical statistical mean 25 C Maximum mean 3 40 C to 125 C Minimum mean 3 40 C to 125 C VIH Max VIN V V DS30485A page 294 Preliminary 2002 Microchip Technology Inc PIC18FXX39 FIGURE 24 17 MINIMUM AND MAXIMUM VIN vs TTL INPUT 40 C TO 125 C 1 6 Typical statistical mean 25 C 14 Maximum mean 3c 40 C to 125 C Minimum mean 3 40 C to 125 C VTH Max Min 0 8 V 0 6 0 4 0 2 0 0 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 V FIGURE 24 18 MINIMUM AND MAXIMUM VIN vs I2C INPUT 40 C TO 125 C 38 Typical statistical mean 25 C Maximum mean 40 C to 125 C Minimum mean 3 40 C to 125 C ViLMax V
24. 8 n mRBolNro osctuciki 9 OQ OSC2 CLKO RAG 4 10 6 19 1 lt 58 RCO T13CKI lt 11 18 1 lt RC7 RXIDT PWM2 112 171 RC6 TX CK PWM1 13 16 1 RC5 SDO RC3 SCK SCL 14 15 1 RC4 SDUSDA 2002 Microchip Technology Inc Preliminary DS30485A page 3 PIC18FXX39 Table of Contents 1 0 2 0 3 0 40 eredi eene rei e ed d En dinh oe ER ke e Tee 33 5 0 FLASH Program Memory 6 0 Data EEPROM Memory 7 0 8X8Hardware Multiplier du 8 0 tec E 9 02 POTIS 10 0 TimerO Module 11 0 Timer1 Module 12 0 Timer2 Module 13 0 Timer3 Module 14 0 Single Phase Induction Motor Control inna 113 15 0 Pulse Width Modulation PWM Modules 16 0 Master Synchronous Serial Port MSSP Module ssssssssssssseseseeeeeeeeenenen nennen 125 17 0 Addressable Universal Synchronous Asynchronous Receiver Transmitter 05 165 18 0 Compatible 10 bit Analog to Digital Converter A D 181 49 0 Moltage Delect s 20 0 Special Features of the CPU 24 0 Instr ction Set Summary aos
25. Baud Rate Generator Register 0000 0000 0000 0000 Legend x unknown unimplemented read as 0 Shaded cells are not used for Synchronous Master Reception Note 1 The PSPIF PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices always maintain these bits clear FIGURE 17 8 SYNCHRONOUS RECEPTION MASTER MODE SREN 6 a2lasfaqlar azjaslas ar aalas oslar arlasjas RC7 RX DT DX bit X bitt XK Its bit5 XK bite RC6 TX CK pin Write to bit SREN SRENbit CREN bit 0 RCIF bit Interrupt Read RXREG Note Timing diagram demonstrates Sync Master mode with bit SREN 1 and bit BRGH 0 DS30485A page 178 Preliminary 2002 Microchip Technology Inc 17 4 USART Synchronous Slave Mode Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6 TX CK pin instead of being supplied internally PIC18FXX39 To set up a Synchronous Slave Transmission 1 Enable the synchronous slave serial port by set ting bits SYNC and SPEN and clearing bit CSRC in Master mode This allows the device to transfer or 2 Clear bits CREN and SREN rece
26. esae n e 235 Lookup Tables GOTO ue ette 38 Table Reads Table Writes 38 Low Voltage Detect 189 Characteristics 266 Effects of a RESET ete ees 193 Operation nire en efe repe 192 Current Consumption 193 During SLEEP 193 Reference Voltage Set Point 193 Typical Application 189 LVD See Low Voltage Detect 189 M Master SSP MSSP Module OVerVIeW ates tr aet o tyre eas 125 Master Synchronous Serial Port MSSP See MSSP Master Synchronous Serial Port See MSSP Memory Organization Data 39 Program Memory Memory Programming Requirements 267 Migration from High End to Enhanced Devices 307 Motor ace cereos 113 121 Methods 117 120 Defined Parameters 121 Software Interface 4 2222 1 114 Theory of Operation 113 VIF Curve 114 MPLAB C17 and MPLAB C18 C Compilers MPLAB ICD In Circuit Debugger MPLAB ICE High Performance Universal In Circuit Emulator with MPLAB IDE 254 MPLAB Integrated Development Environment Software 2 01 253 MPLINK Object Linker MPLIB Object Librarian
27. ooe d E sey qavass seu Qavdss erepdn S 99010 play SI 49019 Sojeuiuuo Jasen sng DS30485A page 143 iminary Prel 2002 Microchip Technology Inc PIC18FXX39 16 4 4 CLOCK STRETCHING Both 7 and 10 bit Slave modes implement automatic clock stretching during a transmit sequence The SEN bit SSPCON2 lt 0 gt allows clock stretching to be enabled during receives Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence 16 4 4 1 Clock Stretching for 7 bit Slave Receive Mode SEN 1 In 7 bit Slave Receive mode on the falling edge of the ninth clock at the end of the ACK sequence if the BF bit is set the bit in the SSPCON 1 register is auto matically cleared forcing the SCL output to be held low The being cleared to 0 will assert the SCL line low The CKP bit must be set in the user s ISR before reception is allowed to continue By holding the SCL line low the user has time to service the ISR and read the contents of the SSPBUF before the master device can initiate another receive sequence This will prevent buffer overruns from occurring see Figure 16 13 16 4 4 3 Clock Stretching for 7 bit Slave Transmit Mode 7 bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock if
28. ype PORTE is a bi directional I O port REO RD AN5 8 25 25 W O REO ST Digital I O RD TTL Read control for parallel slave port see also WR and CS pins AN5 Analog Analog input 5 RE1 WR AN6 9 26 26 40 RET ST Digital I O WR TTL Write control for parallel slave port see CS and RD pins AN6 Analog Analog input 6 RE2 CS AN7 10 27 27 10 2 ST Digital I O CS TTL Chip Select control for parallel slave port see related RD and WR AN7 Analog Analog input 7 Vss 12 311 6 31 6 29 Ground reference for logic and pins VDD 11 32 1 7 28 7 28 P Positive supply for logic and I O pins 29 AVSS 30 P Ground reference for analog modules AVDD 8 P Positive supply for analog modules NC 13 12 13 These pins should be left unconnected 33 34 Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input O Output P Power OD Open Drain no P diode to VDD DS30485A page 18 Preliminary 2002 Microchip Technology Inc PIC18FXX39 2 0 OSCILLATOR CONFIGURATIONS 2 1 Oscillator Types The PIC18FXX39 can be operated in four different Oscillator modes at a frequency of 20 MHz The user can program three configuration bits FOSC2 FOSC1 and FOSCO to select one of these four modes 1 HS High Speed Crystal Resonator 2 HS PLL Speed Crystal Resonator with PLL enabled using 5 M
29. 2002 Microchip Technology Inc PIC18FXX39 TABLE 1 3 PIC18F4X39 PINOUT I O DESCRIPTIONS CONTINUED Pin Number Pin Name d m Description DIP QFN TQFP ype PORTD is a bi directional I O port or a Parallel Slave Port PSP for interfacing to a microprocessor port These pins have TTL input buffers when PSP module is enabled RDO PSPO 19 38 38 RDO ST Digital I O PSPO TTL Parallel Slave Port Data RD1 PSP1 20 39 39 RD1 ST Digital 1 PSP1 TTL Parallel Slave Port Data RD2 PSP2 21 40 40 RD2 ST Digital I O PSP2 TTL Parallel Slave Port Data RD3 PSP3 22 41 41 RD3 ST Digital I O PSP3 TTL Parallel Slave Port Data RD4 PSP4 27 2 2 RD4 ST Digital I O PSP4 TTL Parallel Slave Port Data RD5 PSP5 28 3 3 RD5 ST Digital I O PSP5 TTL Parallel Slave Port Data RD6 PSP6 29 4 4 RD6 ST Digital I O PSP6 TTL Parallel Slave Port Data RD7 PSP7 30 5 5 RD7 ST Digital I O PSP7 TTL Parallel Slave Port Data Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input O Output P Power OD Open Drain no P diode to VDD 2002 Microchip Technology Inc Preliminary DS30485A page 17 PIC18FXX39 TABLE 1 3 PIC18F4X39 PINOUT I O DESCRIPTIONS CONTINUED Pin Number A Pin Name EA pel Description DIP QFN TQFP
30. 2002 Microchip Technology Inc Preliminary DS30485A page 213 PIC18FXX39 TABLE 21 2 PIC18FXXX INSTRUCTION SET Mnemonic 16 Bit Instruction Word Status Description Cycles Notes Operands MSb LSb Affected BYTE ORIENTED FILE REGISTER OPERATIONS ADDWF f d a Add WREG and f 1 0010 O1da0 ffff ffff 2 1 2 ADDWFC f d a Add WREG and Carry bit to f 1 0010 0da ffff ffff C DC Z OV N 1 2 ANDWF f d a AND WREG with f 1 0001 0144 ffff ffff ZN 1 2 CLRF fa Clear f 1 0110 101a Z 2 f a Complement f 1 0001 lida ffff ffff 2 1 2 CPFSEQ fa Compare f with WREG skip 1 20r3 0110 ffff _ 4 CPFSGT fa Compare f with WREG skip gt 1 20 3 0110 010a ffff ffff 4 CPFSLT fa Compare f with WREG skip 1 20 3 110 000a ffff 1 2 DECF f d Decrement f 1 0000 0144 ffff ffff C DC Z OV N 1 2 3 4 DECFSZ f d a Decrement f Skip if O 1 2 0 3 0010 1144 ffff None 1 2 3 4 DCFSNZ f d a Decrement f Skip if Not O 1 20r3 0100 1144 ffff 1 2 INCF f a Increment f 1 0010 1044 ffff C DC Z OV N 1 2 3 4 INCFSZ f d a Increment f Skip if O 1 2 0 3 0011 lida ffff None 4 INFSNZ f a Increment f Skip if Not 0 1 20r3 0100 1044 ffff None 1 2 IORWF f a Inclusive OR WREG with f 1 0001 ffff ffff ZN 1 2 MO
31. A Next Q4 cycle SSPSR to i i i 1 i i after Q24 SSPBUF SDO FIGURE 16 6 SPI MODE WAVEFORM SLAVE MODE WITH 1 Not Optional SCK 0 CKE f SCK 1 CKE 1 Write to SSPBUF 1 bit7 bito x bid X x bit2 y bit NC em a hae 225 l